2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
19 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
20 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include "nv_include.h"
28 /* FIXME: put these somewhere */
29 #define CRTC_INDEX_COLOR VGA_IOBASE_COLOR + VGA_CRTC_INDEX_OFFSET
30 #define NV_VGA_CRTCX_OWNER_HEADA 0x0
31 #define NV_VGA_CRTCX_OWNER_HEADB 0x3
32 #define NV_PBUS_PCI_NV_19 0x0000184C
33 #define NV_PBUS_PCI_NV_20 0x00001850
34 #define NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED 0x00000000
35 #define NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED 0x00000001
36 #define NV_PRAMIN_ROM_OFFSET 0x00700000
44 static int crtchead = 0;
51 static uint16_t le16_to_cpu(const uint16_t x)
53 #if X_BYTE_ORDER == X_BIG_ENDIAN
60 static uint32_t le32_to_cpu(const uint32_t x)
62 #if X_BYTE_ORDER == X_BIG_ENDIAN
69 static Bool nv_cksum(const uint8_t *data, unsigned int length)
71 /* there's a few checksums in the BIOS, so here's a generic checking function */
75 for (i = 0; i < length; i++)
84 static int NVValidVBIOS(ScrnInfoPtr pScrn, const uint8_t *data)
86 /* check for BIOS signature */
87 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
88 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
89 "... BIOS signature not found\n");
93 if (nv_cksum(data, data[2] * 512)) {
94 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
95 "... BIOS checksum invalid\n");
96 /* probably ought to set a do_not_execute flag for table parsing here,
97 * assuming most BIOSen are valid */
100 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "... appears to be valid\n");
105 static void NVShadowVBIOS_PROM(ScrnInfoPtr pScrn, uint8_t *data)
107 NVPtr pNv = NVPTR(pScrn);
110 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
111 "Attempting to locate BIOS image in PROM\n");
113 /* enable ROM access */
114 nvWriteMC(pNv, NV_PBUS_PCI_NV_20, NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED);
115 for (i = 0; i < NV_PROM_SIZE; i++) {
116 /* according to nvclock, we need that to work around a 6600GT/6800LE bug */
117 data[i] = pNv->PROM[i];
118 data[i] = pNv->PROM[i];
119 data[i] = pNv->PROM[i];
120 data[i] = pNv->PROM[i];
121 data[i] = pNv->PROM[i];
123 /* disable ROM access */
124 nvWriteMC(pNv, NV_PBUS_PCI_NV_20, NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
127 static void NVShadowVBIOS_PRAMIN(ScrnInfoPtr pScrn, uint32_t *data)
129 NVPtr pNv = NVPTR(pScrn);
130 const uint32_t *pramin = (uint32_t *)&pNv->REGS[NV_PRAMIN_ROM_OFFSET/4];
131 uint32_t old_bar0_pramin = 0;
133 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
134 "Attempting to locate BIOS image in PRAMIN\n");
136 if (pNv->Architecture >= NV_ARCH_50) {
139 vbios_vram = (pNv->REGS[0x619f04/4] & ~0xff) << 8;
141 vbios_vram = pNv->REGS[0x1700/4] << 16;
142 vbios_vram += 0xf0000;
145 old_bar0_pramin = pNv->REGS[0x1700/4];
146 pNv->REGS[0x1700/4] = vbios_vram >> 16;
149 memcpy(data, pramin, NV_PROM_SIZE);
151 if (pNv->Architecture >= NV_ARCH_50) {
152 pNv->REGS[0x1700/4] = old_bar0_pramin;
156 static Bool NVShadowVBIOS(ScrnInfoPtr pScrn, uint8_t *data)
158 NVShadowVBIOS_PROM(pScrn, data);
159 if (NVValidVBIOS(pScrn, data) == 2)
162 NVShadowVBIOS_PRAMIN(pScrn, (uint32_t *)data);
163 if (NVValidVBIOS(pScrn, data))
174 int length_multiplier;
175 Bool (*handler)(ScrnInfoPtr pScrn, bios_t *, uint16_t, init_exec_t *);
184 static void parse_init_table(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset, init_exec_t *iexec);
186 #define MACRO_INDEX_SIZE 2
188 #define CONDITION_SIZE 12
189 #define IO_FLAG_CONDITION_SIZE 9
197 static int nv_valid_reg(uint32_t reg)
199 #define WITHIN(x,y,z) ((x>=y)&&(x<y+z))
200 if (WITHIN(reg,NV_PRAMIN_OFFSET,NV_PRAMIN_SIZE))
202 if (WITHIN(reg,NV_PCRTC0_OFFSET,NV_PCRTC0_SIZE))
204 if (WITHIN(reg,NV_PRAMDAC0_OFFSET,NV_PRAMDAC0_SIZE))
206 if (WITHIN(reg,NV_PFB_OFFSET,NV_PFB_SIZE))
208 if (WITHIN(reg,NV_PFIFO_OFFSET,NV_PFIFO_SIZE))
210 if (WITHIN(reg,NV_PGRAPH_OFFSET,NV_PGRAPH_SIZE))
212 if (WITHIN(reg,NV_PEXTDEV_OFFSET,NV_PEXTDEV_SIZE))
214 if (WITHIN(reg,NV_PTIMER_OFFSET,NV_PTIMER_SIZE))
216 if (WITHIN(reg,NV_PVIDEO_OFFSET,NV_PVIDEO_SIZE))
218 if (WITHIN(reg,NV_PMC_OFFSET,NV_PMC_SIZE))
220 if (WITHIN(reg,NV_FIFO_OFFSET,NV_FIFO_SIZE))
222 if (WITHIN(reg,NV_PCIO0_OFFSET,NV_PCIO0_SIZE))
224 if (WITHIN(reg,NV_PDIO0_OFFSET,NV_PDIO0_SIZE))
226 if (WITHIN(reg,NV_PVIO_OFFSET,NV_PVIO_SIZE))
228 if (WITHIN(reg,NV_PROM_OFFSET,NV_PROM_SIZE))
230 if (WITHIN(reg,NV_PRAMIN_ROM_OFFSET,NV_PROM_SIZE))
233 if (WITHIN(reg,0x88000,0x1000))
239 static void nv32_rd(ScrnInfoPtr pScrn, uint32_t reg, uint32_t *data)
241 NVPtr pNv = NVPTR(pScrn);
243 if (!nv_valid_reg(reg)) {
244 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
245 "========= unknown reg 0x%08X ==========\n", reg);
248 *data = pNv->REGS[reg/4];
250 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
251 " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, *data);
254 static int nv32_wr(ScrnInfoPtr pScrn, uint32_t reg, uint32_t data)
256 NVPtr pNv = NVPTR(pScrn);
258 uint8_t saved1 = 0, saved2 = 0;
259 volatile uint8_t *crtcptr = crtchead ? pNv->PCIO1 : pNv->PCIO0;
261 if (DEBUGLEVEL >= 8) {
263 nv32_rd(pScrn, reg, &tmp);
266 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
267 " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
268 if (!nv_valid_reg(reg)) {
269 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
270 "========= unknown reg 0x%08X ==========\n", reg);
274 if (pNv->VBIOS.execute) {
277 if ((reg & 0xffc) == 0x3c0) {
279 saved1 = VGA_RD08(crtcptr, VGA_MISC_OUT_R);
280 saved2 = VGA_RD08(crtcptr, VGA_ENABLE);
282 if ((reg & 0xffc) == 0x3cc) {
284 saved1 = VGA_RD08(crtcptr, VGA_GRAPH_INDEX);
285 VGA_WR08(crtcptr, VGA_GRAPH_INDEX, 0x06);
286 saved2 = VGA_RD08(crtcptr, VGA_GRAPH_DATA);
289 pNv->REGS[reg/4] = data;
291 if (specialcase == 1) {
292 VGA_WR08(crtcptr, VGA_ENABLE, saved2);
293 VGA_WR08(crtcptr, VGA_MISC_OUT_W, saved1);
295 if (specialcase == 2) {
296 VGA_WR08(crtcptr, VGA_GRAPH_INDEX, 0x06);
297 VGA_WR08(crtcptr, VGA_GRAPH_DATA, saved2);
298 VGA_WR08(crtcptr, VGA_GRAPH_INDEX, saved1);
305 static void nv_idx_port_rd(ScrnInfoPtr pScrn, uint16_t port, uint8_t index, uint8_t *data)
307 NVPtr pNv = NVPTR(pScrn);
308 volatile uint8_t *ptr = crtchead ? pNv->PCIO1 : pNv->PCIO0;
310 VGA_WR08(ptr, port, index);
311 *data = VGA_RD08(ptr, port + 1);
314 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
315 " Indexed read: Port: 0x%04X, Index: 0x%02X, Head: 0x%02X, Data: 0x%02X\n",
316 port, index, crtchead, *data);
319 static void nv_idx_port_wr(ScrnInfoPtr pScrn, uint16_t port, uint8_t index, uint8_t data)
321 NVPtr pNv = NVPTR(pScrn);
322 volatile uint8_t *ptr;
324 /* The current head is maintained in a file scope variable crtchead.
325 * We trap changes to CRTCX_OWNER and update the head variable
326 * and hence the register set written.
327 * As CRTCX_OWNER only exists on CRTC0, we update crtchead to head0
328 * in advance of the write, and to head1 after the write
330 if (port == CRTC_INDEX_COLOR && index == NV_VGA_CRTCX_OWNER && data != NV_VGA_CRTCX_OWNER_HEADB)
332 ptr = crtchead ? pNv->PCIO1 : pNv->PCIO0;
334 if (DEBUGLEVEL >= 8) {
336 nv_idx_port_rd(pScrn, port, index, &tmp);
339 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
340 " Indexed write: Port: 0x%04X, Index: 0x%02X, Head: 0x%02X, Data: 0x%02X\n",
341 port, index, crtchead, data);
343 if (pNv->VBIOS.execute) {
345 VGA_WR08(ptr, port, index);
346 VGA_WR08(ptr, port + 1, data);
349 if (port == CRTC_INDEX_COLOR && index == NV_VGA_CRTCX_OWNER && data == NV_VGA_CRTCX_OWNER_HEADB)
353 static Bool io_flag_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, uint8_t cond)
355 /* The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
356 * for the CRTC index; 1 byte for the mask to apply to the value
357 * retrieved from the CRTC; 1 byte for the shift right to apply to the
358 * masked CRTC value; 2 bytes for the offset to the flag array, to
359 * which the shifted value is added; 1 byte for the mask applied to the
360 * value read from the flag array; and 1 byte for the value to compare
361 * against the masked byte from the flag table.
364 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
365 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[condptr])));
366 uint8_t crtcindex = bios->data[condptr + 2];
367 uint8_t mask = bios->data[condptr + 3];
368 uint8_t shift = bios->data[condptr + 4];
369 uint16_t flagarray = le16_to_cpu(*((uint16_t *)(&bios->data[condptr + 5])));
370 uint8_t flagarraymask = bios->data[condptr + 7];
371 uint8_t cmpval = bios->data[condptr + 8];
375 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
376 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, Cmpval: 0x%02X\n",
377 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
379 nv_idx_port_rd(pScrn, crtcport, crtcindex, &data);
381 data = bios->data[flagarray + ((data & mask) >> shift)];
382 data &= flagarraymask;
385 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
386 "0x%04X: Checking if 0x%02X equals 0x%02X\n",
387 offset, data, cmpval);
395 static Bool init_prog(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
397 /* INIT_PROG opcode: 0x31
399 * offset (8 bit): opcode
400 * offset + 1 (32 bit): reg
401 * offset + 5 (32 bit): and mask
402 * offset + 9 (8 bit): shift right
403 * offset + 10 (8 bit): number of configurations
404 * offset + 11 (32 bit): register
405 * offset + 15 (32 bit): configuration 1
408 * Starting at offset + 15 there are "number of configurations"
409 * 32 bit values. To find out which configuration value to use
410 * read "CRTC reg" on the CRTC controller with index "CRTC index"
411 * and bitwise AND this value with "and mask" and then bit shift the
412 * result "shift right" bits to the right.
413 * Assign "register" with appropriate configuration value.
416 CARD32 reg = *((CARD32 *) (&bios->data[offset + 1]));
417 CARD32 and = *((CARD32 *) (&bios->data[offset + 5]));
418 CARD8 shiftr = *((CARD8 *) (&bios->data[offset + 9]));
419 CARD8 nr = *((CARD8 *) (&bios->data[offset + 10]));
420 CARD32 reg2 = *((CARD32 *) (&bios->data[offset + 11]));
422 CARD32 configval, tmp;
424 if (iexec->execute) {
425 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: REG: 0x%04X\n", offset,
428 nv32_rd(pScrn, reg, &tmp);
429 configuration = (tmp & and) >> shiftr;
431 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONFIGURATION TO USE: 0x%02X\n",
432 offset, configuration);
434 if (configuration <= nr) {
437 *((CARD32 *) (&bios->data[offset + 15 + configuration * 4]));
439 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: REG: 0x%08X, VALUE: 0x%08X\n", offset,
442 nv32_rd(pScrn, reg2, &tmp);
443 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CURRENT VALUE IS: 0x%08X\n",
445 nv32_wr(pScrn, reg2, configval);
451 static Bool init_io_restrict_prog(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
453 /* INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
455 * offset (8 bit): opcode
456 * offset + 1 (16 bit): CRTC port
457 * offset + 3 (8 bit): CRTC index
458 * offset + 4 (8 bit): mask
459 * offset + 5 (8 bit): shift
460 * offset + 6 (8 bit): count
461 * offset + 7 (32 bit): register
462 * offset + 11 (32 bit): configuration 1
465 * Starting at offset + 11 there are "count" 32 bit values.
466 * To find out which value to use read index "CRTC index" on "CRTC port",
467 * AND this value with "mask" and then bit shift right "shift" bits.
468 * Read the appropriate value using this index and write to "register"
471 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
472 uint8_t crtcindex = bios->data[offset + 3];
473 uint8_t mask = bios->data[offset + 4];
474 uint8_t shift = bios->data[offset + 5];
475 uint8_t count = bios->data[offset + 6];
476 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7])));
484 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
485 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
486 offset, crtcport, crtcindex, mask, shift, count, reg);
488 nv_idx_port_rd(pScrn, crtcport, crtcindex, &config);
489 config = (config & mask) >> shift;
490 if (config > count) {
491 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
492 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
493 offset, config, count);
497 configval = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 11 + config * 4])));
500 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
501 "0x%04X: Writing config %02X\n", offset, config);
503 nv32_wr(pScrn, reg, configval);
508 static Bool init_repeat(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
510 /* INIT_REPEAT opcode: 0x33 ('3')
512 * offset (8 bit): opcode
513 * offset + 1 (8 bit): count
515 * Execute script following this opcode up to INIT_REPEAT_END
519 uint8_t count = bios->data[offset + 1];
522 /* no iexec->execute check by design */
524 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
525 "0x%04X: REPEATING FOLLOWING SEGMENT %d TIMES.\n",
528 iexec->repeat = TRUE;
530 /* count - 1, as the script block will execute once when we leave this
531 * opcode -- this is compatible with bios behaviour as:
532 * a) the block is always executed at least once, even if count == 0
533 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
536 for (i = 0; i < count - 1; i++)
537 parse_init_table(pScrn, bios, offset + 2, iexec);
539 iexec->repeat = FALSE;
544 static Bool init_io_restrict_pll(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
546 /* INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
548 * offset (8 bit): opcode
549 * offset + 1 (16 bit): CRTC port
550 * offset + 3 (8 bit): CRTC index
551 * offset + 4 (8 bit): mask
552 * offset + 5 (8 bit): shift
553 * offset + 6 (8 bit): IO flag condition index
554 * offset + 7 (8 bit): count
555 * offset + 8 (32 bit): register
556 * offset + 12 (16 bit): frequency 1
559 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
560 * Set PLL register "register" to coefficients for frequency n,
561 * selected by reading index "CRTC index" of "CRTC port" ANDed with
562 * "mask" and shifted right by "shift". If "IO flag condition index" > 0,
563 * and condition met, double frequency before setting it.
566 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
567 uint8_t crtcindex = bios->data[offset + 3];
568 uint8_t mask = bios->data[offset + 4];
569 uint8_t shift = bios->data[offset + 5];
570 int8_t io_flag_condition_idx = bios->data[offset + 6];
571 uint8_t count = bios->data[offset + 7];
572 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 8])));
580 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
581 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, IO Flag Condition: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
582 offset, crtcport, crtcindex, mask, shift, io_flag_condition_idx, count, reg);
584 nv_idx_port_rd(pScrn, crtcport, crtcindex, &config);
585 config = (config & mask) >> shift;
586 if (config > count) {
587 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
588 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
589 offset, config, count);
593 freq = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 12 + config * 2])));
595 if (io_flag_condition_idx > 0) {
596 if (io_flag_condition(pScrn, bios, offset, io_flag_condition_idx)) {
597 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
598 "0x%04X: CONDITION FULFILLED - FREQ DOUBLED\n", offset);
601 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
602 "0x%04X: CONDITION IS NOT FULFILLED. FREQ UNCHANGED\n", offset);
606 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
607 "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
608 offset, reg, config, freq);
610 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: [ NOT YET IMPLEMENTED ]\n", offset);
615 configval = 0x01014E07;
618 configval = 0x13030E02;
625 static Bool init_end_repeat(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
627 /* INIT_END_REPEAT opcode: 0x36 ('6')
629 * offset (8 bit): opcode
631 * Marks the end of the block for INIT_REPEAT to repeat
634 /* no iexec->execute check by design */
636 /* iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
637 * we're not in repeat mode
645 static Bool init_copy(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
647 /* INIT_COPY opcode: 0x37 ('7')
649 * offset (8 bit): opcode
650 * offset + 1 (32 bit): register
651 * offset + 5 (8 bit): shift
652 * offset + 6 (8 bit): srcmask
653 * offset + 7 (16 bit): CRTC port
654 * offset + 9 (8 bit): CRTC index
655 * offset + 10 (8 bit): mask
657 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
658 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC port
661 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
662 uint8_t shift = bios->data[offset + 5];
663 uint8_t srcmask = bios->data[offset + 6];
664 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 7])));
665 uint8_t crtcindex = bios->data[offset + 9];
666 uint8_t mask = bios->data[offset + 10];
674 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
675 "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
676 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
678 nv32_rd(pScrn, reg, &data);
683 data <<= (0x100 - shift);
687 nv_idx_port_rd(pScrn, crtcport, crtcindex, &crtcdata);
688 crtcdata = (crtcdata & mask) | (uint8_t)data;
689 nv_idx_port_wr(pScrn, crtcport, crtcindex, crtcdata);
694 static Bool init_not(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
696 /* INIT_NOT opcode: 0x38 ('8')
698 * offset (8 bit): opcode
700 * Invert the current execute / no-execute condition (i.e. "else")
703 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
704 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
706 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
707 "0x%04X: ------ EXECUTING FOLLOWING COMMANDS ------\n", offset);
709 iexec->execute = !iexec->execute;
713 static Bool init_io_flag_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
715 /* INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
717 * offset (8 bit): opcode
718 * offset + 1 (8 bit): condition number
720 * Check condition "condition number" in the IO flag condition table.
721 * If condition not met skip subsequent opcodes until condition
722 * is inverted (INIT_NOT), or we hit INIT_RESUME
725 uint8_t cond = bios->data[offset + 1];
730 if (io_flag_condition(pScrn, bios, offset, cond))
731 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
732 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n", offset);
734 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
735 "0x%04X: CONDITION IS NOT FULFILLED.\n", offset);
736 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
737 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
738 iexec->execute = FALSE;
744 Bool init_idx_addr_latched(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
746 /* INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
748 * offset (8 bit): opcode
749 * offset + 1 (32 bit): control register
750 * offset + 5 (32 bit): data register
751 * offset + 9 (32 bit): mask
752 * offset + 13 (32 bit): data
753 * offset + 17 (8 bit): count
754 * offset + 18 (8 bit): address 1
755 * offset + 19 (8 bit): data 1
758 * For each of "count" address and data pairs, write "data n" to "data register",
759 * read the current value of "control register", and write it back once ANDed
760 * with "mask", ORed with "data", and ORed with "address n"
763 uint32_t controlreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
764 uint32_t datareg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
765 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
766 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 13])));
767 uint8_t count = bios->data[offset + 17];
775 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
776 "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
777 offset, controlreg, datareg, mask, data, count);
779 for (i = 0; i < count; i++) {
780 uint8_t instaddress = bios->data[offset + 18 + i * 2];
781 uint8_t instdata = bios->data[offset + 19 + i * 2];
784 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
785 "0x%04X: Address: 0x%02X, Data: 0x%02X\n", offset, instaddress, instdata);
787 nv32_wr(pScrn, datareg, instdata);
789 nv32_rd(pScrn, controlreg, &value);
790 value = (value & mask) | data | instaddress;
792 nv32_wr(pScrn, controlreg, value);
798 static Bool init_io_restrict_pll2(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
800 /* INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
802 * offset (8 bit): opcode
803 * offset + 1 (16 bit): CRTC port
804 * offset + 3 (8 bit): CRTC index
805 * offset + 4 (8 bit): mask
806 * offset + 5 (8 bit): shift
807 * offset + 6 (8 bit): count
808 * offset + 7 (32 bit): register
809 * offset + 11 (32 bit): frequency 1
812 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
813 * Set PLL register "register" to coefficients for frequency n,
814 * selected by reading index "CRTC index" of "CRTC port" ANDed with
815 * "mask" and shifted right by "shift".
818 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
819 uint8_t crtcindex = bios->data[offset + 3];
820 uint8_t mask = bios->data[offset + 4];
821 uint8_t shift = bios->data[offset + 5];
822 uint8_t count = bios->data[offset + 6];
823 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7])));
831 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
832 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
833 offset, crtcport, crtcindex, mask, shift, count, reg);
838 nv_idx_port_rd(pScrn, crtcport, crtcindex, &config);
839 config = (config & mask) >> shift;
840 if (config > count) {
841 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
842 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
843 offset, config, count);
847 freq = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 11 + config * 4])));
850 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
851 "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
852 offset, reg, config, freq);
854 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: [ NOT YET IMPLEMENTED ]\n", offset);
859 static Bool init_pll2(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
861 /* INIT_PLL2 opcode: 0x4B ('K')
863 * offset (8 bit): opcode
864 * offset + 1 (32 bit): register
865 * offset + 5 (32 bit): freq
867 * Set PLL register "register" to coefficients for frequency "freq"
870 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
871 uint32_t freq = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
877 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
878 "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
881 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: [ NOT YET IMPLEMENTED ]\n", offset);
886 static uint32_t get_tmds_index_reg(ScrnInfoPtr pScrn, uint8_t mlv)
888 /* For mlv < 0x80, it is an index into a table of TMDS base addresses
889 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by CR58 for CR57 = 0
890 * to index a table of offsets to the basic 0x6808b0 address
891 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by CR58 for CR57 = 0
892 * to index a table of offsets to the basic 0x6808b0 address, and then flip the offset by 8
895 NVPtr pNv = NVPTR(pScrn);
896 int pramdac_offset[13] = {0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000};
897 uint32_t pramdac_table[4] = {0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8};
900 /* here we assume that the DCB table has already been parsed */
903 /* This register needs to be written to set index for reading CR58 */
904 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, 0x57, 0);
905 nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, 0x58, &dcb_entry);
906 if (dcb_entry > pNv->dcb_table.entries) {
907 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
908 "CR58 doesn't have a valid DCB entry currently (%02X)\n", dcb_entry);
911 dacoffset = pramdac_offset[pNv->dcb_table.entry[dcb_entry].or];
914 return (0x6808b0 + dacoffset);
916 if (mlv > (sizeof(pramdac_table) / sizeof(uint32_t))) {
917 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
918 "Magic Lookup Value too big (%02X)\n", mlv);
921 return pramdac_table[mlv];
925 static Bool init_tmds(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
927 /* INIT_TMDS opcode: 0x4F ('O') (non-canon name)
929 * offset (8 bit): opcode
930 * offset + 1 (8 bit): magic lookup value
931 * offset + 2 (8 bit): TMDS address
932 * offset + 3 (8 bit): mask
933 * offset + 4 (8 bit): data
935 * Read the data reg for TMDS address "TMDS address", AND it with mask
936 * and OR it with data, then write it back
937 * "magic lookup value" determines which TMDS base address register is used --
938 * see get_tmds_index_reg()
941 uint8_t mlv = bios->data[offset + 1];
942 uint32_t tmdsaddr = bios->data[offset + 2];
943 uint8_t mask = bios->data[offset + 3];
944 uint8_t data = bios->data[offset + 4];
951 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
952 "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
953 offset, mlv, tmdsaddr, mask, data);
955 reg = get_tmds_index_reg(pScrn, mlv);
957 nv32_wr(pScrn, reg, tmdsaddr | 0x10000);
958 nv32_rd(pScrn, reg + 4, &value);
959 value = (value & mask) | data;
960 nv32_wr(pScrn, reg + 4, value);
961 nv32_wr(pScrn, reg, tmdsaddr);
966 Bool init_zm_tmds_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
968 /* INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
970 * offset (8 bit): opcode
971 * offset + 1 (8 bit): magic lookup value
972 * offset + 2 (8 bit): count
973 * offset + 3 (8 bit): addr 1
974 * offset + 4 (8 bit): data 1
977 * For each of "count" TMDS address and data pairs write "data n" to "addr n"
978 * "magic lookup value" determines which TMDS base address register is used --
979 * see get_tmds_index_reg()
982 uint8_t mlv = bios->data[offset + 1];
983 uint8_t count = bios->data[offset + 2];
991 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
992 "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
995 reg = get_tmds_index_reg(pScrn, mlv);
997 for (i = 0; i < count; i++) {
998 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
999 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1001 nv32_wr(pScrn, reg + 4, tmdsdata);
1002 nv32_wr(pScrn, reg, tmdsaddr);
1008 Bool init_cr_idx_adr_latch(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1010 /* INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1012 * offset (8 bit): opcode
1013 * offset + 1 (8 bit): CRTC index1
1014 * offset + 2 (8 bit): CRTC index2
1015 * offset + 3 (8 bit): baseaddr
1016 * offset + 4 (8 bit): count
1017 * offset + 5 (8 bit): data 1
1020 * For each of "count" address and data pairs, write "baseaddr + n" to
1021 * "CRTC index1" and "data n" to "CRTC index2"
1022 * Once complete, restore initial value read from "CRTC index1"
1024 uint8_t crtcindex1 = bios->data[offset + 1];
1025 uint8_t crtcindex2 = bios->data[offset + 2];
1026 uint8_t baseaddr = bios->data[offset + 3];
1027 uint8_t count = bios->data[offset + 4];
1028 uint8_t oldaddr, data;
1031 if (!iexec->execute)
1034 if (DEBUGLEVEL >= 6)
1035 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1036 "0x%04X: Index1: 0x%02X, Index2: 0x%02X, BaseAddr: 0x%02X, Count: 0x%02X\n",
1037 offset, crtcindex1, crtcindex2, baseaddr, count);
1039 nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, crtcindex1, &oldaddr);
1041 for (i = 0; i < count; i++) {
1042 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex1, baseaddr + i);
1044 data = bios->data[offset + 5 + i];
1045 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex2, data);
1048 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex1, oldaddr);
1053 Bool init_cr(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1055 /* INIT_CR opcode: 0x52 ('R')
1057 * offset (8 bit): opcode
1058 * offset + 1 (8 bit): CRTC index
1059 * offset + 2 (8 bit): mask
1060 * offset + 3 (8 bit): data
1062 * Assign the value of at "CRTC index" ANDed with mask and ORed with data
1063 * back to "CRTC index"
1066 uint8_t crtcindex = bios->data[offset + 1];
1067 uint8_t mask = bios->data[offset + 2];
1068 uint8_t data = bios->data[offset + 3];
1071 if (!iexec->execute)
1074 if (DEBUGLEVEL >= 6)
1075 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1076 "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1077 offset, crtcindex, mask, data);
1079 nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, crtcindex, &value);
1081 value = (value & mask) | data;
1083 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex, value);
1088 static Bool init_zm_cr(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1090 /* INIT_ZM_CR opcode: 0x53 ('S')
1092 * offset (8 bit): opcode
1093 * offset + 1 (8 bit): CRTC index
1094 * offset + 2 (8 bit): value
1096 * Assign "value" to CRTC register with index "CRTC index".
1099 uint8_t crtcindex = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1100 uint8_t data = bios->data[offset + 2];
1102 if (!iexec->execute)
1105 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex, data);
1110 static Bool init_zm_cr_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1112 /* INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1114 * offset (8 bit): opcode
1115 * offset + 1 (8 bit): count
1116 * offset + 2 (8 bit): CRTC index 1
1117 * offset + 3 (8 bit): value 1
1120 * For "count", assign "value n" to CRTC register with index "CRTC index n".
1123 uint8_t count = bios->data[offset + 1];
1126 if (!iexec->execute)
1129 for (i = 0; i < count; i++)
1130 init_zm_cr(pScrn, bios, offset + 2 + 2 * i - 1, iexec);
1135 static Bool init_condition_time(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1137 /* INIT_CONDITION_TIME opcode: 0x56 ('V')
1139 * offset (8 bit): opcode
1140 * offset + 1 (8 bit): condition number
1142 * Check condition "condition number" in the condition table.
1143 * The condition table entry has 4 bytes for the address of the
1144 * register to check, 4 bytes for a mask and 4 for a test value.
1145 * If condition not met sleep for 2ms
1148 // this opcode makes no sense. it seems to do some competely useless things
1149 uint8_t cond = bios->data[offset + 1];
1150 // uint16_t b = bios->data[offset + 2]; // this needs printing
1151 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
1152 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[condptr])));
1153 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 4])));
1154 uint32_t cmpval = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 8])));
1157 if (!iexec->execute)
1160 if (DEBUGLEVEL >= 6)
1161 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1162 "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X, Cmpval: 0x%08X\n",
1163 offset, cond, reg, mask, cmpval);
1166 reg &= 0xfffffffc; // FIXME: this not in init_condition() - should it be?
1168 nv32_rd(pScrn, reg, &data);
1171 if (DEBUGLEVEL >= 6)
1172 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1173 "0x%04X: Checking if 0x%08X equals 0x%08X\n",
1174 offset, data, cmpval);
1176 if (data != cmpval) {
1177 if (DEBUGLEVEL >= 6)
1178 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1179 "0x%04X: Condition not met, sleeping for 2ms\n", offset);
1183 if (DEBUGLEVEL >= 6)
1184 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1185 "0x%04X: Condition met, continuing\n", offset);
1190 static Bool init_zm_reg_sequence(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1192 /* INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1194 * offset (8 bit): opcode
1195 * offset + 1 (32 bit): base register
1196 * offset + 5 (8 bit): count
1197 * offset + 6 (32 bit): value 1
1200 * Starting at offset + 6 there are "count" 32 bit values.
1201 * For "count" iterations set "base register" + 4 * current_iteration
1202 * to "value current_iteration"
1205 uint32_t basereg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1206 uint32_t count = bios->data[offset + 5];
1209 if (!iexec->execute)
1212 if (DEBUGLEVEL >= 6)
1213 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1214 "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1215 offset, basereg, count);
1217 for (i = 0; i < count; i++) {
1218 uint32_t reg = basereg + i * 4;
1219 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 6 + i * 4])));
1221 nv32_wr(pScrn, reg, data);
1227 static Bool init_indirect_reg(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
1229 /* INIT_INDIRECT_REG opcode: 0x5A
1231 * offset (8 bit): opcode
1232 * offset + 1 (32 bit): register
1233 * offset + 5 (16 bit): adress offset (in bios)
1235 * Lookup value at offset data in the bios and write it to reg
1237 CARD32 reg = *((CARD32 *) (&bios->data[offset + 1]));
1238 CARD16 data = le16_to_cpu(*((CARD16 *) (&bios->data[offset + 5])));
1239 CARD32 data2 = bios->data[data];
1241 if (iexec->execute) {
1242 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1243 "0x%04X: REG: 0x%04X, DATA AT: 0x%04X, VALUE IS: 0x%08X\n",
1244 offset, reg, data, data2);
1246 if (DEBUGLEVEL >= 6) {
1248 nv32_rd(pScrn, reg, &tmpval);
1249 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CURRENT VALUE IS: 0x%08X\n", offset, tmpval);
1252 nv32_wr(pScrn, reg, data2);
1257 static Bool init_sub_direct(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1259 /* INIT_SUB_DIRECT opcode: 0x5B ('[')
1261 * offset (8 bit): opcode
1262 * offset + 1 (16 bit): subroutine offset (in bios)
1264 * Calls a subroutine that will execute commands until INIT_DONE
1268 uint16_t sub_offset = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1270 if (!iexec->execute)
1273 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: EXECUTING SUB-ROUTINE AT 0x%04X\n",
1274 offset, sub_offset);
1276 parse_init_table(pScrn, bios, sub_offset, iexec);
1278 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: END OF SUB-ROUTINE AT 0x%04X\n",
1279 offset, sub_offset);
1284 static Bool init_copy_nv_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1286 /* INIT_COPY_NV_REG opcode: 0x5F ('_')
1288 * offset (8 bit): opcode
1289 * offset + 1 (32 bit): src reg
1290 * offset + 5 (8 bit): shift
1291 * offset + 6 (32 bit): src mask
1292 * offset + 10 (32 bit): xor
1293 * offset + 14 (32 bit): dst reg
1294 * offset + 18 (32 bit): dst mask
1296 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
1297 * "src mask", then XOR with "xor". Write this OR'd with
1298 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
1301 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
1302 uint8_t shift = bios->data[offset + 5];
1303 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
1304 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
1305 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
1306 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
1307 uint32_t srcvalue, dstvalue;
1309 if (!iexec->execute)
1312 if (DEBUGLEVEL >= 6)
1313 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1314 "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
1315 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
1317 nv32_rd(pScrn, srcreg, &srcvalue);
1322 srcvalue <<= (0x100 - shift);
1324 srcvalue = (srcvalue & srcmask) ^ xor;
1326 nv32_rd(pScrn, dstreg, &dstvalue);
1327 dstvalue &= dstmask;
1329 nv32_wr(pScrn, dstreg, dstvalue | srcvalue);
1334 static Bool init_zm_index_io(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1336 /* INIT_ZM_INDEX_IO opcode: 0x62 ('b')
1338 * offset (8 bit): opcode
1339 * offset + 1 (16 bit): CRTC port
1340 * offset + 3 (8 bit): CRTC index
1341 * offset + 4 (8 bit): data
1343 * Write "data" to index "CRTC index" of "CRTC port"
1345 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1346 uint8_t crtcindex = bios->data[offset + 3];
1347 uint8_t data = bios->data[offset + 4];
1349 if (!iexec->execute)
1352 nv_idx_port_wr(pScrn, crtcport, crtcindex, data);
1357 static Bool init_compute_mem(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1359 /* INIT_COMPUTE_MEM opcode: 0x63 ('c')
1361 * offset (8 bit): opcode
1366 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: [ NOT YET IMPLEMENTED ]\n", offset);
1368 uint16_t ramcfg = le16_to_cpu(*((uint16_t *)(&bios->data[bios->ram_table_offset])));
1373 if (!iexec->execute)
1376 nv32_rd(pScrn, 0x00101000, &strapinfo);
1377 nv32_rd(pScrn, 0x00100080, &pfb_debug);
1379 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "STRAPINFO: 0x%08X\n", strapinfo);
1380 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "PFB_DEBUG: 0x%08X\n", pfb_debug);
1381 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "RAM CFG: 0x%04X\n", ramcfg);
1383 pfb_debug &= 0xffffffef;
1385 strapinfo &= 0x0000000f;
1386 ramcfg2 = le16_to_cpu(*((uint16_t *)
1387 (&bios->data[bios->ram_table_offset + (2 * strapinfo)])));
1389 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "AFTER MANIPULATION\n");
1390 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "STRAPINFO: 0x%08X\n", strapinfo);
1391 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "PFB_DEBUG: 0x%08X\n", pfb_debug);
1392 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "RAM CFG2: 0x%08X\n", ramcfg2);
1398 nv32_rd(pScrn, 0x00100200, ®1);
1399 nv32_rd(pScrn, 0x0010020C, ®2);
1401 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x00100200: 0x%08X\n", reg1);
1402 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x0010020C: 0x%08X\n", reg2);
1408 static Bool init_reset(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1410 /* INIT_RESET opcode: 0x65 ('e')
1412 * offset (8 bit): opcode
1413 * offset + 1 (32 bit): register
1414 * offset + 5 (32 bit): value1
1415 * offset + 9 (32 bit): value2
1417 * Assign "value1" to "register", then assign "value2" to "register"
1420 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1421 uint32_t value1 = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1422 uint32_t value2 = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
1423 uint32_t pci_nv_19, pci_nv_20;
1425 /* no iexec->execute check by design */
1427 nv32_rd(pScrn, NV_PBUS_PCI_NV_19, &pci_nv_19);
1428 nv32_wr(pScrn, NV_PBUS_PCI_NV_19, 0);
1429 nv32_wr(pScrn, reg, value1);
1433 nv32_wr(pScrn, reg, value2);
1434 nv32_wr(pScrn, NV_PBUS_PCI_NV_19, pci_nv_19);
1436 nv32_rd(pScrn, NV_PBUS_PCI_NV_20, &pci_nv_20);
1437 pci_nv_20 &= !NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
1438 nv32_wr(pScrn, NV_PBUS_PCI_NV_20, pci_nv_20);
1443 static Bool init_index_io8(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
1445 /* INIT_INDEX_IO8 opcode: 0x69
1447 * offset (8 bit): opcode
1448 * offset + 1 (16 bit): CRTC reg
1449 * offset + 3 (8 bit): and mask
1450 * offset + 4 (8 bit): or with
1455 NVPtr pNv = NVPTR(pScrn);
1456 volatile CARD8 *ptr = crtchead ? pNv->PCIO1 : pNv->PCIO0;
1457 CARD16 reg = le16_to_cpu(*((CARD16 *)(&bios->data[offset + 1])));
1458 CARD8 and = *((CARD8 *)(&bios->data[offset + 3]));
1459 CARD8 or = *((CARD8 *)(&bios->data[offset + 4]));
1462 if (iexec->execute) {
1463 data = (VGA_RD08(ptr, reg) & and) | or;
1465 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1466 "0x%04X: CRTC REG: 0x%04X, VALUE: 0x%02X\n",
1468 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CURRENT VALUE IS: 0x%02X\n", offset,
1469 VGA_RD08(ptr, reg));
1471 #ifdef PERFORM_WRITE
1472 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "init_index_io8 crtcreg 0x%X value 0x%X\n",reg,data);
1474 VGA_WR08(ptr, reg, data);
1480 static Bool init_sub(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1482 /* INIT_SUB opcode: 0x6B ('k')
1484 * offset (8 bit): opcode
1485 * offset + 1 (8 bit): script number
1487 * Execute script number "script number", as a subroutine
1490 uint8_t sub = bios->data[offset + 1];
1492 if (!iexec->execute)
1495 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1496 "0x%04X: EXECUTING SUB-SCRIPT %d\n", offset, sub);
1498 parse_init_table(pScrn, bios,
1499 le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + sub * 2]))),
1502 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1503 "0x%04X: END OF SUB-SCRIPT %d\n", offset, sub);
1508 static Bool init_ram_condition(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
1510 /* INIT_RAM_CONDITION opcode: 0x6D
1512 * offset (8 bit): opcode
1513 * offset + 1 (8 bit): and mask
1514 * offset + 2 (8 bit): cmpval
1516 * Test if (NV_PFB_BOOT & and mask) matches cmpval
1518 NVPtr pNv = NVPTR(pScrn);
1519 CARD8 and = *((CARD8 *) (&bios->data[offset + 1]));
1520 CARD8 cmpval = *((CARD8 *) (&bios->data[offset + 2]));
1523 if (iexec->execute) {
1524 data=(pNv->PFB[NV_PFB_BOOT/4])∧
1526 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1527 "0x%04X: CHECKING IF REGVAL: 0x%08X equals COND: 0x%08X\n",
1528 offset, data, cmpval);
1530 if (data == cmpval) {
1531 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1532 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n",
1535 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONDITION IS NOT FULFILLED.\n", offset);
1536 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1537 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
1538 iexec->execute = FALSE;
1544 static Bool init_nv_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1546 /* INIT_NV_REG opcode: 0x6E ('n')
1548 * offset (8 bit): opcode
1549 * offset + 1 (32 bit): register
1550 * offset + 5 (32 bit): mask
1551 * offset + 9 (32 bit): data
1553 * Assign ((REGVAL("register") & "mask") | "data") to "register"
1556 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1557 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1558 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
1561 if (!iexec->execute)
1564 if (DEBUGLEVEL >= 6)
1565 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1566 "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
1567 offset, reg, mask, data);
1569 nv32_rd(pScrn, reg, &value);
1571 value = (value & mask) | data;
1573 nv32_wr(pScrn, reg, value);
1578 static Bool init_macro(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1580 /* INIT_MACRO opcode: 0x6F ('o')
1582 * offset (8 bit): opcode
1583 * offset + 1 (8 bit): macro number
1585 * Look up macro index "macro number" in the macro index table.
1586 * The macro index table entry has 1 byte for the index in the macro table,
1587 * and 1 byte for the number of times to repeat the macro.
1588 * The macro table entry has 4 bytes for the register address and
1589 * 4 bytes for the value to write to that register
1592 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
1593 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
1594 uint8_t macro_tbl_idx = bios->data[tmp];
1595 uint8_t count = bios->data[tmp + 1];
1599 if (!iexec->execute)
1602 if (DEBUGLEVEL >= 6)
1603 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1604 "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, Count: 0x%02X\n",
1605 offset, macro_index_tbl_idx, macro_tbl_idx, count);
1607 for (i = 0; i < count; i++) {
1608 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
1610 reg = le32_to_cpu(*((uint32_t *)(&bios->data[macroentryptr])));
1611 data = le32_to_cpu(*((uint32_t *)(&bios->data[macroentryptr + 4])));
1613 nv32_wr(pScrn, reg, data);
1619 static Bool init_done(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1621 /* INIT_DONE opcode: 0x71 ('q')
1623 * offset (8 bit): opcode
1625 * End the current script
1628 /* mild retval abuse to stop parsing this table */
1632 static Bool init_resume(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1634 /* INIT_RESUME opcode: 0x72 ('r')
1636 * offset (8 bit): opcode
1638 * End the current execute / no-execute condition
1644 iexec->execute = TRUE;;
1645 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1646 "0x%04X: ---- EXECUTING FOLLOWING COMMANDS ----\n", offset);
1651 static Bool init_ram_condition2(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
1653 /* INIT_RAM_CONDITION2 opcode: 0x73
1655 * offset (8 bit): opcode
1656 * offset + 1 (8 bit): and mask
1657 * offset + 2 (8 bit): cmpval
1659 * Test if (NV_EXTDEV_BOOT & and mask) matches cmpval
1661 NVPtr pNv = NVPTR(pScrn);
1662 CARD32 and = *((CARD32 *) (&bios->data[offset + 1]));
1663 CARD32 cmpval = *((CARD32 *) (&bios->data[offset + 5]));
1666 if (iexec->execute) {
1667 data=(nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT))∧
1669 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1670 "0x%04X: CHECKING IF REGVAL: 0x%08X equals COND: 0x%08X\n",
1671 offset, data, cmpval);
1673 if (data == cmpval) {
1674 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1675 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n",
1678 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONDITION IS NOT FULFILLED.\n", offset);
1679 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1680 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
1681 iexec->execute = FALSE;
1687 static Bool init_time(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1689 /* INIT_TIME opcode: 0x74 ('t')
1691 * offset (8 bit): opcode
1692 * offset + 1 (16 bit): time
1694 * Sleep for "time" microseconds.
1697 uint16_t time = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1699 if (!iexec->execute)
1702 if (DEBUGLEVEL >= 6)
1703 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1704 "0x%04X: Sleeping for 0x%04X microseconds.\n", offset, time);
1711 static Bool init_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1713 /* INIT_CONDITION opcode: 0x75 ('u')
1715 * offset (8 bit): opcode
1716 * offset + 1 (8 bit): condition number
1718 * Check condition "condition number" in the condition table.
1719 * The condition table entry has 4 bytes for the address of the
1720 * register to check, 4 bytes for a mask and 4 for a test value.
1721 * If condition not met skip subsequent opcodes until condition
1722 * is inverted (INIT_NOT), or we hit INIT_RESUME
1725 uint8_t cond = bios->data[offset + 1];
1726 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
1727 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[condptr])));
1728 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 4])));
1729 uint32_t cmpval = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 8])));
1732 if (!iexec->execute)
1735 if (DEBUGLEVEL >= 6)
1736 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1737 "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X, Cmpval: 0x%08X\n",
1738 offset, cond, reg, mask, cmpval);
1740 nv32_rd(pScrn, reg, &data);
1743 if (DEBUGLEVEL >= 6)
1744 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1745 "0x%04X: Checking if 0x%08X equals 0x%08X\n",
1746 offset, data, cmpval);
1748 if (data == cmpval) {
1749 if (DEBUGLEVEL >= 6)
1750 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1751 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n", offset);
1753 if (DEBUGLEVEL >= 6)
1754 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1755 "0x%04X: CONDITION IS NOT FULFILLED.\n", offset);
1756 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1757 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
1758 iexec->execute = FALSE;
1764 static Bool init_index_io(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1766 /* INIT_INDEX_IO opcode: 0x78 ('x')
1768 * offset (8 bit): opcode
1769 * offset + 1 (16 bit): CRTC port
1770 * offset + 3 (8 bit): CRTC index
1771 * offset + 4 (8 bit): mask
1772 * offset + 5 (8 bit): data
1774 * Read value at index "CRTC index" on "CRTC port", AND with "mask", OR with "data", write-back
1777 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1778 uint8_t crtcindex = bios->data[offset + 3];
1779 uint8_t mask = bios->data[offset + 4];
1780 uint8_t data = bios->data[offset + 5];
1783 if (!iexec->execute)
1786 if (DEBUGLEVEL >= 6)
1787 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1788 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1789 offset, crtcport, crtcindex, mask, data);
1791 nv_idx_port_rd(pScrn, crtcport, crtcindex, &value);
1792 value = (value & mask) | data;
1793 nv_idx_port_wr(pScrn, crtcport, crtcindex, value);
1798 static Bool init_pll(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1800 /* INIT_PLL opcode: 0x79 ('y')
1802 * offset (8 bit): opcode
1803 * offset + 1 (32 bit): register
1804 * offset + 5 (16 bit): freq
1806 * Set PLL register "register" to coefficients for frequency (10kHz) "freq"
1809 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1810 uint16_t freq = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 5])));
1812 if (!iexec->execute)
1815 if (DEBUGLEVEL >= 6)
1816 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1817 "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n",
1820 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: [ NOT YET IMPLEMENTED ]\n", offset);
1825 configval = 0x00011F05;
1832 static Bool init_zm_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1834 /* INIT_ZM_REG opcode: 0x7A ('z')
1836 * offset (8 bit): opcode
1837 * offset + 1 (32 bit): register
1838 * offset + 5 (32 bit): value
1840 * Assign "value" to "register"
1843 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1844 uint32_t value = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1846 if (!iexec->execute)
1849 nv32_wr(pScrn, reg, value);
1854 /* hack to avoid moving the itbl_entry array before this function */
1855 int init_ram_restrict_zm_reg_group_blocklen = 0;
1857 static Bool init_ram_restrict_zm_reg_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1859 /* INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
1861 * offset (8 bit): opcode
1862 * offset + 1 (32 bit): reg
1863 * offset + 5 (8 bit): regincrement
1864 * offset + 6 (8 bit): count
1865 * offset + 7 (32 bit): value 1,1
1868 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
1869 * ram_restrict_table_ptr. The value read from here is 'n', and
1870 * "value 1,n" gets written to "reg". This repeats "count" times and on
1871 * each iteration 'm', "reg" increases by "regincrement" and
1872 * "value m,n" is used. The extent of n is limited by a number read
1873 * from the 'M' BIT table, herein called "blocklen"
1876 NVPtr pNv = NVPTR(pScrn);
1877 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1878 uint8_t regincrement = bios->data[offset + 5];
1879 uint8_t count = bios->data[offset + 6];
1880 uint32_t strap_ramcfg, data;
1885 /* previously set by 'M' BIT table */
1886 blocklen = init_ram_restrict_zm_reg_group_blocklen;
1888 if (!iexec->execute)
1892 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1893 "0x%04X: Zero block length - has the M table been parsed?\n", offset);
1897 strap_ramcfg = (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT) >> 2) & 0xf;
1898 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
1900 if (DEBUGLEVEL >= 6)
1901 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1902 "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
1903 offset, reg, regincrement, count, strap_ramcfg, index);
1905 for (i = 0; i < count; i++) {
1906 data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7 + index * 4 + blocklen * i])));
1908 nv32_wr(pScrn, reg, data);
1910 reg += regincrement;
1916 static Bool init_copy_zm_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1918 /* INIT_COPY_ZM_REG opcode: 0x90 ('')
1920 * offset (8 bit): opcode
1921 * offset + 1 (32 bit): src reg
1922 * offset + 5 (32 bit): dst reg
1924 * Put contents of "src reg" into "dst reg"
1927 uint32_t srcreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1928 uint32_t dstreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1931 if (!iexec->execute)
1934 nv32_rd(pScrn, srcreg, &data);
1935 nv32_wr(pScrn, dstreg, data);
1940 static Bool init_zm_reg_group_addr_latched(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1942 /* INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
1944 * offset (8 bit): opcode
1945 * offset + 1 (32 bit): src reg
1946 * offset + 5 (8 bit): count
1947 * offset + 6 (32 bit): data 1
1950 * For each of "count" values write "data n" to "src reg"
1953 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1954 uint8_t count = bios->data[offset + 5];
1957 if (!iexec->execute)
1960 for (i = 0; i < count; i++) {
1961 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 6 + 4 * i])));
1962 nv32_wr(pScrn, reg, data);
1968 static Bool init_reserved(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1970 /* INIT_RESERVED opcode: 0x92 ('')
1972 * offset (8 bit): opcode
1974 * Seemingly does nothing
1980 static init_tbl_entry_t itbl_entry[] = {
1981 /* command name , id , length , offset , mult , command handler */
1982 // { "INIT_PROG" , 0x31, 15 , 10 , 4 , init_prog },
1983 { "INIT_IO_RESTRICT_PROG" , 0x32, 11 , 6 , 4 , init_io_restrict_prog },
1984 { "INIT_REPEAT" , 0x33, 2 , 0 , 0 , init_repeat },
1985 { "INIT_IO_RESTRICT_PLL" , 0x34, 12 , 7 , 2 , init_io_restrict_pll },
1986 { "INIT_END_REPEAT" , 0x36, 1 , 0 , 0 , init_end_repeat },
1987 { "INIT_COPY" , 0x37, 11 , 0 , 0 , init_copy },
1988 { "INIT_NOT" , 0x38, 1 , 0 , 0 , init_not },
1989 { "INIT_IO_FLAG_CONDITION" , 0x39, 2 , 0 , 0 , init_io_flag_condition },
1990 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, 18 , 17 , 2 , init_idx_addr_latched },
1991 { "INIT_IO_RESTRICT_PLL2" , 0x4A, 11 , 6 , 4 , init_io_restrict_pll2 },
1992 { "INIT_PLL2" , 0x4B, 9 , 0 , 0 , init_pll2 },
1993 /* { "INIT_I2C_BYTE" , 0x4C, x , x , x , init_i2c_byte }, */
1994 /* { "INIT_ZM_I2C_BYTE" , 0x4D, x , x , x , init_zm_i2c_byte }, */
1995 /* { "INIT_ZM_I2C" , 0x4E, x , x , x , init_zm_i2c }, */
1996 { "INIT_TMDS" , 0x4F, 5 , 0 , 0 , init_tmds },
1997 { "INIT_ZM_TMDS_GROUP" , 0x50, 3 , 2 , 2 , init_zm_tmds_group },
1998 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, 5 , 4 , 1 , init_cr_idx_adr_latch },
1999 { "INIT_CR" , 0x52, 4 , 0 , 0 , init_cr },
2000 { "INIT_ZM_CR" , 0x53, 3 , 0 , 0 , init_zm_cr },
2001 { "INIT_ZM_CR_GROUP" , 0x54, 2 , 1 , 2 , init_zm_cr_group },
2002 { "INIT_CONDITION_TIME" , 0x56, 3 , 0 , 0 , init_condition_time },
2003 { "INIT_ZM_REG_SEQUENCE" , 0x58, 6 , 5 , 4 , init_zm_reg_sequence },
2004 // { "INIT_INDIRECT_REG" , 0x5A, 7 , 0 , 0 , init_indirect_reg },
2005 { "INIT_SUB_DIRECT" , 0x5B, 3 , 0 , 0 , init_sub_direct },
2006 { "INIT_COPY_NV_REG" , 0x5F, 22 , 0 , 0 , init_copy_nv_reg },
2007 { "INIT_ZM_INDEX_IO" , 0x62, 5 , 0 , 0 , init_zm_index_io },
2008 { "INIT_COMPUTE_MEM" , 0x63, 1 , 0 , 0 , init_compute_mem },
2009 { "INIT_RESET" , 0x65, 13 , 0 , 0 , init_reset },
2010 /* { "INIT_NEXT" , 0x66, x , x , x , init_next }, */
2011 /* { "INIT_NEXT" , 0x67, x , x , x , init_next }, */
2012 /* { "INIT_NEXT" , 0x68, x , x , x , init_next }, */
2013 // { "INIT_INDEX_IO8" , 0x69, 5 , 0 , 0 , init_index_io8 },
2014 { "INIT_SUB" , 0x6B, 2 , 0 , 0 , init_sub },
2015 // { "INIT_RAM_CONDITION" , 0x6D, 3 , 0 , 0 , init_ram_condition },
2016 { "INIT_NV_REG" , 0x6E, 13 , 0 , 0 , init_nv_reg },
2017 { "INIT_MACRO" , 0x6F, 2 , 0 , 0 , init_macro },
2018 { "INIT_DONE" , 0x71, 1 , 0 , 0 , init_done },
2019 { "INIT_RESUME" , 0x72, 1 , 0 , 0 , init_resume },
2020 // { "INIT_RAM_CONDITION2" , 0x73, 9 , 0 , 0 , init_ram_condition2 },
2021 { "INIT_TIME" , 0x74, 3 , 0 , 0 , init_time },
2022 { "INIT_CONDITION" , 0x75, 2 , 0 , 0 , init_condition },
2023 /* { "INIT_IO_CONDITION" , 0x76, x , x , x , init_io_condition }, */
2024 { "INIT_INDEX_IO" , 0x78, 6 , 0 , 0 , init_index_io },
2025 { "INIT_PLL" , 0x79, 7 , 0 , 0 , init_pll },
2026 { "INIT_ZM_REG" , 0x7A, 9 , 0 , 0 , init_zm_reg },
2027 /* INIT_RAM_RESTRICT_ZM_REG_GROUP's mult is loaded by M table in BIT */
2028 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, 7 , 6 , 0 , init_ram_restrict_zm_reg_group },
2029 { "INIT_COPY_ZM_REG" , 0x90, 9 , 0 , 0 , init_copy_zm_reg },
2030 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, 6 , 5 , 4 , init_zm_reg_group_addr_latched },
2031 { "INIT_RESERVED" , 0x92, 1 , 0 , 0 , init_reserved },
2032 { 0 , 0 , 0 , 0 , 0 , 0 }
2035 static unsigned int get_init_table_entry_length(bios_t *bios, unsigned int offset, int i)
2037 /* Calculates the length of a given init table entry. */
2038 return itbl_entry[i].length + bios->data[offset + itbl_entry[i].length_offset]*itbl_entry[i].length_multiplier;
2041 static void parse_init_table(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset, init_exec_t *iexec)
2043 /* Parses all commands in a init table. */
2045 /* We start out executing all commands found in the
2046 * init table. Some op codes may change the status
2047 * of this variable to SKIP, which will cause
2048 * the following op codes to perform no operation until
2049 * the value is changed back to EXECUTE.
2055 /* Loop until INIT_DONE causes us to break out of the loop
2056 * (or until offset > bios length just in case... )
2057 * (and no more than 10000 iterations just in case... ) */
2058 while ((offset < bios->length) && (count++ < 10000)) {
2059 id = bios->data[offset];
2061 /* Find matching id in itbl_entry */
2062 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
2065 if (itbl_entry[i].name) {
2066 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: [ (0x%02X) - %s ]\n",
2067 offset, itbl_entry[i].id, itbl_entry[i].name);
2069 /* execute eventual command handler */
2070 if (itbl_entry[i].handler)
2071 if (!(*itbl_entry[i].handler)(pScrn, bios, offset, iexec))
2074 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2075 "0x%04X: Init table command not found: 0x%02X\n", offset, id);
2079 /* Add the offset of the current command including all data
2080 * of that command. The offset will then be pointing on the
2083 offset += get_init_table_entry_length(bios, offset, i);
2087 static void parse_init_tables(ScrnInfoPtr pScrn, bios_t *bios)
2089 /* Loops and calls parse_init_table() for each present table. */
2093 init_exec_t iexec = {TRUE, FALSE};
2095 while ((table = le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + i]))))) {
2097 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: Parsing init table %d\n",
2100 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2101 "0x%04X: ------ EXECUTING FOLLOWING COMMANDS ------\n", table);
2103 parse_init_table(pScrn, bios, table, &iexec);
2108 void link_head_and_output(ScrnInfoPtr pScrn, int head, int dcb_entry, Bool overrideval)
2110 /* The BIOS scripts don't do this for us, sadly
2111 * Luckily we do know the values ;-)
2113 * head < 0 indicates we wish to force a setting with the overrideval
2114 * (for VT restore etc.)
2117 NVPtr pNv = NVPTR(pScrn);
2118 int preferred_output = (ffs(pNv->dcb_table.entry[dcb_entry].or) & OUTPUT_1) >> 1;
2119 Bool crosswired = FALSE;
2120 uint8_t tmds04 = 0x80;
2121 uint32_t tmds_ctrl, tmds_ctrl2;
2123 if (head != preferred_output) {
2127 /* Bit 3 crosswires output and bus. */
2128 if (head >= 0 && crosswired)
2130 if (head < 0 && overrideval)
2133 if (pNv->dcb_table.entry[dcb_entry].type == OUTPUT_LVDS)
2136 tmds_ctrl = NV_PRAMDAC0_OFFSET + (preferred_output ? NV_PRAMDAC0_SIZE : 0) + NV_RAMDAC_FP_TMDS_CONTROL;
2137 tmds_ctrl2 = NV_PRAMDAC0_OFFSET + (preferred_output ? NV_PRAMDAC0_SIZE : 0) + NV_RAMDAC_FP_TMDS_CONTROL_2;
2139 Bool oldexecute = pNv->VBIOS.execute;
2140 pNv->VBIOS.execute = TRUE;
2141 nv32_wr(pScrn, tmds_ctrl + 4, tmds04);
2142 nv32_wr(pScrn, tmds_ctrl, 0x04);
2143 if (pNv->dcb_table.entry[dcb_entry].type == OUTPUT_LVDS && pNv->VBIOS.fp.dual_link)
2144 nv32_wr(pScrn, tmds_ctrl2 + 4, tmds04 ^ 0x08);
2146 /* I have encountered no dvi (dual-link or not) that sets to anything else. */
2147 /* Does this change beyond the 165 MHz boundary? */
2148 nv32_wr(pScrn, tmds_ctrl2 + 4, 0x0);
2150 nv32_wr(pScrn, tmds_ctrl2, 0x04);
2151 pNv->VBIOS.execute = oldexecute;
2154 static void call_lvds_manufacturer_script(ScrnInfoPtr pScrn, int head, int dcb_entry, enum LVDS_script script)
2156 NVPtr pNv = NVPTR(pScrn);
2157 bios_t *bios = &pNv->VBIOS;
2158 init_exec_t iexec = {TRUE, FALSE};
2160 uint8_t sub = bios->data[bios->fp.xlated_entry + script];
2161 uint16_t scriptofs = le16_to_cpu(*((CARD16 *)(&bios->data[bios->init_script_tbls_ptr + sub * 2])));
2162 Bool power_off_for_reset, reset_after_pclk_change;
2163 uint16_t off_on_delay;
2165 if (!bios->fp.xlated_entry || !sub || !scriptofs)
2168 if (script == LVDS_INIT && bios->data[scriptofs] != 'q') {
2169 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "LVDS init script not stubbed\n");
2173 power_off_for_reset = bios->data[bios->fp.xlated_entry] & 1;
2174 reset_after_pclk_change = bios->data[bios->fp.xlated_entry] & 2;
2175 off_on_delay = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.xlated_entry + 7]);
2177 if (script == LVDS_PANEL_ON && reset_after_pclk_change)
2178 call_lvds_manufacturer_script(pScrn, head, dcb_entry, LVDS_RESET);
2179 if (script == LVDS_RESET && power_off_for_reset)
2180 call_lvds_manufacturer_script(pScrn, head, dcb_entry, LVDS_PANEL_OFF);
2182 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Calling LVDS script %d:\n", script);
2183 pNv->VBIOS.execute = TRUE;
2184 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_OWNER,
2185 head ? NV_VGA_CRTCX_OWNER_HEADB : NV_VGA_CRTCX_OWNER_HEADA);
2186 parse_init_table(pScrn, bios, scriptofs, &iexec);
2187 pNv->VBIOS.execute = FALSE;
2189 if (script == LVDS_PANEL_OFF)
2190 usleep(off_on_delay * 1000);
2191 if (script == LVDS_RESET)
2192 link_head_and_output(pScrn, head, dcb_entry, FALSE);
2195 static uint16_t clkcmptable(bios_t *bios, uint16_t clktable, uint16_t pxclk)
2197 int compare_record_len, i = 0;
2198 uint16_t compareclk, scriptptr = 0;
2200 if (bios->major_version < 5) /* pre BIT */
2201 compare_record_len = 3;
2203 compare_record_len = 4;
2206 compareclk = le16_to_cpu(*((uint16_t *)&bios->data[clktable + compare_record_len * i]));
2207 if (pxclk >= compareclk) {
2208 if (bios->major_version < 5) {
2209 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
2210 scriptptr = le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + tmdssub * 2])));
2212 scriptptr = le16_to_cpu(*((uint16_t *)&bios->data[clktable + 2 + compare_record_len * i]));
2216 } while (compareclk);
2221 static void rundigitaloutscript(ScrnInfoPtr pScrn, uint16_t scriptptr, int head, int dcb_entry)
2223 NVPtr pNv = NVPTR(pScrn);
2224 bios_t *bios = &pNv->VBIOS;
2225 init_exec_t iexec = {TRUE, FALSE};
2227 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: Parsing digital output script table\n", scriptptr);
2228 bios->execute = TRUE;
2229 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_OWNER,
2230 head ? NV_VGA_CRTCX_OWNER_HEADB : NV_VGA_CRTCX_OWNER_HEADA);
2231 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, 0x57, 0);
2232 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, 0x58, dcb_entry);
2233 parse_init_table(pScrn, bios, scriptptr, &iexec);
2234 bios->execute = FALSE;
2236 link_head_and_output(pScrn, head, dcb_entry, FALSE);
2239 static void run_lvds_table(ScrnInfoPtr pScrn, int head, int dcb_entry, enum LVDS_script script, uint16_t pxclk)
2241 /* The BIT LVDS table's header has the information to setup the
2242 * necessary registers. Following the standard 4 byte header are:
2243 * A bitmask byte and a dual-link transition pxclk valur for use in
2244 * selecting the init script when not using straps; 4 script pointers
2245 * for panel power, selected by output and on/off; and 8 table pointers
2246 * for panel init, the needed one determined by output, and bits in the
2247 * conf byte. These tables are similar to the TMDS tables, consisting
2248 * of a list of pxclks and script pointers.
2251 NVPtr pNv = NVPTR(pScrn);
2252 bios_t *bios = &pNv->VBIOS;
2253 int fpstrapping, outputset = (pNv->dcb_table.entry[dcb_entry].or == 4) ? 1 : 0;
2254 uint16_t scriptptr = 0, clktable;
2255 uint8_t clktableptr = 0;
2257 fpstrapping = (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT) >> 16) & 0xf;
2259 /* for now we assume version 3.0 table - g80 support will need some changes */
2264 case LVDS_BACKLIGHT_ON: // check applicability of the script for this
2266 scriptptr = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
2268 case LVDS_BACKLIGHT_OFF: // check applicability of the script for this
2269 case LVDS_PANEL_OFF:
2270 scriptptr = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
2273 if (pNv->dcb_table.entry[dcb_entry].lvdsconf.use_straps_for_mode ||
2274 (fpstrapping != 0x0f && bios->data[bios->fp.xlated_entry + 1] != 0x0f)) {
2275 if (bios->fp.dual_link)
2277 if (bios->fp.BITbit1)
2280 uint8_t fallback = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
2281 int fallbackcmpval = (pNv->dcb_table.entry[dcb_entry].or == 4) ? 4 : 1;
2282 uint8_t dltransitionclk = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 5]);
2283 if (pxclk > dltransitionclk) { // dual-link
2285 fallbackcmpval *= 2;
2287 if (fallbackcmpval & fallback)
2291 /* adding outputset * 8 may not be correct */
2292 clktable = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 15 + clktableptr * 2 + outputset * 8]);
2294 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Pixel clock comparison table not found\n");
2297 scriptptr = clkcmptable(bios, clktable, pxclk);
2301 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "LVDS output init script not found\n");
2304 rundigitaloutscript(pScrn, scriptptr, head, dcb_entry);
2307 void call_lvds_script(ScrnInfoPtr pScrn, int head, int dcb_entry, enum LVDS_script script, uint16_t pxclk)
2309 /* LVDS operations are multiplexed in an effort to present a single API
2310 * which works with two vastly differing underlying structures.
2311 * This acts as the demux
2314 NVPtr pNv = NVPTR(pScrn);
2315 bios_t *bios = &pNv->VBIOS;
2316 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
2321 if (lvds_ver < 0x30)
2322 call_lvds_manufacturer_script(pScrn, head, dcb_entry, script);
2324 run_lvds_table(pScrn, head, dcb_entry, script, pxclk);
2328 uint16_t fptablepointer;
2329 uint16_t fpxlatetableptr;
2330 uint16_t fpxlatemanufacturertableptr;
2334 static void parse_fp_mode_table(ScrnInfoPtr pScrn, bios_t *bios, struct fppointers *fpp)
2336 NVPtr pNv = NVPTR(pScrn);
2337 unsigned int fpstrapping;
2339 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
2341 DisplayModePtr mode;
2343 fpstrapping = (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT) >> 16) & 0xf;
2345 if (fpp->fptablepointer == 0x0 || fpp->fpxlatetableptr == 0x0) {
2346 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2347 "Pointers to flat panel table invalid\n");
2351 fptable = &bios->data[fpp->fptablepointer];
2353 fptable_ver = fptable[0];
2355 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2356 "Found flat panel mode table revision %d.%d\n",
2357 fptable_ver >> 4, fptable_ver & 0xf);
2359 switch (fptable_ver) {
2360 /* PINS version 0x5.0x11 BIOSen have version 1 like tables, but no version field,
2361 * and miss one of the spread spectrum/PWM bytes.
2362 * This could affect early GF2Go parts (not seen any appropriate ROMs though).
2363 * Here we assume that a version of 0x05 matches this case (combining with a
2364 * PINS version check would be better), as the common case for the panel type
2365 * field is 0x0005, and that is in fact what we are reading the first byte of. */
2366 case 0x05: /* some NV10, 11, 15, 16 */
2370 case 0x10: /* some NV15/16, and NV11+ */
2374 case 0x20: /* NV40+ */
2375 headerlen = fptable[1];
2376 recordlen = fptable[2];
2377 fpentries = fptable[3];
2381 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2382 "FP Table revision not currently supported\n");
2386 fpindex = bios->data[fpp->fpxlatetableptr + fpstrapping * fpp->xlatwidth];
2387 if (fpindex > fpentries) {
2388 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2389 "Bad flat panel table index\n");
2393 if (!(mode = xcalloc(1, sizeof(DisplayModeRec))))
2396 int modeofs = headerlen + recordlen * fpindex + ofs;
2397 mode->Clock = le16_to_cpu(*(uint16_t *)&fptable[modeofs]) * 10;
2398 mode->HDisplay = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 2]);
2399 mode->HSyncStart = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 10] + 1);
2400 mode->HSyncEnd = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 12] + 1);
2401 mode->HTotal = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 14] + 1);
2402 mode->VDisplay = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 16]);
2403 mode->VSyncStart = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 24] + 1);
2404 mode->VSyncEnd = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 26] + 1);
2405 mode->VTotal = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 28] + 1);
2406 mode->Flags |= (fptable[modeofs + 30] & 0x10) ? V_PHSYNC : V_NHSYNC;
2407 mode->Flags |= (fptable[modeofs + 30] & 0x1) ? V_PVSYNC : V_NVSYNC;
2410 * bytes 1-2 are "panel type", including bits on whether Colour/mono, single/dual link, and type (TFT etc.)
2411 * bytes 3-6 are bits per colour in RGBX
2413 * 13-14 is HValid Start
2414 * 15-16 is HValid End
2415 * bytes 38-39 relate to spread spectrum settings
2416 * bytes 40-43 are something to do with PWM */
2418 mode->prev = mode->next = NULL;
2419 mode->status = MODE_OK;
2420 mode->type = M_T_DRIVER | M_T_PREFERRED;
2421 xf86SetModeDefaultName(mode);
2423 // if (pNv->debug_modes) { this should exist
2424 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2425 "Found flat panel mode in BIOS tables:\n");
2426 xf86PrintModeline(pScrn->scrnIndex, mode);
2429 bios->fp.native_mode = mode;
2432 static void parse_lvds_manufacturer_table_init(ScrnInfoPtr pScrn, bios_t *bios, struct fppointers *fpp)
2434 /* The LVDS table changed considerably with BIT bioses. Previously
2435 * there was a header of version and record length, followed by several
2436 * records, indexed by a seperate xlat table, indexed in turn by the fp
2437 * strap in EXTDEV_BOOT. Each record had a config byte, followed by 6
2438 * script numbers for use by INIT_SUB which controlled panel init and
2439 * power, and finally a dword of ms to sleep between power off and on
2442 * The BIT LVDS table has the typical BIT table header: version byte,
2443 * header length byte, record length byte, and a byte for the maximum
2444 * number of records that can be held in the table.
2446 * The table following the header serves as an integrated config and
2447 * xlat table: the records in the table are indexed by the FP strap
2448 * nibble in EXTDEV_BOOT, and each record has two bytes - the first as
2449 * a config byte, the second for indexing the fp mode table pointed to
2450 * by the BIT 'D' table
2453 NVPtr pNv = NVPTR(pScrn);
2454 unsigned int fpstrapping, lvdsmanufacturerindex = 0;
2455 uint8_t lvds_ver, headerlen, recordlen;
2457 fpstrapping = (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT) >> 16) & 0xf;
2459 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
2460 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2461 "Pointer to LVDS manufacturer table invalid\n");
2465 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
2467 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2468 "Found LVDS manufacturer table revision %d.%d\n",
2469 lvds_ver >> 4, lvds_ver & 0xf);
2472 case 0x0a: /* pre NV40 */
2473 lvdsmanufacturerindex = bios->data[fpp->fpxlatemanufacturertableptr + fpstrapping];
2476 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
2479 case 0x30: /* NV4x */
2480 lvdsmanufacturerindex = fpstrapping;
2481 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
2482 if (headerlen < 0x1f) {
2483 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2484 "LVDS table header not understood\n");
2487 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
2489 case 0x40: /* It changed again with gf8 :o( */
2491 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2492 "LVDS table revision not currently supported\n");
2496 uint16_t lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + headerlen + recordlen * lvdsmanufacturerindex;
2499 bios->fp.dual_link = bios->data[lvdsofs] & 4;
2500 bios->fp.if_is_18bit = !(bios->data[lvdsofs] & 16);
2503 bios->fp.dual_link = bios->data[lvdsofs] & 1;
2504 bios->fp.BITbit1 = bios->data[lvdsofs] & 2;
2505 fpp->fpxlatetableptr = bios->fp.lvdsmanufacturerpointer + headerlen + 1;
2506 fpp->xlatwidth = recordlen;
2511 void run_tmds_table(ScrnInfoPtr pScrn, int dcb_entry, int head, uint16_t pxclk)
2513 /* the dcb_entry parameter is the index of the appropriate DCB entry
2514 * the pxclk parameter is in 10s of kHz (eg. 108Mhz is 10800, or 0x2a30)
2516 * This runs the TMDS regs setting code found on BIT bios cards
2518 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
2519 * ffs(or) == 3, use the second.
2522 NVPtr pNv = NVPTR(pScrn);
2523 bios_t *bios = &pNv->VBIOS;
2524 uint16_t clktable = 0, scriptptr;
2526 if (pNv->dcb_table.entry[dcb_entry].location) /* off chip */
2529 switch (ffs(pNv->dcb_table.entry[dcb_entry].or)) {
2531 clktable = bios->tmds.output0_script_ptr;
2535 clktable = bios->tmds.output1_script_ptr;
2540 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Pixel clock comparison table not found\n");
2544 scriptptr = clkcmptable(bios, clktable, pxclk);
2547 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TMDS output init script not found\n");
2551 rundigitaloutscript(pScrn, scriptptr, head, dcb_entry);
2554 static void parse_bios_version(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset)
2556 /* offset + 0 (8 bits): Micro version
2557 * offset + 1 (8 bits): Minor version
2558 * offset + 2 (8 bits): Chip version
2559 * offset + 3 (8 bits): Major version
2562 bios->major_version = bios->data[offset + 3];
2563 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Bios version %02x.%02x.%02x.%02x\n",
2564 bios->data[offset+3], bios->data[offset+2],
2565 bios->data[offset+1], bios->data[offset]);
2568 static int parse_bit_b_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
2570 /* offset + 0 (32 bits): BIOS version dword
2572 * There's a bunch of bits in this table other than the bios version
2573 * that we don't use - their use currently unknown
2576 if (bitentry->length < 0x4) {
2577 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2578 "Do not understand B table entry.\n");
2582 parse_bios_version(pScrn, bios, bitentry->offset);
2587 static void parse_pll_limits(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset)
2590 * Version 0x20: Exists on (some?) Geforce 6 cards.
2591 * Version 0x21: Exists on (some?) Geforce 7 cards.
2592 * This version is longer(35 vs 31), but we do nothing with that.
2594 bios->pll.version = bios->data[offset + 0];
2595 bios->pll.start = bios->data[offset + 1];
2596 bios->pll.entry_size = bios->data[offset + 2];
2597 bios->pll.num_entries = bios->data[offset + 3];
2599 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2600 "Found pll table version 0x%X.\n", bios->pll.version);
2602 if (bios->pll.version != 0x20 && bios->pll.version != 0x21) {
2603 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2604 "Unknown pll table version.\n");
2608 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2609 "Found pll table entry size %d.\n", bios->pll.entry_size);
2611 uint16_t new_offs = offset + bios->pll.start;
2612 Bool generic_pll = TRUE;
2615 for (i = 0; i < bios->pll.num_entries; i++) {
2616 uint32_t reg = *((uint32_t *)(&bios->data[new_offs]));
2617 if (reg == 0x4010 || reg == 0x4018) { /* primary and secondary vpll */
2618 generic_pll = FALSE;
2623 if (reg == 0x0000) { /* generic pll settings */
2626 new_offs += bios->pll.entry_size;
2629 /* We're only interrested in the vpll, not the other pll's. */
2630 new_offs = offset + bios->pll.start + bios->pll.entry_size * index;
2632 /* What is output frequencies can each VCO generate? */
2633 bios->pll.vco1.minfreq = *((uint16_t *)(&bios->data[new_offs + 4]));
2634 bios->pll.vco1.maxfreq = *((uint16_t *)(&bios->data[new_offs + 6]));
2635 bios->pll.vco2.minfreq = *((uint16_t *)(&bios->data[new_offs + 8]));
2636 bios->pll.vco2.maxfreq = *((uint16_t *)(&bios->data[new_offs + 10]));
2638 /* What input frequencies do they accept (past the m-divider)? */
2639 bios->pll.vco1.min_inputfreq = *((uint16_t *)(&bios->data[new_offs + 12]));
2640 bios->pll.vco1.max_inputfreq = *((uint16_t *)(&bios->data[new_offs + 14]));
2641 bios->pll.vco2.min_inputfreq = *((uint16_t *)(&bios->data[new_offs + 16]));
2642 bios->pll.vco2.max_inputfreq = *((uint16_t *)(&bios->data[new_offs + 18]));
2644 /* What values are accepted as multiplier and divider? */
2645 bios->pll.vco1.min_n = bios->data[new_offs + 20];
2646 bios->pll.vco1.max_n = bios->data[new_offs + 21];
2647 bios->pll.vco1.min_m = bios->data[new_offs + 22];
2648 bios->pll.vco1.max_m = bios->data[new_offs + 23];
2649 bios->pll.vco2.min_n = bios->data[new_offs + 24];
2650 bios->pll.vco2.max_n = bios->data[new_offs + 25];
2651 bios->pll.vco2.min_m = bios->data[new_offs + 26];
2652 bios->pll.vco2.max_m = bios->data[new_offs + 27];
2654 bios->pll.unk1c = bios->data[new_offs + 28];
2655 bios->pll.unk1d = bios->data[new_offs + 29];
2656 bios->pll.unk1e = bios->data[new_offs + 30];
2658 #if 1 /* for easy debugging */
2659 ErrorF("pll.vco1.minfreq: %d\n", bios->pll.vco1.minfreq);
2660 ErrorF("pll.vco1.maxfreq: %d\n", bios->pll.vco1.maxfreq);
2661 ErrorF("pll.vco2.minfreq: %d\n", bios->pll.vco2.minfreq);
2662 ErrorF("pll.vco2.maxfreq: %d\n", bios->pll.vco2.maxfreq);
2664 ErrorF("pll.vco1.min_inputfreq: %d\n", bios->pll.vco1.min_inputfreq);
2665 ErrorF("pll.vco1.max_inputfreq: %d\n", bios->pll.vco1.max_inputfreq);
2666 ErrorF("pll.vco2.min_inputfreq: %d\n", bios->pll.vco2.min_inputfreq);
2667 ErrorF("pll.vco2.max_inputfreq: %d\n", bios->pll.vco2.max_inputfreq);
2669 ErrorF("pll.vco1.min_n: %d\n", bios->pll.vco1.min_n);
2670 ErrorF("pll.vco1.max_n: %d\n", bios->pll.vco1.max_n);
2671 ErrorF("pll.vco1.min_m: %d\n", bios->pll.vco1.min_m);
2672 ErrorF("pll.vco1.max_m: %d\n", bios->pll.vco1.max_m);
2673 ErrorF("pll.vco2.min_n: %d\n", bios->pll.vco2.min_n);
2674 ErrorF("pll.vco2.max_n: %d\n", bios->pll.vco2.max_n);
2675 ErrorF("pll.vco2.min_m: %d\n", bios->pll.vco2.min_m);
2676 ErrorF("pll.vco2.max_m: %d\n", bios->pll.vco2.max_m);
2678 ErrorF("pll.unk1c: %d\n", bios->pll.unk1c);
2679 ErrorF("pll.unk1d: %d\n", bios->pll.unk1d);
2680 ErrorF("pll.unk1e: %d\n", bios->pll.unk1e);
2684 static int parse_bit_c_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
2686 /* offset + 8 (16 bits): PLL limits for NV4x cards (what about other cards?).
2688 * There's more in here, but that's unknown.
2691 parse_pll_limits(pScrn, bios, le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 8]))));
2696 static int parse_bit_display_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry, struct fppointers *fpp)
2698 /* Parses the flat panel table segment that the bit entry points to.
2699 * Starting at bitentry->offset:
2701 * offset + 0 (16 bits): FIXME table pointer
2702 * offset + 2 (16 bits): mode table pointer
2705 if (bitentry->length != 4) {
2706 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2707 "Do not understand BIT display table entry.\n");
2711 fpp->fptablepointer = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 2])));
2716 static unsigned int parse_bit_init_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
2718 /* Parses the init table segment that the bit entry points to.
2719 * Starting at bitentry->offset:
2721 * offset + 0 (16 bits): init script tables pointer
2722 * offset + 2 (16 bits): macro index table pointer
2723 * offset + 4 (16 bits): macro table pointer
2724 * offset + 6 (16 bits): condition table pointer
2725 * offset + 8 (16 bits): io condition table pointer
2726 * offset + 10 (16 bits): io flag condition table pointer
2727 * offset + 12 (16 bits): init function table pointer
2730 * * Are 'I' bit entries always of length 0xE?
2734 if (bitentry->length < 12) {
2735 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2736 "Unable to recognize BIT init table entry.\n");
2740 bios->init_script_tbls_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
2741 bios->macro_index_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 2])));
2742 bios->macro_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 4])));
2743 bios->condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 6])));
2744 bios->io_condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 8])));
2745 bios->io_flag_condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 10])));
2746 bios->init_function_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 12])));
2748 parse_init_tables(pScrn, bios);
2753 static int parse_bit_lvds_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry, struct fppointers *fpp)
2755 /* Parses the LVDS table segment that the bit entry points to.
2756 * Starting at bitentry->offset:
2758 * offset + 0 (16 bits): LVDS strap xlate table pointer
2761 if (bitentry->length != 2) {
2762 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2763 "Do not understand BIT LVDS table entry.\n");
2767 /* no idea if it's still called the LVDS manufacturer table, but the concept's close enough */
2768 bios->fp.lvdsmanufacturerpointer = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
2770 parse_lvds_manufacturer_table_init(pScrn, bios, fpp);
2775 static int parse_bit_m_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
2777 /* offset + 2 (8 bits): number of options in an INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
2778 * offset + 3 (16 bits): pointer to strap xlate table for RAM restrict option selection
2780 * There's a bunch of bits in this table other than the RAM restrict
2781 * stuff that we don't use - their use currently unknown
2786 /* Older bios versions don't have a sufficiently long table for what we want */
2787 if (bitentry->length < 0x5)
2790 /* set up multiplier for INIT_RAM_RESTRICT_ZM_REG_GROUP */
2791 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != 0x8f); i++)
2793 itbl_entry[i].length_multiplier = bios->data[bitentry->offset + 2] * 4;
2794 init_ram_restrict_zm_reg_group_blocklen = itbl_entry[i].length_multiplier;
2796 bios->ram_restrict_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 3])));
2801 static int parse_bit_tmds_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
2803 /* Parses the pointer to the TMDS table
2805 * Starting at bitentry->offset:
2807 * offset + 0 (16 bits): TMDS table pointer
2809 * The TMDS table is typically found just before the DCB table, with a
2810 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
2813 * At offset +7 is a pointer to a script, which I don't know how to run yet
2814 * At offset +9 is a pointer to another script, likewise
2815 * Offset +11 has a pointer to a table where the first word is a pxclk
2816 * frequency and the second word a pointer to a script, which should be
2817 * run if the comparison pxclk frequency is less than the pxclk desired.
2818 * This repeats for decreasing comparison frequencies
2819 * Offset +13 has a pointer to a similar table
2820 * The selection of table (and possibly +7/+9 script) is dictated by
2821 * "or" from the DCB.
2824 uint16_t tmdstableptr, script1, script2;
2826 if (bitentry->length != 2) {
2827 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2828 "Do not understand BIT TMDS table entry.\n");
2832 tmdstableptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
2834 if (tmdstableptr == 0x0) {
2835 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Pointer to TMDS table invalid\n");
2839 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Found TMDS table revision %d.%d\n",
2840 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
2842 /* These two scripts are odd: they don't seem to get run even when they are not stubbed */
2843 script1 = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 7]));
2844 script2 = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 9]));
2845 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
2846 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TMDS table script pointers not stubbed\n");
2848 bios->tmds.output0_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 11]));
2849 bios->tmds.output1_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 13]));
2854 static unsigned int parse_bmp_table_pointers(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
2856 /* Parse the pointers for useful tables in the BMP structure, starting at
2857 * offset 75 from the ..NV. signature.
2859 * First 7 pointers as for parse_bit_init_tbl_entry
2861 * offset + 30: flat panel timings table pointer
2862 * offset + 32: flat panel strapping translation table pointer
2863 * offset + 42: LVDS manufacturer panel config table pointer
2864 * offset + 44: LVDS manufacturer strapping translation table pointer
2867 NVPtr pNv = NVPTR(pScrn);
2868 struct fppointers fpp;
2870 if (!parse_bit_init_tbl_entry(pScrn, bios, bitentry))
2873 /* If it's not a laptop, you probably don't care about fptables */
2874 /* FIXME: detect mobile BIOS? */
2878 if (bitentry->length > 17) {
2879 bios->tmds.output0_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[bitentry->offset + 14]));
2880 bios->tmds.output1_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[bitentry->offset + 16]));
2883 memset(&fpp, 0, sizeof(struct fppointers));
2884 if (bitentry->length > 33) {
2885 fpp.fptablepointer = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 30])));
2886 fpp.fpxlatetableptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 32])));
2888 parse_fp_mode_table(pScrn, bios, &fpp);
2890 if (bitentry->length > 45) {
2891 bios->fp.lvdsmanufacturerpointer = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 42])));
2892 fpp.fpxlatemanufacturertableptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 44])));
2893 parse_lvds_manufacturer_table_init(pScrn, bios, &fpp);
2894 /* I've never seen a valid LVDS_INIT script, so we'll do a test for it here */
2895 call_lvds_script(pScrn, 0, 0, LVDS_INIT, 0);
2901 static void parse_bit_structure(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset)
2903 bit_entry_t bitentry, storedinitentry = {{ 0 }};
2905 struct fppointers fpp;
2906 NVPtr pNv = NVPTR(pScrn);
2908 memset(&fpp, 0, sizeof(struct fppointers));
2911 bitentry.id[0] = bios->data[offset];
2912 bitentry.id[1] = bios->data[offset + 1];
2913 bitentry.length = le16_to_cpu(*((uint16_t *)&bios->data[offset + 2]));
2914 bitentry.offset = le16_to_cpu(*((uint16_t *)&bios->data[offset + 4]));
2916 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2917 "0x%04X: Found BIT command with id 0x%02X (%c)\n",
2918 offset, bitentry.id[0], bitentry.id[0]);
2920 switch (bitentry.id[0]) {
2922 /* id[0] = 0 and id[1] = 0 ==> end of BIT struture */
2923 if (bitentry.id[1] == 0)
2927 parse_bit_b_tbl_entry(pScrn, bios, &bitentry);
2930 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2931 "0x%04X: Found C table entry in BIT structure.\n", offset);
2932 parse_bit_c_tbl_entry(pScrn, bios, &bitentry);
2935 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2936 "0x%04X: Found flat panel display table entry in BIT structure.\n", offset);
2937 parse_bit_display_tbl_entry(pScrn, bios, &bitentry, &fpp);
2940 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2941 "0x%04X: Found init table entry in BIT structure.\n", offset);
2942 memcpy(&storedinitentry, &bitentry, sizeof(bit_entry_t));
2945 parse_bit_lvds_tbl_entry(pScrn, bios, &bitentry, &fpp);
2947 case 'M': /* memory? */
2948 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2949 "0x%04X: Found M table entry in BIT structure.\n", offset);
2950 parse_bit_m_tbl_entry(pScrn, bios, &bitentry);
2953 parse_bit_tmds_tbl_entry(pScrn, bios, &bitentry);
2956 /* TODO: What kind of information does the other BIT entrys point to?
2957 * 'P' entry is probably performance tables, but there are
2958 * quite a few others...
2962 offset += sizeof(bit_entry_t);
2965 /* 'M' table has to be parsed before 'I' can run */
2966 if (storedinitentry.id[0]) {
2967 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2968 "Parsing previously deferred init table entry.\n");
2969 parse_bit_init_tbl_entry(pScrn, bios, &storedinitentry);
2972 /* If it's not a laptop, you probably don't care about LVDS */
2973 /* FIXME: detect mobile BIOS? */
2977 /* Need D and L tables parsed before doing this */
2978 parse_fp_mode_table(pScrn, bios, &fpp);
2982 static void parse_pins_structure(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset)
2984 int pins_version_major=bios->data[offset+5];
2985 int pins_version_minor=bios->data[offset+6];
2986 int init1 = bios->data[offset + 18] + (bios->data[offset + 19] * 256);
2987 int init2 = bios->data[offset + 20] + (bios->data[offset + 21] * 256);
2988 int init_size = bios->data[offset + 22] + (bios->data[offset + 23] * 256) + 1;
2991 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "PINS version %d.%d\n",
2992 pins_version_major, pins_version_minor);
2995 if (nv_cksum(bios->data + offset, 8)) {
2996 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "bad PINS checksum\n");
3000 switch (pins_version_major) {
3002 ram_tab = init1-0x0010;
3007 ram_tab = bios->data[offset + 24] + (bios->data[offset + 25] * 256);
3013 if ((pins_version_major==5)&&(pins_version_minor>=6)) {
3014 /* VCO range info */
3017 if ((pins_version_major==5)&&(pins_version_minor>=16)) {
3018 bit_entry_t bitentry;
3020 if (pins_version_minor == 0x10)
3021 bitentry.length = 12; /* I've not seen this version, so be "long enough" */
3022 else if (pins_version_minor < 0x14)
3023 bitentry.length = 34;
3025 bitentry.length = 48; /* versions after 0x14 are longer,
3026 but extra contents unneeded ATM */
3028 parse_bios_version(pScrn, bios, offset + 10);
3029 bitentry.offset = offset + 75;
3030 parse_bmp_table_pointers(pScrn, bios, &bitentry);
3032 /* TODO type1 script */
3036 static unsigned int findstr(bios_t* bios, unsigned char *str, int len)
3040 for (i = 2; i <= (bios->length - len); i++)
3041 if (strncmp((char *)&bios->data[i], (char *)str, len) == 0)
3047 static Bool parse_dcb_entry(uint8_t dcb_version, uint32_t conn, uint32_t conf, struct dcb_entry *entry)
3049 memset(entry, 0, sizeof (struct dcb_entry));
3051 if (dcb_version >= 0x20) {
3052 entry->type = conn & 0xf;
3053 entry->i2c_index = (conn >> 4) & 0xf;
3054 entry->heads = (conn >> 8) & 0xf;
3055 entry->bus = (conn >> 16) & 0xf;
3056 entry->location = (conn >> 20) & 0xf;
3057 entry->or = (conn >> 24) & 0xf;
3058 if ((1 << ffs(entry->or)) * 3 == entry->or)
3059 entry->duallink_possible = TRUE;
3061 entry->duallink_possible = FALSE;
3063 switch (entry->type) {
3065 if (conf & 0xfffffffa)
3066 ErrorF("Unknown LVDS configuration bits, please report\n");
3068 entry->lvdsconf.use_straps_for_mode = TRUE;
3070 entry->lvdsconf.use_power_scripts = TRUE;
3073 } else if (dcb_version >= 0x14 ) {
3074 if (conn != 0xf0003f00) {
3075 ErrorF("Unknown DCB 1.4 entry, please report\n");
3078 /* safe defaults for a crt */
3080 entry->i2c_index = 0;
3083 entry->location = 0;
3085 entry->duallink_possible = FALSE;
3087 // 1.2 needs more loving
3090 entry->i2c_index = 0;
3093 entry->location = 0;
3095 entry->duallink_possible = FALSE;
3102 read_dcb_i2c_table(ScrnInfoPtr pScrn, bios_t *bios, uint8_t dcb_version, uint16_t i2ctabptr)
3104 NVPtr pNv = NVPTR(pScrn);
3106 uint8_t headerlen = 0;
3108 int recordoffset = 0, rdofs = 1, wrofs = 0;
3111 i2c_entries = MAX_NUM_DCB_ENTRIES;
3112 memset(pNv->dcb_table.i2c_read, 0, sizeof(pNv->dcb_table.i2c_read));
3113 memset(pNv->dcb_table.i2c_write, 0, sizeof(pNv->dcb_table.i2c_write));
3115 i2ctable = &bios->data[i2ctabptr];
3117 if (dcb_version >= 0x30) {
3118 if (i2ctable[0] != dcb_version) { /* necessary? */
3119 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3120 "DCB I2C table version mismatch (%02X vs %02X)\n",
3121 i2ctable[0], dcb_version);
3124 headerlen = i2ctable[1];
3125 i2c_entries = i2ctable[2];
3126 if (i2ctable[0] >= 0x40) {
3127 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3128 "G80 DCB I2C table detected, arrgh\n"); /* they're plain weird */
3132 /* it's your own fault if you call this function on a DCB 1.1 BIOS */
3133 if (dcb_version < 0x14) {
3139 for (i = 0; i < i2c_entries; i++) {
3140 if (i2ctable[headerlen + 4 * i + 3] != 0xff) {
3141 pNv->dcb_table.i2c_read[i] = i2ctable[headerlen + recordoffset + rdofs + 4 * i];
3142 pNv->dcb_table.i2c_write[i] = i2ctable[headerlen + recordoffset + wrofs + 4 * i];
3147 static unsigned int parse_dcb_table(ScrnInfoPtr pScrn, bios_t *bios)
3149 NVPtr pNv = NVPTR(pScrn);
3150 uint16_t dcbptr, i2ctabptr = 0;
3152 uint8_t dcb_version, headerlen = 0x4, entries = MAX_NUM_DCB_ENTRIES;
3153 Bool configblock = TRUE;
3154 int recordlength = 8, confofs = 4;
3157 pNv->dcb_table.entries = 0;
3159 /* get the offset from 0x36 */
3160 dcbptr = le16_to_cpu(*(uint16_t *)&bios->data[0x36]);
3162 if (dcbptr == 0x0) {
3163 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3164 "No Display Configuration Block pointer found\n");
3168 dcbtable = &bios->data[dcbptr];
3170 /* get DCB version */
3171 dcb_version = dcbtable[0];
3172 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3173 "Display Configuration Block version %d.%d found\n",
3174 dcb_version >> 4, dcb_version & 0xf);
3176 if (dcb_version >= 0x20) { /* NV17+ */
3179 if (dcb_version >= 0x30) { /* NV40+ */
3180 headerlen = dcbtable[1];
3181 entries = dcbtable[2];
3182 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[4]);
3183 sig = le32_to_cpu(*(uint32_t *)&dcbtable[6]);
3185 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3186 "DCB header length %02X, with %02X possible entries\n",
3187 headerlen, entries);
3189 /* dcb_block_count = *(dcbtable[1]); */
3190 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
3191 sig = le32_to_cpu(*(uint32_t *)&dcbtable[4]);
3195 if (sig != 0x4edcbdcb) {
3196 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3197 "Bad Display Configuration Block signature (%08X)\n", sig);
3200 } else if (dcb_version >= 0x14) { /* some NV15/16, and NV11+ */
3204 strncpy(sig, (char *)&dcbtable[-7], 7);
3205 /* dcb_block_count = *(dcbtable[1]); */
3206 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
3210 if (strcmp(sig, "DEV_REC")) {
3211 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3212 "Bad Display Configuration Block signature (%s)\n", sig);
3215 } else if (dcb_version >= 0x12) { /* some NV6/10, and NV15+ */
3216 /* dcb_block_count = *(dcbtable[1]); */
3217 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
3218 configblock = FALSE;
3219 } else { /* NV5+, maybe NV4 */
3220 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3221 "Structure of Display Configuration Blocks prior to version 1.2 unknown\n");
3225 if (entries >= MAX_NUM_DCB_ENTRIES)
3226 entries = MAX_NUM_DCB_ENTRIES;
3228 for (i = 0; i < entries; i++) {
3229 uint32_t connection, config = 0;
3231 connection = le32_to_cpu(*(uint32_t *)&dcbtable[headerlen + recordlength * i]);
3233 config = le32_to_cpu(*(uint32_t *)&dcbtable[headerlen + confofs + recordlength * i]);
3235 /* Should we allow discontinuous DCBs? Certainly DCB I2C tables
3236 * can be discontinuous */
3237 if ((connection & 0x0000000f) == 0x0000000f) /* end of records */
3240 ErrorF("Raw DCB entry %d: %08x %08x\n", i, connection, config);
3241 if (!parse_dcb_entry(dcb_version, connection, config, &pNv->dcb_table.entry[i]))
3244 pNv->dcb_table.entries = i;
3246 read_dcb_i2c_table(pScrn, bios, dcb_version, i2ctabptr);
3248 /* This is needed for DCB version 2.0 */
3249 /* Otherwise you end up with multiple outputs that are trying to be activated */
3250 for ( i = 0; i < pNv->dcb_table.entries; i ++) {
3252 int cur_i2c = pNv->dcb_table.entry[i].i2c_index;
3253 int cur_type = pNv->dcb_table.entry[i].type;
3254 for ( j = 0; j < pNv->dcb_table.entries; j ++ ) {
3255 if ( i == j ) continue;
3256 if ( pNv->dcb_table.entry[j].type == 100) continue; /* merged entry */
3257 if (( pNv->dcb_table.entry[j].i2c_index == cur_i2c ) && ( pNv->dcb_table.entry[j].type == cur_type )) {
3258 /* We can only merge entries with the same allowed crtc's. */
3259 /* This has not occured so far and needs some logic (to merge dual link properly). */
3260 /* So this remains TODO for the moment. */
3262 /* We also merge entries with the same allowed output routes */
3263 if (pNv->dcb_table.entry[i].or == pNv->dcb_table.entry[j].or) {
3264 xf86DrvMsg(0, X_INFO, "Merging DCB entries %d and %d!\n", i, j);
3265 pNv->dcb_table.entry[i].heads |= pNv->dcb_table.entry[j].heads;
3267 pNv->dcb_table.entry[j].type = 100; /* dummy value */
3273 /* Remove "disabled" entries (merged) */
3274 int valid_entries[pNv->dcb_table.entries];
3276 for ( i = 0; i < pNv->dcb_table.entries; i ++) valid_entries[i] = -1;
3277 for ( i = 0; i < pNv->dcb_table.entries; i ++)
3278 if ( pNv->dcb_table.entry[i].type != 100 ) {
3279 valid_entries[cent] = i;
3282 for ( i = 0; i < cent; i++) {
3283 memmove(&pNv->dcb_table.entry[i], &pNv->dcb_table.entry[valid_entries[i]], sizeof(pNv->dcb_table.entry[i]));
3284 memmove(&pNv->dcb_table.i2c_read[i], &pNv->dcb_table.i2c_read[valid_entries[i]], sizeof(pNv->dcb_table.i2c_read[i]));
3285 memmove(&pNv->dcb_table.i2c_write[i], &pNv->dcb_table.i2c_write[valid_entries[i]], sizeof(pNv->dcb_table.i2c_write[i]));
3288 pNv->dcb_table.entries = cent;
3290 return pNv->dcb_table.entries;
3293 unsigned int NVParseBios(ScrnInfoPtr pScrn)
3295 unsigned int bit_offset;
3296 uint8_t nv_signature[]={0xff,0x7f,'N','V',0x0};
3297 uint8_t bit_signature[]={'B','I','T'};
3301 pNv->dcb_table.entries = 0;
3303 memset(&pNv->VBIOS, 0, sizeof(bios_t));
3304 pNv->VBIOS.execute = FALSE;
3305 pNv->VBIOS.data = xalloc(64 * 1024);
3306 if (!NVShadowVBIOS(pScrn, pNv->VBIOS.data)) {
3307 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3308 "No valid BIOS image found.\n");
3309 xfree(pNv->VBIOS.data);
3312 pNv->VBIOS.length = pNv->VBIOS.data[2] * 512;
3313 if (pNv->VBIOS.length > NV_PROM_SIZE)
3314 pNv->VBIOS.length = NV_PROM_SIZE;
3316 /* parse Display Configuration Block (DCB) table */
3317 if (parse_dcb_table(pScrn, &pNv->VBIOS))
3318 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3319 "Found %d entries in DCB.\n", pNv->dcb_table.entries);
3321 /* check for known signatures */
3322 if ((bit_offset = findstr(&pNv->VBIOS, bit_signature, sizeof(bit_signature)))) {
3323 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BIT signature found.\n");
3324 parse_bit_structure(pScrn, &pNv->VBIOS, bit_offset + 4);
3325 } else if ((bit_offset = findstr(&pNv->VBIOS, nv_signature, sizeof(nv_signature)))) {
3326 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NV signature found.\n");
3327 parse_pins_structure(pScrn, &pNv->VBIOS, bit_offset);
3329 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3330 "No known script signature found.\n");