git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 2006 Dave Airlie
   3  * Copyright 2007 Maarten Maathuis
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
  26  * decleration is at the bottom of this file as it is rather ugly
  27  */
  28
  29
  30 #ifdef HAVE_CONFIG_H
  31 #include "config.h"
  32 #endif
  33
  34 #ifdef ENABLE_RANDR12
  35
  36 #include <assert.h>
  37 #include "xf86.h"
  38 #include "os.h"
  39 #include "mibank.h"
  40 #include "globals.h"
  41 #include "xf86.h"
  42 #include "xf86Priv.h"
  43 #include "xf86DDC.h"
  44 #include "mipointer.h"
  45 #include "windowstr.h"
  46 #include <randrstr.h>
  47 #include <X11/extensions/render.h>
  48
  49 #include "xf86Crtc.h"
  50 #include "nv_include.h"
  51
  52 #include "vgaHW.h"
  53
  54 #define CRTC_INDEX 0x3d4
  55 #define CRTC_DATA 0x3d5
  56 #define CRTC_IN_STAT_1 0x3da
  57
  58 #define WHITE_VALUE 0x3F
  59 #define BLACK_VALUE 0x00
  60 #define OVERSCAN_VALUE 0x01
  61
  62 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  63 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  64 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  65 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  66
  67 static CARD8 NVReadPVIO(xf86CrtcPtr crtc, CARD8 address)
  68 {
  69         ScrnInfoPtr pScrn = crtc->scrn;
  70         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  71         NVPtr pNv = NVPTR(pScrn);
  72
  73         if (nv_crtc->head == 1) {
  74                 return NV_RD08(pNv->PVIO1, address);
  75         } else {
  76                 return NV_RD08(pNv->PVIO0, address);
  77         }
  78 }
  79
  80 static void NVWritePVIO(xf86CrtcPtr crtc, CARD8 address, CARD8 value)
  81 {
  82         ScrnInfoPtr pScrn = crtc->scrn;
  83         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  84         NVPtr pNv = NVPTR(pScrn);
  85
  86         if (nv_crtc->head == 1) {
  87                 NV_WR08(pNv->PVIO1, address, value);
  88         } else {
  89                 NV_WR08(pNv->PVIO0, address, value);
  90         }
  91 }
  92
  93 static void NVWriteMiscOut(xf86CrtcPtr crtc, CARD8 value)
  94 {
  95         ScrnInfoPtr pScrn = crtc->scrn;
  96         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  97         NVPtr pNv = NVPTR(pScrn);
  98
  99         NVWritePVIO(crtc, VGA_MISC_OUT_W, value);
 100 }
 101
 102 static CARD8 NVReadMiscOut(xf86CrtcPtr crtc)
 103 {
 104         ScrnInfoPtr pScrn = crtc->scrn;
 105         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 106         NVPtr pNv = NVPTR(pScrn);
 107
 108         return NVReadPVIO(crtc, VGA_MISC_OUT_R);
 109 }
 110
 111 void NVWriteVGA(NVPtr pNv, int head, CARD8 index, CARD8 value)
 112 {
 113         volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 114
 115         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 116         NV_WR08(pCRTCReg, CRTC_DATA, value);
 117 }
 118
 119 CARD8 NVReadVGA(NVPtr pNv, int head, CARD8 index)
 120 {
 121         volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 122
 123         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 124         return NV_RD08(pCRTCReg, CRTC_DATA);
 125 }
 126
 127 void NVWriteVgaCrtc(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 128 {
 129         ScrnInfoPtr pScrn = crtc->scrn;
 130         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 131         NVPtr pNv = NVPTR(pScrn);
 132
 133         NVWriteVGA(pNv, nv_crtc->head, index, value);
 134 }
 135
 136 CARD8 NVReadVgaCrtc(xf86CrtcPtr crtc, CARD8 index)
 137 {
 138         ScrnInfoPtr pScrn = crtc->scrn;
 139         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 140         NVPtr pNv = NVPTR(pScrn);
 141
 142         return NVReadVGA(pNv, nv_crtc->head, index);
 143 }
 144
 145 static void NVWriteVgaSeq(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 146 {
 147         ScrnInfoPtr pScrn = crtc->scrn;
 148         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 149         NVPtr pNv = NVPTR(pScrn);
 150
 151         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 152         NVWritePVIO(crtc, VGA_SEQ_DATA, value);
 153 }
 154
 155 static CARD8 NVReadVgaSeq(xf86CrtcPtr crtc, CARD8 index)
 156 {
 157         ScrnInfoPtr pScrn = crtc->scrn;
 158         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 159         NVPtr pNv = NVPTR(pScrn);
 160
 161         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 162         return NVReadPVIO(crtc, VGA_SEQ_DATA);
 163 }
 164
 165 static void NVWriteVgaGr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 166 {
 167         ScrnInfoPtr pScrn = crtc->scrn;
 168         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 169         NVPtr pNv = NVPTR(pScrn);
 170
 171         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 172         NVWritePVIO(crtc, VGA_GRAPH_DATA, value);
 173 }
 174
 175 static CARD8 NVReadVgaGr(xf86CrtcPtr crtc, CARD8 index)
 176 {
 177         ScrnInfoPtr pScrn = crtc->scrn;
 178         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 179         NVPtr pNv = NVPTR(pScrn);
 180
 181         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 182         return NVReadPVIO(crtc, VGA_GRAPH_DATA);
 183 }
 184
 185
 186 static void NVWriteVgaAttr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 187 {
 188   ScrnInfoPtr pScrn = crtc->scrn;
 189   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 190   NVPtr pNv = NVPTR(pScrn);
 191   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 192
 193   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 194   if (nv_crtc->paletteEnabled)
 195     index &= ~0x20;
 196   else
 197     index |= 0x20;
 198   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 199   NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
 200 }
 201
 202 static CARD8 NVReadVgaAttr(xf86CrtcPtr crtc, CARD8 index)
 203 {
 204   ScrnInfoPtr pScrn = crtc->scrn;
 205   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 206   NVPtr pNv = NVPTR(pScrn);
 207   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 208
 209   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 210   if (nv_crtc->paletteEnabled)
 211     index &= ~0x20;
 212   else
 213     index |= 0x20;
 214   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 215   return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
 216 }
 217
 218 void NVCrtcSetOwner(xf86CrtcPtr crtc)
 219 {
 220         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 221         ScrnInfoPtr pScrn = crtc->scrn;
 222         NVPtr pNv = NVPTR(pScrn);
 223         /* Non standard beheaviour required by NV11 */
 224         if (pNv) {
 225                 uint8_t owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 226                 ErrorF("pre-Owner: 0x%X\n", owner);
 227                 if (owner == 0x04) {
 228                         uint32_t pbus84 = nvReadMC(pNv, 0x1084);
 229                         ErrorF("pbus84: 0x%X\n", pbus84);
 230                         pbus84 &= ~(1<<28);
 231                         ErrorF("pbus84: 0x%X\n", pbus84);
 232                         nvWriteMC(pNv, 0x1084, pbus84);
 233                 }
 234                 /* The blob never writes owner to pcio1, so should we */
 235                 if (pNv->NVArch == 0x11) {
 236                         NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, 0xff);
 237                 }
 238                 NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, nv_crtc->crtc * 0x3);
 239                 owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 240                 ErrorF("post-Owner: 0x%X\n", owner);
 241         } else {
 242                 ErrorF("pNv pointer is NULL\n");
 243         }
 244 }
 245
 246 static void
 247 NVEnablePalette(xf86CrtcPtr crtc)
 248 {
 249   ScrnInfoPtr pScrn = crtc->scrn;
 250   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 251   NVPtr pNv = NVPTR(pScrn);
 252   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 253
 254   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 255   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
 256   nv_crtc->paletteEnabled = TRUE;
 257 }
 258
 259 static void
 260 NVDisablePalette(xf86CrtcPtr crtc)
 261 {
 262   ScrnInfoPtr pScrn = crtc->scrn;
 263   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 264   NVPtr pNv = NVPTR(pScrn);
 265   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 266
 267   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 268   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
 269   nv_crtc->paletteEnabled = FALSE;
 270 }
 271
 272 static void NVWriteVgaReg(xf86CrtcPtr crtc, CARD32 reg, CARD8 value)
 273 {
 274  ScrnInfoPtr pScrn = crtc->scrn;
 275   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 276   NVPtr pNv = NVPTR(pScrn);
 277   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 278
 279   NV_WR08(pCRTCReg, reg, value);
 280 }
 281
 282 /* perform a sequencer reset */
 283 static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
 284 {
 285   if (start)
 286     NVWriteVgaSeq(crtc, 0x00, 0x1);
 287   else
 288     NVWriteVgaSeq(crtc, 0x00, 0x3);
 289
 290 }
 291 static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
 292 {
 293   CARD8 tmp;
 294
 295   if (on) {
 296     tmp = NVReadVgaSeq(crtc, 0x1);
 297     NVVgaSeqReset(crtc, TRUE);
 298     NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
 299
 300     NVEnablePalette(crtc);
 301   } else {
 302     /*
 303      * Reenable sequencer, then turn on screen.
 304      */
 305     tmp = NVReadVgaSeq(crtc, 0x1);
 306     NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20);     /* reenable display */
 307     NVVgaSeqReset(crtc, FALSE);
 308
 309     NVDisablePalette(crtc);
 310   }
 311 }
 312
 313 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool Lock)
 314 {
 315   CARD8 cr11;
 316
 317   NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57);
 318   cr11 = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE);
 319   if (Lock) cr11 |= 0x80;
 320   else cr11 &= ~0x80;
 321   NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE, cr11);
 322 }
 323
 324 xf86OutputPtr
 325 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
 326 {
 327         ScrnInfoPtr pScrn = crtc->scrn;
 328         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 329         int i;
 330         for (i = 0; i < xf86_config->num_output; i++) {
 331                 xf86OutputPtr output = xf86_config->output[i];
 332                 NVOutputPrivatePtr nv_output = output->driver_private;
 333
 334                 if (output->crtc == crtc) {
 335                         return output;
 336                 }
 337         }
 338 }
 339
 340 xf86CrtcPtr
 341 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
 342 {
 343         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 344         int i;
 345
 346         for (i = 0; i < xf86_config->num_crtc; i++) {
 347                 xf86CrtcPtr crtc = xf86_config->crtc[i];
 348                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 349                 if (nv_crtc->crtc == index)
 350                         return crtc;
 351         }
 352
 353         return NULL;
 354 }
 355
 356 /*
 357  * Calculate the Video Clock parameters for the PLL.
 358  */
 359 static void CalcVClock (
 360         int             clockIn,
 361         int             *clockOut,
 362         CARD32          *pllOut,
 363         NVPtr           pNv
 364 )
 365 {
 366         unsigned lowM, highM, highP;
 367         unsigned DeltaNew, DeltaOld;
 368         unsigned VClk, Freq;
 369         unsigned M, N, P;
 370
 371         /* M: PLL reference frequency postscaler divider */
 372         /* P: PLL VCO output postscaler divider */
 373         /* N: PLL VCO postscaler setting */
 374
 375         DeltaOld = 0xFFFFFFFF;
 376
 377         VClk = (unsigned)clockIn;
 378
 379         /* Taken from Haiku, after someone with an NV28 had an issue */
 380         switch(pNv->NVArch) {
 381                 case 0x28:
 382                         lowM = 1;
 383                         highP = 32;
 384                         if (VClk > 340000) {
 385                                 highM = 2;
 386                         } else if (VClk > 200000) {
 387                                 highM = 4;
 388                         } else if (VClk > 150000) {
 389                                 highM = 6;
 390                         } else {
 391                                 highM = 14;
 392                         }
 393                         break;
 394                 default:
 395                         lowM = 1;
 396                         highP = 16;
 397                         if (VClk > 340000) {
 398                                 highM = 2;
 399                         } else if (VClk > 250000) {
 400                                 highM = 6;
 401                         } else {
 402                                 highM = 14;
 403                         }
 404                         break;
 405         }
 406
 407         for (P = 0; P <= highP; P++) {
 408                 Freq = VClk << P;
 409                 if ((Freq >= 128000) && (Freq <= 350000)) {
 410                         for (M = lowM; M <= highM; M++) {
 411                                 N = ((VClk << P) * M) / pNv->CrystalFreqKHz;
 412                                 if (N <= 255) {
 413                                         Freq = ((pNv->CrystalFreqKHz * N) / M) >> P;
 414                                         if (Freq > VClk) {
 415                                                 DeltaNew = Freq - VClk;
 416                                         } else {
 417                                                 DeltaNew = VClk - Freq;
 418                                         }
 419                                         if (DeltaNew < DeltaOld) {
 420                                                 *pllOut   = (P << 16) | (N << 8) | M;
 421                                                 *clockOut = Freq;
 422                                                 DeltaOld  = DeltaNew;
 423                                         }
 424                                 }
 425                         }
 426                 }
 427         }
 428 }
 429
 430 static void CalcVClock2Stage (
 431         int             clockIn,
 432         int             *clockOut,
 433         CARD32          *pllOut,
 434         CARD32          *pllBOut,
 435         NVPtr           pNv
 436 )
 437 {
 438         unsigned DeltaNew, DeltaOld;
 439         unsigned VClk, Freq;
 440         unsigned M, N, P;
 441         unsigned lowM, highM, highP;
 442
 443         DeltaOld = 0xFFFFFFFF;
 444
 445         *pllBOut = 0x80000401;  /* fixed at x4 for now */
 446
 447         VClk = (unsigned)clockIn;
 448
 449         /* Taken from Haiku, after someone with an NV28 had an issue */
 450         switch(pNv->NVArch) {
 451                 case 0x28:
 452                         lowM = 1;
 453                         highP = 32;
 454                         if (VClk > 340000) {
 455                                 highM = 2;
 456                         } else if (VClk > 200000) {
 457                                 highM = 4;
 458                         } else if (VClk > 150000) {
 459                                 highM = 6;
 460                         } else {
 461                                 highM = 14;
 462                         }
 463                         break;
 464                 default:
 465                         lowM = 1;
 466                         highP = 16;
 467                         if (VClk > 340000) {
 468                                 highM = 2;
 469                         } else if (VClk > 250000) {
 470                                 highM = 6;
 471                         } else {
 472                                 highM = 14;
 473                         }
 474                         break;
 475         }
 476
 477         for (P = 0; P <= highP; P++) {
 478                 Freq = VClk << P;
 479                 if ((Freq >= 400000) && (Freq <= 1000000)) {
 480                         for (M = lowM; M <= highM; M++) {
 481                                 N = ((VClk << P) * M) / (pNv->CrystalFreqKHz << 2);
 482                                 if ((N >= 5) && (N <= 255)) {
 483                                         Freq = (((pNv->CrystalFreqKHz << 2) * N) / M) >> P;
 484                                         if (Freq > VClk) {
 485                                                 DeltaNew = Freq - VClk;
 486                                         } else {
 487                                                 DeltaNew = VClk - Freq;
 488                                         }
 489                                         if (DeltaNew < DeltaOld) {
 490                                                 *pllOut   = (P << 16) | (N << 8) | M;
 491                                                 *clockOut = Freq;
 492                                                 DeltaOld  = DeltaNew;
 493                                         }
 494                                 }
 495                         }
 496                 }
 497         }
 498 }
 499
 500 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 501 {
 502         state->vpll = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 503         if(pNv->twoHeads) {
 504                 state->vpll2 = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 505         }
 506         if(pNv->twoStagePLL) {
 507                 state->vpllB = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 508                 state->vpll2B = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 509         }
 510         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 511         /* This is almost a magic register */
 512         /* This seems to be strictly NV40 */
 513         if (pNv->Architecture == NV_ARCH_40) {
 514                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040 & ~(0x3 << 16));
 515                 state->reg580 = nvReadRAMDAC0(pNv, NV_RAMDAC_580);
 516                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 517         }
 518 }
 519
 520
 521 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 522 {
 523         nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 524         if (pNv->Architecture == NV_ARCH_40) {
 525                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 526         }
 527
 528         ErrorF("writing vpll %08X\n", state->vpll);
 529         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll);
 530         if(pNv->twoHeads) {
 531                 ErrorF("writing vpll2 %08X\n", state->vpll2);
 532                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2);
 533         }
 534         if(pNv->twoStagePLL) {
 535                 ErrorF("writing vpllB %08X\n", state->vpllB);
 536                 ErrorF("writing vpll2B %08X\n", state->vpll2B);
 537                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpllB);
 538                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2B);
 539         }
 540 }
 541
 542 /*
 543  * Calculate extended mode parameters (SVGA) and save in a
 544  * mode state structure.
 545  */
 546 void nv_crtc_calc_state_ext(
 547         xf86CrtcPtr     crtc,
 548         int                     bpp,
 549         int                     DisplayWidth, /* Does this change after setting the mode? */
 550         int                     CrtcHDisplay,
 551         int                     CrtcVDisplay,
 552         int                     dotClock,
 553         int                     flags
 554 )
 555 {
 556         ScrnInfoPtr pScrn = crtc->scrn;
 557         int pixelDepth, VClk;
 558         CARD32 CursorStart;
 559         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 560         xf86CrtcConfigPtr   xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 561         NVCrtcRegPtr regp;
 562         NVPtr pNv = NVPTR(pScrn);
 563         RIVA_HW_STATE *state;
 564         int num_crtc_enabled, i;
 565
 566         state = &pNv->ModeReg;
 567
 568         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 569
 570         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 571         NVOutputPrivatePtr nv_output = output->driver_private;
 572
 573         /*
 574          * Extended RIVA registers.
 575          */
 576         pixelDepth = (bpp + 1)/8;
 577         if(pNv->twoStagePLL)
 578                 CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB, pNv);
 579         else
 580                 CalcVClock(dotClock, &VClk, &state->pll, pNv);
 581
 582         switch (pNv->Architecture) {
 583         case NV_ARCH_04:
 584                 nv4UpdateArbitrationSettings(VClk,
 585                                                 pixelDepth * 8,
 586                                                 &(state->arbitration0),
 587                                                 &(state->arbitration1),
 588                                                 pNv);
 589                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
 590                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
 591                 if (flags & V_DBLSCAN)
 592                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 593                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
 594                 state->pllsel   |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
 595                 state->config   = 0x00001114;
 596                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 597                 break;
 598         case NV_ARCH_10:
 599         case NV_ARCH_20:
 600         case NV_ARCH_30:
 601         default:
 602                 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
 603                         ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
 604                         state->arbitration0 = 128;
 605                         state->arbitration1 = 0x0480;
 606                 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
 607                         ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
 608                         nForceUpdateArbitrationSettings(VClk,
 609                                                 pixelDepth * 8,
 610                                                 &(state->arbitration0),
 611                                                 &(state->arbitration1),
 612                                                 pNv);
 613                 } else if (pNv->Architecture < NV_ARCH_30) {
 614                         nv10UpdateArbitrationSettings(VClk,
 615                                                 pixelDepth * 8,
 616                                                 &(state->arbitration0),
 617                                                 &(state->arbitration1),
 618                                                 pNv);
 619                 } else {
 620                         nv30UpdateArbitrationSettings(pNv,
 621                                                 &(state->arbitration0),
 622                                                 &(state->arbitration1));
 623                 }
 624
 625                 CursorStart = pNv->Cursor->offset;
 626
 627                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
 628                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
 629                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
 630
 631                 if (flags & V_DBLSCAN)
 632                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 633
 634                 state->config   = nvReadFB(pNv, NV_PFB_CFG0);
 635                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 636                 break;
 637         }
 638
 639         /* okay do we have 2 CRTCs running ? */
 640         num_crtc_enabled = 0;
 641         for (i = 0; i < xf86_config->num_crtc; i++) {
 642                 if (xf86_config->crtc[i]->enabled) {
 643                         num_crtc_enabled++;
 644                 }
 645         }
 646
 647         ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
 648
 649         if (pNv->Architecture == NV_ARCH_40) {
 650                 /* Do not remove any present VPLL related bits, that can cause problems */
 651                 /* The meaning of this register is debatable */
 652                 state->reg580 = pNv->misc_info.ramdac_0_reg_580;
 653
 654                 /* Vclk ratio db1 is used whenever reg580 is modified for vpll activity */
 655                 if (!(pNv->misc_info.ramdac_0_pllsel & NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2)) {
 656                         if (nv_crtc->crtc == 1) {
 657                                 state->reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 658                                 state->reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 659                         } else {
 660                                 /* CRTC0 must always be active */
 661                                 state->reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 662                         }
 663                 }
 664         }
 665
 666         /* We've bound crtc's and ramdac's together */
 667         if (nv_crtc->crtc == 1) {
 668                 state->vpll2 = state->pll;
 669                 state->vpll2B = state->pllB;
 670                 if (pNv->misc_info.ramdac_0_pllsel & NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2) {
 671                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 672                 } else {
 673                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 674                 }
 675                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_CRTC1;
 676         } else {
 677                 state->vpll = state->pll;
 678                 state->vpllB = state->pllB;
 679                 if (nv_output->type == OUTPUT_LVDS)
 680                         state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
 681                 else
 682                         state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
 683                 if (pNv->misc_info.ramdac_0_pllsel & NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2) {
 684                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 685                 } else {
 686                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 687                 }
 688         }
 689
 690         regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
 691         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
 692         if (pNv->Architecture >= NV_ARCH_30) {
 693                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
 694         }
 695
 696         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
 697         regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
 698 }
 699
 700 static void
 701 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
 702 {
 703         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 704         ScrnInfoPtr pScrn = crtc->scrn;
 705         NVPtr pNv = NVPTR(pScrn);
 706         unsigned char seq1 = 0, crtc17 = 0;
 707         unsigned char crtc1A;
 708         int ret;
 709
 710         ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->crtc, mode);
 711
 712         NVCrtcSetOwner(crtc);
 713
 714         crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
 715         switch(mode) {
 716                 case DPMSModeStandby:
 717                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
 718                 seq1 = 0x20;
 719                 crtc17 = 0x80;
 720                 crtc1A |= 0x80;
 721                 break;
 722         case DPMSModeSuspend:
 723                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
 724                 seq1 = 0x20;
 725                 crtc17 = 0x80;
 726                 crtc1A |= 0x40;
 727                 break;
 728         case DPMSModeOff:
 729                 /* Screen: Off; HSync: Off, VSync: Off */
 730                 seq1 = 0x20;
 731                 crtc17 = 0x00;
 732                 crtc1A |= 0xC0;
 733                 break;
 734         case DPMSModeOn:
 735         default:
 736                 /* Screen: On; HSync: On, VSync: On */
 737                 seq1 = 0x00;
 738                 crtc17 = 0x80;
 739                 break;
 740         }
 741
 742         NVVgaSeqReset(crtc, TRUE);
 743         /* Each head has it's own sequencer, so we can turn it off when we want */
 744         seq1 |= (NVReadVgaSeq(crtc, 0x01) & ~0x20);
 745         NVWriteVgaSeq(crtc, 0x1, seq1);
 746         crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
 747         usleep(10000);
 748         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
 749         NVVgaSeqReset(crtc, FALSE);
 750
 751         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
 752
 753         /* I hope this is the right place */
 754         if (crtc->enabled && mode == DPMSModeOn) {
 755                 pNv->crtc_active[nv_crtc->head] = TRUE;
 756         } else {
 757                 pNv->crtc_active[nv_crtc->head] = FALSE;
 758         }
 759
 760 #if 0
 761         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 762         NVOutputPrivatePtr nv_output = output->driver_private;
 763         if (!nv_output->valid_ramdac & RAMDAC_1) {
 764                 /* Assumption we are ramdac 0, currently the same as the crtc */
 765                 xf86CrtcPtr crtc2 = nv_find_crtc_by_index(pScrn, 1);
 766                 xf86OutputPtr output2 = NVGetOutputFromCRTC(crtc2);
 767                 NVOutputPrivatePtr nv_output2 = output2->driver_private;
 768                 /* Let's force them to crtc 0 if we are inactive */
 769                 if (pNv->crtc_active[0]) {
 770                         if (nv_output2->valid_ramdac & RAMDAC_1)
 771                                 output2->possible_crtcs |= (1<<1);
 772                 } else {
 773                         output2->possible_crtcs &= ~(1<<1);
 774                 }
 775         }
 776 #endif
 777 }
 778
 779 static Bool
 780 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
 781                      DisplayModePtr adjusted_mode)
 782 {
 783         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 784         ScrnInfoPtr pScrn = crtc->scrn;
 785         NVPtr pNv = NVPTR(pScrn);
 786         ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->crtc);
 787
 788         return TRUE;
 789 }
 790
 791 static void
 792 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode)
 793 {
 794         ScrnInfoPtr pScrn = crtc->scrn;
 795         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 796         NVCrtcRegPtr regp;
 797         NVPtr pNv = NVPTR(pScrn);
 798         int depth = pScrn->depth;
 799         unsigned int i;
 800
 801         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 802
 803         /*
 804         * compute correct Hsync & Vsync polarity
 805         */
 806         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
 807                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
 808
 809                 regp->MiscOutReg = 0x23;
 810                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
 811                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
 812         } else {
 813                 int VDisplay = mode->VDisplay;
 814                 if (mode->Flags & V_DBLSCAN)
 815                         VDisplay *= 2;
 816                 if (mode->VScan > 1)
 817                         VDisplay *= mode->VScan;
 818                 if (VDisplay < 400) {
 819                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
 820                 } else if (VDisplay < 480) {
 821                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
 822                 } else if (VDisplay < 768) {
 823                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
 824                 } else {
 825                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
 826                 }
 827         }
 828
 829         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
 830
 831         /*
 832         * Time Sequencer
 833         */
 834         if (depth == 4) {
 835                 regp->Sequencer[0] = 0x02;
 836         } else {
 837                 regp->Sequencer[0] = 0x00;
 838         }
 839         /* 0x20 disables the sequencer */
 840         if (mode->Flags & V_CLKDIV2) {
 841                 regp->Sequencer[1] = 0x29;
 842         } else {
 843                 regp->Sequencer[1] = 0x21;
 844         }
 845         if (depth == 1) {
 846                 regp->Sequencer[2] = 1 << BIT_PLANE;
 847         } else {
 848                 regp->Sequencer[2] = 0x0F;
 849                 regp->Sequencer[3] = 0x00;                     /* Font select */
 850         }
 851         if (depth < 8) {
 852                 regp->Sequencer[4] = 0x06;                             /* Misc */
 853         } else {
 854                 regp->Sequencer[4] = 0x0E;                             /* Misc */
 855         }
 856
 857         /*
 858         * CRTC Controller
 859         */
 860         regp->CRTC[0]  = (mode->CrtcHTotal >> 3) - 5;
 861         regp->CRTC[1]  = (mode->CrtcHDisplay >> 3) - 1;
 862         regp->CRTC[2]  = (mode->CrtcHBlankStart >> 3) - 1;
 863         regp->CRTC[3]  = (((mode->CrtcHBlankEnd >> 3) - 1) & 0x1F) | 0x80;
 864         i = (((mode->CrtcHSkew << 2) + 0x10) & ~0x1F);
 865         if (i < 0x80) {
 866                 regp->CRTC[3] |= i;
 867         }
 868         regp->CRTC[4]  = (mode->CrtcHSyncStart >> 3);
 869         regp->CRTC[5]  = ((((mode->CrtcHBlankEnd >> 3) - 1) & 0x20) << 2)
 870         | (((mode->CrtcHSyncEnd >> 3)) & 0x1F);
 871         regp->CRTC[6]  = (mode->CrtcVTotal - 2) & 0xFF;
 872         regp->CRTC[7]  = (((mode->CrtcVTotal - 2) & 0x100) >> 8)
 873                         | (((mode->CrtcVDisplay - 1) & 0x100) >> 7)
 874                         | ((mode->CrtcVSyncStart & 0x100) >> 6)
 875                         | (((mode->CrtcVBlankStart - 1) & 0x100) >> 5)
 876                         | 0x10
 877                         | (((mode->CrtcVTotal - 2) & 0x200)   >> 4)
 878                         | (((mode->CrtcVDisplay - 1) & 0x200) >> 3)
 879                         | ((mode->CrtcVSyncStart & 0x200) >> 2);
 880         regp->CRTC[8]  = 0x00;
 881         regp->CRTC[9]  = (((mode->CrtcVBlankStart - 1) & 0x200) >> 4) | 0x40;
 882         if (mode->Flags & V_DBLSCAN) {
 883                 regp->CRTC[9] |= 0x80;
 884         }
 885         if (mode->VScan >= 32) {
 886                 regp->CRTC[9] |= 0x1F;
 887         } else if (mode->VScan > 1) {
 888                 regp->CRTC[9] |= mode->VScan - 1;
 889         }
 890         regp->CRTC[10] = 0x00;
 891         regp->CRTC[11] = 0x00;
 892         regp->CRTC[12] = 0x00;
 893         regp->CRTC[13] = 0x00;
 894         regp->CRTC[14] = 0x00;
 895         regp->CRTC[15] = 0x00;
 896         regp->CRTC[16] = mode->CrtcVSyncStart & 0xFF;
 897         regp->CRTC[17] = (mode->CrtcVSyncEnd & 0x0F) | 0x20;
 898         regp->CRTC[18] = (mode->CrtcVDisplay - 1) & 0xFF;
 899         regp->CRTC[19] = mode->CrtcHDisplay >> 4;  /* just a guess */
 900         regp->CRTC[20] = 0x00;
 901         regp->CRTC[21] = (mode->CrtcVBlankStart - 1) & 0xFF;
 902         regp->CRTC[22] = (mode->CrtcVBlankEnd - 1) & 0xFF;
 903         /* 0x80 enables the sequencer, we don't want that */
 904         if (depth < 8) {
 905                 regp->CRTC[23] = 0xE3 & ~0x80;
 906         } else {
 907                 regp->CRTC[23] = 0xC3 & ~0x80;
 908         }
 909         regp->CRTC[24] = 0xFF;
 910
 911         /*
 912         * Theory resumes here....
 913         */
 914
 915         /*
 916         * Graphics Display Controller
 917         */
 918         regp->Graphics[0] = 0x00;
 919         regp->Graphics[1] = 0x00;
 920         regp->Graphics[2] = 0x00;
 921         regp->Graphics[3] = 0x00;
 922         if (depth == 1) {
 923                 regp->Graphics[4] = BIT_PLANE;
 924                 regp->Graphics[5] = 0x00;
 925         } else {
 926                 regp->Graphics[4] = 0x00;
 927                 if (depth == 4) {
 928                         regp->Graphics[5] = 0x02;
 929                 } else {
 930                         regp->Graphics[5] = 0x40;
 931                 }
 932         }
 933         regp->Graphics[6] = 0x05;   /* only map 64k VGA memory !!!! */
 934         regp->Graphics[7] = 0x0F;
 935         regp->Graphics[8] = 0xFF;
 936
 937         if (depth == 1) {
 938                 /* Initialise the Mono map according to which bit-plane gets used */
 939
 940                 Bool flipPixels = xf86GetFlipPixels();
 941
 942                 for (i=0; i<16; i++) {
 943                         if (((i & (1 << BIT_PLANE)) != 0) != flipPixels) {
 944                                 regp->Attribute[i] = WHITE_VALUE;
 945                         } else {
 946                                 regp->Attribute[i] = BLACK_VALUE;
 947                         }
 948                 }
 949
 950         } else {
 951                 regp->Attribute[0]  = 0x00; /* standard colormap translation */
 952                 regp->Attribute[1]  = 0x01;
 953                 regp->Attribute[2]  = 0x02;
 954                 regp->Attribute[3]  = 0x03;
 955                 regp->Attribute[4]  = 0x04;
 956                 regp->Attribute[5]  = 0x05;
 957                 regp->Attribute[6]  = 0x06;
 958                 regp->Attribute[7]  = 0x07;
 959                 regp->Attribute[8]  = 0x08;
 960                 regp->Attribute[9]  = 0x09;
 961                 regp->Attribute[10] = 0x0A;
 962                 regp->Attribute[11] = 0x0B;
 963                 regp->Attribute[12] = 0x0C;
 964                 regp->Attribute[13] = 0x0D;
 965                 regp->Attribute[14] = 0x0E;
 966                 regp->Attribute[15] = 0x0F;
 967                 if (depth == 4) {
 968                         regp->Attribute[16] = 0x81; /* wrong for the ET4000 */
 969                 } else {
 970                         regp->Attribute[16] = 0x41; /* wrong for the ET4000 */
 971                 }
 972                 if (depth > 4) {
 973                         regp->Attribute[17] = 0xff;
 974                 }
 975                 /* Attribute[17] (overscan) initialised in vgaHWGetHWRec() */
 976         }
 977         regp->Attribute[18] = 0x0F;
 978         regp->Attribute[19] = 0x00;
 979         regp->Attribute[20] = 0x00;
 980 }
 981
 982 #define MAX_H_VALUE(i) ((0x1ff + i) << 3)
 983 #define MAX_V_VALUE(i) ((0xfff + i) << 0)
 984
 985 /**
 986  * Sets up registers for the given mode/adjusted_mode pair.
 987  *
 988  * The clocks, CRTCs and outputs attached to this CRTC must be off.
 989  *
 990  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
 991  * be easily turned on/off after this.
 992  */
 993 static void
 994 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
 995 {
 996         ScrnInfoPtr pScrn = crtc->scrn;
 997         NVPtr pNv = NVPTR(pScrn);
 998         NVRegPtr state = &pNv->ModeReg;
 999         xf86CrtcConfigPtr   xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
1000         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1001         NVFBLayout *pLayout = &pNv->CurrentLayout;
1002         NVCrtcRegPtr regp, savep;
1003         unsigned int i;
1004         uint32_t clock = adjusted_mode->Clock;
1005
1006         /* Happily borrowed from haiku driver, as an extra safety */
1007
1008         /* Make it multiples of 8 */
1009         mode->CrtcHDisplay &= ~7;
1010         mode->CrtcHSyncStart &= ~7;
1011         mode->CrtcHSyncEnd &= ~7;
1012         mode->CrtcHTotal &= ~7;
1013
1014         /* Horizontal stuff */
1015
1016         /* Time for some mode mangling */
1017         /* We only have 9 bits to store most of this information (mask 0x3f) */
1018         if (mode->CrtcHDisplay > MAX_H_VALUE(-2))
1019                 mode->CrtcHDisplay = MAX_H_VALUE(-2);
1020
1021         if (mode->CrtcHSyncStart > MAX_H_VALUE(-1))
1022                 mode->CrtcHSyncStart = MAX_H_VALUE(-1);
1023
1024         if  (mode->CrtcHSyncEnd > MAX_H_VALUE(0))
1025                 mode->CrtcHSyncEnd = MAX_H_VALUE(0);
1026
1027         if (mode->CrtcHTotal > MAX_H_VALUE(5))
1028                 mode->CrtcHTotal = MAX_H_VALUE(5);
1029
1030         /* Make room for a sync pulse if there is not enough room */
1031         if (mode->CrtcHTotal < mode->CrtcHSyncEnd + 0x50)
1032                 mode->CrtcHTotal = mode->CrtcHSyncEnd + 0x50;
1033
1034         /* Too large sync pulse? */
1035         if (mode->CrtcHTotal > mode->CrtcHSyncEnd + 0x3f8)
1036                 mode->CrtcHTotal = mode->CrtcHSyncEnd + 0x3f8;
1037
1038         /* Is the sync pulse outside the screen? */
1039         if (mode->CrtcHSyncEnd > mode->CrtcHTotal - 8)
1040                 mode->CrtcHSyncEnd = mode->CrtcHTotal - 8;
1041
1042         if (mode->CrtcHSyncStart < mode->CrtcHDisplay + 8)
1043                 mode->CrtcHSyncStart = mode->CrtcHDisplay + 8;
1044
1045         /* We've only got 5 bits to store the sync stuff */
1046         if (mode->CrtcHSyncEnd > mode->CrtcHSyncStart + (0x1f << 3))
1047                 mode->CrtcHSyncEnd = mode->CrtcHSyncStart + (0x1f << 3);
1048
1049         /* Vertical stuff */
1050
1051         /* We've only got 12 bits for this stuff */
1052         if (mode->CrtcVDisplay > MAX_V_VALUE(-2))
1053                 mode->CrtcVDisplay = MAX_V_VALUE(-2);
1054
1055         if (mode->CrtcVSyncStart > MAX_V_VALUE(-1))
1056                 mode->CrtcVSyncStart = MAX_V_VALUE(-1);
1057
1058         if  (mode->CrtcVSyncEnd > MAX_V_VALUE(0))
1059                 mode->CrtcVSyncEnd = MAX_V_VALUE(0);
1060
1061         if (mode->CrtcVTotal > MAX_V_VALUE(5))
1062                 mode->CrtcVTotal = MAX_V_VALUE(5);
1063
1064         /* Make room for a sync pulse if there is not enough room */
1065         if (mode->CrtcVTotal < mode->CrtcVSyncEnd + 0x3)
1066                 mode->CrtcVTotal = mode->CrtcVSyncEnd + 0x3;
1067
1068         /* Too large sync pulse? */
1069         if (mode->CrtcVTotal > mode->CrtcVSyncEnd + 0xff)
1070                 mode->CrtcVTotal = mode->CrtcVSyncEnd + 0xff;
1071
1072         /* Is the sync pulse outside the screen? */
1073         if (mode->CrtcVSyncEnd > mode->CrtcVTotal - 1)
1074                 mode->CrtcVSyncEnd = mode->CrtcVTotal - 1;
1075
1076         if (mode->CrtcVSyncStart < mode->CrtcVDisplay + 1)
1077                 mode->CrtcVSyncStart = mode->CrtcVDisplay + 1;
1078
1079         /* We've only got 4 bits to store the sync stuff */
1080         if (mode->CrtcVSyncEnd > mode->CrtcVSyncStart + (0x0f << 0))
1081                 mode->CrtcVSyncEnd = mode->CrtcVSyncStart + (0x0f << 0);
1082
1083         int horizDisplay        = (mode->CrtcHDisplay >> 3) - 1;
1084         int horizStart          = (mode->CrtcHSyncStart >> 3);
1085         /* The reason for this offset is completelt unknown, but important to keep analog screen alligned */
1086         int horizEnd            = (mode->CrtcHSyncEnd >> 3) + 4;
1087         int horizTotal          = (mode->CrtcHTotal >> 3) - 5;
1088         int horizBlankStart     = horizDisplay;
1089         int horizBlankEnd       = horizTotal + 4;
1090         int vertDisplay         = mode->CrtcVDisplay - 1;
1091         int vertStart           = mode->CrtcVSyncStart;
1092         int vertEnd             = mode->CrtcVSyncEnd;
1093         int vertTotal           = mode->CrtcVTotal - 2;
1094         int vertBlankStart      = vertDisplay;
1095         int vertBlankEnd        = vertTotal + 1;
1096         int lineComp            = mode->CrtcVDisplay;
1097
1098         Bool is_fp = FALSE;
1099
1100         xf86OutputPtr  output;
1101         NVOutputPrivatePtr nv_output;
1102         for (i = 0; i < xf86_config->num_output; i++) {
1103                 output = xf86_config->output[i];
1104                 nv_output = output->driver_private;
1105
1106                 if (output->crtc == crtc) {
1107                         if ((nv_output->type == OUTPUT_LVDS) ||
1108                                 (nv_output->type == OUTPUT_TMDS)) {
1109
1110                                 is_fp = TRUE;
1111                                 break;
1112                         }
1113                 }
1114         }
1115
1116         ErrorF("Mode clock: %d\n", clock);
1117
1118         ErrorF("crtc: Pre-sync workaround\n");
1119         /* Reverted to what nv did, because that works for all resolutions on flatpanels */
1120         if (is_fp) {
1121                 vertStart = vertTotal - 3;
1122                 vertEnd = vertTotal - 2;
1123                 vertBlankStart = vertStart;
1124                 horizStart = horizTotal - 5;
1125                 horizEnd = horizTotal - 2;
1126                 horizBlankEnd = horizTotal + 4;
1127                 if (pNv->overlayAdaptor) {
1128                         /* This reportedly works around Xv some overlay bandwidth problems*/
1129                         horizTotal += 2;
1130                 }
1131         }
1132         ErrorF("crtc: Post-sync workaround\n");
1133
1134         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
1135         ErrorF("horizStart: 0x%X \n", horizStart);
1136         ErrorF("horizEnd: 0x%X \n", horizEnd);
1137         ErrorF("horizTotal: 0x%X \n", horizTotal);
1138         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
1139         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
1140         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
1141         ErrorF("vertStart: 0x%X \n", vertStart);
1142         ErrorF("vertEnd: 0x%X \n", vertEnd);
1143         ErrorF("vertTotal: 0x%X \n", vertTotal);
1144         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
1145         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
1146
1147         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1148         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1149
1150         if(mode->Flags & V_INTERLACE)
1151                 vertTotal |= 1;
1152
1153         regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
1154         regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
1155         regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
1156         regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0)
1157                                 | SetBit(7);
1158         regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
1159         regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
1160                                 | SetBitField(horizEnd,4:0,4:0);
1161         regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
1162         regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
1163                                 | SetBitField(vertDisplay,8:8,1:1)
1164                                 | SetBitField(vertStart,8:8,2:2)
1165                                 | SetBitField(vertBlankStart,8:8,3:3)
1166                                 | SetBitField(lineComp,8:8,4:4)
1167                                 | SetBitField(vertTotal,9:9,5:5)
1168                                 | SetBitField(vertDisplay,9:9,6:6)
1169                                 | SetBitField(vertStart,9:9,7:7);
1170         regp->CRTC[NV_VGA_CRTCX_MAXSCLIN]  = SetBitField(vertBlankStart,9:9,5:5)
1171                                 | SetBitField(lineComp,9:9,6:6)
1172                                 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00);
1173         regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
1174         regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
1175         regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
1176         regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
1177         regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
1178         regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
1179         /* Not an extended register */
1180         regp->CRTC[NV_VGA_CRTCX_LINECOMP] = lineComp & 0xff;
1181
1182         regp->Attribute[0x10] = 0x01;
1183         /* Blob sets this for normal monitors as well */
1184         regp->Attribute[0x11] = 0x00;
1185
1186         regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
1187                                 | SetBitField(vertBlankStart,10:10,3:3)
1188                                 | SetBitField(vertStart,10:10,2:2)
1189                                 | SetBitField(vertDisplay,10:10,1:1)
1190                                 | SetBitField(vertTotal,10:10,0:0);
1191
1192         regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
1193                                 | SetBitField(horizDisplay,8:8,1:1)
1194                                 | SetBitField(horizBlankStart,8:8,2:2)
1195                                 | SetBitField(horizStart,8:8,3:3);
1196
1197         regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
1198                                 | SetBitField(vertDisplay,11:11,2:2)
1199                                 | SetBitField(vertStart,11:11,4:4)
1200                                 | SetBitField(vertBlankStart,11:11,6:6);
1201
1202         if(mode->Flags & V_INTERLACE) {
1203                 horizTotal = (horizTotal >> 1) & ~1;
1204                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
1205                 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
1206         } else {
1207                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff;  /* interlace off */
1208         }
1209
1210         /* bit2 = 0 -> fine pitched crtc granularity */
1211         /* The rest disables double buffering on CRTC access */
1212         regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfb;
1213
1214         /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1215         if (nv_crtc->head == 0) {
1216                 regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1217         }
1218
1219         if (is_fp) {
1220                 regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0) | (1 << 1);
1221         }
1222
1223         /* I'm trusting haiku driver on this one, they say it enables an external TDMS clock */
1224         if (is_fp) {
1225                 regp->CRTC[NV_VGA_CRTCX_59] = 0x1;
1226         } else {
1227                 regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1228         }
1229
1230         /*
1231         * Initialize DAC palette.
1232         */
1233         if(pLayout->bitsPerPixel != 8 ) {
1234                 for (i = 0; i < 256; i++) {
1235                         regp->DAC[i*3]     = i;
1236                         regp->DAC[(i*3)+1] = i;
1237                         regp->DAC[(i*3)+2] = i;
1238                 }
1239         }
1240
1241         /*
1242         * Calculate the extended registers.
1243         */
1244
1245         if(pLayout->depth < 24) {
1246                 i = pLayout->depth;
1247         } else {
1248                 i = 32;
1249         }
1250
1251         if(pNv->Architecture >= NV_ARCH_10) {
1252                 pNv->CURSOR = (CARD32 *)pNv->Cursor->map;
1253         }
1254
1255         ErrorF("crtc %d %d %d\n", nv_crtc->crtc, mode->CrtcHDisplay, pScrn->displayWidth);
1256         nv_crtc_calc_state_ext(crtc,
1257                                 i,
1258                                 pScrn->displayWidth,
1259                                 mode->CrtcHDisplay,
1260                                 mode->CrtcVDisplay,
1261                                 clock,
1262                                 mode->Flags);
1263
1264         /* Enable slaved mode */
1265         if (is_fp) {
1266                 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1267         }
1268
1269         /* What is the meaning of this register? */
1270         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1271         regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1];
1272
1273         /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1274         /* But what are those special conditions? */
1275         if (pNv->Architecture <= NV_ARCH_30) {
1276                 if (is_fp) {
1277                         if(nv_crtc->head == 1) {
1278                                 regp->head |= NV_CRTC_FSEL_FPP1;
1279                         } else if (pNv->twoHeads) {
1280                                 regp->head |= NV_CRTC_FSEL_FPP2;
1281                         }
1282                 }
1283         }
1284
1285         /* In some situations I2C is also enabled on head 1, even when head 1 is not used */
1286         /* Seems to be in "crosswired" tmds situations as far as i can tell (only one known case) */
1287         if (nv_crtc->head == 0) {
1288                 regp->head |= NV_CRTC_FSEL_I2C;
1289                 if (pNv->overlayAdaptor) {
1290                         regp->head |= NV_CRTC_FSEL_OVERLAY;
1291                 }
1292         }
1293
1294         regp->cursorConfig = 0x00000100;
1295         if(mode->Flags & V_DBLSCAN)
1296                 regp->cursorConfig |= (1 << 4);
1297         if(pNv->alphaCursor) {
1298                 if((pNv->Chipset & 0x0ff0) != CHIPSET_NV11) {
1299                         regp->cursorConfig |= 0x04011000;
1300                 } else {
1301                         regp->cursorConfig |= 0x14011000;
1302                 }
1303         } else {
1304                 regp->cursorConfig |= 0x02000000;
1305         }
1306
1307         /* Unblock some timings */
1308         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1309         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1310
1311         /* 0x20 seems to be enabled and 0x14 disabled */
1312         regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1313
1314         /* 0x00 is disabled, 0x22 crt and 0x88 dfp */
1315         /* 0x11 is LVDS? */
1316         if (is_fp) {
1317                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1318         } else {
1319                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1320         }
1321
1322         /* These values seem to vary */
1323         regp->CRTC[NV_VGA_CRTCX_3C] = savep->CRTC[NV_VGA_CRTCX_3C];
1324
1325         /* 0x80 seems to be used very often, if not always */
1326         regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1327
1328         /* Are these(0x55 and 0x56) also timing related registers, since disabling them does nothing? */
1329         regp->CRTC[NV_VGA_CRTCX_55] = 0x0;
1330
1331         /* Common values like 0x14 and 0x04 are converted to 0x10 and 0x00 */
1332         //regp->CRTC[NV_VGA_CRTCX_56] = savep->CRTC[NV_VGA_CRTCX_56] & ~(1<<4);
1333         regp->CRTC[NV_VGA_CRTCX_56] = 0x0;
1334
1335         regp->CRTC[NV_VGA_CRTCX_57] = 0x0;
1336
1337         /* bit0: Seems to be mostly used on crtc1 */
1338         /* bit1: 1=crtc1, 0=crtc, but i'm unsure about this */
1339         /* 0x7E (crtc0, only seen in one dump) and 0x7F (crtc1) seem to be some kind of disable setting */
1340         /* This is likely to be incomplete */
1341         /* This is a very strange register, changed very often by the blob */
1342         regp->CRTC[NV_VGA_CRTCX_58] = 0x0;
1343
1344         /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1*/
1345         if (nv_crtc->head == 1) {
1346                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52;
1347         } else {
1348                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52 + 4;
1349         }
1350
1351         /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1352         regp->unk81c = nvReadCRTC0(pNv, NV_CRTC_081C);
1353
1354         regp->unk830 = mode->CrtcVDisplay - 3;
1355         regp->unk834 = mode->CrtcVDisplay - 1;
1356
1357         /* This is what the blob does */
1358         regp->unk850 = nvReadCRTC(pNv, 0, NV_CRTC_0850);
1359
1360         /* Never ever modify gpio, unless you know very well what you're doing */
1361         regp->gpio = nvReadCRTC(pNv, 0, NV_CRTC_GPIO);
1362 }
1363
1364 /**
1365  * Sets up registers for the given mode/adjusted_mode pair.
1366  *
1367  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1368  *
1369  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1370  * be easily turned on/off after this.
1371  */
1372 static void
1373 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
1374                  DisplayModePtr adjusted_mode,
1375                  int x, int y)
1376 {
1377         ScrnInfoPtr pScrn = crtc->scrn;
1378         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1379         NVPtr pNv = NVPTR(pScrn);
1380
1381         ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->crtc);
1382
1383     xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->crtc);
1384     xf86PrintModeline(pScrn->scrnIndex, mode);
1385     NVCrtcSetOwner(crtc);
1386
1387     nv_crtc_mode_set_vga(crtc, mode);
1388     nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
1389
1390     NVVgaProtect(crtc, TRUE);
1391     nv_crtc_load_state_ext(crtc, &pNv->ModeReg);
1392     nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
1393     nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
1394
1395     NVVgaProtect(crtc, FALSE);
1396     //    NVCrtcLockUnlock(crtc, 1);
1397
1398     NVCrtcSetBase(crtc, x, y);
1399
1400 #if X_BYTE_ORDER == X_BIG_ENDIAN
1401     /* turn on LFB swapping */
1402     {
1403         unsigned char tmp;
1404
1405         tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
1406         tmp |= (1 << 7);
1407         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
1408     }
1409 #endif
1410
1411 }
1412
1413 void nv_crtc_save(xf86CrtcPtr crtc)
1414 {
1415     ScrnInfoPtr pScrn = crtc->scrn;
1416     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1417     NVPtr pNv = NVPTR(pScrn);
1418
1419         ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->crtc);
1420
1421     NVCrtcSetOwner(crtc);
1422     nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
1423     nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
1424     nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
1425 }
1426
1427 void nv_crtc_restore(xf86CrtcPtr crtc)
1428 {
1429     ScrnInfoPtr pScrn = crtc->scrn;
1430     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1431     NVPtr pNv = NVPTR(pScrn);
1432
1433         ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->crtc);
1434
1435     NVCrtcSetOwner(crtc);
1436     nv_crtc_load_state_ext(crtc, &pNv->SavedReg);
1437     nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
1438     nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
1439     nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->vtOWNER);
1440 }
1441
1442 void nv_crtc_prepare(xf86CrtcPtr crtc)
1443 {
1444         ScrnInfoPtr pScrn = crtc->scrn;
1445         NVPtr pNv = NVPTR(pScrn);
1446         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1447
1448         ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->crtc);
1449
1450         crtc->funcs->dpms(crtc, DPMSModeOff);
1451
1452         /* Sync the engine before adjust mode */
1453         if (pNv->EXADriverPtr) {
1454                 exaMarkSync(pScrn->pScreen);
1455                 exaWaitSync(pScrn->pScreen);
1456         }
1457 }
1458
1459 void nv_crtc_commit(xf86CrtcPtr crtc)
1460 {
1461         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1462         ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->crtc);
1463         ScrnInfoPtr pScrn = crtc->scrn;
1464         NVPtr pNv = NVPTR(pScrn);
1465
1466         crtc->funcs->dpms (crtc, DPMSModeOn);
1467         if (crtc->scrn->pScreen != NULL)
1468                 xf86_reload_cursors (crtc->scrn->pScreen);
1469 }
1470
1471 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
1472 {
1473         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1474         ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->crtc);
1475
1476         return FALSE;
1477 }
1478
1479 static void nv_crtc_unlock(xf86CrtcPtr crtc)
1480 {
1481         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1482         ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->crtc);
1483 }
1484
1485 /* NV04-NV10 doesn't support alpha cursors */
1486 static const xf86CrtcFuncsRec nv_crtc_funcs = {
1487         .dpms = nv_crtc_dpms,
1488         .save = nv_crtc_save, /* XXX */
1489         .restore = nv_crtc_restore, /* XXX */
1490         .mode_fixup = nv_crtc_mode_fixup,
1491         .mode_set = nv_crtc_mode_set,
1492         .prepare = nv_crtc_prepare,
1493         .commit = nv_crtc_commit,
1494         .destroy = NULL, /* XXX */
1495         .lock = nv_crtc_lock,
1496         .unlock = nv_crtc_unlock,
1497         .set_cursor_colors = nv_crtc_set_cursor_colors,
1498         .set_cursor_position = nv_crtc_set_cursor_position,
1499         .show_cursor = nv_crtc_show_cursor,
1500         .hide_cursor = nv_crtc_hide_cursor,
1501         .load_cursor_image = nv_crtc_load_cursor_image,
1502 };
1503
1504 /* NV11 and up has support for alpha cursors. */
1505 /* Due to different maximum sizes we cannot allow it to use normal cursors */
1506 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
1507         .dpms = nv_crtc_dpms,
1508         .save = nv_crtc_save, /* XXX */
1509         .restore = nv_crtc_restore, /* XXX */
1510         .mode_fixup = nv_crtc_mode_fixup,
1511         .mode_set = nv_crtc_mode_set,
1512         .prepare = nv_crtc_prepare,
1513         .commit = nv_crtc_commit,
1514         .destroy = NULL, /* XXX */
1515         .lock = nv_crtc_lock,
1516         .unlock = nv_crtc_unlock,
1517         .set_cursor_colors = nv_crtc_set_cursor_colors,
1518         .set_cursor_position = nv_crtc_set_cursor_position,
1519         .show_cursor = nv_crtc_show_cursor,
1520         .hide_cursor = nv_crtc_hide_cursor,
1521         .load_cursor_argb = nv_crtc_load_cursor_argb,
1522 };
1523
1524
1525 void
1526 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
1527 {
1528         NVPtr pNv = NVPTR(pScrn);
1529         xf86CrtcPtr crtc;
1530         NVCrtcPrivatePtr nv_crtc;
1531
1532         if (pNv->NVArch >= 0x11) {
1533                 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
1534         } else {
1535                 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
1536         }
1537         if (crtc == NULL)
1538                 return;
1539
1540         nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
1541         nv_crtc->crtc = crtc_num;
1542         nv_crtc->head = crtc_num;
1543
1544         crtc->driver_private = nv_crtc;
1545
1546         NVCrtcLockUnlock(crtc, 0);
1547 }
1548
1549 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1550 {
1551     ScrnInfoPtr pScrn = crtc->scrn;
1552     NVPtr pNv = NVPTR(pScrn);
1553     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1554     int i, j;
1555     CARD32 temp;
1556     NVCrtcRegPtr regp;
1557
1558     regp = &state->crtc_reg[nv_crtc->head];
1559
1560     NVWriteMiscOut(crtc, regp->MiscOutReg);
1561
1562     for (i = 1; i < 5; i++)
1563       NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
1564
1565     /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
1566     NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
1567
1568     for (i = 0; i < 25; i++)
1569       NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
1570
1571     for (i = 0; i < 9; i++)
1572       NVWriteVgaGr(crtc, i, regp->Graphics[i]);
1573
1574     NVEnablePalette(crtc);
1575     for (i = 0; i < 21; i++)
1576       NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
1577     NVDisablePalette(crtc);
1578
1579 }
1580
1581 static void nv_crtc_fix_nv40_hw_cursor(xf86CrtcPtr crtc)
1582 {
1583   /* TODO - implement this properly */
1584   ScrnInfoPtr pScrn = crtc->scrn;
1585   NVPtr pNv = NVPTR(pScrn);
1586
1587   if(pNv->Architecture == NV_ARCH_40) {  /* HW bug */
1588     volatile CARD32 curpos = nvReadCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS);
1589     nvWriteCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS, curpos);
1590   }
1591
1592 }
1593 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1594 {
1595     ScrnInfoPtr pScrn = crtc->scrn;
1596     NVPtr pNv = NVPTR(pScrn);
1597     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1598     int i, j;
1599     CARD32 temp;
1600     NVCrtcRegPtr regp;
1601
1602     regp = &state->crtc_reg[nv_crtc->head];
1603
1604     if(pNv->Architecture >= NV_ARCH_10) {
1605         if(pNv->twoHeads) {
1606            nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL, regp->head);
1607         }
1608         nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
1609         nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
1610         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
1611         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
1612         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1613         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1614         nvWriteMC(pNv, 0x1588, 0);
1615
1616         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, 0xff);
1617         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
1618         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
1619         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO, regp->gpio);
1620         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0830, regp->unk830);
1621         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0834, regp->unk834);
1622         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0850, regp->unk850);
1623         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_081C, regp->unk81c);
1624
1625         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
1626         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
1627
1628         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
1629         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
1630         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3C, regp->CRTC[NV_VGA_CRTCX_3C]);
1631         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
1632         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
1633         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_56, regp->CRTC[NV_VGA_CRTCX_56]);
1634         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_57, regp->CRTC[NV_VGA_CRTCX_57]);
1635         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_58, regp->CRTC[NV_VGA_CRTCX_58]);
1636         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
1637         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
1638     }
1639
1640     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
1641     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
1642     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
1643     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
1644     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
1645     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
1646     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
1647     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
1648     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
1649     if(pNv->Architecture >= NV_ARCH_30) {
1650       NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
1651     }
1652
1653     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
1654     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
1655     nv_crtc_fix_nv40_hw_cursor(crtc);
1656     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
1657     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
1658
1659     nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_EN_0, 0);
1660     nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
1661
1662     pNv->CurrentState = state;
1663 }
1664
1665 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1666 {
1667     ScrnInfoPtr pScrn = crtc->scrn;
1668     NVPtr pNv = NVPTR(pScrn);
1669     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1670     int i;
1671     NVCrtcRegPtr regp;
1672
1673     regp = &state->crtc_reg[nv_crtc->head];
1674
1675     regp->MiscOutReg = NVReadMiscOut(crtc);
1676
1677     for (i = 0; i < 25; i++)
1678         regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
1679
1680     NVEnablePalette(crtc);
1681     for (i = 0; i < 21; i++)
1682         regp->Attribute[i] = NVReadVgaAttr(crtc, i);
1683     NVDisablePalette(crtc);
1684
1685     for (i = 0; i < 9; i++)
1686         regp->Graphics[i] = NVReadVgaGr(crtc, i);
1687
1688     for (i = 1; i < 5; i++)
1689         regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
1690
1691 }
1692
1693 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1694 {
1695     ScrnInfoPtr pScrn = crtc->scrn;
1696     NVPtr pNv = NVPTR(pScrn);
1697     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1698     NVCrtcRegPtr regp;
1699     int i;
1700
1701     regp = &state->crtc_reg[nv_crtc->head];
1702
1703     regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
1704     regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
1705     regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
1706     regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
1707     regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
1708     regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
1709     regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
1710
1711     regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
1712     regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
1713     if(pNv->Architecture >= NV_ARCH_30) {
1714          regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
1715     }
1716     regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
1717     regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
1718     regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
1719     regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
1720
1721     regp->gpio = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO);
1722     regp->unk830 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0830);
1723     regp->unk834 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0834);
1724     regp->unk850 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0850);
1725     regp->unk81c = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_081C);
1726
1727     if(pNv->Architecture >= NV_ARCH_10) {
1728         if(pNv->twoHeads) {
1729            regp->head     = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL);
1730            regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
1731         }
1732         regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
1733
1734         regp->cursorConfig = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG);
1735
1736         regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
1737         regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
1738         regp->CRTC[NV_VGA_CRTCX_3C] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3C);
1739         regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
1740         regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
1741         regp->CRTC[NV_VGA_CRTCX_56] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_56);
1742         regp->CRTC[NV_VGA_CRTCX_57] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_57);
1743         regp->CRTC[NV_VGA_CRTCX_58] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_58);
1744         regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
1745         regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
1746         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
1747         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
1748     }
1749 }
1750
1751 void
1752 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y)
1753 {
1754         ScrnInfoPtr pScrn = crtc->scrn;
1755         NVPtr pNv = NVPTR(pScrn);
1756         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1757         NVFBLayout *pLayout = &pNv->CurrentLayout;
1758         CARD32 start = 0;
1759
1760         ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
1761
1762         start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
1763         start += pNv->FB->offset;
1764
1765         /* 30 bits addresses in 32 bits according to haiku */
1766         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_START, start & 0xfffffffc);
1767
1768         /* set NV4/NV10 byte adress: (bit0 - 1) */
1769         NVWriteVgaAttr(crtc, 0x13, (start & 0x3) << 1);
1770
1771         crtc->x = x;
1772         crtc->y = y;
1773 }
1774
1775 static void NVCrtcWriteDacMask(xf86CrtcPtr crtc, CARD8 value)
1776 {
1777   ScrnInfoPtr pScrn = crtc->scrn;
1778   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1779   NVPtr pNv = NVPTR(pScrn);
1780   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
1781
1782   NV_WR08(pDACReg, VGA_DAC_MASK, value);
1783 }
1784
1785 static CARD8 NVCrtcReadDacMask(xf86CrtcPtr crtc)
1786 {
1787   ScrnInfoPtr pScrn = crtc->scrn;
1788   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1789   NVPtr pNv = NVPTR(pScrn);
1790   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
1791
1792   return NV_RD08(pDACReg, VGA_DAC_MASK);
1793 }
1794
1795 static void NVCrtcWriteDacReadAddr(xf86CrtcPtr crtc, CARD8 value)
1796 {
1797   ScrnInfoPtr pScrn = crtc->scrn;
1798   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1799   NVPtr pNv = NVPTR(pScrn);
1800   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
1801
1802   NV_WR08(pDACReg, VGA_DAC_READ_ADDR, value);
1803 }
1804
1805 static void NVCrtcWriteDacWriteAddr(xf86CrtcPtr crtc, CARD8 value)
1806 {
1807   ScrnInfoPtr pScrn = crtc->scrn;
1808   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1809   NVPtr pNv = NVPTR(pScrn);
1810   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
1811
1812   NV_WR08(pDACReg, VGA_DAC_WRITE_ADDR, value);
1813 }
1814
1815 static void NVCrtcWriteDacData(xf86CrtcPtr crtc, CARD8 value)
1816 {
1817   ScrnInfoPtr pScrn = crtc->scrn;
1818   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1819   NVPtr pNv = NVPTR(pScrn);
1820   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
1821
1822   NV_WR08(pDACReg, VGA_DAC_DATA, value);
1823 }
1824
1825 static CARD8 NVCrtcReadDacData(xf86CrtcPtr crtc, CARD8 value)
1826 {
1827   ScrnInfoPtr pScrn = crtc->scrn;
1828   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1829   NVPtr pNv = NVPTR(pScrn);
1830   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
1831
1832   return NV_RD08(pDACReg, VGA_DAC_DATA);
1833 }
1834
1835 void NVCrtcLoadPalette(xf86CrtcPtr crtc)
1836 {
1837   int i;
1838   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1839   NVCrtcRegPtr regp;
1840   ScrnInfoPtr pScrn = crtc->scrn;
1841   NVPtr pNv = NVPTR(pScrn);
1842
1843   regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1844
1845   NVCrtcSetOwner(crtc);
1846   NVCrtcWriteDacMask(crtc, 0xff);
1847   NVCrtcWriteDacWriteAddr(crtc, 0x00);
1848
1849   for (i = 0; i<768; i++) {
1850     NVCrtcWriteDacData(crtc, regp->DAC[i]);
1851   }
1852   NVDisablePalette(crtc);
1853 }
1854
1855 void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
1856 {
1857     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1858     unsigned char scrn;
1859
1860     NVCrtcSetOwner(crtc);
1861
1862     scrn = NVReadVgaSeq(crtc, 0x01);
1863     if (on) {
1864         scrn &= ~0x20;
1865     } else {
1866         scrn |= 0x20;
1867     }
1868
1869     NVVgaSeqReset(crtc, TRUE);
1870     NVWriteVgaSeq(crtc, 0x01, scrn);
1871     NVVgaSeqReset(crtc, FALSE);
1872 }
1873
1874 #endif /* ENABLE_RANDR12 */
1875
1876 /*************************************************************************** \
1877 |*                                                                           *|
1878 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
1879 |*                                                                           *|
1880 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
1881 |*     international laws.  Users and possessors of this source code are     *|
1882 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
1883 |*     use this code in individual and commercial software.                  *|
1884 |*                                                                           *|
1885 |*     Any use of this source code must include,  in the user documenta-     *|
1886 |*     tion and  internal comments to the code,  notices to the end user     *|
1887 |*     as follows:                                                           *|
1888 |*                                                                           *|
1889 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
1890 |*                                                                           *|
1891 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
1892 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
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1894 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
1895 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
1896 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
1897 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
1898 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
1899 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
1900 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
1901 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
1902 |*                                                                           *|
1903 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
1904 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
1905 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
1906 |*     computer  software  documentation,"  as such  terms  are  used in     *|
1907 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
1908 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
1909 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
1910 |*     all U.S. Government End Users  acquire the source code  with only     *|
1911 |*     those rights set forth herein.                                        *|
1912 |*                                                                           *|
1913  \***************************************************************************/