git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 2006 Dave Airlie
   3  * Copyright 2007 Maarten Maathuis
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
  26  * decleration is at the bottom of this file as it is rather ugly
  27  */
  28
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include <assert.h>
  34 #include "xf86.h"
  35 #include "os.h"
  36 #include "mibank.h"
  37 #include "globals.h"
  38 #include "xf86.h"
  39 #include "xf86Priv.h"
  40 #include "xf86DDC.h"
  41 #include "mipointer.h"
  42 #include "windowstr.h"
  43 #include <randrstr.h>
  44 #include <X11/extensions/render.h>
  45
  46 #include "xf86Crtc.h"
  47 #include "nv_include.h"
  48
  49 #include "vgaHW.h"
  50
  51 #define CRTC_INDEX 0x3d4
  52 #define CRTC_DATA 0x3d5
  53 #define CRTC_IN_STAT_1 0x3da
  54
  55 #define WHITE_VALUE 0x3F
  56 #define BLACK_VALUE 0x00
  57 #define OVERSCAN_VALUE 0x01
  58
  59 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  60 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override);
  61 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  62 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  63 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  64 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  65
  66 static uint8_t NVReadPVIO(xf86CrtcPtr crtc, uint32_t address)
  67 {
  68         ScrnInfoPtr pScrn = crtc->scrn;
  69         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  70         NVPtr pNv = NVPTR(pScrn);
  71
  72         /* Only NV4x have two pvio ranges */
  73         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  74                 return NV_RD08(pNv->PVIO1, address);
  75         } else {
  76                 return NV_RD08(pNv->PVIO0, address);
  77         }
  78 }
  79
  80 static void NVWritePVIO(xf86CrtcPtr crtc, uint32_t address, uint8_t value)
  81 {
  82         ScrnInfoPtr pScrn = crtc->scrn;
  83         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  84         NVPtr pNv = NVPTR(pScrn);
  85
  86         /* Only NV4x have two pvio ranges */
  87         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  88                 NV_WR08(pNv->PVIO1, address, value);
  89         } else {
  90                 NV_WR08(pNv->PVIO0, address, value);
  91         }
  92 }
  93
  94 static void NVWriteMiscOut(xf86CrtcPtr crtc, uint8_t value)
  95 {
  96 #ifdef NOUVEAU_MODESET_TRACE
  97         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  98         ErrorF("NVWriteMiscOut: value: 0x%X head: %d\n", value, nv_crtc->head);
  99 #endif
 100         NVWritePVIO(crtc, VGA_MISC_OUT_W, value);
 101 }
 102
 103 static uint8_t NVReadMiscOut(xf86CrtcPtr crtc)
 104 {
 105         return NVReadPVIO(crtc, VGA_MISC_OUT_R);
 106 }
 107
 108 void NVWriteVGA(NVPtr pNv, int head, uint8_t index, uint8_t value)
 109 {
 110         volatile uint8_t *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 111
 112 #ifdef NOUVEAU_MODESET_TRACE
 113         ErrorF("NVWriteVGA: index: 0x%X data: 0x%X head: %d\n", index, value, head);
 114 #endif
 115
 116         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 117         NV_WR08(pCRTCReg, CRTC_DATA, value);
 118 }
 119
 120 uint8_t NVReadVGA(NVPtr pNv, int head, uint8_t index)
 121 {
 122         volatile uint8_t *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 123
 124         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 125         return NV_RD08(pCRTCReg, CRTC_DATA);
 126 }
 127
 128 /* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
 129  * I suspect they in fact do nothing, but are merely a way to carry useful
 130  * per-head variables around
 131  *
 132  * Known uses:
 133  * CR57         CR58
 134  * 0x00         index to the appropriate dcb entry (or 7f for inactive)
 135  * 0x02         dcb entry's "or" value (or 00 for inactive)
 136  * 0x03         bit0 set for dual link (LVDS, possibly elsewhere too)
 137  * 0x08 or 0x09 pxclk in MHz
 138  * 0x0f         laptop panel info -     low nibble for PEXTDEV_BOOT strap
 139  *                                      high nibble for xlat strap value
 140  */
 141
 142 void NVWriteVGACR5758(NVPtr pNv, int head, uint8_t index, uint8_t value)
 143 {
 144         NVWriteVGA(pNv, head, 0x57, index);
 145         NVWriteVGA(pNv, head, 0x58, value);
 146 }
 147
 148 uint8_t NVReadVGACR5758(NVPtr pNv, int head, uint8_t index)
 149 {
 150         NVWriteVGA(pNv, head, 0x57, index);
 151         return NVReadVGA(pNv, head, 0x58);
 152 }
 153
 154 void NVWriteVgaCrtc(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 155 {
 156         ScrnInfoPtr pScrn = crtc->scrn;
 157         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 158         NVPtr pNv = NVPTR(pScrn);
 159
 160         NVWriteVGA(pNv, nv_crtc->head, index, value);
 161 }
 162
 163 uint8_t NVReadVgaCrtc(xf86CrtcPtr crtc, uint8_t index)
 164 {
 165         ScrnInfoPtr pScrn = crtc->scrn;
 166         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 167         NVPtr pNv = NVPTR(pScrn);
 168
 169         return NVReadVGA(pNv, nv_crtc->head, index);
 170 }
 171
 172 static void NVWriteVgaSeq(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 173 {
 174 #ifdef NOUVEAU_MODESET_TRACE
 175         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 176         ErrorF("NVWriteVgaSeq: index: 0x%X value: 0x%x head %d\n", index, value, nv_crtc->head);
 177 #endif
 178         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 179         NVWritePVIO(crtc, VGA_SEQ_DATA, value);
 180 }
 181
 182 static uint8_t NVReadVgaSeq(xf86CrtcPtr crtc, uint8_t index)
 183 {
 184         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 185         return NVReadPVIO(crtc, VGA_SEQ_DATA);
 186 }
 187
 188 static void NVWriteVgaGr(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 189 {
 190 #ifdef NOUVEAU_MODESET_TRACE
 191         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 192         ErrorF("NVWriteVgaGr: index: 0x%X value: 0x%x head %d\n", index, value, nv_crtc->head);
 193 #endif
 194         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 195         NVWritePVIO(crtc, VGA_GRAPH_DATA, value);
 196 }
 197
 198 static uint8_t NVReadVgaGr(xf86CrtcPtr crtc, uint8_t index)
 199 {
 200         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 201         return NVReadPVIO(crtc, VGA_GRAPH_DATA);
 202 }
 203
 204
 205 static void NVWriteVgaAttr(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 206 {
 207         ScrnInfoPtr pScrn = crtc->scrn;
 208         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 209         NVPtr pNv = NVPTR(pScrn);
 210         volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 211
 212         NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 213         if (nv_crtc->paletteEnabled)
 214                 index &= ~0x20;
 215         else
 216                 index |= 0x20;
 217 #ifdef NOUVEAU_MODESET_TRACE
 218         ErrorF("NVWriteVgaAttr: index: 0x%X value: 0x%X head: %d\n", index, value, nv_crtc->head);
 219 #endif
 220         NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 221         NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
 222 }
 223
 224 static uint8_t NVReadVgaAttr(xf86CrtcPtr crtc, uint8_t index)
 225 {
 226   ScrnInfoPtr pScrn = crtc->scrn;
 227   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 228   NVPtr pNv = NVPTR(pScrn);
 229   volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 230
 231   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 232   if (nv_crtc->paletteEnabled)
 233     index &= ~0x20;
 234   else
 235     index |= 0x20;
 236   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 237   return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
 238 }
 239
 240 static void NVCrtcSetOwner(xf86CrtcPtr crtc)
 241 {
 242         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 243         ScrnInfoPtr pScrn = crtc->scrn;
 244         NVPtr pNv = NVPTR(pScrn);
 245         /* Non standard beheaviour required by NV11 */
 246         if (pNv) {
 247                 uint8_t owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 248                 ErrorF("pre-Owner: 0x%X\n", owner);
 249                 if (owner == 0x04) {
 250                         uint32_t pbus84 = nvReadMC(pNv, 0x1084);
 251                         ErrorF("pbus84: 0x%X\n", pbus84);
 252                         pbus84 &= ~(1<<28);
 253                         ErrorF("pbus84: 0x%X\n", pbus84);
 254                         nvWriteMC(pNv, 0x1084, pbus84);
 255                 }
 256                 /* The blob never writes owner to pcio1, so should we */
 257                 if (pNv->NVArch == 0x11) {
 258                         NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, 0xff);
 259                 }
 260                 NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, nv_crtc->head * 0x3);
 261                 owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 262                 ErrorF("post-Owner: 0x%X\n", owner);
 263         } else {
 264                 ErrorF("pNv pointer is NULL\n");
 265         }
 266 }
 267
 268 static void
 269 NVEnablePalette(xf86CrtcPtr crtc)
 270 {
 271   ScrnInfoPtr pScrn = crtc->scrn;
 272   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 273   NVPtr pNv = NVPTR(pScrn);
 274   volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 275
 276   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 277   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
 278   nv_crtc->paletteEnabled = TRUE;
 279 }
 280
 281 static void
 282 NVDisablePalette(xf86CrtcPtr crtc)
 283 {
 284   ScrnInfoPtr pScrn = crtc->scrn;
 285   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 286   NVPtr pNv = NVPTR(pScrn);
 287   volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 288
 289   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 290   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
 291   nv_crtc->paletteEnabled = FALSE;
 292 }
 293
 294 static void NVWriteVgaReg(xf86CrtcPtr crtc, uint32_t reg, uint8_t value)
 295 {
 296  ScrnInfoPtr pScrn = crtc->scrn;
 297   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 298   NVPtr pNv = NVPTR(pScrn);
 299   volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 300
 301   NV_WR08(pCRTCReg, reg, value);
 302 }
 303
 304 /* perform a sequencer reset */
 305 static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
 306 {
 307   if (start)
 308     NVWriteVgaSeq(crtc, 0x00, 0x1);
 309   else
 310     NVWriteVgaSeq(crtc, 0x00, 0x3);
 311
 312 }
 313 static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
 314 {
 315         uint8_t tmp;
 316
 317         if (on) {
 318                 tmp = NVReadVgaSeq(crtc, 0x1);
 319                 NVVgaSeqReset(crtc, TRUE);
 320                 NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
 321
 322                 NVEnablePalette(crtc);
 323         } else {
 324                 /*
 325                  * Reenable sequencer, then turn on screen.
 326                  */
 327                 tmp = NVReadVgaSeq(crtc, 0x1);
 328                 NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20); /* reenable display */
 329                 NVVgaSeqReset(crtc, FALSE);
 330
 331                 NVDisablePalette(crtc);
 332         }
 333 }
 334
 335 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool Lock)
 336 {
 337         NVPtr pNv = NVPTR(crtc->scrn);
 338         uint8_t cr11;
 339
 340         if (pNv->twoHeads)
 341                 NVCrtcSetOwner(crtc);
 342
 343         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57);
 344         cr11 = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE);
 345         if (Lock) cr11 |= 0x80;
 346         else cr11 &= ~0x80;
 347         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE, cr11);
 348 }
 349
 350 xf86OutputPtr
 351 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
 352 {
 353         ScrnInfoPtr pScrn = crtc->scrn;
 354         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 355         int i;
 356         for (i = 0; i < xf86_config->num_output; i++) {
 357                 xf86OutputPtr output = xf86_config->output[i];
 358
 359                 if (output->crtc == crtc) {
 360                         return output;
 361                 }
 362         }
 363
 364         return NULL;
 365 }
 366
 367 xf86CrtcPtr
 368 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
 369 {
 370         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 371         int i;
 372
 373         for (i = 0; i < xf86_config->num_crtc; i++) {
 374                 xf86CrtcPtr crtc = xf86_config->crtc[i];
 375                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 376                 if (nv_crtc->head == index)
 377                         return crtc;
 378         }
 379
 380         return NULL;
 381 }
 382
 383 /*
 384  * Calculate the Video Clock parameters for the PLL.
 385  */
 386 /* Code taken from NVClock, with permission of the author (being a GPL->MIT code transfer). */
 387
 388 static void
 389 CalculateVClkNV4x_SingleVCO(NVPtr pNv, struct pll_lims *pll_lim, uint32_t clockIn, uint32_t *n1_best, uint32_t *m1_best, uint32_t *p_best)
 390 {
 391         uint32_t clock, M, N, P;
 392         uint32_t delta, bestDelta, minM, maxM, minN, maxN, maxP;
 393         uint32_t minVCOInputFreq, minVCOFreq, maxVCOFreq;
 394         uint32_t VCOFreq;
 395         uint32_t refClk = pNv->CrystalFreqKHz;
 396         bestDelta = clockIn;
 397
 398         minVCOInputFreq = pll_lim->vco1.min_inputfreq;
 399         minVCOFreq = pll_lim->vco1.minfreq;
 400         maxVCOFreq = pll_lim->vco1.maxfreq;
 401         minM = pll_lim->vco1.min_m;
 402         maxM = pll_lim->vco1.max_m;
 403         minN = pll_lim->vco1.min_n;
 404         maxN = pll_lim->vco1.max_n;
 405
 406         maxP = 6;
 407
 408         /* The optimal frequency for the PLL to work at is somewhere in the center of its range.
 409         /  Choose a post divider in such a way to achieve this.
 410         /  The G8x nv driver does something similar but they they derive a minP and maxP. That
 411         /  doesn't seem required as you get so many matching clocks that you don't enter a second
 412         /  iteration for P. (The minP / maxP values in the nv driver only differ at most 1, so it is for
 413         /  some rare corner cases.
 414         */
 415         for (P=0, VCOFreq=maxVCOFreq/2; clockIn<=VCOFreq && P <= maxP; P++)
 416         {
 417                 VCOFreq /= 2;
 418         }
 419
 420         /* Calculate the m and n values. There are a lot of values which give the same speed;
 421         /  We choose the speed for which the difference with the request speed is as small as possible.
 422         */
 423         for (M=minM; M<=maxM; M++)
 424         {
 425                 /* The VCO has a minimum input frequency */
 426                 if ((refClk/M) < minVCOInputFreq)
 427                         break;
 428
 429                 for (N=minN; N<=maxN; N++)
 430                 {
 431                         /* Calculate the frequency generated by VCO1 */
 432                         clock = (int)(refClk * N / (float)M);
 433
 434                         /* Verify if the clock lies within the output limits of VCO1 */
 435                         if (clock < minVCOFreq)
 436                                 continue;
 437                         else if (clock > maxVCOFreq) /* It is no use to continue as the clock will only become higher */
 438                                 break;
 439
 440                         clock >>= P;
 441                         delta = abs((int)(clockIn - clock));
 442                         /* When the difference is 0 or less than .5% accept the speed */
 443                         if (((delta == 0) || ((float)delta/(float)clockIn <= 0.005)))
 444                         {
 445                                 *m1_best = M;
 446                                 *n1_best = N;
 447                                 *p_best = P;
 448                                 return;
 449                         }
 450
 451                         /* When the new difference is smaller than the old one, use this one */
 452                         if (delta < bestDelta)
 453                         {
 454                                 bestDelta = delta;
 455                                 *m1_best = M;
 456                                 *n1_best = N;
 457                                 *p_best = P;
 458                         }
 459                 }
 460         }
 461 }
 462
 463 static void
 464 CalculateVClkNV4x_DoubleVCO(NVPtr pNv, struct pll_lims *pll_lim, uint32_t clockIn, uint32_t *n1_best, uint32_t *n2_best, uint32_t *m1_best, uint32_t *m2_best, uint32_t *p_best)
 465 {
 466         uint32_t clock1, clock2, M, M2, N, N2, P;
 467         uint32_t delta, bestDelta, minM, minM2, maxM, maxM2, minN, minN2, maxN, maxN2, maxP;
 468         uint32_t minVCOInputFreq, minVCO2InputFreq, maxVCO2InputFreq, minVCOFreq, minVCO2Freq, maxVCOFreq, maxVCO2Freq;
 469         uint32_t VCO2Freq, maxClock;
 470         uint32_t refClk = pNv->CrystalFreqKHz;
 471         bestDelta = clockIn;
 472
 473         minVCOInputFreq = pll_lim->vco1.min_inputfreq;
 474         minVCOFreq = pll_lim->vco1.minfreq;
 475         maxVCOFreq = pll_lim->vco1.maxfreq;
 476         minM = pll_lim->vco1.min_m;
 477         maxM = pll_lim->vco1.max_m;
 478         minN = pll_lim->vco1.min_n;
 479         maxN = pll_lim->vco1.max_n;
 480
 481         minVCO2InputFreq = pll_lim->vco2.min_inputfreq;
 482         maxVCO2InputFreq = pll_lim->vco2.max_inputfreq;
 483         minVCO2Freq = pll_lim->vco2.minfreq;
 484         maxVCO2Freq = pll_lim->vco2.maxfreq;
 485         minM2 = pll_lim->vco2.min_m;
 486         maxM2 = pll_lim->vco2.max_m;
 487         minN2 = pll_lim->vco2.min_n;
 488         maxN2 = pll_lim->vco2.max_n;
 489
 490         maxP = 6;
 491
 492         maxClock = maxVCO2Freq;
 493         /* If the requested clock is behind the bios limits, try it anyway */
 494         if (clockIn > maxVCO2Freq)
 495                 maxClock = clockIn + clockIn/200; /* Add a .5% margin */
 496
 497         /* The optimal frequency for the PLL to work at is somewhere in the center of its range.
 498         /  Choose a post divider in such a way to achieve this.
 499         /  The G8x nv driver does something similar but they they derive a minP and maxP. That
 500         /  doesn't seem required as you get so many matching clocks that you don't enter a second
 501         /  iteration for P. (The minP / maxP values in the nv driver only differ at most 1, so it is for
 502         /  some rare corner cases.
 503         */
 504         for (P=0, VCO2Freq=maxClock/2; clockIn<=VCO2Freq && P <= maxP; P++)
 505         {
 506                 VCO2Freq /= 2;
 507         }
 508
 509         /* The PLLs on Geforce6/7 hardware can operate in a single stage made with only 1 VCO
 510         /  and a cascade mode of two VCOs. This second mode is in general used for relatively high
 511         /  frequencies. The loop below calculates the divider and multiplier ratios for the cascade
 512         /  mode. The code takes into account limits defined in the video bios.
 513         */
 514         for (M=minM; M<=maxM; M++)
 515         {
 516                 /* The VCO has a minimum input frequency */
 517                 if ((refClk/M) < minVCOInputFreq)
 518                         break;
 519
 520                 for (N=minN; N<=maxN; N++)
 521                 {
 522                         /* Calculate the frequency generated by VCO1 */
 523                         clock1 = (int)(refClk * N / (float)M);
 524                         /* Verify if the clock lies within the output limits of VCO1 */
 525                         if ( (clock1 < minVCOFreq) )
 526                                 continue;
 527                         else if (clock1 > maxVCOFreq) /* For future N, the clock will only increase so stop; xorg nv continues but that is useless */
 528                                 break;
 529
 530                         for (M2=minM2; M2<=maxM2; M2++)
 531                         {
 532                                 /* The clock fed to the second VCO needs to lie within a certain input range */
 533                                 if (clock1 / M2 < minVCO2InputFreq)
 534                                         break;
 535                                 else if (clock1 / M2 > maxVCO2InputFreq)
 536                                         continue;
 537
 538                                 N2 = (int)((float)((clockIn << P) * M * M2) / (float)(refClk * N)+.5);
 539                                 if( (N2 < minN2) || (N2 > maxN2) )
 540                                         continue;
 541
 542                                 /* The clock before being fed to the post-divider needs to lie within a certain range.
 543                                 /  Further there are some limits on N2/M2.
 544                                 */
 545                                 clock2 = (int)((float)(N*N2)/(M*M2) * refClk);
 546                                 if( (clock2 < minVCO2Freq) || (clock2 > maxClock))// || ((N2 / M2) < 4) || ((N2 / M2) > 10) )
 547                                         continue;
 548
 549                                 /* The post-divider delays the 'high' clock to create a low clock if requested.
 550                                 /  This post-divider exists because the VCOs can only generate frequencies within
 551                                 /  a limited frequency range. This range has been tuned to lie around half of its max
 552                                 /  input frequency. It tries to calculate all clocks (including lower ones) around this
 553                                 /  'center' frequency.
 554                                 */
 555                                 clock2 >>= P;
 556                                 delta = abs((int)(clockIn - clock2));
 557
 558                                 /* When the difference is 0 or less than .5% accept the speed */
 559                                 if (((delta == 0) || ((float)delta/(float)clockIn <= 0.005)))
 560                                 {
 561                                         *m1_best = M;
 562                                         *m2_best = M2;
 563                                         *n1_best = N;
 564                                         *n2_best = N2;
 565                                         *p_best = P;
 566                                         return;
 567                                 }
 568
 569                                 /* When the new difference is smaller than the old one, use this one */
 570                                 if (delta < bestDelta)
 571                                 {
 572                                         bestDelta = delta;
 573                                         *m1_best = M;
 574                                         *m2_best = M2;
 575                                         *n1_best = N;
 576                                         *n2_best = N2;
 577                                         *p_best = P;
 578                                 }
 579                         }
 580                 }
 581         }
 582 }
 583
 584 /* BIG NOTE: modifying vpll1 and vpll2 does not work, what bit is the switch to allow it? */
 585
 586 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
 587 /* They are only valid for NV4x, appearantly reordered for NV5x */
 588 /* gpu pll: 0x4000 + 0x4004
 589  * unknown pll: 0x4008 + 0x400c
 590  * vpll1: 0x4010 + 0x4014
 591  * vpll2: 0x4018 + 0x401c
 592  * unknown pll: 0x4020 + 0x4024
 593  * unknown pll: 0x4038 + 0x403c
 594  * Some of the unknown's are probably memory pll's.
 595  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
 596  * 1 and 2 refer to the registers of each pair. There is only one post divider.
 597  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
 598  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
 599  *     bit8: A switch that turns of the second divider and multiplier off.
 600  *     bit12: Also a switch, i haven't seen it yet.
 601  *     bit16-19: p-divider
 602  *     but 28-31: Something related to the mode that is used (see bit8).
 603  * 2) bit0-7: m-divider (a)
 604  *     bit8-15: n-multiplier (a)
 605  *     bit16-23: m-divider (b)
 606  *     bit24-31: n-multiplier (b)
 607  */
 608
 609 /* Modifying the gpu pll for example requires:
 610  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 611  * This is not needed for the vpll's which have their own bits.
 612  */
 613
 614 static void
 615 CalculateVClkNV4x(
 616         ScrnInfoPtr pScrn,
 617         uint32_t requested_clock,
 618         uint32_t *given_clock,
 619         uint32_t *pll_a,
 620         uint32_t *pll_b,
 621         uint32_t *reg580,
 622         Bool    *db1_ratio,
 623         Bool primary
 624 )
 625 {
 626         NVPtr pNv = NVPTR(pScrn);
 627         uint32_t pll_lim_reg;
 628         struct pll_lims pll_lim;
 629         /* We have 2 mulitpliers, 2 dividers and one post divider */
 630         /* Note that p is only 3 bits */
 631         uint32_t m1_best = 0, m2_best = 0, n1_best = 0, n2_best = 0, p_best = 0;
 632         uint32_t special_bits = 0;
 633
 634         if (primary) {
 635                 if (!get_pll_limits_reg(pScrn, VPLL1, &pll_lim_reg))
 636                         return;
 637         } else
 638                 if (!get_pll_limits_reg(pScrn, VPLL2, &pll_lim_reg))
 639                         return;
 640
 641         get_pll_limits(pScrn, pll_lim_reg, &pll_lim);
 642
 643         if (requested_clock < pll_lim.vco1.maxfreq && pNv->NVArch > 0x40) { /* single VCO */
 644                 *db1_ratio = TRUE;
 645                 /* Turn the second set of divider and multiplier off */
 646                 /* Bogus data, the same nvidia uses */
 647                 n2_best = 1;
 648                 m2_best = 31;
 649                 CalculateVClkNV4x_SingleVCO(pNv, &pll_lim, requested_clock, &n1_best, &m1_best, &p_best);
 650         } else { /* dual VCO */
 651                 *db1_ratio = FALSE;
 652                 CalculateVClkNV4x_DoubleVCO(pNv, &pll_lim, requested_clock, &n1_best, &n2_best, &m1_best, &m2_best, &p_best);
 653         }
 654
 655         /* Are this all (relevant) G70 cards? */
 656         if (pNv->NVArch == 0x4B || pNv->NVArch == 0x46 || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
 657                 /* This is a big guess, but should be reasonable until we can narrow it down. */
 658                 if (*db1_ratio) {
 659                         special_bits = 0x1;
 660                 } else {
 661                         special_bits = 0x3;
 662                 }
 663         }
 664
 665         /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
 666         *pll_a = (special_bits << 30) | (p_best << 16) | (n1_best << 8) | (m1_best << 0);
 667         /* This VCO2 bit is an educated guess, but it needs to stay on for NV4x. */
 668         *pll_b = NV31_RAMDAC_ENABLE_VCO2 | (n2_best << 8) | (m2_best << 0);
 669
 670         if (*db1_ratio) {
 671                 if (primary) {
 672                         *reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 673                 } else {
 674                         *reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 675                 }
 676         } else {
 677                 if (primary) {
 678                         *reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
 679                 } else {
 680                         *reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
 681                 }
 682         }
 683
 684         if (*db1_ratio) {
 685                 ErrorF("vpll: n1 %d m1 %d p %d db1_ratio %d\n", n1_best, m1_best, p_best, *db1_ratio);
 686         } else {
 687                 ErrorF("vpll: n1 %d n2 %d m1 %d m2 %d p %d db1_ratio %d\n", n1_best, n2_best, m1_best, m2_best, p_best, *db1_ratio);
 688         }
 689 }
 690
 691 static void nv40_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 692 {
 693         state->vpll1_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 694         state->vpll1_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 695         state->vpll2_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 696         state->vpll2_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 697         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 698         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 699         state->reg580 = nvReadRAMDAC0(pNv, NV_RAMDAC_580);
 700         state->reg594 = nvReadRAMDAC0(pNv, NV_RAMDAC_594);
 701 }
 702
 703 static void nv40_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 704 {
 705         ScrnInfoPtr pScrn = crtc->scrn;
 706         NVPtr pNv = NVPTR(pScrn);
 707         uint32_t fp_debug_0[2];
 708         uint32_t index[2];
 709         fp_debug_0[0] = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
 710         fp_debug_0[1] = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
 711
 712         /* The TMDS_PLL switch is on the actual ramdac */
 713         if (state->crosswired) {
 714                 index[0] = 1;
 715                 index[1] = 0;
 716                 ErrorF("Crosswired pll state load\n");
 717         } else {
 718                 index[0] = 0;
 719                 index[1] = 1;
 720         }
 721
 722         if (state->vpll2_b && state->vpll_changed[1]) {
 723                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0,
 724                         fp_debug_0[index[1]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 725
 726                 /* Wait for the situation to stabilise */
 727                 usleep(5000);
 728
 729                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 730                 /* for vpll2 change bits 18 and 19 are disabled */
 731                 reg_c040 &= ~(0x3 << 18);
 732                 nvWriteMC(pNv, 0xc040, reg_c040);
 733
 734                 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 735                 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 736
 737                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2_a);
 738                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 739
 740                 ErrorF("writing pllsel %08X\n", state->pllsel);
 741                 /* Don't turn vpll1 off. */
 742                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 743
 744                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 745                 ErrorF("writing reg580 %08X\n", state->reg580);
 746
 747                 /* We need to wait a while */
 748                 usleep(5000);
 749                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 750
 751                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[1]]);
 752
 753                 /* Wait for the situation to stabilise */
 754                 usleep(5000);
 755         }
 756
 757         if (state->vpll1_b && state->vpll_changed[0]) {
 758                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0,
 759                         fp_debug_0[index[0]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 760
 761                 /* Wait for the situation to stabilise */
 762                 usleep(5000);
 763
 764                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 765                 /* for vpll2 change bits 16 and 17 are disabled */
 766                 reg_c040 &= ~(0x3 << 16);
 767                 nvWriteMC(pNv, 0xc040, reg_c040);
 768
 769                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 770                 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 771
 772                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll1_a);
 773                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpll1_b);
 774
 775                 ErrorF("writing pllsel %08X\n", state->pllsel);
 776                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 777
 778                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 779                 ErrorF("writing reg580 %08X\n", state->reg580);
 780
 781                 /* We need to wait a while */
 782                 usleep(5000);
 783                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 784
 785                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[0]]);
 786
 787                 /* Wait for the situation to stabilise */
 788                 usleep(5000);
 789         }
 790
 791         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 792         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 793
 794         ErrorF("writing reg594 %08X\n", state->reg594);
 795         nvWriteRAMDAC0(pNv, NV_RAMDAC_594, state->reg594);
 796
 797         /* All clocks have been set at this point. */
 798         state->vpll_changed[0] = FALSE;
 799         state->vpll_changed[1] = FALSE;
 800 }
 801
 802 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 803 {
 804         state->vpll1_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 805         if (pNv->twoHeads) {
 806                 state->vpll2_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 807         }
 808         if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 809                 state->vpll1_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 810                 state->vpll2_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 811         }
 812         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 813         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 814 }
 815
 816
 817 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 818 {
 819         /* This sequence is important, the NV28 is very sensitive in this area. */
 820         /* Keep pllsel last and sel_clk first. */
 821         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 822         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 823
 824         if (state->vpll2_a && state->vpll_changed[1]) {
 825                 if (pNv->twoHeads) {
 826                         ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 827                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2_a);
 828                 }
 829                 if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 830                         ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 831                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 832                 }
 833         }
 834
 835         if (state->vpll1_a && state->vpll_changed[0]) {
 836                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 837                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll1_a);
 838                 if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 839                         ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 840                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpll1_b);
 841                 }
 842         }
 843
 844         ErrorF("writing pllsel %08X\n", state->pllsel);
 845         nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 846
 847         /* All clocks have been set at this point. */
 848         state->vpll_changed[0] = FALSE;
 849         state->vpll_changed[1] = FALSE;
 850 }
 851
 852 #define IS_NV44P (pNv->NVArch >= 0x44 ? 1 : 0)
 853 #define SEL_CLK_OFFSET (nv_get_sel_clk_offset(pNv->NVArch, nv_output->bus))
 854
 855 #define WIPE_OTHER_CLOCKS(_sel_clk, _head, _bus) (nv_wipe_other_clocks(_sel_clk, pNv->NVArch, _head, _bus))
 856
 857 /*
 858  * Calculate extended mode parameters (SVGA) and save in a
 859  * mode state structure.
 860  * State is not specific to a single crtc, but shared.
 861  */
 862 void nv_crtc_calc_state_ext(
 863         xf86CrtcPtr             crtc,
 864         DisplayModePtr  mode,
 865         int                             bpp,
 866         int                             DisplayWidth, /* Does this change after setting the mode? */
 867         int                             CrtcHDisplay,
 868         int                             CrtcVDisplay,
 869         int                             dotClock,
 870         int                             flags
 871 )
 872 {
 873         ScrnInfoPtr pScrn = crtc->scrn;
 874         uint32_t pixelDepth, VClk = 0;
 875         uint32_t CursorStart;
 876         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 877         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 878         NVCrtcRegPtr regp;
 879         NVPtr pNv = NVPTR(pScrn);
 880         RIVA_HW_STATE *state;
 881         int num_crtc_enabled, i;
 882         uint32_t old_clock_a = 0, old_clock_b = 0;
 883
 884         state = &pNv->ModeReg;
 885
 886         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 887
 888         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 889         NVOutputPrivatePtr nv_output = NULL;
 890         Bool is_fp = FALSE;
 891         if (output) {
 892                 nv_output = output->driver_private;
 893                 if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)
 894                         is_fp = TRUE;
 895         }
 896
 897         /* Store old clock. */
 898         if (nv_crtc->head == 1) {
 899                 old_clock_a = state->vpll2_a;
 900                 old_clock_b = state->vpll2_b;
 901         } else {
 902                 old_clock_a = state->vpll1_a;
 903                 old_clock_b = state->vpll1_b;
 904         }
 905
 906         /*
 907          * Extended RIVA registers.
 908          */
 909         /* This is pitch related, not mode related. */
 910         pixelDepth = (bpp + 1)/8;
 911         if (pNv->Architecture == NV_ARCH_40) {
 912                 /* Does register 0x580 already have a value? */
 913                 if (!state->reg580) {
 914                         state->reg580 = pNv->misc_info.ramdac_0_reg_580;
 915                 }
 916                 if (nv_crtc->head == 1) {
 917                         CalculateVClkNV4x(pScrn, dotClock, &VClk, &state->vpll2_a, &state->vpll2_b, &state->reg580, &state->db1_ratio[1], FALSE);
 918                 } else {
 919                         CalculateVClkNV4x(pScrn, dotClock, &VClk, &state->vpll1_a, &state->vpll1_b, &state->reg580, &state->db1_ratio[0], TRUE);
 920                 }
 921         } else if (pNv->twoStagePLL) {
 922                 int NM1, NM2, log2P;
 923                 VClk = getMNP_double(pScrn, 0, dotClock, &NM1, &NM2, &log2P);
 924                 if (pNv->NVArch == 0x30) {
 925                         /* See nvregisters.xml for details. */
 926                         state->pll = log2P << 16 | NM1 | (NM2 & 7) << 4 | ((NM2 >> 8) & 7) << 19 | ((NM2 >> 11) & 3) << 24 | NV30_RAMDAC_ENABLE_VCO2;
 927                 } else {
 928                         state->pll = log2P << 16 | NM1;
 929                         state->pllB = NV31_RAMDAC_ENABLE_VCO2 | NM2;
 930                 }
 931         } else {
 932                 int NM, log2P;
 933                 VClk = getMNP_single(pScrn, 0, dotClock, &NM, &log2P);
 934                 state->pll = log2P << 16 | NM;
 935         }
 936
 937         if (pNv->Architecture < NV_ARCH_40) {
 938                 if (nv_crtc->head == 1) {
 939                         state->vpll2_a = state->pll;
 940                         state->vpll2_b = state->pllB;
 941                 } else {
 942                         state->vpll1_a = state->pll;
 943                         state->vpll1_b = state->pllB;
 944                 }
 945         }
 946
 947         /* always reset vpll, just to be sure. */
 948         state->vpll_changed[nv_crtc->head] = TRUE;
 949
 950         switch (pNv->Architecture) {
 951         case NV_ARCH_04:
 952                 nv4UpdateArbitrationSettings(VClk,
 953                                                 pixelDepth * 8,
 954                                                 &(state->arbitration0),
 955                                                 &(state->arbitration1),
 956                                                 pNv);
 957                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
 958                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
 959                 if (flags & V_DBLSCAN)
 960                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 961                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
 962                 state->pllsel   |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
 963                 state->config   = 0x00001114;
 964                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 965                 break;
 966         case NV_ARCH_10:
 967         case NV_ARCH_20:
 968         case NV_ARCH_30:
 969         default:
 970                 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
 971                         ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
 972                         state->arbitration0 = 128;
 973                         state->arbitration1 = 0x0480;
 974                 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
 975                         ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
 976                         nForceUpdateArbitrationSettings(VClk,
 977                                                 pixelDepth * 8,
 978                                                 &(state->arbitration0),
 979                                                 &(state->arbitration1),
 980                                                 pNv);
 981                 } else if (pNv->Architecture < NV_ARCH_30) {
 982                         nv10UpdateArbitrationSettings(VClk,
 983                                                 pixelDepth * 8,
 984                                                 &(state->arbitration0),
 985                                                 &(state->arbitration1),
 986                                                 pNv);
 987                 } else {
 988                         nv30UpdateArbitrationSettings(pNv,
 989                                                 &(state->arbitration0),
 990                                                 &(state->arbitration1));
 991                 }
 992
 993                 if (nv_crtc->head == 1) {
 994                         CursorStart = pNv->Cursor2->offset;
 995                 } else {
 996                         CursorStart = pNv->Cursor->offset;
 997                 }
 998
 999                 if (!NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1000                         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
1001                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
1002                         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
1003                 } else {
1004                         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x0;
1005                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0x0;
1006                         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x0;
1007                 }
1008
1009                 if (flags & V_DBLSCAN)
1010                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
1011
1012                 state->config   = nvReadFB(pNv, NV_PFB_CFG0);
1013                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
1014                 break;
1015         }
1016
1017         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1018                 /* This is a bit of a guess. */
1019                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] |= 0xB8;
1020         }
1021
1022         /* okay do we have 2 CRTCs running ? */
1023         num_crtc_enabled = 0;
1024         for (i = 0; i < xf86_config->num_crtc; i++) {
1025                 if (xf86_config->crtc[i]->enabled) {
1026                         num_crtc_enabled++;
1027                 }
1028         }
1029
1030         ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
1031
1032         /* The main stuff seems to be valid for NV3x also. */
1033         if (pNv->Architecture >= NV_ARCH_30) {
1034                 /* This register is only used on the primary ramdac */
1035                 /* This seems to be needed to select the proper clocks, otherwise bad things happen */
1036
1037                 if (!state->sel_clk)
1038                         state->sel_clk = pNv->misc_info.sel_clk & ~(0xf << 16);
1039
1040                 if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1041                         if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
1042                                 /* bioses are very conservative with regards to sel_clk. */
1043                                 /* At this stage we expect a clean sel_clk value. */
1044                                 if (nv_crtc->head == 1) {
1045                                         if (nv_output->preferred_output == 1) {
1046                                                 state->sel_clk |= (0x4 << 16);
1047                                         } else {
1048                                                 state->sel_clk |= (0x1 << 16);
1049                                         }
1050                                 }
1051                         }
1052                 } else {
1053                         if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
1054                                 /* Only wipe when are a relevant (digital) output. */
1055                                 state->sel_clk &= ~(0xf << 16);
1056                                 Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1057                                 /* Even with two dvi, this should not conflict. */
1058                                 if (crossed_clocks) {
1059                                         state->sel_clk |= (0x1 << 16);
1060                                 } else {
1061                                         state->sel_clk |= (0x4 << 16);
1062                                 }
1063                         }
1064
1065                         /* Some cards, specifically dual dvi/lvds cards set another bitrange.
1066                          * I suspect inverse beheaviour to the normal bitrange, but i am not a 100% certain about this.
1067                          * This is all based on default settings found in mmio-traces.
1068                          * The blob never changes these, as it doesn't run unusual output configurations.
1069                          * It seems to prefer situations that avoid changing these bits (for a good reason?).
1070                          * I still don't know the purpose of value 2, it's similar to 4, but what exactly does it do?
1071                          */
1072
1073                         /* Some extra info:
1074                          * nv30:
1075                          *      bit 0           NVClk spread spectrum on/off
1076                          *      bit 2           MemClk spread spectrum on/off
1077                          *      bit 4           PixClk1 spread spectrum on/off
1078                          *      bit 6           PixClk2 spread spectrum on/off
1079
1080                          *      nv40:
1081                          *      what causes setting of bits not obvious but:
1082                          *      bits 4&5                relate to headA
1083                          *      bits 6&7                relate to headB
1084                         */
1085                         /* Only let digital outputs mess with this, otherwise strange output routings may mess it up. */
1086                         if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
1087                                 if (pNv->Architecture == NV_ARCH_40) {
1088                                         for (i = 0; i < 4; i++) {
1089                                                 uint32_t var = (state->sel_clk & (0xf << 4*i)) >> 4*i;
1090                                                 if (var == 0x1 || var == 0x4) {
1091                                                         state->sel_clk &= ~(0xf << 4*i);
1092                                                         Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1093                                                         if (crossed_clocks) {
1094                                                                 state->sel_clk |= (0x4 << 4*i);
1095                                                         } else {
1096                                                                 state->sel_clk |= (0x1 << 4*i);
1097                                                         }
1098                                                         break; /* This should only occur once. */
1099                                                 }
1100                                         }
1101                                 /* Based on NV31M. */
1102                                 } else if (pNv->Architecture == NV_ARCH_30) {
1103                                         for (i = 0; i < 4; i++) {
1104                                                 uint32_t var = (state->sel_clk & (0xf << 4*i)) >> 4*i;
1105                                                 if (var == 0x4 || var == 0x5) {
1106                                                         state->sel_clk &= ~(0xf << 4*i);
1107                                                         Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1108                                                         if (crossed_clocks) {
1109                                                                 state->sel_clk |= (0x4 << 4*i);
1110                                                         } else {
1111                                                                 state->sel_clk |= (0x5 << 4*i);
1112                                                         }
1113                                                         break; /* This should only occur once. */
1114                                                 }
1115                                         }
1116                                 }
1117                         }
1118                 }
1119
1120                 /* Are we crosswired? */
1121                 if (output && nv_crtc->head != nv_output->preferred_output) {
1122                         state->crosswired = TRUE;
1123                 } else {
1124                         state->crosswired = FALSE;
1125                 }
1126
1127                 if (nv_crtc->head == 1) {
1128                         if (state->db1_ratio[1])
1129                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1130                 } else if (nv_crtc->head == 0) {
1131                         if (state->db1_ratio[0])
1132                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1133                 }
1134         } else {
1135                 /* Do NV1x/NV2x cards need anything in sel_clk? */
1136                 state->sel_clk = 0x0;
1137                 state->crosswired = FALSE;
1138         }
1139
1140         /* The NV40 seems to have more similarities to NV3x than other cards. */
1141         if (pNv->NVArch < 0x41) {
1142                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL;
1143                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL;
1144         }
1145
1146         if (nv_crtc->head == 1) {
1147                 if (!state->db1_ratio[1]) {
1148                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1149                 } else {
1150                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1151                 }
1152                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
1153         } else {
1154                 if (!state->db1_ratio[0]) {
1155                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1156                 } else {
1157                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1158                 }
1159                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
1160         }
1161
1162         /* The blob uses this always, so let's do the same */
1163         if (pNv->Architecture == NV_ARCH_40) {
1164                 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
1165         }
1166
1167         /* The primary output resource doesn't seem to care */
1168         if (output && pNv->Architecture == NV_ARCH_40 && nv_output->output_resource == 1) { /* This is the "output" */
1169                 /* non-zero values are for analog, don't know about tv-out and the likes */
1170                 if (output && nv_output->type != OUTPUT_ANALOG) {
1171                         state->reg594 = 0x0;
1172                 } else if (output) {
1173                         /* Are we a flexible output? */
1174                         if (ffs(pNv->dcb_table.entry[nv_output->dcb_entry].or) & OUTPUT_0) {
1175                                 state->reg594 = 0x1;
1176                                 pNv->restricted_mode = FALSE;
1177                         } else {
1178                                 state->reg594 = 0x0;
1179                                 pNv->restricted_mode = TRUE;
1180                         }
1181
1182                         /* More values exist, but they seem related to the 3rd dac (tv-out?) somehow */
1183                         /* bit 16-19 are bits that are set on some G70 cards */
1184                         /* Those bits are also set to the 3rd OUTPUT register */
1185                         if (nv_crtc->head == 1) {
1186                                 state->reg594 |= 0x100;
1187                         }
1188                 }
1189         }
1190
1191         regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
1192         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
1193         if (pNv->Architecture >= NV_ARCH_30) {
1194                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
1195         }
1196
1197         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1198                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = ((CrtcHDisplay/16) & 0x700) >> 3;
1199         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1200                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((CrtcHDisplay*bpp)/64) & 0x700) >> 3;
1201         } else { /* framebuffer can be larger than crtc scanout area. */
1202                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
1203         }
1204         regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
1205 }
1206
1207 static void
1208 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
1209 {
1210         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1211
1212         ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->head, mode);
1213
1214         if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */
1215                 return;
1216
1217         nv_crtc->last_dpms = mode;
1218
1219         ScrnInfoPtr pScrn = crtc->scrn;
1220         NVPtr pNv = NVPTR(pScrn);
1221         unsigned char seq1 = 0, crtc17 = 0;
1222         unsigned char crtc1A;
1223
1224         if (pNv->twoHeads)
1225                 NVCrtcSetOwner(crtc);
1226
1227         crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
1228         switch(mode) {
1229                 case DPMSModeStandby:
1230                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
1231                 seq1 = 0x20;
1232                 crtc17 = 0x80;
1233                 crtc1A |= 0x80;
1234                 break;
1235         case DPMSModeSuspend:
1236                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
1237                 seq1 = 0x20;
1238                 crtc17 = 0x80;
1239                 crtc1A |= 0x40;
1240                 break;
1241         case DPMSModeOff:
1242                 /* Screen: Off; HSync: Off, VSync: Off */
1243                 seq1 = 0x20;
1244                 crtc17 = 0x00;
1245                 crtc1A |= 0xC0;
1246                 break;
1247         case DPMSModeOn:
1248         default:
1249                 /* Screen: On; HSync: On, VSync: On */
1250                 seq1 = 0x00;
1251                 crtc17 = 0x80;
1252                 break;
1253         }
1254
1255         NVVgaSeqReset(crtc, TRUE);
1256         /* Each head has it's own sequencer, so we can turn it off when we want */
1257         seq1 |= (NVReadVgaSeq(crtc, 0x01) & ~0x20);
1258         NVWriteVgaSeq(crtc, 0x1, seq1);
1259         crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
1260         usleep(10000);
1261         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
1262         NVVgaSeqReset(crtc, FALSE);
1263
1264         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
1265
1266         /* I hope this is the right place */
1267         if (crtc->enabled && mode == DPMSModeOn) {
1268                 pNv->crtc_active[nv_crtc->head] = TRUE;
1269         } else {
1270                 pNv->crtc_active[nv_crtc->head] = FALSE;
1271         }
1272 }
1273
1274 static Bool
1275 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
1276                      DisplayModePtr adjusted_mode)
1277 {
1278         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1279         ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->head);
1280
1281         return TRUE;
1282 }
1283
1284 static void
1285 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1286 {
1287         ScrnInfoPtr pScrn = crtc->scrn;
1288         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1289         NVCrtcRegPtr regp;
1290         NVPtr pNv = NVPTR(pScrn);
1291         NVFBLayout *pLayout = &pNv->CurrentLayout;
1292         int depth = pScrn->depth;
1293
1294         /* This is pitch/memory size related. */
1295         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE))
1296                 depth = pNv->console_mode[nv_crtc->head].bpp;
1297
1298         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1299
1300         /* Calculate our timings */
1301         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
1302         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
1303         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
1304         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
1305         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
1306         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
1307         int vertDisplay         = mode->CrtcVDisplay                    - 1;
1308         int vertStart           = mode->CrtcVSyncStart          - 1;
1309         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
1310         int vertTotal           = mode->CrtcVTotal                      - 2;
1311         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
1312         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
1313
1314         Bool is_fp = FALSE;
1315
1316         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1317         NVOutputPrivatePtr nv_output = NULL;
1318         if (output) {
1319                 nv_output = output->driver_private;
1320
1321                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1322                         is_fp = TRUE;
1323         }
1324
1325         ErrorF("Mode clock: %d\n", mode->Clock);
1326         ErrorF("Adjusted mode clock: %d\n", adjusted_mode->Clock);
1327
1328         /* Reverted to what nv did, because that works for all resolutions on flatpanels */
1329         if (is_fp) {
1330                 vertStart = vertTotal - 3;
1331                 vertEnd = vertTotal - 2;
1332                 vertBlankStart = vertStart;
1333                 horizStart = horizTotal - 5;
1334                 horizEnd = horizTotal - 2;
1335                 horizBlankEnd = horizTotal + 4;
1336                 if (pNv->overlayAdaptor && pNv->Architecture >= NV_ARCH_10) {
1337                         /* This reportedly works around Xv some overlay bandwidth problems*/
1338                         horizTotal += 2;
1339                 }
1340         }
1341
1342         if (mode->Flags & V_INTERLACE)
1343                 vertTotal |= 1;
1344
1345         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
1346         ErrorF("horizStart: 0x%X \n", horizStart);
1347         ErrorF("horizEnd: 0x%X \n", horizEnd);
1348         ErrorF("horizTotal: 0x%X \n", horizTotal);
1349         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
1350         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
1351         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
1352         ErrorF("vertStart: 0x%X \n", vertStart);
1353         ErrorF("vertEnd: 0x%X \n", vertEnd);
1354         ErrorF("vertTotal: 0x%X \n", vertTotal);
1355         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
1356         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
1357
1358         /*
1359         * compute correct Hsync & Vsync polarity
1360         */
1361         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
1362                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
1363
1364                 regp->MiscOutReg = 0x23;
1365                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
1366                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
1367         } else {
1368                 int VDisplay = mode->VDisplay;
1369                 if (mode->Flags & V_DBLSCAN)
1370                         VDisplay *= 2;
1371                 if (mode->VScan > 1)
1372                         VDisplay *= mode->VScan;
1373                 if (VDisplay < 400) {
1374                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
1375                 } else if (VDisplay < 480) {
1376                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
1377                 } else if (VDisplay < 768) {
1378                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
1379                 } else {
1380                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
1381                 }
1382         }
1383
1384         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
1385
1386         /*
1387         * Time Sequencer
1388         */
1389         regp->Sequencer[0] = 0x00;
1390         /* 0x20 disables the sequencer */
1391         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1392                 if (mode->HDisplay == 720) {
1393                         regp->Sequencer[1] = 0x21; /* enable 9/8 mode */
1394                 } else {
1395                         regp->Sequencer[1] = 0x20;
1396                 }
1397         } else {
1398                 if (mode->Flags & V_CLKDIV2) {
1399                         regp->Sequencer[1] = 0x29;
1400                 } else {
1401                         regp->Sequencer[1] = 0x21;
1402                 }
1403         }
1404         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1405                 regp->Sequencer[2] = 0x03; /* select 2 out of 4 planes */
1406         } else {
1407                 regp->Sequencer[2] = 0x0F;
1408         }
1409         regp->Sequencer[3] = 0x00;                     /* Font select */
1410         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1411                 regp->Sequencer[4] = 0x02;
1412         } else {
1413                 regp->Sequencer[4] = 0x0E;                             /* Misc */
1414         }
1415
1416         /*
1417         * CRTC Controller
1418         */
1419         regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
1420         regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
1421         regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
1422         regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0)
1423                                 | SetBit(7);
1424         regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
1425         regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
1426                                 | SetBitField(horizEnd,4:0,4:0);
1427         regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
1428         regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
1429                                 | SetBitField(vertDisplay,8:8,1:1)
1430                                 | SetBitField(vertStart,8:8,2:2)
1431                                 | SetBitField(vertBlankStart,8:8,3:3)
1432                                 | SetBit(4)
1433                                 | SetBitField(vertTotal,9:9,5:5)
1434                                 | SetBitField(vertDisplay,9:9,6:6)
1435                                 | SetBitField(vertStart,9:9,7:7);
1436         regp->CRTC[NV_VGA_CRTCX_PRROWSCN]  = 0x00;
1437         regp->CRTC[NV_VGA_CRTCX_MAXSCLIN]  = SetBitField(vertBlankStart,9:9,5:5)
1438                                 | SetBit(6)
1439                                 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00)
1440                                 | (NVMatchModePrivate(mode, NV_MODE_VGA) ? 0xF : 0x00); /* 8x15 chars */
1441         if (NVMatchModePrivate(mode, NV_MODE_VGA)) { /* Were do these cursor offsets come from? */
1442                 regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0xD; /* start scanline */
1443                 regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0xE; /* end scanline */
1444         } else {
1445                 regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0x00;
1446                 regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0x00;
1447         }
1448         regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00;
1449         regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
1450         regp->CRTC[0xe] = 0x00;
1451         regp->CRTC[0xf] = 0x00;
1452         regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
1453         /* What is the meaning of bit5, it is empty in the vga spec. */
1454         regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) |
1455                                                                         (NVMatchModePrivate(mode, NV_MODE_VGA) ? 0 : SetBit(5));
1456         regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
1457         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1458                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = (mode->CrtcHDisplay/16);
1459         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1460                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((mode->CrtcHDisplay*depth)/64);
1461         } else { /* framebuffer can be larger than crtc scanout area. */
1462                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
1463         }
1464         if (depth == 4) { /* How can these values be calculated? */
1465                 regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x1F;
1466         } else {
1467                 regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x00;
1468         }
1469         regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
1470         regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
1471         /* 0x80 enables the sequencer, we don't want that */
1472         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1473                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xA3 & ~0x80;
1474         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1475                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xE3 & ~0x80;
1476         } else {
1477                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80;
1478         }
1479         regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
1480
1481         /*
1482          * Some extended CRTC registers (they are not saved with the rest of the vga regs).
1483          */
1484
1485         regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
1486                                 | SetBitField(vertBlankStart,10:10,3:3)
1487                                 | SetBitField(vertStart,10:10,2:2)
1488                                 | SetBitField(vertDisplay,10:10,1:1)
1489                                 | SetBitField(vertTotal,10:10,0:0);
1490
1491         regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
1492                                 | SetBitField(horizDisplay,8:8,1:1)
1493                                 | SetBitField(horizBlankStart,8:8,2:2)
1494                                 | SetBitField(horizStart,8:8,3:3);
1495
1496         regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
1497                                 | SetBitField(vertDisplay,11:11,2:2)
1498                                 | SetBitField(vertStart,11:11,4:4)
1499                                 | SetBitField(vertBlankStart,11:11,6:6);
1500
1501         if(mode->Flags & V_INTERLACE) {
1502                 horizTotal = (horizTotal >> 1) & ~1;
1503                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
1504                 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
1505         } else {
1506                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff;  /* interlace off */
1507         }
1508
1509         /*
1510         * Theory resumes here....
1511         */
1512
1513         /*
1514         * Graphics Display Controller
1515         */
1516         regp->Graphics[0] = 0x00;
1517         regp->Graphics[1] = 0x00;
1518         regp->Graphics[2] = 0x00;
1519         regp->Graphics[3] = 0x00;
1520         regp->Graphics[4] = 0x00;
1521         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1522                 regp->Graphics[5] = 0x10;
1523                 regp->Graphics[6] = 0x0E; /* map 32k mem */
1524                 regp->Graphics[7] = 0x00;
1525         } else {
1526                 regp->Graphics[5] = 0x40; /* 256 color mode */
1527                 regp->Graphics[6] = 0x05; /* map 64k mem + graphic mode */
1528                 regp->Graphics[7] = 0x0F;
1529         }
1530         regp->Graphics[8] = 0xFF;
1531
1532         /* I ditched the mono stuff */
1533         regp->Attribute[0]  = 0x00; /* standard colormap translation */
1534         regp->Attribute[1]  = 0x01;
1535         regp->Attribute[2]  = 0x02;
1536         regp->Attribute[3]  = 0x03;
1537         regp->Attribute[4]  = 0x04;
1538         regp->Attribute[5]  = 0x05;
1539         regp->Attribute[6]  = 0x06;
1540         regp->Attribute[7]  = 0x07;
1541         regp->Attribute[8]  = 0x08;
1542         regp->Attribute[9]  = 0x09;
1543         regp->Attribute[10] = 0x0A;
1544         regp->Attribute[11] = 0x0B;
1545         regp->Attribute[12] = 0x0C;
1546         regp->Attribute[13] = 0x0D;
1547         regp->Attribute[14] = 0x0E;
1548         regp->Attribute[15] = 0x0F;
1549         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1550                 regp->Attribute[16] = 0x0C; /* Line Graphics Enable + Blink enable */
1551         } else {
1552                 regp->Attribute[16] = 0x01; /* Enable graphic mode */
1553         }
1554         /* Non-vga */
1555         regp->Attribute[17] = 0x00;
1556         regp->Attribute[18] = 0x0F; /* enable all color planes */
1557         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1558                 regp->Attribute[19] = 0x08; /* shift bits by 8 */
1559         } else {
1560                 regp->Attribute[19] = 0x00;
1561         }
1562         regp->Attribute[20] = 0x00;
1563 }
1564
1565 #define MAX_H_VALUE(i) ((0x1ff + i) << 3)
1566 #define MAX_V_VALUE(i) ((0xfff + i) << 0)
1567
1568 /**
1569  * Sets up registers for the given mode/adjusted_mode pair.
1570  *
1571  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1572  *
1573  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1574  * be easily turned on/off after this.
1575  */
1576 static void
1577 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1578 {
1579         ScrnInfoPtr pScrn = crtc->scrn;
1580         NVPtr pNv = NVPTR(pScrn);
1581         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1582         NVFBLayout *pLayout = &pNv->CurrentLayout;
1583         NVCrtcRegPtr regp, savep;
1584         uint32_t i, depth;
1585         Bool is_fp = FALSE;
1586         Bool is_lvds = FALSE;
1587
1588         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1589         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1590
1591         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1592         NVOutputPrivatePtr nv_output = NULL;
1593         if (output) {
1594                 nv_output = output->driver_private;
1595
1596                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1597                         is_fp = TRUE;
1598
1599                 if (nv_output->type == OUTPUT_LVDS)
1600                         is_lvds = TRUE;
1601         }
1602
1603         /* Registers not directly related to the (s)vga mode */
1604
1605         /* bit2 = 0 -> fine pitched crtc granularity */
1606         /* The rest disables double buffering on CRTC access */
1607         regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
1608
1609         if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
1610                 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1611                 if (nv_crtc->head == 0) {
1612                         regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1613                 }
1614
1615                 if (is_fp) {
1616                         regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0);
1617                         if (!NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1618                                 regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 1);
1619                         }
1620                 }
1621         } else {
1622                 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
1623                 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
1624         }
1625
1626         /* Sometimes 0x10 is used, what is this? */
1627         regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1628         /* Some kind of tmds switch for older cards */
1629         if (pNv->Architecture < NV_ARCH_40) {
1630                 regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
1631         }
1632
1633         /*
1634         * Initialize DAC palette.
1635         * Will only be written when depth != 8.
1636         */
1637         for (i = 0; i < 256; i++) {
1638                 regp->DAC[i*3] = i;
1639                 regp->DAC[(i*3)+1] = i;
1640                 regp->DAC[(i*3)+2] = i;
1641         }
1642
1643         /*
1644         * Calculate the extended registers.
1645         */
1646
1647         if (pLayout->depth < 24) {
1648                 depth = pLayout->depth;
1649         } else {
1650                 depth = 32;
1651         }
1652
1653         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1654                 /* bpp is pitch related. */
1655                 depth = pNv->console_mode[nv_crtc->head].bpp;
1656         }
1657
1658         /* What is the meaning of this register? */
1659         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1660         regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
1661
1662         regp->head = 0;
1663
1664         /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1665         /* But what are those special conditions? */
1666         if (pNv->Architecture <= NV_ARCH_30) {
1667                 if (is_fp) {
1668                         if(nv_crtc->head == 1) {
1669                                 regp->head |= NV_CRTC_FSEL_FPP1;
1670                         } else if (pNv->twoHeads) {
1671                                 regp->head |= NV_CRTC_FSEL_FPP2;
1672                         }
1673                 }
1674         } else {
1675                 /* Most G70 cards have FPP2 set on the secondary CRTC. */
1676                 if (nv_crtc->head == 1 && pNv->NVArch > 0x44) {
1677                         regp->head |= NV_CRTC_FSEL_FPP2;
1678                 }
1679         }
1680
1681         /* Except for rare conditions I2C is enabled on the primary crtc */
1682         if (nv_crtc->head == 0) {
1683                 regp->head |= NV_CRTC_FSEL_I2C;
1684         }
1685
1686         /* Set overlay to desired crtc. */
1687         if (pNv->overlayAdaptor) {
1688                 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(pNv);
1689                 if (pPriv->overlayCRTC == nv_crtc->head)
1690                         regp->head |= NV_CRTC_FSEL_OVERLAY;
1691         }
1692
1693         /* This is not what nv does, but it is what the blob does (for nv4x at least) */
1694         /* This fixes my cursor corruption issue */
1695         regp->cursorConfig = 0x0;
1696         if(mode->Flags & V_DBLSCAN)
1697                 regp->cursorConfig |= (1 << 4);
1698         if (pNv->alphaCursor && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1699                 /* bit28 means we go into alpha blend mode and not rely on the current ROP */
1700                 regp->cursorConfig |= 0x14011000;
1701         } else {
1702                 regp->cursorConfig |= 0x02000000;
1703         }
1704
1705         /* Unblock some timings */
1706         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1707         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1708
1709         /* What is the purpose of this register? */
1710         /* 0x14 may be disabled? */
1711         regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1712
1713         /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
1714         if (is_lvds) {
1715                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x11;
1716         } else if (is_fp) {
1717                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1718         } else {
1719                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1720         }
1721
1722         /* These values seem to vary */
1723         /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
1724         regp->CRTC[NV_VGA_CRTCX_3C] = savep->CRTC[NV_VGA_CRTCX_3C];
1725
1726         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1727                 regp->CRTC[NV_VGA_CRTCX_45] = 0x0;
1728         } else {
1729                 regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1730         }
1731
1732         /* Some cards have 0x41 instead of 0x1 (for crtc 0), what is the meaning of that? */
1733         if (nv_crtc->head == 0)
1734                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x1;
1735         else
1736                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x0;
1737
1738         if (is_fp && !NVMatchModePrivate(mode, NV_MODE_CONSOLE))
1739                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x80;
1740
1741         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) { /* we need consistent restore. */
1742                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[nv_crtc->head];
1743         } else {
1744                 /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1.*/
1745                 if (nv_crtc->head == 1) {
1746                         regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[0];
1747                 } else {
1748                         regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[0] + 4;
1749                 }
1750         }
1751
1752         if (pNv->twoHeads)
1753                 /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1754                 regp->unk81c = nvReadCRTC0(pNv, NV_CRTC_081C);
1755
1756         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1757                 regp->unk830 = 0;
1758                 regp->unk834 = 0;
1759         } else {
1760                 regp->unk830 = mode->CrtcVDisplay - 3;
1761                 regp->unk834 = mode->CrtcVDisplay - 1;
1762         }
1763
1764         if (pNv->twoHeads)
1765                 /* This is what the blob does */
1766                 regp->unk850 = nvReadCRTC(pNv, 0, NV_CRTC_0850);
1767
1768         /* Never ever modify gpio, unless you know very well what you're doing */
1769         regp->gpio = nvReadCRTC(pNv, 0, NV_CRTC_GPIO);
1770
1771         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1772                 regp->config = 0x0; /* VGA mode */
1773         } else {
1774                 regp->config = 0x2; /* HSYNC mode */
1775         }
1776
1777         /* Some misc regs */
1778         regp->CRTC[NV_VGA_CRTCX_43] = 0x1;
1779         if (pNv->Architecture == NV_ARCH_40) {
1780                 regp->CRTC[NV_VGA_CRTCX_85] = 0xFF;
1781                 regp->CRTC[NV_VGA_CRTCX_86] = 0x1;
1782         }
1783
1784         /*
1785          * Calculate the state that is common to all crtc's (stored in the state struct).
1786          */
1787         ErrorF("crtc %d %d %d\n", nv_crtc->head, mode->CrtcHDisplay, pScrn->displayWidth);
1788         nv_crtc_calc_state_ext(crtc,
1789                                 mode,
1790                                 depth,
1791                                 pScrn->displayWidth,
1792                                 mode->CrtcHDisplay,
1793                                 mode->CrtcVDisplay,
1794                                 adjusted_mode->Clock,
1795                                 mode->Flags);
1796
1797         /* Enable slaved mode */
1798         if (is_fp) {
1799                 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1800         }
1801 }
1802
1803 static void
1804 nv_crtc_mode_set_ramdac_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1805 {
1806         ScrnInfoPtr pScrn = crtc->scrn;
1807         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1808         NVCrtcRegPtr regp, savep;
1809         NVPtr pNv = NVPTR(pScrn);
1810         NVFBLayout *pLayout = &pNv->CurrentLayout;
1811         Bool is_fp = FALSE;
1812         Bool is_lvds = FALSE;
1813         float aspect_ratio, panel_ratio;
1814         uint32_t h_scale, v_scale;
1815
1816         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1817         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1818
1819         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1820         NVOutputPrivatePtr nv_output = NULL;
1821         if (output) {
1822                 nv_output = output->driver_private;
1823
1824                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1825                         is_fp = TRUE;
1826
1827                 if (nv_output->type == OUTPUT_LVDS)
1828                         is_lvds = TRUE;
1829         }
1830
1831         if (is_fp) {
1832                 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
1833                 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
1834                 /* This is what the blob does. */
1835                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HSyncStart - 75 - 1;
1836                 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
1837                 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
1838                 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
1839                 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
1840
1841                 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
1842                 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
1843                 /* This is what the blob does. */
1844                 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VTotal - 5 - 1;
1845                 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
1846                 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
1847                 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
1848                 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
1849
1850                 /* Quirks, maybe move them somewere else? */
1851                 if (is_lvds) {
1852                         switch(pNv->NVArch) {
1853                                 case 0x46: /* 7300GO */
1854                                         /* Only native mode needed, is there some logic to this? */
1855                                         if (mode->HDisplay == 1280 && mode->VDisplay == 800) {
1856                                                 regp->fp_horiz_regs[REG_DISP_CRTC] = 0x4c6;
1857                                         }
1858                                         break;
1859                                 default:
1860                                         break;
1861                         }
1862                 }
1863
1864                 ErrorF("Horizontal:\n");
1865                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
1866                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
1867                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
1868                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
1869                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
1870                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
1871                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
1872
1873                 ErrorF("Vertical:\n");
1874                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
1875                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
1876                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
1877                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
1878                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
1879                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
1880                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
1881         }
1882
1883         /*
1884         * bit0: positive vsync
1885         * bit4: positive hsync
1886         * bit8: enable center mode
1887         * bit9: enable native mode
1888         * bit24: 12/24 bit interface (12bit=on, 24bit=off)
1889         * bit26: a bit sometimes seen on some g70 cards
1890         * bit28: fp display enable bit
1891         * bit31: set for dual link LVDS
1892         * nv10reg contains a few more things, but i don't quite get what it all means.
1893         */
1894
1895         if (pNv->Architecture >= NV_ARCH_30)
1896                 regp->fp_control[nv_crtc->head] = 0x00100000;
1897         else
1898                 regp->fp_control[nv_crtc->head] = 0x00000000;
1899
1900         /* Deal with vsync/hsync polarity */
1901         /* LVDS screens do set this, but modes with +ve syncs are very rare */
1902         if (is_fp) {
1903                 if (adjusted_mode->Flags & V_PVSYNC)
1904                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
1905                 if (adjusted_mode->Flags & V_PHSYNC)
1906                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
1907         } else {
1908                 /* The blob doesn't always do this, but often */
1909                 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_VSYNC_DISABLE;
1910                 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_HSYNC_DISABLE;
1911         }
1912
1913         if (is_fp) {
1914                 if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) /* seems to be used almost always */
1915                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1916                 else if (nv_output->scaling_mode == SCALE_PANEL) /* panel needs to scale */
1917                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
1918                 /* This is also true for panel scaling, so we must put the panel scale check first */
1919                 else if (mode->Clock == adjusted_mode->Clock) /* native mode */
1920                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
1921                 else /* gpu needs to scale */
1922                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1923         }
1924
1925         if (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
1926                 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
1927
1928         /* If the special bit exists, it exists on both ramdacs */
1929         regp->fp_control[nv_crtc->head] |= nvReadRAMDAC0(pNv, NV_RAMDAC_FP_CONTROL) & (1 << 26);
1930
1931         if (is_fp)
1932                 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS;
1933         else
1934                 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE;
1935
1936         Bool lvds_use_straps = pNv->dcb_table.entry[nv_output->dcb_entry].lvdsconf.use_straps_for_mode;
1937         if (is_lvds && ((lvds_use_straps && pNv->VBIOS.fp.dual_link) || (!lvds_use_straps && adjusted_mode->Clock >= pNv->VBIOS.fp.duallink_transition_clk)))
1938                 regp->fp_control[nv_crtc->head] |= (8 << 28);
1939
1940         if (is_fp) {
1941                 ErrorF("Pre-panel scaling\n");
1942                 ErrorF("panel-size:%dx%d\n", nv_output->fpWidth, nv_output->fpHeight);
1943                 panel_ratio = (nv_output->fpWidth)/(float)(nv_output->fpHeight);
1944                 ErrorF("panel_ratio=%f\n", panel_ratio);
1945                 aspect_ratio = (mode->HDisplay)/(float)(mode->VDisplay);
1946                 ErrorF("aspect_ratio=%f\n", aspect_ratio);
1947                 /* Scale factors is the so called 20.12 format, taken from Haiku */
1948                 h_scale = ((1 << 12) * mode->HDisplay)/nv_output->fpWidth;
1949                 v_scale = ((1 << 12) * mode->VDisplay)/nv_output->fpHeight;
1950                 ErrorF("h_scale=%d\n", h_scale);
1951                 ErrorF("v_scale=%d\n", v_scale);
1952
1953                 /* This can override HTOTAL and VTOTAL */
1954                 regp->debug_2 = 0;
1955
1956                 /* We want automatic scaling */
1957                 regp->debug_1 = 0;
1958
1959                 regp->fp_hvalid_start = 0;
1960                 regp->fp_hvalid_end = (nv_output->fpWidth - 1);
1961
1962                 regp->fp_vvalid_start = 0;
1963                 regp->fp_vvalid_end = (nv_output->fpHeight - 1);
1964
1965                 /* 0 = panel scaling */
1966                 if (nv_output->scaling_mode == SCALE_PANEL) {
1967                         ErrorF("Flat panel is doing the scaling.\n");
1968                 } else {
1969                         ErrorF("GPU is doing the scaling.\n");
1970
1971                         if (nv_output->scaling_mode == SCALE_ASPECT) {
1972                                 /* GPU scaling happens automaticly at a ratio of 1.33 */
1973                                 /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
1974                                 if (h_scale != (1 << 12) && (panel_ratio > (aspect_ratio + 0.10))) {
1975                                         uint32_t diff;
1976
1977                                         ErrorF("Scaling resolution on a widescreen panel\n");
1978
1979                                         /* Scaling in both directions needs to the same */
1980                                         h_scale = v_scale;
1981
1982                                         /* Set a new horizontal scale factor and enable testmode (bit12) */
1983                                         regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
1984
1985                                         diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
1986                                         regp->fp_hvalid_start = diff/2;
1987                                         regp->fp_hvalid_end = nv_output->fpWidth - (diff/2) - 1;
1988                                 }
1989
1990                                 /* Same scaling, just for panels with aspect ratio's smaller than 1 */
1991                                 if (v_scale != (1 << 12) && (panel_ratio < (aspect_ratio - 0.10))) {
1992                                         uint32_t diff;
1993
1994                                         ErrorF("Scaling resolution on a portrait panel\n");
1995
1996                                         /* Scaling in both directions needs to the same */
1997                                         v_scale = h_scale;
1998
1999                                         /* Set a new vertical scale factor and enable testmode (bit28) */
2000                                         regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
2001
2002                                         diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
2003                                         regp->fp_vvalid_start = diff/2;
2004                                         regp->fp_vvalid_end = nv_output->fpHeight - (diff/2) - 1;
2005                                 }
2006                         }
2007                 }
2008
2009                 ErrorF("Post-panel scaling\n");
2010         }
2011
2012         if (!is_fp && NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
2013                 regp->debug_1 = 0x08000800;
2014         }
2015
2016         if (pNv->Architecture >= NV_ARCH_10) {
2017                 /* Bios and blob don't seem to do anything (else) */
2018                 if (!NVMatchModePrivate(mode, NV_MODE_CONSOLE))
2019                         regp->nv10_cursync = (1<<25);
2020                 else
2021                         regp->nv10_cursync = 0;
2022         }
2023
2024         /* These are the common blob values, minus a few fp specific bit's */
2025         /* Let's keep the TMDS pll and fpclock running in all situations */
2026         regp->debug_0[nv_crtc->head] = 0x1101100;
2027
2028         if (is_fp && nv_output->scaling_mode != SCALE_NOSCALE) {
2029                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_XSCALE_ENABLED;
2030                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_YSCALE_ENABLED;
2031         } else if (is_fp) { /* no_scale mode, so we must center it */
2032                 uint32_t diff;
2033
2034                 diff = nv_output->fpWidth - mode->HDisplay;
2035                 regp->fp_hvalid_start = diff/2;
2036                 regp->fp_hvalid_end = (nv_output->fpWidth - diff/2 - 1);
2037
2038                 diff = nv_output->fpHeight - mode->VDisplay;
2039                 regp->fp_vvalid_start = diff/2;
2040                 regp->fp_vvalid_end = (nv_output->fpHeight - diff/2 - 1);
2041         }
2042
2043         /* Is this crtc bound or output bound? */
2044         /* Does the bios TMDS script try to change this sometimes? */
2045         if (is_fp) {
2046                 /* I am not completely certain, but seems to be set only for dfp's */
2047                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED;
2048         }
2049
2050         if (output)
2051                 ErrorF("output %d debug_0 %08X\n", nv_output->output_resource, regp->debug_0[nv_crtc->head]);
2052
2053         /* Flatpanel support needs at least a NV10 */
2054         if (pNv->twoHeads) {
2055                 /* The blob does this differently. */
2056                 /* TODO: Find out what precisely and why. */
2057                 /* Let's not destroy any bits that were already present. */
2058                 if (pNv->FPDither || (is_lvds && pNv->VBIOS.fp.if_is_18bit)) {
2059                         if (pNv->NVArch == 0x11) {
2060                                 regp->dither = savep->dither | 0x00010000;
2061                         } else {
2062                                 regp->dither = savep->dither | 0x00000001;
2063                         }
2064                 } else {
2065                         regp->dither = savep->dither;
2066                 }
2067         }
2068
2069         uint8_t depth;
2070         /* This is mode related, not pitch. */
2071         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
2072                 depth = pNv->console_mode[nv_crtc->head].depth;
2073         } else {
2074                 depth = pLayout->depth;
2075         }
2076
2077         switch (depth) {
2078                 case 4:
2079                         regp->general = 0x00000100;
2080                         break;
2081                 case 24:
2082                 case 15:
2083                         regp->general = 0x00100100;
2084                         break;
2085                 case 32:
2086                 case 16:
2087                 case 8:
2088                 default:
2089                         regp->general = 0x00101100;
2090                         break;
2091         }
2092
2093         if (depth > 8 && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
2094                 regp->general |= 0x30; /* enable palette mode */
2095         }
2096
2097         if (pNv->alphaCursor && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
2098                 /* PIPE_LONG mode, something to do with the size of the cursor? */
2099                 regp->general |= (1<<29);
2100         }
2101
2102         /* Some values the blob sets */
2103         /* This may apply to the real ramdac that is being used (for crosswired situations) */
2104         /* Nevertheless, it's unlikely to cause many problems, since the values are equal for both */
2105         regp->unk_a20 = 0x0;
2106         regp->unk_a24 = 0xfffff;
2107         regp->unk_a34 = 0x1;
2108
2109         if (pNv->twoHeads) {
2110                 /* Do we also "own" the other register pair? */
2111                 /* If we own neither, they will just be ignored at load time. */
2112                 uint8_t other_head = (~nv_crtc->head) & 1;
2113                 if (pNv->fp_regs_owner[other_head] == nv_crtc->head) {
2114                         if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS) {
2115                                 regp->fp_control[other_head] = regp->fp_control[nv_crtc->head];
2116                                 regp->debug_0[other_head] = regp->debug_0[nv_crtc->head];
2117                                 /* Set TMDS_PLL and FPCLK, only seen for a NV31M so far. */
2118                                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK;
2119                                 regp->debug_0[other_head] |= NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL;
2120                         } else {
2121                                 ErrorF("This is BAD, we own more than one fp reg set, but are not a LVDS or TMDS output.\n");
2122                         }
2123                 }
2124         }
2125 }
2126
2127 /**
2128  * Sets up registers for the given mode/adjusted_mode pair.
2129  *
2130  * The clocks, CRTCs and outputs attached to this CRTC must be off.
2131  *
2132  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
2133  * be easily turned on/off after this.
2134  */
2135 static void
2136 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
2137                  DisplayModePtr adjusted_mode,
2138                  int x, int y)
2139 {
2140         ScrnInfoPtr pScrn = crtc->scrn;
2141         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2142         NVPtr pNv = NVPTR(pScrn);
2143         NVFBLayout *pLayout = &pNv->CurrentLayout;
2144
2145         ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->head);
2146
2147         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->head);
2148         xf86PrintModeline(pScrn->scrnIndex, mode);
2149         if (pNv->twoHeads)
2150                 NVCrtcSetOwner(crtc);
2151
2152         nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
2153         nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
2154         nv_crtc_mode_set_ramdac_regs(crtc, mode, adjusted_mode);
2155
2156         NVVgaProtect(crtc, TRUE);
2157         nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
2158         nv_crtc_load_state_ext(crtc, &pNv->ModeReg, FALSE);
2159         if (pLayout->depth > 8)
2160                 NVCrtcLoadPalette(crtc);
2161         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
2162         if (pNv->Architecture == NV_ARCH_40) {
2163                 nv40_crtc_load_state_pll(crtc, &pNv->ModeReg);
2164         } else {
2165                 nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
2166         }
2167
2168         NVVgaProtect(crtc, FALSE);
2169
2170         NVCrtcSetBase(crtc, x, y, NVMatchModePrivate(mode, NV_MODE_CONSOLE));
2171
2172 #if X_BYTE_ORDER == X_BIG_ENDIAN
2173         /* turn on LFB swapping */
2174         {
2175                 unsigned char tmp;
2176
2177                 tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
2178                 tmp |= (1 << 7);
2179                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
2180         }
2181 #endif
2182 }
2183
2184 /* This functions generates data that is not saved, but still is needed. */
2185 void nv_crtc_restore_generate(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2186 {
2187         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2188         ScrnInfoPtr pScrn = crtc->scrn;
2189         NVPtr pNv = NVPTR(pScrn);
2190         int i;
2191         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
2192
2193         /* It's a good idea to also save a default palette on shutdown. */
2194         for (i = 0; i < 256; i++) {
2195                 regp->DAC[i*3] = i;
2196                 regp->DAC[(i*3)+1] = i;
2197                 regp->DAC[(i*3)+2] = i;
2198         }
2199
2200         /* Noticed that reading this variable is problematic on one card. */
2201         if (pNv->NVArch == 0x11)
2202                 state->sel_clk = 0x0;
2203 }
2204
2205 void nv_crtc_save(xf86CrtcPtr crtc)
2206 {
2207         ScrnInfoPtr pScrn = crtc->scrn;
2208         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2209         NVPtr pNv = NVPTR(pScrn);
2210
2211         ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->head);
2212
2213         /* We just came back from terminal, so unlock */
2214         NVCrtcLockUnlock(crtc, FALSE);
2215
2216         if (pNv->twoHeads)
2217                 NVCrtcSetOwner(crtc);
2218         nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
2219         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
2220         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
2221         if (pNv->Architecture == NV_ARCH_40) {
2222                 nv40_crtc_save_state_pll(pNv, &pNv->SavedReg);
2223         } else {
2224                 nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
2225         }
2226 }
2227
2228 void nv_crtc_restore(xf86CrtcPtr crtc)
2229 {
2230         ScrnInfoPtr pScrn = crtc->scrn;
2231         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2232         NVPtr pNv = NVPTR(pScrn);
2233         RIVA_HW_STATE *state;
2234         NVCrtcRegPtr savep;
2235
2236         state = &pNv->SavedReg;
2237         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
2238
2239         ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->head);
2240
2241         if (pNv->twoHeads)
2242                 NVCrtcSetOwner(crtc);
2243
2244         /* Just to be safe */
2245         NVCrtcLockUnlock(crtc, FALSE);
2246
2247         NVVgaProtect(crtc, TRUE);
2248         nv_crtc_restore_generate(crtc, &pNv->SavedReg);
2249         nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
2250         nv_crtc_load_state_ext(crtc, &pNv->SavedReg, TRUE);
2251         if (savep->general & 0x30) /* Palette mode */
2252                 NVCrtcLoadPalette(crtc);
2253         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
2254
2255         /* Force restoring vpll. */
2256         state->vpll_changed[nv_crtc->head] = TRUE;
2257
2258         if (pNv->Architecture == NV_ARCH_40) {
2259                 nv40_crtc_load_state_pll(crtc, &pNv->SavedReg);
2260         } else {
2261                 nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
2262         }
2263         if (pNv->twoHeads)
2264                 nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->vtOWNER);
2265         NVVgaProtect(crtc, FALSE);
2266
2267         nv_crtc->last_dpms = NV_DPMS_CLEARED;
2268 }
2269
2270 static void
2271 NVResetCrtcConfig(xf86CrtcPtr crtc, Bool set)
2272 {
2273         ScrnInfoPtr pScrn = crtc->scrn;
2274         NVPtr pNv = NVPTR(pScrn);
2275
2276         if (pNv->twoHeads) {
2277                 uint32_t val = 0;
2278
2279                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2280
2281                 if (set) {
2282                         NVCrtcRegPtr regp;
2283
2284                         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2285                         val = regp->head;
2286                 }
2287
2288                 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL, val);
2289         }
2290 }
2291
2292 void nv_crtc_prepare(xf86CrtcPtr crtc)
2293 {
2294         ScrnInfoPtr pScrn = crtc->scrn;
2295         NVPtr pNv = NVPTR(pScrn);
2296         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2297
2298         ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->head);
2299
2300         /* Just in case */
2301         NVCrtcLockUnlock(crtc, 0);
2302
2303         NVResetCrtcConfig(crtc, FALSE);
2304
2305         crtc->funcs->dpms(crtc, DPMSModeOff);
2306
2307         /* Sync the engine before adjust mode */
2308         if (pNv->EXADriverPtr) {
2309                 exaMarkSync(pScrn->pScreen);
2310                 exaWaitSync(pScrn->pScreen);
2311         }
2312
2313         NVCrtcBlankScreen(crtc, FALSE); /* Blank screen */
2314
2315         /* Some more preperation. */
2316         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG, 0x1); /* Go to non-vga mode/out of enhanced mode */
2317         if (pNv->Architecture == NV_ARCH_40) {
2318                 uint32_t reg900 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900);
2319                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 & ~0x10000);
2320         }
2321 }
2322
2323 void nv_crtc_commit(xf86CrtcPtr crtc)
2324 {
2325         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2326         ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->head);
2327
2328         crtc->funcs->dpms (crtc, DPMSModeOn);
2329
2330         if (crtc->scrn->pScreen != NULL)
2331                 xf86_reload_cursors (crtc->scrn->pScreen);
2332
2333         NVResetCrtcConfig(crtc, TRUE);
2334 }
2335
2336 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
2337 {
2338         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2339         ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->head);
2340
2341         return FALSE;
2342 }
2343
2344 static void nv_crtc_unlock(xf86CrtcPtr crtc)
2345 {
2346         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2347         ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->head);
2348 }
2349
2350 static void
2351 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
2352                                         int size)
2353 {
2354         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2355         ScrnInfoPtr pScrn = crtc->scrn;
2356         NVPtr pNv = NVPTR(pScrn);
2357         int i, j;
2358
2359         NVCrtcRegPtr regp;
2360         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2361
2362         switch (pNv->CurrentLayout.depth) {
2363         case 15:
2364                 /* R5G5B5 */
2365                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
2366                 for (i = 0; i < 32; i++) {
2367                         for (j = 0; j < 8; j++) {
2368                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2369                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
2370                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2371                         }
2372                 }
2373                 break;
2374         case 16:
2375                 /* R5G6B5 */
2376                 /* First deal with the 5 bit colors */
2377                 for (i = 0; i < 32; i++) {
2378                         for (j = 0; j < 8; j++) {
2379                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2380                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2381                         }
2382                 }
2383                 /* Now deal with the 6 bit color */
2384                 for (i = 0; i < 64; i++) {
2385                         for (j = 0; j < 4; j++) {
2386                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
2387                         }
2388                 }
2389                 break;
2390         default:
2391                 /* R8G8B8 */
2392                 for (i = 0; i < 256; i++) {
2393                         regp->DAC[i * 3] = red[i] >> 8;
2394                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
2395                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
2396                 }
2397                 break;
2398         }
2399
2400         NVCrtcLoadPalette(crtc);
2401 }
2402
2403 /**
2404  * Allocates memory for a locked-in-framebuffer shadow of the given
2405  * width and height for this CRTC's rotated shadow framebuffer.
2406  */
2407
2408 static void *
2409 nv_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
2410 {
2411         ErrorF("nv_crtc_shadow_allocate is called\n");
2412         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2413         ScrnInfoPtr pScrn = crtc->scrn;
2414 #if !NOUVEAU_EXA_PIXMAPS
2415         ScreenPtr pScreen = pScrn->pScreen;
2416 #endif /* !NOUVEAU_EXA_PIXMAPS */
2417         NVPtr pNv = NVPTR(pScrn);
2418         void *offset;
2419
2420         unsigned long rotate_pitch;
2421         int size, align = 64;
2422
2423         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2424         size = rotate_pitch * height;
2425
2426         assert(nv_crtc->shadow == NULL);
2427 #if NOUVEAU_EXA_PIXMAPS
2428         if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN,
2429                         align, size, &nv_crtc->shadow)) {
2430                 ErrorF("Failed to allocate memory for shadow buffer!\n");
2431                 return NULL;
2432         }
2433
2434         if (nv_crtc->shadow && nouveau_bo_map(nv_crtc->shadow, NOUVEAU_BO_RDWR)) {
2435                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2436                                 "Failed to map shadow buffer.\n");
2437                 return NULL;
2438         }
2439
2440         offset = nv_crtc->shadow->map;
2441 #else
2442         nv_crtc->shadow = exaOffscreenAlloc(pScreen, size, align, TRUE, NULL, NULL);
2443         if (nv_crtc->shadow == NULL) {
2444                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2445                         "Couldn't allocate shadow memory for rotated CRTC\n");
2446                 return NULL;
2447         }
2448         offset = pNv->FB->map + nv_crtc->shadow->offset;
2449 #endif /* NOUVEAU_EXA_PIXMAPS */
2450
2451         return offset;
2452 }
2453
2454 /**
2455  * Creates a pixmap for this CRTC's rotated shadow framebuffer.
2456  */
2457 static PixmapPtr
2458 nv_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
2459 {
2460         ErrorF("nv_crtc_shadow_create is called\n");
2461         ScrnInfoPtr pScrn = crtc->scrn;
2462 #if NOUVEAU_EXA_PIXMAPS
2463         ScreenPtr pScreen = pScrn->pScreen;
2464         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2465 #endif /* NOUVEAU_EXA_PIXMAPS */
2466         unsigned long rotate_pitch;
2467         PixmapPtr rotate_pixmap;
2468 #if NOUVEAU_EXA_PIXMAPS
2469         struct nouveau_pixmap *nvpix;
2470 #endif /* NOUVEAU_EXA_PIXMAPS */
2471
2472         if (!data)
2473                 data = crtc->funcs->shadow_allocate (crtc, width, height);
2474
2475         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2476
2477 #if NOUVEAU_EXA_PIXMAPS
2478         /* Create a dummy pixmap, to get a private that will be accepted by the system.*/
2479         rotate_pixmap = pScreen->CreatePixmap(pScreen,
2480                                                                 0, /* width */
2481                                                                 0, /* height */
2482         #ifdef CREATE_PIXMAP_USAGE_SCRATCH /* there seems to have been no api bump */
2483                                                                 pScrn->depth,
2484                                                                 0);
2485         #else
2486                                                                 pScrn->depth);
2487         #endif /* CREATE_PIXMAP_USAGE_SCRATCH */
2488 #else
2489         rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen,
2490                                                                 width, height,
2491                                                                 pScrn->depth,
2492                                                                 pScrn->bitsPerPixel,
2493                                                                 rotate_pitch,
2494                                                                 data);
2495 #endif /* NOUVEAU_EXA_PIXMAPS */
2496
2497         if (rotate_pixmap == NULL) {
2498                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2499                         "Couldn't allocate shadow pixmap for rotated CRTC\n");
2500         }
2501
2502 #if NOUVEAU_EXA_PIXMAPS
2503         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2504         if (!nvpix) {
2505                 ErrorF("No shadow private, stage 1\n");
2506         } else {
2507                 nvpix->bo = nv_crtc->shadow;
2508                 nvpix->mapped = TRUE;
2509         }
2510
2511         /* Modify the pixmap to actually be the one we need. */
2512         pScreen->ModifyPixmapHeader(rotate_pixmap,
2513                                         width,
2514                                         height,
2515                                         pScrn->depth,
2516                                         pScrn->bitsPerPixel,
2517                                         rotate_pitch,
2518                                         data);
2519
2520         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2521         if (!nvpix || !nvpix->bo)
2522                 ErrorF("No shadow private, stage 2\n");
2523 #endif /* NOUVEAU_EXA_PIXMAPS */
2524
2525         return rotate_pixmap;
2526 }
2527
2528 static void
2529 nv_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
2530 {
2531         ErrorF("nv_crtc_shadow_destroy is called\n");
2532         ScrnInfoPtr pScrn = crtc->scrn;
2533         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2534         ScreenPtr pScreen = pScrn->pScreen;
2535
2536         if (rotate_pixmap) { /* This should also unmap the buffer object if relevant. */
2537                 pScreen->DestroyPixmap(rotate_pixmap);
2538         }
2539
2540 #if !NOUVEAU_EXA_PIXMAPS
2541         if (data && nv_crtc->shadow) {
2542                 exaOffscreenFree(pScreen, nv_crtc->shadow);
2543         }
2544 #endif /* !NOUVEAU_EXA_PIXMAPS */
2545
2546         nv_crtc->shadow = NULL;
2547 }
2548
2549 /* NV04-NV10 doesn't support alpha cursors */
2550 static const xf86CrtcFuncsRec nv_crtc_funcs = {
2551         .dpms = nv_crtc_dpms,
2552         .save = nv_crtc_save, /* XXX */
2553         .restore = nv_crtc_restore, /* XXX */
2554         .mode_fixup = nv_crtc_mode_fixup,
2555         .mode_set = nv_crtc_mode_set,
2556         .prepare = nv_crtc_prepare,
2557         .commit = nv_crtc_commit,
2558         .destroy = NULL, /* XXX */
2559         .lock = nv_crtc_lock,
2560         .unlock = nv_crtc_unlock,
2561         .set_cursor_colors = nv_crtc_set_cursor_colors,
2562         .set_cursor_position = nv_crtc_set_cursor_position,
2563         .show_cursor = nv_crtc_show_cursor,
2564         .hide_cursor = nv_crtc_hide_cursor,
2565         .load_cursor_image = nv_crtc_load_cursor_image,
2566         .gamma_set = nv_crtc_gamma_set,
2567         .shadow_create = nv_crtc_shadow_create,
2568         .shadow_allocate = nv_crtc_shadow_allocate,
2569         .shadow_destroy = nv_crtc_shadow_destroy,
2570 };
2571
2572 /* NV11 and up has support for alpha cursors. */
2573 /* Due to different maximum sizes we cannot allow it to use normal cursors */
2574 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
2575         .dpms = nv_crtc_dpms,
2576         .save = nv_crtc_save, /* XXX */
2577         .restore = nv_crtc_restore, /* XXX */
2578         .mode_fixup = nv_crtc_mode_fixup,
2579         .mode_set = nv_crtc_mode_set,
2580         .prepare = nv_crtc_prepare,
2581         .commit = nv_crtc_commit,
2582         .destroy = NULL, /* XXX */
2583         .lock = nv_crtc_lock,
2584         .unlock = nv_crtc_unlock,
2585         .set_cursor_colors = NULL, /* Alpha cursors do not need this */
2586         .set_cursor_position = nv_crtc_set_cursor_position,
2587         .show_cursor = nv_crtc_show_cursor,
2588         .hide_cursor = nv_crtc_hide_cursor,
2589         .load_cursor_argb = nv_crtc_load_cursor_argb,
2590         .gamma_set = nv_crtc_gamma_set,
2591         .shadow_create = nv_crtc_shadow_create,
2592         .shadow_allocate = nv_crtc_shadow_allocate,
2593         .shadow_destroy = nv_crtc_shadow_destroy,
2594 };
2595
2596
2597 void
2598 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
2599 {
2600         NVPtr pNv = NVPTR(pScrn);
2601         xf86CrtcPtr crtc;
2602         NVCrtcPrivatePtr nv_crtc;
2603
2604         if (pNv->NVArch >= 0x11) {
2605                 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
2606         } else {
2607                 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
2608         }
2609         if (crtc == NULL)
2610                 return;
2611
2612         nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
2613         nv_crtc->head = crtc_num;
2614         nv_crtc->last_dpms = NV_DPMS_CLEARED;
2615         pNv->fp_regs_owner[nv_crtc->head] = nv_crtc->head;
2616
2617         crtc->driver_private = nv_crtc;
2618
2619         NVCrtcLockUnlock(crtc, FALSE);
2620 }
2621
2622 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2623 {
2624         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2625         int i;
2626         NVCrtcRegPtr regp;
2627
2628         regp = &state->crtc_reg[nv_crtc->head];
2629
2630         NVWriteMiscOut(crtc, regp->MiscOutReg);
2631
2632         for (i = 1; i < 5; i++)
2633                 NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
2634
2635         /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
2636         NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
2637
2638         for (i = 0; i < 25; i++)
2639                 NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
2640
2641         for (i = 0; i < 9; i++)
2642                 NVWriteVgaGr(crtc, i, regp->Graphics[i]);
2643
2644         NVEnablePalette(crtc);
2645         for (i = 0; i < 21; i++)
2646                 NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
2647
2648         NVDisablePalette(crtc);
2649 }
2650
2651 static void nv_crtc_fix_nv40_hw_cursor(xf86CrtcPtr crtc)
2652 {
2653         /* TODO - implement this properly */
2654         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2655         ScrnInfoPtr pScrn = crtc->scrn;
2656         NVPtr pNv = NVPTR(pScrn);
2657
2658         if (pNv->Architecture == NV_ARCH_40) {  /* HW bug */
2659                 volatile uint32_t curpos = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS);
2660                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS, curpos);
2661         }
2662 }
2663 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override)
2664 {
2665         ScrnInfoPtr pScrn = crtc->scrn;
2666         NVPtr pNv = NVPTR(pScrn);
2667         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2668         NVCrtcRegPtr regp;
2669         int i;
2670
2671         regp = &state->crtc_reg[nv_crtc->head];
2672
2673         if (pNv->Architecture >= NV_ARCH_10) {
2674                 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
2675                 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
2676                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
2677                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
2678                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2679                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2680                 nvWriteMC(pNv, 0x1588, 0);
2681
2682                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
2683                 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
2684                 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0830, regp->unk830);
2685                 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0834, regp->unk834);
2686                 if (pNv->Architecture == NV_ARCH_40) {
2687                         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0850, regp->unk850);
2688                         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_081C, regp->unk81c);
2689                 }
2690
2691                 if (pNv->Architecture == NV_ARCH_40) {
2692                         uint32_t reg900 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900);
2693                         if (regp->config == 0x2) { /* enhanced "horizontal only" non-vga mode */
2694                                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 | 0x10000);
2695                         } else {
2696                                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 & ~0x10000);
2697                         }
2698                 }
2699         }
2700
2701         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG, regp->config);
2702         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO, regp->gpio);
2703
2704         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
2705         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
2706         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
2707         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
2708         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
2709         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
2710         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
2711         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
2712         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
2713         if (pNv->Architecture >= NV_ARCH_30)
2714                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
2715
2716         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
2717         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
2718         nv_crtc_fix_nv40_hw_cursor(crtc);
2719         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
2720         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
2721
2722         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
2723         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
2724         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3C, regp->CRTC[NV_VGA_CRTCX_3C]);
2725         if (pNv->Architecture >= NV_ARCH_10) {
2726                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
2727                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_43, regp->CRTC[NV_VGA_CRTCX_43]);
2728                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
2729                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_4B, regp->CRTC[NV_VGA_CRTCX_4B]);
2730                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
2731         }
2732         /* NV11 and NV20 stop at 0x52. */
2733         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
2734                 if (override)
2735                         for (i = 0; i < 0x10; i++)
2736                                 NVWriteVGACR5758(pNv, nv_crtc->head, i, regp->CR58[i]);
2737
2738                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
2739                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
2740
2741                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
2742
2743                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_85, regp->CRTC[NV_VGA_CRTCX_85]);
2744                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_86, regp->CRTC[NV_VGA_CRTCX_86]);
2745         }
2746
2747         /* Setting 1 on this value gives you interrupts for every vblank period. */
2748         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_EN_0, 0);
2749         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
2750
2751         pNv->CurrentState = state;
2752 }
2753
2754 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2755 {
2756         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2757         int i;
2758         NVCrtcRegPtr regp;
2759
2760         regp = &state->crtc_reg[nv_crtc->head];
2761
2762         regp->MiscOutReg = NVReadMiscOut(crtc);
2763
2764         for (i = 0; i < 25; i++)
2765                 regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
2766
2767         NVEnablePalette(crtc);
2768         for (i = 0; i < 21; i++)
2769                 regp->Attribute[i] = NVReadVgaAttr(crtc, i);
2770         NVDisablePalette(crtc);
2771
2772         for (i = 0; i < 9; i++)
2773                 regp->Graphics[i] = NVReadVgaGr(crtc, i);
2774
2775         for (i = 1; i < 5; i++)
2776                 regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
2777 }
2778
2779 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2780 {
2781         ScrnInfoPtr pScrn = crtc->scrn;
2782         NVPtr pNv = NVPTR(pScrn);
2783         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2784         NVCrtcRegPtr regp;
2785         int i;
2786
2787         regp = &state->crtc_reg[nv_crtc->head];
2788
2789         regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
2790         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
2791         regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
2792         regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
2793         regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
2794         regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
2795         regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
2796
2797         regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
2798         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
2799         regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
2800         if (pNv->Architecture >= NV_ARCH_30)
2801                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
2802         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
2803         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
2804         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
2805         regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
2806
2807         if (pNv->Architecture >= NV_ARCH_10) {
2808                 regp->unk830 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0830);
2809                 regp->unk834 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0834);
2810                 if (pNv->Architecture == NV_ARCH_40) {
2811                         regp->unk850 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0850);
2812                         regp->unk81c = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_081C);
2813                 }
2814                 if (pNv->twoHeads) {
2815                         regp->head = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL);
2816                         regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
2817                 }
2818                 regp->cursorConfig = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG);
2819         }
2820
2821         regp->gpio = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO);
2822         regp->config = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG);
2823
2824         regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
2825         regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
2826         regp->CRTC[NV_VGA_CRTCX_3C] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3C);
2827         if (pNv->Architecture >= NV_ARCH_10) {
2828                 regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
2829                 regp->CRTC[NV_VGA_CRTCX_43] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_43);
2830                 regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
2831                 regp->CRTC[NV_VGA_CRTCX_4B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_4B);
2832                 regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
2833         }
2834         /* NV11 and NV20 don't have this, they stop at 0x52. */
2835         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
2836                 for (i = 0; i < 0x10; i++)
2837                         regp->CR58[i] = NVReadVGACR5758(pNv, nv_crtc->head, i);
2838
2839                 regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
2840                 regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
2841                 regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
2842
2843                 regp->CRTC[NV_VGA_CRTCX_85] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_85);
2844                 regp->CRTC[NV_VGA_CRTCX_86] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_86);
2845         }
2846 }
2847
2848 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2849 {
2850         ScrnInfoPtr pScrn = crtc->scrn;
2851         NVPtr pNv = NVPTR(pScrn);
2852         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2853         NVCrtcRegPtr regp;
2854         int i;
2855
2856         regp = &state->crtc_reg[nv_crtc->head];
2857
2858         regp->general = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL);
2859
2860         regp->fp_control[0]     = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL);
2861         regp->debug_0[0]        = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
2862
2863         if (pNv->twoHeads) {
2864                 regp->fp_control[1]     = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_CONTROL);
2865                 regp->debug_0[1]        = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
2866
2867                 regp->debug_1   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1);
2868                 regp->debug_2   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2);
2869
2870                 regp->unk_a20 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20);
2871                 regp->unk_a24 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24);
2872                 regp->unk_a34 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34);
2873         }
2874
2875         if (pNv->NVArch == 0x11) {
2876                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11);
2877         } else if (pNv->twoHeads) {
2878                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER);
2879         }
2880         if (pNv->Architecture >= NV_ARCH_10)
2881                 regp->nv10_cursync = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC);
2882
2883         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2884
2885         for (i = 0; i < 7; i++) {
2886                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2887                 regp->fp_horiz_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2888         }
2889
2890         for (i = 0; i < 7; i++) {
2891                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2892                 regp->fp_vert_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2893         }
2894
2895         regp->fp_hvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START);
2896         regp->fp_hvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END);
2897         regp->fp_vvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START);
2898         regp->fp_vvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END);
2899 }
2900
2901 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2902 {
2903         ScrnInfoPtr pScrn = crtc->scrn;
2904         NVPtr pNv = NVPTR(pScrn);
2905         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2906         NVCrtcRegPtr regp;
2907         int i;
2908
2909         regp = &state->crtc_reg[nv_crtc->head];
2910
2911         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL, regp->general);
2912
2913         if (pNv->fp_regs_owner[0] == nv_crtc->head) {
2914                 nvWriteRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL, regp->fp_control[0]);
2915                 nvWriteRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0, regp->debug_0[0]);
2916         }
2917         if (pNv->twoHeads) {
2918                 if (pNv->fp_regs_owner[1] == nv_crtc->head) {
2919                         nvWriteRAMDAC(pNv, 1, NV_RAMDAC_FP_CONTROL, regp->fp_control[1]);
2920                         nvWriteRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0, regp->debug_0[1]);
2921                 }
2922                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
2923                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
2924                 if (pNv->NVArch == 0x30) { /* For unknown purposes. */
2925                         uint32_t reg890 = nvReadRAMDAC(pNv, nv_crtc->head, NV30_RAMDAC_890);
2926                         nvWriteRAMDAC(pNv, nv_crtc->head, NV30_RAMDAC_89C, reg890);
2927                 }
2928
2929                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20, regp->unk_a20);
2930                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24, regp->unk_a24);
2931                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34, regp->unk_a34);
2932         }
2933
2934         if (pNv->NVArch == 0x11) {
2935                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11, regp->dither);
2936         } else if (pNv->twoHeads) {
2937                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER, regp->dither);
2938         }
2939         if (pNv->Architecture >= NV_ARCH_10)
2940                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
2941
2942         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2943
2944         for (i = 0; i < 7; i++) {
2945                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2946                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_horiz_regs[i]);
2947         }
2948
2949         for (i = 0; i < 7; i++) {
2950                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2951                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_vert_regs[i]);
2952         }
2953
2954         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START, regp->fp_hvalid_start);
2955         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END, regp->fp_hvalid_end);
2956         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START, regp->fp_vvalid_start);
2957         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END, regp->fp_vvalid_end);
2958 }
2959
2960 void
2961 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y, Bool bios_restore)
2962 {
2963         ScrnInfoPtr pScrn = crtc->scrn;
2964         NVPtr pNv = NVPTR(pScrn);
2965         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2966         NVFBLayout *pLayout = &pNv->CurrentLayout;
2967         uint32_t start = 0;
2968
2969         ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
2970
2971         if (bios_restore) {
2972                 start = pNv->console_mode[nv_crtc->head].fb_start;
2973         } else {
2974                 start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
2975                 if (crtc->rotatedData != NULL) { /* we do not exist on the real framebuffer */
2976 #if NOUVEAU_EXA_PIXMAPS
2977                         start = nv_crtc->shadow->offset;
2978 #else
2979                         start = pNv->FB->offset + nv_crtc->shadow->offset; /* We do exist relative to the framebuffer */
2980 #endif
2981                 } else {
2982                         start += pNv->FB->offset;
2983                 }
2984         }
2985
2986         /* 30 bits addresses in 32 bits according to haiku */
2987         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_START, start & 0xfffffffc);
2988
2989         /* set NV4/NV10 byte adress: (bit0 - 1) */
2990         NVWriteVgaAttr(crtc, 0x13, (start & 0x3) << 1);
2991
2992         crtc->x = x;
2993         crtc->y = y;
2994 }
2995
2996 static void NVCrtcWriteDacMask(xf86CrtcPtr crtc, uint8_t value)
2997 {
2998   ScrnInfoPtr pScrn = crtc->scrn;
2999   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3000   NVPtr pNv = NVPTR(pScrn);
3001   volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3002
3003   NV_WR08(pDACReg, VGA_DAC_MASK, value);
3004 }
3005
3006 static uint8_t NVCrtcReadDacMask(xf86CrtcPtr crtc)
3007 {
3008   ScrnInfoPtr pScrn = crtc->scrn;
3009   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3010   NVPtr pNv = NVPTR(pScrn);
3011   volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3012
3013   return NV_RD08(pDACReg, VGA_DAC_MASK);
3014 }
3015
3016 static void NVCrtcWriteDacReadAddr(xf86CrtcPtr crtc, uint8_t value)
3017 {
3018   ScrnInfoPtr pScrn = crtc->scrn;
3019   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3020   NVPtr pNv = NVPTR(pScrn);
3021   volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3022
3023   NV_WR08(pDACReg, VGA_DAC_READ_ADDR, value);
3024 }
3025
3026 static void NVCrtcWriteDacWriteAddr(xf86CrtcPtr crtc, uint8_t value)
3027 {
3028   ScrnInfoPtr pScrn = crtc->scrn;
3029   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3030   NVPtr pNv = NVPTR(pScrn);
3031   volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3032
3033   NV_WR08(pDACReg, VGA_DAC_WRITE_ADDR, value);
3034 }
3035
3036 static void NVCrtcWriteDacData(xf86CrtcPtr crtc, uint8_t value)
3037 {
3038   ScrnInfoPtr pScrn = crtc->scrn;
3039   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3040   NVPtr pNv = NVPTR(pScrn);
3041   volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3042
3043   NV_WR08(pDACReg, VGA_DAC_DATA, value);
3044 }
3045
3046 static uint8_t NVCrtcReadDacData(xf86CrtcPtr crtc, uint8_t value)
3047 {
3048   ScrnInfoPtr pScrn = crtc->scrn;
3049   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3050   NVPtr pNv = NVPTR(pScrn);
3051   volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3052
3053   return NV_RD08(pDACReg, VGA_DAC_DATA);
3054 }
3055
3056 void NVCrtcLoadPalette(xf86CrtcPtr crtc)
3057 {
3058         int i;
3059         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3060         NVCrtcRegPtr regp;
3061         ScrnInfoPtr pScrn = crtc->scrn;
3062         NVPtr pNv = NVPTR(pScrn);
3063
3064         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
3065
3066         if (pNv->twoHeads)
3067                 NVCrtcSetOwner(crtc);
3068         NVCrtcWriteDacMask(crtc, 0xff);
3069         NVCrtcWriteDacWriteAddr(crtc, 0x00);
3070
3071         for (i = 0; i<768; i++) {
3072                 NVCrtcWriteDacData(crtc, regp->DAC[i]);
3073         }
3074         NVDisablePalette(crtc);
3075 }
3076
3077 /* on = unblank */
3078 void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
3079 {
3080         NVPtr pNv = NVPTR(crtc->scrn);
3081         unsigned char scrn;
3082
3083         if (pNv->twoHeads)
3084                 NVCrtcSetOwner(crtc);
3085
3086         scrn = NVReadVgaSeq(crtc, 0x01);
3087         if (on) {
3088                 scrn &= ~0x20;
3089         } else {
3090                 scrn |= 0x20;
3091         }
3092
3093         NVVgaSeqReset(crtc, TRUE);
3094         NVWriteVgaSeq(crtc, 0x01, scrn);
3095         NVVgaSeqReset(crtc, FALSE);
3096 }
3097
3098 /* Reset a mode after a drastic output resource change for example. */
3099 void NVCrtcModeFix(xf86CrtcPtr crtc)
3100 {
3101         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3102         Bool need_unlock;
3103
3104         if (!crtc->enabled)
3105                 return;
3106
3107         if (!xf86ModesEqual(&crtc->mode, &crtc->desiredMode)) /* not currently in X */
3108                 return;
3109
3110         DisplayModePtr adjusted_mode = xf86DuplicateMode(&crtc->mode);
3111         uint8_t dpms_mode = nv_crtc->last_dpms;
3112
3113         /* Set the crtc mode again. */
3114         crtc->funcs->dpms(crtc, DPMSModeOff);
3115         need_unlock = crtc->funcs->lock(crtc);
3116         crtc->funcs->mode_fixup(crtc, &crtc->mode, adjusted_mode);
3117         crtc->funcs->prepare(crtc);
3118         crtc->funcs->mode_set(crtc, &crtc->mode, adjusted_mode, crtc->x, crtc->y);
3119         crtc->funcs->commit(crtc);
3120         if (need_unlock)
3121                 crtc->funcs->unlock(crtc);
3122         crtc->funcs->dpms(crtc, dpms_mode);
3123
3124         /* Free mode. */
3125         xfree(adjusted_mode);
3126 }
3127
3128 /*************************************************************************** \
3129 |*                                                                           *|
3130 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
3131 |*                                                                           *|
3132 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
3133 |*     international laws.  Users and possessors of this source code are     *|
3134 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
3135 |*     use this code in individual and commercial software.                  *|
3136 |*                                                                           *|
3137 |*     Any use of this source code must include,  in the user documenta-     *|
3138 |*     tion and  internal comments to the code,  notices to the end user     *|
3139 |*     as follows:                                                           *|
3140 |*                                                                           *|
3141 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
3142 |*                                                                           *|
3143 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
3144 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
3145 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
3146 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
3147 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
3148 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
3149 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
3150 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
3151 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
3152 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
3153 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
3154 |*                                                                           *|
3155 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
3156 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
3157 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
3158 |*     computer  software  documentation,"  as such  terms  are  used in     *|
3159 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
3160 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
3161 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
3162 |*     all U.S. Government End Users  acquire the source code  with only     *|
3163 |*     those rights set forth herein.                                        *|
3164 |*                                                                           *|
3165  \***************************************************************************/