2 * Copyright 2006 Dave Airlie
3 * Copyright 2007 Maarten Maathuis
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
26 * decleration is at the bottom of this file as it is rather ugly
41 #include "mipointer.h"
42 #include "windowstr.h"
44 #include <X11/extensions/render.h>
47 #include "nv_include.h"
51 #define CRTC_INDEX 0x3d4
52 #define CRTC_DATA 0x3d5
53 #define CRTC_IN_STAT_1 0x3da
55 #define WHITE_VALUE 0x3F
56 #define BLACK_VALUE 0x00
57 #define OVERSCAN_VALUE 0x01
59 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
60 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override);
61 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
62 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
63 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
64 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
66 static CARD8 NVReadPVIO(xf86CrtcPtr crtc, CARD32 address)
68 ScrnInfoPtr pScrn = crtc->scrn;
69 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
70 NVPtr pNv = NVPTR(pScrn);
72 /* Only NV4x have two pvio ranges */
73 if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
74 return NV_RD08(pNv->PVIO1, address);
76 return NV_RD08(pNv->PVIO0, address);
80 static void NVWritePVIO(xf86CrtcPtr crtc, CARD32 address, CARD8 value)
82 ScrnInfoPtr pScrn = crtc->scrn;
83 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
84 NVPtr pNv = NVPTR(pScrn);
86 /* Only NV4x have two pvio ranges */
87 if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
88 NV_WR08(pNv->PVIO1, address, value);
90 NV_WR08(pNv->PVIO0, address, value);
94 static void NVWriteMiscOut(xf86CrtcPtr crtc, CARD8 value)
96 NVWritePVIO(crtc, VGA_MISC_OUT_W, value);
99 static CARD8 NVReadMiscOut(xf86CrtcPtr crtc)
101 return NVReadPVIO(crtc, VGA_MISC_OUT_R);
104 void NVWriteVGA(NVPtr pNv, int head, CARD8 index, CARD8 value)
106 volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
108 NV_WR08(pCRTCReg, CRTC_INDEX, index);
109 NV_WR08(pCRTCReg, CRTC_DATA, value);
112 CARD8 NVReadVGA(NVPtr pNv, int head, CARD8 index)
114 volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
116 NV_WR08(pCRTCReg, CRTC_INDEX, index);
117 return NV_RD08(pCRTCReg, CRTC_DATA);
120 /* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
121 * I suspect they in fact do nothing, but are merely a way to carry useful
122 * per-head variables around
126 * 0x00 index to the appropriate dcb entry (or 7f for inactive)
127 * 0x02 dcb entry's "or" value (or 00 for inactive)
128 * 0x03 bit0 set for dual link (LVDS, possibly elsewhere too)
129 * 0x0f laptop panel info - high nibble for PEXTDEV_BOOT strap
130 * low nibble for xlat strap value
133 void NVWriteVGACR5758(NVPtr pNv, int head, uint8_t index, uint8_t value)
135 NVWriteVGA(pNv, head, 0x57, index);
136 NVWriteVGA(pNv, head, 0x58, value);
139 uint8_t NVReadVGACR5758(NVPtr pNv, int head, uint8_t index)
141 NVWriteVGA(pNv, head, 0x57, index);
142 return NVReadVGA(pNv, head, 0x58);
145 void NVWriteVgaCrtc(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
147 ScrnInfoPtr pScrn = crtc->scrn;
148 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
149 NVPtr pNv = NVPTR(pScrn);
151 NVWriteVGA(pNv, nv_crtc->head, index, value);
154 CARD8 NVReadVgaCrtc(xf86CrtcPtr crtc, CARD8 index)
156 ScrnInfoPtr pScrn = crtc->scrn;
157 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
158 NVPtr pNv = NVPTR(pScrn);
160 return NVReadVGA(pNv, nv_crtc->head, index);
163 static void NVWriteVgaSeq(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
165 NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
166 NVWritePVIO(crtc, VGA_SEQ_DATA, value);
169 static CARD8 NVReadVgaSeq(xf86CrtcPtr crtc, CARD8 index)
171 NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
172 return NVReadPVIO(crtc, VGA_SEQ_DATA);
175 static void NVWriteVgaGr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
177 NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
178 NVWritePVIO(crtc, VGA_GRAPH_DATA, value);
181 static CARD8 NVReadVgaGr(xf86CrtcPtr crtc, CARD8 index)
183 NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
184 return NVReadPVIO(crtc, VGA_GRAPH_DATA);
188 static void NVWriteVgaAttr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
190 ScrnInfoPtr pScrn = crtc->scrn;
191 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
192 NVPtr pNv = NVPTR(pScrn);
193 volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
195 NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
196 if (nv_crtc->paletteEnabled)
200 NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
201 NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
204 static CARD8 NVReadVgaAttr(xf86CrtcPtr crtc, CARD8 index)
206 ScrnInfoPtr pScrn = crtc->scrn;
207 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
208 NVPtr pNv = NVPTR(pScrn);
209 volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
211 NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
212 if (nv_crtc->paletteEnabled)
216 NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
217 return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
220 void NVCrtcSetOwner(xf86CrtcPtr crtc)
222 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
223 ScrnInfoPtr pScrn = crtc->scrn;
224 NVPtr pNv = NVPTR(pScrn);
225 /* Non standard beheaviour required by NV11 */
227 uint8_t owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
228 ErrorF("pre-Owner: 0x%X\n", owner);
230 uint32_t pbus84 = nvReadMC(pNv, 0x1084);
231 ErrorF("pbus84: 0x%X\n", pbus84);
233 ErrorF("pbus84: 0x%X\n", pbus84);
234 nvWriteMC(pNv, 0x1084, pbus84);
236 /* The blob never writes owner to pcio1, so should we */
237 if (pNv->NVArch == 0x11) {
238 NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, 0xff);
240 NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, nv_crtc->crtc * 0x3);
241 owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
242 ErrorF("post-Owner: 0x%X\n", owner);
244 ErrorF("pNv pointer is NULL\n");
249 NVEnablePalette(xf86CrtcPtr crtc)
251 ScrnInfoPtr pScrn = crtc->scrn;
252 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
253 NVPtr pNv = NVPTR(pScrn);
254 volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
256 NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
257 NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
258 nv_crtc->paletteEnabled = TRUE;
262 NVDisablePalette(xf86CrtcPtr crtc)
264 ScrnInfoPtr pScrn = crtc->scrn;
265 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
266 NVPtr pNv = NVPTR(pScrn);
267 volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
269 NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
270 NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
271 nv_crtc->paletteEnabled = FALSE;
274 static void NVWriteVgaReg(xf86CrtcPtr crtc, CARD32 reg, CARD8 value)
276 ScrnInfoPtr pScrn = crtc->scrn;
277 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
278 NVPtr pNv = NVPTR(pScrn);
279 volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
281 NV_WR08(pCRTCReg, reg, value);
284 /* perform a sequencer reset */
285 static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
288 NVWriteVgaSeq(crtc, 0x00, 0x1);
290 NVWriteVgaSeq(crtc, 0x00, 0x3);
293 static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
298 tmp = NVReadVgaSeq(crtc, 0x1);
299 NVVgaSeqReset(crtc, TRUE);
300 NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
302 NVEnablePalette(crtc);
305 * Reenable sequencer, then turn on screen.
307 tmp = NVReadVgaSeq(crtc, 0x1);
308 NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20); /* reenable display */
309 NVVgaSeqReset(crtc, FALSE);
311 NVDisablePalette(crtc);
315 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool Lock)
319 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57);
320 cr11 = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE);
321 if (Lock) cr11 |= 0x80;
323 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE, cr11);
327 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
329 ScrnInfoPtr pScrn = crtc->scrn;
330 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
332 for (i = 0; i < xf86_config->num_output; i++) {
333 xf86OutputPtr output = xf86_config->output[i];
335 if (output->crtc == crtc) {
344 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
346 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
349 for (i = 0; i < xf86_config->num_crtc; i++) {
350 xf86CrtcPtr crtc = xf86_config->crtc[i];
351 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
352 if (nv_crtc->crtc == index)
360 * Calculate the Video Clock parameters for the PLL.
362 static void CalcVClock (
369 unsigned lowM, highM, highP;
370 unsigned DeltaNew, DeltaOld;
374 /* M: PLL reference frequency postscaler divider */
375 /* P: PLL VCO output postscaler divider */
376 /* N: PLL VCO postscaler setting */
378 DeltaOld = 0xFFFFFFFF;
380 VClk = (unsigned)clockIn;
382 /* Taken from Haiku, after someone with an NV28 had an issue */
383 switch(pNv->NVArch) {
389 } else if (VClk > 200000) {
391 } else if (VClk > 150000) {
402 } else if (VClk > 250000) {
410 for (P = 1; P <= highP; P++) {
412 if ((Freq >= 128000) && (Freq <= 350000)) {
413 for (M = lowM; M <= highM; M++) {
414 N = ((VClk << P) * M) / pNv->CrystalFreqKHz;
416 Freq = ((pNv->CrystalFreqKHz * N) / M) >> P;
418 DeltaNew = Freq - VClk;
420 DeltaNew = VClk - Freq;
422 if (DeltaNew < DeltaOld) {
423 *pllOut = (P << 16) | (N << 8) | M;
433 static void CalcVClock2Stage (
441 unsigned DeltaNew, DeltaOld;
444 unsigned lowM, highM, highP;
446 DeltaOld = 0xFFFFFFFF;
448 *pllBOut = 0x80000401; /* fixed at x4 for now */
450 VClk = (unsigned)clockIn;
452 /* Taken from Haiku, after someone with an NV28 had an issue */
453 switch(pNv->NVArch) {
459 } else if (VClk > 200000) {
461 } else if (VClk > 150000) {
472 } else if (VClk > 250000) {
480 for (P = 0; P <= highP; P++) {
482 if ((Freq >= 400000) && (Freq <= 1000000)) {
483 for (M = lowM; M <= highM; M++) {
484 N = ((VClk << P) * M) / (pNv->CrystalFreqKHz << 2);
485 if ((N >= 5) && (N <= 255)) {
486 Freq = (((pNv->CrystalFreqKHz << 2) * N) / M) >> P;
488 DeltaNew = Freq - VClk;
490 DeltaNew = VClk - Freq;
492 if (DeltaNew < DeltaOld) {
493 *pllOut = (P << 16) | (N << 8) | M;
503 /* BIG NOTE: modifying vpll1 and vpll2vpll2 does not work, what bit is the switch to allow it? */
505 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
506 /* They are only valid for NV4x, appearantly reordered for NV5x */
507 /* gpu pll: 0x4000 + 0x4004
508 * unknown pll: 0x4008 + 0x400c
509 * vpll1: 0x4010 + 0x4014
510 * vpll2: 0x4018 + 0x401c
511 * unknown pll: 0x4020 + 0x4024
512 * unknown pll: 0x4038 + 0x403c
513 * Some of the unknown's are probably memory pll's.
514 * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
515 * 1 and 2 refer to the registers of each pair. There is only one post divider.
516 * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
517 * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
518 * bit8: A switch that turns of the second divider and multiplier off.
519 * bit12: Also a switch, i haven't seen it yet.
520 * bit16-19: p-divider
521 * but 28-31: Something related to the mode that is used (see bit8).
522 * 2) bit0-7: m-divider (a)
523 * bit8-15: n-multiplier (a)
524 * bit16-23: m-divider (b)
525 * bit24-31: n-multiplier (b)
528 /* Modifying the gpu pll for example requires:
529 * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
530 * This is not needed for the vpll's which have their own bits.
536 uint32_t requested_clock,
537 uint32_t *given_clock,
546 uint32_t DeltaOld, DeltaNew;
548 /* We have 2 mulitpliers, 2 dividers and one post divider */
549 /* Note that p is only 4 bits */
550 uint32_t m1, m2, n1, n2, p;
551 uint32_t m1_best = 0, m2_best = 0, n1_best = 0, n2_best = 0, p_best = 0;
553 DeltaOld = 0xFFFFFFFF;
555 /* This is no solid limit, but a reasonable boundary */
556 if (requested_clock < 120000) {
558 /* Turn the second set of divider and multiplier off */
559 /* Neutral settings */
564 /* Fixed at x4 for the moment */
574 temp = 0.4975 * 250000;
577 while (requested_clock <= temp) {
582 /* The minimum clock after m1 is 3 Mhz, and the clock is 27 Mhz, so m_max = 9 */
583 /* The maximum clock is 25 Mhz */
584 for (m1 = 2; m1 <= 9; m1++) {
585 n1 = ((requested_clock << p) * m1)/(pNv->CrystalFreqKHz);
586 if (n1 > 0 && n1 <= 255) {
587 freq = ((pNv->CrystalFreqKHz * n1)/m1) >> p;
588 if (freq > requested_clock) {
589 DeltaNew = freq - requested_clock;
591 DeltaNew = requested_clock - freq;
593 if (DeltaNew < DeltaOld) {
603 for (p = 0; p <= 6; p++) {
604 /* Assuming a fixed 2nd stage */
605 freq = requested_clock << p;
606 /* The maximum output frequency of stage 2 is allowed to be between 400 Mhz and 1 GHz */
607 if (freq > 400000 && freq < 1000000) {
608 /* The minimum clock after m1 is 3 Mhz, and the clock is 27 Mhz, so m_max = 9 */
609 /* The maximum clock is 25 Mhz */
610 for (m1 = 2; m1 <= 9; m1++) {
611 n1 = ((requested_clock << p) * m1 * m2)/(pNv->CrystalFreqKHz * n2);
612 if (n1 >= 5 && n1 <= 255) {
613 freq = ((pNv->CrystalFreqKHz * n1 * n2)/(m1 * m2)) >> p;
614 if (freq > requested_clock) {
615 DeltaNew = freq - requested_clock;
617 DeltaNew = requested_clock - freq;
619 if (DeltaNew < DeltaOld) {
632 /* Bogus data, the same nvidia uses */
637 /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
638 /* Let's keep the special bits, if the bios already set them */
639 *pll_a = (special_bits << 30) | (p_best << 16) | (n1_best << 8) | (m1_best << 0);
640 *pll_b = (1 << 31) | (n2_best << 8) | (m2_best << 0);
644 *reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
646 *reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
650 *reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
652 *reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
657 ErrorF("vpll: n1 %d m1 %d p %d db1_ratio %d\n", n1_best, m1_best, p_best, *db1_ratio);
659 ErrorF("vpll: n1 %d n2 %d m1 %d m2 %d p %d db1_ratio %d\n", n1_best, n2_best, m1_best, m2_best, p_best, *db1_ratio);
663 static void nv40_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
665 state->vpll1_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
666 state->vpll1_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
667 state->vpll2_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
668 state->vpll2_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
669 state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
670 state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
671 state->reg580 = nvReadRAMDAC0(pNv, NV_RAMDAC_580);
672 state->reg594 = nvReadRAMDAC0(pNv, NV_RAMDAC_594);
675 static void nv40_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
677 CARD32 fp_debug_0[2];
679 fp_debug_0[0] = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
680 fp_debug_0[1] = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
682 /* The TMDS_PLL switch is on the actual ramdac */
683 if (state->crosswired) {
686 ErrorF("Crosswired pll state load\n");
692 if (state->vpll2_b) {
693 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0,
694 fp_debug_0[index[1]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
696 /* Wait for the situation to stabilise */
699 uint32_t reg_c040 = pNv->misc_info.reg_c040;
700 /* for vpll2 change bits 18 and 19 are disabled */
701 reg_c040 &= ~(0x3 << 18);
702 nvWriteMC(pNv, 0xc040, reg_c040);
704 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
705 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
707 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2_a);
708 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2_b);
710 ErrorF("writing pllsel %08X\n", state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
711 /* Let's keep the primary vpll off */
712 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
714 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
715 ErrorF("writing reg580 %08X\n", state->reg580);
717 /* We need to wait a while */
719 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
721 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[1]]);
723 /* Wait for the situation to stabilise */
727 if (state->vpll1_b) {
728 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0,
729 fp_debug_0[index[0]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
731 /* Wait for the situation to stabilise */
734 uint32_t reg_c040 = pNv->misc_info.reg_c040;
735 /* for vpll2 change bits 16 and 17 are disabled */
736 reg_c040 &= ~(0x3 << 16);
737 nvWriteMC(pNv, 0xc040, reg_c040);
739 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
740 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
742 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll1_a);
743 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpll1_b);
745 ErrorF("writing pllsel %08X\n", state->pllsel);
746 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
748 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
749 ErrorF("writing reg580 %08X\n", state->reg580);
751 /* We need to wait a while */
753 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
755 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[0]]);
757 /* Wait for the situation to stabilise */
761 ErrorF("writing sel_clk %08X\n", state->sel_clk);
762 nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
764 ErrorF("writing reg594 %08X\n", state->reg594);
765 nvWriteRAMDAC0(pNv, NV_RAMDAC_594, state->reg594);
768 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
770 state->vpll = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
772 state->vpll2 = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
774 if(pNv->twoStagePLL) {
775 state->vpllB = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
776 state->vpll2B = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
778 state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
779 state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
783 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
787 ErrorF("writing vpll2 %08X\n", state->vpll2);
788 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2);
790 if(pNv->twoStagePLL) {
791 ErrorF("writing vpll2B %08X\n", state->vpll2B);
792 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2B);
795 ErrorF("writing pllsel %08X\n", state->pllsel);
796 /* Let's keep the primary vpll off */
797 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
801 ErrorF("writing vpll %08X\n", state->vpll);
802 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll);
803 if(pNv->twoStagePLL) {
804 ErrorF("writing vpllB %08X\n", state->vpllB);
805 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpllB);
808 ErrorF("writing pllsel %08X\n", state->pllsel);
809 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
812 ErrorF("writing sel_clk %08X\n", state->sel_clk);
813 nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
816 #define IS_NV44P (pNv->NVArch >= 0x44 ? 1 : 0)
817 #define SEL_CLK_OFFSET (16 - 4 * !nv_output->preferred_output * (1 + IS_NV44P))
818 #define SEL_CLK_OFFSET_INV (16 - 4 * nv_output->preferred_output * (1 + IS_NV44P))
821 * Calculate extended mode parameters (SVGA) and save in a
822 * mode state structure.
823 * State is not specific to a single crtc, but shared.
825 void nv_crtc_calc_state_ext(
828 int DisplayWidth, /* Does this change after setting the mode? */
835 ScrnInfoPtr pScrn = crtc->scrn;
836 uint32_t pixelDepth, VClk = 0;
838 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
839 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
841 NVPtr pNv = NVPTR(pScrn);
842 RIVA_HW_STATE *state, *sv_state;
843 int num_crtc_enabled, i;
845 state = &pNv->ModeReg;
846 sv_state = &pNv->SavedReg;
848 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
850 xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
851 NVOutputPrivatePtr nv_output = NULL;
853 nv_output = output->driver_private;
857 * Extended RIVA registers.
859 pixelDepth = (bpp + 1)/8;
860 if (pNv->Architecture == NV_ARCH_40) {
861 /* Does register 0x580 already have a value? */
862 if (!state->reg580) {
863 state->reg580 = pNv->misc_info.ramdac_0_reg_580;
865 if (nv_crtc->head == 1) {
866 CalculateVClkNV4x(pNv, dotClock, &VClk, &state->vpll2_a, &state->vpll2_b, &state->reg580, &state->db1_ratio[1], FALSE, (sv_state->vpll2_a >> 30));
868 CalculateVClkNV4x(pNv, dotClock, &VClk, &state->vpll1_a, &state->vpll1_b, &state->reg580, &state->db1_ratio[0], TRUE, (sv_state->vpll1_a >> 30));
870 } else if (pNv->twoStagePLL) {
871 CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB, pNv);
873 CalcVClock(dotClock, &VClk, &state->pll, pNv);
876 switch (pNv->Architecture) {
878 nv4UpdateArbitrationSettings(VClk,
880 &(state->arbitration0),
881 &(state->arbitration1),
883 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
884 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
885 if (flags & V_DBLSCAN)
886 regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
887 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
888 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
889 state->config = 0x00001114;
890 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
896 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
897 ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
898 state->arbitration0 = 128;
899 state->arbitration1 = 0x0480;
900 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
901 ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
902 nForceUpdateArbitrationSettings(VClk,
904 &(state->arbitration0),
905 &(state->arbitration1),
907 } else if (pNv->Architecture < NV_ARCH_30) {
908 nv10UpdateArbitrationSettings(VClk,
910 &(state->arbitration0),
911 &(state->arbitration1),
914 nv30UpdateArbitrationSettings(pNv,
915 &(state->arbitration0),
916 &(state->arbitration1));
919 CursorStart = pNv->Cursor->offset;
921 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
922 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
923 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
925 if (flags & V_DBLSCAN)
926 regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
928 state->config = nvReadFB(pNv, NV_PFB_CFG0);
929 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
933 /* okay do we have 2 CRTCs running ? */
934 num_crtc_enabled = 0;
935 for (i = 0; i < xf86_config->num_crtc; i++) {
936 if (xf86_config->crtc[i]->enabled) {
941 ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
943 if (pNv->Architecture < NV_ARCH_40) {
944 /* We need this before the next code */
945 if (nv_crtc->head == 1) {
946 state->vpll2 = state->pll;
947 state->vpll2B = state->pllB;
949 state->vpll = state->pll;
950 state->vpllB = state->pllB;
954 if (pNv->Architecture == NV_ARCH_40) {
955 /* This register is only used on the primary ramdac */
956 /* This seems to be needed to select the proper clocks, otherwise bad things happen */
959 state->sel_clk = pNv->misc_info.sel_clk & ~(0xfff << 8);
961 /* There are a few possibilities:
962 * Early NV4x cards: 0x41000 for example
963 * Later NV4x cards: 0x40100 for example
964 * The lower entry is the first bus, the higher entry is the second bus
967 * 2: Unknown, similar to 4?
971 /* This won't work when tv-out's come into play */
972 state->sel_clk &= ~(0xf << SEL_CLK_OFFSET);
973 if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
974 if (nv_crtc->head == 1) { /* secondary clock */
975 state->sel_clk |= (0x4 << SEL_CLK_OFFSET);
976 /* Does the other output occupy the same clock? -> Switch it to primary clock */
977 if ((state->sel_clk & (0xf << SEL_CLK_OFFSET_INV)) == (0x4 << SEL_CLK_OFFSET_INV)) {
978 state->sel_clk &= ~(0xf << SEL_CLK_OFFSET_INV);
979 state->sel_clk |= (0x1 << SEL_CLK_OFFSET_INV);
981 } else { /* primary clock */
982 state->sel_clk |= (0x1 << SEL_CLK_OFFSET);
983 /* Does the other output occupy the same clock? -> Switch it to secondary clock */
984 if ((state->sel_clk & (0xf << SEL_CLK_OFFSET_INV)) == (0x1 << SEL_CLK_OFFSET_INV)) {
985 state->sel_clk &= ~(0xf << SEL_CLK_OFFSET_INV);
986 state->sel_clk |= (0x4 << SEL_CLK_OFFSET_INV);
991 /* The hardware gets upset if for example 0x00100 is set instead of 0x40100 */
992 if ((state->sel_clk & (0xff << 8)) && !(state->sel_clk & (0xf << 16))) {
993 if ((state->sel_clk & (0xf << (12 - 4*IS_NV44P))) == (0x1 << (12 - 4*IS_NV44P))) {
994 state->sel_clk |= (0x4 << 16);
996 state->sel_clk |= (0x1 << 16);
1000 /* Are we crosswired? */
1001 if (output && nv_crtc->head != nv_output->preferred_output &&
1002 (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
1003 state->crosswired = TRUE;
1004 } else if (output && nv_crtc->head != nv_output->preferred_output) {
1005 state->crosswired = FALSE;
1007 state->crosswired = FALSE;
1010 if (nv_crtc->head == 1) {
1011 if (state->db1_ratio[1])
1012 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1013 } else if (nv_crtc->head == 0) {
1014 if (state->db1_ratio[0])
1015 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1018 /* This seems true for nv34 */
1019 state->sel_clk = 0x0;
1020 state->crosswired = FALSE;
1023 if (nv_crtc->head == 1) {
1024 if (!state->db1_ratio[1]) {
1025 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1027 state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1029 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
1031 if (pNv->Architecture < NV_ARCH_40)
1032 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
1034 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
1035 if (!state->db1_ratio[0]) {
1036 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1038 state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1042 /* The blob uses this always, so let's do the same */
1043 if (pNv->Architecture == NV_ARCH_40) {
1044 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
1047 /* The primary output doesn't seem to care */
1048 if (nv_output->preferred_output == 1) { /* This is the "output" */
1049 /* non-zero values are for analog, don't know about tv-out and the likes */
1050 if (output && nv_output->type != OUTPUT_ANALOG) {
1051 state->reg594 = 0x0;
1053 /* More values exist, but they seem related to the 3rd dac (tv-out?) somehow */
1054 /* bit 16-19 are bits that are set on some G70 cards */
1055 /* Those bits are also set to the 3rd OUTPUT register */
1056 if (nv_crtc->head == 1) {
1057 state->reg594 = 0x101;
1059 state->reg594 = 0x1;
1064 regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
1065 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
1066 if (pNv->Architecture >= NV_ARCH_30) {
1067 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
1070 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
1071 regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
1075 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
1077 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1078 ScrnInfoPtr pScrn = crtc->scrn;
1079 NVPtr pNv = NVPTR(pScrn);
1080 unsigned char seq1 = 0, crtc17 = 0;
1081 unsigned char crtc1A;
1083 ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->crtc, mode);
1085 NVCrtcSetOwner(crtc);
1087 crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
1089 case DPMSModeStandby:
1090 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
1095 case DPMSModeSuspend:
1096 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
1102 /* Screen: Off; HSync: Off, VSync: Off */
1109 /* Screen: On; HSync: On, VSync: On */
1115 NVVgaSeqReset(crtc, TRUE);
1116 /* Each head has it's own sequencer, so we can turn it off when we want */
1117 seq1 |= (NVReadVgaSeq(crtc, 0x01) & ~0x20);
1118 NVWriteVgaSeq(crtc, 0x1, seq1);
1119 crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
1121 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
1122 NVVgaSeqReset(crtc, FALSE);
1124 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
1126 /* I hope this is the right place */
1127 if (crtc->enabled && mode == DPMSModeOn) {
1128 pNv->crtc_active[nv_crtc->head] = TRUE;
1130 pNv->crtc_active[nv_crtc->head] = FALSE;
1135 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
1136 DisplayModePtr adjusted_mode)
1138 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1139 ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->crtc);
1141 xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1142 NVOutputPrivatePtr nv_output = NULL;
1144 nv_output = output->driver_private;
1147 /* For internal panels and gpu scaling on DVI we need the native mode */
1148 if (output && ((nv_output->type == OUTPUT_LVDS) || (nv_output->scaling_mode > 0 && (nv_output->type == OUTPUT_TMDS)))) {
1149 adjusted_mode->HDisplay = nv_output->native_mode->HDisplay;
1150 adjusted_mode->HSkew = nv_output->native_mode->HSkew;
1151 adjusted_mode->HSyncStart = nv_output->native_mode->HSyncStart;
1152 adjusted_mode->HSyncEnd = nv_output->native_mode->HSyncEnd;
1153 adjusted_mode->HTotal = nv_output->native_mode->HTotal;
1154 adjusted_mode->VDisplay = nv_output->native_mode->VDisplay;
1155 adjusted_mode->VScan = nv_output->native_mode->VScan;
1156 adjusted_mode->VSyncStart = nv_output->native_mode->VSyncStart;
1157 adjusted_mode->VSyncEnd = nv_output->native_mode->VSyncEnd;
1158 adjusted_mode->VTotal = nv_output->native_mode->VTotal;
1159 adjusted_mode->Clock = nv_output->native_mode->Clock;
1161 xf86SetModeCrtc(adjusted_mode, INTERLACE_HALVE_V);
1168 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1170 ScrnInfoPtr pScrn = crtc->scrn;
1171 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1173 NVPtr pNv = NVPTR(pScrn);
1174 NVFBLayout *pLayout = &pNv->CurrentLayout;
1175 int depth = pScrn->depth;
1177 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1179 /* Calculate our timings */
1180 int horizDisplay = (mode->CrtcHDisplay >> 3) - 1;
1181 int horizStart = (mode->CrtcHSyncStart >> 3) - 1;
1182 int horizEnd = (mode->CrtcHSyncEnd >> 3) - 1;
1183 int horizTotal = (mode->CrtcHTotal >> 3) - 5;
1184 int horizBlankStart = (mode->CrtcHDisplay >> 3) - 1;
1185 int horizBlankEnd = (mode->CrtcHTotal >> 3) - 1;
1186 int vertDisplay = mode->CrtcVDisplay - 1;
1187 int vertStart = mode->CrtcVSyncStart - 1;
1188 int vertEnd = mode->CrtcVSyncEnd - 1;
1189 int vertTotal = mode->CrtcVTotal - 2;
1190 int vertBlankStart = mode->CrtcVDisplay - 1;
1191 int vertBlankEnd = mode->CrtcVTotal - 1;
1195 xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1196 NVOutputPrivatePtr nv_output = NULL;
1198 nv_output = output->driver_private;
1200 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1204 ErrorF("Mode clock: %d\n", mode->Clock);
1205 ErrorF("Adjusted mode clock: %d\n", adjusted_mode->Clock);
1207 /* Reverted to what nv did, because that works for all resolutions on flatpanels */
1209 vertStart = vertTotal - 3;
1210 vertEnd = vertTotal - 2;
1211 vertBlankStart = vertStart;
1212 horizStart = horizTotal - 5;
1213 horizEnd = horizTotal - 2;
1214 horizBlankEnd = horizTotal + 4;
1215 if (pNv->overlayAdaptor) {
1216 /* This reportedly works around Xv some overlay bandwidth problems*/
1221 if(mode->Flags & V_INTERLACE)
1224 ErrorF("horizDisplay: 0x%X \n", horizDisplay);
1225 ErrorF("horizStart: 0x%X \n", horizStart);
1226 ErrorF("horizEnd: 0x%X \n", horizEnd);
1227 ErrorF("horizTotal: 0x%X \n", horizTotal);
1228 ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
1229 ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
1230 ErrorF("vertDisplay: 0x%X \n", vertDisplay);
1231 ErrorF("vertStart: 0x%X \n", vertStart);
1232 ErrorF("vertEnd: 0x%X \n", vertEnd);
1233 ErrorF("vertTotal: 0x%X \n", vertTotal);
1234 ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
1235 ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
1238 * compute correct Hsync & Vsync polarity
1240 if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
1241 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
1243 regp->MiscOutReg = 0x23;
1244 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
1245 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
1247 int VDisplay = mode->VDisplay;
1248 if (mode->Flags & V_DBLSCAN)
1250 if (mode->VScan > 1)
1251 VDisplay *= mode->VScan;
1252 if (VDisplay < 400) {
1253 regp->MiscOutReg = 0xA3; /* +hsync -vsync */
1254 } else if (VDisplay < 480) {
1255 regp->MiscOutReg = 0x63; /* -hsync +vsync */
1256 } else if (VDisplay < 768) {
1257 regp->MiscOutReg = 0xE3; /* -hsync -vsync */
1259 regp->MiscOutReg = 0x23; /* +hsync +vsync */
1263 regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
1269 regp->Sequencer[0] = 0x02;
1271 regp->Sequencer[0] = 0x00;
1273 /* 0x20 disables the sequencer */
1274 if (mode->Flags & V_CLKDIV2) {
1275 regp->Sequencer[1] = 0x29;
1277 regp->Sequencer[1] = 0x21;
1280 regp->Sequencer[2] = 1 << BIT_PLANE;
1282 regp->Sequencer[2] = 0x0F;
1283 regp->Sequencer[3] = 0x00; /* Font select */
1286 regp->Sequencer[4] = 0x06; /* Misc */
1288 regp->Sequencer[4] = 0x0E; /* Misc */
1294 regp->CRTC[NV_VGA_CRTCX_HTOTAL] = Set8Bits(horizTotal);
1295 regp->CRTC[NV_VGA_CRTCX_HDISPE] = Set8Bits(horizDisplay);
1296 regp->CRTC[NV_VGA_CRTCX_HBLANKS] = Set8Bits(horizBlankStart);
1297 regp->CRTC[NV_VGA_CRTCX_HBLANKE] = SetBitField(horizBlankEnd,4:0,4:0)
1299 regp->CRTC[NV_VGA_CRTCX_HSYNCS] = Set8Bits(horizStart);
1300 regp->CRTC[NV_VGA_CRTCX_HSYNCE] = SetBitField(horizBlankEnd,5:5,7:7)
1301 | SetBitField(horizEnd,4:0,4:0);
1302 regp->CRTC[NV_VGA_CRTCX_VTOTAL] = SetBitField(vertTotal,7:0,7:0);
1303 regp->CRTC[NV_VGA_CRTCX_OVERFLOW] = SetBitField(vertTotal,8:8,0:0)
1304 | SetBitField(vertDisplay,8:8,1:1)
1305 | SetBitField(vertStart,8:8,2:2)
1306 | SetBitField(vertBlankStart,8:8,3:3)
1308 | SetBitField(vertTotal,9:9,5:5)
1309 | SetBitField(vertDisplay,9:9,6:6)
1310 | SetBitField(vertStart,9:9,7:7);
1311 regp->CRTC[NV_VGA_CRTCX_PRROWSCN] = 0x00;
1312 regp->CRTC[NV_VGA_CRTCX_MAXSCLIN] = SetBitField(vertBlankStart,9:9,5:5)
1314 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00);
1315 regp->CRTC[NV_VGA_CRTCX_VGACURCTRL] = 0x00;
1316 regp->CRTC[0xb] = 0x00;
1317 regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00;
1318 regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
1319 regp->CRTC[0xe] = 0x00;
1320 regp->CRTC[0xf] = 0x00;
1321 regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
1322 regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
1323 regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
1324 regp->CRTC[0x14] = 0x00;
1325 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
1326 regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
1327 regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
1328 /* 0x80 enables the sequencer, we don't want that */
1330 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xE3 & ~0x80;
1332 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80;
1334 regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
1337 * Some extended CRTC registers (they are not saved with the rest of the vga regs).
1340 regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
1341 | SetBitField(vertBlankStart,10:10,3:3)
1342 | SetBitField(vertStart,10:10,2:2)
1343 | SetBitField(vertDisplay,10:10,1:1)
1344 | SetBitField(vertTotal,10:10,0:0);
1346 regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
1347 | SetBitField(horizDisplay,8:8,1:1)
1348 | SetBitField(horizBlankStart,8:8,2:2)
1349 | SetBitField(horizStart,8:8,3:3);
1351 regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
1352 | SetBitField(vertDisplay,11:11,2:2)
1353 | SetBitField(vertStart,11:11,4:4)
1354 | SetBitField(vertBlankStart,11:11,6:6);
1356 if(mode->Flags & V_INTERLACE) {
1357 horizTotal = (horizTotal >> 1) & ~1;
1358 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
1359 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
1361 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff; /* interlace off */
1365 * Theory resumes here....
1369 * Graphics Display Controller
1371 regp->Graphics[0] = 0x00;
1372 regp->Graphics[1] = 0x00;
1373 regp->Graphics[2] = 0x00;
1374 regp->Graphics[3] = 0x00;
1376 regp->Graphics[4] = BIT_PLANE;
1377 regp->Graphics[5] = 0x00;
1379 regp->Graphics[4] = 0x00;
1381 regp->Graphics[5] = 0x02;
1383 regp->Graphics[5] = 0x40;
1386 regp->Graphics[6] = 0x05; /* only map 64k VGA memory !!!! */
1387 regp->Graphics[7] = 0x0F;
1388 regp->Graphics[8] = 0xFF;
1390 /* I ditched the mono stuff */
1391 regp->Attribute[0] = 0x00; /* standard colormap translation */
1392 regp->Attribute[1] = 0x01;
1393 regp->Attribute[2] = 0x02;
1394 regp->Attribute[3] = 0x03;
1395 regp->Attribute[4] = 0x04;
1396 regp->Attribute[5] = 0x05;
1397 regp->Attribute[6] = 0x06;
1398 regp->Attribute[7] = 0x07;
1399 regp->Attribute[8] = 0x08;
1400 regp->Attribute[9] = 0x09;
1401 regp->Attribute[10] = 0x0A;
1402 regp->Attribute[11] = 0x0B;
1403 regp->Attribute[12] = 0x0C;
1404 regp->Attribute[13] = 0x0D;
1405 regp->Attribute[14] = 0x0E;
1406 regp->Attribute[15] = 0x0F;
1407 /* These two below are non-vga */
1408 regp->Attribute[16] = 0x01;
1409 regp->Attribute[17] = 0x00;
1410 regp->Attribute[18] = 0x0F;
1411 regp->Attribute[19] = 0x00;
1412 regp->Attribute[20] = 0x00;
1415 #define MAX_H_VALUE(i) ((0x1ff + i) << 3)
1416 #define MAX_V_VALUE(i) ((0xfff + i) << 0)
1419 * Sets up registers for the given mode/adjusted_mode pair.
1421 * The clocks, CRTCs and outputs attached to this CRTC must be off.
1423 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1424 * be easily turned on/off after this.
1427 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1429 ScrnInfoPtr pScrn = crtc->scrn;
1430 NVPtr pNv = NVPTR(pScrn);
1431 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1432 NVFBLayout *pLayout = &pNv->CurrentLayout;
1433 NVCrtcRegPtr regp, savep;
1437 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1438 savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1440 xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1441 NVOutputPrivatePtr nv_output = NULL;
1443 nv_output = output->driver_private;
1445 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1449 /* Registers not directly related to the (s)vga mode */
1451 /* bit2 = 0 -> fine pitched crtc granularity */
1452 /* The rest disables double buffering on CRTC access */
1453 regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
1455 if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
1456 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1457 if (nv_crtc->head == 0) {
1458 regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1462 regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0) | (1 << 1);
1465 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
1466 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
1469 /* Sometimes 0x10 is used, what is this? */
1470 regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1471 /* Some kind of tmds switch for older cards */
1472 if (pNv->Architecture < NV_ARCH_40) {
1473 regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
1477 * Initialize DAC palette.
1479 if(pLayout->bitsPerPixel != 8 ) {
1480 for (i = 0; i < 256; i++) {
1482 regp->DAC[(i*3)+1] = i;
1483 regp->DAC[(i*3)+2] = i;
1488 * Calculate the extended registers.
1491 if(pLayout->depth < 24) {
1497 if(pNv->Architecture >= NV_ARCH_10) {
1498 pNv->CURSOR = (CARD32 *)pNv->Cursor->map;
1501 /* What is the meaning of this register? */
1502 /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1503 regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
1505 /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1506 /* But what are those special conditions? */
1507 if (pNv->Architecture <= NV_ARCH_30) {
1509 if(nv_crtc->head == 1) {
1510 regp->head |= NV_CRTC_FSEL_FPP1;
1511 } else if (pNv->twoHeads) {
1512 regp->head |= NV_CRTC_FSEL_FPP2;
1516 /* Some G70 cards have either FPP1 or FPP2 set, copy this if it's already present */
1517 if (nv_crtc->head == 1 && pNv->NVArch > 0x44) {
1518 regp->head |= savep->head & (NV_CRTC_FSEL_FPP1 | NV_CRTC_FSEL_FPP2);
1522 /* Except for rare conditions I2C is enabled on the primary crtc */
1523 if (nv_crtc->head == 0) {
1524 if (pNv->overlayAdaptor) {
1525 regp->head |= NV_CRTC_FSEL_OVERLAY;
1527 regp->head |= NV_CRTC_FSEL_I2C;
1530 /* This is not what nv does, but it is what the blob does (for nv4x at least) */
1531 /* This fixes my cursor corruption issue */
1532 regp->cursorConfig = 0x0;
1533 if(mode->Flags & V_DBLSCAN)
1534 regp->cursorConfig |= (1 << 4);
1535 if (pNv->alphaCursor) {
1536 /* bit28 means we go into alpha blend mode and not rely on the current ROP */
1537 regp->cursorConfig |= 0x14011000;
1539 regp->cursorConfig |= 0x02000000;
1542 /* Unblock some timings */
1543 regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1544 regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1546 /* What is the purpose of this register? */
1547 if (nv_crtc->head == 1) {
1548 regp->CRTC[NV_VGA_CRTCX_26] = 0x14;
1550 regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1553 /* 0x00 is disabled, 0x22 crt and 0x88 dfp */
1556 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1558 /* 0x20 is also seen sometimes, why? */
1559 if (nv_crtc->head == 1) {
1560 regp->CRTC[NV_VGA_CRTCX_3B] = 0x24;
1562 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1566 /* These values seem to vary */
1567 if (nv_crtc->head == 1) {
1568 regp->CRTC[NV_VGA_CRTCX_3C] = 0x0;
1570 regp->CRTC[NV_VGA_CRTCX_3C] = 0x70;
1573 /* 0x80 seems to be used very often, if not always */
1574 regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1576 if (nv_crtc->head == 1) {
1577 regp->CRTC[NV_VGA_CRTCX_4B] = 0x0;
1579 regp->CRTC[NV_VGA_CRTCX_4B] = 0x1;
1583 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x80;
1585 /* Are these(0x55 and 0x56) also timing related registers, since disabling them does nothing? */
1586 regp->CRTC[NV_VGA_CRTCX_55] = 0x0;
1588 /* Common values like 0x14 and 0x04 are converted to 0x10 and 0x00 */
1589 regp->CRTC[NV_VGA_CRTCX_56] = 0x0;
1591 /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1*/
1592 if (nv_crtc->head == 1) {
1593 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52;
1595 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52 + 4;
1598 /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1599 regp->unk81c = nvReadCRTC0(pNv, NV_CRTC_081C);
1601 regp->unk830 = mode->CrtcVDisplay - 3;
1602 regp->unk834 = mode->CrtcVDisplay - 1;
1604 /* This is what the blob does */
1605 regp->unk850 = nvReadCRTC(pNv, 0, NV_CRTC_0850);
1607 /* Never ever modify gpio, unless you know very well what you're doing */
1608 regp->gpio = nvReadCRTC(pNv, 0, NV_CRTC_GPIO);
1610 /* Switch to non-vga mode (the so called HSYNC mode) */
1614 * Calculate the state that is common to all crtc's (stored in the state struct).
1616 ErrorF("crtc %d %d %d\n", nv_crtc->crtc, mode->CrtcHDisplay, pScrn->displayWidth);
1617 nv_crtc_calc_state_ext(crtc,
1619 pScrn->displayWidth,
1622 adjusted_mode->Clock,
1625 /* Enable slaved mode */
1627 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1632 nv_crtc_mode_set_ramdac_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1634 ScrnInfoPtr pScrn = crtc->scrn;
1635 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1637 NVPtr pNv = NVPTR(pScrn);
1638 NVFBLayout *pLayout = &pNv->CurrentLayout;
1640 Bool is_lvds = FALSE;
1641 float aspect_ratio, panel_ratio;
1642 uint32_t h_scale, v_scale;
1644 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1646 xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1647 NVOutputPrivatePtr nv_output = NULL;
1649 nv_output = output->driver_private;
1651 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1654 if (nv_output->type == OUTPUT_LVDS)
1659 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
1660 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
1661 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HDisplay;
1662 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
1663 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
1664 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
1665 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
1667 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
1668 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
1669 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VDisplay;
1670 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
1671 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
1672 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
1673 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
1675 ErrorF("Horizontal:\n");
1676 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
1677 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
1678 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
1679 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
1680 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
1681 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
1682 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
1684 ErrorF("Vertical:\n");
1685 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
1686 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
1687 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
1688 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
1689 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
1690 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
1691 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
1695 * bit0: positive vsync
1696 * bit4: positive hsync
1697 * bit8: enable center mode
1698 * bit9: enable native mode
1699 * bit26: a bit sometimes seen on some g70 cards
1700 * bit31: set for dual link LVDS
1701 * nv10reg contains a few more things, but i don't quite get what it all means.
1704 if (pNv->Architecture >= NV_ARCH_30) {
1705 regp->fp_control = 0x01100000;
1707 regp->fp_control = 0x00000000;
1711 regp->fp_control |= (1 << 28);
1713 regp->fp_control |= (2 << 28);
1714 if (pNv->Architecture < NV_ARCH_30)
1715 regp->fp_control |= (1 << 24);
1718 if (is_lvds && pNv->VBIOS.fp.dual_link) {
1719 regp->fp_control |= (8 << 28);
1721 /* If the special bit exists, it exists on both ramdac's */
1722 regp->fp_control |= nvReadRAMDAC0(pNv, NV_RAMDAC_FP_CONTROL) & (1 << 26);
1726 if (nv_output->scaling_mode == 0) { /* panel needs to scale */
1727 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
1728 /* This is also true for panel scaling, so we must put the panel scale check first */
1729 } else if (mode->Clock == adjusted_mode->Clock) { /* native mode */
1730 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
1731 } else { /* gpu needs to scale */
1732 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1736 /* Deal with vsync/hsync polarity */
1738 if (adjusted_mode->Flags & V_PVSYNC) {
1739 regp->fp_control |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
1742 if (adjusted_mode->Flags & V_PHSYNC) {
1743 regp->fp_control |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
1746 /* The blob doesn't always do this, but often */
1747 regp->fp_control |= NV_RAMDAC_FP_CONTROL_VSYNC_DISABLE;
1748 regp->fp_control |= NV_RAMDAC_FP_CONTROL_HSYNC_DISABLE;
1752 ErrorF("Pre-panel scaling\n");
1753 ErrorF("panel-size:%dx%d\n", nv_output->fpWidth, nv_output->fpHeight);
1754 panel_ratio = (nv_output->fpWidth)/(float)(nv_output->fpHeight);
1755 ErrorF("panel_ratio=%f\n", panel_ratio);
1756 aspect_ratio = (mode->HDisplay)/(float)(mode->VDisplay);
1757 ErrorF("aspect_ratio=%f\n", aspect_ratio);
1758 /* Scale factors is the so called 20.12 format, taken from Haiku */
1759 h_scale = ((1 << 12) * mode->HDisplay)/nv_output->fpWidth;
1760 v_scale = ((1 << 12) * mode->VDisplay)/nv_output->fpHeight;
1761 ErrorF("h_scale=%d\n", h_scale);
1762 ErrorF("v_scale=%d\n", v_scale);
1764 /* This can override HTOTAL and VTOTAL */
1767 /* We want automatic scaling */
1770 regp->fp_hvalid_start = 0;
1771 regp->fp_hvalid_end = (nv_output->fpWidth - 1);
1773 regp->fp_vvalid_start = 0;
1774 regp->fp_vvalid_end = (nv_output->fpHeight - 1);
1776 /* 0 = panel scaling */
1777 if (nv_output->scaling_mode == 0) {
1778 ErrorF("Flat panel is doing the scaling.\n");
1780 ErrorF("GPU is doing the scaling.\n");
1782 /* 1 = fullscale gpu */
1783 /* 2 = aspect ratio scaling */
1784 /* 3 = no scaling */
1785 if (nv_output->scaling_mode == 2) {
1786 /* GPU scaling happens automaticly at a ratio of 1.33 */
1787 /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
1788 if (h_scale != (1 << 12) && (panel_ratio > (aspect_ratio + 0.10))) {
1791 ErrorF("Scaling resolution on a widescreen panel\n");
1793 /* Scaling in both directions needs to the same */
1796 /* Set a new horizontal scale factor and enable testmode (bit12) */
1797 regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
1799 diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
1800 regp->fp_hvalid_start = diff/2;
1801 regp->fp_hvalid_end = nv_output->fpWidth - (diff/2) - 1;
1804 /* Same scaling, just for panels with aspect ratio's smaller than 1 */
1805 if (v_scale != (1 << 12) && (panel_ratio < (aspect_ratio - 0.10))) {
1808 ErrorF("Scaling resolution on a portrait panel\n");
1810 /* Scaling in both directions needs to the same */
1813 /* Set a new vertical scale factor and enable testmode (bit28) */
1814 regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
1816 diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
1817 regp->fp_vvalid_start = diff/2;
1818 regp->fp_vvalid_end = nv_output->fpHeight - (diff/2) - 1;
1823 ErrorF("Post-panel scaling\n");
1826 if (pNv->Architecture >= NV_ARCH_10) {
1827 /* Bios and blob don't seem to do anything (else) */
1828 regp->nv10_cursync = (1<<25);
1831 /* These are the common blob values, minus a few fp specific bit's */
1832 /* Let's keep the TMDS pll and fpclock running in all situations */
1833 regp->debug_0 = 0x1101100;
1835 if (is_fp && nv_output->scaling_mode != 3) { /* !no_scale mode */
1836 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_XSCALE_ENABLED;
1837 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_YSCALE_ENABLED;
1838 } else if (is_fp) { /* no_scale mode, so we must center it */
1841 diff = nv_output->fpWidth - mode->HDisplay;
1842 regp->fp_hvalid_start = diff/2;
1843 regp->fp_hvalid_end = (nv_output->fpWidth - diff/2 - 1);
1845 diff = nv_output->fpHeight - mode->VDisplay;
1846 regp->fp_vvalid_start = diff/2;
1847 regp->fp_vvalid_end = (nv_output->fpHeight - diff/2 - 1);
1850 /* Is this crtc bound or output bound? */
1851 /* Does the bios TMDS script try to change this sometimes? */
1853 /* I am not completely certain, but seems to be set only for dfp's */
1854 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED;
1858 ErrorF("output %d debug_0 %08X\n", nv_output->preferred_output, regp->debug_0);
1860 /* Flatpanel support needs at least a NV10 */
1862 /* The blob does this differently. */
1863 /* TODO: Find out what precisely and why. */
1865 if (pNv->NVArch == 0x11) {
1866 regp->dither = 0x00010000;
1868 regp->dither = 0x00000001;
1873 /* Kindly borrowed from haiku driver */
1874 /* bit4 and bit5 activate indirect mode trough color palette */
1875 switch (pLayout->depth) {
1878 regp->general = 0x00101130;
1882 regp->general = 0x00100130;
1886 regp->general = 0x00101100;
1890 if (pNv->alphaCursor) {
1891 /* PIPE_LONG mode, something to do with the size of the cursor? */
1892 regp->general |= (1<<29);
1895 /* Some values the blob sets */
1896 /* This may apply to the real ramdac that is being used (for crosswired situations) */
1897 /* Nevertheless, it's unlikely to cause many problems, since the values are equal for both */
1898 regp->unk_a20 = 0x0;
1899 regp->unk_a24 = 0xfffff;
1900 regp->unk_a34 = 0x1;
1904 * Sets up registers for the given mode/adjusted_mode pair.
1906 * The clocks, CRTCs and outputs attached to this CRTC must be off.
1908 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1909 * be easily turned on/off after this.
1912 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
1913 DisplayModePtr adjusted_mode,
1916 ScrnInfoPtr pScrn = crtc->scrn;
1917 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1918 NVPtr pNv = NVPTR(pScrn);
1920 ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->crtc);
1922 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->crtc);
1923 xf86PrintModeline(pScrn->scrnIndex, mode);
1924 NVCrtcSetOwner(crtc);
1926 nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
1927 nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
1928 nv_crtc_mode_set_ramdac_regs(crtc, mode, adjusted_mode);
1931 NVCrtcLockUnlock(crtc, FALSE);
1933 NVVgaProtect(crtc, TRUE);
1934 nv_crtc_load_state_ext(crtc, &pNv->ModeReg, FALSE);
1935 nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
1936 if (pNv->Architecture == NV_ARCH_40) {
1937 nv40_crtc_load_state_pll(pNv, &pNv->ModeReg);
1939 nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
1941 nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
1943 NVVgaProtect(crtc, FALSE);
1945 NVCrtcSetBase(crtc, x, y);
1947 #if X_BYTE_ORDER == X_BIG_ENDIAN
1948 /* turn on LFB swapping */
1952 tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
1954 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
1959 void nv_crtc_save(xf86CrtcPtr crtc)
1961 ScrnInfoPtr pScrn = crtc->scrn;
1962 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1963 NVPtr pNv = NVPTR(pScrn);
1965 ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->crtc);
1967 /* We just came back from terminal, so unlock */
1968 NVCrtcLockUnlock(crtc, FALSE);
1970 NVCrtcSetOwner(crtc);
1971 nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
1972 nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
1973 if (pNv->Architecture == NV_ARCH_40) {
1974 nv40_crtc_save_state_pll(pNv, &pNv->SavedReg);
1976 nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
1978 nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
1981 void nv_crtc_restore(xf86CrtcPtr crtc)
1983 ScrnInfoPtr pScrn = crtc->scrn;
1984 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1985 NVPtr pNv = NVPTR(pScrn);
1986 RIVA_HW_STATE *state;
1987 NVOutputRegPtr regp;
1989 state = &pNv->SavedReg;
1991 /* Some aspects of an output needs to be restore before the crtc. */
1992 /* In my case this has to do with the mode that i get at very low resolutions. */
1993 /* If i do this at the end, it will not be restored properly */
1994 /* Assumption: crtc0 is restored first. */
1995 if (nv_crtc->head == 0) {
1996 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
1998 ErrorF("Restore all TMDS timings, before restoring anything else\n");
1999 for (i = 0; i < config->num_output; i++) {
2000 NVOutputPrivatePtr nv_output2 = config->output[i]->driver_private;
2001 regp = &state->dac_reg[nv_output2->preferred_output];
2002 Bool crosswired = regp->TMDS[0x4] & (1 << 3);
2003 /* Let's guess the bios state ;-) */
2004 if (nv_output2->type == OUTPUT_TMDS) {
2005 uint32_t clock = nv_calc_tmds_clock_from_pll(config->output[i]);
2006 nv_set_tmds_registers(config->output[i], clock, TRUE, crosswired);
2008 if (nv_output2->type == OUTPUT_TMDS || nv_output2->type == OUTPUT_LVDS)
2009 link_head_and_output(pScrn, -1, nv_output2->dcb_entry, crosswired);
2013 ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->crtc);
2015 NVCrtcSetOwner(crtc);
2017 /* Just to be safe */
2018 NVCrtcLockUnlock(crtc, FALSE);
2020 NVVgaProtect(crtc, TRUE);
2021 nv_crtc_load_state_ext(crtc, &pNv->SavedReg, TRUE);
2022 nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
2023 if (pNv->Architecture == NV_ARCH_40) {
2024 nv40_crtc_load_state_pll(pNv, &pNv->SavedReg);
2026 nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
2028 nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
2029 nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->vtOWNER);
2030 NVVgaProtect(crtc, FALSE);
2032 /* We must lock the door if we leave ;-) */
2033 NVCrtcLockUnlock(crtc, TRUE);
2036 void nv_crtc_prepare(xf86CrtcPtr crtc)
2038 ScrnInfoPtr pScrn = crtc->scrn;
2039 NVPtr pNv = NVPTR(pScrn);
2040 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2042 ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->crtc);
2044 crtc->funcs->dpms(crtc, DPMSModeOff);
2046 /* Sync the engine before adjust mode */
2047 if (pNv->EXADriverPtr) {
2048 exaMarkSync(pScrn->pScreen);
2049 exaWaitSync(pScrn->pScreen);
2053 void nv_crtc_commit(xf86CrtcPtr crtc)
2055 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2056 ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->crtc);
2058 crtc->funcs->dpms (crtc, DPMSModeOn);
2060 if (crtc->scrn->pScreen != NULL)
2061 xf86_reload_cursors (crtc->scrn->pScreen);
2064 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
2066 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2067 ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->crtc);
2072 static void nv_crtc_unlock(xf86CrtcPtr crtc)
2074 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2075 ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->crtc);
2079 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
2082 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2083 ScrnInfoPtr pScrn = crtc->scrn;
2084 NVPtr pNv = NVPTR(pScrn);
2088 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2090 switch (pNv->CurrentLayout.depth) {
2093 /* We've got 5 bit (32 values) colors and 256 registers for each color */
2094 for (i = 0; i < 32; i++) {
2095 for (j = 0; j < 8; j++) {
2096 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2097 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
2098 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2104 /* First deal with the 5 bit colors */
2105 for (i = 0; i < 32; i++) {
2106 for (j = 0; j < 8; j++) {
2107 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2108 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2111 /* Now deal with the 6 bit color */
2112 for (i = 0; i < 64; i++) {
2113 for (j = 0; j < 4; j++) {
2114 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
2120 for (i = 0; i < 256; i++) {
2121 regp->DAC[i * 3] = red[i] >> 8;
2122 regp->DAC[(i * 3) + 1] = green[i] >> 8;
2123 regp->DAC[(i * 3) + 2] = blue[i] >> 8;
2128 NVCrtcLoadPalette(crtc);
2131 /* NV04-NV10 doesn't support alpha cursors */
2132 static const xf86CrtcFuncsRec nv_crtc_funcs = {
2133 .dpms = nv_crtc_dpms,
2134 .save = nv_crtc_save, /* XXX */
2135 .restore = nv_crtc_restore, /* XXX */
2136 .mode_fixup = nv_crtc_mode_fixup,
2137 .mode_set = nv_crtc_mode_set,
2138 .prepare = nv_crtc_prepare,
2139 .commit = nv_crtc_commit,
2140 .destroy = NULL, /* XXX */
2141 .lock = nv_crtc_lock,
2142 .unlock = nv_crtc_unlock,
2143 .set_cursor_colors = nv_crtc_set_cursor_colors,
2144 .set_cursor_position = nv_crtc_set_cursor_position,
2145 .show_cursor = nv_crtc_show_cursor,
2146 .hide_cursor = nv_crtc_hide_cursor,
2147 .load_cursor_image = nv_crtc_load_cursor_image,
2148 .gamma_set = nv_crtc_gamma_set,
2151 /* NV11 and up has support for alpha cursors. */
2152 /* Due to different maximum sizes we cannot allow it to use normal cursors */
2153 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
2154 .dpms = nv_crtc_dpms,
2155 .save = nv_crtc_save, /* XXX */
2156 .restore = nv_crtc_restore, /* XXX */
2157 .mode_fixup = nv_crtc_mode_fixup,
2158 .mode_set = nv_crtc_mode_set,
2159 .prepare = nv_crtc_prepare,
2160 .commit = nv_crtc_commit,
2161 .destroy = NULL, /* XXX */
2162 .lock = nv_crtc_lock,
2163 .unlock = nv_crtc_unlock,
2164 .set_cursor_colors = NULL, /* Alpha cursors do not need this */
2165 .set_cursor_position = nv_crtc_set_cursor_position,
2166 .show_cursor = nv_crtc_show_cursor,
2167 .hide_cursor = nv_crtc_hide_cursor,
2168 .load_cursor_argb = nv_crtc_load_cursor_argb,
2169 .gamma_set = nv_crtc_gamma_set,
2174 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
2176 NVPtr pNv = NVPTR(pScrn);
2178 NVCrtcPrivatePtr nv_crtc;
2180 if (pNv->NVArch >= 0x11) {
2181 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
2183 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
2188 nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
2189 nv_crtc->crtc = crtc_num;
2190 nv_crtc->head = crtc_num;
2192 crtc->driver_private = nv_crtc;
2194 NVCrtcLockUnlock(crtc, FALSE);
2197 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2199 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2203 regp = &state->crtc_reg[nv_crtc->head];
2205 NVWriteMiscOut(crtc, regp->MiscOutReg);
2207 for (i = 1; i < 5; i++)
2208 NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
2210 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
2211 NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
2213 for (i = 0; i < 25; i++)
2214 NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
2216 for (i = 0; i < 9; i++)
2217 NVWriteVgaGr(crtc, i, regp->Graphics[i]);
2219 NVEnablePalette(crtc);
2220 for (i = 0; i < 21; i++)
2221 NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
2222 NVDisablePalette(crtc);
2226 static void nv_crtc_fix_nv40_hw_cursor(xf86CrtcPtr crtc)
2228 /* TODO - implement this properly */
2229 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2230 ScrnInfoPtr pScrn = crtc->scrn;
2231 NVPtr pNv = NVPTR(pScrn);
2233 if (pNv->Architecture == NV_ARCH_40) { /* HW bug */
2234 volatile CARD32 curpos = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS);
2235 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS, curpos);
2238 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override)
2240 ScrnInfoPtr pScrn = crtc->scrn;
2241 NVPtr pNv = NVPTR(pScrn);
2242 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2246 regp = &state->crtc_reg[nv_crtc->head];
2248 if(pNv->Architecture >= NV_ARCH_10) {
2250 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL, regp->head);
2252 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
2253 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
2254 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
2255 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
2256 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2257 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2258 nvWriteMC(pNv, 0x1588, 0);
2260 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
2261 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
2262 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO, regp->gpio);
2263 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0830, regp->unk830);
2264 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0834, regp->unk834);
2265 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0850, regp->unk850);
2266 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_081C, regp->unk81c);
2268 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG, regp->config);
2270 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
2271 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
2273 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
2274 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
2275 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3C, regp->CRTC[NV_VGA_CRTCX_3C]);
2276 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
2277 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_4B, regp->CRTC[NV_VGA_CRTCX_4B]);
2278 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
2279 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_56, regp->CRTC[NV_VGA_CRTCX_56]);
2281 for (i = 0; i < 0x10; i++)
2282 NVWriteVGACR5758(pNv, nv_crtc->head, i, regp->CR58[i]);
2284 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
2285 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
2288 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
2289 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
2290 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
2291 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
2292 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
2293 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
2294 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
2295 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
2296 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
2297 if(pNv->Architecture >= NV_ARCH_30) {
2298 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
2301 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
2302 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
2303 nv_crtc_fix_nv40_hw_cursor(crtc);
2304 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
2305 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
2307 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_EN_0, 0);
2308 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
2310 pNv->CurrentState = state;
2313 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2315 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2319 regp = &state->crtc_reg[nv_crtc->head];
2321 regp->MiscOutReg = NVReadMiscOut(crtc);
2323 for (i = 0; i < 25; i++)
2324 regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
2326 NVEnablePalette(crtc);
2327 for (i = 0; i < 21; i++)
2328 regp->Attribute[i] = NVReadVgaAttr(crtc, i);
2329 NVDisablePalette(crtc);
2331 for (i = 0; i < 9; i++)
2332 regp->Graphics[i] = NVReadVgaGr(crtc, i);
2334 for (i = 1; i < 5; i++)
2335 regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
2339 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2341 ScrnInfoPtr pScrn = crtc->scrn;
2342 NVPtr pNv = NVPTR(pScrn);
2343 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2347 regp = &state->crtc_reg[nv_crtc->head];
2349 regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
2350 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
2351 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
2352 regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
2353 regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
2354 regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
2355 regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
2357 regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
2358 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
2359 if(pNv->Architecture >= NV_ARCH_30) {
2360 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
2362 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
2363 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
2364 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
2365 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
2367 regp->gpio = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO);
2368 regp->unk830 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0830);
2369 regp->unk834 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0834);
2370 regp->unk850 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0850);
2371 regp->unk81c = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_081C);
2373 regp->config = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG);
2375 if(pNv->Architecture >= NV_ARCH_10) {
2377 regp->head = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL);
2378 regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
2380 regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
2382 regp->cursorConfig = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG);
2384 regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
2385 regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
2386 regp->CRTC[NV_VGA_CRTCX_3C] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3C);
2387 regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
2388 regp->CRTC[NV_VGA_CRTCX_4B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_4B);
2389 regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
2390 regp->CRTC[NV_VGA_CRTCX_56] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_56);
2391 for (i = 0; i < 0x10; i++)
2392 regp->CR58[i] = NVReadVGACR5758(pNv, nv_crtc->head, i);
2393 regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
2394 regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
2395 regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
2396 regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
2400 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2402 ScrnInfoPtr pScrn = crtc->scrn;
2403 NVPtr pNv = NVPTR(pScrn);
2404 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2408 regp = &state->crtc_reg[nv_crtc->head];
2410 regp->general = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL);
2412 regp->fp_control = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL);
2413 regp->debug_0 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0);
2414 regp->debug_1 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1);
2415 regp->debug_2 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2);
2417 regp->unk_a20 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20);
2418 regp->unk_a24 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24);
2419 regp->unk_a34 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34);
2421 if (pNv->NVArch == 0x11) {
2422 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11);
2423 } else if (pNv->twoHeads) {
2424 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER);
2426 regp->nv10_cursync = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC);
2428 /* The regs below are 0 for non-flatpanels, so you can load and save them */
2430 for (i = 0; i < 7; i++) {
2431 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2432 regp->fp_horiz_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2435 for (i = 0; i < 7; i++) {
2436 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2437 regp->fp_vert_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2440 regp->fp_hvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START);
2441 regp->fp_hvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END);
2442 regp->fp_vvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START);
2443 regp->fp_vvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END);
2446 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2448 ScrnInfoPtr pScrn = crtc->scrn;
2449 NVPtr pNv = NVPTR(pScrn);
2450 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2454 regp = &state->crtc_reg[nv_crtc->head];
2456 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL, regp->general);
2458 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control);
2459 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0, regp->debug_0);
2460 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
2461 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
2463 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20, regp->unk_a20);
2464 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24, regp->unk_a24);
2465 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34, regp->unk_a34);
2467 if (pNv->NVArch == 0x11) {
2468 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11, regp->dither);
2469 } else if (pNv->twoHeads) {
2470 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER, regp->dither);
2472 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
2474 /* The regs below are 0 for non-flatpanels, so you can load and save them */
2476 for (i = 0; i < 7; i++) {
2477 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2478 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_horiz_regs[i]);
2481 for (i = 0; i < 7; i++) {
2482 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2483 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_vert_regs[i]);
2486 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START, regp->fp_hvalid_start);
2487 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END, regp->fp_hvalid_end);
2488 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START, regp->fp_vvalid_start);
2489 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END, regp->fp_vvalid_end);
2493 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y)
2495 ScrnInfoPtr pScrn = crtc->scrn;
2496 NVPtr pNv = NVPTR(pScrn);
2497 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2498 NVFBLayout *pLayout = &pNv->CurrentLayout;
2501 ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
2503 start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
2504 start += pNv->FB->offset;
2506 /* 30 bits addresses in 32 bits according to haiku */
2507 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_START, start & 0xfffffffc);
2509 /* set NV4/NV10 byte adress: (bit0 - 1) */
2510 NVWriteVgaAttr(crtc, 0x13, (start & 0x3) << 1);
2516 static void NVCrtcWriteDacMask(xf86CrtcPtr crtc, CARD8 value)
2518 ScrnInfoPtr pScrn = crtc->scrn;
2519 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2520 NVPtr pNv = NVPTR(pScrn);
2521 volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2523 NV_WR08(pDACReg, VGA_DAC_MASK, value);
2526 static CARD8 NVCrtcReadDacMask(xf86CrtcPtr crtc)
2528 ScrnInfoPtr pScrn = crtc->scrn;
2529 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2530 NVPtr pNv = NVPTR(pScrn);
2531 volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2533 return NV_RD08(pDACReg, VGA_DAC_MASK);
2536 static void NVCrtcWriteDacReadAddr(xf86CrtcPtr crtc, CARD8 value)
2538 ScrnInfoPtr pScrn = crtc->scrn;
2539 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2540 NVPtr pNv = NVPTR(pScrn);
2541 volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2543 NV_WR08(pDACReg, VGA_DAC_READ_ADDR, value);
2546 static void NVCrtcWriteDacWriteAddr(xf86CrtcPtr crtc, CARD8 value)
2548 ScrnInfoPtr pScrn = crtc->scrn;
2549 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2550 NVPtr pNv = NVPTR(pScrn);
2551 volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2553 NV_WR08(pDACReg, VGA_DAC_WRITE_ADDR, value);
2556 static void NVCrtcWriteDacData(xf86CrtcPtr crtc, CARD8 value)
2558 ScrnInfoPtr pScrn = crtc->scrn;
2559 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2560 NVPtr pNv = NVPTR(pScrn);
2561 volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2563 NV_WR08(pDACReg, VGA_DAC_DATA, value);
2566 static CARD8 NVCrtcReadDacData(xf86CrtcPtr crtc, CARD8 value)
2568 ScrnInfoPtr pScrn = crtc->scrn;
2569 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2570 NVPtr pNv = NVPTR(pScrn);
2571 volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2573 return NV_RD08(pDACReg, VGA_DAC_DATA);
2576 void NVCrtcLoadPalette(xf86CrtcPtr crtc)
2579 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2581 ScrnInfoPtr pScrn = crtc->scrn;
2582 NVPtr pNv = NVPTR(pScrn);
2584 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2586 NVCrtcSetOwner(crtc);
2587 NVCrtcWriteDacMask(crtc, 0xff);
2588 NVCrtcWriteDacWriteAddr(crtc, 0x00);
2590 for (i = 0; i<768; i++) {
2591 NVCrtcWriteDacData(crtc, regp->DAC[i]);
2593 NVDisablePalette(crtc);
2596 void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
2600 NVCrtcSetOwner(crtc);
2602 scrn = NVReadVgaSeq(crtc, 0x01);
2609 NVVgaSeqReset(crtc, TRUE);
2610 NVWriteVgaSeq(crtc, 0x01, scrn);
2611 NVVgaSeqReset(crtc, FALSE);
2614 /*************************************************************************** \
2616 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
2618 |* NOTICE TO USER: The source code is copyrighted under U.S. and *|
2619 |* international laws. Users and possessors of this source code are *|
2620 |* hereby granted a nonexclusive, royalty-free copyright license to *|
2621 |* use this code in individual and commercial software. *|
2623 |* Any use of this source code must include, in the user documenta- *|
2624 |* tion and internal comments to the code, notices to the end user *|
2627 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
2629 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
2630 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
2631 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
2632 |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
2633 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
2634 |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
2635 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
2636 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
2637 |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
2638 |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
2639 |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
2641 |* U.S. Government End Users. This source code is a "commercial *|
2642 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
2643 |* consisting of "commercial computer software" and "commercial *|
2644 |* computer software documentation," as such terms are used in *|
2645 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
2646 |* ment only as a commercial end item. Consistent with 48 C.F.R. *|
2647 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
2648 |* all U.S. Government End Users acquire the source code with only *|
2649 |* those rights set forth herein. *|
2651 \***************************************************************************/