git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 2006 Dave Airlie
   3  * Copyright 2007 Maarten Maathuis
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
  26  * decleration is at the bottom of this file as it is rather ugly
  27  */
  28
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include <assert.h>
  34 #include "xf86.h"
  35 #include "os.h"
  36 #include "mibank.h"
  37 #include "globals.h"
  38 #include "xf86.h"
  39 #include "xf86Priv.h"
  40 #include "xf86DDC.h"
  41 #include "mipointer.h"
  42 #include "windowstr.h"
  43 #include <randrstr.h>
  44 #include <X11/extensions/render.h>
  45
  46 #include "xf86Crtc.h"
  47 #include "nv_include.h"
  48
  49 #include "vgaHW.h"
  50
  51 #define CRTC_INDEX 0x3d4
  52 #define CRTC_DATA 0x3d5
  53 #define CRTC_IN_STAT_1 0x3da
  54
  55 #define WHITE_VALUE 0x3F
  56 #define BLACK_VALUE 0x00
  57 #define OVERSCAN_VALUE 0x01
  58
  59 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  60 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override);
  61 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  62 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  63 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  64 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  65
  66 uint32_t NVReadCRTC(NVPtr pNv, uint8_t head, uint32_t reg)
  67 {
  68         volatile const void *ptr = head ? pNv->PCRTC1 : pNv->PCRTC0;
  69         DDXMMIOH("NVReadCRTC: head %d reg %08x val %08x\n", head, reg + NV_PCRTC0_OFFSET + (head ? NV_PCRTC0_SIZE : 0), (uint32_t)MMIO_IN32(ptr, reg));
  70         return MMIO_IN32(ptr, reg);
  71 }
  72
  73 void NVWriteCRTC(NVPtr pNv, uint8_t head, uint32_t reg, uint32_t val)
  74 {
  75         volatile const void *ptr = head ? pNv->PCRTC1 : pNv->PCRTC0;
  76         DDXMMIOH("NVWriteCRTC: head %d reg %08x val %08x\n", head, reg + NV_PCRTC0_OFFSET + (head ? NV_PCRTC0_SIZE : 0), val);
  77         MMIO_OUT32(ptr, reg, val);
  78 }
  79
  80 uint32_t NVCrtcReadCRTC(xf86CrtcPtr crtc, uint32_t reg)
  81 {
  82         ScrnInfoPtr pScrn = crtc->scrn;
  83         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  84         NVPtr pNv = NVPTR(pScrn);
  85
  86         return NVReadCRTC(pNv, nv_crtc->head, reg);
  87 }
  88
  89 void NVCrtcWriteCRTC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
  90 {
  91         ScrnInfoPtr pScrn = crtc->scrn;
  92         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  93         NVPtr pNv = NVPTR(pScrn);
  94
  95         NVWriteCRTC(pNv, nv_crtc->head, reg, val);
  96 }
  97
  98 uint32_t NVReadRAMDAC(NVPtr pNv, uint8_t head, uint32_t reg)
  99 {
 100         volatile const void *ptr = head ? pNv->PRAMDAC1 : pNv->PRAMDAC0;
 101         DDXMMIOH("NVReadRamdac: head %d reg %08x val %08x\n", head, reg + NV_PRAMDAC0_OFFSET + (head ? NV_PRAMDAC0_SIZE : 0), (uint32_t)MMIO_IN32(ptr, reg));
 102         return MMIO_IN32(ptr, reg);
 103 }
 104
 105 void NVWriteRAMDAC(NVPtr pNv, uint8_t head, uint32_t reg, uint32_t val)
 106 {
 107         volatile const void *ptr = head ? pNv->PRAMDAC1 : pNv->PRAMDAC0;
 108         DDXMMIOH("NVWriteRamdac: head %d reg %08x val %08x\n", head, reg + NV_PRAMDAC0_OFFSET + (head ? NV_PRAMDAC0_SIZE : 0), val);
 109         MMIO_OUT32(ptr, reg, val);
 110 }
 111
 112 uint32_t NVCrtcReadRAMDAC(xf86CrtcPtr crtc, uint32_t reg)
 113 {
 114         ScrnInfoPtr pScrn = crtc->scrn;
 115         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 116         NVPtr pNv = NVPTR(pScrn);
 117
 118         return NVReadRAMDAC(pNv, nv_crtc->head, reg);
 119 }
 120
 121 void NVCrtcWriteRAMDAC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
 122 {
 123         ScrnInfoPtr pScrn = crtc->scrn;
 124         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 125         NVPtr pNv = NVPTR(pScrn);
 126
 127         NVWriteRAMDAC(pNv, nv_crtc->head, reg, val);
 128 }
 129
 130 static uint8_t NVReadPVIO(xf86CrtcPtr crtc, uint32_t address)
 131 {
 132         ScrnInfoPtr pScrn = crtc->scrn;
 133         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 134         NVPtr pNv = NVPTR(pScrn);
 135
 136         /* Only NV4x have two pvio ranges */
 137         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
 138                 DDXMMIOH("NVReadPVIO: head %d reg %08x val %02x\n", 1, address + NV_PVIO_OFFSET + NV_PVIO_SIZE, NV_RD08(pNv->PVIO1, address));
 139                 return NV_RD08(pNv->PVIO1, address);
 140         } else {
 141                 DDXMMIOH("NVReadPVIO: head %d reg %08x val %02x\n", 0, address + NV_PVIO_OFFSET, NV_RD08(pNv->PVIO0, address));
 142                 return NV_RD08(pNv->PVIO0, address);
 143         }
 144 }
 145
 146 static void NVWritePVIO(xf86CrtcPtr crtc, uint32_t address, uint8_t value)
 147 {
 148         ScrnInfoPtr pScrn = crtc->scrn;
 149         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 150         NVPtr pNv = NVPTR(pScrn);
 151
 152         DDXMMIOH("NVWritePVIO: head %d reg %08x val %02x\n", nv_crtc->head, address + NV_PVIO_OFFSET + (nv_crtc->head ? NV_PVIO_SIZE : 0), value);
 153         /* Only NV4x have two pvio ranges */
 154         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
 155                 NV_WR08(pNv->PVIO1, address, value);
 156         } else {
 157                 NV_WR08(pNv->PVIO0, address, value);
 158         }
 159 }
 160
 161 static void NVWriteMiscOut(xf86CrtcPtr crtc, uint8_t value)
 162 {
 163         NVWritePVIO(crtc, VGA_MISC_OUT_W, value);
 164 }
 165
 166 static uint8_t NVReadMiscOut(xf86CrtcPtr crtc)
 167 {
 168         return NVReadPVIO(crtc, VGA_MISC_OUT_R);
 169 }
 170
 171 void NVWriteVGA(NVPtr pNv, int head, uint8_t index, uint8_t value)
 172 {
 173         volatile uint8_t *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 174
 175         DDXMMIOH("NVWriteVGA: head %d index 0x%02x data 0x%02x\n", head, index, value);
 176         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 177         NV_WR08(pCRTCReg, CRTC_DATA, value);
 178 }
 179
 180 uint8_t NVReadVGA(NVPtr pNv, int head, uint8_t index)
 181 {
 182         volatile uint8_t *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 183
 184         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 185         DDXMMIOH("NVReadVGA: head %d index 0x%02x data 0x%02x\n", head, index, NV_RD08(pCRTCReg, CRTC_DATA));
 186         return NV_RD08(pCRTCReg, CRTC_DATA);
 187 }
 188
 189 /* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
 190  * I suspect they in fact do nothing, but are merely a way to carry useful
 191  * per-head variables around
 192  *
 193  * Known uses:
 194  * CR57         CR58
 195  * 0x00         index to the appropriate dcb entry (or 7f for inactive)
 196  * 0x02         dcb entry's "or" value (or 00 for inactive)
 197  * 0x03         bit0 set for dual link (LVDS, possibly elsewhere too)
 198  * 0x08 or 0x09 pxclk in MHz
 199  * 0x0f         laptop panel info -     low nibble for PEXTDEV_BOOT strap
 200  *                                      high nibble for xlat strap value
 201  */
 202
 203 void NVWriteVGACR5758(NVPtr pNv, int head, uint8_t index, uint8_t value)
 204 {
 205         NVWriteVGA(pNv, head, 0x57, index);
 206         NVWriteVGA(pNv, head, 0x58, value);
 207 }
 208
 209 uint8_t NVReadVGACR5758(NVPtr pNv, int head, uint8_t index)
 210 {
 211         NVWriteVGA(pNv, head, 0x57, index);
 212         return NVReadVGA(pNv, head, 0x58);
 213 }
 214
 215 void NVWriteVgaCrtc(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 216 {
 217         ScrnInfoPtr pScrn = crtc->scrn;
 218         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 219         NVPtr pNv = NVPTR(pScrn);
 220
 221         NVWriteVGA(pNv, nv_crtc->head, index, value);
 222 }
 223
 224 uint8_t NVReadVgaCrtc(xf86CrtcPtr crtc, uint8_t index)
 225 {
 226         ScrnInfoPtr pScrn = crtc->scrn;
 227         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 228         NVPtr pNv = NVPTR(pScrn);
 229
 230         return NVReadVGA(pNv, nv_crtc->head, index);
 231 }
 232
 233 static void NVWriteVgaSeq(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 234 {
 235         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 236         NVWritePVIO(crtc, VGA_SEQ_DATA, value);
 237 }
 238
 239 static uint8_t NVReadVgaSeq(xf86CrtcPtr crtc, uint8_t index)
 240 {
 241         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 242         return NVReadPVIO(crtc, VGA_SEQ_DATA);
 243 }
 244
 245 static void NVWriteVgaGr(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 246 {
 247         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 248         NVWritePVIO(crtc, VGA_GRAPH_DATA, value);
 249 }
 250
 251 static uint8_t NVReadVgaGr(xf86CrtcPtr crtc, uint8_t index)
 252 {
 253         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 254         return NVReadPVIO(crtc, VGA_GRAPH_DATA);
 255 }
 256
 257
 258 static void NVWriteVgaAttr(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 259 {
 260         ScrnInfoPtr pScrn = crtc->scrn;
 261         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 262         NVPtr pNv = NVPTR(pScrn);
 263         volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 264
 265         DDXMMIOH("NVWriteVgaAttr: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, CRTC_IN_STAT_1, NV_RD08(pCRTCReg, CRTC_IN_STAT_1));
 266         NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 267         if (nv_crtc->paletteEnabled)
 268                 index &= ~0x20;
 269         else
 270                 index |= 0x20;
 271
 272         DDXMMIOH("NVWriteVgaAttr: head %d index 0x%02x data 0x%02x\n", nv_crtc->head, index, value);
 273         NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 274         NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
 275 }
 276
 277 static uint8_t NVReadVgaAttr(xf86CrtcPtr crtc, uint8_t index)
 278 {
 279         ScrnInfoPtr pScrn = crtc->scrn;
 280         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 281         NVPtr pNv = NVPTR(pScrn);
 282         volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 283
 284         DDXMMIOH("NVReadVgaAttr: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, CRTC_IN_STAT_1, NV_RD08(pCRTCReg, CRTC_IN_STAT_1));
 285         NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 286         if (nv_crtc->paletteEnabled)
 287                 index &= ~0x20;
 288         else
 289                 index |= 0x20;
 290
 291         NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 292         DDXMMIOH("NVReadVgaAttr: head %d index 0x%02x data 0x%02x\n", nv_crtc->head, index, NV_RD08(pCRTCReg, VGA_ATTR_DATA_R));
 293         return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
 294 }
 295
 296 static void NVCrtcSetOwner(xf86CrtcPtr crtc)
 297 {
 298         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 299         ScrnInfoPtr pScrn = crtc->scrn;
 300         NVPtr pNv = NVPTR(pScrn);
 301         /* Non standard beheaviour required by NV11 */
 302         if (pNv) {
 303                 uint8_t owner = NVReadVGA(pNv, 0, NV_VGA_CRTCX_OWNER);
 304                 ErrorF("pre-Owner: 0x%X\n", owner);
 305                 if (owner == 0x04) {
 306                         uint32_t pbus84 = nvReadMC(pNv, 0x1084);
 307                         ErrorF("pbus84: 0x%X\n", pbus84);
 308                         pbus84 &= ~(1<<28);
 309                         ErrorF("pbus84: 0x%X\n", pbus84);
 310                         nvWriteMC(pNv, 0x1084, pbus84);
 311                 }
 312                 /* The blob never writes owner to pcio1, so should we */
 313                 if (pNv->NVArch == 0x11) {
 314                         NVWriteVGA(pNv, 0, NV_VGA_CRTCX_OWNER, 0xff);
 315                 }
 316                 NVWriteVGA(pNv, 0, NV_VGA_CRTCX_OWNER, nv_crtc->head * 0x3);
 317                 owner = NVReadVGA(pNv, 0, NV_VGA_CRTCX_OWNER);
 318                 ErrorF("post-Owner: 0x%X\n", owner);
 319         } else {
 320                 ErrorF("pNv pointer is NULL\n");
 321         }
 322 }
 323
 324 static void
 325 NVEnablePalette(xf86CrtcPtr crtc)
 326 {
 327         ScrnInfoPtr pScrn = crtc->scrn;
 328         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 329         NVPtr pNv = NVPTR(pScrn);
 330         volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 331
 332         DDXMMIOH("NVEnablePalette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, CRTC_IN_STAT_1, NV_RD08(pCRTCReg, CRTC_IN_STAT_1));
 333         NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 334         DDXMMIOH("NVEnablePalette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_ATTR_INDEX, 0);
 335         NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
 336         nv_crtc->paletteEnabled = TRUE;
 337 }
 338
 339 static void
 340 NVDisablePalette(xf86CrtcPtr crtc)
 341 {
 342         ScrnInfoPtr pScrn = crtc->scrn;
 343         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 344         NVPtr pNv = NVPTR(pScrn);
 345         volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 346
 347         DDXMMIOH("NVDisablePalette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, CRTC_IN_STAT_1, NV_RD08(pCRTCReg, CRTC_IN_STAT_1));
 348         NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 349         DDXMMIOH("NVEnablePalette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_ATTR_INDEX, 0x20);
 350         NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
 351         nv_crtc->paletteEnabled = FALSE;
 352 }
 353
 354 static void NVWriteVgaReg(xf86CrtcPtr crtc, uint32_t reg, uint8_t value)
 355 {
 356         ScrnInfoPtr pScrn = crtc->scrn;
 357         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 358         NVPtr pNv = NVPTR(pScrn);
 359         volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 360
 361         DDXMMIOH("NVWriteVgaReg: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, reg, value);
 362         NV_WR08(pCRTCReg, reg, value);
 363 }
 364
 365 /* perform a sequencer reset */
 366 static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
 367 {
 368   if (start)
 369     NVWriteVgaSeq(crtc, 0x00, 0x1);
 370   else
 371     NVWriteVgaSeq(crtc, 0x00, 0x3);
 372
 373 }
 374 static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
 375 {
 376         uint8_t tmp;
 377
 378         if (on) {
 379                 tmp = NVReadVgaSeq(crtc, 0x1);
 380                 NVVgaSeqReset(crtc, TRUE);
 381                 NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
 382
 383                 NVEnablePalette(crtc);
 384         } else {
 385                 /*
 386                  * Reenable sequencer, then turn on screen.
 387                  */
 388                 tmp = NVReadVgaSeq(crtc, 0x1);
 389                 NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20); /* reenable display */
 390                 NVVgaSeqReset(crtc, FALSE);
 391
 392                 NVDisablePalette(crtc);
 393         }
 394 }
 395
 396 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool Lock)
 397 {
 398         NVPtr pNv = NVPTR(crtc->scrn);
 399         uint8_t cr11;
 400
 401         if (pNv->twoHeads)
 402                 NVCrtcSetOwner(crtc);
 403
 404         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57);
 405         cr11 = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE);
 406         if (Lock) cr11 |= 0x80;
 407         else cr11 &= ~0x80;
 408         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE, cr11);
 409 }
 410
 411 xf86OutputPtr
 412 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
 413 {
 414         ScrnInfoPtr pScrn = crtc->scrn;
 415         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 416         int i;
 417         for (i = 0; i < xf86_config->num_output; i++) {
 418                 xf86OutputPtr output = xf86_config->output[i];
 419
 420                 if (output->crtc == crtc) {
 421                         return output;
 422                 }
 423         }
 424
 425         return NULL;
 426 }
 427
 428 xf86CrtcPtr
 429 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
 430 {
 431         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 432         int i;
 433
 434         for (i = 0; i < xf86_config->num_crtc; i++) {
 435                 xf86CrtcPtr crtc = xf86_config->crtc[i];
 436                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 437                 if (nv_crtc->head == index)
 438                         return crtc;
 439         }
 440
 441         return NULL;
 442 }
 443
 444 /*
 445  * Calculate the Video Clock parameters for the PLL.
 446  */
 447 /* Code taken from NVClock, with permission of the author (being a GPL->MIT code transfer). */
 448
 449 static void
 450 CalculateVClkNV4x_SingleVCO(NVPtr pNv, struct pll_lims *pll_lim, uint32_t clockIn, uint32_t *n1_best, uint32_t *m1_best, uint32_t *p_best)
 451 {
 452         uint32_t clock, M, N, P;
 453         uint32_t delta, bestDelta, minM, maxM, minN, maxN, maxP;
 454         uint32_t minVCOInputFreq, minVCOFreq, maxVCOFreq;
 455         uint32_t VCOFreq;
 456         uint32_t refClk = pNv->CrystalFreqKHz;
 457         bestDelta = clockIn;
 458
 459         minVCOInputFreq = pll_lim->vco1.min_inputfreq;
 460         minVCOFreq = pll_lim->vco1.minfreq;
 461         maxVCOFreq = pll_lim->vco1.maxfreq;
 462         minM = pll_lim->vco1.min_m;
 463         maxM = pll_lim->vco1.max_m;
 464         minN = pll_lim->vco1.min_n;
 465         maxN = pll_lim->vco1.max_n;
 466
 467         maxP = 6;
 468
 469         /* The optimal frequency for the PLL to work at is somewhere in the center of its range.
 470         /  Choose a post divider in such a way to achieve this.
 471         /  The G8x nv driver does something similar but they they derive a minP and maxP. That
 472         /  doesn't seem required as you get so many matching clocks that you don't enter a second
 473         /  iteration for P. (The minP / maxP values in the nv driver only differ at most 1, so it is for
 474         /  some rare corner cases.
 475         */
 476         for (P=0, VCOFreq=maxVCOFreq/2; clockIn<=VCOFreq && P <= maxP; P++)
 477         {
 478                 VCOFreq /= 2;
 479         }
 480
 481         /* Calculate the m and n values. There are a lot of values which give the same speed;
 482         /  We choose the speed for which the difference with the request speed is as small as possible.
 483         */
 484         for (M=minM; M<=maxM; M++)
 485         {
 486                 /* The VCO has a minimum input frequency */
 487                 if ((refClk/M) < minVCOInputFreq)
 488                         break;
 489
 490                 for (N=minN; N<=maxN; N++)
 491                 {
 492                         /* Calculate the frequency generated by VCO1 */
 493                         clock = (int)(refClk * N / (float)M);
 494
 495                         /* Verify if the clock lies within the output limits of VCO1 */
 496                         if (clock < minVCOFreq)
 497                                 continue;
 498                         else if (clock > maxVCOFreq) /* It is no use to continue as the clock will only become higher */
 499                                 break;
 500
 501                         clock >>= P;
 502                         delta = abs((int)(clockIn - clock));
 503                         /* When the difference is 0 or less than .5% accept the speed */
 504                         if (((delta == 0) || ((float)delta/(float)clockIn <= 0.005)))
 505                         {
 506                                 *m1_best = M;
 507                                 *n1_best = N;
 508                                 *p_best = P;
 509                                 return;
 510                         }
 511
 512                         /* When the new difference is smaller than the old one, use this one */
 513                         if (delta < bestDelta)
 514                         {
 515                                 bestDelta = delta;
 516                                 *m1_best = M;
 517                                 *n1_best = N;
 518                                 *p_best = P;
 519                         }
 520                 }
 521         }
 522 }
 523
 524 static void
 525 CalculateVClkNV4x_DoubleVCO(NVPtr pNv, struct pll_lims *pll_lim, uint32_t clockIn, uint32_t *n1_best, uint32_t *n2_best, uint32_t *m1_best, uint32_t *m2_best, uint32_t *p_best)
 526 {
 527         uint32_t clock1, clock2, M, M2, N, N2, P;
 528         uint32_t delta, bestDelta, minM, minM2, maxM, maxM2, minN, minN2, maxN, maxN2, maxP;
 529         uint32_t minVCOInputFreq, minVCO2InputFreq, maxVCO2InputFreq, minVCOFreq, minVCO2Freq, maxVCOFreq, maxVCO2Freq;
 530         uint32_t VCO2Freq, maxClock;
 531         uint32_t refClk = pNv->CrystalFreqKHz;
 532         bestDelta = clockIn;
 533
 534         minVCOInputFreq = pll_lim->vco1.min_inputfreq;
 535         minVCOFreq = pll_lim->vco1.minfreq;
 536         maxVCOFreq = pll_lim->vco1.maxfreq;
 537         minM = pll_lim->vco1.min_m;
 538         maxM = pll_lim->vco1.max_m;
 539         minN = pll_lim->vco1.min_n;
 540         maxN = pll_lim->vco1.max_n;
 541
 542         minVCO2InputFreq = pll_lim->vco2.min_inputfreq;
 543         maxVCO2InputFreq = pll_lim->vco2.max_inputfreq;
 544         minVCO2Freq = pll_lim->vco2.minfreq;
 545         maxVCO2Freq = pll_lim->vco2.maxfreq;
 546         minM2 = pll_lim->vco2.min_m;
 547         maxM2 = pll_lim->vco2.max_m;
 548         minN2 = pll_lim->vco2.min_n;
 549         maxN2 = pll_lim->vco2.max_n;
 550
 551         maxP = 6;
 552
 553         maxClock = maxVCO2Freq;
 554         /* If the requested clock is behind the bios limits, try it anyway */
 555         if (clockIn > maxVCO2Freq)
 556                 maxClock = clockIn + clockIn/200; /* Add a .5% margin */
 557
 558         /* The optimal frequency for the PLL to work at is somewhere in the center of its range.
 559         /  Choose a post divider in such a way to achieve this.
 560         /  The G8x nv driver does something similar but they they derive a minP and maxP. That
 561         /  doesn't seem required as you get so many matching clocks that you don't enter a second
 562         /  iteration for P. (The minP / maxP values in the nv driver only differ at most 1, so it is for
 563         /  some rare corner cases.
 564         */
 565         for (P=0, VCO2Freq=maxClock/2; clockIn<=VCO2Freq && P <= maxP; P++)
 566         {
 567                 VCO2Freq /= 2;
 568         }
 569
 570         /* The PLLs on Geforce6/7 hardware can operate in a single stage made with only 1 VCO
 571         /  and a cascade mode of two VCOs. This second mode is in general used for relatively high
 572         /  frequencies. The loop below calculates the divider and multiplier ratios for the cascade
 573         /  mode. The code takes into account limits defined in the video bios.
 574         */
 575         for (M=minM; M<=maxM; M++)
 576         {
 577                 /* The VCO has a minimum input frequency */
 578                 if ((refClk/M) < minVCOInputFreq)
 579                         break;
 580
 581                 for (N=minN; N<=maxN; N++)
 582                 {
 583                         /* Calculate the frequency generated by VCO1 */
 584                         clock1 = (int)(refClk * N / (float)M);
 585                         /* Verify if the clock lies within the output limits of VCO1 */
 586                         if ( (clock1 < minVCOFreq) )
 587                                 continue;
 588                         else if (clock1 > maxVCOFreq) /* For future N, the clock will only increase so stop; xorg nv continues but that is useless */
 589                                 break;
 590
 591                         for (M2=minM2; M2<=maxM2; M2++)
 592                         {
 593                                 /* The clock fed to the second VCO needs to lie within a certain input range */
 594                                 if (clock1 / M2 < minVCO2InputFreq)
 595                                         break;
 596                                 else if (clock1 / M2 > maxVCO2InputFreq)
 597                                         continue;
 598
 599                                 N2 = (int)((float)((clockIn << P) * M * M2) / (float)(refClk * N)+.5);
 600                                 if( (N2 < minN2) || (N2 > maxN2) )
 601                                         continue;
 602
 603                                 /* The clock before being fed to the post-divider needs to lie within a certain range.
 604                                 /  Further there are some limits on N2/M2.
 605                                 */
 606                                 clock2 = (int)((float)(N*N2)/(M*M2) * refClk);
 607                                 if( (clock2 < minVCO2Freq) || (clock2 > maxClock))// || ((N2 / M2) < 4) || ((N2 / M2) > 10) )
 608                                         continue;
 609
 610                                 /* The post-divider delays the 'high' clock to create a low clock if requested.
 611                                 /  This post-divider exists because the VCOs can only generate frequencies within
 612                                 /  a limited frequency range. This range has been tuned to lie around half of its max
 613                                 /  input frequency. It tries to calculate all clocks (including lower ones) around this
 614                                 /  'center' frequency.
 615                                 */
 616                                 clock2 >>= P;
 617                                 delta = abs((int)(clockIn - clock2));
 618
 619                                 /* When the difference is 0 or less than .5% accept the speed */
 620                                 if (((delta == 0) || ((float)delta/(float)clockIn <= 0.005)))
 621                                 {
 622                                         *m1_best = M;
 623                                         *m2_best = M2;
 624                                         *n1_best = N;
 625                                         *n2_best = N2;
 626                                         *p_best = P;
 627                                         return;
 628                                 }
 629
 630                                 /* When the new difference is smaller than the old one, use this one */
 631                                 if (delta < bestDelta)
 632                                 {
 633                                         bestDelta = delta;
 634                                         *m1_best = M;
 635                                         *m2_best = M2;
 636                                         *n1_best = N;
 637                                         *n2_best = N2;
 638                                         *p_best = P;
 639                                 }
 640                         }
 641                 }
 642         }
 643 }
 644
 645 /* BIG NOTE: modifying vpll1 and vpll2 does not work, what bit is the switch to allow it? */
 646
 647 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
 648 /* They are only valid for NV4x, appearantly reordered for NV5x */
 649 /* gpu pll: 0x4000 + 0x4004
 650  * unknown pll: 0x4008 + 0x400c
 651  * vpll1: 0x4010 + 0x4014
 652  * vpll2: 0x4018 + 0x401c
 653  * unknown pll: 0x4020 + 0x4024
 654  * unknown pll: 0x4038 + 0x403c
 655  * Some of the unknown's are probably memory pll's.
 656  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
 657  * 1 and 2 refer to the registers of each pair. There is only one post divider.
 658  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
 659  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
 660  *     bit8: A switch that turns of the second divider and multiplier off.
 661  *     bit12: Also a switch, i haven't seen it yet.
 662  *     bit16-19: p-divider
 663  *     but 28-31: Something related to the mode that is used (see bit8).
 664  * 2) bit0-7: m-divider (a)
 665  *     bit8-15: n-multiplier (a)
 666  *     bit16-23: m-divider (b)
 667  *     bit24-31: n-multiplier (b)
 668  */
 669
 670 /* Modifying the gpu pll for example requires:
 671  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 672  * This is not needed for the vpll's which have their own bits.
 673  */
 674
 675 static void
 676 CalculateVClkNV4x(
 677         ScrnInfoPtr pScrn,
 678         uint32_t requested_clock,
 679         uint32_t *given_clock,
 680         uint32_t *pll_a,
 681         uint32_t *pll_b,
 682         uint32_t *reg580,
 683         Bool    *db1_ratio,
 684         Bool primary
 685 )
 686 {
 687         NVPtr pNv = NVPTR(pScrn);
 688         uint32_t pll_lim_reg;
 689         struct pll_lims pll_lim;
 690         /* We have 2 mulitpliers, 2 dividers and one post divider */
 691         /* Note that p is only 3 bits */
 692         int NM1 = 0xbeef, NM2 = 0xdead, log2P = 0;
 693         uint32_t special_bits = 0;
 694
 695         if (primary) {
 696                 if (!get_pll_limits_reg(pScrn, VPLL1, &pll_lim_reg))
 697                         return;
 698         } else
 699                 if (!get_pll_limits_reg(pScrn, VPLL2, &pll_lim_reg))
 700                         return;
 701
 702         get_pll_limits(pScrn, pll_lim_reg, &pll_lim);
 703
 704         if (requested_clock < pll_lim.vco1.maxfreq && pNv->NVArch > 0x40) { /* single VCO */
 705                 *db1_ratio = TRUE;
 706                 /* Turn the second set of divider and multiplier off */
 707                 /* Bogus data, the same nvidia uses */
 708                 NM2 = 0x11f;
 709                 *given_clock = getMNP_single(pScrn, pll_lim_reg, requested_clock, &NM1, &log2P);
 710         } else { /* dual VCO */
 711                 *db1_ratio = FALSE;
 712                 *given_clock = getMNP_double(pScrn, pll_lim_reg, requested_clock, &NM1, &NM2, &log2P);
 713         }
 714
 715         /* Are this all (relevant) G70 cards? */
 716         if (pNv->NVArch == 0x4B || pNv->NVArch == 0x46 || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
 717                 /* This is a big guess, but should be reasonable until we can narrow it down. */
 718                 if (*db1_ratio) {
 719                         special_bits = 0x1;
 720                 } else {
 721                         special_bits = 0x3;
 722                 }
 723         }
 724
 725         /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
 726         *pll_a = (special_bits << 30) | (log2P << 16) | NM1;
 727         /* This VCO2 bit is an educated guess, but it needs to stay on for NV4x. */
 728         *pll_b = NV31_RAMDAC_ENABLE_VCO2 | NM2;
 729
 730         if (*db1_ratio) {
 731                 if (primary) {
 732                         *reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 733                 } else {
 734                         *reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 735                 }
 736         } else {
 737                 if (primary) {
 738                         *reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
 739                 } else {
 740                         *reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
 741                 }
 742         }
 743
 744         if (*db1_ratio) {
 745                 ErrorF("vpll: n1 %d m1 %d p %d db1_ratio %d\n", NM1 >> 8, NM1 & 0xff, log2P, *db1_ratio);
 746         } else {
 747                 ErrorF("vpll: n1 %d n2 %d m1 %d m2 %d p %d db1_ratio %d\n", NM1 >> 8, NM2 >> 8, NM1 & 0xff, NM2 & 0xff, log2P, *db1_ratio);
 748         }
 749 }
 750
 751 static void nv40_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 752 {
 753         state->vpll1_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL);
 754         state->vpll1_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B);
 755         state->vpll2_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2);
 756         state->vpll2_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B);
 757         state->pllsel = NVReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT);
 758         state->sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
 759         state->reg580 = NVReadRAMDAC(pNv, 0, NV_RAMDAC_580);
 760         state->reg594 = NVReadRAMDAC(pNv, 0, NV_RAMDAC_594);
 761 }
 762
 763 static void nv40_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 764 {
 765         ScrnInfoPtr pScrn = crtc->scrn;
 766         NVPtr pNv = NVPTR(pScrn);
 767         uint32_t fp_debug_0[2];
 768         uint32_t index[2];
 769         fp_debug_0[0] = NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
 770         fp_debug_0[1] = NVReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
 771
 772         /* The TMDS_PLL switch is on the actual ramdac */
 773         if (state->crosswired) {
 774                 index[0] = 1;
 775                 index[1] = 0;
 776                 ErrorF("Crosswired pll state load\n");
 777         } else {
 778                 index[0] = 0;
 779                 index[1] = 1;
 780         }
 781
 782         if (state->vpll2_b && state->vpll_changed[1]) {
 783                 NVWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0,
 784                         fp_debug_0[index[1]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 785
 786                 /* Wait for the situation to stabilise */
 787                 usleep(5000);
 788
 789                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 790                 /* for vpll2 change bits 18 and 19 are disabled */
 791                 reg_c040 &= ~(0x3 << 18);
 792                 nvWriteMC(pNv, 0xc040, reg_c040);
 793
 794                 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 795                 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 796
 797                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2_a);
 798                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 799
 800                 ErrorF("writing pllsel %08X\n", state->pllsel);
 801                 /* Don't turn vpll1 off. */
 802                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 803
 804                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 805                 ErrorF("writing reg580 %08X\n", state->reg580);
 806
 807                 /* We need to wait a while */
 808                 usleep(5000);
 809                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 810
 811                 NVWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[1]]);
 812
 813                 /* Wait for the situation to stabilise */
 814                 usleep(5000);
 815         }
 816
 817         if (state->vpll1_b && state->vpll_changed[0]) {
 818                 NVWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0,
 819                         fp_debug_0[index[0]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 820
 821                 /* Wait for the situation to stabilise */
 822                 usleep(5000);
 823
 824                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 825                 /* for vpll2 change bits 16 and 17 are disabled */
 826                 reg_c040 &= ~(0x3 << 16);
 827                 nvWriteMC(pNv, 0xc040, reg_c040);
 828
 829                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 830                 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 831
 832                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll1_a);
 833                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpll1_b);
 834
 835                 ErrorF("writing pllsel %08X\n", state->pllsel);
 836                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 837
 838                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 839                 ErrorF("writing reg580 %08X\n", state->reg580);
 840
 841                 /* We need to wait a while */
 842                 usleep(5000);
 843                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 844
 845                 NVWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[0]]);
 846
 847                 /* Wait for the situation to stabilise */
 848                 usleep(5000);
 849         }
 850
 851         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 852         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 853
 854         ErrorF("writing reg594 %08X\n", state->reg594);
 855         nvWriteRAMDAC0(pNv, NV_RAMDAC_594, state->reg594);
 856
 857         /* All clocks have been set at this point. */
 858         state->vpll_changed[0] = FALSE;
 859         state->vpll_changed[1] = FALSE;
 860 }
 861
 862 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 863 {
 864         state->vpll1_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL);
 865         if (pNv->twoHeads) {
 866                 state->vpll2_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2);
 867         }
 868         if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 869                 state->vpll1_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B);
 870                 state->vpll2_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B);
 871         }
 872         state->pllsel = NVReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT);
 873         state->sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
 874 }
 875
 876
 877 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 878 {
 879         /* This sequence is important, the NV28 is very sensitive in this area. */
 880         /* Keep pllsel last and sel_clk first. */
 881         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 882         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 883
 884         if (state->vpll2_a && state->vpll_changed[1]) {
 885                 if (pNv->twoHeads) {
 886                         ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 887                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2_a);
 888                 }
 889                 if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 890                         ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 891                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 892                 }
 893         }
 894
 895         if (state->vpll1_a && state->vpll_changed[0]) {
 896                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 897                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll1_a);
 898                 if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 899                         ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 900                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpll1_b);
 901                 }
 902         }
 903
 904         ErrorF("writing pllsel %08X\n", state->pllsel);
 905         nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 906
 907         /* All clocks have been set at this point. */
 908         state->vpll_changed[0] = FALSE;
 909         state->vpll_changed[1] = FALSE;
 910 }
 911
 912 #define IS_NV44P (pNv->NVArch >= 0x44 ? 1 : 0)
 913 #define SEL_CLK_OFFSET (nv_get_sel_clk_offset(pNv->NVArch, nv_output->bus))
 914
 915 #define WIPE_OTHER_CLOCKS(_sel_clk, _head, _bus) (nv_wipe_other_clocks(_sel_clk, pNv->NVArch, _head, _bus))
 916
 917 /*
 918  * Calculate extended mode parameters (SVGA) and save in a
 919  * mode state structure.
 920  * State is not specific to a single crtc, but shared.
 921  */
 922 void nv_crtc_calc_state_ext(
 923         xf86CrtcPtr             crtc,
 924         DisplayModePtr  mode,
 925         int                             bpp,
 926         int                             DisplayWidth, /* Does this change after setting the mode? */
 927         int                             CrtcHDisplay,
 928         int                             CrtcVDisplay,
 929         int                             dotClock,
 930         int                             flags
 931 )
 932 {
 933         ScrnInfoPtr pScrn = crtc->scrn;
 934         uint32_t pixelDepth, VClk = 0;
 935         uint32_t CursorStart;
 936         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 937         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 938         NVCrtcRegPtr regp;
 939         NVPtr pNv = NVPTR(pScrn);
 940         RIVA_HW_STATE *state;
 941         int num_crtc_enabled, i;
 942         uint32_t old_clock_a = 0, old_clock_b = 0;
 943
 944         state = &pNv->ModeReg;
 945
 946         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 947
 948         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 949         NVOutputPrivatePtr nv_output = NULL;
 950         Bool is_fp = FALSE;
 951         if (output) {
 952                 nv_output = output->driver_private;
 953                 if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)
 954                         is_fp = TRUE;
 955         }
 956
 957         /* Store old clock. */
 958         if (nv_crtc->head == 1) {
 959                 old_clock_a = state->vpll2_a;
 960                 old_clock_b = state->vpll2_b;
 961         } else {
 962                 old_clock_a = state->vpll1_a;
 963                 old_clock_b = state->vpll1_b;
 964         }
 965
 966         /*
 967          * Extended RIVA registers.
 968          */
 969         /* This is pitch related, not mode related. */
 970         pixelDepth = (bpp + 1)/8;
 971         if (pNv->Architecture == NV_ARCH_40) {
 972                 /* Does register 0x580 already have a value? */
 973                 if (!state->reg580) {
 974                         state->reg580 = pNv->misc_info.ramdac_0_reg_580;
 975                 }
 976                 if (nv_crtc->head == 1) {
 977                         CalculateVClkNV4x(pScrn, dotClock, &VClk, &state->vpll2_a, &state->vpll2_b, &state->reg580, &state->db1_ratio[1], FALSE);
 978                 } else {
 979                         CalculateVClkNV4x(pScrn, dotClock, &VClk, &state->vpll1_a, &state->vpll1_b, &state->reg580, &state->db1_ratio[0], TRUE);
 980                 }
 981         } else if (pNv->twoStagePLL) {
 982                 int NM1, NM2, log2P;
 983                 VClk = getMNP_double(pScrn, 0, dotClock, &NM1, &NM2, &log2P);
 984                 if (pNv->NVArch == 0x30) {
 985                         /* See nvregisters.xml for details. */
 986                         state->pll = log2P << 16 | NM1 | (NM2 & 7) << 4 | ((NM2 >> 8) & 7) << 19 | ((NM2 >> 11) & 3) << 24 | NV30_RAMDAC_ENABLE_VCO2;
 987                 } else {
 988                         state->pll = log2P << 16 | NM1;
 989                         state->pllB = NV31_RAMDAC_ENABLE_VCO2 | NM2;
 990                 }
 991         } else {
 992                 int NM, log2P;
 993                 VClk = getMNP_single(pScrn, 0, dotClock, &NM, &log2P);
 994                 state->pll = log2P << 16 | NM;
 995         }
 996
 997         if (pNv->Architecture < NV_ARCH_40) {
 998                 if (nv_crtc->head == 1) {
 999                         state->vpll2_a = state->pll;
1000                         state->vpll2_b = state->pllB;
1001                 } else {
1002                         state->vpll1_a = state->pll;
1003                         state->vpll1_b = state->pllB;
1004                 }
1005         }
1006
1007         /* always reset vpll, just to be sure. */
1008         state->vpll_changed[nv_crtc->head] = TRUE;
1009
1010         switch (pNv->Architecture) {
1011         case NV_ARCH_04:
1012                 nv4UpdateArbitrationSettings(VClk,
1013                                                 pixelDepth * 8,
1014                                                 &(state->arbitration0),
1015                                                 &(state->arbitration1),
1016                                                 pNv);
1017                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
1018                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
1019                 if (flags & V_DBLSCAN)
1020                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
1021                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
1022                 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
1023                 state->config = 0x00001114;
1024                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
1025                 break;
1026         case NV_ARCH_10:
1027         case NV_ARCH_20:
1028         case NV_ARCH_30:
1029         default:
1030                 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
1031                         ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
1032                         state->arbitration0 = 128;
1033                         state->arbitration1 = 0x0480;
1034                 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
1035                         ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
1036                         nForceUpdateArbitrationSettings(VClk,
1037                                                 pixelDepth * 8,
1038                                                 &(state->arbitration0),
1039                                                 &(state->arbitration1),
1040                                                 pNv);
1041                 } else if (pNv->Architecture < NV_ARCH_30) {
1042                         nv10UpdateArbitrationSettings(VClk,
1043                                                 pixelDepth * 8,
1044                                                 &(state->arbitration0),
1045                                                 &(state->arbitration1),
1046                                                 pNv);
1047                 } else {
1048                         nv30UpdateArbitrationSettings(pNv,
1049                                                 &(state->arbitration0),
1050                                                 &(state->arbitration1));
1051                 }
1052
1053                 if (nv_crtc->head == 1) {
1054                         CursorStart = pNv->Cursor2->offset;
1055                 } else {
1056                         CursorStart = pNv->Cursor->offset;
1057                 }
1058
1059                 if (!NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1060                         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
1061                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
1062                         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
1063                 } else {
1064                         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x0;
1065                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0x0;
1066                         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x0;
1067                 }
1068
1069                 if (flags & V_DBLSCAN)
1070                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
1071
1072                 state->config   = nvReadFB(pNv, NV_PFB_CFG0);
1073                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
1074                 break;
1075         }
1076
1077         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1078                 /* This is a bit of a guess. */
1079                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] |= 0xB8;
1080         }
1081
1082         /* okay do we have 2 CRTCs running ? */
1083         num_crtc_enabled = 0;
1084         for (i = 0; i < xf86_config->num_crtc; i++) {
1085                 if (xf86_config->crtc[i]->enabled) {
1086                         num_crtc_enabled++;
1087                 }
1088         }
1089
1090         ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
1091
1092         /* The main stuff seems to be valid for NV3x also. */
1093         if (pNv->Architecture >= NV_ARCH_30) {
1094                 /* This register is only used on the primary ramdac */
1095                 /* This seems to be needed to select the proper clocks, otherwise bad things happen */
1096
1097                 if (!state->sel_clk)
1098                         state->sel_clk = pNv->misc_info.sel_clk & ~(0xf << 16);
1099
1100                 if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
1101                         /* Only wipe when are a relevant (digital) output. */
1102                         state->sel_clk &= ~(0xf << 16);
1103                         Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1104                         /* Even with two dvi, this should not conflict. */
1105                         if (crossed_clocks) {
1106                                 state->sel_clk |= (0x1 << 16);
1107                         } else {
1108                                 state->sel_clk |= (0x4 << 16);
1109                         }
1110                 }
1111
1112                 /* Some cards, specifically dual dvi/lvds cards set another bitrange.
1113                  * I suspect inverse beheaviour to the normal bitrange, but i am not a 100% certain about this.
1114                  * This is all based on default settings found in mmio-traces.
1115                  * The blob never changes these, as it doesn't run unusual output configurations.
1116                  * It seems to prefer situations that avoid changing these bits (for a good reason?).
1117                  * I still don't know the purpose of value 2, it's similar to 4, but what exactly does it do?
1118                  */
1119
1120                 /* Some extra info:
1121                  * nv30:
1122                  *      bit 0           NVClk spread spectrum on/off
1123                  *      bit 2           MemClk spread spectrum on/off
1124                  *      bit 4           PixClk1 spread spectrum on/off
1125                  *      bit 6           PixClk2 spread spectrum on/off
1126
1127                  *      nv40:
1128                  *      what causes setting of bits not obvious but:
1129                  *      bits 4&5                relate to headA
1130                 *       bits 6&7                relate to headB
1131                 */
1132                 /* Only let digital outputs mess with this, otherwise strange output routings may mess it up. */
1133                 if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
1134                         if (pNv->Architecture == NV_ARCH_40) {
1135                                 for (i = 0; i < 4; i++) {
1136                                         uint32_t var = (state->sel_clk & (0xf << 4*i)) >> 4*i;
1137                                         if (var == 0x1 || var == 0x4) {
1138                                                 state->sel_clk &= ~(0xf << 4*i);
1139                                                 Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1140                                                 if (crossed_clocks) {
1141                                                         state->sel_clk |= (0x4 << 4*i);
1142                                                 } else {
1143                                                         state->sel_clk |= (0x1 << 4*i);
1144                                                 }
1145                                                 break; /* This should only occur once. */
1146                                         }
1147                                 }
1148                         /* Based on NV31M. */
1149                         } else if (pNv->Architecture == NV_ARCH_30) {
1150                                 for (i = 0; i < 4; i++) {
1151                                         uint32_t var = (state->sel_clk & (0xf << 4*i)) >> 4*i;
1152                                         if (var == 0x4 || var == 0x5) {
1153                                                 state->sel_clk &= ~(0xf << 4*i);
1154                                                 Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1155                                                 if (crossed_clocks) {
1156                                                         state->sel_clk |= (0x4 << 4*i);
1157                                                 } else {
1158                                                         state->sel_clk |= (0x5 << 4*i);
1159                                                 }
1160                                                 break; /* This should only occur once. */
1161                                         }
1162                                 }
1163                         }
1164                 }
1165         }
1166
1167         /* Are we crosswired? */
1168         if (output && nv_crtc->head != nv_output->preferred_output) {
1169                 state->crosswired = TRUE;
1170         } else {
1171                 state->crosswired = FALSE;
1172         }
1173
1174         if (nv_crtc->head == 1) {
1175                 if (state->db1_ratio[1]) {
1176                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1177                 } else if (nv_crtc->head == 0) {
1178                         if (state->db1_ratio[0])
1179                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1180                 }
1181         } else {
1182                 /* Do NV1x/NV2x cards need anything in sel_clk? */
1183                 state->sel_clk = 0x0;
1184                 state->crosswired = FALSE;
1185         }
1186
1187         /* The NV40 seems to have more similarities to NV3x than other cards. */
1188         if (pNv->NVArch < 0x41) {
1189                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL;
1190                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL;
1191         }
1192
1193         if (nv_crtc->head == 1) {
1194                 if (!state->db1_ratio[1]) {
1195                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1196                 } else {
1197                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1198                 }
1199                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
1200         } else {
1201                 if (!state->db1_ratio[0]) {
1202                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1203                 } else {
1204                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1205                 }
1206                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
1207         }
1208
1209         /* The blob uses this always, so let's do the same */
1210         if (pNv->Architecture == NV_ARCH_40) {
1211                 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
1212         }
1213
1214         /* The primary output resource doesn't seem to care */
1215         if (output && pNv->Architecture == NV_ARCH_40 && nv_output->output_resource == 1) { /* This is the "output" */
1216                 /* non-zero values are for analog, don't know about tv-out and the likes */
1217                 if (output && nv_output->type != OUTPUT_ANALOG) {
1218                         state->reg594 = 0x0;
1219                 } else if (output) {
1220                         /* Are we a flexible output? */
1221                         if (ffs(pNv->dcb_table.entry[nv_output->dcb_entry].or) & OUTPUT_0) {
1222                                 state->reg594 = 0x1;
1223                                 pNv->restricted_mode = FALSE;
1224                         } else {
1225                                 state->reg594 = 0x0;
1226                                 pNv->restricted_mode = TRUE;
1227                         }
1228
1229                         /* More values exist, but they seem related to the 3rd dac (tv-out?) somehow */
1230                         /* bit 16-19 are bits that are set on some G70 cards */
1231                         /* Those bits are also set to the 3rd OUTPUT register */
1232                         if (nv_crtc->head == 1) {
1233                                 state->reg594 |= 0x100;
1234                         }
1235                 }
1236         }
1237
1238         regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
1239         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
1240         if (pNv->Architecture >= NV_ARCH_30) {
1241                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
1242         }
1243
1244         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1245                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = ((CrtcHDisplay/16) & 0x700) >> 3;
1246         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1247                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((CrtcHDisplay*bpp)/64) & 0x700) >> 3;
1248         } else { /* framebuffer can be larger than crtc scanout area. */
1249                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
1250         }
1251         regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
1252 }
1253
1254 static void
1255 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
1256 {
1257         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1258
1259         ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->head, mode);
1260
1261         if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */
1262                 return;
1263
1264         nv_crtc->last_dpms = mode;
1265
1266         ScrnInfoPtr pScrn = crtc->scrn;
1267         NVPtr pNv = NVPTR(pScrn);
1268         unsigned char seq1 = 0, crtc17 = 0;
1269         unsigned char crtc1A;
1270
1271         if (pNv->twoHeads)
1272                 NVCrtcSetOwner(crtc);
1273
1274         crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
1275         switch(mode) {
1276                 case DPMSModeStandby:
1277                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
1278                 seq1 = 0x20;
1279                 crtc17 = 0x80;
1280                 crtc1A |= 0x80;
1281                 break;
1282         case DPMSModeSuspend:
1283                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
1284                 seq1 = 0x20;
1285                 crtc17 = 0x80;
1286                 crtc1A |= 0x40;
1287                 break;
1288         case DPMSModeOff:
1289                 /* Screen: Off; HSync: Off, VSync: Off */
1290                 seq1 = 0x20;
1291                 crtc17 = 0x00;
1292                 crtc1A |= 0xC0;
1293                 break;
1294         case DPMSModeOn:
1295         default:
1296                 /* Screen: On; HSync: On, VSync: On */
1297                 seq1 = 0x00;
1298                 crtc17 = 0x80;
1299                 break;
1300         }
1301
1302         NVVgaSeqReset(crtc, TRUE);
1303         /* Each head has it's own sequencer, so we can turn it off when we want */
1304         seq1 |= (NVReadVgaSeq(crtc, 0x01) & ~0x20);
1305         NVWriteVgaSeq(crtc, 0x1, seq1);
1306         crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
1307         usleep(10000);
1308         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
1309         NVVgaSeqReset(crtc, FALSE);
1310
1311         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
1312
1313         /* I hope this is the right place */
1314         if (crtc->enabled && mode == DPMSModeOn) {
1315                 pNv->crtc_active[nv_crtc->head] = TRUE;
1316         } else {
1317                 pNv->crtc_active[nv_crtc->head] = FALSE;
1318         }
1319 }
1320
1321 static Bool
1322 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
1323                      DisplayModePtr adjusted_mode)
1324 {
1325         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1326         ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->head);
1327
1328         return TRUE;
1329 }
1330
1331 static void
1332 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1333 {
1334         ScrnInfoPtr pScrn = crtc->scrn;
1335         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1336         NVCrtcRegPtr regp;
1337         NVPtr pNv = NVPTR(pScrn);
1338         NVFBLayout *pLayout = &pNv->CurrentLayout;
1339         int depth = pScrn->depth;
1340
1341         /* This is pitch/memory size related. */
1342         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE))
1343                 depth = pNv->console_mode[nv_crtc->head].bpp;
1344
1345         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1346
1347         /* Calculate our timings */
1348         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
1349         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
1350         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
1351         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
1352         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
1353         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
1354         int vertDisplay         = mode->CrtcVDisplay                    - 1;
1355         int vertStart           = mode->CrtcVSyncStart          - 1;
1356         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
1357         int vertTotal           = mode->CrtcVTotal                      - 2;
1358         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
1359         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
1360
1361         Bool is_fp = FALSE;
1362
1363         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1364         NVOutputPrivatePtr nv_output = NULL;
1365         if (output) {
1366                 nv_output = output->driver_private;
1367
1368                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1369                         is_fp = TRUE;
1370         }
1371
1372         ErrorF("Mode clock: %d\n", mode->Clock);
1373         ErrorF("Adjusted mode clock: %d\n", adjusted_mode->Clock);
1374
1375         /* Reverted to what nv did, because that works for all resolutions on flatpanels */
1376         if (is_fp) {
1377                 vertStart = vertTotal - 3;
1378                 vertEnd = vertTotal - 2;
1379                 vertBlankStart = vertStart;
1380                 horizStart = horizTotal - 5;
1381                 horizEnd = horizTotal - 2;
1382                 horizBlankEnd = horizTotal + 4;
1383                 if (pNv->overlayAdaptor && pNv->Architecture >= NV_ARCH_10) {
1384                         /* This reportedly works around Xv some overlay bandwidth problems*/
1385                         horizTotal += 2;
1386                 }
1387         }
1388
1389         if (mode->Flags & V_INTERLACE)
1390                 vertTotal |= 1;
1391
1392         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
1393         ErrorF("horizStart: 0x%X \n", horizStart);
1394         ErrorF("horizEnd: 0x%X \n", horizEnd);
1395         ErrorF("horizTotal: 0x%X \n", horizTotal);
1396         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
1397         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
1398         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
1399         ErrorF("vertStart: 0x%X \n", vertStart);
1400         ErrorF("vertEnd: 0x%X \n", vertEnd);
1401         ErrorF("vertTotal: 0x%X \n", vertTotal);
1402         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
1403         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
1404
1405         /*
1406         * compute correct Hsync & Vsync polarity
1407         */
1408         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
1409                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
1410
1411                 regp->MiscOutReg = 0x23;
1412                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
1413                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
1414         } else {
1415                 int VDisplay = mode->VDisplay;
1416                 if (mode->Flags & V_DBLSCAN)
1417                         VDisplay *= 2;
1418                 if (mode->VScan > 1)
1419                         VDisplay *= mode->VScan;
1420                 if (VDisplay < 400) {
1421                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
1422                 } else if (VDisplay < 480) {
1423                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
1424                 } else if (VDisplay < 768) {
1425                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
1426                 } else {
1427                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
1428                 }
1429         }
1430
1431         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
1432
1433         /*
1434         * Time Sequencer
1435         */
1436         regp->Sequencer[0] = 0x00;
1437         /* 0x20 disables the sequencer */
1438         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1439                 if (mode->HDisplay == 720) {
1440                         regp->Sequencer[1] = 0x21; /* enable 9/8 mode */
1441                 } else {
1442                         regp->Sequencer[1] = 0x20;
1443                 }
1444         } else {
1445                 if (mode->Flags & V_CLKDIV2) {
1446                         regp->Sequencer[1] = 0x29;
1447                 } else {
1448                         regp->Sequencer[1] = 0x21;
1449                 }
1450         }
1451         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1452                 regp->Sequencer[2] = 0x03; /* select 2 out of 4 planes */
1453         } else {
1454                 regp->Sequencer[2] = 0x0F;
1455         }
1456         regp->Sequencer[3] = 0x00;                     /* Font select */
1457         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1458                 regp->Sequencer[4] = 0x02;
1459         } else {
1460                 regp->Sequencer[4] = 0x0E;                             /* Misc */
1461         }
1462
1463         /*
1464         * CRTC Controller
1465         */
1466         regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
1467         regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
1468         regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
1469         regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0)
1470                                 | SetBit(7);
1471         regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
1472         regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
1473                                 | SetBitField(horizEnd,4:0,4:0);
1474         regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
1475         regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
1476                                 | SetBitField(vertDisplay,8:8,1:1)
1477                                 | SetBitField(vertStart,8:8,2:2)
1478                                 | SetBitField(vertBlankStart,8:8,3:3)
1479                                 | SetBit(4)
1480                                 | SetBitField(vertTotal,9:9,5:5)
1481                                 | SetBitField(vertDisplay,9:9,6:6)
1482                                 | SetBitField(vertStart,9:9,7:7);
1483         regp->CRTC[NV_VGA_CRTCX_PRROWSCN]  = 0x00;
1484         regp->CRTC[NV_VGA_CRTCX_MAXSCLIN]  = SetBitField(vertBlankStart,9:9,5:5)
1485                                 | SetBit(6)
1486                                 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00)
1487                                 | (NVMatchModePrivate(mode, NV_MODE_VGA) ? 0xF : 0x00); /* 8x15 chars */
1488         if (NVMatchModePrivate(mode, NV_MODE_VGA)) { /* Were do these cursor offsets come from? */
1489                 regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0xD; /* start scanline */
1490                 regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0xE; /* end scanline */
1491         } else {
1492                 regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0x00;
1493                 regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0x00;
1494         }
1495         regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00;
1496         regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
1497         regp->CRTC[0xe] = 0x00;
1498         regp->CRTC[0xf] = 0x00;
1499         regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
1500         /* What is the meaning of bit5, it is empty in the vga spec. */
1501         regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) |
1502                                                                         (NVMatchModePrivate(mode, NV_MODE_VGA) ? 0 : SetBit(5));
1503         regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
1504         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1505                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = (mode->CrtcHDisplay/16);
1506         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1507                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((mode->CrtcHDisplay*depth)/64);
1508         } else { /* framebuffer can be larger than crtc scanout area. */
1509                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
1510         }
1511         if (depth == 4) { /* How can these values be calculated? */
1512                 regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x1F;
1513         } else {
1514                 regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x00;
1515         }
1516         regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
1517         regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
1518         /* 0x80 enables the sequencer, we don't want that */
1519         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1520                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xA3 & ~0x80;
1521         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1522                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xE3 & ~0x80;
1523         } else {
1524                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80;
1525         }
1526         regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
1527
1528         /*
1529          * Some extended CRTC registers (they are not saved with the rest of the vga regs).
1530          */
1531
1532         regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
1533                                 | SetBitField(vertBlankStart,10:10,3:3)
1534                                 | SetBitField(vertStart,10:10,2:2)
1535                                 | SetBitField(vertDisplay,10:10,1:1)
1536                                 | SetBitField(vertTotal,10:10,0:0);
1537
1538         regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
1539                                 | SetBitField(horizDisplay,8:8,1:1)
1540                                 | SetBitField(horizBlankStart,8:8,2:2)
1541                                 | SetBitField(horizStart,8:8,3:3);
1542
1543         regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
1544                                 | SetBitField(vertDisplay,11:11,2:2)
1545                                 | SetBitField(vertStart,11:11,4:4)
1546                                 | SetBitField(vertBlankStart,11:11,6:6);
1547
1548         if(mode->Flags & V_INTERLACE) {
1549                 horizTotal = (horizTotal >> 1) & ~1;
1550                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
1551                 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
1552         } else {
1553                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff;  /* interlace off */
1554         }
1555
1556         /*
1557         * Theory resumes here....
1558         */
1559
1560         /*
1561         * Graphics Display Controller
1562         */
1563         regp->Graphics[0] = 0x00;
1564         regp->Graphics[1] = 0x00;
1565         regp->Graphics[2] = 0x00;
1566         regp->Graphics[3] = 0x00;
1567         regp->Graphics[4] = 0x00;
1568         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1569                 regp->Graphics[5] = 0x10;
1570                 regp->Graphics[6] = 0x0E; /* map 32k mem */
1571                 regp->Graphics[7] = 0x00;
1572         } else {
1573                 regp->Graphics[5] = 0x40; /* 256 color mode */
1574                 regp->Graphics[6] = 0x05; /* map 64k mem + graphic mode */
1575                 regp->Graphics[7] = 0x0F;
1576         }
1577         regp->Graphics[8] = 0xFF;
1578
1579         /* I ditched the mono stuff */
1580         regp->Attribute[0]  = 0x00; /* standard colormap translation */
1581         regp->Attribute[1]  = 0x01;
1582         regp->Attribute[2]  = 0x02;
1583         regp->Attribute[3]  = 0x03;
1584         regp->Attribute[4]  = 0x04;
1585         regp->Attribute[5]  = 0x05;
1586         regp->Attribute[6]  = 0x06;
1587         regp->Attribute[7]  = 0x07;
1588         regp->Attribute[8]  = 0x08;
1589         regp->Attribute[9]  = 0x09;
1590         regp->Attribute[10] = 0x0A;
1591         regp->Attribute[11] = 0x0B;
1592         regp->Attribute[12] = 0x0C;
1593         regp->Attribute[13] = 0x0D;
1594         regp->Attribute[14] = 0x0E;
1595         regp->Attribute[15] = 0x0F;
1596         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1597                 regp->Attribute[16] = 0x0C; /* Line Graphics Enable + Blink enable */
1598         } else {
1599                 regp->Attribute[16] = 0x01; /* Enable graphic mode */
1600         }
1601         /* Non-vga */
1602         regp->Attribute[17] = 0x00;
1603         regp->Attribute[18] = 0x0F; /* enable all color planes */
1604         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1605                 regp->Attribute[19] = 0x08; /* shift bits by 8 */
1606         } else {
1607                 regp->Attribute[19] = 0x00;
1608         }
1609         regp->Attribute[20] = 0x00;
1610 }
1611
1612 #define MAX_H_VALUE(i) ((0x1ff + i) << 3)
1613 #define MAX_V_VALUE(i) ((0xfff + i) << 0)
1614
1615 /**
1616  * Sets up registers for the given mode/adjusted_mode pair.
1617  *
1618  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1619  *
1620  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1621  * be easily turned on/off after this.
1622  */
1623 static void
1624 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1625 {
1626         ScrnInfoPtr pScrn = crtc->scrn;
1627         NVPtr pNv = NVPTR(pScrn);
1628         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1629         NVFBLayout *pLayout = &pNv->CurrentLayout;
1630         NVCrtcRegPtr regp, savep;
1631         uint32_t i, depth;
1632         Bool is_fp = FALSE;
1633         Bool is_lvds = FALSE;
1634
1635         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1636         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1637
1638         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1639         NVOutputPrivatePtr nv_output = NULL;
1640         if (output) {
1641                 nv_output = output->driver_private;
1642
1643                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1644                         is_fp = TRUE;
1645
1646                 if (nv_output->type == OUTPUT_LVDS)
1647                         is_lvds = TRUE;
1648         }
1649
1650         /* Registers not directly related to the (s)vga mode */
1651
1652         /* bit2 = 0 -> fine pitched crtc granularity */
1653         /* The rest disables double buffering on CRTC access */
1654         regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
1655
1656         if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
1657                 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1658                 if (nv_crtc->head == 0) {
1659                         regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1660                 }
1661
1662                 if (is_fp) {
1663                         regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0);
1664                         if (!NVMatchModePrivate(mode, NV_MODE_VGA)) {
1665                                 regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 1);
1666                         }
1667                 }
1668         } else {
1669                 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
1670                 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
1671         }
1672
1673         /* Sometimes 0x10 is used, what is this? */
1674         regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1675         /* Some kind of tmds switch for older cards */
1676         if (pNv->Architecture < NV_ARCH_40) {
1677                 regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
1678         }
1679
1680         /*
1681         * Initialize DAC palette.
1682         * Will only be written when depth != 8.
1683         */
1684         for (i = 0; i < 256; i++) {
1685                 regp->DAC[i*3] = i;
1686                 regp->DAC[(i*3)+1] = i;
1687                 regp->DAC[(i*3)+2] = i;
1688         }
1689
1690         /*
1691         * Calculate the extended registers.
1692         */
1693
1694         if (pLayout->depth < 24) {
1695                 depth = pLayout->depth;
1696         } else {
1697                 depth = 32;
1698         }
1699
1700         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1701                 /* bpp is pitch related. */
1702                 depth = pNv->console_mode[nv_crtc->head].bpp;
1703         }
1704
1705         /* What is the meaning of this register? */
1706         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1707         regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
1708
1709         regp->head = 0;
1710
1711         /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1712         /* But what are those special conditions? */
1713         if (pNv->Architecture <= NV_ARCH_30) {
1714                 if (is_fp) {
1715                         if(nv_crtc->head == 1) {
1716                                 regp->head |= NV_CRTC_FSEL_FPP1;
1717                         } else if (pNv->twoHeads) {
1718                                 regp->head |= NV_CRTC_FSEL_FPP2;
1719                         }
1720                 }
1721         } else {
1722                 /* Most G70 cards have FPP2 set on the secondary CRTC. */
1723                 if (nv_crtc->head == 1 && pNv->NVArch > 0x44) {
1724                         regp->head |= NV_CRTC_FSEL_FPP2;
1725                 }
1726         }
1727
1728         /* Except for rare conditions I2C is enabled on the primary crtc */
1729         if (nv_crtc->head == 0) {
1730                 regp->head |= NV_CRTC_FSEL_I2C;
1731         }
1732
1733         /* Set overlay to desired crtc. */
1734         if (pNv->overlayAdaptor) {
1735                 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(pNv);
1736                 if (pPriv->overlayCRTC == nv_crtc->head)
1737                         regp->head |= NV_CRTC_FSEL_OVERLAY;
1738         }
1739
1740         /* This is not what nv does, but it is what the blob does (for nv4x at least) */
1741         /* This fixes my cursor corruption issue */
1742         regp->cursorConfig = 0x0;
1743         if(mode->Flags & V_DBLSCAN)
1744                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_DOUBLE_SCAN;
1745         if (pNv->alphaCursor && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1746                 regp->cursorConfig |=   (NV_CRTC_CURSOR_CONFIG_32BPP |
1747                                                         NV_CRTC_CURSOR_CONFIG_64PIXELS |
1748                                                         NV_CRTC_CURSOR_CONFIG_64LINES |
1749                                                         NV_CRTC_CURSOR_CONFIG_ALPHA_BLEND);
1750         } else {
1751                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_32LINES;
1752         }
1753
1754         /* Unblock some timings */
1755         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1756         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1757
1758         /* What is the purpose of this register? */
1759         /* 0x14 may be disabled? */
1760         regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1761
1762         /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
1763         if (is_lvds) {
1764                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x11;
1765         } else if (is_fp) {
1766                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1767         } else {
1768                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1769         }
1770
1771         /* These values seem to vary */
1772         /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
1773         regp->CRTC[NV_VGA_CRTCX_3C] = savep->CRTC[NV_VGA_CRTCX_3C];
1774
1775         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1776                 regp->CRTC[NV_VGA_CRTCX_45] = 0x0;
1777         } else {
1778                 regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1779         }
1780
1781         /* What does this do?:
1782          * bit0: crtc0
1783          * bit6: lvds
1784          * bit7: lvds + tmds (only in X)
1785          */
1786         if (nv_crtc->head == 0)
1787                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x1;
1788         else
1789                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x0;
1790
1791         if (is_lvds)
1792                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x40;
1793
1794         if (is_fp && !NVMatchModePrivate(mode, NV_MODE_VGA))
1795                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x80;
1796
1797         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) { /* we need consistent restore. */
1798                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[nv_crtc->head];
1799         } else {
1800                 /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1.*/
1801                 if (nv_crtc->head == 1) {
1802                         regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[0];
1803                 } else {
1804                         regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[0] + 4;
1805                 }
1806         }
1807
1808         if (pNv->twoHeads)
1809                 /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1810                 regp->unk81c = NVReadCRTC(pNv, 0, NV_CRTC_081C);
1811
1812         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1813                 regp->unk830 = 0;
1814                 regp->unk834 = 0;
1815         } else {
1816                 regp->unk830 = mode->CrtcVDisplay - 3;
1817                 regp->unk834 = mode->CrtcVDisplay - 1;
1818         }
1819
1820         if (pNv->twoHeads)
1821                 /* This is what the blob does */
1822                 regp->unk850 = NVReadCRTC(pNv, 0, NV_CRTC_0850);
1823
1824         /* Never ever modify gpio, unless you know very well what you're doing */
1825         regp->gpio = NVReadCRTC(pNv, 0, NV_CRTC_GPIO);
1826
1827         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1828                 regp->config = 0x0; /* VGA mode */
1829         } else {
1830                 regp->config = 0x2; /* HSYNC mode */
1831         }
1832
1833         /* Some misc regs */
1834         regp->CRTC[NV_VGA_CRTCX_43] = 0x1;
1835         if (pNv->Architecture == NV_ARCH_40) {
1836                 regp->CRTC[NV_VGA_CRTCX_85] = 0xFF;
1837                 regp->CRTC[NV_VGA_CRTCX_86] = 0x1;
1838         }
1839
1840         /*
1841          * Calculate the state that is common to all crtc's (stored in the state struct).
1842          */
1843         ErrorF("crtc %d %d %d\n", nv_crtc->head, mode->CrtcHDisplay, pScrn->displayWidth);
1844         nv_crtc_calc_state_ext(crtc,
1845                                 mode,
1846                                 depth,
1847                                 pScrn->displayWidth,
1848                                 mode->CrtcHDisplay,
1849                                 mode->CrtcVDisplay,
1850                                 adjusted_mode->Clock,
1851                                 mode->Flags);
1852
1853         /* Enable slaved mode */
1854         if (is_fp) {
1855                 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1856         }
1857 }
1858
1859 static void
1860 nv_crtc_mode_set_ramdac_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1861 {
1862         ScrnInfoPtr pScrn = crtc->scrn;
1863         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1864         NVCrtcRegPtr regp, savep;
1865         NVPtr pNv = NVPTR(pScrn);
1866         NVFBLayout *pLayout = &pNv->CurrentLayout;
1867         Bool is_fp = FALSE;
1868         Bool is_lvds = FALSE;
1869         float aspect_ratio, panel_ratio;
1870         uint32_t h_scale, v_scale;
1871
1872         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1873         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1874
1875         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1876         NVOutputPrivatePtr nv_output = NULL;
1877         if (output) {
1878                 nv_output = output->driver_private;
1879
1880                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1881                         is_fp = TRUE;
1882
1883                 if (nv_output->type == OUTPUT_LVDS)
1884                         is_lvds = TRUE;
1885         }
1886
1887         if (is_fp) {
1888                 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
1889                 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
1890                 /* This is what the blob does. */
1891                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HSyncStart - 75 - 1;
1892                 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
1893                 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
1894                 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
1895                 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
1896
1897                 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
1898                 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
1899                 /* This is what the blob does. */
1900                 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VTotal - 5 - 1;
1901                 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
1902                 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
1903                 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
1904                 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
1905
1906                 ErrorF("Horizontal:\n");
1907                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
1908                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
1909                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
1910                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
1911                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
1912                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
1913                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
1914
1915                 ErrorF("Vertical:\n");
1916                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
1917                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
1918                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
1919                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
1920                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
1921                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
1922                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
1923         }
1924
1925         /*
1926         * bit0: positive vsync
1927         * bit4: positive hsync
1928         * bit8: enable center mode
1929         * bit9: enable native mode
1930         * bit24: 12/24 bit interface (12bit=on, 24bit=off)
1931         * bit26: a bit sometimes seen on some g70 cards
1932         * bit28: fp display enable bit
1933         * bit31: set for dual link LVDS
1934         * nv10reg contains a few more things, but i don't quite get what it all means.
1935         */
1936
1937         if (pNv->Architecture >= NV_ARCH_30)
1938                 regp->fp_control[nv_crtc->head] = 0x00100000;
1939         else
1940                 regp->fp_control[nv_crtc->head] = 0x00000000;
1941
1942         /* Deal with vsync/hsync polarity */
1943         /* LVDS screens do set this, but modes with +ve syncs are very rare */
1944         if (is_fp) {
1945                 if (adjusted_mode->Flags & V_PVSYNC)
1946                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
1947                 if (adjusted_mode->Flags & V_PHSYNC)
1948                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
1949         } else {
1950                 /* The blob doesn't always do this, but often */
1951                 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_VSYNC_DISABLE;
1952                 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_HSYNC_DISABLE;
1953         }
1954
1955         if (is_fp) {
1956                 if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) /* seems to be used almost always */
1957                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1958                 else if (nv_output->scaling_mode == SCALE_PANEL) /* panel needs to scale */
1959                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
1960                 /* This is also true for panel scaling, so we must put the panel scale check first */
1961                 else if (mode->Clock == adjusted_mode->Clock) /* native mode */
1962                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
1963                 else /* gpu needs to scale */
1964                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1965         }
1966
1967         if (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
1968                 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
1969
1970         /* If the special bit exists, it exists on both ramdacs */
1971         regp->fp_control[nv_crtc->head] |= NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL) & (1 << 26);
1972
1973         if (is_fp)
1974                 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS;
1975         else
1976                 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE;
1977
1978         Bool lvds_use_straps = pNv->dcb_table.entry[nv_output->dcb_entry].lvdsconf.use_straps_for_mode;
1979         if (is_lvds && ((lvds_use_straps && pNv->VBIOS.fp.dual_link) || (!lvds_use_straps && adjusted_mode->Clock >= pNv->VBIOS.fp.duallink_transition_clk)))
1980                 regp->fp_control[nv_crtc->head] |= (8 << 28);
1981
1982         if (is_fp) {
1983                 ErrorF("Pre-panel scaling\n");
1984                 ErrorF("panel-size:%dx%d\n", nv_output->fpWidth, nv_output->fpHeight);
1985                 panel_ratio = (nv_output->fpWidth)/(float)(nv_output->fpHeight);
1986                 ErrorF("panel_ratio=%f\n", panel_ratio);
1987                 aspect_ratio = (mode->HDisplay)/(float)(mode->VDisplay);
1988                 ErrorF("aspect_ratio=%f\n", aspect_ratio);
1989                 /* Scale factors is the so called 20.12 format, taken from Haiku */
1990                 h_scale = ((1 << 12) * mode->HDisplay)/nv_output->fpWidth;
1991                 v_scale = ((1 << 12) * mode->VDisplay)/nv_output->fpHeight;
1992                 ErrorF("h_scale=%d\n", h_scale);
1993                 ErrorF("v_scale=%d\n", v_scale);
1994
1995                 /* This can override HTOTAL and VTOTAL */
1996                 regp->debug_2 = 0;
1997
1998                 /* We want automatic scaling */
1999                 regp->debug_1 = 0;
2000
2001                 regp->fp_hvalid_start = 0;
2002                 regp->fp_hvalid_end = (nv_output->fpWidth - 1);
2003
2004                 regp->fp_vvalid_start = 0;
2005                 regp->fp_vvalid_end = (nv_output->fpHeight - 1);
2006
2007                 /* 0 = panel scaling */
2008                 if (nv_output->scaling_mode == SCALE_PANEL) {
2009                         ErrorF("Flat panel is doing the scaling.\n");
2010                 } else {
2011                         ErrorF("GPU is doing the scaling.\n");
2012
2013                         if (nv_output->scaling_mode == SCALE_ASPECT) {
2014                                 /* GPU scaling happens automaticly at a ratio of 1.33 */
2015                                 /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
2016                                 if (h_scale != (1 << 12) && (panel_ratio > (aspect_ratio + 0.10))) {
2017                                         uint32_t diff;
2018
2019                                         ErrorF("Scaling resolution on a widescreen panel\n");
2020
2021                                         /* Scaling in both directions needs to the same */
2022                                         h_scale = v_scale;
2023
2024                                         /* Set a new horizontal scale factor and enable testmode (bit12) */
2025                                         regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
2026
2027                                         diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
2028                                         regp->fp_hvalid_start = diff/2;
2029                                         regp->fp_hvalid_end = nv_output->fpWidth - (diff/2) - 1;
2030                                 }
2031
2032                                 /* Same scaling, just for panels with aspect ratio's smaller than 1 */
2033                                 if (v_scale != (1 << 12) && (panel_ratio < (aspect_ratio - 0.10))) {
2034                                         uint32_t diff;
2035
2036                                         ErrorF("Scaling resolution on a portrait panel\n");
2037
2038                                         /* Scaling in both directions needs to the same */
2039                                         v_scale = h_scale;
2040
2041                                         /* Set a new vertical scale factor and enable testmode (bit28) */
2042                                         regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
2043
2044                                         diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
2045                                         regp->fp_vvalid_start = diff/2;
2046                                         regp->fp_vvalid_end = nv_output->fpHeight - (diff/2) - 1;
2047                                 }
2048                         }
2049                 }
2050
2051                 ErrorF("Post-panel scaling\n");
2052         }
2053
2054         if (!is_fp && NVMatchModePrivate(mode, NV_MODE_VGA)) {
2055                 regp->debug_1 = 0x08000800;
2056         }
2057
2058         if (pNv->Architecture >= NV_ARCH_10) {
2059                 /* Bios and blob don't seem to do anything (else) */
2060                 if (!NVMatchModePrivate(mode, NV_MODE_CONSOLE))
2061                         regp->nv10_cursync = (1<<25);
2062                 else
2063                         regp->nv10_cursync = 0;
2064         }
2065
2066         /* These are the common blob values, minus a few fp specific bit's */
2067         /* Let's keep the TMDS pll and fpclock running in all situations */
2068         regp->debug_0[nv_crtc->head] = 0x1101100;
2069
2070         if (is_fp && nv_output->scaling_mode != SCALE_NOSCALE) {
2071                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_XSCALE_ENABLED;
2072                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_YSCALE_ENABLED;
2073         } else if (is_fp) { /* no_scale mode, so we must center it */
2074                 uint32_t diff;
2075
2076                 diff = nv_output->fpWidth - mode->HDisplay;
2077                 regp->fp_hvalid_start = diff/2;
2078                 regp->fp_hvalid_end = (nv_output->fpWidth - diff/2 - 1);
2079
2080                 diff = nv_output->fpHeight - mode->VDisplay;
2081                 regp->fp_vvalid_start = diff/2;
2082                 regp->fp_vvalid_end = (nv_output->fpHeight - diff/2 - 1);
2083         }
2084
2085         /* Is this crtc bound or output bound? */
2086         /* Does the bios TMDS script try to change this sometimes? */
2087         if (is_fp) {
2088                 /* I am not completely certain, but seems to be set only for dfp's */
2089                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED;
2090         }
2091
2092         if (output)
2093                 ErrorF("output %d debug_0 %08X\n", nv_output->output_resource, regp->debug_0[nv_crtc->head]);
2094
2095         /* Flatpanel support needs at least a NV10 */
2096         if (pNv->twoHeads) {
2097                 /* The blob does this differently. */
2098                 /* TODO: Find out what precisely and why. */
2099                 /* Let's not destroy any bits that were already present. */
2100                 if (pNv->FPDither || (is_lvds && pNv->VBIOS.fp.if_is_18bit)) {
2101                         if (pNv->NVArch == 0x11) {
2102                                 regp->dither = savep->dither | 0x00010000;
2103                         } else {
2104                                 regp->dither = savep->dither | 0x00000001;
2105                         }
2106                 } else {
2107                         regp->dither = savep->dither;
2108                 }
2109         }
2110
2111         uint8_t depth;
2112         /* This is mode related, not pitch. */
2113         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
2114                 depth = pNv->console_mode[nv_crtc->head].depth;
2115         } else {
2116                 depth = pLayout->depth;
2117         }
2118
2119         switch (depth) {
2120                 case 4:
2121                         regp->general = 0x00000100;
2122                         break;
2123                 case 24:
2124                 case 15:
2125                         regp->general = 0x00100100;
2126                         break;
2127                 case 32:
2128                 case 16:
2129                 case 8:
2130                 default:
2131                         regp->general = 0x00101100;
2132                         break;
2133         }
2134
2135         if (depth > 8 && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
2136                 regp->general |= 0x30; /* enable palette mode */
2137         }
2138
2139         if (pNv->alphaCursor && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
2140                 /* PIPE_LONG mode, something to do with the size of the cursor? */
2141                 regp->general |= (1<<29);
2142         }
2143
2144         /* Some values the blob sets */
2145         /* This may apply to the real ramdac that is being used (for crosswired situations) */
2146         /* Nevertheless, it's unlikely to cause many problems, since the values are equal for both */
2147         regp->unk_a20 = 0x0;
2148         regp->unk_a24 = 0xfffff;
2149         regp->unk_a34 = 0x1;
2150
2151         if (pNv->twoHeads) {
2152                 /* Do we also "own" the other register pair? */
2153                 /* If we own neither, they will just be ignored at load time. */
2154                 uint8_t other_head = (~nv_crtc->head) & 1;
2155                 if (pNv->fp_regs_owner[other_head] == nv_crtc->head) {
2156                         if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS) {
2157                                 regp->fp_control[other_head] = regp->fp_control[nv_crtc->head];
2158                                 regp->debug_0[other_head] = regp->debug_0[nv_crtc->head];
2159                                 /* Set TMDS_PLL and FPCLK, only seen for a NV31M so far. */
2160                                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK;
2161                                 regp->debug_0[other_head] |= NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL;
2162                         } else {
2163                                 ErrorF("This is BAD, we own more than one fp reg set, but are not a LVDS or TMDS output.\n");
2164                         }
2165                 }
2166         }
2167 }
2168
2169 /**
2170  * Sets up registers for the given mode/adjusted_mode pair.
2171  *
2172  * The clocks, CRTCs and outputs attached to this CRTC must be off.
2173  *
2174  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
2175  * be easily turned on/off after this.
2176  */
2177 static void
2178 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
2179                  DisplayModePtr adjusted_mode,
2180                  int x, int y)
2181 {
2182         ScrnInfoPtr pScrn = crtc->scrn;
2183         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2184         NVPtr pNv = NVPTR(pScrn);
2185         NVFBLayout *pLayout = &pNv->CurrentLayout;
2186
2187         ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->head);
2188
2189         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->head);
2190         xf86PrintModeline(pScrn->scrnIndex, mode);
2191         if (pNv->twoHeads)
2192                 NVCrtcSetOwner(crtc);
2193
2194         nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
2195         nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
2196         nv_crtc_mode_set_ramdac_regs(crtc, mode, adjusted_mode);
2197
2198         NVVgaProtect(crtc, TRUE);
2199         nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
2200         nv_crtc_load_state_ext(crtc, &pNv->ModeReg, FALSE);
2201         if (pLayout->depth > 8)
2202                 NVCrtcLoadPalette(crtc);
2203         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
2204         if (pNv->Architecture == NV_ARCH_40) {
2205                 nv40_crtc_load_state_pll(crtc, &pNv->ModeReg);
2206         } else {
2207                 nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
2208         }
2209
2210         NVVgaProtect(crtc, FALSE);
2211
2212         NVCrtcSetBase(crtc, x, y, NVMatchModePrivate(mode, NV_MODE_CONSOLE));
2213
2214 #if X_BYTE_ORDER == X_BIG_ENDIAN
2215         /* turn on LFB swapping */
2216         {
2217                 unsigned char tmp;
2218
2219                 tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
2220                 tmp |= (1 << 7);
2221                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
2222         }
2223 #endif
2224 }
2225
2226 /* This functions generates data that is not saved, but still is needed. */
2227 void nv_crtc_restore_generate(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2228 {
2229         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2230         ScrnInfoPtr pScrn = crtc->scrn;
2231         NVPtr pNv = NVPTR(pScrn);
2232         int i;
2233         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
2234
2235         /* It's a good idea to also save a default palette on shutdown. */
2236         for (i = 0; i < 256; i++) {
2237                 regp->DAC[i*3] = i;
2238                 regp->DAC[(i*3)+1] = i;
2239                 regp->DAC[(i*3)+2] = i;
2240         }
2241
2242         /* Noticed that reading this variable is problematic on one card. */
2243         if (pNv->NVArch == 0x11)
2244                 state->sel_clk = 0x0;
2245 }
2246
2247 void nv_crtc_save(xf86CrtcPtr crtc)
2248 {
2249         ScrnInfoPtr pScrn = crtc->scrn;
2250         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2251         NVPtr pNv = NVPTR(pScrn);
2252
2253         ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->head);
2254
2255         /* We just came back from terminal, so unlock */
2256         NVCrtcLockUnlock(crtc, FALSE);
2257
2258         if (pNv->twoHeads)
2259                 NVCrtcSetOwner(crtc);
2260         nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
2261         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
2262         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
2263         if (pNv->Architecture == NV_ARCH_40) {
2264                 nv40_crtc_save_state_pll(pNv, &pNv->SavedReg);
2265         } else {
2266                 nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
2267         }
2268 }
2269
2270 void nv_crtc_restore(xf86CrtcPtr crtc)
2271 {
2272         ScrnInfoPtr pScrn = crtc->scrn;
2273         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2274         NVPtr pNv = NVPTR(pScrn);
2275         RIVA_HW_STATE *state;
2276         NVCrtcRegPtr savep;
2277
2278         state = &pNv->SavedReg;
2279         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
2280
2281         ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->head);
2282
2283         if (pNv->twoHeads)
2284                 NVCrtcSetOwner(crtc);
2285
2286         /* Just to be safe */
2287         NVCrtcLockUnlock(crtc, FALSE);
2288
2289         NVVgaProtect(crtc, TRUE);
2290         nv_crtc_restore_generate(crtc, &pNv->SavedReg);
2291         nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
2292         nv_crtc_load_state_ext(crtc, &pNv->SavedReg, TRUE);
2293         if (savep->general & 0x30) /* Palette mode */
2294                 NVCrtcLoadPalette(crtc);
2295         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
2296
2297         /* Force restoring vpll. */
2298         state->vpll_changed[nv_crtc->head] = TRUE;
2299
2300         if (pNv->Architecture == NV_ARCH_40) {
2301                 nv40_crtc_load_state_pll(crtc, &pNv->SavedReg);
2302         } else {
2303                 nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
2304         }
2305         if (pNv->twoHeads)
2306                 nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->vtOWNER);
2307         NVVgaProtect(crtc, FALSE);
2308
2309         nv_crtc->last_dpms = NV_DPMS_CLEARED;
2310 }
2311
2312 static void
2313 NVResetCrtcConfig(xf86CrtcPtr crtc, Bool set)
2314 {
2315         ScrnInfoPtr pScrn = crtc->scrn;
2316         NVPtr pNv = NVPTR(pScrn);
2317
2318         if (pNv->twoHeads) {
2319                 uint32_t val = 0;
2320
2321                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2322
2323                 if (set) {
2324                         NVCrtcRegPtr regp;
2325
2326                         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2327                         val = regp->head;
2328                 }
2329
2330                 NVCrtcWriteCRTC(crtc, NV_CRTC_FSEL, val);
2331         }
2332 }
2333
2334 void nv_crtc_prepare(xf86CrtcPtr crtc)
2335 {
2336         ScrnInfoPtr pScrn = crtc->scrn;
2337         NVPtr pNv = NVPTR(pScrn);
2338         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2339
2340         ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->head);
2341
2342         /* Just in case */
2343         NVCrtcLockUnlock(crtc, 0);
2344
2345         NVResetCrtcConfig(crtc, FALSE);
2346
2347         crtc->funcs->dpms(crtc, DPMSModeOff);
2348
2349         /* Sync the engine before adjust mode */
2350         if (pNv->EXADriverPtr) {
2351                 exaMarkSync(pScrn->pScreen);
2352                 exaWaitSync(pScrn->pScreen);
2353         }
2354
2355         NVCrtcBlankScreen(crtc, FALSE); /* Blank screen */
2356
2357         /* Some more preperation. */
2358         NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, 0x1); /* Go to non-vga mode/out of enhanced mode */
2359         if (pNv->Architecture == NV_ARCH_40) {
2360                 uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
2361                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
2362         }
2363 }
2364
2365 void nv_crtc_commit(xf86CrtcPtr crtc)
2366 {
2367         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2368         ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->head);
2369
2370         crtc->funcs->dpms (crtc, DPMSModeOn);
2371
2372         if (crtc->scrn->pScreen != NULL)
2373                 xf86_reload_cursors (crtc->scrn->pScreen);
2374
2375         NVResetCrtcConfig(crtc, TRUE);
2376 }
2377
2378 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
2379 {
2380         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2381         ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->head);
2382
2383         return FALSE;
2384 }
2385
2386 static void nv_crtc_unlock(xf86CrtcPtr crtc)
2387 {
2388         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2389         ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->head);
2390 }
2391
2392 static void
2393 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
2394                                         int size)
2395 {
2396         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2397         ScrnInfoPtr pScrn = crtc->scrn;
2398         NVPtr pNv = NVPTR(pScrn);
2399         int i, j;
2400
2401         NVCrtcRegPtr regp;
2402         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2403
2404         switch (pNv->CurrentLayout.depth) {
2405         case 15:
2406                 /* R5G5B5 */
2407                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
2408                 for (i = 0; i < 32; i++) {
2409                         for (j = 0; j < 8; j++) {
2410                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2411                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
2412                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2413                         }
2414                 }
2415                 break;
2416         case 16:
2417                 /* R5G6B5 */
2418                 /* First deal with the 5 bit colors */
2419                 for (i = 0; i < 32; i++) {
2420                         for (j = 0; j < 8; j++) {
2421                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2422                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2423                         }
2424                 }
2425                 /* Now deal with the 6 bit color */
2426                 for (i = 0; i < 64; i++) {
2427                         for (j = 0; j < 4; j++) {
2428                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
2429                         }
2430                 }
2431                 break;
2432         default:
2433                 /* R8G8B8 */
2434                 for (i = 0; i < 256; i++) {
2435                         regp->DAC[i * 3] = red[i] >> 8;
2436                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
2437                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
2438                 }
2439                 break;
2440         }
2441
2442         NVCrtcLoadPalette(crtc);
2443 }
2444
2445 /**
2446  * Allocates memory for a locked-in-framebuffer shadow of the given
2447  * width and height for this CRTC's rotated shadow framebuffer.
2448  */
2449
2450 static void *
2451 nv_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
2452 {
2453         ErrorF("nv_crtc_shadow_allocate is called\n");
2454         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2455         ScrnInfoPtr pScrn = crtc->scrn;
2456 #if !NOUVEAU_EXA_PIXMAPS
2457         ScreenPtr pScreen = pScrn->pScreen;
2458 #endif /* !NOUVEAU_EXA_PIXMAPS */
2459         NVPtr pNv = NVPTR(pScrn);
2460         void *offset;
2461
2462         unsigned long rotate_pitch;
2463         int size, align = 64;
2464
2465         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2466         size = rotate_pitch * height;
2467
2468         assert(nv_crtc->shadow == NULL);
2469 #if NOUVEAU_EXA_PIXMAPS
2470         if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN,
2471                         align, size, &nv_crtc->shadow)) {
2472                 ErrorF("Failed to allocate memory for shadow buffer!\n");
2473                 return NULL;
2474         }
2475
2476         if (nv_crtc->shadow && nouveau_bo_map(nv_crtc->shadow, NOUVEAU_BO_RDWR)) {
2477                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2478                                 "Failed to map shadow buffer.\n");
2479                 return NULL;
2480         }
2481
2482         offset = nv_crtc->shadow->map;
2483 #else
2484         nv_crtc->shadow = exaOffscreenAlloc(pScreen, size, align, TRUE, NULL, NULL);
2485         if (nv_crtc->shadow == NULL) {
2486                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2487                         "Couldn't allocate shadow memory for rotated CRTC\n");
2488                 return NULL;
2489         }
2490         offset = pNv->FB->map + nv_crtc->shadow->offset;
2491 #endif /* NOUVEAU_EXA_PIXMAPS */
2492
2493         return offset;
2494 }
2495
2496 /**
2497  * Creates a pixmap for this CRTC's rotated shadow framebuffer.
2498  */
2499 static PixmapPtr
2500 nv_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
2501 {
2502         ErrorF("nv_crtc_shadow_create is called\n");
2503         ScrnInfoPtr pScrn = crtc->scrn;
2504 #if NOUVEAU_EXA_PIXMAPS
2505         ScreenPtr pScreen = pScrn->pScreen;
2506         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2507 #endif /* NOUVEAU_EXA_PIXMAPS */
2508         unsigned long rotate_pitch;
2509         PixmapPtr rotate_pixmap;
2510 #if NOUVEAU_EXA_PIXMAPS
2511         struct nouveau_pixmap *nvpix;
2512 #endif /* NOUVEAU_EXA_PIXMAPS */
2513
2514         if (!data)
2515                 data = crtc->funcs->shadow_allocate (crtc, width, height);
2516
2517         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2518
2519 #if NOUVEAU_EXA_PIXMAPS
2520         /* Create a dummy pixmap, to get a private that will be accepted by the system.*/
2521         rotate_pixmap = pScreen->CreatePixmap(pScreen,
2522                                                                 0, /* width */
2523                                                                 0, /* height */
2524         #ifdef CREATE_PIXMAP_USAGE_SCRATCH /* there seems to have been no api bump */
2525                                                                 pScrn->depth,
2526                                                                 0);
2527         #else
2528                                                                 pScrn->depth);
2529         #endif /* CREATE_PIXMAP_USAGE_SCRATCH */
2530 #else
2531         rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen,
2532                                                                 width, height,
2533                                                                 pScrn->depth,
2534                                                                 pScrn->bitsPerPixel,
2535                                                                 rotate_pitch,
2536                                                                 data);
2537 #endif /* NOUVEAU_EXA_PIXMAPS */
2538
2539         if (rotate_pixmap == NULL) {
2540                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2541                         "Couldn't allocate shadow pixmap for rotated CRTC\n");
2542         }
2543
2544 #if NOUVEAU_EXA_PIXMAPS
2545         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2546         if (!nvpix) {
2547                 ErrorF("No shadow private, stage 1\n");
2548         } else {
2549                 nvpix->bo = nv_crtc->shadow;
2550                 nvpix->mapped = TRUE;
2551         }
2552
2553         /* Modify the pixmap to actually be the one we need. */
2554         pScreen->ModifyPixmapHeader(rotate_pixmap,
2555                                         width,
2556                                         height,
2557                                         pScrn->depth,
2558                                         pScrn->bitsPerPixel,
2559                                         rotate_pitch,
2560                                         data);
2561
2562         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2563         if (!nvpix || !nvpix->bo)
2564                 ErrorF("No shadow private, stage 2\n");
2565 #endif /* NOUVEAU_EXA_PIXMAPS */
2566
2567         return rotate_pixmap;
2568 }
2569
2570 static void
2571 nv_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
2572 {
2573         ErrorF("nv_crtc_shadow_destroy is called\n");
2574         ScrnInfoPtr pScrn = crtc->scrn;
2575         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2576         ScreenPtr pScreen = pScrn->pScreen;
2577
2578         if (rotate_pixmap) { /* This should also unmap the buffer object if relevant. */
2579                 pScreen->DestroyPixmap(rotate_pixmap);
2580         }
2581
2582 #if !NOUVEAU_EXA_PIXMAPS
2583         if (data && nv_crtc->shadow) {
2584                 exaOffscreenFree(pScreen, nv_crtc->shadow);
2585         }
2586 #endif /* !NOUVEAU_EXA_PIXMAPS */
2587
2588         nv_crtc->shadow = NULL;
2589 }
2590
2591 /* NV04-NV10 doesn't support alpha cursors */
2592 static const xf86CrtcFuncsRec nv_crtc_funcs = {
2593         .dpms = nv_crtc_dpms,
2594         .save = nv_crtc_save, /* XXX */
2595         .restore = nv_crtc_restore, /* XXX */
2596         .mode_fixup = nv_crtc_mode_fixup,
2597         .mode_set = nv_crtc_mode_set,
2598         .prepare = nv_crtc_prepare,
2599         .commit = nv_crtc_commit,
2600         .destroy = NULL, /* XXX */
2601         .lock = nv_crtc_lock,
2602         .unlock = nv_crtc_unlock,
2603         .set_cursor_colors = nv_crtc_set_cursor_colors,
2604         .set_cursor_position = nv_crtc_set_cursor_position,
2605         .show_cursor = nv_crtc_show_cursor,
2606         .hide_cursor = nv_crtc_hide_cursor,
2607         .load_cursor_image = nv_crtc_load_cursor_image,
2608         .gamma_set = nv_crtc_gamma_set,
2609         .shadow_create = nv_crtc_shadow_create,
2610         .shadow_allocate = nv_crtc_shadow_allocate,
2611         .shadow_destroy = nv_crtc_shadow_destroy,
2612 };
2613
2614 /* NV11 and up has support for alpha cursors. */
2615 /* Due to different maximum sizes we cannot allow it to use normal cursors */
2616 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
2617         .dpms = nv_crtc_dpms,
2618         .save = nv_crtc_save, /* XXX */
2619         .restore = nv_crtc_restore, /* XXX */
2620         .mode_fixup = nv_crtc_mode_fixup,
2621         .mode_set = nv_crtc_mode_set,
2622         .prepare = nv_crtc_prepare,
2623         .commit = nv_crtc_commit,
2624         .destroy = NULL, /* XXX */
2625         .lock = nv_crtc_lock,
2626         .unlock = nv_crtc_unlock,
2627         .set_cursor_colors = NULL, /* Alpha cursors do not need this */
2628         .set_cursor_position = nv_crtc_set_cursor_position,
2629         .show_cursor = nv_crtc_show_cursor,
2630         .hide_cursor = nv_crtc_hide_cursor,
2631         .load_cursor_argb = nv_crtc_load_cursor_argb,
2632         .gamma_set = nv_crtc_gamma_set,
2633         .shadow_create = nv_crtc_shadow_create,
2634         .shadow_allocate = nv_crtc_shadow_allocate,
2635         .shadow_destroy = nv_crtc_shadow_destroy,
2636 };
2637
2638
2639 void
2640 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
2641 {
2642         NVPtr pNv = NVPTR(pScrn);
2643         xf86CrtcPtr crtc;
2644         NVCrtcPrivatePtr nv_crtc;
2645
2646         if (pNv->NVArch >= 0x11) {
2647                 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
2648         } else {
2649                 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
2650         }
2651         if (crtc == NULL)
2652                 return;
2653
2654         nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
2655         nv_crtc->head = crtc_num;
2656         nv_crtc->last_dpms = NV_DPMS_CLEARED;
2657         pNv->fp_regs_owner[nv_crtc->head] = nv_crtc->head;
2658
2659         crtc->driver_private = nv_crtc;
2660
2661         NVCrtcLockUnlock(crtc, FALSE);
2662 }
2663
2664 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2665 {
2666         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2667         int i;
2668         NVCrtcRegPtr regp;
2669
2670         regp = &state->crtc_reg[nv_crtc->head];
2671
2672         NVWriteMiscOut(crtc, regp->MiscOutReg);
2673
2674         for (i = 1; i < 5; i++)
2675                 NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
2676
2677         /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
2678         NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
2679
2680         for (i = 0; i < 25; i++)
2681                 NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
2682
2683         for (i = 0; i < 9; i++)
2684                 NVWriteVgaGr(crtc, i, regp->Graphics[i]);
2685
2686         NVEnablePalette(crtc);
2687         for (i = 0; i < 21; i++)
2688                 NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
2689
2690         NVDisablePalette(crtc);
2691 }
2692
2693 static void nv_crtc_fix_nv40_hw_cursor(xf86CrtcPtr crtc)
2694 {
2695         /* TODO - implement this properly */
2696         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2697         ScrnInfoPtr pScrn = crtc->scrn;
2698         NVPtr pNv = NVPTR(pScrn);
2699
2700         if (pNv->Architecture == NV_ARCH_40) {  /* HW bug */
2701                 volatile uint32_t curpos = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_CURSOR_POS);
2702                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_CURSOR_POS, curpos);
2703         }
2704 }
2705 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override)
2706 {
2707         ScrnInfoPtr pScrn = crtc->scrn;
2708         NVPtr pNv = NVPTR(pScrn);
2709         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2710         NVCrtcRegPtr regp;
2711         int i;
2712
2713         regp = &state->crtc_reg[nv_crtc->head];
2714
2715         if (pNv->Architecture >= NV_ARCH_10) {
2716                 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
2717                 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
2718                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
2719                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
2720                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2721                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2722                 nvWriteMC(pNv, 0x1588, 0);
2723
2724                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
2725                 NVCrtcWriteCRTC(crtc, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
2726                 NVCrtcWriteCRTC(crtc, NV_CRTC_0830, regp->unk830);
2727                 NVCrtcWriteCRTC(crtc, NV_CRTC_0834, regp->unk834);
2728                 if (pNv->Architecture == NV_ARCH_40) {
2729                         NVCrtcWriteCRTC(crtc, NV_CRTC_0850, regp->unk850);
2730                         NVCrtcWriteCRTC(crtc, NV_CRTC_081C, regp->unk81c);
2731                 }
2732
2733                 if (pNv->Architecture == NV_ARCH_40) {
2734                         uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
2735                         if (regp->config == 0x2) { /* enhanced "horizontal only" non-vga mode */
2736                                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 | 0x10000);
2737                         } else {
2738                                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
2739                         }
2740                 }
2741         }
2742
2743         NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, regp->config);
2744         NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO, regp->gpio);
2745
2746         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
2747         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
2748         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
2749         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
2750         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
2751         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
2752         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
2753         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
2754         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
2755         if (pNv->Architecture >= NV_ARCH_30)
2756                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
2757
2758         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
2759         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
2760         nv_crtc_fix_nv40_hw_cursor(crtc);
2761         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
2762         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
2763
2764         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
2765         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
2766         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3C, regp->CRTC[NV_VGA_CRTCX_3C]);
2767         if (pNv->Architecture >= NV_ARCH_10) {
2768                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
2769                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_43, regp->CRTC[NV_VGA_CRTCX_43]);
2770                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
2771                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_4B, regp->CRTC[NV_VGA_CRTCX_4B]);
2772                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
2773         }
2774         /* NV11 and NV20 stop at 0x52. */
2775         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
2776                 if (override)
2777                         for (i = 0; i < 0x10; i++)
2778                                 NVWriteVGACR5758(pNv, nv_crtc->head, i, regp->CR58[i]);
2779
2780                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
2781                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
2782
2783                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
2784
2785                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_85, regp->CRTC[NV_VGA_CRTCX_85]);
2786                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_86, regp->CRTC[NV_VGA_CRTCX_86]);
2787         }
2788
2789         /* Setting 1 on this value gives you interrupts for every vblank period. */
2790         NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_EN_0, 0);
2791         NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
2792
2793         pNv->CurrentState = state;
2794 }
2795
2796 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2797 {
2798         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2799         int i;
2800         NVCrtcRegPtr regp;
2801
2802         regp = &state->crtc_reg[nv_crtc->head];
2803
2804         regp->MiscOutReg = NVReadMiscOut(crtc);
2805
2806         for (i = 0; i < 25; i++)
2807                 regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
2808
2809         NVEnablePalette(crtc);
2810         for (i = 0; i < 21; i++)
2811                 regp->Attribute[i] = NVReadVgaAttr(crtc, i);
2812         NVDisablePalette(crtc);
2813
2814         for (i = 0; i < 9; i++)
2815                 regp->Graphics[i] = NVReadVgaGr(crtc, i);
2816
2817         for (i = 1; i < 5; i++)
2818                 regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
2819 }
2820
2821 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2822 {
2823         ScrnInfoPtr pScrn = crtc->scrn;
2824         NVPtr pNv = NVPTR(pScrn);
2825         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2826         NVCrtcRegPtr regp;
2827         int i;
2828
2829         regp = &state->crtc_reg[nv_crtc->head];
2830
2831         regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
2832         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
2833         regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
2834         regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
2835         regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
2836         regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
2837         regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
2838
2839         regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
2840         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
2841         regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
2842         if (pNv->Architecture >= NV_ARCH_30)
2843                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
2844         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
2845         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
2846         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
2847         regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
2848
2849         if (pNv->Architecture >= NV_ARCH_10) {
2850                 regp->unk830 = NVCrtcReadCRTC(crtc, NV_CRTC_0830);
2851                 regp->unk834 = NVCrtcReadCRTC(crtc, NV_CRTC_0834);
2852                 if (pNv->Architecture == NV_ARCH_40) {
2853                         regp->unk850 = NVCrtcReadCRTC(crtc, NV_CRTC_0850);
2854                         regp->unk81c = NVCrtcReadCRTC(crtc, NV_CRTC_081C);
2855                 }
2856                 if (pNv->twoHeads) {
2857                         regp->head = NVCrtcReadCRTC(crtc, NV_CRTC_FSEL);
2858                         regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
2859                 }
2860                 regp->cursorConfig = NVCrtcReadCRTC(crtc, NV_CRTC_CURSOR_CONFIG);
2861         }
2862
2863         regp->gpio = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO);
2864         regp->config = NVCrtcReadCRTC(crtc, NV_CRTC_CONFIG);
2865
2866         regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
2867         regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
2868         regp->CRTC[NV_VGA_CRTCX_3C] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3C);
2869         if (pNv->Architecture >= NV_ARCH_10) {
2870                 regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
2871                 regp->CRTC[NV_VGA_CRTCX_43] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_43);
2872                 regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
2873                 regp->CRTC[NV_VGA_CRTCX_4B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_4B);
2874                 regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
2875         }
2876         /* NV11 and NV20 don't have this, they stop at 0x52. */
2877         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
2878                 for (i = 0; i < 0x10; i++)
2879                         regp->CR58[i] = NVReadVGACR5758(pNv, nv_crtc->head, i);
2880
2881                 regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
2882                 regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
2883                 regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
2884
2885                 regp->CRTC[NV_VGA_CRTCX_85] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_85);
2886                 regp->CRTC[NV_VGA_CRTCX_86] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_86);
2887         }
2888 }
2889
2890 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2891 {
2892         ScrnInfoPtr pScrn = crtc->scrn;
2893         NVPtr pNv = NVPTR(pScrn);
2894         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2895         NVCrtcRegPtr regp;
2896         int i;
2897
2898         regp = &state->crtc_reg[nv_crtc->head];
2899
2900         regp->general = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL);
2901
2902         regp->fp_control[0]     = NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL);
2903         regp->debug_0[0]        = NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
2904
2905         if (pNv->twoHeads) {
2906                 regp->fp_control[1]     = NVReadRAMDAC(pNv, 1, NV_RAMDAC_FP_CONTROL);
2907                 regp->debug_0[1]        = NVReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
2908
2909                 regp->debug_1   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1);
2910                 regp->debug_2   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2);
2911
2912                 regp->unk_a20 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A20);
2913                 regp->unk_a24 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A24);
2914                 regp->unk_a34 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A34);
2915         }
2916
2917         if (pNv->NVArch == 0x11) {
2918                 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_DITHER_NV11);
2919         } else if (pNv->twoHeads) {
2920                 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DITHER);
2921         }
2922         if (pNv->Architecture >= NV_ARCH_10)
2923                 regp->nv10_cursync = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC);
2924
2925         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2926
2927         for (i = 0; i < 7; i++) {
2928                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2929                 regp->fp_horiz_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
2930         }
2931
2932         for (i = 0; i < 7; i++) {
2933                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2934                 regp->fp_vert_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
2935         }
2936
2937         regp->fp_hvalid_start = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_HVALID_START);
2938         regp->fp_hvalid_end = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_HVALID_END);
2939         regp->fp_vvalid_start = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_VVALID_START);
2940         regp->fp_vvalid_end = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_VVALID_END);
2941 }
2942
2943 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2944 {
2945         ScrnInfoPtr pScrn = crtc->scrn;
2946         NVPtr pNv = NVPTR(pScrn);
2947         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2948         NVCrtcRegPtr regp;
2949         int i;
2950
2951         regp = &state->crtc_reg[nv_crtc->head];
2952
2953         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL, regp->general);
2954
2955         if (pNv->fp_regs_owner[0] == nv_crtc->head) {
2956                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL, regp->fp_control[0]);
2957                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0, regp->debug_0[0]);
2958         }
2959         if (pNv->twoHeads) {
2960                 if (pNv->fp_regs_owner[1] == nv_crtc->head) {
2961                         NVWriteRAMDAC(pNv, 1, NV_RAMDAC_FP_CONTROL, regp->fp_control[1]);
2962                         NVWriteRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0, regp->debug_0[1]);
2963                 }
2964                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
2965                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
2966                 if (pNv->NVArch == 0x30) { /* For unknown purposes. */
2967                         uint32_t reg890 = NVCrtcReadRAMDAC(crtc, NV30_RAMDAC_890);
2968                         NVCrtcWriteRAMDAC(crtc, NV30_RAMDAC_89C, reg890);
2969                 }
2970
2971                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A20, regp->unk_a20);
2972                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A24, regp->unk_a24);
2973                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A34, regp->unk_a34);
2974         }
2975
2976         if (pNv->NVArch == 0x11) {
2977                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_DITHER_NV11, regp->dither);
2978         } else if (pNv->twoHeads) {
2979                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DITHER, regp->dither);
2980         }
2981         if (pNv->Architecture >= NV_ARCH_10)
2982                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
2983
2984         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2985
2986         for (i = 0; i < 7; i++) {
2987                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2988                 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_horiz_regs[i]);
2989         }
2990
2991         for (i = 0; i < 7; i++) {
2992                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2993                 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_vert_regs[i]);
2994         }
2995
2996         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_HVALID_START, regp->fp_hvalid_start);
2997         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_HVALID_END, regp->fp_hvalid_end);
2998         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_VVALID_START, regp->fp_vvalid_start);
2999         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_VVALID_END, regp->fp_vvalid_end);
3000 }
3001
3002 void
3003 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y, Bool bios_restore)
3004 {
3005         ScrnInfoPtr pScrn = crtc->scrn;
3006         NVPtr pNv = NVPTR(pScrn);
3007         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3008         NVFBLayout *pLayout = &pNv->CurrentLayout;
3009         uint32_t start = 0;
3010
3011         ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
3012
3013         if (bios_restore) {
3014                 start = pNv->console_mode[nv_crtc->head].fb_start;
3015         } else {
3016                 start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
3017                 if (crtc->rotatedData != NULL) { /* we do not exist on the real framebuffer */
3018 #if NOUVEAU_EXA_PIXMAPS
3019                         start = nv_crtc->shadow->offset;
3020 #else
3021                         start = pNv->FB->offset + nv_crtc->shadow->offset; /* We do exist relative to the framebuffer */
3022 #endif
3023                 } else {
3024                         start += pNv->FB->offset;
3025                 }
3026         }
3027
3028         /* 30 bits addresses in 32 bits according to haiku */
3029         NVCrtcWriteCRTC(crtc, NV_CRTC_START, start & 0xfffffffc);
3030
3031         /* set NV4/NV10 byte adress: (bit0 - 1) */
3032         NVWriteVgaAttr(crtc, 0x13, (start & 0x3) << 1);
3033
3034         crtc->x = x;
3035         crtc->y = y;
3036 }
3037
3038 static void NVCrtcWriteDacMask(xf86CrtcPtr crtc, uint8_t value)
3039 {
3040         ScrnInfoPtr pScrn = crtc->scrn;
3041         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3042         NVPtr pNv = NVPTR(pScrn);
3043         volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3044
3045         DDXMMIOH("NVCrtcWriteDacMask: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_MASK, value);
3046         NV_WR08(pDACReg, VGA_DAC_MASK, value);
3047 }
3048
3049 static uint8_t NVCrtcReadDacMask(xf86CrtcPtr crtc)
3050 {
3051         ScrnInfoPtr pScrn = crtc->scrn;
3052         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3053         NVPtr pNv = NVPTR(pScrn);
3054         volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3055
3056         DDXMMIOH("NVCrtcReadDacMask: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_MASK, NV_RD08(pDACReg, VGA_DAC_MASK));
3057         return NV_RD08(pDACReg, VGA_DAC_MASK);
3058 }
3059
3060 static void NVCrtcWriteDacReadAddr(xf86CrtcPtr crtc, uint8_t value)
3061 {
3062         ScrnInfoPtr pScrn = crtc->scrn;
3063         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3064         NVPtr pNv = NVPTR(pScrn);
3065         volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3066
3067         DDXMMIOH("NVCrtcWriteDacReadAddr: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_READ_ADDR, value);
3068         NV_WR08(pDACReg, VGA_DAC_READ_ADDR, value);
3069 }
3070
3071 static void NVCrtcWriteDacWriteAddr(xf86CrtcPtr crtc, uint8_t value)
3072 {
3073         ScrnInfoPtr pScrn = crtc->scrn;
3074         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3075         NVPtr pNv = NVPTR(pScrn);
3076         volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3077
3078         DDXMMIOH("NVCrtcWriteDacWriteAddr: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_WRITE_ADDR, value);
3079         NV_WR08(pDACReg, VGA_DAC_WRITE_ADDR, value);
3080 }
3081
3082 static void NVCrtcWriteDacData(xf86CrtcPtr crtc, uint8_t value)
3083 {
3084         ScrnInfoPtr pScrn = crtc->scrn;
3085         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3086         NVPtr pNv = NVPTR(pScrn);
3087         volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3088
3089         DDXMMIOH("NVCrtcWriteDacData: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_DATA, value);
3090         NV_WR08(pDACReg, VGA_DAC_DATA, value);
3091 }
3092
3093 static uint8_t NVCrtcReadDacData(xf86CrtcPtr crtc, uint8_t value)
3094 {
3095         ScrnInfoPtr pScrn = crtc->scrn;
3096         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3097         NVPtr pNv = NVPTR(pScrn);
3098         volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3099
3100         DDXMMIOH("NVCrtcReadDacData: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_DATA, NV_RD08(pDACReg, VGA_DAC_DATA));
3101         return NV_RD08(pDACReg, VGA_DAC_DATA);
3102 }
3103
3104 void NVCrtcLoadPalette(xf86CrtcPtr crtc)
3105 {
3106         int i;
3107         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3108         NVCrtcRegPtr regp;
3109         ScrnInfoPtr pScrn = crtc->scrn;
3110         NVPtr pNv = NVPTR(pScrn);
3111
3112         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
3113
3114         if (pNv->twoHeads)
3115                 NVCrtcSetOwner(crtc);
3116         NVCrtcWriteDacMask(crtc, 0xff);
3117         NVCrtcWriteDacWriteAddr(crtc, 0x00);
3118
3119         for (i = 0; i<768; i++) {
3120                 NVCrtcWriteDacData(crtc, regp->DAC[i]);
3121         }
3122         NVDisablePalette(crtc);
3123 }
3124
3125 /* on = unblank */
3126 void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
3127 {
3128         NVPtr pNv = NVPTR(crtc->scrn);
3129         unsigned char scrn;
3130
3131         if (pNv->twoHeads)
3132                 NVCrtcSetOwner(crtc);
3133
3134         scrn = NVReadVgaSeq(crtc, 0x01);
3135         if (on) {
3136                 scrn &= ~0x20;
3137         } else {
3138                 scrn |= 0x20;
3139         }
3140
3141         NVVgaSeqReset(crtc, TRUE);
3142         NVWriteVgaSeq(crtc, 0x01, scrn);
3143         NVVgaSeqReset(crtc, FALSE);
3144 }
3145
3146 /* Reset a mode after a drastic output resource change for example. */
3147 void NVCrtcModeFix(xf86CrtcPtr crtc)
3148 {
3149         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3150         Bool need_unlock;
3151
3152         if (!crtc->enabled)
3153                 return;
3154
3155         if (!xf86ModesEqual(&crtc->mode, &crtc->desiredMode)) /* not currently in X */
3156                 return;
3157
3158         DisplayModePtr adjusted_mode = xf86DuplicateMode(&crtc->mode);
3159         uint8_t dpms_mode = nv_crtc->last_dpms;
3160
3161         /* Set the crtc mode again. */
3162         crtc->funcs->dpms(crtc, DPMSModeOff);
3163         need_unlock = crtc->funcs->lock(crtc);
3164         crtc->funcs->mode_fixup(crtc, &crtc->mode, adjusted_mode);
3165         crtc->funcs->prepare(crtc);
3166         crtc->funcs->mode_set(crtc, &crtc->mode, adjusted_mode, crtc->x, crtc->y);
3167         crtc->funcs->commit(crtc);
3168         if (need_unlock)
3169                 crtc->funcs->unlock(crtc);
3170         crtc->funcs->dpms(crtc, dpms_mode);
3171
3172         /* Free mode. */
3173         xfree(adjusted_mode);
3174 }
3175
3176 /*************************************************************************** \
3177 |*                                                                           *|
3178 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
3179 |*                                                                           *|
3180 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
3181 |*     international laws.  Users and possessors of this source code are     *|
3182 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
3183 |*     use this code in individual and commercial software.                  *|
3184 |*                                                                           *|
3185 |*     Any use of this source code must include,  in the user documenta-     *|
3186 |*     tion and  internal comments to the code,  notices to the end user     *|
3187 |*     as follows:                                                           *|
3188 |*                                                                           *|
3189 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
3190 |*                                                                           *|
3191 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
3192 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
3193 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
3194 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
3195 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
3196 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
3197 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
3198 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
3199 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
3200 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
3201 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
3202 |*                                                                           *|
3203 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
3204 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
3205 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
3206 |*     computer  software  documentation,"  as such  terms  are  used in     *|
3207 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
3208 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
3209 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
3210 |*     all U.S. Government End Users  acquire the source code  with only     *|
3211 |*     those rights set forth herein.                                        *|
3212 |*                                                                           *|
3213  \***************************************************************************/