2 * Copyright 2007 Ben Skeggs
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include "nv_include.h"
24 #include "nv_shaders.h"
26 typedef struct nv_pict_surface_format {
29 } nv_pict_surface_format_t;
31 typedef struct nv_pict_texture_format {
35 } nv_pict_texture_format_t;
37 typedef struct nv_pict_op {
44 typedef struct nv40_exa_state {
48 PictTransformPtr transform;
53 static nv40_exa_state_t exa_state;
54 #define NV40EXA_STATE nv40_exa_state_t *state = &exa_state
56 static nv_pict_surface_format_t
57 NV40SurfaceFormat[] = {
58 { PICT_a8r8g8b8 , NV40TCL_RT_FORMAT_COLOR_A8R8G8B8 },
59 { PICT_x8r8g8b8 , NV40TCL_RT_FORMAT_COLOR_X8R8G8B8 },
60 { PICT_r5g6b5 , NV40TCL_RT_FORMAT_COLOR_R5G6B5 },
61 { PICT_a8 , NV40TCL_RT_FORMAT_COLOR_B8 },
65 static nv_pict_surface_format_t *
66 NV40_GetPictSurfaceFormat(int format)
70 while (NV40SurfaceFormat[i].pict_fmt != -1) {
71 if (NV40SurfaceFormat[i].pict_fmt == format)
72 return &NV40SurfaceFormat[i];
80 NV40EXA_FPID_PASS_COL0 = 0,
81 NV40EXA_FPID_PASS_TEX0 = 1,
82 NV40EXA_FPID_COMPOSITE_MASK = 2,
83 NV40EXA_FPID_COMPOSITE_MASK_SA_CA = 3,
84 NV40EXA_FPID_COMPOSITE_MASK_CA = 4,
88 static nv_shader_t *nv40_fp_map[NV40EXA_FPID_MAX] = {
91 &nv30_fp_composite_mask,
92 &nv30_fp_composite_mask_sa_ca,
93 &nv30_fp_composite_mask_ca
96 static nv_shader_t *nv40_fp_map_a8[NV40EXA_FPID_MAX];
99 NV40EXAHackupA8Shaders(ScrnInfoPtr pScrn)
103 for (s = 0; s < NV40EXA_FPID_MAX; s++) {
104 nv_shader_t *def, *a8;
106 def = nv40_fp_map[s];
107 a8 = xcalloc(1, sizeof(nv_shader_t));
108 a8->card_priv.NV30FP.num_regs = def->card_priv.NV30FP.num_regs;
109 a8->size = def->size + 4;
110 memcpy(a8->data, def->data, def->size * sizeof(uint32_t));
111 nv40_fp_map_a8[s] = a8;
113 a8->data[a8->size - 8 + 0] &= ~0x00000081;
114 a8->data[a8->size - 4 + 0] = 0x01401e81;
115 a8->data[a8->size - 4 + 1] = 0x1c9dfe00;
116 a8->data[a8->size - 4 + 2] = 0x0001c800;
117 a8->data[a8->size - 4 + 3] = 0x0001c800;
121 #define _(r,tf,ts0x,ts0y,ts0z,ts0w,ts1x,ts1y,ts1z,ts1w) \
123 PICT_##r, NV40TCL_TEX_FORMAT_FORMAT_##tf, \
124 NV40TCL_TEX_SWIZZLE_S0_X_##ts0x | NV40TCL_TEX_SWIZZLE_S0_Y_##ts0y | \
125 NV40TCL_TEX_SWIZZLE_S0_Z_##ts0z | NV40TCL_TEX_SWIZZLE_S0_W_##ts0w | \
126 NV40TCL_TEX_SWIZZLE_S1_X_##ts1x | NV40TCL_TEX_SWIZZLE_S1_Y_##ts1y | \
127 NV40TCL_TEX_SWIZZLE_S1_Z_##ts1z | NV40TCL_TEX_SWIZZLE_S1_W_##ts1w, \
129 static nv_pict_texture_format_t
130 NV40TextureFormat[] = {
131 _(a8r8g8b8, A8R8G8B8, S1, S1, S1, S1, X, Y, Z, W),
132 _(x8r8g8b8, A8R8G8B8, S1, S1, S1, ONE, X, Y, Z, W),
133 _(x8b8g8r8, A8R8G8B8, S1, S1, S1, ONE, Z, Y, X, W),
134 _(a1r5g5b5, A1R5G5B5, S1, S1, S1, S1, X, Y, Z, W),
135 _(x1r5g5b5, A1R5G5B5, S1, S1, S1, ONE, X, Y, Z, W),
136 _( r5g6b5, R5G6B5, S1, S1, S1, S1, X, Y, Z, W),
137 _( a8, L8, ZERO, ZERO, ZERO, S1, X, X, X, X),
142 static nv_pict_texture_format_t *
143 NV40_GetPictTextureFormat(int format)
147 while (NV40TextureFormat[i].pict_fmt != -1) {
148 if (NV40TextureFormat[i].pict_fmt == format)
149 return &NV40TextureFormat[i];
156 #define SF(bf) (NV40TCL_BLEND_FUNC_SRC_RGB_##bf | \
157 NV40TCL_BLEND_FUNC_SRC_ALPHA_##bf)
158 #define DF(bf) (NV40TCL_BLEND_FUNC_DST_RGB_##bf | \
159 NV40TCL_BLEND_FUNC_DST_ALPHA_##bf)
162 /* Clear */ { 0, 0, SF( ZERO), DF( ZERO) },
163 /* Src */ { 0, 0, SF( ONE), DF( ZERO) },
164 /* Dst */ { 0, 0, SF( ZERO), DF( ONE) },
165 /* Over */ { 1, 0, SF( ONE), DF(ONE_MINUS_SRC_ALPHA) },
166 /* OverReverse */ { 0, 1, SF(ONE_MINUS_DST_ALPHA), DF( ONE) },
167 /* In */ { 0, 1, SF( DST_ALPHA), DF( ZERO) },
168 /* InReverse */ { 1, 0, SF( ZERO), DF( SRC_ALPHA) },
169 /* Out */ { 0, 1, SF(ONE_MINUS_DST_ALPHA), DF( ZERO) },
170 /* OutReverse */ { 1, 0, SF( ZERO), DF(ONE_MINUS_SRC_ALPHA) },
171 /* Atop */ { 1, 1, SF( DST_ALPHA), DF(ONE_MINUS_SRC_ALPHA) },
172 /* AtopReverse */ { 1, 1, SF(ONE_MINUS_DST_ALPHA), DF( SRC_ALPHA) },
173 /* Xor */ { 1, 1, SF(ONE_MINUS_DST_ALPHA), DF(ONE_MINUS_SRC_ALPHA) },
174 /* Add */ { 0, 0, SF( ONE), DF( ONE) }
177 static nv_pict_op_t *
178 NV40_GetPictOpRec(int op)
180 if (op >= PictOpSaturate)
182 return &NV40PictOp[op];
186 #define FALLBACK(fmt,args...) do { \
187 ErrorF("FALLBACK %s:%d> " fmt, __func__, __LINE__, ##args); \
191 #define FALLBACK(fmt,args...) do { \
197 NV40_SetupBlend(ScrnInfoPtr pScrn, nv_pict_op_t *blend,
198 PictFormatShort dest_format, Bool component_alpha)
200 NVPtr pNv = NVPTR(pScrn);
201 uint32_t sblend, dblend;
203 sblend = blend->src_card_op;
204 dblend = blend->dst_card_op;
206 if (blend->dst_alpha) {
207 if (!PICT_FORMAT_A(dest_format)) {
208 if (sblend == SF(DST_ALPHA)) {
210 } else if (sblend == SF(ONE_MINUS_DST_ALPHA)) {
213 } else if (dest_format == PICT_a8) {
214 if (sblend == SF(DST_ALPHA)) {
215 sblend = SF(DST_COLOR);
216 } else if (sblend == SF(ONE_MINUS_DST_ALPHA)) {
217 sblend = SF(ONE_MINUS_DST_COLOR);
222 if (blend->src_alpha && (component_alpha || dest_format == PICT_a8)) {
223 if (dblend == DF(SRC_ALPHA)) {
224 dblend = DF(SRC_COLOR);
225 } else if (dblend == DF(ONE_MINUS_SRC_ALPHA)) {
226 dblend = DF(ONE_MINUS_SRC_COLOR);
230 if (sblend == SF(ONE) && dblend == DF(ZERO)) {
231 BEGIN_RING(Nv3D, NV40TCL_BLEND_ENABLE, 1);
234 BEGIN_RING(Nv3D, NV40TCL_BLEND_ENABLE, 5);
238 OUT_RING (0x00000000);
239 OUT_RING (NV40TCL_BLEND_EQUATION_ALPHA_FUNC_ADD |
240 NV40TCL_BLEND_EQUATION_RGB_FUNC_ADD);
245 NV40EXATexture(ScrnInfoPtr pScrn, PixmapPtr pPix, PicturePtr pPict, int unit)
247 NVPtr pNv = NVPTR(pScrn);
248 nv_pict_texture_format_t *fmt;
251 fmt = NV40_GetPictTextureFormat(pPict->format);
255 BEGIN_RING(Nv3D, NV40TCL_TEX_OFFSET(unit), 8);
256 OUT_PIXMAPl(pPix, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD);
257 OUT_PIXMAPd(pPix, fmt->card_fmt | NV40TCL_TEX_FORMAT_LINEAR |
258 NV40TCL_TEX_FORMAT_DIMS_2D | NV40TCL_TEX_FORMAT_NO_BORDER |
259 (0x8000) | (1 << NV40TCL_TEX_FORMAT_MIPMAP_COUNT_SHIFT),
260 NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD,
261 NV40TCL_TEX_FORMAT_DMA0, NV40TCL_TEX_FORMAT_DMA1);
263 switch(pPict->repeatType) {
264 /* At the moment i do not know if we can support RepeatPad. */
266 OUT_RING (NV40TCL_TEX_WRAP_S_MIRRORED_REPEAT |
267 NV40TCL_TEX_WRAP_T_MIRRORED_REPEAT |
268 NV40TCL_TEX_WRAP_R_MIRRORED_REPEAT);
272 OUT_RING (NV40TCL_TEX_WRAP_S_REPEAT |
273 NV40TCL_TEX_WRAP_T_REPEAT |
274 NV40TCL_TEX_WRAP_R_REPEAT);
278 OUT_RING (NV40TCL_TEX_WRAP_S_CLAMP_TO_BORDER |
279 NV40TCL_TEX_WRAP_T_CLAMP_TO_BORDER |
280 NV40TCL_TEX_WRAP_R_CLAMP_TO_BORDER);
282 OUT_RING (NV40TCL_TEX_ENABLE_ENABLE);
283 OUT_RING (fmt->card_swz);
284 if (pPict->filter == PictFilterBilinear) {
285 OUT_RING (NV40TCL_TEX_FILTER_MIN_LINEAR |
286 NV40TCL_TEX_FILTER_MAG_LINEAR |
289 OUT_RING (NV40TCL_TEX_FILTER_MIN_NEAREST |
290 NV40TCL_TEX_FILTER_MAG_NEAREST |
293 OUT_RING ((pPix->drawable.width << 16) | pPix->drawable.height);
294 OUT_RING (0); /* border ARGB */
295 BEGIN_RING(Nv3D, NV40TCL_TEX_SIZE1(unit), 1);
296 OUT_RING ((1 << NV40TCL_TEX_SIZE1_DEPTH_SHIFT) |
297 (uint32_t)exaGetPixmapPitch(pPix));
299 state->unit[unit].width = (float)pPix->drawable.width;
300 state->unit[unit].height = (float)pPix->drawable.height;
301 state->unit[unit].transform = pPict->transform;
307 NV40_SetupSurface(ScrnInfoPtr pScrn, PixmapPtr pPix, PictFormatShort format)
309 NVPtr pNv = NVPTR(pScrn);
310 nv_pict_surface_format_t *fmt;
312 fmt = NV40_GetPictSurfaceFormat(format);
314 ErrorF("AIII no format\n");
318 BEGIN_RING(Nv3D, NV40TCL_RT_FORMAT, 3);
319 OUT_RING (NV40TCL_RT_FORMAT_TYPE_LINEAR |
320 NV40TCL_RT_FORMAT_ZETA_Z24S8 |
322 OUT_RING (exaGetPixmapPitch(pPix));
323 OUT_PIXMAPl(pPix, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
329 NV40EXACheckCompositeTexture(PicturePtr pPict)
331 nv_pict_texture_format_t *fmt;
332 int w = pPict->pDrawable->width;
333 int h = pPict->pDrawable->height;
335 if ((w > 4096) || (h > 4096))
336 FALLBACK("picture too large, %dx%d\n", w, h);
338 fmt = NV40_GetPictTextureFormat(pPict->format);
340 FALLBACK("picture format 0x%08x not supported\n",
343 if (pPict->filter != PictFilterNearest &&
344 pPict->filter != PictFilterBilinear)
345 FALLBACK("filter 0x%x not supported\n", pPict->filter);
347 if (pPict->repeat && pPict->repeatType == RepeatPad)
348 FALLBACK("repeat 0x%x not supported\n", pPict->repeatType);
354 NV40EXACheckComposite(int op, PicturePtr psPict,
358 nv_pict_surface_format_t *fmt;
361 opr = NV40_GetPictOpRec(op);
363 FALLBACK("unsupported blend op 0x%x\n", op);
365 fmt = NV40_GetPictSurfaceFormat(pdPict->format);
367 FALLBACK("dst picture format 0x%08x not supported\n",
370 if (!NV40EXACheckCompositeTexture(psPict))
371 FALLBACK("src picture\n");
373 if (pmPict->componentAlpha &&
374 PICT_FORMAT_RGB(pmPict->format) &&
375 opr->src_alpha && opr->src_card_op != SF(ZERO))
376 FALLBACK("mask CA + SA\n");
377 if (!NV40EXACheckCompositeTexture(pmPict))
378 FALLBACK("mask picture\n");
385 NV40EXAPrepareComposite(int op, PicturePtr psPict,
392 ScrnInfoPtr pScrn = xf86Screens[psPix->drawable.pScreen->myNum];
393 NVPtr pNv = NVPTR(pScrn);
395 int fpid = NV40EXA_FPID_PASS_COL0;
398 blend = NV40_GetPictOpRec(op);
400 NV40_SetupBlend(pScrn, blend, pdPict->format,
401 (pmPict && pmPict->componentAlpha &&
402 PICT_FORMAT_RGB(pmPict->format)));
404 NV40_SetupSurface(pScrn, pdPix, pdPict->format);
405 NV40EXATexture(pScrn, psPix, psPict, 0);
407 NV40_LoadVtxProg(pScrn, &nv40_vp_exa_render);
409 NV40EXATexture(pScrn, pmPix, pmPict, 1);
411 if (pmPict->componentAlpha && PICT_FORMAT_RGB(pmPict->format)) {
412 if (blend->src_alpha)
413 fpid = NV40EXA_FPID_COMPOSITE_MASK_SA_CA;
415 fpid = NV40EXA_FPID_COMPOSITE_MASK_CA;
417 fpid = NV40EXA_FPID_COMPOSITE_MASK;
420 state->have_mask = TRUE;
422 fpid = NV40EXA_FPID_PASS_TEX0;
424 state->have_mask = FALSE;
427 if (pdPict->format == PICT_a8)
428 NV40_LoadFragProg(pScrn, nv40_fp_map_a8[fpid]);
430 NV40_LoadFragProg(pScrn, nv40_fp_map[fpid]);
432 /* Appears to be some kind of cache flush, needed here at least
433 * sometimes.. funky text rendering otherwise :)
435 BEGIN_RING(Nv3D, NV40TCL_TEX_CACHE_CTL, 1);
437 BEGIN_RING(Nv3D, NV40TCL_TEX_CACHE_CTL, 1);
440 BEGIN_RING(Nv3D, NV40TCL_BEGIN_END, 1);
441 OUT_RING (NV40TCL_BEGIN_END_QUADS);
446 #define xFixedToFloat(v) \
447 ((float)xFixedToInt((v)) + ((float)xFixedFrac(v) / 65536.0))
450 NV40EXATransformCoord(PictTransformPtr t, int x, int y, float sx, float sy,
451 float *x_ret, float *y_ret)
455 v.vector[0] = IntToxFixed(x);
456 v.vector[1] = IntToxFixed(y);
457 v.vector[2] = xFixed1;
458 PictureTransformPoint(t, &v);
459 *x_ret = xFixedToFloat(v.vector[0]) / sx;
460 *y_ret = xFixedToFloat(v.vector[1]) / sy;
462 *x_ret = (float)x / sx;
463 *y_ret = (float)y / sy;
467 #define CV_OUTm(sx,sy,mx,my,dx,dy) do { \
468 BEGIN_RING(Nv3D, NV40TCL_VTX_ATTR_2F_X(8), 4); \
469 OUT_RINGf ((sx)); OUT_RINGf ((sy)); \
470 OUT_RINGf ((mx)); OUT_RINGf ((my)); \
471 BEGIN_RING(Nv3D, NV40TCL_VTX_ATTR_2I(0), 1); \
472 OUT_RING (((dy)<<16)|(dx)); \
474 #define CV_OUT(sx,sy,dx,dy) do { \
475 BEGIN_RING(Nv3D, NV40TCL_VTX_ATTR_2F_X(8), 2); \
476 OUT_RINGf ((sx)); OUT_RINGf ((sy)); \
477 BEGIN_RING(Nv3D, NV40TCL_VTX_ATTR_2I(0), 1); \
478 OUT_RING (((dy)<<16)|(dx)); \
482 NV40EXAComposite(PixmapPtr pdPix, int srcX , int srcY,
483 int maskX, int maskY,
485 int width, int height)
487 ScrnInfoPtr pScrn = xf86Screens[pdPix->drawable.pScreen->myNum];
488 NVPtr pNv = NVPTR(pScrn);
489 float sX0, sX1, sX2, sY0, sY1, sY2, sX3, sY3;
490 float mX0, mX1, mX2, mY0, mY1, mY2, mX3, mY3;
493 NV40EXATransformCoord(state->unit[0].transform, srcX, srcY,
494 state->unit[0].width,
495 state->unit[0].height, &sX0, &sY0);
496 NV40EXATransformCoord(state->unit[0].transform,
498 state->unit[0].width,
499 state->unit[0].height, &sX1, &sY1);
500 NV40EXATransformCoord(state->unit[0].transform,
501 srcX + width, srcY + height,
502 state->unit[0].width,
503 state->unit[0].height, &sX2, &sY2);
504 NV40EXATransformCoord(state->unit[0].transform,
506 state->unit[0].width,
507 state->unit[0].height, &sX3, &sY3);
509 if (state->have_mask) {
510 NV40EXATransformCoord(state->unit[1].transform, maskX, maskY,
511 state->unit[1].width,
512 state->unit[1].height, &mX0, &mY0);
513 NV40EXATransformCoord(state->unit[1].transform,
514 maskX + width, maskY,
515 state->unit[1].width,
516 state->unit[1].height, &mX1, &mY1);
517 NV40EXATransformCoord(state->unit[1].transform,
518 maskX + width, maskY + height,
519 state->unit[1].width,
520 state->unit[1].height, &mX2, &mY2);
521 NV40EXATransformCoord(state->unit[1].transform,
522 maskX, maskY + height,
523 state->unit[1].width,
524 state->unit[1].height, &mX3, &mY3);
526 CV_OUTm(sX0 , sY0 , mX0, mY0, dstX , dstY);
527 CV_OUTm(sX1 , sY1 , mX1, mY1, dstX + width, dstY);
528 CV_OUTm(sX2 , sY2 , mX2, mY2, dstX + width, dstY + height);
529 CV_OUTm(sX3 , sY3 , mX3, mY3, dstX , dstY + height);
531 CV_OUT(sX0 , sY0 , dstX , dstY);
532 CV_OUT(sX1 , sY1 , dstX + width, dstY);
533 CV_OUT(sX2 , sY2 , dstX + width, dstY + height);
534 CV_OUT(sX3 , sY3 , dstX , dstY + height);
541 NV40EXADoneComposite(PixmapPtr pdPix)
543 ScrnInfoPtr pScrn = xf86Screens[pdPix->drawable.pScreen->myNum];
544 NVPtr pNv = NVPTR(pScrn);
546 BEGIN_RING(Nv3D, NV40TCL_BEGIN_END, 1);
547 OUT_RING (NV40TCL_BEGIN_END_STOP);
550 #define NV40TCL_CHIPSET_4X_MASK 0x00000baf
551 #define NV44TCL_CHIPSET_4X_MASK 0x00005450
553 NVAccelInitNV40TCL(ScrnInfoPtr pScrn)
555 NVPtr pNv = NVPTR(pScrn);
556 uint32_t class = 0, chipset;
559 NV40EXAHackupA8Shaders(pScrn);
561 chipset = (nvReadMC(pNv, 0) >> 20) & 0xff;
562 if ((chipset & 0xf0) != NV_ARCH_40)
566 if (NV40TCL_CHIPSET_4X_MASK & (1<<chipset))
568 else if (NV44TCL_CHIPSET_4X_MASK & (1<<chipset))
571 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
572 "NV40EXA: Unknown chipset NV4%1x\n", chipset);
577 if (nouveau_grobj_alloc(pNv->chan, Nv3D, class, &pNv->Nv3D))
581 BEGIN_RING(Nv3D, NV40TCL_DMA_NOTIFY, 1);
582 OUT_RING (pNv->notify0->handle);
583 BEGIN_RING(Nv3D, NV40TCL_DMA_TEXTURE0, 2);
584 OUT_RING (pNv->chan->vram->handle);
585 OUT_RING (pNv->chan->gart->handle);
586 BEGIN_RING(Nv3D, NV40TCL_DMA_COLOR0, 2);
587 OUT_RING (pNv->chan->vram->handle);
588 OUT_RING (pNv->chan->vram->handle);
591 BEGIN_RING(Nv3D, 0x1ea4, 3);
592 OUT_RING (0x00000010);
593 OUT_RING (0x01000100);
594 OUT_RING (0xff800006);
595 BEGIN_RING(Nv3D, 0x1fc4, 1);
596 OUT_RING (0x06144321);
597 BEGIN_RING(Nv3D, 0x1fc8, 2);
598 OUT_RING (0xedcba987);
599 OUT_RING (0x00000021);
600 BEGIN_RING(Nv3D, 0x1fd0, 1);
601 OUT_RING (0x00171615);
602 BEGIN_RING(Nv3D, 0x1fd4, 1);
603 OUT_RING (0x001b1a19);
604 BEGIN_RING(Nv3D, 0x1ef8, 1);
605 OUT_RING (0x0020ffff);
606 BEGIN_RING(Nv3D, 0x1d64, 1);
607 OUT_RING (0x00d30000);
608 BEGIN_RING(Nv3D, 0x1e94, 1);
609 OUT_RING (0x00000001);
611 BEGIN_RING(Nv3D, NV40TCL_VIEWPORT_TRANSLATE_X, 8);
621 /* default 3D state */
622 /*XXX: replace with the same state that the DRI emits on startup */
623 BEGIN_RING(Nv3D, NV40TCL_STENCIL_FRONT_ENABLE, 1);
625 BEGIN_RING(Nv3D, NV40TCL_STENCIL_BACK_ENABLE, 1);
627 BEGIN_RING(Nv3D, NV40TCL_ALPHA_TEST_ENABLE, 1);
629 BEGIN_RING(Nv3D, NV40TCL_DEPTH_WRITE_ENABLE, 2);
632 BEGIN_RING(Nv3D, NV40TCL_COLOR_MASK, 1);
633 OUT_RING (0x01010101); /* TR,TR,TR,TR */
634 BEGIN_RING(Nv3D, NV40TCL_CULL_FACE_ENABLE, 1);
636 BEGIN_RING(Nv3D, NV40TCL_BLEND_ENABLE, 1);
638 BEGIN_RING(Nv3D, NV40TCL_COLOR_LOGIC_OP_ENABLE, 2);
640 OUT_RING (NV40TCL_COLOR_LOGIC_OP_COPY);
641 BEGIN_RING(Nv3D, NV40TCL_DITHER_ENABLE, 1);
643 BEGIN_RING(Nv3D, NV40TCL_SHADE_MODEL, 1);
644 OUT_RING (NV40TCL_SHADE_MODEL_SMOOTH);
645 BEGIN_RING(Nv3D, NV40TCL_POLYGON_OFFSET_FACTOR,2);
648 BEGIN_RING(Nv3D, NV40TCL_POLYGON_MODE_FRONT, 2);
649 OUT_RING (NV40TCL_POLYGON_MODE_FRONT_FILL);
650 OUT_RING (NV40TCL_POLYGON_MODE_BACK_FILL);
651 BEGIN_RING(Nv3D, NV40TCL_POLYGON_STIPPLE_PATTERN(0), 0x20);
653 OUT_RING (0xFFFFFFFF);
655 BEGIN_RING(Nv3D, NV40TCL_TEX_ENABLE(i), 1);
659 BEGIN_RING(Nv3D, 0x1d78, 1);
662 BEGIN_RING(Nv3D, NV40TCL_RT_ENABLE, 1);
663 OUT_RING (NV40TCL_RT_ENABLE_COLOR0);
665 BEGIN_RING(Nv3D, NV40TCL_RT_HORIZ, 2);
666 OUT_RING ((4096 << 16));
667 OUT_RING ((4096 << 16));
668 BEGIN_RING(Nv3D, NV40TCL_SCISSOR_HORIZ, 2);
669 OUT_RING ((4096 << 16));
670 OUT_RING ((4096 << 16));
671 BEGIN_RING(Nv3D, NV40TCL_VIEWPORT_HORIZ, 2);
672 OUT_RING ((4096 << 16));
673 OUT_RING ((4096 << 16));
674 BEGIN_RING(Nv3D, NV40TCL_VIEWPORT_CLIP_HORIZ(0), 2);
675 OUT_RING ((4095 << 16));
676 OUT_RING ((4095 << 16));