2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2008 Stuart Bennett
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 #include "nv_include.h"
28 /* FIXME: put these somewhere */
29 #define SEQ_INDEX VGA_SEQ_INDEX
30 #define NV_VGA_CRTCX_OWNER_HEADA 0x0
31 #define NV_VGA_CRTCX_OWNER_HEADB 0x3
32 #define FEATURE_MOBILE 0x10
36 static int crtchead = 0;
38 /* this will need remembering across a suspend */
39 static uint32_t saved_nv_pfb_cfg0;
46 static uint16_t le16_to_cpu(const uint16_t x)
48 #if X_BYTE_ORDER == X_BIG_ENDIAN
55 static uint32_t le32_to_cpu(const uint32_t x)
57 #if X_BYTE_ORDER == X_BIG_ENDIAN
64 static bool nv_cksum(const uint8_t *data, unsigned int length)
66 /* there's a few checksums in the BIOS, so here's a generic checking function */
70 for (i = 0; i < length; i++)
79 static int NVValidVBIOS(ScrnInfoPtr pScrn, const uint8_t *data)
81 /* check for BIOS signature */
82 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
83 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
84 "... BIOS signature not found\n");
88 if (nv_cksum(data, data[2] * 512)) {
89 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
90 "... BIOS checksum invalid\n");
91 /* probably ought to set a do_not_execute flag for table parsing here,
92 * assuming most BIOSen are valid */
95 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "... appears to be valid\n");
100 static void NVShadowVBIOS_PROM(ScrnInfoPtr pScrn, uint8_t *data)
102 NVPtr pNv = NVPTR(pScrn);
105 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
106 "Attempting to locate BIOS image in PROM\n");
108 /* enable ROM access */
109 nvWriteMC(pNv, NV_PBUS_PCI_NV_20, NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED);
110 for (i = 0; i < NV_PROM_SIZE; i++) {
111 /* according to nvclock, we need that to work around a 6600GT/6800LE bug */
112 data[i] = NV_RD08(pNv->REGS, NV_PROM_OFFSET + i);
113 data[i] = NV_RD08(pNv->REGS, NV_PROM_OFFSET + i);
114 data[i] = NV_RD08(pNv->REGS, NV_PROM_OFFSET + i);
115 data[i] = NV_RD08(pNv->REGS, NV_PROM_OFFSET + i);
116 data[i] = NV_RD08(pNv->REGS, NV_PROM_OFFSET + i);
118 /* disable ROM access */
119 nvWriteMC(pNv, NV_PBUS_PCI_NV_20, NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
122 static void NVShadowVBIOS_PRAMIN(ScrnInfoPtr pScrn, uint8_t *data)
124 NVPtr pNv = NVPTR(pScrn);
125 uint32_t old_bar0_pramin = 0;
128 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
129 "Attempting to locate BIOS image in PRAMIN\n");
131 if (pNv->Architecture >= NV_ARCH_50) {
132 uint32_t vbios_vram = (NV_RD32(pNv->REGS, 0x619f04) & ~0xff) << 8;
135 vbios_vram = (NV_RD32(pNv->REGS, 0x1700) << 16) + 0xf0000;
137 old_bar0_pramin = NV_RD32(pNv->REGS, 0x1700);
138 NV_WR32(pNv->REGS, 0x1700, vbios_vram >> 16);
141 for (i = 0; i < NV_PROM_SIZE; i++)
142 data[i] = NV_RD08(pNv->REGS, NV_PRAMIN_OFFSET + i);
144 if (pNv->Architecture >= NV_ARCH_50)
145 NV_WR32(pNv->REGS, 0x1700, old_bar0_pramin);
148 static void NVVBIOS_PCIROM(ScrnInfoPtr pScrn, uint8_t *data)
150 NVPtr pNv = NVPTR(pScrn);
152 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
153 "Attempting to use PCI ROM BIOS image\n");
155 #if XSERVER_LIBPCIACCESS
156 pci_device_read_rom(pNv->PciInfo, data);
158 xf86ReadPciBIOS(0, pNv->PciTag, 0, data, NV_PROM_SIZE);
162 static bool NVShadowVBIOS(ScrnInfoPtr pScrn, uint8_t *data)
164 NVShadowVBIOS_PROM(pScrn, data);
165 if (NVValidVBIOS(pScrn, data) == 2)
168 NVShadowVBIOS_PRAMIN(pScrn, data);
169 if (NVValidVBIOS(pScrn, data))
173 NVVBIOS_PCIROM(pScrn, data);
174 if (NVValidVBIOS(pScrn, data))
186 int length_multiplier;
187 bool (*handler)(ScrnInfoPtr pScrn, bios_t *, uint16_t, init_exec_t *);
196 static void parse_init_table(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset, init_exec_t *iexec);
198 #define MACRO_INDEX_SIZE 2
200 #define CONDITION_SIZE 12
201 #define IO_FLAG_CONDITION_SIZE 9
202 #define MEM_INIT_SIZE 66
204 static void still_alive(void)
210 static int nv_valid_reg(ScrnInfoPtr pScrn, uint32_t reg)
212 NVPtr pNv = NVPTR(pScrn);
214 /* C51 has misaligned regs on purpose. Marvellous */
215 if ((reg & 0x3 && pNv->VBIOS.chip_version != 0x51) ||
216 (reg & 0x2 && pNv->VBIOS.chip_version == 0x51)) {
217 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
218 "========== misaligned reg 0x%08X ==========\n", reg);
222 #define WITHIN(x,y,z) ((x>=y)&&(x<=y+z))
223 if (WITHIN(reg,NV_PMC_OFFSET,NV_PMC_SIZE))
225 if (WITHIN(reg,NV_PBUS_OFFSET,NV_PBUS_SIZE))
227 if (WITHIN(reg,NV_PFIFO_OFFSET,NV_PFIFO_SIZE))
229 if (pNv->VBIOS.chip_version >= 0x30 && WITHIN(reg,0x4000,0x600))
231 if (pNv->VBIOS.chip_version >= 0x40 && WITHIN(reg,0xc000,0x48))
233 if (pNv->VBIOS.chip_version >= 0x17 && reg == 0x0000d204)
235 if (pNv->VBIOS.chip_version >= 0x40) {
236 if (reg == 0x00011014 || reg == 0x00020328)
238 if (WITHIN(reg,0x88000,NV_PBUS_SIZE)) /* new PBUS */
241 if (WITHIN(reg,NV_PFB_OFFSET,NV_PFB_SIZE))
243 if (WITHIN(reg,NV_PEXTDEV_OFFSET,NV_PEXTDEV_SIZE))
245 if (WITHIN(reg,NV_PCRTC0_OFFSET,NV_PCRTC0_SIZE * 2))
247 if (WITHIN(reg,NV_PRAMDAC0_OFFSET,NV_PRAMDAC0_SIZE * 2))
249 if (pNv->VBIOS.chip_version >= 0x17 && reg == 0x0070fff0)
251 if (pNv->VBIOS.chip_version == 0x51 && WITHIN(reg,NV_PRAMIN_OFFSET,NV_PRAMIN_SIZE))
255 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
256 "========== unknown reg 0x%08X ==========\n", reg);
261 static bool nv_valid_idx_port(ScrnInfoPtr pScrn, uint16_t port)
263 /* if adding more ports here, the read/write functions below will need
264 * updating so that the correct mmio range (PCIO, PDIO, PVIO) is used
265 * for the port in question
267 if (port == CRTC_INDEX_COLOR)
269 if (port == SEQ_INDEX)
272 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
273 "========== unknown indexed io port 0x%04X ==========\n", port);
278 static bool nv_valid_port(ScrnInfoPtr pScrn, uint16_t port)
280 /* if adding more ports here, the read/write functions below will need
281 * updating so that the correct mmio range (PCIO, PDIO, PVIO) is used
282 * for the port in question
284 if (port == VGA_ENABLE)
287 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
288 "========== unknown io port 0x%04X ==========\n", port);
293 static uint32_t nv32_rd(ScrnInfoPtr pScrn, uint32_t reg)
295 NVPtr pNv = NVPTR(pScrn);
298 if (!nv_valid_reg(pScrn, reg))
301 /* C51 sometimes uses regs with bit0 set in the address. For these
302 * cases there should exist a translation in a BIOS table to an IO
303 * port address which the BIOS uses for accessing the reg
305 * These only seem to appear for the power control regs to a flat panel
306 * and in C51 mmio traces the normal regs for 0x1308 and 0x1310 are
307 * used - hence the mask below. An S3 suspend-resume mmio trace from a
308 * C51 will be required to see if this is true for the power microcode
309 * in 0x14.., or whether the direct IO port access method is needed
314 data = NV_RD32(pNv->REGS, reg);
317 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
318 " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
323 static void nv32_wr(ScrnInfoPtr pScrn, uint32_t reg, uint32_t data)
325 NVPtr pNv = NVPTR(pScrn);
327 if (!nv_valid_reg(pScrn, reg))
330 /* see note in nv32_rd */
337 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
338 " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
340 if (pNv->VBIOS.execute) {
342 NV_WR32(pNv->REGS, reg, data);
346 static uint8_t nv_idx_port_rd(ScrnInfoPtr pScrn, uint16_t port, uint8_t index)
348 NVPtr pNv = NVPTR(pScrn);
351 if (!nv_valid_idx_port(pScrn, port))
354 if (port == SEQ_INDEX)
355 data = NVReadVgaSeq(pNv, crtchead, index);
356 else /* assume CRTC_INDEX_COLOR */
357 data = NVReadVgaCrtc(pNv, crtchead, index);
360 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
361 " Indexed IO read: Port: 0x%04X, Index: 0x%02X, Head: 0x%02X, Data: 0x%02X\n",
362 port, index, crtchead, data);
367 static void nv_idx_port_wr(ScrnInfoPtr pScrn, uint16_t port, uint8_t index, uint8_t data)
369 NVPtr pNv = NVPTR(pScrn);
371 if (!nv_valid_idx_port(pScrn, port))
374 /* The current head is maintained in a file scope variable crtchead.
375 * We trap changes to CRTCX_OWNER and update the head variable
376 * and hence the register set written.
377 * As CRTCX_OWNER only exists on CRTC0, we update crtchead to head0
378 * in advance of the write, and to head1 after the write
380 if (port == CRTC_INDEX_COLOR && index == NV_VGA_CRTCX_OWNER && data != NV_VGA_CRTCX_OWNER_HEADB)
384 nv_idx_port_rd(pScrn, port, index);
386 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
387 " Indexed IO write: Port: 0x%04X, Index: 0x%02X, Head: 0x%02X, Data: 0x%02X\n",
388 port, index, crtchead, data);
390 if (pNv->VBIOS.execute) {
392 if (port == SEQ_INDEX)
393 NVWriteVgaSeq(pNv, crtchead, index, data);
394 else /* assume CRTC_INDEX_COLOR */
395 NVWriteVgaCrtc(pNv, crtchead, index, data);
398 if (port == CRTC_INDEX_COLOR && index == NV_VGA_CRTCX_OWNER && data == NV_VGA_CRTCX_OWNER_HEADB)
402 static uint8_t nv_port_rd(ScrnInfoPtr pScrn, uint16_t port)
404 NVPtr pNv = NVPTR(pScrn);
407 if (!nv_valid_port(pScrn, port))
410 data = NVReadPVIO(pNv, crtchead, port);
413 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
414 " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
415 port, crtchead, data);
420 static void nv_port_wr(ScrnInfoPtr pScrn, uint16_t port, uint8_t data)
422 NVPtr pNv = NVPTR(pScrn);
424 if (!nv_valid_port(pScrn, port))
428 nv_port_rd(pScrn, port);
430 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
431 " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
432 port, crtchead, data);
434 if (pNv->VBIOS.execute) {
436 NVWritePVIO(pNv, crtchead, port, data);
440 #define ACCESS_UNLOCK 0
441 #define ACCESS_LOCK 1
442 static void crtc_access(ScrnInfoPtr pScrn, bool lock)
444 NVPtr pNv = NVPTR(pScrn);
447 NVSetOwner(pScrn, 0);
448 NVLockVgaCrtc(pNv, 0, lock);
450 NVSetOwner(pScrn, 1);
451 NVLockVgaCrtc(pNv, 1, lock);
452 NVSetOwner(pScrn, crtchead);
456 static bool io_flag_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, uint8_t cond)
458 /* The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
459 * for the CRTC index; 1 byte for the mask to apply to the value
460 * retrieved from the CRTC; 1 byte for the shift right to apply to the
461 * masked CRTC value; 2 bytes for the offset to the flag array, to
462 * which the shifted value is added; 1 byte for the mask applied to the
463 * value read from the flag array; and 1 byte for the value to compare
464 * against the masked byte from the flag table.
467 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
468 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[condptr])));
469 uint8_t crtcindex = bios->data[condptr + 2];
470 uint8_t mask = bios->data[condptr + 3];
471 uint8_t shift = bios->data[condptr + 4];
472 uint16_t flagarray = le16_to_cpu(*((uint16_t *)(&bios->data[condptr + 5])));
473 uint8_t flagarraymask = bios->data[condptr + 7];
474 uint8_t cmpval = bios->data[condptr + 8];
478 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
479 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, Cmpval: 0x%02X\n",
480 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
482 data = nv_idx_port_rd(pScrn, crtcport, crtcindex);
484 data = bios->data[flagarray + ((data & mask) >> shift)];
485 data &= flagarraymask;
488 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
489 "0x%04X: Checking if 0x%02X equals 0x%02X\n",
490 offset, data, cmpval);
498 int getMNP_single(ScrnInfoPtr pScrn, struct pll_lims *pll_lim, int clk, int *bestNM, int *bestlog2P)
500 /* Find M, N and P for a single stage PLL
502 * Note that some bioses (NV3x) have lookup tables of precomputed MNP
503 * values, but we're too lazy to use those atm
505 * "clk" parameter in kHz
506 * returns calculated clock
509 bios_t *bios = &NVPTR(pScrn)->VBIOS;
510 int minvco = pll_lim->vco1.minfreq, maxvco = pll_lim->vco1.maxfreq;
511 int minM = pll_lim->vco1.min_m, maxM = pll_lim->vco1.max_m;
512 int minN = pll_lim->vco1.min_n, maxN = pll_lim->vco1.max_n;
513 int minU = pll_lim->vco1.min_inputfreq, maxU = pll_lim->vco1.max_inputfreq;
515 int crystal = pll_lim->refclk;
518 int delta, bestdelta = INT_MAX;
521 /* this division verified for nv20, nv18, nv28 (Haiku), and nv34 */
522 /* possibly correlated with introduction of 27MHz crystal */
523 if (bios->chip_version <= 0x16 || bios->chip_version == 0x20) {
529 } else if (bios->chip_version < 0x40) {
537 } else /* nv4x may be subject to the nv17+ limits, but assume not for now */
540 if ((clk << maxlog2P) < minvco) {
541 minvco = clk << maxlog2P;
544 if (clk + clk/200 > maxvco) /* +0.5% */
545 maxvco = clk + clk/200;
547 /* NV34 goes maxlog2P->0, NV20 goes 0->maxlog2P */
548 for (log2P = 0; log2P <= maxlog2P; log2P++) {
557 for (M = minM; M <= maxM; M++) {
558 if (crystal/M < minU)
560 if (crystal/M > maxU)
563 /* add crystal/2 to round better */
564 N = (clkP * M + crystal/2) / crystal;
571 /* more rounding additions */
572 calcclk = ((N * crystal + P/2) / P + M/2) / M;
573 delta = abs(calcclk - clk);
574 /* we do an exhaustive search rather than terminating
575 * on an optimality condition...
577 if (delta < bestdelta) {
580 *bestNM = N << 8 | M;
582 if (delta == 0) /* except this one */
591 int getMNP_double(ScrnInfoPtr pScrn, struct pll_lims *pll_lim, int clk, int *bestNM1, int *bestNM2, int *bestlog2P)
593 /* Find M, N and P for a two stage PLL
595 * Note that some bioses (NV30+) have lookup tables of precomputed MNP
596 * values, but we're too lazy to use those atm
598 * "clk" parameter in kHz
599 * returns calculated clock
602 int minvco1 = pll_lim->vco1.minfreq, maxvco1 = pll_lim->vco1.maxfreq;
603 int minvco2 = pll_lim->vco2.minfreq, maxvco2 = pll_lim->vco2.maxfreq;
604 int minU1 = pll_lim->vco1.min_inputfreq, minU2 = pll_lim->vco2.min_inputfreq;
605 int maxU1 = pll_lim->vco1.max_inputfreq, maxU2 = pll_lim->vco2.max_inputfreq;
606 int minM1 = pll_lim->vco1.min_m, maxM1 = pll_lim->vco1.max_m;
607 int minN1 = pll_lim->vco1.min_n, maxN1 = pll_lim->vco1.max_n;
608 int minM2 = pll_lim->vco2.min_m, maxM2 = pll_lim->vco2.max_m;
609 int minN2 = pll_lim->vco2.min_n, maxN2 = pll_lim->vco2.max_n;
610 int crystal = pll_lim->refclk;
611 bool fixedgain2 = (minM2 == maxM2 && minN2 == maxN2);
612 int M1, N1, M2, N2, log2P;
613 int clkP, calcclk1, calcclk2, calcclkout;
614 int delta, bestdelta = INT_MAX;
617 int vco2 = (maxvco2 - maxvco2/200) / 2;
618 for (log2P = 0; log2P < 6 && clk <= (vco2 >> log2P); log2P++) /* log2P is maximum of 6 */
622 if (maxvco2 < clk + clk/200) /* +0.5% */
623 maxvco2 = clk + clk/200;
625 for (M1 = minM1; M1 <= maxM1; M1++) {
626 if (crystal/M1 < minU1)
628 if (crystal/M1 > maxU1)
631 for (N1 = minN1; N1 <= maxN1; N1++) {
632 calcclk1 = crystal * N1 / M1;
633 if (calcclk1 < minvco1)
635 if (calcclk1 > maxvco1)
638 for (M2 = minM2; M2 <= maxM2; M2++) {
639 if (calcclk1/M2 < minU2)
641 if (calcclk1/M2 > maxU2)
644 /* add calcclk1/2 to round better */
645 N2 = (clkP * M2 + calcclk1/2) / calcclk1;
652 if (N2/M2 < 4 || N2/M2 > 10)
655 calcclk2 = calcclk1 * N2 / M2;
656 if (calcclk2 < minvco2)
658 if (calcclk2 > maxvco2)
663 calcclkout = calcclk2 >> log2P;
664 delta = abs(calcclkout - clk);
665 /* we do an exhaustive search rather than terminating
666 * on an optimality condition...
668 if (delta < bestdelta) {
670 bestclk = calcclkout;
671 *bestNM1 = N1 << 8 | M1;
672 *bestNM2 = N2 << 8 | M2;
674 if (delta == 0) /* except this one */
684 static void setPLL_single(ScrnInfoPtr pScrn, uint32_t reg, int NM, int log2P)
686 bios_t *bios = &NVPTR(pScrn)->VBIOS;
687 uint32_t oldpll = nv32_rd(pScrn, reg);
688 uint32_t pll = (oldpll & 0xfff80000) | log2P << 16 | NM;
689 uint32_t saved_powerctrl_1 = 0;
690 int shift_powerctrl_1 = -4;
693 return; /* already set */
695 /* nv18 doesn't change POWERCTRL_1 for VPLL*; does gf4 need special-casing? */
696 if (bios->chip_version >= 0x17 && bios->chip_version != 0x20) {
698 case NV_RAMDAC_VPLL2:
699 shift_powerctrl_1 += 4;
701 shift_powerctrl_1 += 4;
703 shift_powerctrl_1 += 4;
704 case NV_RAMDAC_NVPLL:
705 shift_powerctrl_1 += 4;
708 if (shift_powerctrl_1 >= 0) {
709 saved_powerctrl_1 = nv32_rd(pScrn, NV_PBUS_POWERCTRL_1);
710 nv32_wr(pScrn, NV_PBUS_POWERCTRL_1, (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) | 1 << shift_powerctrl_1);
715 nv32_wr(pScrn, reg, (oldpll & 0xffff0000) | NM);
721 /* then write P as well */
722 nv32_wr(pScrn, reg, pll);
724 if (shift_powerctrl_1 >= 0)
725 nv32_wr(pScrn, NV_PBUS_POWERCTRL_1, saved_powerctrl_1);
728 static void setPLL_double_highregs(ScrnInfoPtr pScrn, uint32_t reg1, int NM1, int NM2, int log2P)
730 bios_t *bios = &NVPTR(pScrn)->VBIOS;
731 uint32_t reg2 = reg1 + ((reg1 == NV_RAMDAC_VPLL2) ? 0x5c : 0x70);
732 uint32_t oldpll1 = nv32_rd(pScrn, reg1), oldpll2 = nv32_rd(pScrn, reg2);
733 uint32_t pll1 = (oldpll1 & 0xfff80000) | log2P << 16 | NM1;
734 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | NM2;
735 uint32_t saved_powerctrl_1 = 0, savedc040 = 0, maskc040 = ~0;
736 int shift_powerctrl_1 = -1;
738 if (oldpll1 == pll1 && oldpll2 == pll2)
739 return; /* already set */
741 if (reg1 == NV_RAMDAC_NVPLL) {
742 shift_powerctrl_1 = 0;
743 maskc040 = ~(3 << 20);
745 if (reg1 == NV_RAMDAC_MPLL) {
746 shift_powerctrl_1 = 4;
747 maskc040 = ~(3 << 22);
749 if (shift_powerctrl_1 >= 0) {
750 saved_powerctrl_1 = nv32_rd(pScrn, NV_PBUS_POWERCTRL_1);
751 nv32_wr(pScrn, NV_PBUS_POWERCTRL_1, (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) | 1 << shift_powerctrl_1);
754 if (bios->chip_version >= 0x40) {
755 savedc040 = nv32_rd(pScrn, 0xc040);
756 nv32_wr(pScrn, 0xc040, savedc040 & maskc040);
759 if (reg1 == NV_RAMDAC_VPLL)
760 nv32_wr(pScrn, NV_RAMDAC_580, nv32_rd(pScrn, NV_RAMDAC_580) & ~NV_RAMDAC_580_VPLL1_ACTIVE);
761 if (reg1 == NV_RAMDAC_VPLL2)
762 nv32_wr(pScrn, NV_RAMDAC_580, nv32_rd(pScrn, NV_RAMDAC_580) & ~NV_RAMDAC_580_VPLL2_ACTIVE);
764 if (reg1 == NV_RAMDAC_VPLL)
765 nv32_wr(pScrn, NV_RAMDAC_580, nv32_rd(pScrn, NV_RAMDAC_580) | NV_RAMDAC_580_VPLL1_ACTIVE);
766 if (reg1 == NV_RAMDAC_VPLL2)
767 nv32_wr(pScrn, NV_RAMDAC_580, nv32_rd(pScrn, NV_RAMDAC_580) | NV_RAMDAC_580_VPLL2_ACTIVE);
772 nv32_wr(pScrn, reg2, pll2);
773 nv32_wr(pScrn, reg1, pll1);
775 if (shift_powerctrl_1 >= 0) {
776 nv32_wr(pScrn, NV_PBUS_POWERCTRL_1, saved_powerctrl_1);
777 if (bios->chip_version >= 0x40)
778 nv32_wr(pScrn, 0xc040, savedc040);
782 static void setPLL_double_lowregs(ScrnInfoPtr pScrn, uint32_t NMNMreg, int NM1, int NM2, int log2P)
784 /* When setting PLLs, there is a merry game of disabling and enabling
785 * various bits of hardware during the process. This function is a
786 * synthesis of six nv40 traces, nearly each card doing a subtly
787 * different thing. With luck all the necessary bits for each card are
788 * combined herein. Without luck it deviates from each card's formula
789 * so as to not work on any :)
792 uint32_t Preg = NMNMreg - 4;
793 uint32_t oldPval = nv32_rd(pScrn, Preg);
794 uint32_t NMNM = NM2 << 16 | NM1;
795 uint32_t Pval = (oldPval & ((Preg == 0x4020) ? ~(0x11 << 16) : ~(1 << 16))) | 0xc << 28 | log2P << 16;
796 uint32_t saved4600 = 0;
797 /* some cards have different maskc040s */
798 uint32_t maskc040 = ~(3 << 14), savedc040;
800 if (nv32_rd(pScrn, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval)
806 maskc040 = ~(3 << 26);
808 if (Preg == 0x4020) {
809 struct pll_lims pll_lim;
812 if (!get_pll_limits(pScrn, Preg, &pll_lim))
815 Pval2 = log2P + pll_lim.log2p_bias;
816 if (Pval2 > pll_lim.max_log2p_bias)
817 Pval2 = pll_lim.max_log2p_bias;
818 Pval |= 1 << 28 | Pval2 << 20;
820 saved4600 = nv32_rd(pScrn, 0x4600);
821 nv32_wr(pScrn, 0x4600, saved4600 | 8 << 28);
824 nv32_wr(pScrn, Preg, oldPval | 1 << 28);
825 nv32_wr(pScrn, Preg, Pval & ~(4 << 28));
826 if (Preg == 0x4020) {
827 // some cards do '| 1 << 12', but using it breaks on 6600 :(
828 Pval |= 8 << 20;// | 1 << 12;
829 nv32_wr(pScrn, 0x4020, Pval & ~(3 << 30));
830 nv32_wr(pScrn, 0x4038, Pval & ~(3 << 30));
833 savedc040 = nv32_rd(pScrn, 0xc040);
834 nv32_wr(pScrn, 0xc040, savedc040 & maskc040);
836 nv32_wr(pScrn, NMNMreg, NMNM);
837 if (NMNMreg == 0x4024)
838 nv32_wr(pScrn, 0x403c, NMNM);
840 nv32_wr(pScrn, Preg, Pval);
841 if (Preg == 0x4020) {
843 nv32_wr(pScrn, 0x4020, Pval);
844 nv32_wr(pScrn, 0x4038, Pval);
845 nv32_wr(pScrn, 0x4600, saved4600);
848 nv32_wr(pScrn, 0xc040, savedc040);
850 if (Preg == 0x4020) {
851 nv32_wr(pScrn, 0x4020, Pval & ~(1 << 28));
852 nv32_wr(pScrn, 0x4038, Pval & ~(1 << 28));
856 static void setPLL(ScrnInfoPtr pScrn, bios_t *bios, uint32_t reg, uint32_t clk)
859 struct pll_lims pll_lim;
860 int NM1 = 0xbeef, NM2 = 0xdead, log2P;
862 /* high regs (such as in the mac g5 table) are not -= 4 */
863 if (!get_pll_limits(pScrn, reg > 0x405c ? reg : reg - 4, &pll_lim))
866 if (bios->chip_version >= 0x40 || bios->chip_version == 0x31 || bios->chip_version == 0x36) {
867 getMNP_double(pScrn, &pll_lim, clk, &NM1, &NM2, &log2P);
869 setPLL_double_highregs(pScrn, reg, NM1, NM2, log2P);
871 setPLL_double_lowregs(pScrn, reg, NM1, NM2, log2P);
873 getMNP_single(pScrn, &pll_lim, clk, &NM1, &log2P);
874 setPLL_single(pScrn, reg, NM1, log2P);
879 static bool init_prog(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
881 /* INIT_PROG opcode: 0x31
883 * offset (8 bit): opcode
884 * offset + 1 (32 bit): reg
885 * offset + 5 (32 bit): and mask
886 * offset + 9 (8 bit): shift right
887 * offset + 10 (8 bit): number of configurations
888 * offset + 11 (32 bit): register
889 * offset + 15 (32 bit): configuration 1
892 * Starting at offset + 15 there are "number of configurations"
893 * 32 bit values. To find out which configuration value to use
894 * read "CRTC reg" on the CRTC controller with index "CRTC index"
895 * and bitwise AND this value with "and mask" and then bit shift the
896 * result "shift right" bits to the right.
897 * Assign "register" with appropriate configuration value.
900 CARD32 reg = *((CARD32 *) (&bios->data[offset + 1]));
901 CARD32 and = *((CARD32 *) (&bios->data[offset + 5]));
902 CARD8 shiftr = *((CARD8 *) (&bios->data[offset + 9]));
903 CARD8 nr = *((CARD8 *) (&bios->data[offset + 10]));
904 CARD32 reg2 = *((CARD32 *) (&bios->data[offset + 11]));
906 CARD32 configval, tmp;
908 if (iexec->execute) {
909 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: REG: 0x%04X\n", offset,
912 tmp = nv32_rd(pScrn, reg);
913 configuration = (tmp & and) >> shiftr;
915 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONFIGURATION TO USE: 0x%02X\n",
916 offset, configuration);
918 if (configuration <= nr) {
921 *((CARD32 *) (&bios->data[offset + 15 + configuration * 4]));
923 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: REG: 0x%08X, VALUE: 0x%08X\n", offset,
926 tmp = nv32_rd(pScrn, reg2);
927 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CURRENT VALUE IS: 0x%08X\n",
929 nv32_wr(pScrn, reg2, configval);
936 static bool init_io_restrict_prog(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
938 /* INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
940 * offset (8 bit): opcode
941 * offset + 1 (16 bit): CRTC port
942 * offset + 3 (8 bit): CRTC index
943 * offset + 4 (8 bit): mask
944 * offset + 5 (8 bit): shift
945 * offset + 6 (8 bit): count
946 * offset + 7 (32 bit): register
947 * offset + 11 (32 bit): configuration 1
950 * Starting at offset + 11 there are "count" 32 bit values.
951 * To find out which value to use read index "CRTC index" on "CRTC port",
952 * AND this value with "mask" and then bit shift right "shift" bits.
953 * Read the appropriate value using this index and write to "register"
956 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
957 uint8_t crtcindex = bios->data[offset + 3];
958 uint8_t mask = bios->data[offset + 4];
959 uint8_t shift = bios->data[offset + 5];
960 uint8_t count = bios->data[offset + 6];
961 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7])));
969 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
970 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
971 offset, crtcport, crtcindex, mask, shift, count, reg);
973 config = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) >> shift;
974 if (config > count) {
975 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
976 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
977 offset, config, count);
981 configval = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 11 + config * 4])));
984 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
985 "0x%04X: Writing config %02X\n", offset, config);
987 nv32_wr(pScrn, reg, configval);
992 static bool init_repeat(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
994 /* INIT_REPEAT opcode: 0x33 ('3')
996 * offset (8 bit): opcode
997 * offset + 1 (8 bit): count
999 * Execute script following this opcode up to INIT_REPEAT_END
1003 uint8_t count = bios->data[offset + 1];
1006 /* no iexec->execute check by design */
1008 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1009 "0x%04X: REPEATING FOLLOWING SEGMENT %d TIMES\n",
1012 iexec->repeat = true;
1014 /* count - 1, as the script block will execute once when we leave this
1015 * opcode -- this is compatible with bios behaviour as:
1016 * a) the block is always executed at least once, even if count == 0
1017 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
1020 for (i = 0; i < count - 1; i++)
1021 parse_init_table(pScrn, bios, offset + 2, iexec);
1023 iexec->repeat = false;
1028 static bool init_io_restrict_pll(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1030 /* INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
1032 * offset (8 bit): opcode
1033 * offset + 1 (16 bit): CRTC port
1034 * offset + 3 (8 bit): CRTC index
1035 * offset + 4 (8 bit): mask
1036 * offset + 5 (8 bit): shift
1037 * offset + 6 (8 bit): IO flag condition index
1038 * offset + 7 (8 bit): count
1039 * offset + 8 (32 bit): register
1040 * offset + 12 (16 bit): frequency 1
1043 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
1044 * Set PLL register "register" to coefficients for frequency n,
1045 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1046 * "mask" and shifted right by "shift". If "IO flag condition index" > 0,
1047 * and condition met, double frequency before setting it.
1050 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1051 uint8_t crtcindex = bios->data[offset + 3];
1052 uint8_t mask = bios->data[offset + 4];
1053 uint8_t shift = bios->data[offset + 5];
1054 int8_t io_flag_condition_idx = bios->data[offset + 6];
1055 uint8_t count = bios->data[offset + 7];
1056 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 8])));
1060 if (!iexec->execute)
1063 if (DEBUGLEVEL >= 6)
1064 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1065 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, IO Flag Condition: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1066 offset, crtcport, crtcindex, mask, shift, io_flag_condition_idx, count, reg);
1068 config = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) >> shift;
1069 if (config > count) {
1070 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1071 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1072 offset, config, count);
1076 freq = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 12 + config * 2])));
1078 if (io_flag_condition_idx > 0) {
1079 if (io_flag_condition(pScrn, bios, offset, io_flag_condition_idx)) {
1080 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1081 "0x%04X: CONDITION FULFILLED - FREQ DOUBLED\n", offset);
1084 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1085 "0x%04X: CONDITION IS NOT FULFILLED. FREQ UNCHANGED\n", offset);
1088 if (DEBUGLEVEL >= 6)
1089 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1090 "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
1091 offset, reg, config, freq);
1093 setPLL(pScrn, bios, reg, freq * 10);
1098 static bool init_end_repeat(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1100 /* INIT_END_REPEAT opcode: 0x36 ('6')
1102 * offset (8 bit): opcode
1104 * Marks the end of the block for INIT_REPEAT to repeat
1107 /* no iexec->execute check by design */
1109 /* iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
1110 * we're not in repeat mode
1118 static bool init_copy(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1120 /* INIT_COPY opcode: 0x37 ('7')
1122 * offset (8 bit): opcode
1123 * offset + 1 (32 bit): register
1124 * offset + 5 (8 bit): shift
1125 * offset + 6 (8 bit): srcmask
1126 * offset + 7 (16 bit): CRTC port
1127 * offset + 9 (8 bit): CRTC index
1128 * offset + 10 (8 bit): mask
1130 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
1131 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC port
1134 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1135 uint8_t shift = bios->data[offset + 5];
1136 uint8_t srcmask = bios->data[offset + 6];
1137 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 7])));
1138 uint8_t crtcindex = bios->data[offset + 9];
1139 uint8_t mask = bios->data[offset + 10];
1143 if (!iexec->execute)
1146 if (DEBUGLEVEL >= 6)
1147 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1148 "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1149 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1151 data = nv32_rd(pScrn, reg);
1156 data <<= (0x100 - shift);
1160 crtcdata = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) | (uint8_t)data;
1161 nv_idx_port_wr(pScrn, crtcport, crtcindex, crtcdata);
1166 static bool init_not(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1168 /* INIT_NOT opcode: 0x38 ('8')
1170 * offset (8 bit): opcode
1172 * Invert the current execute / no-execute condition (i.e. "else")
1175 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1176 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
1178 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1179 "0x%04X: ------ EXECUTING FOLLOWING COMMANDS ------\n", offset);
1181 iexec->execute = !iexec->execute;
1185 static bool init_io_flag_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1187 /* INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1189 * offset (8 bit): opcode
1190 * offset + 1 (8 bit): condition number
1192 * Check condition "condition number" in the IO flag condition table.
1193 * If condition not met skip subsequent opcodes until condition is
1194 * inverted (INIT_NOT), or we hit INIT_RESUME
1197 uint8_t cond = bios->data[offset + 1];
1199 if (!iexec->execute)
1202 if (io_flag_condition(pScrn, bios, offset, cond))
1203 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1204 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n", offset);
1206 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1207 "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
1208 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1209 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
1210 iexec->execute = false;
1216 static bool init_idx_addr_latched(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1218 /* INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1220 * offset (8 bit): opcode
1221 * offset + 1 (32 bit): control register
1222 * offset + 5 (32 bit): data register
1223 * offset + 9 (32 bit): mask
1224 * offset + 13 (32 bit): data
1225 * offset + 17 (8 bit): count
1226 * offset + 18 (8 bit): address 1
1227 * offset + 19 (8 bit): data 1
1230 * For each of "count" address and data pairs, write "data n" to "data register",
1231 * read the current value of "control register", and write it back once ANDed
1232 * with "mask", ORed with "data", and ORed with "address n"
1235 uint32_t controlreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1236 uint32_t datareg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1237 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
1238 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 13])));
1239 uint8_t count = bios->data[offset + 17];
1243 if (!iexec->execute)
1246 if (DEBUGLEVEL >= 6)
1247 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1248 "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1249 offset, controlreg, datareg, mask, data, count);
1251 for (i = 0; i < count; i++) {
1252 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1253 uint8_t instdata = bios->data[offset + 19 + i * 2];
1255 if (DEBUGLEVEL >= 6)
1256 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1257 "0x%04X: Address: 0x%02X, Data: 0x%02X\n", offset, instaddress, instdata);
1259 nv32_wr(pScrn, datareg, instdata);
1260 value = (nv32_rd(pScrn, controlreg) & mask) | data | instaddress;
1261 nv32_wr(pScrn, controlreg, value);
1267 static bool init_io_restrict_pll2(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1269 /* INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1271 * offset (8 bit): opcode
1272 * offset + 1 (16 bit): CRTC port
1273 * offset + 3 (8 bit): CRTC index
1274 * offset + 4 (8 bit): mask
1275 * offset + 5 (8 bit): shift
1276 * offset + 6 (8 bit): count
1277 * offset + 7 (32 bit): register
1278 * offset + 11 (32 bit): frequency 1
1281 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1282 * Set PLL register "register" to coefficients for frequency n,
1283 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1284 * "mask" and shifted right by "shift".
1287 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1288 uint8_t crtcindex = bios->data[offset + 3];
1289 uint8_t mask = bios->data[offset + 4];
1290 uint8_t shift = bios->data[offset + 5];
1291 uint8_t count = bios->data[offset + 6];
1292 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7])));
1296 if (!iexec->execute)
1299 if (DEBUGLEVEL >= 6)
1300 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1301 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1302 offset, crtcport, crtcindex, mask, shift, count, reg);
1307 config = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) >> shift;
1308 if (config > count) {
1309 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1310 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1311 offset, config, count);
1315 freq = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 11 + config * 4])));
1317 if (DEBUGLEVEL >= 6)
1318 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1319 "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1320 offset, reg, config, freq);
1322 setPLL(pScrn, bios, reg, freq);
1327 static bool init_pll2(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1329 /* INIT_PLL2 opcode: 0x4B ('K')
1331 * offset (8 bit): opcode
1332 * offset + 1 (32 bit): register
1333 * offset + 5 (32 bit): freq
1335 * Set PLL register "register" to coefficients for frequency "freq"
1338 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1339 uint32_t freq = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1341 if (!iexec->execute)
1344 if (DEBUGLEVEL >= 6)
1345 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1346 "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1349 setPLL(pScrn, bios, reg, freq);
1354 static uint32_t get_tmds_index_reg(ScrnInfoPtr pScrn, uint8_t mlv)
1356 /* For mlv < 0x80, it is an index into a table of TMDS base addresses
1357 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by CR58 for CR57 = 0
1358 * to index a table of offsets to the basic 0x6808b0 address
1359 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by CR58 for CR57 = 0
1360 * to index a table of offsets to the basic 0x6808b0 address, and then flip the offset by 8
1363 NVPtr pNv = NVPTR(pScrn);
1364 const int pramdac_offset[13] = {0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000};
1365 const uint32_t pramdac_table[4] = {0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8};
1368 /* here we assume that the DCB table has already been parsed */
1371 /* This register needs to be written to set index for reading CR58 */
1372 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_57, 0);
1373 dcb_entry = nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_58);
1374 if (dcb_entry > pNv->dcb_table.entries) {
1375 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1376 "CR58 doesn't have a valid DCB entry currently (%02X)\n", dcb_entry);
1379 dacoffset = pramdac_offset[pNv->dcb_table.entry[dcb_entry].or];
1382 return (0x6808b0 + dacoffset);
1384 if (mlv > (sizeof(pramdac_table) / sizeof(uint32_t))) {
1385 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1386 "Magic Lookup Value too big (%02X)\n", mlv);
1389 return pramdac_table[mlv];
1393 static bool init_tmds(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1395 /* INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1397 * offset (8 bit): opcode
1398 * offset + 1 (8 bit): magic lookup value
1399 * offset + 2 (8 bit): TMDS address
1400 * offset + 3 (8 bit): mask
1401 * offset + 4 (8 bit): data
1403 * Read the data reg for TMDS address "TMDS address", AND it with mask
1404 * and OR it with data, then write it back
1405 * "magic lookup value" determines which TMDS base address register is used --
1406 * see get_tmds_index_reg()
1409 uint8_t mlv = bios->data[offset + 1];
1410 uint32_t tmdsaddr = bios->data[offset + 2];
1411 uint8_t mask = bios->data[offset + 3];
1412 uint8_t data = bios->data[offset + 4];
1413 uint32_t reg, value;
1415 if (!iexec->execute)
1418 if (DEBUGLEVEL >= 6)
1419 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1420 "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1421 offset, mlv, tmdsaddr, mask, data);
1423 if (!(reg = get_tmds_index_reg(pScrn, mlv)))
1426 nv32_wr(pScrn, reg, tmdsaddr | 0x10000);
1427 value = (nv32_rd(pScrn, reg + 4) & mask) | data;
1428 nv32_wr(pScrn, reg + 4, value);
1429 nv32_wr(pScrn, reg, tmdsaddr);
1434 static bool init_zm_tmds_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1436 /* INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1438 * offset (8 bit): opcode
1439 * offset + 1 (8 bit): magic lookup value
1440 * offset + 2 (8 bit): count
1441 * offset + 3 (8 bit): addr 1
1442 * offset + 4 (8 bit): data 1
1445 * For each of "count" TMDS address and data pairs write "data n" to "addr n"
1446 * "magic lookup value" determines which TMDS base address register is used --
1447 * see get_tmds_index_reg()
1450 uint8_t mlv = bios->data[offset + 1];
1451 uint8_t count = bios->data[offset + 2];
1455 if (!iexec->execute)
1458 if (DEBUGLEVEL >= 6)
1459 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1460 "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1461 offset, mlv, count);
1463 if (!(reg = get_tmds_index_reg(pScrn, mlv)))
1466 for (i = 0; i < count; i++) {
1467 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1468 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1470 nv32_wr(pScrn, reg + 4, tmdsdata);
1471 nv32_wr(pScrn, reg, tmdsaddr);
1477 static bool init_cr_idx_adr_latch(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1479 /* INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1481 * offset (8 bit): opcode
1482 * offset + 1 (8 bit): CRTC index1
1483 * offset + 2 (8 bit): CRTC index2
1484 * offset + 3 (8 bit): baseaddr
1485 * offset + 4 (8 bit): count
1486 * offset + 5 (8 bit): data 1
1489 * For each of "count" address and data pairs, write "baseaddr + n" to
1490 * "CRTC index1" and "data n" to "CRTC index2"
1491 * Once complete, restore initial value read from "CRTC index1"
1493 uint8_t crtcindex1 = bios->data[offset + 1];
1494 uint8_t crtcindex2 = bios->data[offset + 2];
1495 uint8_t baseaddr = bios->data[offset + 3];
1496 uint8_t count = bios->data[offset + 4];
1497 uint8_t oldaddr, data;
1500 if (!iexec->execute)
1503 if (DEBUGLEVEL >= 6)
1504 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1505 "0x%04X: Index1: 0x%02X, Index2: 0x%02X, BaseAddr: 0x%02X, Count: 0x%02X\n",
1506 offset, crtcindex1, crtcindex2, baseaddr, count);
1508 oldaddr = nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, crtcindex1);
1510 for (i = 0; i < count; i++) {
1511 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex1, baseaddr + i);
1513 data = bios->data[offset + 5 + i];
1514 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex2, data);
1517 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex1, oldaddr);
1522 static bool init_cr(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1524 /* INIT_CR opcode: 0x52 ('R')
1526 * offset (8 bit): opcode
1527 * offset + 1 (8 bit): CRTC index
1528 * offset + 2 (8 bit): mask
1529 * offset + 3 (8 bit): data
1531 * Assign the value of at "CRTC index" ANDed with mask and ORed with data
1532 * back to "CRTC index"
1535 uint8_t crtcindex = bios->data[offset + 1];
1536 uint8_t mask = bios->data[offset + 2];
1537 uint8_t data = bios->data[offset + 3];
1540 if (!iexec->execute)
1543 if (DEBUGLEVEL >= 6)
1544 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1545 "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1546 offset, crtcindex, mask, data);
1548 value = (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, crtcindex) & mask) | data;
1549 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex, value);
1554 static bool init_zm_cr(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1556 /* INIT_ZM_CR opcode: 0x53 ('S')
1558 * offset (8 bit): opcode
1559 * offset + 1 (8 bit): CRTC index
1560 * offset + 2 (8 bit): value
1562 * Assign "value" to CRTC register with index "CRTC index".
1565 uint8_t crtcindex = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1566 uint8_t data = bios->data[offset + 2];
1568 if (!iexec->execute)
1571 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex, data);
1576 static bool init_zm_cr_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1578 /* INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1580 * offset (8 bit): opcode
1581 * offset + 1 (8 bit): count
1582 * offset + 2 (8 bit): CRTC index 1
1583 * offset + 3 (8 bit): value 1
1586 * For "count", assign "value n" to CRTC register with index "CRTC index n".
1589 uint8_t count = bios->data[offset + 1];
1592 if (!iexec->execute)
1595 for (i = 0; i < count; i++)
1596 init_zm_cr(pScrn, bios, offset + 2 + 2 * i - 1, iexec);
1601 static bool init_condition_time(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1603 /* INIT_CONDITION_TIME opcode: 0x56 ('V')
1605 * offset (8 bit): opcode
1606 * offset + 1 (8 bit): condition number
1607 * offset + 2 (8 bit): retries / 50
1609 * Check condition "condition number" in the condition table.
1610 * The condition table entry has 4 bytes for the address of the
1611 * register to check, 4 bytes for a mask and 4 for a test value.
1612 * If condition not met sleep for 2ms, and repeat upto "retries" times.
1613 * If still not met after retries, clear execution flag for this table.
1616 uint8_t cond = bios->data[offset + 1];
1617 uint16_t retries = bios->data[offset + 2];
1618 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
1619 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[condptr])));
1620 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 4])));
1621 uint32_t cmpval = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 8])));
1624 if (!iexec->execute)
1629 if (DEBUGLEVEL >= 6)
1630 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1631 "0x%04X: Cond: 0x%02X, Retries: 0x%02X\n", offset, cond, retries);
1633 for (; retries > 0; retries--) {
1634 data = nv32_rd(pScrn, reg) & mask;
1636 if (DEBUGLEVEL >= 6)
1637 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1638 "0x%04X: Checking if 0x%08X equals 0x%08X\n",
1639 offset, data, cmpval);
1641 if (data != cmpval) {
1642 if (DEBUGLEVEL >= 6)
1643 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1644 "0x%04X: Condition not met, sleeping for 2ms\n", offset);
1647 if (DEBUGLEVEL >= 6)
1648 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1649 "0x%04X: Condition met, continuing\n", offset);
1654 if (data != cmpval) {
1655 if (DEBUGLEVEL >= 6)
1656 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1657 "0x%04X: Condition still not met, skiping following opcodes\n", offset);
1658 iexec->execute = false;
1664 static bool init_zm_reg_sequence(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1666 /* INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1668 * offset (8 bit): opcode
1669 * offset + 1 (32 bit): base register
1670 * offset + 5 (8 bit): count
1671 * offset + 6 (32 bit): value 1
1674 * Starting at offset + 6 there are "count" 32 bit values.
1675 * For "count" iterations set "base register" + 4 * current_iteration
1676 * to "value current_iteration"
1679 uint32_t basereg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1680 uint32_t count = bios->data[offset + 5];
1683 if (!iexec->execute)
1686 if (DEBUGLEVEL >= 6)
1687 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1688 "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1689 offset, basereg, count);
1691 for (i = 0; i < count; i++) {
1692 uint32_t reg = basereg + i * 4;
1693 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 6 + i * 4])));
1695 nv32_wr(pScrn, reg, data);
1702 static bool init_indirect_reg(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
1704 /* INIT_INDIRECT_REG opcode: 0x5A
1706 * offset (8 bit): opcode
1707 * offset + 1 (32 bit): register
1708 * offset + 5 (16 bit): adress offset (in bios)
1710 * Lookup value at offset data in the bios and write it to reg
1712 CARD32 reg = *((CARD32 *) (&bios->data[offset + 1]));
1713 CARD16 data = le16_to_cpu(*((CARD16 *) (&bios->data[offset + 5])));
1714 CARD32 data2 = bios->data[data];
1716 if (iexec->execute) {
1717 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1718 "0x%04X: REG: 0x%04X, DATA AT: 0x%04X, VALUE IS: 0x%08X\n",
1719 offset, reg, data, data2);
1721 if (DEBUGLEVEL >= 6) {
1723 tmpval = nv32_rd(pScrn, reg);
1724 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CURRENT VALUE IS: 0x%08X\n", offset, tmpval);
1727 nv32_wr(pScrn, reg, data2);
1733 static bool init_sub_direct(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1735 /* INIT_SUB_DIRECT opcode: 0x5B ('[')
1737 * offset (8 bit): opcode
1738 * offset + 1 (16 bit): subroutine offset (in bios)
1740 * Calls a subroutine that will execute commands until INIT_DONE
1744 uint16_t sub_offset = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1746 if (!iexec->execute)
1749 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: EXECUTING SUB-ROUTINE AT 0x%04X\n",
1750 offset, sub_offset);
1752 parse_init_table(pScrn, bios, sub_offset, iexec);
1754 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: END OF SUB-ROUTINE AT 0x%04X\n",
1755 offset, sub_offset);
1760 static bool init_copy_nv_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1762 /* INIT_COPY_NV_REG opcode: 0x5F ('_')
1764 * offset (8 bit): opcode
1765 * offset + 1 (32 bit): src reg
1766 * offset + 5 (8 bit): shift
1767 * offset + 6 (32 bit): src mask
1768 * offset + 10 (32 bit): xor
1769 * offset + 14 (32 bit): dst reg
1770 * offset + 18 (32 bit): dst mask
1772 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
1773 * "src mask", then XOR with "xor". Write this OR'd with
1774 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
1777 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
1778 uint8_t shift = bios->data[offset + 5];
1779 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
1780 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
1781 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
1782 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
1783 uint32_t srcvalue, dstvalue;
1785 if (!iexec->execute)
1788 if (DEBUGLEVEL >= 6)
1789 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1790 "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
1791 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
1793 srcvalue = nv32_rd(pScrn, srcreg);
1798 srcvalue <<= (0x100 - shift);
1800 srcvalue = (srcvalue & srcmask) ^ xor;
1802 dstvalue = nv32_rd(pScrn, dstreg) & dstmask;
1804 nv32_wr(pScrn, dstreg, dstvalue | srcvalue);
1809 static bool init_zm_index_io(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1811 /* INIT_ZM_INDEX_IO opcode: 0x62 ('b')
1813 * offset (8 bit): opcode
1814 * offset + 1 (16 bit): CRTC port
1815 * offset + 3 (8 bit): CRTC index
1816 * offset + 4 (8 bit): data
1818 * Write "data" to index "CRTC index" of "CRTC port"
1820 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1821 uint8_t crtcindex = bios->data[offset + 3];
1822 uint8_t data = bios->data[offset + 4];
1824 if (!iexec->execute)
1827 nv_idx_port_wr(pScrn, crtcport, crtcindex, data);
1832 static bool init_compute_mem(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1834 /* INIT_COMPUTE_MEM opcode: 0x63 ('c')
1836 * offset (8 bit): opcode
1838 * This opcode is meant to set NV_PFB_CFG0 (0x100200) appropriately so
1839 * that the hardware can correctly calculate how much VRAM it has
1840 * (and subsequently report that value in 0x10020C)
1842 * The implementation of this opcode in general consists of two parts:
1843 * 1) determination of the memory bus width
1844 * 2) determination of how many of the card's RAM pads have ICs attached
1846 * 1) is done by a cunning combination of writes to offsets 0x1c and
1847 * 0x3c in the framebuffer, and seeing whether the written values are
1848 * read back correctly. This then affects bits 4-7 of NV_PFB_CFG0
1850 * 2) is done by a cunning combination of writes to an offset slightly
1851 * less than the maximum memory reported by 0x10020C, then seeing if
1852 * the test pattern can be read back. This then affects bits 12-15 of
1855 * In this context a "cunning combination" may include multiple reads
1856 * and writes to varying locations, often alternating the test pattern
1857 * and 0, doubtless to make sure buffers are filled, residual charges
1858 * on tracks are removed etc.
1860 * Unfortunately, the "cunning combination"s mentioned above, and the
1861 * changes to the bits in NV_PFB_CFG0 differ with nearly every bios
1864 * Therefore, we cheat and assume the value of NV_PFB_CFG0 with which
1865 * we started was correct, and use that instead
1868 /* no iexec->execute check by design */
1870 /* on every card I've seen, this step gets done for us earlier in the init scripts
1871 uint8_t crdata = nv_idx_port_rd(pScrn, SEQ_INDEX, 0x01);
1872 nv_idx_port_wr(pScrn, SEQ_INDEX, 0x01, crdata | 0x20);
1875 /* this also has probably been done in the scripts, but an mmio trace of
1876 * s3 resume shows nvidia doing it anyway (unlike the SEQ_INDEX write)
1878 nv32_wr(pScrn, NV_PFB_REFCTRL, NV_PFB_REFCTRL_VALID_1);
1880 /* write back the saved configuration value */
1881 nv32_wr(pScrn, NV_PFB_CFG0, saved_nv_pfb_cfg0);
1886 static bool init_reset(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1888 /* INIT_RESET opcode: 0x65 ('e')
1890 * offset (8 bit): opcode
1891 * offset + 1 (32 bit): register
1892 * offset + 5 (32 bit): value1
1893 * offset + 9 (32 bit): value2
1895 * Assign "value1" to "register", then assign "value2" to "register"
1898 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1899 uint32_t value1 = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1900 uint32_t value2 = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
1901 uint32_t pci_nv_19, pci_nv_20;
1903 /* no iexec->execute check by design */
1905 pci_nv_19 = nv32_rd(pScrn, NV_PBUS_PCI_NV_19);
1906 nv32_wr(pScrn, NV_PBUS_PCI_NV_19, 0);
1907 nv32_wr(pScrn, reg, value1);
1911 nv32_wr(pScrn, reg, value2);
1912 nv32_wr(pScrn, NV_PBUS_PCI_NV_19, pci_nv_19);
1914 pci_nv_20 = nv32_rd(pScrn, NV_PBUS_PCI_NV_20);
1915 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
1916 nv32_wr(pScrn, NV_PBUS_PCI_NV_20, pci_nv_20);
1921 static bool init_configure_mem(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1923 /* INIT_CONFIGURE_MEM opcode: 0x66 ('f')
1925 * offset (8 bit): opcode
1927 * Equivalent to INIT_DONE on bios version 3 or greater.
1928 * For early bios versions, sets up the memory registers, using values
1929 * taken from the memory init table
1932 /* no iexec->execute check by design */
1934 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_SCRATCH4) >> 4);
1935 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
1938 if (bios->major_version > 2)
1941 nv_idx_port_wr(pScrn, SEQ_INDEX, 0x01, nv_idx_port_rd(pScrn, SEQ_INDEX, 0x01) | 0x20);
1943 if (bios->data[meminitoffs] & 1)
1944 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
1946 for (reg = le32_to_cpu(*(uint32_t *)&bios->data[seqtbloffs]);
1948 reg = le32_to_cpu(*(uint32_t *)&bios->data[seqtbloffs += 4])) {
1952 data = NV_PFB_PRE_CMD_PRECHARGE;
1955 data = NV_PFB_PAD_CKE_NORMAL;
1958 data = NV_PFB_REF_CMD_REFRESH;
1961 data = le32_to_cpu(*(uint32_t *)&bios->data[meminitdata]);
1963 if (data == 0xffffffff)
1967 nv32_wr(pScrn, reg, data);
1973 static bool init_configure_clk(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1975 /* INIT_CONFIGURE_CLK opcode: 0x67 ('g')
1977 * offset (8 bit): opcode
1979 * Equivalent to INIT_DONE on bios version 3 or greater.
1980 * For early bios versions, sets up the NVClk and MClk PLLs, using
1981 * values taken from the memory init table
1984 /* no iexec->execute check by design */
1986 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_SCRATCH4) >> 4);
1989 if (bios->major_version > 2)
1992 clock = le16_to_cpu(*(uint16_t *)&bios->data[meminitoffs + 4]) * 10;
1993 setPLL(pScrn, bios, NV_RAMDAC_NVPLL, clock);
1995 clock = le16_to_cpu(*(uint16_t *)&bios->data[meminitoffs + 2]) * 10;
1996 if (bios->data[meminitoffs] & 1) /* DDR */
1998 setPLL(pScrn, bios, NV_RAMDAC_MPLL, clock);
2003 static bool init_configure_preinit(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2005 /* INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2007 * offset (8 bit): opcode
2009 * Equivalent to INIT_DONE on bios version 3 or greater.
2010 * For early bios versions, does early init, loading ram and crystal
2011 * configuration from straps into CR3C
2014 /* no iexec->execute check by design */
2016 uint32_t straps = nv32_rd(pScrn, NV_PEXTDEV_BOOT_0);
2017 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & (1 << 6));
2019 if (bios->major_version > 2)
2022 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_SCRATCH4, cr3c);
2027 static bool init_io(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2029 /* INIT_IO opcode: 0x69 ('i')
2031 * offset (8 bit): opcode
2032 * offset + 1 (16 bit): CRTC port
2033 * offset + 3 (8 bit): mask
2034 * offset + 4 (8 bit): data
2036 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2039 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
2040 uint8_t mask = bios->data[offset + 3];
2041 uint8_t data = bios->data[offset + 4];
2043 if (!iexec->execute)
2046 if (DEBUGLEVEL >= 6)
2047 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2048 "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2049 offset, crtcport, mask, data);
2051 nv_port_wr(pScrn, crtcport, (nv_port_rd(pScrn, crtcport) & mask) | data);
2056 static bool init_sub(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2058 /* INIT_SUB opcode: 0x6B ('k')
2060 * offset (8 bit): opcode
2061 * offset + 1 (8 bit): script number
2063 * Execute script number "script number", as a subroutine
2066 uint8_t sub = bios->data[offset + 1];
2068 if (!iexec->execute)
2071 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2072 "0x%04X: EXECUTING SUB-SCRIPT %d\n", offset, sub);
2074 parse_init_table(pScrn, bios,
2075 le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + sub * 2]))),
2078 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2079 "0x%04X: END OF SUB-SCRIPT %d\n", offset, sub);
2084 static bool init_ram_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2086 /* INIT_RAM_CONDITION opcode: 0x6D ('m')
2088 * offset (8 bit): opcode
2089 * offset + 1 (8 bit): mask
2090 * offset + 2 (8 bit): cmpval
2092 * Test if (NV_PFB_BOOT_0 & "mask") equals "cmpval".
2093 * If condition not met skip subsequent opcodes until condition is
2094 * inverted (INIT_NOT), or we hit INIT_RESUME
2097 uint8_t mask = bios->data[offset + 1];
2098 uint8_t cmpval = bios->data[offset + 2];
2101 if (!iexec->execute)
2104 data = nv32_rd(pScrn, NV_PFB_BOOT_0) & mask;
2106 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2107 "0x%04X: Checking if 0x%08X equals 0x%08X\n", offset, data, cmpval);
2110 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2111 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n", offset);
2113 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
2114 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2115 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
2116 iexec->execute = false;
2122 static bool init_nv_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2124 /* INIT_NV_REG opcode: 0x6E ('n')
2126 * offset (8 bit): opcode
2127 * offset + 1 (32 bit): register
2128 * offset + 5 (32 bit): mask
2129 * offset + 9 (32 bit): data
2131 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2134 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2135 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
2136 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
2138 if (!iexec->execute)
2141 if (DEBUGLEVEL >= 6)
2142 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2143 "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2144 offset, reg, mask, data);
2146 nv32_wr(pScrn, reg, (nv32_rd(pScrn, reg) & mask) | data);
2151 static bool init_macro(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2153 /* INIT_MACRO opcode: 0x6F ('o')
2155 * offset (8 bit): opcode
2156 * offset + 1 (8 bit): macro number
2158 * Look up macro index "macro number" in the macro index table.
2159 * The macro index table entry has 1 byte for the index in the macro table,
2160 * and 1 byte for the number of times to repeat the macro.
2161 * The macro table entry has 4 bytes for the register address and
2162 * 4 bytes for the value to write to that register
2165 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2166 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2167 uint8_t macro_tbl_idx = bios->data[tmp];
2168 uint8_t count = bios->data[tmp + 1];
2172 if (!iexec->execute)
2175 if (DEBUGLEVEL >= 6)
2176 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2177 "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, Count: 0x%02X\n",
2178 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2180 for (i = 0; i < count; i++) {
2181 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2183 reg = le32_to_cpu(*((uint32_t *)(&bios->data[macroentryptr])));
2184 data = le32_to_cpu(*((uint32_t *)(&bios->data[macroentryptr + 4])));
2186 nv32_wr(pScrn, reg, data);
2192 static bool init_done(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2194 /* INIT_DONE opcode: 0x71 ('q')
2196 * offset (8 bit): opcode
2198 * End the current script
2201 /* mild retval abuse to stop parsing this table */
2205 static bool init_resume(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2207 /* INIT_RESUME opcode: 0x72 ('r')
2209 * offset (8 bit): opcode
2211 * End the current execute / no-execute condition
2217 iexec->execute = true;
2218 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2219 "0x%04X: ---- EXECUTING FOLLOWING COMMANDS ----\n", offset);
2225 static bool init_ram_condition2(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
2227 /* INIT_RAM_CONDITION2 opcode: 0x73
2229 * offset (8 bit): opcode
2230 * offset + 1 (8 bit): and mask
2231 * offset + 2 (8 bit): cmpval
2233 * Test if (NV_EXTDEV_BOOT & and mask) matches cmpval
2235 NVPtr pNv = NVPTR(pScrn);
2236 CARD32 and = *((CARD32 *) (&bios->data[offset + 1]));
2237 CARD32 cmpval = *((CARD32 *) (&bios->data[offset + 5]));
2240 if (iexec->execute) {
2241 data=(nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT))∧
2243 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2244 "0x%04X: CHECKING IF REGVAL: 0x%08X equals COND: 0x%08X\n",
2245 offset, data, cmpval);
2247 if (data == cmpval) {
2248 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2249 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n",
2252 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
2253 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2254 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
2255 iexec->execute = false;
2262 static bool init_time(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2264 /* INIT_TIME opcode: 0x74 ('t')
2266 * offset (8 bit): opcode
2267 * offset + 1 (16 bit): time
2269 * Sleep for "time" microseconds.
2272 uint16_t time = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
2274 if (!iexec->execute)
2277 if (DEBUGLEVEL >= 6)
2278 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2279 "0x%04X: Sleeping for 0x%04X microseconds\n", offset, time);
2286 static bool init_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2288 /* INIT_CONDITION opcode: 0x75 ('u')
2290 * offset (8 bit): opcode
2291 * offset + 1 (8 bit): condition number
2293 * Check condition "condition number" in the condition table.
2294 * The condition table entry has 4 bytes for the address of the
2295 * register to check, 4 bytes for a mask and 4 for a test value.
2296 * If condition not met skip subsequent opcodes until condition is
2297 * inverted (INIT_NOT), or we hit INIT_RESUME
2300 uint8_t cond = bios->data[offset + 1];
2301 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
2302 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[condptr])));
2303 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 4])));
2304 uint32_t cmpval = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 8])));
2307 if (!iexec->execute)
2310 if (DEBUGLEVEL >= 6)
2311 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2312 "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X, Cmpval: 0x%08X\n",
2313 offset, cond, reg, mask, cmpval);
2315 data = nv32_rd(pScrn, reg) & mask;
2317 if (DEBUGLEVEL >= 6)
2318 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2319 "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2320 offset, data, cmpval);
2322 if (data == cmpval) {
2323 if (DEBUGLEVEL >= 6)
2324 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2325 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n", offset);
2327 if (DEBUGLEVEL >= 6)
2328 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2329 "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
2330 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2331 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
2332 iexec->execute = false;
2338 static bool init_index_io(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2340 /* INIT_INDEX_IO opcode: 0x78 ('x')
2342 * offset (8 bit): opcode
2343 * offset + 1 (16 bit): CRTC port
2344 * offset + 3 (8 bit): CRTC index
2345 * offset + 4 (8 bit): mask
2346 * offset + 5 (8 bit): data
2348 * Read value at index "CRTC index" on "CRTC port", AND with "mask", OR with "data", write-back
2351 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
2352 uint8_t crtcindex = bios->data[offset + 3];
2353 uint8_t mask = bios->data[offset + 4];
2354 uint8_t data = bios->data[offset + 5];
2357 if (!iexec->execute)
2360 if (DEBUGLEVEL >= 6)
2361 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2362 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
2363 offset, crtcport, crtcindex, mask, data);
2365 value = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) | data;
2366 nv_idx_port_wr(pScrn, crtcport, crtcindex, value);
2371 static bool init_pll(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2373 /* INIT_PLL opcode: 0x79 ('y')
2375 * offset (8 bit): opcode
2376 * offset + 1 (32 bit): register
2377 * offset + 5 (16 bit): freq
2379 * Set PLL register "register" to coefficients for frequency (10kHz) "freq"
2382 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2383 uint16_t freq = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 5])));
2385 if (!iexec->execute)
2388 if (DEBUGLEVEL >= 6)
2389 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2390 "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n",
2393 setPLL(pScrn, bios, reg, freq * 10);
2398 static bool init_zm_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2400 /* INIT_ZM_REG opcode: 0x7A ('z')
2402 * offset (8 bit): opcode
2403 * offset + 1 (32 bit): register
2404 * offset + 5 (32 bit): value
2406 * Assign "value" to "register"
2409 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2410 uint32_t value = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
2412 if (!iexec->execute)
2415 nv32_wr(pScrn, reg, value);
2420 static bool init_8e(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2422 /* INIT_8E opcode: 0x8E ('')
2424 * offset (8 bit): opcode
2426 * The purpose of this opcode is unclear (being for nv50 cards), and
2427 * the literal functionality can be seen in the code below.
2429 * A brief synopsis is that for each entry in a table pointed to by the
2430 * DCB table header, depending on the settings of various bits, various
2431 * other bits in registers 0xe100, 0xe104, and 0xe108, are set or
2435 uint16_t dcbptr = le16_to_cpu(*(uint16_t *)&bios->data[0x36]);
2437 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2438 "No Display Configuration Block pointer found\n");
2441 if (bios->data[dcbptr] != 0x40) {
2442 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2443 "DCB table not version 4.0\n");
2446 uint16_t init8etblptr = le16_to_cpu(*(uint16_t *)&bios->data[dcbptr + 10]);
2447 if (!init8etblptr) {
2448 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
2449 "Invalid pointer to INIT_8E table\n");
2452 uint8_t headerlen = bios->data[init8etblptr + 1];
2453 uint8_t entries = bios->data[init8etblptr + 2];
2454 uint8_t recordlen = bios->data[init8etblptr + 3];
2457 for (i = 0; i < entries; i++) {
2458 uint32_t entry = le32_to_cpu(*(uint32_t *)&bios->data[init8etblptr + headerlen + recordlen * i]);
2459 int shift = (entry & 0x1f) * 4;
2461 uint32_t reg = 0xe104;
2464 if ((entry & 0xff00) == 0xff00)
2473 mask = ~(3 << shift);
2474 if (entry & (1 << 24))
2475 data = (entry >> 21);
2477 data = (entry >> 19);
2478 data = ((data & 3) ^ 2) << shift;
2480 if (DEBUGLEVEL >= 6)
2481 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2482 "0x%04X: Entry: 0x%08X, Reg: 0x%08X, Shift: 0x%02X, Mask: 0x%08X, Data: 0x%08X\n",
2483 offset, entry, reg, shift, mask, data);
2485 nv32_wr(pScrn, reg, (nv32_rd(pScrn, reg) & mask) | data);
2488 shift = entry & 0x1f;
2490 mask = ~(1 << 16 | 1);
2491 mask = mask << shift | mask >> (32 - shift);
2493 if ((entry & (3 << 25)) == (1 << 25))
2495 if ((entry & (3 << 25)) == (2 << 25))
2499 if (DEBUGLEVEL >= 6)
2500 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2501 "0x%04X: Entry: 0x%08X, Reg: 0x%08X, Shift: 0x%02X, Mask: 0x%08X, Data: 0x%08X\n",
2502 offset, entry, reg, shift, mask, data);
2504 nv32_wr(pScrn, reg, (nv32_rd(pScrn, reg) & mask) | data);
2510 /* hack to avoid moving the itbl_entry array before this function */
2511 int init_ram_restrict_zm_reg_group_blocklen = 0;
2513 static bool init_ram_restrict_zm_reg_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2515 /* INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
2517 * offset (8 bit): opcode
2518 * offset + 1 (32 bit): reg
2519 * offset + 5 (8 bit): regincrement
2520 * offset + 6 (8 bit): count
2521 * offset + 7 (32 bit): value 1,1
2524 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2525 * ram_restrict_table_ptr. The value read from here is 'n', and
2526 * "value 1,n" gets written to "reg". This repeats "count" times and on
2527 * each iteration 'm', "reg" increases by "regincrement" and
2528 * "value m,n" is used. The extent of n is limited by a number read
2529 * from the 'M' BIT table, herein called "blocklen"
2532 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2533 uint8_t regincrement = bios->data[offset + 5];
2534 uint8_t count = bios->data[offset + 6];
2535 uint32_t strap_ramcfg, data;
2540 /* previously set by 'M' BIT table */
2541 blocklen = init_ram_restrict_zm_reg_group_blocklen;
2543 if (!iexec->execute)
2547 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2548 "0x%04X: Zero block length - has the M table been parsed?\n", offset);
2552 strap_ramcfg = (nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
2553 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
2555 if (DEBUGLEVEL >= 6)
2556 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2557 "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
2558 offset, reg, regincrement, count, strap_ramcfg, index);
2560 for (i = 0; i < count; i++) {
2561 data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7 + index * 4 + blocklen * i])));
2563 nv32_wr(pScrn, reg, data);
2565 reg += regincrement;
2571 static bool init_copy_zm_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2573 /* INIT_COPY_ZM_REG opcode: 0x90 ('')
2575 * offset (8 bit): opcode
2576 * offset + 1 (32 bit): src reg
2577 * offset + 5 (32 bit): dst reg
2579 * Put contents of "src reg" into "dst reg"
2582 uint32_t srcreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2583 uint32_t dstreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
2585 if (!iexec->execute)
2588 nv32_wr(pScrn, dstreg, nv32_rd(pScrn, srcreg));
2593 static bool init_zm_reg_group_addr_latched(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2595 /* INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
2597 * offset (8 bit): opcode
2598 * offset + 1 (32 bit): dst reg
2599 * offset + 5 (8 bit): count
2600 * offset + 6 (32 bit): data 1
2603 * For each of "count" values write "data n" to "dst reg"
2606 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2607 uint8_t count = bios->data[offset + 5];
2610 if (!iexec->execute)
2613 for (i = 0; i < count; i++) {
2614 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 6 + 4 * i])));
2615 nv32_wr(pScrn, reg, data);
2621 static bool init_reserved(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2623 /* INIT_RESERVED opcode: 0x92 ('')
2625 * offset (8 bit): opcode
2627 * Seemingly does nothing
2633 static init_tbl_entry_t itbl_entry[] = {
2634 /* command name , id , length , offset , mult , command handler */
2635 // { "INIT_PROG" , 0x31, 15 , 10 , 4 , init_prog },
2636 { "INIT_IO_RESTRICT_PROG" , 0x32, 11 , 6 , 4 , init_io_restrict_prog },
2637 { "INIT_REPEAT" , 0x33, 2 , 0 , 0 , init_repeat },
2638 { "INIT_IO_RESTRICT_PLL" , 0x34, 12 , 7 , 2 , init_io_restrict_pll },
2639 { "INIT_END_REPEAT" , 0x36, 1 , 0 , 0 , init_end_repeat },
2640 { "INIT_COPY" , 0x37, 11 , 0 , 0 , init_copy },
2641 { "INIT_NOT" , 0x38, 1 , 0 , 0 , init_not },
2642 { "INIT_IO_FLAG_CONDITION" , 0x39, 2 , 0 , 0 , init_io_flag_condition },
2643 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, 18 , 17 , 2 , init_idx_addr_latched },
2644 { "INIT_IO_RESTRICT_PLL2" , 0x4A, 11 , 6 , 4 , init_io_restrict_pll2 },
2645 { "INIT_PLL2" , 0x4B, 9 , 0 , 0 , init_pll2 },
2646 /* { "INIT_I2C_BYTE" , 0x4C, x , x , x , init_i2c_byte }, */
2647 /* { "INIT_ZM_I2C_BYTE" , 0x4D, x , x , x , init_zm_i2c_byte }, */
2648 /* { "INIT_ZM_I2C" , 0x4E, x , x , x , init_zm_i2c }, */
2649 { "INIT_TMDS" , 0x4F, 5 , 0 , 0 , init_tmds },
2650 { "INIT_ZM_TMDS_GROUP" , 0x50, 3 , 2 , 2 , init_zm_tmds_group },
2651 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, 5 , 4 , 1 , init_cr_idx_adr_latch },
2652 { "INIT_CR" , 0x52, 4 , 0 , 0 , init_cr },
2653 { "INIT_ZM_CR" , 0x53, 3 , 0 , 0 , init_zm_cr },
2654 { "INIT_ZM_CR_GROUP" , 0x54, 2 , 1 , 2 , init_zm_cr_group },
2655 { "INIT_CONDITION_TIME" , 0x56, 3 , 0 , 0 , init_condition_time },
2656 { "INIT_ZM_REG_SEQUENCE" , 0x58, 6 , 5 , 4 , init_zm_reg_sequence },
2657 // { "INIT_INDIRECT_REG" , 0x5A, 7 , 0 , 0 , init_indirect_reg },
2658 { "INIT_SUB_DIRECT" , 0x5B, 3 , 0 , 0 , init_sub_direct },
2659 { "INIT_COPY_NV_REG" , 0x5F, 22 , 0 , 0 , init_copy_nv_reg },
2660 { "INIT_ZM_INDEX_IO" , 0x62, 5 , 0 , 0 , init_zm_index_io },
2661 { "INIT_COMPUTE_MEM" , 0x63, 1 , 0 , 0 , init_compute_mem },
2662 { "INIT_RESET" , 0x65, 13 , 0 , 0 , init_reset },
2663 { "INIT_CONFIGURE_MEM" , 0x66, 1 , 0 , 0 , init_configure_mem },
2664 { "INIT_CONFIGURE_CLK" , 0x67, 1 , 0 , 0 , init_configure_clk },
2665 { "INIT_CONFIGURE_PREINIT" , 0x68, 1 , 0 , 0 , init_configure_preinit },
2666 { "INIT_IO" , 0x69, 5 , 0 , 0 , init_io },
2667 { "INIT_SUB" , 0x6B, 2 , 0 , 0 , init_sub },
2668 { "INIT_RAM_CONDITION" , 0x6D, 3 , 0 , 0 , init_ram_condition },
2669 { "INIT_NV_REG" , 0x6E, 13 , 0 , 0 , init_nv_reg },
2670 { "INIT_MACRO" , 0x6F, 2 , 0 , 0 , init_macro },
2671 { "INIT_DONE" , 0x71, 1 , 0 , 0 , init_done },
2672 { "INIT_RESUME" , 0x72, 1 , 0 , 0 , init_resume },
2673 // { "INIT_RAM_CONDITION2" , 0x73, 9 , 0 , 0 , init_ram_condition2 },
2674 { "INIT_TIME" , 0x74, 3 , 0 , 0 , init_time },
2675 { "INIT_CONDITION" , 0x75, 2 , 0 , 0 , init_condition },
2676 /* { "INIT_IO_CONDITION" , 0x76, x , x , x , init_io_condition }, */
2677 { "INIT_INDEX_IO" , 0x78, 6 , 0 , 0 , init_index_io },
2678 { "INIT_PLL" , 0x79, 7 , 0 , 0 , init_pll },
2679 { "INIT_ZM_REG" , 0x7A, 9 , 0 , 0 , init_zm_reg },
2680 { "INIT_8E" , 0x8E, 1 , 0 , 0 , init_8e },
2681 /* INIT_RAM_RESTRICT_ZM_REG_GROUP's mult is loaded by M table in BIT */
2682 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, 7 , 6 , 0 , init_ram_restrict_zm_reg_group },
2683 { "INIT_COPY_ZM_REG" , 0x90, 9 , 0 , 0 , init_copy_zm_reg },
2684 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, 6 , 5 , 4 , init_zm_reg_group_addr_latched },
2685 { "INIT_RESERVED" , 0x92, 1 , 0 , 0 , init_reserved },
2686 { 0 , 0 , 0 , 0 , 0 , 0 }
2689 static unsigned int get_init_table_entry_length(bios_t *bios, unsigned int offset, int i)
2691 /* Calculates the length of a given init table entry. */
2692 return itbl_entry[i].length + bios->data[offset + itbl_entry[i].length_offset]*itbl_entry[i].length_multiplier;
2695 static void parse_init_table(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset, init_exec_t *iexec)
2697 /* Parses all commands in a init table. */
2699 /* We start out executing all commands found in the
2700 * init table. Some op codes may change the status
2701 * of this variable to SKIP, which will cause
2702 * the following op codes to perform no operation until
2703 * the value is changed back to EXECUTE.
2709 /* Loop until INIT_DONE causes us to break out of the loop
2710 * (or until offset > bios length just in case... )
2711 * (and no more than 10000 iterations just in case... ) */
2712 while ((offset < bios->length) && (count++ < 10000)) {
2713 id = bios->data[offset];
2715 /* Find matching id in itbl_entry */
2716 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
2719 if (itbl_entry[i].name) {
2720 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: [ (0x%02X) - %s ]\n",
2721 offset, itbl_entry[i].id, itbl_entry[i].name);
2723 /* execute eventual command handler */
2724 if (itbl_entry[i].handler)
2725 if (!(*itbl_entry[i].handler)(pScrn, bios, offset, iexec))
2728 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2729 "0x%04X: Init table command not found: 0x%02X\n", offset, id);
2733 /* Add the offset of the current command including all data
2734 * of that command. The offset will then be pointing on the
2737 offset += get_init_table_entry_length(bios, offset, i);
2741 static void parse_init_tables(ScrnInfoPtr pScrn, bios_t *bios)
2743 /* Loops and calls parse_init_table() for each present table. */
2747 init_exec_t iexec = {true, false};
2749 while ((table = le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + i]))))) {
2750 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2751 "0x%04X: Parsing init table %d\n", table, i / 2);
2752 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2753 "0x%04X: ------ EXECUTING FOLLOWING COMMANDS ------\n", table);
2755 parse_init_table(pScrn, bios, table, &iexec);
2760 static void link_head_and_output(ScrnInfoPtr pScrn, int head, int dcb_entry)
2762 /* The BIOS scripts don't do this for us, sadly
2763 * Luckily we do know the values ;-)
2765 * head < 0 indicates we wish to force a setting with the overrideval
2766 * (for VT restore etc.)
2769 NVPtr pNv = NVPTR(pScrn);
2770 struct dcb_entry *dcbent = &pNv->dcb_table.entry[dcb_entry];
2771 int ramdac = (dcbent->or & OUTPUT_C) >> 2;
2772 uint8_t tmds04 = 0x80;
2777 if (dcbent->type == OUTPUT_LVDS)
2780 nv_dcb_write_tmds(pNv, dcb_entry, 0, 0x04, tmds04);
2782 if (dcbent->type == OUTPUT_LVDS && pNv->VBIOS.fp.dual_link)
2783 nv_dcb_write_tmds(pNv, dcb_entry, 1, 0x04, tmds04 ^ 0x08);
2786 static uint16_t clkcmptable(bios_t *bios, uint16_t clktable, int pxclk)
2788 int compare_record_len, i = 0;
2789 uint16_t compareclk, scriptptr = 0;
2791 if (bios->major_version < 5) /* pre BIT */
2792 compare_record_len = 3;
2794 compare_record_len = 4;
2797 compareclk = le16_to_cpu(*((uint16_t *)&bios->data[clktable + compare_record_len * i]));
2798 if (pxclk >= compareclk * 10) {
2799 if (bios->major_version < 5) {
2800 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
2801 scriptptr = le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + tmdssub * 2])));
2803 scriptptr = le16_to_cpu(*((uint16_t *)&bios->data[clktable + 2 + compare_record_len * i]));
2807 } while (compareclk);
2812 static void rundigitaloutscript(ScrnInfoPtr pScrn, uint16_t scriptptr, int head, int dcb_entry)
2814 bios_t *bios = &NVPTR(pScrn)->VBIOS;
2815 init_exec_t iexec = {true, false};
2817 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: Parsing digital output script table\n", scriptptr);
2818 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_OWNER,
2819 head ? NV_VGA_CRTCX_OWNER_HEADB : NV_VGA_CRTCX_OWNER_HEADA);
2820 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_57, 0);
2821 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_58, dcb_entry);
2822 parse_init_table(pScrn, bios, scriptptr, &iexec);
2824 link_head_and_output(pScrn, head, dcb_entry);
2827 static void call_lvds_manufacturer_script(ScrnInfoPtr pScrn, int head, int dcb_entry, enum LVDS_script script)
2829 NVPtr pNv = NVPTR(pScrn);
2830 bios_t *bios = &pNv->VBIOS;
2831 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && pNv->dcb_table.entry[dcb_entry].or & OUTPUT_C ? 1 : 0);
2832 uint16_t scriptofs = le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + sub * 2])));
2834 if (!bios->fp.xlated_entry || !sub || !scriptofs)
2837 rundigitaloutscript(pScrn, scriptofs, head, dcb_entry);
2839 if (script == LVDS_PANEL_OFF)
2840 /* off-on delay in ms */
2841 usleep(le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.xlated_entry + 7]));
2843 /* Powerbook specific quirk */
2844 if (script == LVDS_RESET && ((pNv->Chipset & 0xffff) == 0x0179 || (pNv->Chipset & 0xffff) == 0x0329))
2845 nv_dcb_write_tmds(pNv, dcb_entry, 0, 0x02, 0x72);
2849 static void run_lvds_table(ScrnInfoPtr pScrn, int head, int dcb_entry, enum LVDS_script script, int pxclk)
2851 /* The BIT LVDS table's header has the information to setup the
2852 * necessary registers. Following the standard 4 byte header are:
2853 * A bitmask byte and a dual-link transition pxclk value for use in
2854 * selecting the init script when not using straps; 4 script pointers
2855 * for panel power, selected by output and on/off; and 8 table pointers
2856 * for panel init, the needed one determined by output, and bits in the
2857 * conf byte. These tables are similar to the TMDS tables, consisting
2858 * of a list of pxclks and script pointers.
2861 NVPtr pNv = NVPTR(pScrn);
2862 bios_t *bios = &pNv->VBIOS;
2863 unsigned int outputset = (pNv->dcb_table.entry[dcb_entry].or == 4) ? 1 : 0;
2864 uint16_t scriptptr = 0, clktable;
2865 uint8_t clktableptr = 0;
2867 /* for now we assume version 3.0 table - g80 support will need some changes */
2872 case LVDS_BACKLIGHT_ON:
2874 scriptptr = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
2876 case LVDS_BACKLIGHT_OFF:
2877 case LVDS_PANEL_OFF:
2878 scriptptr = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
2881 if (pNv->dcb_table.entry[dcb_entry].lvdsconf.use_straps_for_mode) {
2882 if (bios->fp.dual_link)
2884 if (bios->fp.BITbit1)
2887 uint8_t fallback = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
2888 int fallbackcmpval = (pNv->dcb_table.entry[dcb_entry].or == 4) ? 4 : 1;
2890 if (bios->fp.dual_link) {
2892 fallbackcmpval *= 2;
2894 if (fallbackcmpval & fallback)
2898 /* adding outputset * 8 may not be correct */
2899 clktable = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 15 + clktableptr * 2 + outputset * 8]);
2901 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Pixel clock comparison table not found\n");
2904 scriptptr = clkcmptable(bios, clktable, pxclk);
2908 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "LVDS output init script not found\n");
2911 rundigitaloutscript(pScrn, scriptptr, head, dcb_entry);
2914 void call_lvds_script(ScrnInfoPtr pScrn, int head, int dcb_entry, enum LVDS_script script, int pxclk)
2916 /* LVDS operations are multiplexed in an effort to present a single API
2917 * which works with two vastly differing underlying structures.
2918 * This acts as the demux
2921 bios_t *bios = &NVPTR(pScrn)->VBIOS;
2922 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
2923 uint32_t sel_clk_binding;
2924 static int last_invoc = 0;
2926 if (last_invoc == (script << 1 | head) || !lvds_ver)
2929 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
2930 call_lvds_script(pScrn, head, dcb_entry, LVDS_RESET, pxclk);
2931 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
2932 call_lvds_script(pScrn, head, dcb_entry, LVDS_PANEL_OFF, pxclk);
2934 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Calling LVDS script %d:\n", script);
2936 /* don't let script change pll->head binding */
2937 sel_clk_binding = nv32_rd(pScrn, NV_RAMDAC_SEL_CLK) & 0x50000;
2939 if (lvds_ver < 0x30)
2940 call_lvds_manufacturer_script(pScrn, head, dcb_entry, script);
2942 run_lvds_table(pScrn, head, dcb_entry, script, pxclk);
2944 last_invoc = (script << 1 | head);
2946 nv32_wr(pScrn, NV_RAMDAC_SEL_CLK, (nv32_rd(pScrn, NV_RAMDAC_SEL_CLK) & ~0x50000) | sel_clk_binding);
2947 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
2948 nv32_wr(pScrn, NV_PBUS_POWERCTRL_2, 0);
2952 uint16_t fptablepointer;
2953 uint16_t fpxlatetableptr;
2954 uint16_t fpxlatemanufacturertableptr;
2958 static void parse_fp_mode_table(ScrnInfoPtr pScrn, bios_t *bios, struct fppointers *fpp)
2961 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
2964 DisplayModePtr mode;
2966 if (fpp->fptablepointer == 0x0 || fpp->fpxlatetableptr == 0x0) {
2967 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2968 "Pointers to flat panel table invalid\n");
2972 fptable = &bios->data[fpp->fptablepointer];
2974 fptable_ver = fptable[0];
2976 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2977 "Found flat panel mode table revision %d.%d\n",
2978 fptable_ver >> 4, fptable_ver & 0xf);
2980 switch (fptable_ver) {
2981 /* BMP version 0x5.0x11 BIOSen have version 1 like tables, but no version field,
2982 * and miss one of the spread spectrum/PWM bytes.
2983 * This could affect early GF2Go parts (not seen any appropriate ROMs though).
2984 * Here we assume that a version of 0x05 matches this case (combining with a
2985 * BMP version check would be better), as the common case for the panel type
2986 * field is 0x0005, and that is in fact what we are reading the first byte of. */
2987 case 0x05: /* some NV10, 11, 15, 16 */
2991 case 0x10: /* some NV15/16, and NV11+ */
2995 case 0x20: /* NV40+ */
2996 headerlen = fptable[1];
2997 recordlen = fptable[2];
2998 fpentries = fptable[3];
2999 /* fptable[4] is the minimum RAMDAC_FP_HCRTC->RAMDAC_FP_HSYNC_START gap.
3000 * Only seen 0x4b (=75) which is what is used in nv_crtc.c anyway,
3001 * so we're not using this table value for now
3006 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3007 "FP Table revision not currently supported\n");
3011 fpindex = bios->data[fpp->fpxlatetableptr + bios->fp.strapping * fpp->xlatwidth];
3012 bios->fp.strapping |= fpindex << 4;
3013 if (fpindex > fpentries) {
3014 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3015 "Bad flat panel table index\n");
3019 /* reserved values - means that ddc or hard coded edid should be used */
3020 if (bios->fp.strapping == 0xff) {
3021 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Ignoring FP table\n");
3025 if (!(mode = xcalloc(1, sizeof(DisplayModeRec))))
3028 modeofs = headerlen + recordlen * fpindex + ofs;
3029 mode->Clock = le16_to_cpu(*(uint16_t *)&fptable[modeofs]) * 10;
3030 mode->HDisplay = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 4] + 1);
3031 mode->HSyncStart = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 10] + 1);
3032 mode->HSyncEnd = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 12] + 1);
3033 mode->HTotal = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 14] + 1);
3034 mode->VDisplay = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 18] + 1);
3035 mode->VSyncStart = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 24] + 1);
3036 mode->VSyncEnd = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 26] + 1);
3037 mode->VTotal = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 28] + 1);
3038 mode->Flags |= (fptable[modeofs + 30] & 0x10) ? V_PHSYNC : V_NHSYNC;
3039 mode->Flags |= (fptable[modeofs + 30] & 0x1) ? V_PVSYNC : V_NVSYNC;
3042 * bytes 1-2 are "panel type", including bits on whether Colour/mono, single/dual link, and type (TFT etc.)
3043 * bytes 3-6 are bits per colour in RGBX
3046 * 13-14 is HValid Start
3047 * 15-16 is HValid End
3048 * bytes 38-39 relate to spread spectrum settings
3049 * bytes 40-43 are something to do with PWM */
3051 mode->prev = mode->next = NULL;
3052 mode->status = MODE_OK;
3053 mode->type = M_T_DRIVER | M_T_PREFERRED;
3054 xf86SetModeDefaultName(mode);
3056 // if (XF86_CRTC_CONFIG_PTR(pScrn)->debug_modes) {
3057 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3058 "Found flat panel mode in BIOS tables:\n");
3059 xf86PrintModeline(pScrn->scrnIndex, mode);
3062 bios->fp.native_mode = mode;
3065 static void parse_lvds_manufacturer_table_init(ScrnInfoPtr pScrn, bios_t *bios, struct fppointers *fpp)
3067 /* The LVDS table changed considerably with BIT bioses. Previously
3068 * there was a header of version and record length, followed by several
3069 * records, indexed by a seperate xlat table, indexed in turn by the fp
3070 * strap in EXTDEV_BOOT. Each record had a config byte, followed by 6
3071 * script numbers for use by INIT_SUB which controlled panel init and
3072 * power, and finally a dword of ms to sleep between power off and on
3075 * The BIT LVDS table has the typical BIT table header: version byte,
3076 * header length byte, record length byte, and a byte for the maximum
3077 * number of records that can be held in the table. At byte 5 in the
3078 * header is the dual-link transition pxclk (in 10s kHz) - if straps
3079 * are not being used for the panel, this specifies the frequency at
3080 * which modes should be set up in the dual link style.
3082 * The table following the header serves as an integrated config and
3083 * xlat table: the records in the table are indexed by the FP strap
3084 * nibble in EXTDEV_BOOT, and each record has two bytes - the first as
3085 * a config byte, the second for indexing the fp mode table pointed to
3086 * by the BIT 'D' table
3089 unsigned int lvdsmanufacturerindex = 0;
3090 uint8_t lvds_ver, headerlen, recordlen;
3093 bios->fp.strapping = (nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
3095 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
3096 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3097 "Pointer to LVDS manufacturer table invalid\n");
3101 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3103 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3104 "Found LVDS manufacturer table revision %d.%d\n",
3105 lvds_ver >> 4, lvds_ver & 0xf);
3108 case 0x0a: /* pre NV40 */
3109 lvdsmanufacturerindex = bios->data[fpp->fpxlatemanufacturertableptr + bios->fp.strapping];
3111 /* adjust some things if straps are invalid (implies the panel has EDID) */
3112 if (bios->fp.strapping == 0xf) {
3113 bios->data[fpp->fpxlatetableptr + 0xf] = 0xf;
3114 lvdsmanufacturerindex = bios->fp.if_is_24bit ? 2 : 0;
3115 /* nvidia set the high nibble of (cr57=f, cr58) to
3116 * lvdsmanufacturerindex in this case; we don't */
3120 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3123 case 0x30: /* NV4x */
3124 lvdsmanufacturerindex = bios->fp.strapping;
3125 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3126 if (headerlen < 0x1f) {
3127 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3128 "LVDS table header not understood\n");
3131 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3133 case 0x40: /* It changed again with gf8 :o( */
3135 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3136 "LVDS table revision not currently supported\n");
3140 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + headerlen + recordlen * lvdsmanufacturerindex;
3143 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1;
3144 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
3145 bios->fp.dual_link = bios->data[lvdsofs] & 4;
3146 bios->fp.link_c_increment = bios->data[lvdsofs] & 8;
3147 bios->fp.if_is_24bit = bios->data[lvdsofs] & 16;
3148 call_lvds_script(pScrn, 0, 0, LVDS_INIT, 0);
3151 /* My money would be on there being a 24 bit interface bit in this table,
3152 * but I have no example of a laptop bios with a 24 bit panel to confirm that.
3153 * Hence we shout loudly if any bit other than bit 0 is set (I've not even
3156 if (bios->data[lvdsofs] > 1)
3157 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3158 "You have a very unusual laptop display; please report it\n");
3159 /* no sign of the "power off for reset" or "reset for panel on" bits, but it's safer to assume we should */
3160 bios->fp.power_off_for_reset = true;
3161 bios->fp.reset_after_pclk_change = true;
3162 bios->fp.dual_link = bios->data[lvdsofs] & 1;
3163 bios->fp.BITbit1 = bios->data[lvdsofs] & 2;
3164 bios->fp.duallink_transition_clk = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
3165 fpp->fpxlatetableptr = bios->fp.lvdsmanufacturerpointer + headerlen + 1;
3166 fpp->xlatwidth = recordlen;
3171 void setup_edid_dual_link_lvds(ScrnInfoPtr pScrn, int pxclk)
3173 /* Due to the stage at which DDC is used, the EDID res for a panel isn't
3174 * known at init, so the dual link flag (which tests against a
3175 * transition frequency) cannot be set until later
3177 * Here the flag and the LVDS script set pointer are updated (only once
3178 * per driver incarnation)
3180 * This function should *not* be called in the case where the panel
3181 * config is set by the straps
3184 bios_t *bios = &NVPTR(pScrn)->VBIOS;
3185 static bool dual_link_correction_done = false;
3187 if ((bios->fp.strapping & 0xf) != 0xf || dual_link_correction_done)
3189 dual_link_correction_done = true;
3191 if (pxclk >= bios->fp.duallink_transition_clk) {
3192 bios->fp.dual_link = true;
3193 /* move to (entry + 1) for BMP bioses (BIT doesn't use this) */
3194 bios->fp.xlated_entry += bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3196 bios->fp.dual_link = false;
3199 void run_tmds_table(ScrnInfoPtr pScrn, int dcb_entry, int head, int pxclk)
3201 /* the dcb_entry parameter is the index of the appropriate DCB entry
3202 * the pxclk parameter is in kHz
3204 * This runs the TMDS regs setting code found on BIT bios cards
3206 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
3207 * ffs(or) == 3, use the second.
3210 NVPtr pNv = NVPTR(pScrn);
3211 bios_t *bios = &pNv->VBIOS;
3212 uint16_t clktable = 0, scriptptr;
3213 uint32_t sel_clk_binding;
3215 if (pNv->dcb_table.entry[dcb_entry].location) /* off chip */
3218 switch (ffs(pNv->dcb_table.entry[dcb_entry].or)) {
3220 clktable = bios->tmds.output0_script_ptr;
3224 clktable = bios->tmds.output1_script_ptr;
3229 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Pixel clock comparison table not found\n");
3233 scriptptr = clkcmptable(bios, clktable, pxclk);
3236 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "TMDS output init script not found\n");
3240 /* don't let script change pll->head binding */
3241 sel_clk_binding = nv32_rd(pScrn, NV_RAMDAC_SEL_CLK) & 0x50000;
3242 rundigitaloutscript(pScrn, scriptptr, head, dcb_entry);
3243 nv32_wr(pScrn, NV_RAMDAC_SEL_CLK, (nv32_rd(pScrn, NV_RAMDAC_SEL_CLK) & ~0x50000) | sel_clk_binding);
3246 static void parse_bios_version(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset)
3248 /* offset + 0 (8 bits): Micro version
3249 * offset + 1 (8 bits): Minor version
3250 * offset + 2 (8 bits): Chip version
3251 * offset + 3 (8 bits): Major version
3254 bios->major_version = bios->data[offset + 3];
3255 bios->chip_version = bios->data[offset + 2];
3256 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Bios version %02x.%02x.%02x.%02x\n",
3257 bios->data[offset + 3], bios->data[offset + 2],
3258 bios->data[offset + 1], bios->data[offset]);
3261 bool get_pll_limits(ScrnInfoPtr pScrn, uint32_t limit_match, struct pll_lims *pll_lim)
3265 * Version 0x10: NV31
3266 * One byte header (version), one record of 24 bytes
3267 * Version 0x11: NV36 - Not implemented
3268 * Seems to have same record style as 0x10, but 3 records rather than 1
3269 * Version 0x20: Found on Geforce 6 cards
3270 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
3271 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
3272 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record length
3275 bios_t *bios = &NVPTR(pScrn)->VBIOS;
3276 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
3278 uint32_t crystal_strap_mask, crystal_straps;
3280 if (!bios->pll_limit_tbl_ptr) {
3281 if (bios->chip_version >= 0x40 || bios->chip_version == 0x31 || bios->chip_version == 0x36) {
3282 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Pointer to PLL limits table invalid\n");
3286 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
3288 if (DEBUGLEVEL >= 6)
3289 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3290 "Found PLL limits table version 0x%X\n", pll_lim_ver);
3293 crystal_strap_mask = 1 << 6;
3294 /* open coded pNv->twoHeads test */
3295 if (bios->chip_version > 0x10 && bios->chip_version != 0x15 &&
3296 bios->chip_version != 0x1a && bios->chip_version != 0x20)
3297 crystal_strap_mask |= 1 << 22;
3298 crystal_straps = nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) & crystal_strap_mask;
3300 switch (pll_lim_ver) {
3301 /* we use version 0 to indicate a pre limit table bios (single stage pll)
3302 * and load the hard coded limits instead */
3306 case 0x11: /* strictly v0x11 has 3 entries, but the last two don't seem to get used */
3314 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
3315 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
3316 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
3319 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
3320 "PLL limits table revision not currently supported\n");
3324 /* initialize all members to zero */
3325 memset(pll_lim, 0, sizeof(struct pll_lims));
3327 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) {
3328 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex;
3330 pll_lim->vco1.minfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs])));
3331 pll_lim->vco1.maxfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 4])));
3332 pll_lim->vco2.minfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 8])));
3333 pll_lim->vco2.maxfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 12])));
3334 pll_lim->vco1.min_inputfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 16])));
3335 pll_lim->vco2.min_inputfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 20])));
3336 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
3338 /* these values taken from nv31. nv30, nv36 might do better with different ones */
3339 pll_lim->vco1.min_n = 0x1;
3340 pll_lim->vco1.max_n = 0xff;
3341 pll_lim->vco1.min_m = 0x1;
3342 pll_lim->vco1.max_m = 0xd;
3343 pll_lim->vco2.min_n = 0x4;
3344 pll_lim->vco2.max_n = 0x46;
3345 if (bios->chip_version == 0x30)
3346 /* only 5 bits available for N2 on nv30 */
3347 pll_lim->vco2.max_n = 0x1f;
3348 if (bios->chip_version == 0x31)
3349 /* on nv31, N2 is compared to maxN2 (0x46) and maxM2 (0x4),
3350 * so set maxN2 to 0x4 and save a comparison
3352 pll_lim->vco2.max_n = 0x4;
3353 pll_lim->vco2.min_m = 0x1;
3354 pll_lim->vco2.max_m = 0x4;
3355 } else if (pll_lim_ver) { /* ver 0x20, 0x21 */
3356 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
3357 uint32_t reg = 0; /* default match */
3360 /* first entry is default match, if nothing better. warn if reg field nonzero */
3361 if (le32_to_cpu(*((uint32_t *)&bios->data[plloffs])))
3362 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
3363 "Default PLL limit entry has non-zero register field\n");
3365 if (limit_match > MAX_PLL_TYPES)
3366 /* we've been passed a reg as the match */
3368 else /* limit match is a pll type */
3369 for (i = 1; i < entries && !reg; i++) {
3370 uint32_t cmpreg = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + recordlen * i])));
3372 if (limit_match == VPLL1 && (cmpreg == NV_RAMDAC_VPLL || cmpreg == 0x4010))
3374 if (limit_match == VPLL2 && (cmpreg == NV_RAMDAC_VPLL2 || cmpreg == 0x4018))
3378 for (i = 1; i < entries; i++)
3379 if (le32_to_cpu(*((uint32_t *)&bios->data[plloffs + recordlen * i])) == reg) {
3384 plloffs += recordlen * pllindex;
3386 if (DEBUGLEVEL >= 6)
3387 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Loading PLL limits for reg 0x%08x\n",
3388 pllindex ? reg : 0);
3390 /* frequencies are stored in tables in MHz, kHz are more useful, so we convert */
3392 /* What output frequencies can each VCO generate? */
3393 pll_lim->vco1.minfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 4]))) * 1000;
3394 pll_lim->vco1.maxfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 6]))) * 1000;
3395 pll_lim->vco2.minfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 8]))) * 1000;
3396 pll_lim->vco2.maxfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 10]))) * 1000;
3398 /* What input frequencies do they accept (past the m-divider)? */
3399 pll_lim->vco1.min_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 12]))) * 1000;
3400 pll_lim->vco2.min_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 14]))) * 1000;
3401 pll_lim->vco1.max_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 16]))) * 1000;
3402 pll_lim->vco2.max_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 18]))) * 1000;
3404 /* What values are accepted as multiplier and divider? */
3405 pll_lim->vco1.min_n = bios->data[plloffs + 20];
3406 pll_lim->vco1.max_n = bios->data[plloffs + 21];
3407 pll_lim->vco1.min_m = bios->data[plloffs + 22];
3408 pll_lim->vco1.max_m = bios->data[plloffs + 23];
3409 pll_lim->vco2.min_n = bios->data[plloffs + 24];
3410 pll_lim->vco2.max_n = bios->data[plloffs + 25];
3411 pll_lim->vco2.min_m = bios->data[plloffs + 26];
3412 pll_lim->vco2.max_m = bios->data[plloffs + 27];
3414 pll_lim->unk1c = bios->data[plloffs + 28];
3415 pll_lim->max_log2p_bias = bios->data[plloffs + 29];
3416 pll_lim->log2p_bias = bios->data[plloffs + 30];
3418 if (recordlen > 0x22)
3419 pll_lim->refclk = le32_to_cpu(*((uint32_t *)&bios->data[plloffs + 31]));
3421 /* C51 special not seen elsewhere */
3422 if (bios->chip_version == 0x51 && !pll_lim->refclk) {
3423 uint32_t sel_clk = nv32_rd(pScrn, NV_RAMDAC_SEL_CLK);
3425 if (((limit_match == NV_RAMDAC_VPLL || limit_match == VPLL1) && sel_clk & 0x20) || ((limit_match == NV_RAMDAC_VPLL2 || limit_match == VPLL2) && sel_clk & 0x80)) {
3426 if (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_27) < 0xa3)
3427 pll_lim->refclk = 200000;
3429 pll_lim->refclk = 25000;
3434 /* By now any valid limit table ought to have set a max frequency for
3435 * vco1, so if it's zero it's either a pre limit table bios, or one
3436 * with an empty limit table (seen on nv18)
3438 if (!pll_lim->vco1.maxfreq) {
3439 pll_lim->vco1.minfreq = bios->fminvco;
3440 pll_lim->vco1.maxfreq = bios->fmaxvco;
3441 pll_lim->vco1.min_n = 0x1;
3442 pll_lim->vco1.max_n = 0xff;
3443 pll_lim->vco1.min_m = 0x1;
3444 if (crystal_straps == 0) {
3445 /* nv05 does this, nv11 doesn't, nv10 unknown */
3446 if (bios->chip_version < 0x11)
3447 pll_lim->vco1.min_m = 0x7;
3448 pll_lim->vco1.max_m = 0xd;
3450 if (bios->chip_version < 0x11)
3451 pll_lim->vco1.min_m = 0x8;
3452 pll_lim->vco1.max_m = 0xe;
3454 pll_lim->vco1.min_inputfreq = 0;
3455 pll_lim->vco1.max_inputfreq = INT_MAX;
3458 if (!pll_lim->refclk)
3459 switch (crystal_straps) {
3461 pll_lim->refclk = 13500;
3464 pll_lim->refclk = 14318;
3467 pll_lim->refclk = 27000;
3469 case (1 << 22 | 1 << 6):
3470 pll_lim->refclk = 25000;
3474 #if 0 /* for easy debugging */
3475 ErrorF("pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
3476 ErrorF("pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
3477 ErrorF("pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
3478 ErrorF("pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
3480 ErrorF("pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
3481 ErrorF("pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
3482 ErrorF("pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
3483 ErrorF("pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
3485 ErrorF("pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
3486 ErrorF("pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
3487 ErrorF("pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
3488 ErrorF("pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
3489 ErrorF("pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
3490 ErrorF("pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
3491 ErrorF("pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
3492 ErrorF("pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
3494 ErrorF("pll.unk1c: %d\n", pll_lim->unk1c);
3495 ErrorF("pll.max_log2p_bias: %d\n", pll_lim->max_log2p_bias);
3496 ErrorF("pll.log2p_bias: %d\n", pll_lim->log2p_bias);
3498 ErrorF("pll.refclk: %d\n", pll_lim->refclk);
3504 static int parse_bit_C_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3506 /* offset + 8 (16 bits): PLL limits table pointer
3508 * There's more in here, but that's unknown.
3511 if (bitentry->length < 10) {
3512 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Do not understand BIT C table\n");
3516 bios->pll_limit_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 8])));
3521 static int parse_bit_display_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry, struct fppointers *fpp)
3523 /* Parses the flat panel table segment that the bit entry points to.
3524 * Starting at bitentry->offset:
3526 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte records beginning with a freq
3527 * offset + 2 (16 bits): mode table pointer
3530 if (bitentry->length != 4) {
3531 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Do not understand BIT display table\n");
3535 fpp->fptablepointer = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 2])));
3537 parse_fp_mode_table(pScrn, bios, fpp);
3542 static unsigned int parse_bit_init_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3544 /* Parses the init table segment that the bit entry points to.
3545 * Starting at bitentry->offset:
3547 * offset + 0 (16 bits): init script tables pointer
3548 * offset + 2 (16 bits): macro index table pointer
3549 * offset + 4 (16 bits): macro table pointer
3550 * offset + 6 (16 bits): condition table pointer
3551 * offset + 8 (16 bits): io condition table pointer
3552 * offset + 10 (16 bits): io flag condition table pointer
3553 * offset + 12 (16 bits): init function table pointer
3557 if (bitentry->length < 14) {
3558 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Do not understand init table\n");
3562 bios->init_script_tbls_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
3563 bios->macro_index_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 2])));
3564 bios->macro_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 4])));
3565 bios->condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 6])));
3566 bios->io_condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 8])));
3567 bios->io_flag_condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 10])));
3568 bios->init_function_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 12])));
3573 static int parse_bit_i_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3575 /* BIT 'i' (info?) table
3577 * offset + 0 (32 bits): BIOS version dword (as in B table)
3578 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
3579 * offset + 13 (16 bits): pointer to table containing DAC load detection comparison values
3581 * There's other things in the table, purpose unknown
3584 uint16_t daccmpoffset;
3585 uint8_t dacversion, dacheaderlen;
3587 if (bitentry->length < 6) {
3588 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
3589 "BIT i table not long enough for BIOS version and feature byte\n");
3593 parse_bios_version(pScrn, bios, bitentry->offset);
3595 /* bit 4 seems to indicate a mobile bios, other bits possibly as for BMP feature byte */
3596 bios->feature_byte = bios->data[bitentry->offset + 5];
3598 if (bitentry->length < 15) {
3599 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
3600 "BIT i table not long enough for DAC load detection comparison table\n");
3604 daccmpoffset = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 13])));
3606 /* doesn't exist on g80 */
3610 /* The first value in the table, following the header, is the comparison value
3611 * Purpose of subsequent values unknown -- TV load detection?
3614 dacversion = bios->data[daccmpoffset];
3615 dacheaderlen = bios->data[daccmpoffset + 1];
3617 if (dacversion != 0x00 && dacversion != 0x10) {
3618 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
3619 "DAC load detection comparison table version %d.%d not known\n",
3620 dacversion >> 4, dacversion & 0xf);
3623 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3624 "DAC load detection comparison table version %x found\n", dacversion);
3626 bios->dactestval = le32_to_cpu(*((uint32_t *)(&bios->data[daccmpoffset + dacheaderlen])));
3631 static int parse_bit_lvds_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry, struct fppointers *fpp)
3633 /* Parses the LVDS table segment that the bit entry points to.
3634 * Starting at bitentry->offset:
3636 * offset + 0 (16 bits): LVDS strap xlate table pointer
3639 if (bitentry->length != 2) {
3640 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Do not understand BIT LVDS table\n");
3644 /* no idea if it's still called the LVDS manufacturer table, but the concept's close enough */
3645 bios->fp.lvdsmanufacturerpointer = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
3647 parse_lvds_manufacturer_table_init(pScrn, bios, fpp);
3652 static int parse_bit_M_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3654 /* offset + 2 (8 bits): number of options in an INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
3655 * offset + 3 (16 bits): pointer to strap xlate table for RAM restrict option selection
3657 * There's a bunch of bits in this table other than the RAM restrict
3658 * stuff that we don't use - their use currently unknown
3663 /* Older bios versions don't have a sufficiently long table for what we want */
3664 if (bitentry->length < 0x5)
3667 /* set up multiplier for INIT_RAM_RESTRICT_ZM_REG_GROUP */
3668 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != 0x8f); i++)
3670 itbl_entry[i].length_multiplier = bios->data[bitentry->offset + 2] * 4;
3671 init_ram_restrict_zm_reg_group_blocklen = itbl_entry[i].length_multiplier;
3673 bios->ram_restrict_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 3])));
3678 static int parse_bit_tmds_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3680 /* Parses the pointer to the TMDS table
3682 * Starting at bitentry->offset:
3684 * offset + 0 (16 bits): TMDS table pointer
3686 * The TMDS table is typically found just before the DCB table, with a
3687 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
3690 * At offset +7 is a pointer to a script, which I don't know how to run yet
3691 * At offset +9 is a pointer to another script, likewise
3692 * Offset +11 has a pointer to a table where the first word is a pxclk
3693 * frequency and the second word a pointer to a script, which should be
3694 * run if the comparison pxclk frequency is less than the pxclk desired.
3695 * This repeats for decreasing comparison frequencies
3696 * Offset +13 has a pointer to a similar table
3697 * The selection of table (and possibly +7/+9 script) is dictated by
3698 * "or" from the DCB.
3701 uint16_t tmdstableptr, script1, script2;
3703 if (bitentry->length != 2) {
3704 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Do not understand BIT TMDS table\n");
3708 tmdstableptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
3710 if (tmdstableptr == 0x0) {
3711 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Pointer to TMDS table invalid\n");
3715 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Found TMDS table revision %d.%d\n",
3716 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
3718 /* These two scripts are odd: they don't seem to get run even when they are not stubbed */
3719 script1 = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 7]));
3720 script2 = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 9]));
3721 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
3722 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "TMDS table script pointers not stubbed\n");
3724 bios->tmds.output0_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 11]));
3725 bios->tmds.output1_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 13]));
3730 static void parse_bit_structure(ScrnInfoPtr pScrn, bios_t *bios, const uint16_t bitoffset)
3732 /* parse i first, I next (which needs C & M before it), and L before D */
3733 char parseorder[] = "iCMILDT";
3734 bit_entry_t bitentry;
3736 struct fppointers fpp;
3738 memset(&fpp, 0, sizeof(struct fppointers));
3740 for (i = 0; i < sizeof(parseorder); i++) {
3741 uint16_t offset = bitoffset;
3744 bitentry.id[0] = bios->data[offset];
3745 bitentry.id[1] = bios->data[offset + 1];
3746 bitentry.length = le16_to_cpu(*((uint16_t *)&bios->data[offset + 2]));
3747 bitentry.offset = le16_to_cpu(*((uint16_t *)&bios->data[offset + 4]));
3749 offset += sizeof(bit_entry_t);
3751 if (bitentry.id[0] != parseorder[i])
3754 switch (bitentry.id[0]) {
3756 parse_bit_C_tbl_entry(pScrn, bios, &bitentry);
3759 if (bios->feature_byte & FEATURE_MOBILE)
3760 parse_bit_display_tbl_entry(pScrn, bios, &bitentry, &fpp);
3763 parse_bit_init_tbl_entry(pScrn, bios, &bitentry);
3764 parse_init_tables(pScrn, bios);
3766 case 'i': /* info? */
3767 parse_bit_i_tbl_entry(pScrn, bios, &bitentry);
3770 if (bios->feature_byte & FEATURE_MOBILE)
3771 parse_bit_lvds_tbl_entry(pScrn, bios, &bitentry, &fpp);
3773 case 'M': /* memory? */
3774 parse_bit_M_tbl_entry(pScrn, bios, &bitentry);
3777 parse_bit_tmds_tbl_entry(pScrn, bios, &bitentry);
3781 /* id[0] = 0 and id[1] = 0 => end of BIT struture */
3782 } while (bitentry.id[0] + bitentry.id[1] != 0);
3786 static void parse_bmp_structure(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset)
3788 /* Parse the BMP structure for useful things
3790 * offset + 5: BMP major version
3791 * offset + 6: BMP minor version
3792 * offset + 10: BCD encoded BIOS version
3794 * offset + 18: init script table pointer (for bios versions < 5.10h)
3795 * offset + 20: extra init script table pointer (for bios versions < 5.10h)
3797 * offset + 24: memory init table pointer (used on early bios versions)
3798 * offset + 26: SDR memory sequencing setup data table
3799 * offset + 28: DDR memory sequencing setup data table
3801 * offset + 54: index of I2C CRTC pair to use for CRT output
3802 * offset + 55: index of I2C CRTC pair to use for TV output
3803 * offset + 56: index of I2C CRTC pair to use for flat panel output
3804 * offset + 58: write CRTC index for I2C pair 0
3805 * offset + 59: read CRTC index for I2C pair 0
3806 * offset + 60: write CRTC index for I2C pair 1
3807 * offset + 61: read CRTC index for I2C pair 1
3809 * offset + 67: maximum internal PLL frequency (single stage PLL)
3810 * offset + 71: minimum internal PLL frequency (single stage PLL)
3812 * offset + 75: script table pointers, as for parse_bit_init_tbl_entry
3814 * offset + 89: TMDS single link output A table pointer
3815 * offset + 91: TMDS single link output B table pointer
3816 * offset + 105: flat panel timings table pointer
3817 * offset + 107: flat panel strapping translation table pointer
3818 * offset + 117: LVDS manufacturer panel config table pointer
3819 * offset + 119: LVDS manufacturer strapping translation table pointer
3821 * offset + 142: PLL limits table pointer
3824 NVPtr pNv = NVPTR(pScrn);
3825 uint8_t bmp_version_major, bmp_version_minor;
3827 struct fppointers fpp;
3828 memset(&fpp, 0, sizeof(struct fppointers));
3830 /* load needed defaults in case we can't parse this info */
3831 pNv->dcb_table.i2c_write[0] = 0x3f;
3832 pNv->dcb_table.i2c_read[0] = 0x3e;
3833 pNv->dcb_table.i2c_write[1] = 0x37;
3834 pNv->dcb_table.i2c_read[1] = 0x36;
3835 bios->fmaxvco = 256000;
3836 bios->fminvco = 128000;
3837 bios->fp.duallink_transition_clk = 90000;
3839 bmp_version_major = bios->data[offset + 5];
3840 bmp_version_minor = bios->data[offset + 6];
3842 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BMP version %d.%d\n",
3843 bmp_version_major, bmp_version_minor);
3845 /* Make sure that 0x36 is blank and can't be mistaken for a DCB pointer on early versions */
3846 if (bmp_version_major < 5)
3847 *(uint16_t *)&bios->data[0x36] = 0;
3849 /* Seems that the minor version was 1 for all major versions prior to 5 */
3850 /* Version 6 could theoretically exist, but I suspect BIT happened instead */
3851 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
3852 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "You have an unsupported BMP version. Please send in your bios\n");
3856 if (bmp_version_major == 0) /* nothing that's currently useful in this version */
3858 else if (bmp_version_major == 1)
3859 bmplength = 44; /* exact for 1.01 */
3860 else if (bmp_version_major == 2)
3861 bmplength = 48; /* exact for 2.01 */
3862 else if (bmp_version_major == 3)
3863 bmplength = 54; /* guessed - mem init tables added in this version */
3864 else if (bmp_version_major == 4 || bmp_version_minor < 0x1) /* don't know if 5.0 exists... */
3865 bmplength = 62; /* guessed - BMP I2C indices added in version 4*/
3866 else if (bmp_version_minor < 0x6)
3867 bmplength = 67; /* exact for 5.01 */
3868 else if (bmp_version_minor < 0x10)
3869 bmplength = 75; /* exact for 5.06 */
3870 else if (bmp_version_minor == 0x10)
3871 bmplength = 89; /* exact for 5.10h */
3872 else if (bmp_version_minor < 0x14)
3873 bmplength = 118; /* exact for 5.11h */
3874 else if (bmp_version_minor < 0x24) /* not sure of version where pll limits came in;
3875 * certainly exist by 0x24 though */
3876 /* length not exact: this is long enough to get lvds members */
3878 else if (bmp_version_minor < 0x27)
3879 /* length not exact: this is long enough to get pll limit member */
3882 /* length not exact: this is long enough to get dual link transition clock */
3886 if (nv_cksum(bios->data + offset, 8)) {
3887 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Bad BMP checksum\n");
3891 /* bit 4 seems to indicate a mobile bios, bit 5 that the flat panel
3892 * tables are present, and bit 6 a tv bios */
3893 bios->feature_byte = bios->data[offset + 9];
3895 parse_bios_version(pScrn, bios, offset + 10);
3897 uint16_t legacy_scripts_offset = offset + 18;
3898 if (bmp_version_major < 2)
3899 legacy_scripts_offset -= 4;
3900 bios->init_script_tbls_ptr = le16_to_cpu(*(uint16_t *)&bios->data[legacy_scripts_offset]);
3901 bios->extra_init_script_tbl_ptr = le16_to_cpu(*(uint16_t *)&bios->data[legacy_scripts_offset + 2]);
3903 if (bmp_version_major > 2) { /* appears in BMP 3 */
3904 bios->legacy.mem_init_tbl_ptr = le16_to_cpu(*(uint16_t *)&bios->data[offset + 24]);
3905 bios->legacy.sdr_seq_tbl_ptr = le16_to_cpu(*(uint16_t *)&bios->data[offset + 26]);
3906 bios->legacy.ddr_seq_tbl_ptr = le16_to_cpu(*(uint16_t *)&bios->data[offset + 28]);
3909 uint16_t legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
3911 legacy_i2c_offset = offset + 54;
3912 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset];
3913 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
3914 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
3915 pNv->dcb_table.i2c_write[0] = bios->data[legacy_i2c_offset + 4];
3916 pNv->dcb_table.i2c_read[0] = bios->data[legacy_i2c_offset + 5];
3917 pNv->dcb_table.i2c_write[1] = bios->data[legacy_i2c_offset + 6];
3918 pNv->dcb_table.i2c_read[1] = bios->data[legacy_i2c_offset + 7];
3920 if (bmplength > 74) {
3921 bios->fmaxvco = le32_to_cpu(*((uint32_t *)&bios->data[offset + 67]));
3922 bios->fminvco = le32_to_cpu(*((uint32_t *)&bios->data[offset + 71]));
3924 if (bmplength > 88) {
3925 bit_entry_t initbitentry;
3926 initbitentry.length = 14;
3927 initbitentry.offset = offset + 75;
3928 parse_bit_init_tbl_entry(pScrn, bios, &initbitentry);
3930 if (bmplength > 94) {
3931 bios->tmds.output0_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[offset + 89]));
3932 bios->tmds.output1_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[offset + 91]));
3933 /* it seems the old style lvds script pointer (which I've not observed in use) gets
3934 * reused as the 18/24 bit panel interface default for EDID equipped panels */
3935 bios->fp.if_is_24bit = bios->data[offset + 95] & 1;
3937 if (bmplength > 108) {
3938 fpp.fptablepointer = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 105])));
3939 fpp.fpxlatetableptr = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 107])));
3942 if (bmplength > 120) {
3943 bios->fp.lvdsmanufacturerpointer = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 117])));
3944 fpp.fpxlatemanufacturertableptr = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 119])));
3946 if (bmplength > 143)
3947 bios->pll_limit_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 142])));
3949 if (bmplength > 157)
3950 bios->fp.duallink_transition_clk = le16_to_cpu(*((uint16_t *)&bios->data[offset + 156])) * 10;
3952 /* want pll_limit_tbl_ptr set (if available) before init is run */
3953 if (bmp_version_major < 5 || bmp_version_minor < 0x10) {
3954 init_exec_t iexec = {true, false};
3955 if (bios->init_script_tbls_ptr)
3956 parse_init_table(pScrn, bios, bios->init_script_tbls_ptr, &iexec);
3957 if (bios->extra_init_script_tbl_ptr)
3958 parse_init_table(pScrn, bios, bios->extra_init_script_tbl_ptr, &iexec);
3960 parse_init_tables(pScrn, bios);
3962 /* If it's not a laptop, you probably don't care about fptables */
3963 if (!(bios->feature_byte & FEATURE_MOBILE))
3966 parse_lvds_manufacturer_table_init(pScrn, bios, &fpp);
3967 parse_fp_mode_table(pScrn, bios, &fpp);
3970 static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
3974 for (i = 0; i <= (n - len); i++) {
3975 for (j = 0; j < len; j++)
3976 if (data[i + j] != str[j])
3986 read_dcb_i2c_entry(ScrnInfoPtr pScrn, uint8_t dcb_version, uint16_t i2ctabptr, int index)
3988 NVPtr pNv = NVPTR(pScrn);
3989 uint8_t *i2ctable = &pNv->VBIOS.data[i2ctabptr];
3990 uint8_t headerlen = 0;
3991 int i2c_entries = MAX_NUM_DCB_ENTRIES;
3992 int recordoffset = 0, rdofs = 1, wrofs = 0;
3997 if (dcb_version >= 0x30) {
3998 if (i2ctable[0] != dcb_version) /* necessary? */
3999 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
4000 "DCB I2C table version mismatch (%02X vs %02X)\n",
4001 i2ctable[0], dcb_version);
4002 headerlen = i2ctable[1];
4003 i2c_entries = i2ctable[2];
4004 if (i2ctable[0] >= 0x40)
4005 /* same port number used for read and write */
4008 /* it's your own fault if you call this function on a DCB 1.1 BIOS --
4009 * the test below is for DCB 1.2
4011 if (dcb_version < 0x14) {
4019 if (index > i2c_entries) {
4020 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4021 "DCB I2C index too big (%d > %d)\n",
4022 index, i2ctable[2]);
4025 if (i2ctable[headerlen + 4 * index + 3] == 0xff) {
4026 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4027 "DCB I2C entry invalid\n");
4031 if (i2ctable[0] >= 0x40) {
4032 int port_type = i2ctable[headerlen + 4 * index + 3];
4035 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
4036 "DCB I2C table has port type %d\n", port_type);
4039 pNv->dcb_table.i2c_read[index] = i2ctable[headerlen + recordoffset + rdofs + 4 * index];
4040 pNv->dcb_table.i2c_write[index] = i2ctable[headerlen + recordoffset + wrofs + 4 * index];
4044 parse_dcb_entry(ScrnInfoPtr pScrn, uint8_t dcb_version, uint16_t i2ctabptr, uint32_t conn, uint32_t conf, struct dcb_entry *entry)
4046 NVPtr pNv = NVPTR(pScrn);
4048 memset(entry, 0, sizeof (struct dcb_entry));
4050 /* safe defaults for a crt */
4052 entry->i2c_index = 0;
4055 entry->location = 0;
4057 entry->duallink_possible = false;
4059 if (dcb_version >= 0x20) {
4060 entry->type = conn & 0xf;
4061 entry->i2c_index = (conn >> 4) & 0xf;
4062 entry->heads = (conn >> 8) & 0xf;
4063 entry->bus = (conn >> 16) & 0xf;
4064 entry->location = (conn >> 20) & 0xf;
4065 entry->or = (conn >> 24) & 0xf;
4066 /* Normal entries consist of a single bit, but dual link has the
4067 * adjacent more significant bit set too
4069 if ((1 << (ffs(entry->or) - 1)) * 3 == entry->or)
4070 entry->duallink_possible = true;
4072 switch (entry->type) {
4077 entry->lvdsconf.use_straps_for_mode = true;
4078 if (dcb_version < 0x22) {
4080 /* both 0x4 and 0x8 show up in v2.0 tables; assume they mean
4081 * the same thing, which is probably wrong, but might work */
4082 if (conf & 0x4 || conf & 0x8)
4083 entry->lvdsconf.use_power_scripts = true;
4087 entry->lvdsconf.use_power_scripts = true;
4090 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4091 "Unknown LVDS configuration bits, please report\n");
4092 /* cause output setting to fail, so message is seen */
4093 pNv->dcb_table.entries = 0;
4099 read_dcb_i2c_entry(pScrn, dcb_version, i2ctabptr, entry->i2c_index);
4100 } else if (dcb_version >= 0x14 ) {
4101 if (conn != 0xf0003f00 && conn != 0xf2247f10 && conn != 0xf2204001 && conn != 0xf2204301 && conn != 0xf2244311 && conn != 0xf2045f14 && conn != 0xf2205004 && conn != 0xf2208001 && conn != 0xf4204011 && conn != 0xf4208011 && conn != 0xf4248011) {
4102 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4103 "Unknown DCB 1.4 / 1.5 entry, please report\n");
4104 /* cause output setting to fail, so message is seen */
4105 pNv->dcb_table.entries = 0;
4108 /* most of the below is a "best guess" atm */
4109 entry->type = conn & 0xf;
4110 if (entry->type == 4) { /* digital */
4112 entry->type = OUTPUT_LVDS;
4114 entry->type = OUTPUT_TMDS;
4116 /* what's in bits 5-13? could be some brooktree/chrontel/philips thing, in tv case */
4117 entry->i2c_index = (conn >> 14) & 0xf;
4118 /* raw heads field is in range 0-1, so move to 1-2 */
4119 entry->heads = ((conn >> 18) & 0x7) + 1;
4120 entry->location = (conn >> 21) & 0xf;
4121 entry->bus = (conn >> 25) & 0x7;
4122 /* set or to be same as heads -- hopefully safe enough */
4123 entry->or = entry->heads;
4125 switch (entry->type) {
4127 /* this is probably buried in conn's unknown bits */
4128 entry->lvdsconf.use_power_scripts = true;
4131 /* invent a DVI-A output, by copying the fields of the DVI-D output
4132 * reported to work by math_b on an NV20(!) */
4133 memcpy(&entry[1], &entry[0], sizeof(struct dcb_entry));
4134 entry[1].type = OUTPUT_ANALOG;
4135 pNv->dcb_table.entries++;
4137 read_dcb_i2c_entry(pScrn, dcb_version, i2ctabptr, entry->i2c_index);
4138 } else if (dcb_version >= 0x12) {
4139 /* v1.2 tables normally have the same 5 entries, which are not
4140 * specific to the card, so use the defaults for a crt */
4141 /* DCB v1.2 does have an I2C table that read_dcb_i2c_table can handle, but cards
4142 * exist (seen on nv11) where the pointer to the table points to the wrong
4143 * place, so for now, we rely on the indices parsed in parse_bmp_structure
4145 entry->i2c_index = pNv->VBIOS.legacy.i2c_indices.crt;
4146 } else { /* pre DCB / v1.1 - use the safe defaults for a crt */
4147 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
4148 "No information in BIOS output table; assuming a CRT output exists\n");
4149 entry->i2c_index = pNv->VBIOS.legacy.i2c_indices.crt;
4152 if (entry->type == OUTPUT_LVDS && pNv->VBIOS.fp.strapping != 0xff)
4153 entry->lvdsconf.use_straps_for_mode = true;
4155 pNv->dcb_table.entries++;
4160 static unsigned int parse_dcb_table(ScrnInfoPtr pScrn, bios_t *bios)
4162 NVPtr pNv = NVPTR(pScrn);
4163 uint16_t dcbptr, i2ctabptr = 0;
4165 uint8_t dcb_version, headerlen = 0x4, entries = MAX_NUM_DCB_ENTRIES;
4166 bool configblock = true;
4167 int recordlength = 8, confofs = 4;
4170 pNv->dcb_table.entries = 0;
4172 /* get the offset from 0x36 */
4173 dcbptr = le16_to_cpu(*(uint16_t *)&bios->data[0x36]);
4175 if (dcbptr == 0x0) {
4176 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
4177 "No Display Configuration Block pointer found\n");
4178 /* this situation likely means a really old card, pre DCB, so we'll add the safe CRT entry */
4179 parse_dcb_entry(pScrn, 0, 0, 0, 0, &pNv->dcb_table.entry[0]);
4183 dcbtable = &bios->data[dcbptr];
4185 /* get DCB version */
4186 dcb_version = dcbtable[0];
4187 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
4188 "Display Configuration Block version %d.%d found\n",
4189 dcb_version >> 4, dcb_version & 0xf);
4191 if (dcb_version >= 0x20) { /* NV17+ */
4194 if (dcb_version >= 0x30) { /* NV40+ */
4195 headerlen = dcbtable[1];
4196 entries = dcbtable[2];
4197 recordlength = dcbtable[3];
4198 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[4]);
4199 sig = le32_to_cpu(*(uint32_t *)&dcbtable[6]);
4201 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
4202 "DCB header length %d, with %d possible entries\n",
4203 headerlen, entries);
4205 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
4206 sig = le32_to_cpu(*(uint32_t *)&dcbtable[4]);
4210 if (sig != 0x4edcbdcb) {
4211 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4212 "Bad Display Configuration Block signature (%08X)\n", sig);
4215 } else if (dcb_version >= 0x14) { /* some NV15/16, and NV11+ */
4219 strncpy(sig, (char *)&dcbtable[-7], 7);
4220 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
4224 if (strcmp(sig, "DEV_REC")) {
4225 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4226 "Bad Display Configuration Block signature (%s)\n", sig);
4229 } else if (dcb_version >= 0x12) { /* some NV6/10, and NV15+ */
4230 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
4231 configblock = false;
4232 } else { /* NV5+, maybe NV4 */
4233 /* DCB 1.1 seems to be quite unhelpful - we'll just add the safe CRT entry */
4234 parse_dcb_entry(pScrn, dcb_version, 0, 0, 0, &pNv->dcb_table.entry[0]);
4238 if (entries >= MAX_NUM_DCB_ENTRIES)
4239 entries = MAX_NUM_DCB_ENTRIES;
4241 for (i = 0; i < entries; i++) {
4242 uint32_t connection, config = 0;
4244 connection = le32_to_cpu(*(uint32_t *)&dcbtable[headerlen + recordlength * i]);
4246 config = le32_to_cpu(*(uint32_t *)&dcbtable[headerlen + confofs + recordlength * i]);
4248 /* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */
4249 if ((connection & 0x0000000f) == 0x0000000f) /* end of records */
4251 if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */
4254 ErrorF("Raw DCB entry %d: %08x %08x\n", i, connection, config);
4255 if (!parse_dcb_entry(pScrn, dcb_version, i2ctabptr, connection, config, &pNv->dcb_table.entry[pNv->dcb_table.entries]))
4259 /* DCB v2.0 lists each output combination separately.
4260 * Here we merge compatible entries to have fewer outputs, with more options
4262 for (i = 0; i < pNv->dcb_table.entries; i++) {
4263 struct dcb_entry *ient = &pNv->dcb_table.entry[i];
4266 for (j = i + 1; j < pNv->dcb_table.entries; j++) {
4267 struct dcb_entry *jent = &pNv->dcb_table.entry[j];
4269 if (jent->type == 100) /* already merged entry */
4272 if (jent->i2c_index == ient->i2c_index && jent->type == ient->type && jent->location == ient->location) {
4273 /* only merge heads field when output field is the same --
4274 * we could merge output field for same heads, but dual link,
4275 * the resultant need to make several merging passes, and lack
4276 * of applicable real life cases has deterred this so far
4278 if (jent->or == ient->or) {
4279 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
4280 "Merging DCB entries %d and %d\n", i, j);
4281 ient->heads |= jent->heads;
4282 jent->type = 100; /* dummy value */
4288 /* Compact entries merged into others out of dcb_table */
4290 for (i = 0; i < pNv->dcb_table.entries; i++) {
4291 if ( pNv->dcb_table.entry[i].type == 100 )
4294 if (newentries != i)
4295 memcpy(&pNv->dcb_table.entry[newentries], &pNv->dcb_table.entry[i], sizeof(struct dcb_entry));
4299 pNv->dcb_table.entries = newentries;
4301 return pNv->dcb_table.entries;
4304 static void load_nv17_hw_sequencer_ucode(ScrnInfoPtr pScrn, bios_t *bios, uint16_t hwsq_offset, int entry)
4306 /* BMP based cards, from NV17, need a microcode loading to correctly
4307 * control the GPIO etc for LVDS panels
4309 * BIT based cards seem to do this directly in the init scripts
4311 * The microcode entries are found by the "HWSQ" signature.
4312 * The header following has the number of entries, and the entry size
4314 * An entry consists of a dword to write to the sequencer control reg
4315 * (0x00001304), followed by the ucode bytes, written sequentially,
4316 * starting at reg 0x00001400
4319 uint8_t bytes_to_write;
4320 uint16_t hwsq_entry_offset;
4323 if (bios->data[hwsq_offset] <= entry) {
4324 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4325 "Too few entries in HW sequencer table for requested entry\n");
4329 bytes_to_write = bios->data[hwsq_offset + 1];
4331 if (bytes_to_write != 36) {
4332 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unknown HW sequencer entry size\n");
4336 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Loading NV17 power sequencing microcode\n");
4338 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
4340 /* set sequencer control */
4341 nv32_wr(pScrn, 0x00001304, le32_to_cpu(*(uint32_t *)&bios->data[hwsq_entry_offset]));
4342 bytes_to_write -= 4;
4345 for (i = 0; i < bytes_to_write; i += 4)
4346 nv32_wr(pScrn, 0x00001400 + i, le32_to_cpu(*(uint32_t *)&bios->data[hwsq_entry_offset + i + 4]));
4348 /* twiddle NV_PBUS_DEBUG_4 */
4349 nv32_wr(pScrn, NV_PBUS_DEBUG_4, nv32_rd(pScrn, NV_PBUS_DEBUG_4) | 0x18);
4352 static void read_bios_edid(ScrnInfoPtr pScrn)
4354 bios_t *bios = &NVPTR(pScrn)->VBIOS;
4355 const uint8_t edid_sig[] = { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
4356 uint16_t offset = 0, newoffset;
4357 int searchlen = NV_PROM_SIZE, i;
4360 if (!(newoffset = findstr(&bios->data[offset], searchlen, edid_sig, 8)))
4362 offset += newoffset;
4363 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
4366 searchlen -= offset;
4370 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Found EDID in BIOS\n");
4372 bios->fp.edid = xalloc(EDID1_LEN);
4373 for (i = 0; i < EDID1_LEN; i++)
4374 bios->fp.edid[i] = bios->data[offset + i];
4377 bool NVInitVBIOS(ScrnInfoPtr pScrn)
4379 NVPtr pNv = NVPTR(pScrn);
4381 memset(&pNv->VBIOS, 0, sizeof(bios_t));
4382 pNv->VBIOS.data = xalloc(NV_PROM_SIZE);
4384 if (!NVShadowVBIOS(pScrn, pNv->VBIOS.data)) {
4385 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4386 "No valid BIOS image found\n");
4387 xfree(pNv->VBIOS.data);
4391 pNv->VBIOS.length = pNv->VBIOS.data[2] * 512;
4392 if (pNv->VBIOS.length > NV_PROM_SIZE)
4393 pNv->VBIOS.length = NV_PROM_SIZE;
4398 bool NVRunVBIOSInit(ScrnInfoPtr pScrn)
4400 NVPtr pNv = NVPTR(pScrn);
4401 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
4402 const uint8_t bit_signature[] = { 'B', 'I', 'T' };
4403 int offset, ret = 0;
4405 crtc_access(pScrn, ACCESS_UNLOCK);
4407 if ((offset = findstr(pNv->VBIOS.data, pNv->VBIOS.length, bit_signature, sizeof(bit_signature)))) {
4408 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BIT BIOS found\n");
4409 parse_bit_structure(pScrn, &pNv->VBIOS, offset + 4);
4410 } else if ((offset = findstr(pNv->VBIOS.data, pNv->VBIOS.length, bmp_signature, sizeof(bmp_signature)))) {
4411 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
4414 if ((hwsq_offset = findstr(pNv->VBIOS.data, pNv->VBIOS.length, hwsq_signature, sizeof(hwsq_signature))))
4415 /* always use entry 0? */
4416 load_nv17_hw_sequencer_ucode(pScrn, &pNv->VBIOS, hwsq_offset + sizeof(hwsq_signature), 0);
4418 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BMP BIOS found\n");
4419 parse_bmp_structure(pScrn, &pNv->VBIOS, offset);
4421 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4422 "No known BIOS signature found\n");
4426 crtc_access(pScrn, ACCESS_LOCK);
4434 unsigned int NVParseBios(ScrnInfoPtr pScrn)
4436 NVPtr pNv = NVPTR(pScrn);
4437 uint32_t saved_nv_pextdev_boot_0;
4439 if (!NVInitVBIOS(pScrn))
4442 /* these will need remembering across a suspend */
4443 saved_nv_pextdev_boot_0 = nv32_rd(pScrn, NV_PEXTDEV_BOOT_0);
4444 saved_nv_pfb_cfg0 = nv32_rd(pScrn, NV_PFB_CFG0);
4446 /* init script execution disabled */
4447 pNv->VBIOS.execute = false;
4449 nv32_wr(pScrn, NV_PEXTDEV_BOOT_0, saved_nv_pextdev_boot_0);
4451 if (!NVRunVBIOSInit(pScrn))
4454 if (parse_dcb_table(pScrn, &pNv->VBIOS))
4455 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
4456 "Found %d entries in DCB\n", pNv->dcb_table.entries);
4458 if (pNv->VBIOS.feature_byte & FEATURE_MOBILE && !pNv->VBIOS.fp.native_mode)
4459 read_bios_edid(pScrn);
4461 /* allow subsequent scripts to execute */
4462 pNv->VBIOS.execute = true;