git.oblomov.eu Git - nouveau/blob - src/nv_output.c

   1 /*
   2  * Copyright 2003 NVIDIA, Corporation
   3  * Copyright 2006 Dave Airlie
   4  * Copyright 2007 Maarten Maathuis
   5  * Copyright 2007-2008 Stuart Bennett
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  23  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  */
  26
  27 #ifdef HAVE_CONFIG_H
  28 #include "config.h"
  29 #endif
  30
  31 #include "xf86.h"
  32 #include "os.h"
  33 #include "mibank.h"
  34 #include "globals.h"
  35 #include "xf86.h"
  36 #include "xf86Priv.h"
  37 #include "xf86DDC.h"
  38 #include "mipointer.h"
  39 #include "windowstr.h"
  40 #include <randrstr.h>
  41 #include <X11/extensions/render.h>
  42 #include "X11/Xatom.h"
  43
  44 #include "xf86Crtc.h"
  45 #include "nv_include.h"
  46
  47 static int nv_output_ramdac_offset(struct nouveau_encoder *nv_encoder)
  48 {
  49         int offset = 0;
  50
  51         if (nv_encoder->dcb->or & (8 | OUTPUT_C))
  52                 offset += 0x68;
  53         if (nv_encoder->dcb->or & (8 | OUTPUT_B))
  54                 offset += 0x2000;
  55
  56         return offset;
  57 }
  58
  59 static void dpms_update_fp_control(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
  60 {
  61         NVPtr pNv = NVPTR(pScrn);
  62         struct nouveau_crtc *nv_crtc;
  63         NVCrtcRegPtr regp;
  64         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
  65         int i;
  66
  67         if (mode == DPMSModeOn) {
  68                 nv_crtc = to_nouveau_crtc(crtc);
  69                 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
  70
  71                 nv_crtc->fp_users |= 1 << nv_encoder->dcb->index;
  72                 NVWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control & ~0x20000022);
  73         } else
  74                 for (i = 0; i <= pNv->twoHeads; i++) {
  75                         nv_crtc = to_nouveau_crtc(xf86_config->crtc[i]);
  76                         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
  77
  78                         nv_crtc->fp_users &= ~(1 << nv_encoder->dcb->index);
  79                         if (!nv_crtc->fp_users) {
  80                                 /* cut the FP output */
  81                                 regp->fp_control |= 0x20000022;
  82                                 NVWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control);
  83                         }
  84                 }
  85 }
  86
  87 static void nv_digital_output_prepare_sel_clk(NVPtr pNv, struct nouveau_encoder *nv_encoder, int head);
  88
  89 static void
  90 lvds_encoder_dpms(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
  91 {
  92         NVPtr pNv = NVPTR(pScrn);
  93
  94         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "lvds_encoder_dpms is called with mode %d\n", mode);
  95
  96         if (nv_encoder->last_dpms == mode)
  97                 return;
  98         nv_encoder->last_dpms = mode;
  99
 100         if (nv_encoder->dcb->lvdsconf.use_power_scripts) {
 101                 /* when removing an output, crtc may not be set, but PANEL_OFF must still be run */
 102                 int head = nv_get_digital_bound_head(pNv, nv_encoder->dcb->or);
 103                 int pclk = nv_encoder->native_mode->Clock;
 104
 105                 if (crtc)
 106                         head = to_nouveau_crtc(crtc)->head;
 107
 108                 if (mode == DPMSModeOn)
 109                         call_lvds_script(pScrn, nv_encoder->dcb, head, LVDS_PANEL_ON, pclk);
 110                 else
 111                         call_lvds_script(pScrn, nv_encoder->dcb, head, LVDS_PANEL_OFF, pclk);
 112         }
 113
 114         dpms_update_fp_control(pScrn, nv_encoder, crtc, mode);
 115
 116         if (mode == DPMSModeOn)
 117                 nv_digital_output_prepare_sel_clk(pNv, nv_encoder, to_nouveau_crtc(crtc)->head);
 118         else {
 119                 pNv->ModeReg.sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
 120                 pNv->ModeReg.sel_clk &= ~0xf0;
 121         }
 122         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, pNv->ModeReg.sel_clk);
 123 }
 124
 125 static void
 126 vga_encoder_dpms(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
 127 {
 128         NVPtr pNv = NVPTR(pScrn);
 129
 130         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vga_encoder_dpms is called with mode %d\n", mode);
 131
 132         if (nv_encoder->last_dpms == mode)
 133                 return;
 134         nv_encoder->last_dpms = mode;
 135
 136         if (pNv->twoHeads) {
 137                 uint32_t outputval = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder));
 138
 139                 if (mode == DPMSModeOff)
 140                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder),
 141                                       outputval & ~NV_RAMDAC_OUTPUT_DAC_ENABLE);
 142                 else if (mode == DPMSModeOn)
 143                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder),
 144                                       outputval | NV_RAMDAC_OUTPUT_DAC_ENABLE);
 145         }
 146 }
 147
 148 static void
 149 tmds_encoder_dpms(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
 150 {
 151         NVPtr pNv = NVPTR(pScrn);
 152
 153         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "tmds_encoder_dpms is called with mode %d\n", mode);
 154
 155         if (nv_encoder->last_dpms == mode)
 156                 return;
 157         nv_encoder->last_dpms = mode;
 158
 159         dpms_update_fp_control(pScrn, nv_encoder, crtc, mode);
 160
 161         if (nv_encoder->dcb->location != LOC_ON_CHIP) {
 162                 struct nouveau_crtc *nv_crtc;
 163                 int i;
 164
 165                 if (mode == DPMSModeOn) {
 166                         nv_crtc = to_nouveau_crtc(crtc);
 167                         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LCD,
 168                                        pNv->ModeReg.crtc_reg[nv_crtc->head].CRTC[NV_VGA_CRTCX_LCD]);
 169                 } else
 170                         for (i = 0; i <= pNv->twoHeads; i++)
 171                                 NVWriteVgaCrtc(pNv, i, NV_VGA_CRTCX_LCD,
 172                                                NVReadVgaCrtc(pNv, i, NV_VGA_CRTCX_LCD) & ~((nv_encoder->dcb->or << 4) & 0x30));
 173         }
 174 }
 175
 176 static void nv_output_dpms(xf86OutputPtr output, int mode)
 177 {
 178         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 179         ScrnInfoPtr pScrn = output->scrn;
 180         xf86CrtcPtr crtc = output->crtc;
 181         void (* const encoder_dpms[4])(ScrnInfoPtr, struct nouveau_encoder *, xf86CrtcPtr, int) =
 182                 /* index matches DCB type */
 183                 { vga_encoder_dpms, NULL, tmds_encoder_dpms, lvds_encoder_dpms };
 184
 185         encoder_dpms[nv_encoder->dcb->type](pScrn, nv_encoder, crtc, mode);
 186 }
 187
 188 static void nv_output_save(xf86OutputPtr output)
 189 {
 190         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 191         ScrnInfoPtr pScrn = output->scrn;
 192         NVPtr pNv = NVPTR(pScrn);
 193
 194         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_save is called.\n");
 195
 196         if (pNv->twoHeads && nv_encoder->dcb->type == OUTPUT_ANALOG)
 197                 nv_encoder->restore.output = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder));
 198         if (nv_encoder->dcb->type == OUTPUT_TMDS || nv_encoder->dcb->type == OUTPUT_LVDS)
 199                 nv_encoder->restore.head = nv_get_digital_bound_head(pNv, nv_encoder->dcb->or);
 200 }
 201
 202 static uint32_t nv_get_clock_from_crtc(ScrnInfoPtr pScrn, RIVA_HW_STATE *state, uint8_t crtc)
 203 {
 204         NVPtr pNv = NVPTR(pScrn);
 205         struct pll_lims pll_lim;
 206         uint32_t vplla = state->crtc_reg[crtc].vpll_a;
 207         uint32_t vpllb = state->crtc_reg[crtc].vpll_b;
 208         bool nv40_single = pNv->Architecture == 0x40 &&
 209                            ((!crtc && state->reg580 & NV_RAMDAC_580_VPLL1_ACTIVE) ||
 210                             (crtc && state->reg580 & NV_RAMDAC_580_VPLL2_ACTIVE));
 211
 212         if (!get_pll_limits(pScrn, crtc ? VPLL2 : VPLL1, &pll_lim))
 213                 return 0;
 214
 215         return nv_decode_pll_highregs(pNv, vplla, vpllb, nv40_single, pll_lim.refclk);
 216 }
 217
 218 static void nv_output_restore(xf86OutputPtr output)
 219 {
 220         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 221         ScrnInfoPtr pScrn = output->scrn;
 222         NVPtr pNv = NVPTR(pScrn);
 223         int head = nv_encoder->restore.head;
 224
 225         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_restore is called.\n");
 226
 227         if (pNv->twoHeads && nv_encoder->dcb->type == OUTPUT_ANALOG)
 228                 NVWriteRAMDAC(pNv, 0,
 229                               NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder),
 230                               nv_encoder->restore.output);
 231         if (nv_encoder->dcb->type == OUTPUT_LVDS)
 232                 call_lvds_script(pScrn, nv_encoder->dcb, head, LVDS_PANEL_ON,
 233                                  nv_encoder->native_mode->Clock);
 234         if (nv_encoder->dcb->type == OUTPUT_TMDS) {
 235                 int clock = nv_get_clock_from_crtc(pScrn, &pNv->SavedReg, head);
 236
 237                 run_tmds_table(pScrn, nv_encoder->dcb, head, clock);
 238         }
 239
 240         nv_encoder->last_dpms = NV_DPMS_CLEARED;
 241 }
 242
 243 static int nv_output_mode_valid(xf86OutputPtr output, DisplayModePtr mode)
 244 {
 245         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 246         NVPtr pNv = NVPTR(output->scrn);
 247
 248         if (!output->doubleScanAllowed && mode->Flags & V_DBLSCAN)
 249                 return MODE_NO_DBLESCAN;
 250         if (!output->interlaceAllowed && mode->Flags & V_INTERLACE)
 251                 return MODE_NO_INTERLACE;
 252
 253         if (nv_encoder->dcb->type == OUTPUT_ANALOG) {
 254                 if (mode->Clock > (pNv->twoStagePLL ? 400000 : 350000))
 255                         return MODE_CLOCK_HIGH;
 256                 if (mode->Clock < 12000)
 257                         return MODE_CLOCK_LOW;
 258         }
 259         if (nv_encoder->dcb->type == OUTPUT_LVDS || nv_encoder->dcb->type == OUTPUT_TMDS)
 260                 /* No modes > panel's native res */
 261                 if (mode->HDisplay > nv_encoder->native_mode->HDisplay ||
 262                     mode->VDisplay > nv_encoder->native_mode->VDisplay)
 263                         return MODE_PANEL;
 264         if (nv_encoder->dcb->type == OUTPUT_TMDS) {
 265                 if (nv_encoder->dcb->duallink_possible) {
 266                         if (mode->Clock > 330000) /* 2x165 MHz */
 267                                 return MODE_CLOCK_HIGH;
 268                 } else {
 269                         if (mode->Clock > 165000) /* 165 MHz */
 270                                 return MODE_CLOCK_HIGH;
 271                 }
 272         }
 273
 274         return MODE_OK;
 275 }
 276
 277 static Bool
 278 nv_output_mode_fixup(xf86OutputPtr output, DisplayModePtr mode,
 279                      DisplayModePtr adjusted_mode)
 280 {
 281         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 282         ScrnInfoPtr pScrn = output->scrn;
 283
 284         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_mode_fixup is called.\n");
 285
 286         /* For internal panels and gpu scaling on DVI we need the native mode */
 287         if (nv_encoder->dcb->type == OUTPUT_LVDS ||
 288             (nv_encoder->dcb->type == OUTPUT_TMDS && nv_encoder->scaling_mode != SCALE_PANEL)) {
 289                 adjusted_mode->HDisplay = nv_encoder->native_mode->HDisplay;
 290                 adjusted_mode->HSkew = nv_encoder->native_mode->HSkew;
 291                 adjusted_mode->HSyncStart = nv_encoder->native_mode->HSyncStart;
 292                 adjusted_mode->HSyncEnd = nv_encoder->native_mode->HSyncEnd;
 293                 adjusted_mode->HTotal = nv_encoder->native_mode->HTotal;
 294                 adjusted_mode->VDisplay = nv_encoder->native_mode->VDisplay;
 295                 adjusted_mode->VScan = nv_encoder->native_mode->VScan;
 296                 adjusted_mode->VSyncStart = nv_encoder->native_mode->VSyncStart;
 297                 adjusted_mode->VSyncEnd = nv_encoder->native_mode->VSyncEnd;
 298                 adjusted_mode->VTotal = nv_encoder->native_mode->VTotal;
 299                 adjusted_mode->Clock = nv_encoder->native_mode->Clock;
 300                 adjusted_mode->Flags = nv_encoder->native_mode->Flags;
 301
 302                 xf86SetModeCrtc(adjusted_mode, INTERLACE_HALVE_V);
 303         }
 304
 305         return TRUE;
 306 }
 307
 308 static void
 309 nv_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, DisplayModePtr adjusted_mode)
 310 {
 311         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 312         ScrnInfoPtr pScrn = output->scrn;
 313         NVPtr pNv = NVPTR(pScrn);
 314         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(output->crtc);
 315
 316         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_mode_set is called.\n");
 317
 318         if (pNv->twoHeads && nv_encoder->dcb->type == OUTPUT_ANALOG)
 319                 /* bit 16-19 are bits that are set on some G70 cards,
 320                  * but don't seem to have much effect */
 321                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder),
 322                               nv_crtc->head << 8 | NV_RAMDAC_OUTPUT_DAC_ENABLE);
 323         if (nv_encoder->dcb->type == OUTPUT_TMDS)
 324                 run_tmds_table(pScrn, nv_encoder->dcb, nv_crtc->head, adjusted_mode->Clock);
 325         else if (nv_encoder->dcb->type == OUTPUT_LVDS)
 326                 call_lvds_script(pScrn, nv_encoder->dcb, nv_crtc->head, LVDS_RESET, adjusted_mode->Clock);
 327
 328         /* This could use refinement for flatpanels, but it should work this way */
 329         if (pNv->NVArch < 0x44)
 330                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + nv_output_ramdac_offset(nv_encoder), 0xf0000000);
 331         else
 332                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + nv_output_ramdac_offset(nv_encoder), 0x00100000);
 333 }
 334
 335 static Bool
 336 nv_load_detect(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder)
 337 {
 338         NVPtr pNv = NVPTR(pScrn);
 339         uint32_t testval, regoffset = nv_output_ramdac_offset(nv_encoder);
 340         uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput, saved_rtest_ctrl, temp;
 341         int present = 0;
 342
 343 #define RGB_TEST_DATA(r,g,b) (r << 0 | g << 10 | b << 20)
 344         testval = RGB_TEST_DATA(0x140, 0x140, 0x140); /* 0x94050140 */
 345         if (pNv->VBIOS.dactestval)
 346                 testval = pNv->VBIOS.dactestval;
 347
 348         saved_rtest_ctrl = NVReadRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset);
 349         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset, saved_rtest_ctrl & ~0x00010000);
 350
 351         if (pNv->NVArch >= 0x17) {
 352                 saved_powerctrl_2 = nvReadMC(pNv, NV_PBUS_POWERCTRL_2);
 353
 354                 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, saved_powerctrl_2 & 0xd7ffffff);
 355                 if (regoffset == 0x68) {
 356                         saved_powerctrl_4 = nvReadMC(pNv, NV_PBUS_POWERCTRL_4);
 357                         nvWriteMC(pNv, NV_PBUS_POWERCTRL_4, saved_powerctrl_4 & 0xffffffcf);
 358                 }
 359         }
 360
 361         usleep(4000);
 362
 363         saved_routput = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset);
 364         /* nv driver and nv31 use 0xfffffeee
 365          * nv34 and 6600 use 0xfffffece */
 366         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset, saved_routput & 0xfffffece);
 367         usleep(1000);
 368
 369         temp = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset);
 370         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset, temp | 1);
 371
 372         /* no regoffset on purpose */
 373         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_DATA, 1 << 31 | testval);
 374         temp = NVReadRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL);
 375         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL, temp | 0x1000);
 376         usleep(1000);
 377
 378         present = NVReadRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset) & (1 << 28);
 379
 380         /* no regoffset on purpose */
 381         temp = NVReadRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL);
 382         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL, temp & 0xffffefff);
 383         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_DATA, 0);
 384
 385         /* bios does something more complex for restoring, but I think this is good enough */
 386         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset, saved_routput);
 387         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset, saved_rtest_ctrl);
 388         if (pNv->NVArch >= 0x17) {
 389                 if (regoffset == 0x68)
 390                         nvWriteMC(pNv, NV_PBUS_POWERCTRL_4, saved_powerctrl_4);
 391                 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, saved_powerctrl_2);
 392         }
 393
 394         if (present) {
 395                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Load detected on output %c\n", '@' + ffs(nv_encoder->dcb->or));
 396                 return TRUE;
 397         }
 398
 399         return FALSE;
 400 }
 401
 402 static xf86OutputStatus
 403 nv_output_detect(xf86OutputPtr output)
 404 {
 405         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 406         ScrnInfoPtr pScrn = output->scrn;
 407         NVPtr pNv = NVPTR(pScrn);
 408         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 409
 410         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_detect is called.\n");
 411
 412         if (nv_connector->pDDCBus) {
 413                 if ((nv_connector->mon = xf86OutputGetEDID(output, nv_connector->pDDCBus)) &&
 414                     ((nv_connector->mon->features.input_type && nv_encoder->dcb->type == OUTPUT_ANALOG) ||
 415                      (!nv_connector->mon->features.input_type && nv_encoder->dcb->type == OUTPUT_TMDS))) {
 416                         xfree(nv_connector->mon);
 417                         nv_connector->mon = NULL;
 418                 }
 419                 xf86OutputSetEDID(output, nv_connector->mon);
 420                 if (nv_connector->mon)
 421                         return XF86OutputStatusConnected;
 422         }
 423
 424         if (nv_encoder->dcb->type == OUTPUT_ANALOG) {
 425                 /* we don't have a load det function for early cards */
 426                 if (!pNv->twoHeads || pNv->NVArch == 0x11)
 427                         return XF86OutputStatusUnknown;
 428                 else if (pNv->twoHeads && nv_load_detect(pScrn, nv_encoder))
 429                         return XF86OutputStatusConnected;
 430         } else if (nv_encoder->dcb->type == OUTPUT_LVDS) {
 431                 if (nv_encoder->dcb->lvdsconf.use_straps_for_mode &&
 432                     pNv->VBIOS.fp.native_mode)
 433                         return XF86OutputStatusConnected;
 434                 if (pNv->VBIOS.fp.edid) {
 435                         xf86DrvMsg(pScrn->scrnIndex, X_INFO,
 436                                    "Will use hardcoded BIOS FP EDID\n");
 437                         nv_connector->mon = xf86InterpretEDID(pScrn->scrnIndex,
 438                                                            pNv->VBIOS.fp.edid);
 439                         xf86OutputSetEDID(output, nv_connector->mon);
 440                         return XF86OutputStatusConnected;
 441                 }
 442         }
 443
 444         return XF86OutputStatusDisconnected;
 445 }
 446
 447 static DisplayModePtr
 448 get_native_mode_from_edid(xf86OutputPtr output, DisplayModePtr edid_modes)
 449 {
 450         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 451         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 452         ScrnInfoPtr pScrn = output->scrn;
 453         int max_h_active = 0, max_v_active = 0;
 454         int i;
 455         DisplayModePtr mode;
 456
 457         for (i = 0; i < DET_TIMINGS; i++) {
 458                 /* We only look at detailed timings atm */
 459                 if (nv_connector->mon->det_mon[i].type != DT)
 460                         continue;
 461                 /* Selecting only based on width ok? */
 462                 if (nv_connector->mon->det_mon[i].section.d_timings.h_active > max_h_active) {
 463                         max_h_active = nv_connector->mon->det_mon[i].section.d_timings.h_active;
 464                         max_v_active = nv_connector->mon->det_mon[i].section.d_timings.v_active;
 465                 }
 466         }
 467         if (!(max_h_active && max_v_active)) {
 468                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No EDID detailed timings available, bailing out.\n");
 469                 return NULL;
 470         }
 471
 472         if (nv_encoder->native_mode) {
 473                 xfree(nv_encoder->native_mode);
 474                 nv_encoder->native_mode = NULL;
 475         }
 476
 477         for (mode = edid_modes; mode != NULL; mode = mode->next) {
 478                 if (mode->HDisplay == max_h_active &&
 479                         mode->VDisplay == max_v_active) {
 480                         /* Take the preferred mode when it exists. */
 481                         if (mode->type & M_T_PREFERRED) {
 482                                 nv_encoder->native_mode = xf86DuplicateMode(mode);
 483                                 break;
 484                         }
 485                         /* Find the highest refresh mode otherwise. */
 486                         if (!nv_encoder->native_mode || (mode->VRefresh > nv_encoder->native_mode->VRefresh)) {
 487                                 if (nv_encoder->native_mode)
 488                                         xfree(nv_encoder->native_mode);
 489                                 mode->type |= M_T_PREFERRED;
 490                                 nv_encoder->native_mode = xf86DuplicateMode(mode);
 491                         }
 492                 }
 493         }
 494
 495         return nv_encoder->native_mode;
 496 }
 497
 498 static DisplayModePtr
 499 nv_output_get_edid_modes(xf86OutputPtr output)
 500 {
 501         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 502         ScrnInfoPtr pScrn = output->scrn;
 503         DisplayModePtr edid_modes;
 504
 505         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_get_edid_modes is called.\n");
 506
 507         if (!(edid_modes = xf86OutputGetEDIDModes(output)))
 508                 return NULL;
 509
 510         if (nv_encoder->dcb->type == OUTPUT_TMDS || nv_encoder->dcb->type == OUTPUT_LVDS)
 511                 if (!get_native_mode_from_edid(output, edid_modes))
 512                         return NULL;
 513
 514         if (nv_encoder->dcb->type == OUTPUT_LVDS) {
 515                 static bool dual_link_correction_done = false;
 516
 517                 if (!dual_link_correction_done) {
 518                         parse_lvds_manufacturer_table(pScrn, &NVPTR(pScrn)->VBIOS, nv_encoder->native_mode->Clock);
 519                         dual_link_correction_done = true;
 520                 }
 521         }
 522
 523         return edid_modes;
 524 }
 525
 526 static void
 527 nv_output_destroy (xf86OutputPtr output)
 528 {
 529         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 530         struct nouveau_encoder *nv_encoder;
 531         ScrnInfoPtr pScrn = output->scrn;
 532
 533         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_destroy is called.\n");
 534
 535         if (!nv_connector)
 536                 return;
 537
 538         if (nv_connector->mon)
 539                 xfree(nv_connector->mon);
 540         nv_encoder = to_nouveau_encoder(output);
 541         if (nv_encoder->native_mode)
 542                 xfree(nv_encoder->native_mode);
 543         xfree(nv_connector);
 544 }
 545
 546 static void nv_digital_output_prepare_sel_clk(NVPtr pNv, struct nouveau_encoder *nv_encoder, int head)
 547 {
 548         NVRegPtr state = &pNv->ModeReg;
 549         uint32_t bits1618 = nv_encoder->dcb->or & OUTPUT_A ? 0x10000 : 0x40000;
 550
 551         if (nv_encoder->dcb->location != LOC_ON_CHIP)
 552                 return;
 553
 554         /* SEL_CLK is only used on the primary ramdac
 555          * It toggles spread spectrum PLL output and sets the bindings of PLLs
 556          * to heads on digital outputs
 557          */
 558         if (head)
 559                 state->sel_clk |= bits1618;
 560         else
 561                 state->sel_clk &= ~bits1618;
 562
 563         /* nv30:
 564          *      bit 0           NVClk spread spectrum on/off
 565          *      bit 2           MemClk spread spectrum on/off
 566          *      bit 4           PixClk1 spread spectrum on/off toggle
 567          *      bit 6           PixClk2 spread spectrum on/off toggle
 568          *
 569          * nv40 (observations from bios behaviour and mmio traces):
 570          *      bits 4&6        as for nv30
 571          *      bits 5&7        head dependent as for bits 4&6, but do not appear with 4&6;
 572          *                      maybe a different spread mode
 573          *      bits 8&10       seen on dual-link dvi outputs, purpose unknown (set by POST scripts)
 574          *      The logic behind turning spread spectrum on/off in the first place,
 575          *      and which bit-pair to use, is unclear on nv40 (for earlier cards, the fp table
 576          *      entry has the necessary info)
 577          */
 578         if (nv_encoder->dcb->type == OUTPUT_LVDS && pNv->SavedReg.sel_clk & 0xf0) {
 579                 int shift = (pNv->SavedReg.sel_clk & 0x50) ? 0 : 1;
 580
 581                 state->sel_clk &= ~0xf0;
 582                 state->sel_clk |= (head ? 0x40 : 0x10) << shift;
 583         }
 584 }
 585
 586 static void
 587 nv_output_prepare(xf86OutputPtr output)
 588 {
 589         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 590         ScrnInfoPtr pScrn = output->scrn;
 591         NVPtr pNv = NVPTR(output->scrn);
 592         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(output->crtc);
 593         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 594
 595         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_prepare is called.\n");
 596
 597         output->funcs->dpms(output, DPMSModeOff);
 598
 599         /* calculate some output specific CRTC regs now, so that they can be written in nv_crtc_set_mode */
 600         if (nv_encoder->dcb->type == OUTPUT_LVDS || nv_encoder->dcb->type == OUTPUT_TMDS)
 601                 nv_digital_output_prepare_sel_clk(pNv, nv_encoder, nv_crtc->head);
 602
 603         /* Some NV4x have unknown values (0x3f, 0x50, 0x54, 0x6b, 0x79, 0x7f etc.) which we don't alter */
 604         if (!(regp->CRTC[NV_VGA_CRTCX_LCD] & 0x44)) {
 605                 if (nv_encoder->dcb->type == OUTPUT_LVDS || nv_encoder->dcb->type == OUTPUT_TMDS) {
 606                         regp->CRTC[NV_VGA_CRTCX_LCD] &= ~0x30;
 607                         regp->CRTC[NV_VGA_CRTCX_LCD] |= 0x3;
 608                         if (nv_crtc->head == 0)
 609                                 regp->CRTC[NV_VGA_CRTCX_LCD] |= 0x8;
 610                         else
 611                                 regp->CRTC[NV_VGA_CRTCX_LCD] &= ~0x8;
 612                         if (nv_encoder->dcb->location != LOC_ON_CHIP)
 613                                 regp->CRTC[NV_VGA_CRTCX_LCD] |= (nv_encoder->dcb->or << 4) & 0x30;
 614                 } else
 615                         regp->CRTC[NV_VGA_CRTCX_LCD] = 0;
 616         }
 617 }
 618
 619 static void
 620 nv_output_commit(xf86OutputPtr output)
 621 {
 622         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 623         ScrnInfoPtr pScrn = output->scrn;
 624         xf86CrtcPtr crtc = output->crtc;
 625         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 626
 627         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_commit is called.\n");
 628
 629         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Output %s is running on CRTC %d using output %c\n", output->name, nv_crtc->head, '@' + ffs(nv_encoder->dcb->or));
 630
 631         output->funcs->dpms(output, DPMSModeOn);
 632 }
 633
 634 /*
 635  * Several scaling modes exist, let the user choose.
 636  */
 637 #define SCALING_MODE_NAME "SCALING_MODE"
 638 static const struct {
 639         char *name;
 640         enum scaling_modes mode;
 641 } scaling_mode[] = {
 642         { "panel", SCALE_PANEL },
 643         { "fullscreen", SCALE_FULLSCREEN },
 644         { "aspect", SCALE_ASPECT },
 645         { "noscale", SCALE_NOSCALE },
 646         { NULL, SCALE_INVALID}
 647 };
 648 static Atom scaling_mode_atom;
 649
 650 #define DITHERING_MODE_NAME "DITHERING"
 651 static Atom dithering_atom;
 652
 653 static void
 654 nv_output_create_resources(xf86OutputPtr output)
 655 {
 656         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 657         ScrnInfoPtr pScrn = output->scrn;
 658         INT32 dithering_range[2] = { 0, 1 };
 659         int error, i;
 660
 661         /* no properties for vga */
 662         if (nv_encoder->dcb->type == OUTPUT_ANALOG)
 663                 return;
 664
 665         /*
 666          * Setup scaling mode property.
 667          */
 668         scaling_mode_atom = MakeAtom(SCALING_MODE_NAME, sizeof(SCALING_MODE_NAME) - 1, TRUE);
 669
 670         error = RRConfigureOutputProperty(output->randr_output,
 671                                         scaling_mode_atom, TRUE, FALSE, FALSE,
 672                                         0, NULL);
 673
 674         if (error != 0) {
 675                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 676                         "RRConfigureOutputProperty error, %d\n", error);
 677         }
 678
 679         char *existing_scale_name = NULL;
 680         for (i = 0; scaling_mode[i].name; i++)
 681                 if (scaling_mode[i].mode == nv_encoder->scaling_mode)
 682                         existing_scale_name = scaling_mode[i].name;
 683
 684         error = RRChangeOutputProperty(output->randr_output, scaling_mode_atom,
 685                                         XA_STRING, 8, PropModeReplace,
 686                                         strlen(existing_scale_name),
 687                                         existing_scale_name, FALSE, TRUE);
 688
 689         if (error != 0) {
 690                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 691                         "Failed to set scaling mode, %d\n", error);
 692         }
 693
 694         /*
 695          * Setup dithering property.
 696          */
 697         dithering_atom = MakeAtom(DITHERING_MODE_NAME, sizeof(DITHERING_MODE_NAME) - 1, TRUE);
 698
 699         error = RRConfigureOutputProperty(output->randr_output,
 700                                         dithering_atom, TRUE, TRUE, FALSE,
 701                                         2, dithering_range);
 702
 703         if (error != 0) {
 704                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 705                         "RRConfigureOutputProperty error, %d\n", error);
 706         }
 707
 708         /* promote bool into int32 to make RandR DIX and big endian happy */
 709         int32_t existing_dither = nv_encoder->dithering;
 710         error = RRChangeOutputProperty(output->randr_output, dithering_atom,
 711                                         XA_INTEGER, 32, PropModeReplace, 1,
 712                                         &existing_dither, FALSE, TRUE);
 713
 714         if (error != 0) {
 715                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 716                         "Failed to set dithering mode, %d\n", error);
 717         }
 718 }
 719
 720 static Bool
 721 nv_output_set_property(xf86OutputPtr output, Atom property,
 722                                 RRPropertyValuePtr value)
 723 {
 724         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 725
 726         if (property == scaling_mode_atom) {
 727                 int32_t ret;
 728                 char *name = NULL;
 729
 730                 if (value->type != XA_STRING || value->format != 8)
 731                         return FALSE;
 732
 733                 name = (char *) value->data;
 734
 735                 /* Match a string to a scaling mode */
 736                 ret = nv_scaling_mode_lookup(name, value->size);
 737                 if (ret == SCALE_INVALID)
 738                         return FALSE;
 739
 740                 /* LVDS must always use gpu scaling. */
 741                 if (ret == SCALE_PANEL && nv_encoder->dcb->type == OUTPUT_LVDS)
 742                         return FALSE;
 743
 744                 nv_encoder->scaling_mode = ret;
 745         } else if (property == dithering_atom) {
 746                 if (value->type != XA_INTEGER || value->format != 32)
 747                         return FALSE;
 748
 749                 int32_t val = *(int32_t *) value->data;
 750
 751                 if (val < 0 || val > 1)
 752                         return FALSE;
 753
 754                 nv_encoder->dithering = val;
 755         }
 756
 757         return TRUE;
 758 }
 759
 760 static const xf86OutputFuncsRec nv_output_funcs = {
 761         .dpms = nv_output_dpms,
 762         .save = nv_output_save,
 763         .restore = nv_output_restore,
 764         .mode_valid = nv_output_mode_valid,
 765         .mode_fixup = nv_output_mode_fixup,
 766         .mode_set = nv_output_mode_set,
 767         .detect = nv_output_detect,
 768         .get_modes = nv_output_get_edid_modes,
 769         .destroy = nv_output_destroy,
 770         .prepare = nv_output_prepare,
 771         .commit = nv_output_commit,
 772         .create_resources = nv_output_create_resources,
 773         .set_property = nv_output_set_property,
 774 };
 775
 776 static DisplayModePtr
 777 nv_lvds_output_get_modes(xf86OutputPtr output)
 778 {
 779         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 780         ScrnInfoPtr pScrn = output->scrn;
 781         NVPtr pNv = NVPTR(pScrn);
 782         DisplayModePtr modes;
 783
 784         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_lvds_output_get_modes is called.\n");
 785
 786         if ((modes = nv_output_get_edid_modes(output)))
 787                 return modes;
 788
 789         if (!nv_encoder->dcb->lvdsconf.use_straps_for_mode || pNv->VBIOS.fp.native_mode == NULL)
 790                 return NULL;
 791
 792         if (nv_encoder->native_mode)
 793                 xfree(nv_encoder->native_mode);
 794         nv_encoder->native_mode = xf86DuplicateMode(pNv->VBIOS.fp.native_mode);
 795
 796         return xf86DuplicateMode(pNv->VBIOS.fp.native_mode);
 797 }
 798
 799 static const xf86OutputFuncsRec nv_lvds_output_funcs = {
 800         .dpms = nv_output_dpms,
 801         .save = nv_output_save,
 802         .restore = nv_output_restore,
 803         .mode_valid = nv_output_mode_valid,
 804         .mode_fixup = nv_output_mode_fixup,
 805         .mode_set = nv_output_mode_set,
 806         .detect = nv_output_detect,
 807         .get_modes = nv_lvds_output_get_modes,
 808         .destroy = nv_output_destroy,
 809         .prepare = nv_output_prepare,
 810         .commit = nv_output_commit,
 811         .create_resources = nv_output_create_resources,
 812         .set_property = nv_output_set_property,
 813 };
 814
 815 static void
 816 nv_add_output(ScrnInfoPtr pScrn, struct dcb_entry *dcbent, const xf86OutputFuncsRec *output_funcs, char *outputname)
 817 {
 818         NVPtr pNv = NVPTR(pScrn);
 819         xf86OutputPtr output;
 820         struct nouveau_connector *nv_connector;
 821         struct nouveau_encoder *nv_encoder = &pNv->encoders[dcbent->index];
 822
 823         if (!(output = xf86OutputCreate(pScrn, output_funcs, outputname)))
 824                 return;
 825         if (!(nv_connector = xnfcalloc(sizeof (struct nouveau_connector), 1)))
 826                 return;
 827
 828         output->driver_private = nv_connector;
 829
 830         if (dcbent->i2c_index < 0xf && pNv->pI2CBus[dcbent->i2c_index] == NULL)
 831                 NV_I2CInit(pScrn, &pNv->pI2CBus[dcbent->i2c_index], pNv->dcb_table.i2c_read[dcbent->i2c_index], xstrdup(outputname));
 832         nv_connector->pDDCBus = pNv->pI2CBus[dcbent->i2c_index];
 833         nv_connector->nv_encoder = nv_encoder;
 834         nv_encoder->dcb = dcbent;
 835         nv_encoder->last_dpms = NV_DPMS_CLEARED;
 836
 837         nv_encoder->dithering = (pNv->FPDither || (nv_encoder->dcb->type == OUTPUT_LVDS && !pNv->VBIOS.fp.if_is_24bit));
 838         if (pNv->fpScaler) /* GPU Scaling */
 839                 nv_encoder->scaling_mode = SCALE_ASPECT;
 840         else if (nv_encoder->dcb->type == OUTPUT_LVDS)
 841                 nv_encoder->scaling_mode = SCALE_NOSCALE;
 842         else
 843                 nv_encoder->scaling_mode = SCALE_PANEL;
 844         if (xf86GetOptValString(pNv->Options, OPTION_SCALING_MODE)) {
 845                 nv_encoder->scaling_mode = nv_scaling_mode_lookup(xf86GetOptValString(pNv->Options, OPTION_SCALING_MODE), -1);
 846                 if (nv_encoder->scaling_mode == SCALE_INVALID)
 847                         nv_encoder->scaling_mode = SCALE_ASPECT; /* default */
 848         }
 849
 850         output->possible_crtcs = dcbent->heads;
 851         if (nv_encoder->dcb->type == OUTPUT_LVDS || nv_encoder->dcb->type == OUTPUT_TMDS) {
 852                 output->doubleScanAllowed = false;
 853                 output->interlaceAllowed = false;
 854         } else {
 855                 output->doubleScanAllowed = true;
 856                 if (pNv->Architecture == NV_ARCH_20 ||
 857                    (pNv->Architecture == NV_ARCH_10 &&
 858                     (pNv->Chipset & 0x0ff0) != CHIPSET_NV10 &&
 859                     (pNv->Chipset & 0x0ff0) != CHIPSET_NV15))
 860                         /* HW is broken */
 861                         output->interlaceAllowed = false;
 862                 else
 863                         output->interlaceAllowed = true;
 864         }
 865 }
 866
 867 void NvSetupOutputs(ScrnInfoPtr pScrn)
 868 {
 869         NVPtr pNv = NVPTR(pScrn);
 870         int i, i2c_count[MAX_NUM_DCB_ENTRIES];
 871         struct dcb_entry *dcbent;
 872         char outputname[20];
 873         int vga_count = 0, tv_count = 0, dvia_count = 0, dvid_count = 0, lvds_count = 0;
 874
 875         if (!(pNv->encoders = xnfcalloc(pNv->dcb_table.entries, sizeof (struct nouveau_encoder))))
 876                 return;
 877         memset(pNv->pI2CBus, 0, sizeof(pNv->pI2CBus));
 878         memset(i2c_count, 0, sizeof(i2c_count));
 879         for (i = 0 ; i < pNv->dcb_table.entries; i++)
 880                 i2c_count[pNv->dcb_table.entry[i].i2c_index]++;
 881
 882         for (i = 0; i < pNv->dcb_table.entries; i++) {
 883                 dcbent = &pNv->dcb_table.entry[i];
 884
 885                 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "DCB entry %d: type: %d, heads: %d, or: %d\n", i, dcbent->type, dcbent->heads, dcbent->or);
 886
 887                 switch (dcbent->type) {
 888                 case OUTPUT_ANALOG:
 889                         if (i2c_count[dcbent->i2c_index] == 1)
 890                                 sprintf(outputname, "VGA-%d", vga_count++);
 891                         else
 892                                 sprintf(outputname, "DVI-A-%d", dvia_count++);
 893                         nv_add_output(pScrn, dcbent, &nv_output_funcs, outputname);
 894                         break;
 895                 case OUTPUT_TMDS:
 896                         sprintf(outputname, "DVI-D-%d", dvid_count++);
 897                         nv_add_output(pScrn, dcbent, &nv_output_funcs, outputname);
 898                         break;
 899                 case OUTPUT_TV:
 900                         sprintf(outputname, "TV-%d", tv_count++);
 901                         break;
 902                 case OUTPUT_LVDS:
 903                         sprintf(outputname, "LVDS-%d", lvds_count++);
 904                         nv_add_output(pScrn, dcbent, &nv_lvds_output_funcs, outputname);
 905                         break;
 906                 default:
 907                         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DCB type %d not known\n", dcbent->type);
 908                         break;
 909                 }
 910         }
 911 }