git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 2006 Dave Airlie
   3  * Copyright 2007 Maarten Maathuis
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
  26  * decleration is at the bottom of this file as it is rather ugly
  27  */
  28
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include <assert.h>
  34 #include "xf86.h"
  35 #include "os.h"
  36 #include "mibank.h"
  37 #include "globals.h"
  38 #include "xf86.h"
  39 #include "xf86Priv.h"
  40 #include "xf86DDC.h"
  41 #include "mipointer.h"
  42 #include "windowstr.h"
  43 #include <randrstr.h>
  44 #include <X11/extensions/render.h>
  45
  46 #include "xf86Crtc.h"
  47 #include "nv_include.h"
  48
  49 #include "vgaHW.h"
  50
  51 #define CRTC_INDEX 0x3d4
  52 #define CRTC_DATA 0x3d5
  53 #define CRTC_IN_STAT_1 0x3da
  54
  55 #define WHITE_VALUE 0x3F
  56 #define BLACK_VALUE 0x00
  57 #define OVERSCAN_VALUE 0x01
  58
  59 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  60 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  61 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  62 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  63 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  64 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  65
  66 static CARD8 NVReadPVIO(xf86CrtcPtr crtc, CARD32 address)
  67 {
  68         ScrnInfoPtr pScrn = crtc->scrn;
  69         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  70         NVPtr pNv = NVPTR(pScrn);
  71
  72         /* Only NV4x have two pvio ranges */
  73         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  74                 return NV_RD08(pNv->PVIO1, address);
  75         } else {
  76                 return NV_RD08(pNv->PVIO0, address);
  77         }
  78 }
  79
  80 static void NVWritePVIO(xf86CrtcPtr crtc, CARD32 address, CARD8 value)
  81 {
  82         ScrnInfoPtr pScrn = crtc->scrn;
  83         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  84         NVPtr pNv = NVPTR(pScrn);
  85
  86         /* Only NV4x have two pvio ranges */
  87         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  88                 NV_WR08(pNv->PVIO1, address, value);
  89         } else {
  90                 NV_WR08(pNv->PVIO0, address, value);
  91         }
  92 }
  93
  94 static void NVWriteMiscOut(xf86CrtcPtr crtc, CARD8 value)
  95 {
  96         NVWritePVIO(crtc, VGA_MISC_OUT_W, value);
  97 }
  98
  99 static CARD8 NVReadMiscOut(xf86CrtcPtr crtc)
 100 {
 101         return NVReadPVIO(crtc, VGA_MISC_OUT_R);
 102 }
 103
 104 void NVWriteVGA(NVPtr pNv, int head, CARD8 index, CARD8 value)
 105 {
 106         volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 107
 108         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 109         NV_WR08(pCRTCReg, CRTC_DATA, value);
 110 }
 111
 112 CARD8 NVReadVGA(NVPtr pNv, int head, CARD8 index)
 113 {
 114         volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 115
 116         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 117         return NV_RD08(pCRTCReg, CRTC_DATA);
 118 }
 119
 120 void NVWriteVgaCrtc(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 121 {
 122         ScrnInfoPtr pScrn = crtc->scrn;
 123         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 124         NVPtr pNv = NVPTR(pScrn);
 125
 126         NVWriteVGA(pNv, nv_crtc->head, index, value);
 127 }
 128
 129 CARD8 NVReadVgaCrtc(xf86CrtcPtr crtc, CARD8 index)
 130 {
 131         ScrnInfoPtr pScrn = crtc->scrn;
 132         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 133         NVPtr pNv = NVPTR(pScrn);
 134
 135         return NVReadVGA(pNv, nv_crtc->head, index);
 136 }
 137
 138 static void NVWriteVgaSeq(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 139 {
 140         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 141         NVWritePVIO(crtc, VGA_SEQ_DATA, value);
 142 }
 143
 144 static CARD8 NVReadVgaSeq(xf86CrtcPtr crtc, CARD8 index)
 145 {
 146         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 147         return NVReadPVIO(crtc, VGA_SEQ_DATA);
 148 }
 149
 150 static void NVWriteVgaGr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 151 {
 152         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 153         NVWritePVIO(crtc, VGA_GRAPH_DATA, value);
 154 }
 155
 156 static CARD8 NVReadVgaGr(xf86CrtcPtr crtc, CARD8 index)
 157 {
 158         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 159         return NVReadPVIO(crtc, VGA_GRAPH_DATA);
 160 }
 161
 162
 163 static void NVWriteVgaAttr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 164 {
 165   ScrnInfoPtr pScrn = crtc->scrn;
 166   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 167   NVPtr pNv = NVPTR(pScrn);
 168   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 169
 170   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 171   if (nv_crtc->paletteEnabled)
 172     index &= ~0x20;
 173   else
 174     index |= 0x20;
 175   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 176   NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
 177 }
 178
 179 static CARD8 NVReadVgaAttr(xf86CrtcPtr crtc, CARD8 index)
 180 {
 181   ScrnInfoPtr pScrn = crtc->scrn;
 182   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 183   NVPtr pNv = NVPTR(pScrn);
 184   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 185
 186   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 187   if (nv_crtc->paletteEnabled)
 188     index &= ~0x20;
 189   else
 190     index |= 0x20;
 191   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 192   return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
 193 }
 194
 195 void NVCrtcSetOwner(xf86CrtcPtr crtc)
 196 {
 197         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 198         ScrnInfoPtr pScrn = crtc->scrn;
 199         NVPtr pNv = NVPTR(pScrn);
 200         /* Non standard beheaviour required by NV11 */
 201         if (pNv) {
 202                 uint8_t owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 203                 ErrorF("pre-Owner: 0x%X\n", owner);
 204                 if (owner == 0x04) {
 205                         uint32_t pbus84 = nvReadMC(pNv, 0x1084);
 206                         ErrorF("pbus84: 0x%X\n", pbus84);
 207                         pbus84 &= ~(1<<28);
 208                         ErrorF("pbus84: 0x%X\n", pbus84);
 209                         nvWriteMC(pNv, 0x1084, pbus84);
 210                 }
 211                 /* The blob never writes owner to pcio1, so should we */
 212                 if (pNv->NVArch == 0x11) {
 213                         NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, 0xff);
 214                 }
 215                 NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, nv_crtc->crtc * 0x3);
 216                 owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 217                 ErrorF("post-Owner: 0x%X\n", owner);
 218         } else {
 219                 ErrorF("pNv pointer is NULL\n");
 220         }
 221 }
 222
 223 static void
 224 NVEnablePalette(xf86CrtcPtr crtc)
 225 {
 226   ScrnInfoPtr pScrn = crtc->scrn;
 227   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 228   NVPtr pNv = NVPTR(pScrn);
 229   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 230
 231   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 232   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
 233   nv_crtc->paletteEnabled = TRUE;
 234 }
 235
 236 static void
 237 NVDisablePalette(xf86CrtcPtr crtc)
 238 {
 239   ScrnInfoPtr pScrn = crtc->scrn;
 240   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 241   NVPtr pNv = NVPTR(pScrn);
 242   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 243
 244   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 245   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
 246   nv_crtc->paletteEnabled = FALSE;
 247 }
 248
 249 static void NVWriteVgaReg(xf86CrtcPtr crtc, CARD32 reg, CARD8 value)
 250 {
 251  ScrnInfoPtr pScrn = crtc->scrn;
 252   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 253   NVPtr pNv = NVPTR(pScrn);
 254   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 255
 256   NV_WR08(pCRTCReg, reg, value);
 257 }
 258
 259 /* perform a sequencer reset */
 260 static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
 261 {
 262   if (start)
 263     NVWriteVgaSeq(crtc, 0x00, 0x1);
 264   else
 265     NVWriteVgaSeq(crtc, 0x00, 0x3);
 266
 267 }
 268 static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
 269 {
 270         CARD8 tmp;
 271
 272         if (on) {
 273                 tmp = NVReadVgaSeq(crtc, 0x1);
 274                 NVVgaSeqReset(crtc, TRUE);
 275                 NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
 276
 277                 NVEnablePalette(crtc);
 278         } else {
 279                 /*
 280                  * Reenable sequencer, then turn on screen.
 281                  */
 282                 tmp = NVReadVgaSeq(crtc, 0x1);
 283                 NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20); /* reenable display */
 284                 NVVgaSeqReset(crtc, FALSE);
 285
 286                 NVDisablePalette(crtc);
 287         }
 288 }
 289
 290 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool Lock)
 291 {
 292         CARD8 cr11;
 293
 294         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57);
 295         cr11 = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE);
 296         if (Lock) cr11 |= 0x80;
 297         else cr11 &= ~0x80;
 298         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE, cr11);
 299 }
 300
 301 xf86OutputPtr
 302 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
 303 {
 304         ScrnInfoPtr pScrn = crtc->scrn;
 305         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 306         int i;
 307         for (i = 0; i < xf86_config->num_output; i++) {
 308                 xf86OutputPtr output = xf86_config->output[i];
 309
 310                 if (output->crtc == crtc) {
 311                         return output;
 312                 }
 313         }
 314
 315         return NULL;
 316 }
 317
 318 xf86CrtcPtr
 319 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
 320 {
 321         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 322         int i;
 323
 324         for (i = 0; i < xf86_config->num_crtc; i++) {
 325                 xf86CrtcPtr crtc = xf86_config->crtc[i];
 326                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 327                 if (nv_crtc->crtc == index)
 328                         return crtc;
 329         }
 330
 331         return NULL;
 332 }
 333
 334 /*
 335  * Calculate the Video Clock parameters for the PLL.
 336  */
 337 static void CalcVClock (
 338         uint32_t                clockIn,
 339         uint32_t                *clockOut,
 340         CARD32          *pllOut,
 341         NVPtr           pNv
 342 )
 343 {
 344         unsigned lowM, highM, highP;
 345         unsigned DeltaNew, DeltaOld;
 346         unsigned VClk, Freq;
 347         unsigned M, N, P;
 348
 349         /* M: PLL reference frequency postscaler divider */
 350         /* P: PLL VCO output postscaler divider */
 351         /* N: PLL VCO postscaler setting */
 352
 353         DeltaOld = 0xFFFFFFFF;
 354
 355         VClk = (unsigned)clockIn;
 356
 357         /* Taken from Haiku, after someone with an NV28 had an issue */
 358         switch(pNv->NVArch) {
 359                 case 0x28:
 360                         lowM = 1;
 361                         highP = 32;
 362                         if (VClk > 340000) {
 363                                 highM = 2;
 364                         } else if (VClk > 200000) {
 365                                 highM = 4;
 366                         } else if (VClk > 150000) {
 367                                 highM = 6;
 368                         } else {
 369                                 highM = 14;
 370                         }
 371                         break;
 372                 default:
 373                         lowM = 1;
 374                         highP = 16;
 375                         if (VClk > 340000) {
 376                                 highM = 2;
 377                         } else if (VClk > 250000) {
 378                                 highM = 6;
 379                         } else {
 380                                 highM = 14;
 381                         }
 382                         break;
 383         }
 384
 385         for (P = 1; P <= highP; P++) {
 386                 Freq = VClk << P;
 387                 if ((Freq >= 128000) && (Freq <= 350000)) {
 388                         for (M = lowM; M <= highM; M++) {
 389                                 N = ((VClk << P) * M) / pNv->CrystalFreqKHz;
 390                                 if (N <= 255) {
 391                                         Freq = ((pNv->CrystalFreqKHz * N) / M) >> P;
 392                                         if (Freq > VClk) {
 393                                                 DeltaNew = Freq - VClk;
 394                                         } else {
 395                                                 DeltaNew = VClk - Freq;
 396                                         }
 397                                         if (DeltaNew < DeltaOld) {
 398                                                 *pllOut   = (P << 16) | (N << 8) | M;
 399                                                 *clockOut = Freq;
 400                                                 DeltaOld  = DeltaNew;
 401                                         }
 402                                 }
 403                         }
 404                 }
 405         }
 406 }
 407
 408 static void CalcVClock2Stage (
 409         uint32_t                clockIn,
 410         uint32_t                *clockOut,
 411         CARD32          *pllOut,
 412         CARD32          *pllBOut,
 413         NVPtr           pNv
 414 )
 415 {
 416         unsigned DeltaNew, DeltaOld;
 417         unsigned VClk, Freq;
 418         unsigned M, N, P;
 419         unsigned lowM, highM, highP;
 420
 421         DeltaOld = 0xFFFFFFFF;
 422
 423         *pllBOut = 0x80000401;  /* fixed at x4 for now */
 424
 425         VClk = (unsigned)clockIn;
 426
 427         /* Taken from Haiku, after someone with an NV28 had an issue */
 428         switch(pNv->NVArch) {
 429                 case 0x28:
 430                         lowM = 1;
 431                         highP = 32;
 432                         if (VClk > 340000) {
 433                                 highM = 2;
 434                         } else if (VClk > 200000) {
 435                                 highM = 4;
 436                         } else if (VClk > 150000) {
 437                                 highM = 6;
 438                         } else {
 439                                 highM = 14;
 440                         }
 441                         break;
 442                 default:
 443                         lowM = 1;
 444                         highP = 15;
 445                         if (VClk > 340000) {
 446                                 highM = 2;
 447                         } else if (VClk > 250000) {
 448                                 highM = 6;
 449                         } else {
 450                                 highM = 14;
 451                         }
 452                         break;
 453         }
 454
 455         for (P = 0; P <= highP; P++) {
 456                 Freq = VClk << P;
 457                 if ((Freq >= 400000) && (Freq <= 1000000)) {
 458                         for (M = lowM; M <= highM; M++) {
 459                                 N = ((VClk << P) * M) / (pNv->CrystalFreqKHz << 2);
 460                                 if ((N >= 5) && (N <= 255)) {
 461                                         Freq = (((pNv->CrystalFreqKHz << 2) * N) / M) >> P;
 462                                         if (Freq > VClk) {
 463                                                 DeltaNew = Freq - VClk;
 464                                         } else {
 465                                                 DeltaNew = VClk - Freq;
 466                                         }
 467                                         if (DeltaNew < DeltaOld) {
 468                                                 *pllOut   = (P << 16) | (N << 8) | M;
 469                                                 *clockOut = Freq;
 470                                                 DeltaOld  = DeltaNew;
 471                                         }
 472                                 }
 473                         }
 474                 }
 475         }
 476 }
 477
 478 /* BIG NOTE: modifying vpll1 and vpll2 does not work, what bit is the switch to allow it? */
 479
 480 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
 481 /* They are only valid for NV4x, appearantly reordered for NV5x */
 482 /* gpu pll: 0x4000 + 0x4004
 483  * unknown pll: 0x4008 + 0x400c
 484  * vpll1: 0x4010 + 0x4014
 485  * vpll2: 0x4018 + 0x401c
 486  * unknown pll: 0x4020 + 0x4024
 487  * unknown pll: 0x4038 + 0x403c
 488  * Some of the unknown's are probably memory pll's.
 489  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
 490  * 1 and 2 refer to the registers of each pair. There is only one post divider.
 491  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
 492  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
 493  *     bit8: A switch that turns of the second divider and multiplier off.
 494  *     bit12: Also a switch, i haven't seen it yet.
 495  *     bit16-19: p-divider
 496  *     but 28-31: Something related to the mode that is used (see bit8).
 497  * 2) bit0-7: m-divider (a)
 498  *     bit8-15: n-multiplier (a)
 499  *     bit16-23: m-divider (b)
 500  *     bit24-31: n-multiplier (b)
 501  */
 502
 503 /* Modifying the gpu pll for example requires:
 504  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 505  * This is not needed for the vpll's which have their own bits.
 506  */
 507
 508 static void
 509 CalculateVClkNV4x(
 510         NVPtr pNv,
 511         uint32_t requested_clock,
 512         uint32_t *given_clock,
 513         uint32_t *pll_a,
 514         uint32_t *pll_b,
 515         uint32_t *reg580,
 516         Bool    *db1_ratio,
 517         Bool primary
 518 )
 519 {
 520         uint32_t DeltaOld, DeltaNew;
 521         uint32_t freq, temp;
 522         /* We have 2 mulitpliers, 2 dividers and one post divider */
 523         /* Note that p is only 4 bits */
 524         uint32_t m1, m2, n1, n2, p;
 525         uint32_t m1_best = 0, m2_best = 0, n1_best = 0, n2_best = 0, p_best = 0;
 526
 527         DeltaOld = 0xFFFFFFFF;
 528
 529         /* This is no solid limit, but a reasonable boundary */
 530         if (requested_clock < 120000) {
 531                 *db1_ratio = TRUE;
 532                 /* Turn the second set of divider and multiplier off */
 533                 /* Neutral settings */
 534                 n2 = 1;
 535                 m2 = 1;
 536         } else {
 537                 *db1_ratio = FALSE;
 538                 /* Fixed at x4 for the moment */
 539                 n2 = 4;
 540                 m2 = 1;
 541         }
 542
 543         n2_best = n2;
 544         m2_best = m2;
 545
 546         /* Single pll */
 547         if (*db1_ratio) {
 548                 temp = 0.4975 * 250000;
 549                 p = 0;
 550
 551                 while (requested_clock <= temp) {
 552                         temp /= 2;
 553                         p++;
 554                 }
 555
 556                 /* The minimum clock after m1 is 3 Mhz, and the clock is 27 Mhz, so m_max = 9 */
 557                 /* The maximum clock is 25 Mhz */
 558                 for (m1 = 2; m1 <= 9; m1++) {
 559                         n1 = ((requested_clock << p) * m1)/(pNv->CrystalFreqKHz);
 560                         //if (n1/m1 < 4 || n1/m1 > 10)
 561                         //      continue;
 562                         if (n1 > 0 && n1 <= 255) {
 563                                 freq = ((pNv->CrystalFreqKHz * n1)/m1) >> p;
 564                                 if (freq > requested_clock) {
 565                                         DeltaNew = freq - requested_clock;
 566                                 } else {
 567                                         DeltaNew = requested_clock - freq;
 568                                 }
 569                                 if (DeltaNew < DeltaOld) {
 570                                         m1_best = m1;
 571                                         n1_best = n1;
 572                                         p_best = p;
 573                                         DeltaOld = DeltaNew;
 574                                 }
 575                         }
 576                 }
 577         /* Dual pll */
 578         } else {
 579                 for (p = 0; p <= 6; p++) {
 580                         /* Assuming a fixed 2nd stage */
 581                         freq = requested_clock << p;
 582                         /* The maximum output frequency of stage 2 is allowed to be between 400 Mhz and 1 GHz */
 583                         if (freq > 400000 && freq < 1000000) {
 584                                 /* The minimum clock after m1 is 3 Mhz, and the clock is 27 Mhz, so m_max = 9 */
 585                                 /* The maximum clock is 25 Mhz */
 586                                 for (m1 = 2; m1 <= 9; m1++) {
 587                                         n1 = ((requested_clock << p) * m1 * m2)/(pNv->CrystalFreqKHz * n2);
 588                                         if (n1 >= 5 && n1 <= 255) {
 589                                                 freq = ((pNv->CrystalFreqKHz * n1 * n2)/(m1 * m2)) >> p;
 590                                                 if (freq > requested_clock) {
 591                                                         DeltaNew = freq - requested_clock;
 592                                                 } else {
 593                                                         DeltaNew = requested_clock - freq;
 594                                                 }
 595                                                 if (DeltaNew < DeltaOld) {
 596                                                         m1_best = m1;
 597                                                         n1_best = n1;
 598                                                         p_best = p;
 599                                                         DeltaOld = DeltaNew;
 600                                                 }
 601                                         }
 602                                 }
 603                         }
 604                 }
 605         }
 606
 607         if (*db1_ratio) {
 608                 /* Bogus data, the same nvidia uses */
 609                 n2_best = 1;
 610                 m2_best = 31;
 611         }
 612
 613         /* What exactly are the purpose of bit30 (a) and bit31(b)? */
 614         *pll_a = (1 << 30) | (p_best << 16) | (n1_best << 8) | (m1_best << 0);
 615         *pll_b = (1 << 31) | (n2_best << 8) | (m2_best << 0);
 616
 617         if (*db1_ratio) {
 618                 if (primary) {
 619                         *reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 620                 } else {
 621                         *reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 622                 }
 623         } else {
 624                 if (primary) {
 625                         *reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
 626                 } else {
 627                         *reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
 628                 }
 629         }
 630
 631         if (*db1_ratio) {
 632                 ErrorF("vpll: n1 %d m1 %d p %d db1_ratio %d\n", n1_best, m1_best, p_best, *db1_ratio);
 633         } else {
 634                 ErrorF("vpll: n1 %d n2 %d m1 %d m2 %d p %d db1_ratio %d\n", n1_best, n2_best, m1_best, m2_best, p_best, *db1_ratio);
 635         }
 636 }
 637
 638 static void nv40_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 639 {
 640         state->vpll1_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 641         state->vpll1_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 642         state->vpll2_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 643         state->vpll2_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 644         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 645         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 646         state->reg580 = nvReadRAMDAC0(pNv, NV_RAMDAC_580);
 647 }
 648
 649 static void nv40_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 650 {
 651         CARD32 fp_debug_0[2];
 652         uint32_t index[2];
 653         fp_debug_0[0] = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
 654         fp_debug_0[1] = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
 655
 656         /* The TMDS_PLL switch is on the actual ramdac */
 657         if (state->crosswired) {
 658                 index[0] = 1;
 659                 index[1] = 0;
 660                 ErrorF("Crosswired pll state load\n");
 661         } else {
 662                 index[0] = 0;
 663                 index[1] = 1;
 664         }
 665
 666         if (state->vpll2_b) {
 667                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0,
 668                         fp_debug_0[index[1]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 669
 670                 /* Wait for the situation to stabilise */
 671                 usleep(5000);
 672
 673                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 674                 /* for vpll2 change bits 18 and 19 are disabled */
 675                 reg_c040 &= ~(0x3 << 18);
 676                 nvWriteMC(pNv, 0xc040, reg_c040);
 677
 678                 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 679                 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 680
 681                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2_a);
 682                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 683
 684                 ErrorF("writing pllsel %08X\n", state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 685                 /* Let's keep the primary vpll off */
 686                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 687
 688                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 689                 ErrorF("writing reg580 %08X\n", state->reg580);
 690
 691                 /* We need to wait a while */
 692                 usleep(5000);
 693                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 694
 695                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[1]]);
 696
 697                 /* Wait for the situation to stabilise */
 698                 usleep(5000);
 699         }
 700
 701         if (state->vpll1_b) {
 702                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0,
 703                         fp_debug_0[index[0]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 704
 705                 /* Wait for the situation to stabilise */
 706                 usleep(5000);
 707
 708                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 709                 /* for vpll2 change bits 16 and 17 are disabled */
 710                 reg_c040 &= ~(0x3 << 16);
 711                 nvWriteMC(pNv, 0xc040, reg_c040);
 712
 713                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 714                 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 715
 716                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll1_a);
 717                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpll1_b);
 718
 719                 ErrorF("writing pllsel %08X\n", state->pllsel);
 720                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 721
 722                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 723                 ErrorF("writing reg580 %08X\n", state->reg580);
 724
 725                 /* We need to wait a while */
 726                 usleep(5000);
 727                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 728
 729                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[0]]);
 730
 731                 /* Wait for the situation to stabilise */
 732                 usleep(5000);
 733         }
 734
 735         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 736         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 737 }
 738
 739 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 740 {
 741         state->vpll = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 742         if(pNv->twoHeads) {
 743                 state->vpll2 = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 744         }
 745         if(pNv->twoStagePLL) {
 746                 state->vpllB = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 747                 state->vpll2B = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 748         }
 749         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 750         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 751 }
 752
 753
 754 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 755 {
 756         if (state->vpll2) {
 757                 if(pNv->twoHeads) {
 758                         ErrorF("writing vpll2 %08X\n", state->vpll2);
 759                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2);
 760                 }
 761                 if(pNv->twoStagePLL) {
 762                         ErrorF("writing vpll2B %08X\n", state->vpll2B);
 763                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2B);
 764                 }
 765
 766                 ErrorF("writing pllsel %08X\n", state->pllsel);
 767                 /* Let's keep the primary vpll off */
 768                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 769         }
 770
 771         if (state->vpll) {
 772                 ErrorF("writing vpll %08X\n", state->vpll);
 773                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll);
 774                 if(pNv->twoStagePLL) {
 775                         ErrorF("writing vpllB %08X\n", state->vpllB);
 776                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpllB);
 777                 }
 778
 779                 ErrorF("writing pllsel %08X\n", state->pllsel);
 780                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 781         }
 782
 783         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 784         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 785 }
 786
 787 /*
 788  * Calculate extended mode parameters (SVGA) and save in a
 789  * mode state structure.
 790  */
 791 void nv_crtc_calc_state_ext(
 792         xf86CrtcPtr     crtc,
 793         int                     bpp,
 794         int                     DisplayWidth, /* Does this change after setting the mode? */
 795         int                     CrtcHDisplay,
 796         int                     CrtcVDisplay,
 797         int                     dotClock,
 798         int                     flags
 799 )
 800 {
 801         ScrnInfoPtr pScrn = crtc->scrn;
 802         uint32_t pixelDepth, VClk = 0;
 803         CARD32 CursorStart;
 804         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 805         xf86CrtcConfigPtr   xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 806         NVCrtcRegPtr regp;
 807         NVPtr pNv = NVPTR(pScrn);
 808         RIVA_HW_STATE *state;
 809         int num_crtc_enabled, i;
 810
 811         state = &pNv->ModeReg;
 812
 813         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 814
 815         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 816         NVOutputPrivatePtr nv_output = output->driver_private;
 817
 818         /*
 819          * Extended RIVA registers.
 820          */
 821         pixelDepth = (bpp + 1)/8;
 822         if (pNv->Architecture == NV_ARCH_40) {
 823                 /* Does register 0x580 already have a value? */
 824                 if (!state->reg580) {
 825                         state->reg580 = pNv->misc_info.ramdac_0_reg_580;
 826                 }
 827                 if (nv_output->ramdac == 1) {
 828                         CalculateVClkNV4x(pNv, dotClock, &VClk, &state->vpll2_a, &state->vpll2_b, &state->reg580, &state->db1_ratio[1], FALSE);
 829                 } else {
 830                         CalculateVClkNV4x(pNv, dotClock, &VClk, &state->vpll1_a, &state->vpll1_b, &state->reg580, &state->db1_ratio[0], TRUE);
 831                 }
 832         } else if (pNv->twoStagePLL) {
 833                 CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB, pNv);
 834         } else {
 835                 CalcVClock(dotClock, &VClk, &state->pll, pNv);
 836         }
 837
 838         switch (pNv->Architecture) {
 839         case NV_ARCH_04:
 840                 nv4UpdateArbitrationSettings(VClk,
 841                                                 pixelDepth * 8,
 842                                                 &(state->arbitration0),
 843                                                 &(state->arbitration1),
 844                                                 pNv);
 845                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
 846                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
 847                 if (flags & V_DBLSCAN)
 848                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 849                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
 850                 state->pllsel   |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
 851                 state->config   = 0x00001114;
 852                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 853                 break;
 854         case NV_ARCH_10:
 855         case NV_ARCH_20:
 856         case NV_ARCH_30:
 857         default:
 858                 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
 859                         ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
 860                         state->arbitration0 = 128;
 861                         state->arbitration1 = 0x0480;
 862                 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
 863                         ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
 864                         nForceUpdateArbitrationSettings(VClk,
 865                                                 pixelDepth * 8,
 866                                                 &(state->arbitration0),
 867                                                 &(state->arbitration1),
 868                                                 pNv);
 869                 } else if (pNv->Architecture < NV_ARCH_30) {
 870                         nv10UpdateArbitrationSettings(VClk,
 871                                                 pixelDepth * 8,
 872                                                 &(state->arbitration0),
 873                                                 &(state->arbitration1),
 874                                                 pNv);
 875                 } else {
 876                         nv30UpdateArbitrationSettings(pNv,
 877                                                 &(state->arbitration0),
 878                                                 &(state->arbitration1));
 879                 }
 880
 881                 CursorStart = pNv->Cursor->offset;
 882
 883                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
 884                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
 885                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
 886
 887                 if (flags & V_DBLSCAN)
 888                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 889
 890                 state->config   = nvReadFB(pNv, NV_PFB_CFG0);
 891                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 892                 break;
 893         }
 894
 895         /* okay do we have 2 CRTCs running ? */
 896         num_crtc_enabled = 0;
 897         for (i = 0; i < xf86_config->num_crtc; i++) {
 898                 if (xf86_config->crtc[i]->enabled) {
 899                         num_crtc_enabled++;
 900                 }
 901         }
 902
 903         ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
 904
 905         if (pNv->Architecture < NV_ARCH_40) {
 906                 /* We need this before the next code */
 907                 if (nv_crtc->crtc == 1) {
 908                         state->vpll2 = state->pll;
 909                         state->vpll2B = state->pllB;
 910                 } else {
 911                         state->vpll = state->pll;
 912                         state->vpllB = state->pllB;
 913                 }
 914         }
 915
 916         if (pNv->Architecture == NV_ARCH_40) {
 917                 /* This register is only used on the primary ramdac */
 918                 /* This seems to be needed to select the proper clocks, otherwise bad things happen */
 919                 /* Assumption CRTC1 will overwrite the CRTC0 value */
 920                 /* Also make sure we don't set both bits */
 921
 922                 if (!state->sel_clk)
 923                         state->sel_clk = pNv->misc_info.sel_clk & ~(0xf << 16);
 924
 925                 if (nv_output->type == OUTPUT_TMDS) {
 926                         /* Clean out all the bits and enable another mode */
 927                         if (nv_crtc->head == 1) {
 928                                 state->sel_clk &= ~(0xf << 16);
 929                                 state->sel_clk |= (1 << 18);
 930                         } else {
 931                                 state->sel_clk &= ~(0xf << 16);
 932                                 state->sel_clk |= (1 << 16);
 933                         }
 934                 } else {
 935                         /* Only unset the specific bits that would have been set if we were a TMDS */
 936                         if (nv_crtc->head == 1) {
 937                                 state->sel_clk &= ~(0x4 << 16);
 938                         } else {
 939                                 state->sel_clk &= ~(0x1 << 16);
 940                         }
 941                 }
 942
 943                 /* Are we a TMDS running on head 0(=ramdac 0), but native to ramdac 1? */
 944                 if (nv_crtc->head == 0 && nv_output->type == OUTPUT_TMDS && nv_output->valid_ramdac & RAMDAC_1) {
 945                         state->crosswired = TRUE;
 946                 } else if (nv_crtc->head == 0) {
 947                         state->crosswired = FALSE;
 948                 }
 949
 950                 if (nv_crtc->head == 1) {
 951                         if (state->db1_ratio[1])
 952                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
 953                 } else if (nv_crtc->head == 0) {
 954                         if (state->db1_ratio[0])
 955                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
 956                 }
 957         } else {
 958                 /* This seems true for nv34 */
 959                 state->sel_clk = 0x0;
 960                 state->crosswired = FALSE;
 961         }
 962
 963         if (nv_output->ramdac == 1) {
 964                 if (!state->db1_ratio[1]) {
 965                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 966                 } else {
 967                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 968                 }
 969                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
 970         } else {
 971                 if (pNv->Architecture < NV_ARCH_40)
 972                         state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
 973                 else
 974                         state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
 975                 if (!state->db1_ratio[0]) {
 976                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 977                 } else {
 978                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 979                 }
 980         }
 981
 982         /* The purpose is unknown */
 983         //if (pNv->Architecture == NV_ARCH_40)
 984         //      state->pllsel |= (1 << 2);
 985
 986         regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
 987         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
 988         if (pNv->Architecture >= NV_ARCH_30) {
 989                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
 990         }
 991
 992         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
 993         regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
 994 }
 995
 996 static void
 997 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
 998 {
 999         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1000         ScrnInfoPtr pScrn = crtc->scrn;
1001         NVPtr pNv = NVPTR(pScrn);
1002         unsigned char seq1 = 0, crtc17 = 0;
1003         unsigned char crtc1A;
1004
1005         ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->crtc, mode);
1006
1007         NVCrtcSetOwner(crtc);
1008
1009         crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
1010         switch(mode) {
1011                 case DPMSModeStandby:
1012                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
1013                 seq1 = 0x20;
1014                 crtc17 = 0x80;
1015                 crtc1A |= 0x80;
1016                 break;
1017         case DPMSModeSuspend:
1018                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
1019                 seq1 = 0x20;
1020                 crtc17 = 0x80;
1021                 crtc1A |= 0x40;
1022                 break;
1023         case DPMSModeOff:
1024                 /* Screen: Off; HSync: Off, VSync: Off */
1025                 seq1 = 0x20;
1026                 crtc17 = 0x00;
1027                 crtc1A |= 0xC0;
1028                 break;
1029         case DPMSModeOn:
1030         default:
1031                 /* Screen: On; HSync: On, VSync: On */
1032                 seq1 = 0x00;
1033                 crtc17 = 0x80;
1034                 break;
1035         }
1036
1037         NVVgaSeqReset(crtc, TRUE);
1038         /* Each head has it's own sequencer, so we can turn it off when we want */
1039         seq1 |= (NVReadVgaSeq(crtc, 0x01) & ~0x20);
1040         NVWriteVgaSeq(crtc, 0x1, seq1);
1041         crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
1042         usleep(10000);
1043         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
1044         NVVgaSeqReset(crtc, FALSE);
1045
1046         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
1047
1048         /* I hope this is the right place */
1049         if (crtc->enabled && mode == DPMSModeOn) {
1050                 pNv->crtc_active[nv_crtc->head] = TRUE;
1051         } else {
1052                 pNv->crtc_active[nv_crtc->head] = FALSE;
1053         }
1054 }
1055
1056 static Bool
1057 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
1058                      DisplayModePtr adjusted_mode)
1059 {
1060         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1061         ScrnInfoPtr pScrn = crtc->scrn;
1062         NVPtr pNv = NVPTR(pScrn);
1063         ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->crtc);
1064
1065         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1066         NVOutputPrivatePtr nv_output = output->driver_private;
1067
1068         /* For internal panels and gpu scaling on DVI we need the native mode */
1069         if ((nv_output->type == OUTPUT_LVDS) || (pNv->fpScaler && (nv_output->type == OUTPUT_TMDS))) {
1070                 adjusted_mode->HDisplay = nv_output->native_mode->HDisplay;
1071                 adjusted_mode->HSkew = nv_output->native_mode->HSkew;
1072                 adjusted_mode->HSyncStart = nv_output->native_mode->HSyncStart;
1073                 adjusted_mode->HSyncEnd = nv_output->native_mode->HSyncEnd;
1074                 adjusted_mode->HTotal = nv_output->native_mode->HTotal;
1075                 adjusted_mode->VDisplay = nv_output->native_mode->VDisplay;
1076                 adjusted_mode->VScan = nv_output->native_mode->VScan;
1077                 adjusted_mode->VSyncStart = nv_output->native_mode->VSyncStart;
1078                 adjusted_mode->VSyncEnd = nv_output->native_mode->VSyncEnd;
1079                 adjusted_mode->VTotal = nv_output->native_mode->VTotal;
1080                 adjusted_mode->Clock = nv_output->native_mode->Clock;
1081
1082                 xf86SetModeCrtc(adjusted_mode, INTERLACE_HALVE_V);
1083         }
1084
1085         return TRUE;
1086 }
1087
1088 static void
1089 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode)
1090 {
1091         ScrnInfoPtr pScrn = crtc->scrn;
1092         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1093         NVCrtcRegPtr regp;
1094         NVPtr pNv = NVPTR(pScrn);
1095         int depth = pScrn->depth;
1096         unsigned int i;
1097
1098         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1099
1100         /*
1101         * compute correct Hsync & Vsync polarity
1102         */
1103         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
1104                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
1105
1106                 regp->MiscOutReg = 0x23;
1107                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
1108                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
1109         } else {
1110                 int VDisplay = mode->VDisplay;
1111                 if (mode->Flags & V_DBLSCAN)
1112                         VDisplay *= 2;
1113                 if (mode->VScan > 1)
1114                         VDisplay *= mode->VScan;
1115                 if (VDisplay < 400) {
1116                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
1117                 } else if (VDisplay < 480) {
1118                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
1119                 } else if (VDisplay < 768) {
1120                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
1121                 } else {
1122                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
1123                 }
1124         }
1125
1126         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
1127
1128         /*
1129         * Time Sequencer
1130         */
1131         if (depth == 4) {
1132                 regp->Sequencer[0] = 0x02;
1133         } else {
1134                 regp->Sequencer[0] = 0x00;
1135         }
1136         /* 0x20 disables the sequencer */
1137         if (mode->Flags & V_CLKDIV2) {
1138                 regp->Sequencer[1] = 0x29;
1139         } else {
1140                 regp->Sequencer[1] = 0x21;
1141         }
1142         if (depth == 1) {
1143                 regp->Sequencer[2] = 1 << BIT_PLANE;
1144         } else {
1145                 regp->Sequencer[2] = 0x0F;
1146                 regp->Sequencer[3] = 0x00;                     /* Font select */
1147         }
1148         if (depth < 8) {
1149                 regp->Sequencer[4] = 0x06;                             /* Misc */
1150         } else {
1151                 regp->Sequencer[4] = 0x0E;                             /* Misc */
1152         }
1153
1154         /*
1155         * CRTC Controller
1156         */
1157         regp->CRTC[0]  = (mode->CrtcHTotal >> 3) - 5;
1158         regp->CRTC[1]  = (mode->CrtcHDisplay >> 3) - 1;
1159         regp->CRTC[2]  = (mode->CrtcHBlankStart >> 3) - 1;
1160         regp->CRTC[3]  = (((mode->CrtcHBlankEnd >> 3) - 1) & 0x1F) | 0x80;
1161         i = (((mode->CrtcHSkew << 2) + 0x10) & ~0x1F);
1162         if (i < 0x80) {
1163                 regp->CRTC[3] |= i;
1164         }
1165         regp->CRTC[4]  = (mode->CrtcHSyncStart >> 3);
1166         regp->CRTC[5]  = ((((mode->CrtcHBlankEnd >> 3) - 1) & 0x20) << 2)
1167         | (((mode->CrtcHSyncEnd >> 3)) & 0x1F);
1168         regp->CRTC[6]  = (mode->CrtcVTotal - 2) & 0xFF;
1169         regp->CRTC[7]  = (((mode->CrtcVTotal - 2) & 0x100) >> 8)
1170                         | (((mode->CrtcVDisplay - 1) & 0x100) >> 7)
1171                         | ((mode->CrtcVSyncStart & 0x100) >> 6)
1172                         | (((mode->CrtcVBlankStart - 1) & 0x100) >> 5)
1173                         | 0x10
1174                         | (((mode->CrtcVTotal - 2) & 0x200)   >> 4)
1175                         | (((mode->CrtcVDisplay - 1) & 0x200) >> 3)
1176                         | ((mode->CrtcVSyncStart & 0x200) >> 2);
1177         regp->CRTC[8]  = 0x00;
1178         regp->CRTC[9]  = (((mode->CrtcVBlankStart - 1) & 0x200) >> 4) | 0x40;
1179         if (mode->Flags & V_DBLSCAN) {
1180                 regp->CRTC[9] |= 0x80;
1181         }
1182         if (mode->VScan >= 32) {
1183                 regp->CRTC[9] |= 0x1F;
1184         } else if (mode->VScan > 1) {
1185                 regp->CRTC[9] |= mode->VScan - 1;
1186         }
1187         regp->CRTC[10] = 0x00;
1188         regp->CRTC[11] = 0x00;
1189         regp->CRTC[12] = 0x00;
1190         regp->CRTC[13] = 0x00;
1191         regp->CRTC[14] = 0x00;
1192         regp->CRTC[15] = 0x00;
1193         regp->CRTC[16] = mode->CrtcVSyncStart & 0xFF;
1194         regp->CRTC[17] = (mode->CrtcVSyncEnd & 0x0F) | 0x20;
1195         regp->CRTC[18] = (mode->CrtcVDisplay - 1) & 0xFF;
1196         regp->CRTC[19] = mode->CrtcHDisplay >> 4;  /* just a guess */
1197         regp->CRTC[20] = 0x00;
1198         regp->CRTC[21] = (mode->CrtcVBlankStart - 1) & 0xFF;
1199         regp->CRTC[22] = (mode->CrtcVBlankEnd - 1) & 0xFF;
1200         /* 0x80 enables the sequencer, we don't want that */
1201         if (depth < 8) {
1202                 regp->CRTC[23] = 0xE3 & ~0x80;
1203         } else {
1204                 regp->CRTC[23] = 0xC3 & ~0x80;
1205         }
1206         regp->CRTC[24] = 0xFF;
1207
1208         /*
1209         * Theory resumes here....
1210         */
1211
1212         /*
1213         * Graphics Display Controller
1214         */
1215         regp->Graphics[0] = 0x00;
1216         regp->Graphics[1] = 0x00;
1217         regp->Graphics[2] = 0x00;
1218         regp->Graphics[3] = 0x00;
1219         if (depth == 1) {
1220                 regp->Graphics[4] = BIT_PLANE;
1221                 regp->Graphics[5] = 0x00;
1222         } else {
1223                 regp->Graphics[4] = 0x00;
1224                 if (depth == 4) {
1225                         regp->Graphics[5] = 0x02;
1226                 } else {
1227                         regp->Graphics[5] = 0x40;
1228                 }
1229         }
1230         regp->Graphics[6] = 0x05;   /* only map 64k VGA memory !!!! */
1231         regp->Graphics[7] = 0x0F;
1232         regp->Graphics[8] = 0xFF;
1233
1234         if (depth == 1) {
1235                 /* Initialise the Mono map according to which bit-plane gets used */
1236
1237                 Bool flipPixels = xf86GetFlipPixels();
1238
1239                 for (i=0; i<16; i++) {
1240                         if (((i & (1 << BIT_PLANE)) != 0) != flipPixels) {
1241                                 regp->Attribute[i] = WHITE_VALUE;
1242                         } else {
1243                                 regp->Attribute[i] = BLACK_VALUE;
1244                         }
1245                 }
1246
1247         } else {
1248                 regp->Attribute[0]  = 0x00; /* standard colormap translation */
1249                 regp->Attribute[1]  = 0x01;
1250                 regp->Attribute[2]  = 0x02;
1251                 regp->Attribute[3]  = 0x03;
1252                 regp->Attribute[4]  = 0x04;
1253                 regp->Attribute[5]  = 0x05;
1254                 regp->Attribute[6]  = 0x06;
1255                 regp->Attribute[7]  = 0x07;
1256                 regp->Attribute[8]  = 0x08;
1257                 regp->Attribute[9]  = 0x09;
1258                 regp->Attribute[10] = 0x0A;
1259                 regp->Attribute[11] = 0x0B;
1260                 regp->Attribute[12] = 0x0C;
1261                 regp->Attribute[13] = 0x0D;
1262                 regp->Attribute[14] = 0x0E;
1263                 regp->Attribute[15] = 0x0F;
1264                 if (depth == 4) {
1265                         regp->Attribute[16] = 0x81; /* wrong for the ET4000 */
1266                 } else {
1267                         regp->Attribute[16] = 0x41; /* wrong for the ET4000 */
1268                 }
1269                 if (depth > 4) {
1270                         regp->Attribute[17] = 0xff;
1271                 }
1272                 /* Attribute[17] (overscan) initialised in vgaHWGetHWRec() */
1273         }
1274         regp->Attribute[18] = 0x0F;
1275         regp->Attribute[19] = 0x00;
1276         regp->Attribute[20] = 0x00;
1277 }
1278
1279 #define MAX_H_VALUE(i) ((0x1ff + i) << 3)
1280 #define MAX_V_VALUE(i) ((0xfff + i) << 0)
1281
1282 /**
1283  * Sets up registers for the given mode/adjusted_mode pair.
1284  *
1285  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1286  *
1287  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1288  * be easily turned on/off after this.
1289  */
1290 static void
1291 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1292 {
1293         ScrnInfoPtr pScrn = crtc->scrn;
1294         NVPtr pNv = NVPTR(pScrn);
1295         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
1296         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1297         NVFBLayout *pLayout = &pNv->CurrentLayout;
1298         NVCrtcRegPtr regp, savep;
1299         unsigned int i;
1300
1301         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
1302         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
1303         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
1304         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
1305         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
1306         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
1307         int vertDisplay         = mode->CrtcVDisplay                    - 1;
1308         int vertStart           = mode->CrtcVSyncStart          - 1;
1309         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
1310         int vertTotal           = mode->CrtcVTotal                      - 2;
1311         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
1312         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
1313
1314         Bool is_fp = FALSE;
1315
1316         xf86OutputPtr  output;
1317         NVOutputPrivatePtr nv_output;
1318         for (i = 0; i < xf86_config->num_output; i++) {
1319                 output = xf86_config->output[i];
1320                 nv_output = output->driver_private;
1321
1322                 if (output->crtc == crtc) {
1323                         if ((nv_output->type == OUTPUT_LVDS) ||
1324                                 (nv_output->type == OUTPUT_TMDS)) {
1325
1326                                 is_fp = TRUE;
1327                                 break;
1328                         }
1329                 }
1330         }
1331
1332         ErrorF("Mode clock: %d\n", mode->Clock);
1333         ErrorF("Adjusted mode clock: %d\n", adjusted_mode->Clock);
1334
1335         ErrorF("crtc: Pre-sync workaround\n");
1336         /* Reverted to what nv did, because that works for all resolutions on flatpanels */
1337         if (is_fp) {
1338                 vertStart = vertTotal - 3;
1339                 vertEnd = vertTotal - 2;
1340                 vertBlankStart = vertStart;
1341                 horizStart = horizTotal - 5;
1342                 horizEnd = horizTotal - 2;
1343                 horizBlankEnd = horizTotal + 4;
1344                 if (pNv->overlayAdaptor) {
1345                         /* This reportedly works around Xv some overlay bandwidth problems*/
1346                         horizTotal += 2;
1347                 }
1348         }
1349         ErrorF("crtc: Post-sync workaround\n");
1350
1351         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
1352         ErrorF("horizStart: 0x%X \n", horizStart);
1353         ErrorF("horizEnd: 0x%X \n", horizEnd);
1354         ErrorF("horizTotal: 0x%X \n", horizTotal);
1355         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
1356         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
1357         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
1358         ErrorF("vertStart: 0x%X \n", vertStart);
1359         ErrorF("vertEnd: 0x%X \n", vertEnd);
1360         ErrorF("vertTotal: 0x%X \n", vertTotal);
1361         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
1362         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
1363
1364         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1365         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1366
1367         if(mode->Flags & V_INTERLACE)
1368                 vertTotal |= 1;
1369
1370         regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
1371         regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
1372         regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
1373         regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0)
1374                                 | SetBit(7);
1375         regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
1376         regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
1377                                 | SetBitField(horizEnd,4:0,4:0);
1378         regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
1379         regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
1380                                 | SetBitField(vertDisplay,8:8,1:1)
1381                                 | SetBitField(vertStart,8:8,2:2)
1382                                 | SetBitField(vertBlankStart,8:8,3:3)
1383                                 | SetBit(4)
1384                                 | SetBitField(vertTotal,9:9,5:5)
1385                                 | SetBitField(vertDisplay,9:9,6:6)
1386                                 | SetBitField(vertStart,9:9,7:7);
1387         regp->CRTC[NV_VGA_CRTCX_MAXSCLIN]  = SetBitField(vertBlankStart,9:9,5:5)
1388                                 | SetBit(6)
1389                                 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00);
1390         regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
1391         regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
1392         regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
1393         regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
1394         regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
1395         regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
1396         /* Not an extended register */
1397         regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
1398
1399         regp->Attribute[0x10] = 0x01;
1400         /* Blob sets this for normal monitors as well */
1401         regp->Attribute[0x11] = 0x00;
1402
1403         regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
1404                                 | SetBitField(vertBlankStart,10:10,3:3)
1405                                 | SetBitField(vertStart,10:10,2:2)
1406                                 | SetBitField(vertDisplay,10:10,1:1)
1407                                 | SetBitField(vertTotal,10:10,0:0);
1408
1409         regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
1410                                 | SetBitField(horizDisplay,8:8,1:1)
1411                                 | SetBitField(horizBlankStart,8:8,2:2)
1412                                 | SetBitField(horizStart,8:8,3:3);
1413
1414         regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
1415                                 | SetBitField(vertDisplay,11:11,2:2)
1416                                 | SetBitField(vertStart,11:11,4:4)
1417                                 | SetBitField(vertBlankStart,11:11,6:6);
1418
1419         if(mode->Flags & V_INTERLACE) {
1420                 horizTotal = (horizTotal >> 1) & ~1;
1421                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
1422                 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
1423         } else {
1424                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff;  /* interlace off */
1425         }
1426
1427         /* bit2 = 0 -> fine pitched crtc granularity */
1428         /* The rest disables double buffering on CRTC access */
1429         regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
1430
1431         if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
1432                 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1433                 if (nv_crtc->head == 0) {
1434                         regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1435                 }
1436
1437                 if (is_fp) {
1438                         regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0) | (1 << 1);
1439                 }
1440         } else {
1441                 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
1442                 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
1443         }
1444
1445         /* I'm trusting haiku driver on this one, they say it enables an external TDMS clock */
1446         if (is_fp) {
1447                 regp->CRTC[NV_VGA_CRTCX_59] = 0x1;
1448         } else {
1449                 regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1450         }
1451
1452         /*
1453         * Initialize DAC palette.
1454         */
1455         if(pLayout->bitsPerPixel != 8 ) {
1456                 for (i = 0; i < 256; i++) {
1457                         regp->DAC[i*3]     = i;
1458                         regp->DAC[(i*3)+1] = i;
1459                         regp->DAC[(i*3)+2] = i;
1460                 }
1461         }
1462
1463         /*
1464         * Calculate the extended registers.
1465         */
1466
1467         if(pLayout->depth < 24) {
1468                 i = pLayout->depth;
1469         } else {
1470                 i = 32;
1471         }
1472
1473         if(pNv->Architecture >= NV_ARCH_10) {
1474                 pNv->CURSOR = (CARD32 *)pNv->Cursor->map;
1475         }
1476
1477         ErrorF("crtc %d %d %d\n", nv_crtc->crtc, mode->CrtcHDisplay, pScrn->displayWidth);
1478         nv_crtc_calc_state_ext(crtc,
1479                                 i,
1480                                 pScrn->displayWidth,
1481                                 mode->CrtcHDisplay,
1482                                 mode->CrtcVDisplay,
1483                                 adjusted_mode->Clock,
1484                                 mode->Flags);
1485
1486         /* Enable slaved mode */
1487         if (is_fp) {
1488                 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1489         }
1490
1491         /* What is the meaning of this register? */
1492         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1493         regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
1494
1495         /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1496         /* But what are those special conditions? */
1497         if (pNv->Architecture <= NV_ARCH_30) {
1498                 if (is_fp) {
1499                         if(nv_crtc->head == 1) {
1500                                 regp->head |= NV_CRTC_FSEL_FPP1;
1501                         } else if (pNv->twoHeads) {
1502                                 regp->head |= NV_CRTC_FSEL_FPP2;
1503                         }
1504                 }
1505         } else {
1506                 /* This is observed on some g70 cards, non-flatpanel's too */
1507                 if (nv_crtc->head == 1) {
1508                         regp->head |= NV_CRTC_FSEL_FPP2;
1509                 }
1510         }
1511
1512         /* Except for rare conditions I2C is enabled on the primary crtc */
1513         if (nv_crtc->head == 0) {
1514                 if (pNv->overlayAdaptor) {
1515                         regp->head |= NV_CRTC_FSEL_OVERLAY;
1516                 }
1517                 regp->head |= NV_CRTC_FSEL_I2C;
1518         }
1519
1520         regp->cursorConfig = 0x00000100;
1521         if(mode->Flags & V_DBLSCAN)
1522                 regp->cursorConfig |= (1 << 4);
1523         if(pNv->alphaCursor) {
1524                 if((pNv->Chipset & 0x0ff0) != CHIPSET_NV11) {
1525                         regp->cursorConfig |= 0x04011000;
1526                 } else {
1527                         regp->cursorConfig |= 0x14011000;
1528                 }
1529         } else {
1530                 regp->cursorConfig |= 0x02000000;
1531         }
1532
1533         /* Unblock some timings */
1534         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1535         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1536
1537         /* 0x20 seems to be enabled and 0x14 disabled */
1538         regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1539
1540         /* 0x00 is disabled, 0x22 crt and 0x88 dfp */
1541         /* 0x11 is LVDS? */
1542         if (is_fp) {
1543                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1544         } else {
1545                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1546         }
1547
1548         /* These values seem to vary */
1549         regp->CRTC[NV_VGA_CRTCX_3C] = savep->CRTC[NV_VGA_CRTCX_3C];
1550
1551         /* 0x80 seems to be used very often, if not always */
1552         regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1553
1554         /* Are these(0x55 and 0x56) also timing related registers, since disabling them does nothing? */
1555         regp->CRTC[NV_VGA_CRTCX_55] = 0x0;
1556
1557         /* Common values like 0x14 and 0x04 are converted to 0x10 and 0x00 */
1558         //regp->CRTC[NV_VGA_CRTCX_56] = savep->CRTC[NV_VGA_CRTCX_56] & ~(1<<4);
1559         regp->CRTC[NV_VGA_CRTCX_56] = 0x0;
1560
1561         regp->CRTC[NV_VGA_CRTCX_57] = 0x0;
1562
1563         /* bit0: Seems to be mostly used on crtc1 */
1564         /* bit1: 1=crtc1, 0=crtc, but i'm unsure about this */
1565         /* 0x7E (crtc0, only seen in one dump) and 0x7F (crtc1) seem to be some kind of disable setting */
1566         /* This is likely to be incomplete */
1567         /* This is a very strange register, changed very often by the blob */
1568         regp->CRTC[NV_VGA_CRTCX_58] = 0x0;
1569
1570         /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1*/
1571         if (nv_crtc->head == 1) {
1572                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52;
1573         } else {
1574                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52 + 4;
1575         }
1576
1577         /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1578         regp->unk81c = nvReadCRTC0(pNv, NV_CRTC_081C);
1579
1580         regp->unk830 = mode->CrtcVDisplay - 3;
1581         regp->unk834 = mode->CrtcVDisplay - 1;
1582
1583         /* This is what the blob does */
1584         regp->unk850 = nvReadCRTC(pNv, 0, NV_CRTC_0850);
1585
1586         /* Never ever modify gpio, unless you know very well what you're doing */
1587         regp->gpio = nvReadCRTC(pNv, 0, NV_CRTC_GPIO);
1588 }
1589
1590 static void
1591 nv_crtc_mode_set_ramdac_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1592 {
1593         ScrnInfoPtr pScrn = crtc->scrn;
1594         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1595         NVCrtcRegPtr regp;
1596         NVPtr pNv = NVPTR(pScrn);
1597         NVFBLayout *pLayout = &pNv->CurrentLayout;
1598         Bool is_fp = FALSE;
1599         Bool is_lvds = FALSE;
1600         float aspect_ratio, panel_ratio;
1601         uint32_t h_scale, v_scale;
1602
1603         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1604
1605         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1606         NVOutputPrivatePtr nv_output = output->driver_private;
1607
1608         if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS)) {
1609                 is_fp = TRUE;
1610
1611                 if (nv_output->type == OUTPUT_LVDS)
1612                         is_lvds = TRUE;
1613
1614                 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
1615                 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
1616                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HDisplay;
1617                 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
1618                 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
1619                 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
1620                 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
1621
1622                 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
1623                 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
1624                 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VDisplay;
1625                 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
1626                 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
1627                 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
1628                 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
1629
1630                 ErrorF("Horizontal:\n");
1631                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
1632                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
1633                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
1634                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
1635                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
1636                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
1637                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
1638
1639                 ErrorF("Vertical:\n");
1640                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
1641                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
1642                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
1643                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
1644                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
1645                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
1646                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
1647         }
1648
1649         /*
1650         * bit0: positive vsync
1651         * bit4: positive hsync
1652         * bit8: enable panel scaling
1653         * bit26: a bit sometimes seen on some g70 cards
1654         * bit31: sometimes seen on LVDS panels
1655         * This must also be set for non-flatpanels
1656         * Some bits seem shifted for vga monitors
1657         */
1658
1659         if (is_fp) {
1660                 regp->fp_control = 0x11100000;
1661         } else {
1662                 regp->fp_control = 0x21100000;
1663         }
1664         if (nv_output->type == OUTPUT_LVDS) {
1665                 /* Let's assume LVDS to be on ramdac0, remember that in the ramdac routing is somewhat random (compared to bios setup), so don't trust it */
1666                 regp->fp_control = nvReadRAMDAC0(pNv, NV_RAMDAC_FP_CONTROL) & 0xfff00000;
1667         } else {
1668                 /* If the special bit exists, it exists on both ramdac's */
1669                 regp->fp_control |= nvReadRAMDAC0(pNv, NV_RAMDAC_FP_CONTROL) & (1 << 26);
1670         }
1671
1672         /* Deal with vsync/hsync polarity */
1673         /* These analog monitor offsets are guesswork */
1674         if (adjusted_mode->Flags & V_PVSYNC) {
1675                 regp->fp_control |= (1 << (0 + !is_fp));
1676         }
1677
1678         if (adjusted_mode->Flags & V_PHSYNC) {
1679                 regp->fp_control |= (1 << (4 + !is_fp));
1680         }
1681
1682         if (is_fp) {
1683                 ErrorF("Pre-panel scaling\n");
1684                 ErrorF("panel-size:%dx%d\n", nv_output->fpWidth, nv_output->fpHeight);
1685                 panel_ratio = (nv_output->fpWidth)/(float)(nv_output->fpHeight);
1686                 ErrorF("panel_ratio=%f\n", panel_ratio);
1687                 aspect_ratio = (mode->HDisplay)/(float)(mode->VDisplay);
1688                 ErrorF("aspect_ratio=%f\n", aspect_ratio);
1689                 /* Scale factors is the so called 20.12 format, taken from Haiku */
1690                 h_scale = ((1 << 12) * mode->HDisplay)/nv_output->fpWidth;
1691                 v_scale = ((1 << 12) * mode->VDisplay)/nv_output->fpHeight;
1692                 ErrorF("h_scale=%d\n", h_scale);
1693                 ErrorF("v_scale=%d\n", v_scale);
1694
1695                 /* Don't limit last fetched line */
1696                 regp->debug_2 = 0;
1697
1698                 /* We want automatic scaling */
1699                 regp->debug_1 = 0;
1700
1701                 regp->fp_hvalid_start = 0;
1702                 regp->fp_hvalid_end = (nv_output->fpWidth - 1);
1703
1704                 regp->fp_vvalid_start = 0;
1705                 regp->fp_vvalid_end = (nv_output->fpHeight - 1);
1706
1707                 if (!pNv->fpScaler) {
1708                         ErrorF("Flat panel is doing the scaling.\n");
1709                         regp->fp_control |= (1 << 8);
1710                 } else {
1711                         ErrorF("GPU is doing the scaling.\n");
1712                         /* GPU scaling happens automaticly at a ratio of 1.33 */
1713                         /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
1714                         if (h_scale != (1 << 12) && (panel_ratio > (aspect_ratio + 0.10))) {
1715                                 uint32_t diff;
1716
1717                                 ErrorF("Scaling resolution on a widescreen panel\n");
1718
1719                                 /* Scaling in both directions needs to the same */
1720                                 h_scale = v_scale;
1721
1722                                 /* Set a new horizontal scale factor and enable testmode (bit12) */
1723                                 regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
1724
1725                                 diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
1726                                 regp->fp_hvalid_start = diff/2;
1727                                 regp->fp_hvalid_end = nv_output->fpWidth - (diff/2) - 1;
1728                         }
1729
1730                         /* Same scaling, just for panels with aspect ratio's smaller than 1 */
1731                         if (v_scale != (1 << 12) && (panel_ratio < (aspect_ratio - 0.10))) {
1732                                 uint32_t diff;
1733
1734                                 ErrorF("Scaling resolution on a portrait panel\n");
1735
1736                                 /* Scaling in both directions needs to the same */
1737                                 v_scale = h_scale;
1738
1739                                 /* Set a new vertical scale factor and enable testmode (bit28) */
1740                                 regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
1741
1742                                 diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
1743                                 regp->fp_vvalid_start = diff/2;
1744                                 regp->fp_vvalid_end = nv_output->fpHeight - (diff/2) - 1;
1745                         }
1746                 }
1747
1748                 ErrorF("Post-panel scaling\n");
1749         }
1750
1751         if (pNv->Architecture >= NV_ARCH_10) {
1752                 /* Bios and blob don't seem to do anything (else) */
1753                 regp->nv10_cursync = (1<<25);
1754         }
1755
1756         /* These are the common blob values, minus a few fp specific bit's */
1757         /* Let's keep the TMDS pll and fpclock running in all situations */
1758         regp->debug_0 = 0x1101111;
1759
1760         if(is_fp) {
1761                 /* I am not completely certain, but seems to be set only for dfp's */
1762                 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED;
1763         }
1764
1765         ErrorF("output %d debug_0 %08X\n", nv_output->ramdac, regp->debug_0);
1766
1767         /* Flatpanel support needs at least a NV10 */
1768         if(pNv->twoHeads) {
1769                 /* Instead of 1, several other values are also used: 2, 7, 9 */
1770                 /* The purpose is unknown */
1771                 if(pNv->FPDither) {
1772                         regp->dither = 0x00010000;
1773                 }
1774         }
1775
1776         /* Kindly borrowed from haiku driver */
1777         /* bit4 and bit5 activate indirect mode trough color palette */
1778         switch (pLayout->depth) {
1779                 case 32:
1780                 case 16:
1781                         regp->general = 0x00101130;
1782                         break;
1783                 case 24:
1784                 case 15:
1785                         regp->general = 0x00100130;
1786                         break;
1787                 case 8:
1788                 default:
1789                         regp->general = 0x00101100;
1790                         break;
1791         }
1792
1793         if (pNv->alphaCursor) {
1794                 regp->general |= (1<<29);
1795         }
1796
1797         /* Some values the blob sets */
1798         /* This may apply to the real ramdac that is being used (for crosswired situations) */
1799         /* Nevertheless, it's unlikely to cause many problems, since the values are equal for both */
1800         regp->unk_a20 = 0x0;
1801         regp->unk_a24 = 0xfffff;
1802         regp->unk_a34 = 0x1;
1803 }
1804
1805 /**
1806  * Sets up registers for the given mode/adjusted_mode pair.
1807  *
1808  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1809  *
1810  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1811  * be easily turned on/off after this.
1812  */
1813 static void
1814 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
1815                  DisplayModePtr adjusted_mode,
1816                  int x, int y)
1817 {
1818         ScrnInfoPtr pScrn = crtc->scrn;
1819         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1820         NVPtr pNv = NVPTR(pScrn);
1821
1822         ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->crtc);
1823
1824         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->crtc);
1825         xf86PrintModeline(pScrn->scrnIndex, mode);
1826         NVCrtcSetOwner(crtc);
1827
1828         nv_crtc_mode_set_vga(crtc, mode);
1829         nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
1830         nv_crtc_mode_set_ramdac_regs(crtc, mode, adjusted_mode);
1831
1832         /* Just in case */
1833         NVCrtcLockUnlock(crtc, FALSE);
1834
1835         NVVgaProtect(crtc, TRUE);
1836         nv_crtc_load_state_ext(crtc, &pNv->ModeReg);
1837         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
1838         if (pNv->Architecture == NV_ARCH_40) {
1839                 nv40_crtc_load_state_pll(pNv, &pNv->ModeReg);
1840         } else {
1841                 nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
1842         }
1843         nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
1844
1845         NVVgaProtect(crtc, FALSE);
1846
1847         NVCrtcSetBase(crtc, x, y);
1848
1849 #if X_BYTE_ORDER == X_BIG_ENDIAN
1850         /* turn on LFB swapping */
1851         {
1852                 unsigned char tmp;
1853
1854                 tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
1855                 tmp |= (1 << 7);
1856                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
1857         }
1858 #endif
1859 }
1860
1861 void nv_crtc_save(xf86CrtcPtr crtc)
1862 {
1863         ScrnInfoPtr pScrn = crtc->scrn;
1864         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1865         NVPtr pNv = NVPTR(pScrn);
1866
1867         ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->crtc);
1868
1869         /* We just came back from terminal, so unlock */
1870         NVCrtcLockUnlock(crtc, FALSE);
1871
1872         NVCrtcSetOwner(crtc);
1873         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
1874         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
1875         if (pNv->Architecture == NV_ARCH_40) {
1876                 nv40_crtc_save_state_pll(pNv, &pNv->SavedReg);
1877         } else {
1878                 nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
1879         }
1880         nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
1881 }
1882
1883 void nv_crtc_restore(xf86CrtcPtr crtc)
1884 {
1885         ScrnInfoPtr pScrn = crtc->scrn;
1886         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1887         NVPtr pNv = NVPTR(pScrn);
1888
1889         ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->crtc);
1890
1891         NVCrtcSetOwner(crtc);
1892
1893         /* Just to be safe */
1894         NVCrtcLockUnlock(crtc, FALSE);
1895
1896         NVVgaProtect(crtc, TRUE);
1897         nv_crtc_load_state_ext(crtc, &pNv->SavedReg);
1898         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
1899         if (pNv->Architecture == NV_ARCH_40) {
1900                 nv40_crtc_load_state_pll(pNv, &pNv->SavedReg);
1901         } else {
1902                 nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
1903         }
1904         nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
1905         nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->vtOWNER);
1906         NVVgaProtect(crtc, FALSE);
1907
1908         /* We must lock the door if we leave ;-) */
1909         NVCrtcLockUnlock(crtc, TRUE);
1910 }
1911
1912 void nv_crtc_prepare(xf86CrtcPtr crtc)
1913 {
1914         ScrnInfoPtr pScrn = crtc->scrn;
1915         NVPtr pNv = NVPTR(pScrn);
1916         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1917
1918         ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->crtc);
1919
1920         crtc->funcs->dpms(crtc, DPMSModeOff);
1921
1922         /* Sync the engine before adjust mode */
1923         if (pNv->EXADriverPtr) {
1924                 exaMarkSync(pScrn->pScreen);
1925                 exaWaitSync(pScrn->pScreen);
1926         }
1927 }
1928
1929 void nv_crtc_commit(xf86CrtcPtr crtc)
1930 {
1931         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1932         ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->crtc);
1933
1934         crtc->funcs->dpms (crtc, DPMSModeOn);
1935         if (crtc->scrn->pScreen != NULL)
1936                 xf86_reload_cursors (crtc->scrn->pScreen);
1937 }
1938
1939 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
1940 {
1941         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1942         ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->crtc);
1943
1944         return FALSE;
1945 }
1946
1947 static void nv_crtc_unlock(xf86CrtcPtr crtc)
1948 {
1949         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1950         ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->crtc);
1951 }
1952
1953 static void
1954 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
1955                                         int size)
1956 {
1957         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1958         ScrnInfoPtr pScrn = crtc->scrn;
1959         NVPtr pNv = NVPTR(pScrn);
1960         int i, j;
1961
1962         NVCrtcRegPtr regp;
1963         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1964
1965         switch (pNv->CurrentLayout.depth) {
1966         case 15:
1967                 /* R5G5B5 */
1968                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
1969                 for (i = 0; i < 32; i++) {
1970                         for (j = 0; j < 8; j++) {
1971                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1972                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
1973                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1974                         }
1975                 }
1976                 break;
1977         case 16:
1978                 /* R5G6B5 */
1979                 /* First deal with the 5 bit colors */
1980                 for (i = 0; i < 32; i++) {
1981                         for (j = 0; j < 8; j++) {
1982                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1983                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1984                         }
1985                 }
1986                 /* Now deal with the 6 bit color */
1987                 for (i = 0; i < 64; i++) {
1988                         for (j = 0; j < 4; j++) {
1989                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
1990                         }
1991                 }
1992                 break;
1993         default:
1994                 /* R8G8B8 */
1995                 for (i = 0; i < 256; i++) {
1996                         regp->DAC[i * 3] = red[i] >> 8;
1997                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
1998                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
1999                 }
2000                 break;
2001         }
2002
2003         NVCrtcLoadPalette(crtc);
2004 }
2005
2006 /* NV04-NV10 doesn't support alpha cursors */
2007 static const xf86CrtcFuncsRec nv_crtc_funcs = {
2008         .dpms = nv_crtc_dpms,
2009         .save = nv_crtc_save, /* XXX */
2010         .restore = nv_crtc_restore, /* XXX */
2011         .mode_fixup = nv_crtc_mode_fixup,
2012         .mode_set = nv_crtc_mode_set,
2013         .prepare = nv_crtc_prepare,
2014         .commit = nv_crtc_commit,
2015         .destroy = NULL, /* XXX */
2016         .lock = nv_crtc_lock,
2017         .unlock = nv_crtc_unlock,
2018         .set_cursor_colors = nv_crtc_set_cursor_colors,
2019         .set_cursor_position = nv_crtc_set_cursor_position,
2020         .show_cursor = nv_crtc_show_cursor,
2021         .hide_cursor = nv_crtc_hide_cursor,
2022         .load_cursor_image = nv_crtc_load_cursor_image,
2023         .gamma_set = nv_crtc_gamma_set,
2024 };
2025
2026 /* NV11 and up has support for alpha cursors. */
2027 /* Due to different maximum sizes we cannot allow it to use normal cursors */
2028 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
2029         .dpms = nv_crtc_dpms,
2030         .save = nv_crtc_save, /* XXX */
2031         .restore = nv_crtc_restore, /* XXX */
2032         .mode_fixup = nv_crtc_mode_fixup,
2033         .mode_set = nv_crtc_mode_set,
2034         .prepare = nv_crtc_prepare,
2035         .commit = nv_crtc_commit,
2036         .destroy = NULL, /* XXX */
2037         .lock = nv_crtc_lock,
2038         .unlock = nv_crtc_unlock,
2039         .set_cursor_colors = nv_crtc_set_cursor_colors,
2040         .set_cursor_position = nv_crtc_set_cursor_position,
2041         .show_cursor = nv_crtc_show_cursor,
2042         .hide_cursor = nv_crtc_hide_cursor,
2043         .load_cursor_argb = nv_crtc_load_cursor_argb,
2044         .gamma_set = nv_crtc_gamma_set,
2045 };
2046
2047
2048 void
2049 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
2050 {
2051         NVPtr pNv = NVPTR(pScrn);
2052         xf86CrtcPtr crtc;
2053         NVCrtcPrivatePtr nv_crtc;
2054
2055         if (pNv->NVArch >= 0x11) {
2056                 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
2057         } else {
2058                 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
2059         }
2060         if (crtc == NULL)
2061                 return;
2062
2063         nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
2064         nv_crtc->crtc = crtc_num;
2065         nv_crtc->head = crtc_num;
2066
2067         crtc->driver_private = nv_crtc;
2068
2069         NVCrtcLockUnlock(crtc, FALSE);
2070 }
2071
2072 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2073 {
2074     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2075     int i;
2076     NVCrtcRegPtr regp;
2077
2078     regp = &state->crtc_reg[nv_crtc->head];
2079
2080     NVWriteMiscOut(crtc, regp->MiscOutReg);
2081
2082     for (i = 1; i < 5; i++)
2083       NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
2084
2085     /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
2086     NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
2087
2088     for (i = 0; i < 25; i++)
2089       NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
2090
2091     for (i = 0; i < 9; i++)
2092       NVWriteVgaGr(crtc, i, regp->Graphics[i]);
2093
2094     NVEnablePalette(crtc);
2095     for (i = 0; i < 21; i++)
2096       NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
2097     NVDisablePalette(crtc);
2098
2099 }
2100
2101 static void nv_crtc_fix_nv40_hw_cursor(xf86CrtcPtr crtc)
2102 {
2103   /* TODO - implement this properly */
2104   ScrnInfoPtr pScrn = crtc->scrn;
2105   NVPtr pNv = NVPTR(pScrn);
2106
2107   if(pNv->Architecture == NV_ARCH_40) {  /* HW bug */
2108     volatile CARD32 curpos = nvReadCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS);
2109     nvWriteCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS, curpos);
2110   }
2111
2112 }
2113 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2114 {
2115     ScrnInfoPtr pScrn = crtc->scrn;
2116     NVPtr pNv = NVPTR(pScrn);
2117     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2118     NVCrtcRegPtr regp;
2119
2120     regp = &state->crtc_reg[nv_crtc->head];
2121
2122     if(pNv->Architecture >= NV_ARCH_10) {
2123         if(pNv->twoHeads) {
2124            nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL, regp->head);
2125         }
2126         nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
2127         nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
2128         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
2129         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
2130         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2131         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2132         nvWriteMC(pNv, 0x1588, 0);
2133
2134         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
2135         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
2136         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO, regp->gpio);
2137         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0830, regp->unk830);
2138         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0834, regp->unk834);
2139         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0850, regp->unk850);
2140         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_081C, regp->unk81c);
2141
2142         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
2143         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
2144
2145         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
2146         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
2147         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3C, regp->CRTC[NV_VGA_CRTCX_3C]);
2148         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
2149         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
2150         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_56, regp->CRTC[NV_VGA_CRTCX_56]);
2151         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_57, regp->CRTC[NV_VGA_CRTCX_57]);
2152         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_58, regp->CRTC[NV_VGA_CRTCX_58]);
2153         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
2154         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
2155     }
2156
2157     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
2158     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
2159     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
2160     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
2161     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
2162     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
2163     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
2164     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
2165     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
2166     if(pNv->Architecture >= NV_ARCH_30) {
2167       NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
2168     }
2169
2170     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
2171     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
2172     nv_crtc_fix_nv40_hw_cursor(crtc);
2173     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
2174     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
2175
2176     nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_EN_0, 0);
2177     nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
2178
2179     pNv->CurrentState = state;
2180 }
2181
2182 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2183 {
2184     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2185     int i;
2186     NVCrtcRegPtr regp;
2187
2188     regp = &state->crtc_reg[nv_crtc->head];
2189
2190     regp->MiscOutReg = NVReadMiscOut(crtc);
2191
2192     for (i = 0; i < 25; i++)
2193         regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
2194
2195     NVEnablePalette(crtc);
2196     for (i = 0; i < 21; i++)
2197         regp->Attribute[i] = NVReadVgaAttr(crtc, i);
2198     NVDisablePalette(crtc);
2199
2200     for (i = 0; i < 9; i++)
2201         regp->Graphics[i] = NVReadVgaGr(crtc, i);
2202
2203     for (i = 1; i < 5; i++)
2204         regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
2205
2206 }
2207
2208 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2209 {
2210     ScrnInfoPtr pScrn = crtc->scrn;
2211     NVPtr pNv = NVPTR(pScrn);
2212     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2213     NVCrtcRegPtr regp;
2214
2215     regp = &state->crtc_reg[nv_crtc->head];
2216
2217     regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
2218     regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
2219     regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
2220     regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
2221     regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
2222     regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
2223     regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
2224
2225     regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
2226     regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
2227     if(pNv->Architecture >= NV_ARCH_30) {
2228          regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
2229     }
2230     regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
2231     regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
2232     regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
2233     regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
2234
2235     regp->gpio = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO);
2236     regp->unk830 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0830);
2237     regp->unk834 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0834);
2238     regp->unk850 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0850);
2239     regp->unk81c = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_081C);
2240
2241     if(pNv->Architecture >= NV_ARCH_10) {
2242         if(pNv->twoHeads) {
2243            regp->head     = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL);
2244            regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
2245         }
2246         regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
2247
2248         regp->cursorConfig = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG);
2249
2250         regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
2251         regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
2252         regp->CRTC[NV_VGA_CRTCX_3C] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3C);
2253         regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
2254         regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
2255         regp->CRTC[NV_VGA_CRTCX_56] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_56);
2256         regp->CRTC[NV_VGA_CRTCX_57] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_57);
2257         regp->CRTC[NV_VGA_CRTCX_58] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_58);
2258         regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
2259         regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
2260         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
2261         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
2262     }
2263 }
2264
2265 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2266 {
2267         ScrnInfoPtr pScrn = crtc->scrn;
2268         NVPtr pNv = NVPTR(pScrn);
2269         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2270         NVCrtcRegPtr regp;
2271         int i;
2272
2273         regp = &state->crtc_reg[nv_crtc->head];
2274
2275         regp->general = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL);
2276
2277         regp->fp_control        = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL);
2278         regp->debug_0   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0);
2279         regp->debug_1   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1);
2280         regp->debug_2   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2);
2281
2282         regp->unk_a20 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20);
2283         regp->unk_a24 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24);
2284         regp->unk_a34 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34);
2285
2286         if (pNv->NVArch == 0x11) {
2287                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11);
2288         } else if (pNv->twoHeads) {
2289                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER);
2290         }
2291         regp->nv10_cursync = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC);
2292
2293         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2294
2295         for (i = 0; i < 7; i++) {
2296                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2297                 regp->fp_horiz_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2298         }
2299
2300         for (i = 0; i < 7; i++) {
2301                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2302                 regp->fp_vert_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2303         }
2304
2305         regp->fp_hvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START);
2306         regp->fp_hvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END);
2307         regp->fp_vvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START);
2308         regp->fp_vvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END);
2309 }
2310
2311 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2312 {
2313         ScrnInfoPtr pScrn = crtc->scrn;
2314         NVPtr pNv = NVPTR(pScrn);
2315         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2316         NVCrtcRegPtr regp;
2317         int i;
2318
2319         regp = &state->crtc_reg[nv_crtc->head];
2320
2321         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL, regp->general);
2322
2323         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control);
2324         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0, regp->debug_0);
2325         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
2326         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
2327
2328         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20, regp->unk_a20);
2329         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24, regp->unk_a24);
2330         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34, regp->unk_a34);
2331
2332         if (pNv->NVArch == 0x11) {
2333                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11, regp->dither);
2334         } else if (pNv->twoHeads) {
2335                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER, regp->dither);
2336         }
2337         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
2338
2339         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2340
2341         for (i = 0; i < 7; i++) {
2342                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2343                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_horiz_regs[i]);
2344         }
2345
2346         for (i = 0; i < 7; i++) {
2347                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2348                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_vert_regs[i]);
2349         }
2350
2351         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START, regp->fp_hvalid_start);
2352         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END, regp->fp_hvalid_end);
2353         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START, regp->fp_vvalid_start);
2354         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END, regp->fp_vvalid_end);
2355 }
2356
2357 void
2358 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y)
2359 {
2360         ScrnInfoPtr pScrn = crtc->scrn;
2361         NVPtr pNv = NVPTR(pScrn);
2362         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2363         NVFBLayout *pLayout = &pNv->CurrentLayout;
2364         CARD32 start = 0;
2365
2366         ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
2367
2368         start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
2369         start += pNv->FB->offset;
2370
2371         /* 30 bits addresses in 32 bits according to haiku */
2372         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_START, start & 0xfffffffc);
2373
2374         /* set NV4/NV10 byte adress: (bit0 - 1) */
2375         NVWriteVgaAttr(crtc, 0x13, (start & 0x3) << 1);
2376
2377         crtc->x = x;
2378         crtc->y = y;
2379 }
2380
2381 static void NVCrtcWriteDacMask(xf86CrtcPtr crtc, CARD8 value)
2382 {
2383   ScrnInfoPtr pScrn = crtc->scrn;
2384   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2385   NVPtr pNv = NVPTR(pScrn);
2386   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2387
2388   NV_WR08(pDACReg, VGA_DAC_MASK, value);
2389 }
2390
2391 static CARD8 NVCrtcReadDacMask(xf86CrtcPtr crtc)
2392 {
2393   ScrnInfoPtr pScrn = crtc->scrn;
2394   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2395   NVPtr pNv = NVPTR(pScrn);
2396   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2397
2398   return NV_RD08(pDACReg, VGA_DAC_MASK);
2399 }
2400
2401 static void NVCrtcWriteDacReadAddr(xf86CrtcPtr crtc, CARD8 value)
2402 {
2403   ScrnInfoPtr pScrn = crtc->scrn;
2404   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2405   NVPtr pNv = NVPTR(pScrn);
2406   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2407
2408   NV_WR08(pDACReg, VGA_DAC_READ_ADDR, value);
2409 }
2410
2411 static void NVCrtcWriteDacWriteAddr(xf86CrtcPtr crtc, CARD8 value)
2412 {
2413   ScrnInfoPtr pScrn = crtc->scrn;
2414   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2415   NVPtr pNv = NVPTR(pScrn);
2416   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2417
2418   NV_WR08(pDACReg, VGA_DAC_WRITE_ADDR, value);
2419 }
2420
2421 static void NVCrtcWriteDacData(xf86CrtcPtr crtc, CARD8 value)
2422 {
2423   ScrnInfoPtr pScrn = crtc->scrn;
2424   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2425   NVPtr pNv = NVPTR(pScrn);
2426   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2427
2428   NV_WR08(pDACReg, VGA_DAC_DATA, value);
2429 }
2430
2431 static CARD8 NVCrtcReadDacData(xf86CrtcPtr crtc, CARD8 value)
2432 {
2433   ScrnInfoPtr pScrn = crtc->scrn;
2434   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2435   NVPtr pNv = NVPTR(pScrn);
2436   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2437
2438   return NV_RD08(pDACReg, VGA_DAC_DATA);
2439 }
2440
2441 void NVCrtcLoadPalette(xf86CrtcPtr crtc)
2442 {
2443         int i;
2444         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2445         NVCrtcRegPtr regp;
2446         ScrnInfoPtr pScrn = crtc->scrn;
2447         NVPtr pNv = NVPTR(pScrn);
2448
2449         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2450
2451         NVCrtcSetOwner(crtc);
2452         NVCrtcWriteDacMask(crtc, 0xff);
2453         NVCrtcWriteDacWriteAddr(crtc, 0x00);
2454
2455         for (i = 0; i<768; i++) {
2456                 NVCrtcWriteDacData(crtc, regp->DAC[i]);
2457         }
2458         NVDisablePalette(crtc);
2459 }
2460
2461 void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
2462 {
2463         unsigned char scrn;
2464
2465         NVCrtcSetOwner(crtc);
2466
2467         scrn = NVReadVgaSeq(crtc, 0x01);
2468         if (on) {
2469                 scrn &= ~0x20;
2470         } else {
2471                 scrn |= 0x20;
2472         }
2473
2474         NVVgaSeqReset(crtc, TRUE);
2475         NVWriteVgaSeq(crtc, 0x01, scrn);
2476         NVVgaSeqReset(crtc, FALSE);
2477 }
2478
2479 /*************************************************************************** \
2480 |*                                                                           *|
2481 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
2482 |*                                                                           *|
2483 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
2484 |*     international laws.  Users and possessors of this source code are     *|
2485 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
2486 |*     use this code in individual and commercial software.                  *|
2487 |*                                                                           *|
2488 |*     Any use of this source code must include,  in the user documenta-     *|
2489 |*     tion and  internal comments to the code,  notices to the end user     *|
2490 |*     as follows:                                                           *|
2491 |*                                                                           *|
2492 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
2493 |*                                                                           *|
2494 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
2495 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
2496 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
2497 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
2498 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
2499 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
2500 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
2501 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
2502 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
2503 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
2504 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
2505 |*                                                                           *|
2506 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
2507 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
2508 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
2509 |*     computer  software  documentation,"  as such  terms  are  used in     *|
2510 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
2511 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
2512 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
2513 |*     all U.S. Government End Users  acquire the source code  with only     *|
2514 |*     those rights set forth herein.                                        *|
2515 |*                                                                           *|
2516  \***************************************************************************/