2 * Copyright 1993-2003 NVIDIA, Corporation
3 * Copyright 2008 Stuart Bennett
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
19 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
20 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include "nv_include.h"
26 uint32_t NVRead(NVPtr pNv, uint32_t reg)
28 DDXMMIOW("NVRead: reg %08x val %08x\n", reg, (uint32_t)NV_RD32(pNv->REGS, reg));
29 return NV_RD32(pNv->REGS, reg);
32 void NVWrite(NVPtr pNv, uint32_t reg, uint32_t val)
34 DDXMMIOW("NVWrite: reg %08x val %08x\n", reg, NV_WR32(pNv->REGS, reg, val));
37 uint32_t NVReadCRTC(NVPtr pNv, int head, uint32_t reg)
40 reg += NV_PCRTC0_SIZE;
41 DDXMMIOH("NVReadCRTC: head %d reg %08x val %08x\n", head, reg, (uint32_t)NV_RD32(pNv->REGS, reg));
42 return NV_RD32(pNv->REGS, reg);
45 void NVWriteCRTC(NVPtr pNv, int head, uint32_t reg, uint32_t val)
48 reg += NV_PCRTC0_SIZE;
49 DDXMMIOH("NVWriteCRTC: head %d reg %08x val %08x\n", head, reg, val);
50 NV_WR32(pNv->REGS, reg, val);
53 uint32_t NVReadRAMDAC(NVPtr pNv, int head, uint32_t reg)
56 reg += NV_PRAMDAC0_SIZE;
57 DDXMMIOH("NVReadRamdac: head %d reg %08x val %08x\n", head, reg, (uint32_t)NV_RD32(pNv->REGS, reg));
58 return NV_RD32(pNv->REGS, reg);
61 void NVWriteRAMDAC(NVPtr pNv, int head, uint32_t reg, uint32_t val)
64 reg += NV_PRAMDAC0_SIZE;
65 DDXMMIOH("NVWriteRamdac: head %d reg %08x val %08x\n", head, reg, val);
66 NV_WR32(pNv->REGS, reg, val);
69 uint8_t nv_read_tmds(NVPtr pNv, int or, int dl, uint8_t address)
71 int ramdac = (or & OUTPUT_C) >> 2;
73 NVWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_CONTROL + dl * 8,
74 NV_RAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE | address);
75 return NVReadRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_DATA + dl * 8);
78 int nv_get_digital_bound_head(NVPtr pNv, int or)
80 /* special case of nv_read_tmds to find crtc associated with an output.
81 * this does not give a correct answer for off-chip dvi, but there's no
82 * use for such an answer anyway
84 int ramdac = (or & OUTPUT_C) >> 2;
86 NVWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_CONTROL,
87 NV_RAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE | 0x4);
88 return (((NVReadRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_DATA) & 0x8) >> 3) ^ ramdac);
91 void nv_write_tmds(NVPtr pNv, int or, int dl, uint8_t address, uint8_t data)
93 int ramdac = (or & OUTPUT_C) >> 2;
95 NVWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_DATA + dl * 8, data);
96 NVWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_CONTROL + dl * 8, address);
99 void NVWriteVgaCrtc(NVPtr pNv, int head, uint8_t index, uint8_t value)
101 DDXMMIOH("NVWriteVgaCrtc: head %d index 0x%02x data 0x%02x\n", head, index, value);
102 NV_WR08(pNv->REGS, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
103 NV_WR08(pNv->REGS, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE, value);
106 uint8_t NVReadVgaCrtc(NVPtr pNv, int head, uint8_t index)
108 NV_WR08(pNv->REGS, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
109 DDXMMIOH("NVReadVgaCrtc: head %d index 0x%02x data 0x%02x\n", head, index, NV_RD08(pNv->REGS, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE));
110 return NV_RD08(pNv->REGS, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE);
113 /* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
114 * I suspect they in fact do nothing, but are merely a way to carry useful
115 * per-head variables around
119 * 0x00 index to the appropriate dcb entry (or 7f for inactive)
120 * 0x02 dcb entry's "or" value (or 00 for inactive)
121 * 0x03 bit0 set for dual link (LVDS, possibly elsewhere too)
122 * 0x08 or 0x09 pxclk in MHz
123 * 0x0f laptop panel info - low nibble for PEXTDEV_BOOT_0 strap
124 * high nibble for xlat strap value
127 void NVWriteVgaCrtc5758(NVPtr pNv, int head, uint8_t index, uint8_t value)
129 NVWriteVgaCrtc(pNv, head, NV_CIO_CRE_57, index);
130 NVWriteVgaCrtc(pNv, head, NV_CIO_CRE_58, value);
133 uint8_t NVReadVgaCrtc5758(NVPtr pNv, int head, uint8_t index)
135 NVWriteVgaCrtc(pNv, head, NV_CIO_CRE_57, index);
136 return NVReadVgaCrtc(pNv, head, NV_CIO_CRE_58);
139 uint8_t NVReadPRMVIO(NVPtr pNv, int head, uint32_t reg)
141 /* Only NV4x have two pvio ranges */
142 if (head && pNv->Architecture == NV_ARCH_40)
143 reg += NV_PRMVIO_SIZE;
145 DDXMMIOH("NVReadPRMVIO: head %d reg %08x val %02x\n", head, reg, NV_RD08(pNv->REGS, reg));
146 return NV_RD08(pNv->REGS, reg);
149 void NVWritePRMVIO(NVPtr pNv, int head, uint32_t reg, uint8_t value)
151 /* Only NV4x have two pvio ranges */
152 if (head && pNv->Architecture == NV_ARCH_40)
153 reg += NV_PRMVIO_SIZE;
155 DDXMMIOH("NVWritePRMVIO: head %d reg %08x val %02x\n", head, reg, value);
156 NV_WR08(pNv->REGS, reg, value);
159 void NVWriteVgaSeq(NVPtr pNv, int head, uint8_t index, uint8_t value)
161 NVWritePRMVIO(pNv, head, NV_PRMVIO_SRX, index);
162 NVWritePRMVIO(pNv, head, NV_PRMVIO_SR, value);
165 uint8_t NVReadVgaSeq(NVPtr pNv, int head, uint8_t index)
167 NVWritePRMVIO(pNv, head, NV_PRMVIO_SRX, index);
168 return NVReadPRMVIO(pNv, head, NV_PRMVIO_SR);
171 void NVWriteVgaGr(NVPtr pNv, int head, uint8_t index, uint8_t value)
173 NVWritePRMVIO(pNv, head, NV_PRMVIO_GRX, index);
174 NVWritePRMVIO(pNv, head, NV_PRMVIO_GX, value);
177 uint8_t NVReadVgaGr(NVPtr pNv, int head, uint8_t index)
179 NVWritePRMVIO(pNv, head, NV_PRMVIO_GRX, index);
180 return NVReadPRMVIO(pNv, head, NV_PRMVIO_GX);
183 void NVSetEnablePalette(NVPtr pNv, int head, bool enable)
185 VGA_RD08(pNv->REGS, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
186 VGA_WR08(pNv->REGS, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, enable ? 0 : 0x20);
189 static bool NVGetEnablePalette(NVPtr pNv, int head)
191 VGA_RD08(pNv->REGS, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
192 return !(VGA_RD08(pNv->REGS, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE) & 0x20);
195 void NVWriteVgaAttr(NVPtr pNv, int head, uint8_t index, uint8_t value)
197 if (NVGetEnablePalette(pNv, head))
202 NV_RD08(pNv->REGS, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
203 DDXMMIOH("NVWriteVgaAttr: head %d index 0x%02x data 0x%02x\n", head, index, value);
204 NV_WR08(pNv->REGS, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);
205 NV_WR08(pNv->REGS, NV_PRMCIO_AR__WRITE + head * NV_PRMCIO_SIZE, value);
208 uint8_t NVReadVgaAttr(NVPtr pNv, int head, uint8_t index)
210 if (NVGetEnablePalette(pNv, head))
215 NV_RD08(pNv->REGS, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
216 NV_WR08(pNv->REGS, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);
217 DDXMMIOH("NVReadVgaAttr: head %d index 0x%02x data 0x%02x\n", head, index, NV_RD08(pNv->REGS, NV_PRMCIO_AR__READ + head * NV_PRMCIO_SIZE));
218 return NV_RD08(pNv->REGS, NV_PRMCIO_AR__READ + head * NV_PRMCIO_SIZE);
221 void NVVgaSeqReset(NVPtr pNv, int head, bool start)
223 NVWriteVgaSeq(pNv, head, NV_VIO_SR_RESET_INDEX, start ? 0x1 : 0x3);
226 void NVVgaProtect(NVPtr pNv, int head, bool protect)
228 uint8_t seq1 = NVReadVgaSeq(pNv, head, NV_VIO_SR_CLOCK_INDEX);
231 NVVgaSeqReset(pNv, head, true);
232 NVWriteVgaSeq(pNv, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);
234 /* Reenable sequencer, then turn on screen */
235 NVWriteVgaSeq(pNv, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20); /* reenable display */
236 NVVgaSeqReset(pNv, head, false);
238 NVSetEnablePalette(pNv, head, protect);
241 void NVSetOwner(NVPtr pNv, int head)
243 /* CR44 is always changed on CRTC0 */
244 NVWriteVgaCrtc(pNv, 0, NV_CIO_CRE_44, head * 0x3);
247 void NVLockVgaCrtc(NVPtr pNv, int head, bool lock)
251 NVWriteVgaCrtc(pNv, head, NV_CIO_SR_LOCK_INDEX,
252 lock ? NV_CIO_SR_LOCK_VALUE : NV_CIO_SR_UNLOCK_RW_VALUE);
254 cr11 = NVReadVgaCrtc(pNv, head, NV_CIO_CR_VRE_INDEX);
259 NVWriteVgaCrtc(pNv, head, NV_CIO_CR_VRE_INDEX, cr11);
262 void NVBlankScreen(NVPtr pNv, int head, bool blank)
267 NVSetOwner(pNv, head);
269 seq1 = NVReadVgaSeq(pNv, head, NV_VIO_SR_CLOCK_INDEX);
271 NVVgaSeqReset(pNv, head, true);
273 NVWriteVgaSeq(pNv, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);
275 NVWriteVgaSeq(pNv, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20);
276 NVVgaSeqReset(pNv, head, false);
279 void nv_fix_nv40_hw_cursor(NVPtr pNv, int head)
281 /* on some nv40 (such as the "true" (in the NV_PFB_BOOT_0 sense) nv40,
282 * the gf6800gt) a hardware bug requires a write to PRAMDAC_CURSOR_POS
283 * for changes to the CRTC CURCTL regs to take effect, whether changing
284 * the pixmap location, or just showing/hiding the cursor
286 volatile uint32_t curpos = NVReadRAMDAC(pNv, head, NV_RAMDAC_CURSOR_POS);
287 NVWriteRAMDAC(pNv, head, NV_RAMDAC_CURSOR_POS, curpos);
290 void nv_show_cursor(NVPtr pNv, int head, bool show)
292 int curctl1 = NVReadVgaCrtc(pNv, head, NV_CIO_CRE_HCUR_ADDR1_INDEX);
295 NVWriteVgaCrtc(pNv, head, NV_CIO_CRE_HCUR_ADDR1_INDEX,
296 curctl1 | NV_CIO_CRE_HCUR_ADDR1_ENABLE);
298 NVWriteVgaCrtc(pNv, head, NV_CIO_CRE_HCUR_ADDR1_INDEX,
299 curctl1 & ~NV_CIO_CRE_HCUR_ADDR1_ENABLE);
301 if (pNv->Architecture == NV_ARCH_40)
302 nv_fix_nv40_hw_cursor(pNv, head);
305 int nv_decode_pll_highregs(NVPtr pNv, uint32_t pll1, uint32_t pll2, bool force_single, int refclk)
307 int M1, N1, M2 = 1, N2 = 1, log2P;
310 N1 = (pll1 >> 8) & 0xff;
311 log2P = (pll1 >> 16) & 0x7; /* never more than 6, and nv30/35 only uses 3 bits */
312 if (pNv->twoStagePLL && pll2 & NV31_RAMDAC_ENABLE_VCO2 && !force_single) {
314 N2 = (pll2 >> 8) & 0xff;
315 } else if (pNv->NVArch == 0x30 || pNv->NVArch == 0x35) {
316 M1 &= 0xf; /* only 4 bits */
317 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) {
318 M2 = (pll1 >> 4) & 0x7;
319 N2 = ((pll2 >> 21) & 0x18) | ((pll2 >> 19) & 0x7);
323 /* Avoid divide by zero if called at an inappropriate time */
327 return (N1 * N2 * refclk / (M1 * M2)) >> log2P;
330 static int nv_decode_pll_lowregs(uint32_t Pval, uint32_t NMNM, int refclk)
332 int M1, N1, M2 = 1, N2 = 1, log2P;
334 log2P = (Pval >> 16) & 0x7;
337 N1 = (NMNM >> 8) & 0xff;
338 /* NVPLL and VPLLs use 1 << 8 to indicate single stage mode, MPLL uses 1 << 12 */
339 if (!(Pval & (1 << 8) || Pval & (1 << 12))) {
340 M2 = (NMNM >> 16) & 0xff;
341 N2 = (NMNM >> 24) & 0xff;
344 /* Avoid divide by zero if called at an inappropriate time */
348 return (N1 * N2 * refclk / (M1 * M2)) >> log2P;
351 static int nv_get_clock(ScrnInfoPtr pScrn, enum pll_types plltype)
353 NVPtr pNv = NVPTR(pScrn);
354 const uint32_t nv04_regs[MAX_PLL_TYPES] = { NV_RAMDAC_NVPLL, NV_RAMDAC_MPLL, NV_RAMDAC_VPLL, NV_RAMDAC_VPLL2 };
355 const uint32_t nv40_regs[MAX_PLL_TYPES] = { 0x4000, 0x4020, NV_RAMDAC_VPLL, NV_RAMDAC_VPLL2 };
357 struct pll_lims pll_lim;
359 if (plltype == MPLL && (pNv->Chipset & 0x0ff0) == CHIPSET_NFORCE) {
360 uint32_t mpllP = (PCI_SLOT_READ_LONG(3, 0x6c) >> 8) & 0xf;
364 return 400000 / mpllP;
365 } else if (plltype == MPLL && (pNv->Chipset & 0xff0) == CHIPSET_NFORCE2)
366 return PCI_SLOT_READ_LONG(5, 0x4c) / 1000;
368 if (pNv->Architecture < NV_ARCH_40)
369 reg1 = nv04_regs[plltype];
371 reg1 = nv40_regs[plltype];
373 if (!get_pll_limits(pScrn, plltype, &pll_lim))
377 return nv_decode_pll_lowregs(nvReadMC(pNv, reg1), nvReadMC(pNv, reg1 + 4), pll_lim.refclk);
378 if (pNv->twoStagePLL) {
379 bool nv40_single = pNv->Architecture == 0x40 && ((plltype == VPLL1 && NVReadRAMDAC(pNv, 0, NV_RAMDAC_580) & NV_RAMDAC_580_VPLL1_ACTIVE) || (plltype == VPLL2 && NVReadRAMDAC(pNv, 0, NV_RAMDAC_580) & NV_RAMDAC_580_VPLL2_ACTIVE));
381 return nv_decode_pll_highregs(pNv, nvReadMC(pNv, reg1), nvReadMC(pNv, reg1 + ((reg1 == NV_RAMDAC_VPLL2) ? 0x5c : 0x70)), nv40_single, pll_lim.refclk);
383 return nv_decode_pll_highregs(pNv, nvReadMC(pNv, reg1), 0, false, pll_lim.refclk);
386 /****************************************************************************\
388 * The video arbitration routines calculate some "magic" numbers. Fixes *
389 * the snow seen when accessing the framebuffer without it. *
390 * It just works (I hope). *
392 \****************************************************************************/
394 struct nv_fifo_info {
397 int graphics_burst_size;
398 int video_burst_size;
402 struct nv_sim_state {
415 static void nv4CalcArbitration(struct nv_fifo_info *fifo, struct nv_sim_state *arb)
417 int pagemiss, cas, width, video_enable, bpp;
418 int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
419 int found, mclk_extra, mclk_loop, cbs, m1, p1;
420 int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
421 int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate;
422 int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt, clwm;
424 pclk_freq = arb->pclk_khz;
425 mclk_freq = arb->mclk_khz;
426 nvclk_freq = arb->nvclk_khz;
427 pagemiss = arb->mem_page_miss;
428 cas = arb->mem_latency;
429 width = arb->memory_width >> 6;
430 video_enable = arb->enable_video;
432 mp_enable = arb->enable_mp;
462 mclk_loop = mclks + mclk_extra;
463 us_m = mclk_loop * 1000 * 1000 / mclk_freq;
464 us_n = nvclks * 1000 * 1000 / nvclk_freq;
465 us_p = nvclks * 1000 * 1000 / pclk_freq;
467 video_drain_rate = pclk_freq * 2;
468 crtc_drain_rate = pclk_freq * bpp / 8;
472 vpm_us = vpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
473 if (nvclk_freq * 2 > mclk_freq * width)
474 video_fill_us = cbs * 1000 * 1000 / 16 / nvclk_freq;
476 video_fill_us = cbs * 1000 * 1000 / (8 * width) / mclk_freq;
477 us_video = vpm_us + us_m + us_n + us_p + video_fill_us;
478 vlwm = us_video * video_drain_rate / (1000 * 1000);
483 if (vlwm > (256 - 64))
485 if (nvclk_freq * 2 > mclk_freq * width)
486 video_fill_us = vbs * 1000 * 1000 / 16 / nvclk_freq;
488 video_fill_us = vbs * 1000 * 1000 / (8 * width) / mclk_freq;
489 cpm_us = crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
490 us_crt = us_video + video_fill_us + cpm_us + us_m + us_n + us_p;
491 clwm = us_crt * crtc_drain_rate / (1000 * 1000);
494 crtc_drain_rate = pclk_freq * bpp / 8;
497 cpm_us = crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
498 us_crt = cpm_us + us_m + us_n + us_p;
499 clwm = us_crt * crtc_drain_rate / (1000 * 1000);
502 m1 = clwm + cbs - 512;
503 p1 = m1 * pclk_freq / mclk_freq;
505 if ((p1 < m1 && m1 > 0) ||
506 (video_enable && (clwm > 511 || vlwm > 255)) ||
507 (!video_enable && clwm > 519)) {
516 fifo->graphics_lwm = clwm;
517 fifo->graphics_burst_size = 128;
518 fifo->video_lwm = vlwm + 15;
519 fifo->video_burst_size = vbs;
523 static void nv10CalcArbitration(struct nv_fifo_info *fifo, struct nv_sim_state *arb)
525 int pagemiss, width, video_enable, bpp;
526 int nvclks, mclks, pclks, vpagemiss, crtpagemiss;
528 int found, mclk_extra, mclk_loop, cbs, m1;
529 int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
530 int us_m, us_m_min, us_n, us_p, crtc_drain_rate;
532 int vpm_us, us_video, cpm_us, us_crt, clwm;
534 int m2us, us_pipe_min, p1clk, p2;
536 int us_min_mclk_extra;
538 pclk_freq = arb->pclk_khz; /* freq in KHz */
539 mclk_freq = arb->mclk_khz;
540 nvclk_freq = arb->nvclk_khz;
541 pagemiss = arb->mem_page_miss;
542 width = arb->memory_width / 64;
543 video_enable = arb->enable_video;
545 mp_enable = arb->enable_mp;
548 pclks = 4; /* lwm detect. */
549 nvclks = 3; /* lwm -> sync. */
550 nvclks += 2; /* fbi bus cycles (1 req + 1 busy) */
551 mclks = 1; /* 2 edge sync. may be very close to edge so just put one. */
552 mclks += 1; /* arb_hp_req */
553 mclks += 5; /* ap_hp_req tiling pipeline */
554 mclks += 2; /* tc_req latency fifo */
555 mclks += 2; /* fb_cas_n_ memory request to fbio block */
556 mclks += 7; /* sm_d_rdv data returned from fbio block */
558 /* fb.rd.d.Put_gc need to accumulate 256 bits for read */
559 if (arb->memory_type == 0) {
560 if (arb->memory_width == 64) /* 64 bit bus */
564 } else if (arb->memory_width == 64) /* 64 bit bus */
569 if (!video_enable && arb->memory_width == 128) {
570 mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */
573 mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */
574 /* mclk_extra = 4; *//* Margin of error */
578 nvclks += 1; /* 2 edge sync. may be very close to edge so just put one. */
579 nvclks += 1; /* fbi_d_rdv_n */
580 nvclks += 1; /* Fbi_d_rdata */
581 nvclks += 1; /* crtfifo load */
584 mclks += 4; /* Mp can get in with a burst of 8. */
585 /* Extra clocks determined by heuristics */
593 mclk_loop = mclks + mclk_extra;
594 us_m = mclk_loop * 1000 * 1000 / mclk_freq; /* Mclk latency in us */
595 us_m_min = mclks * 1000 * 1000 / mclk_freq; /* Minimum Mclk latency in us */
596 us_min_mclk_extra = min_mclk_extra * 1000 * 1000 / mclk_freq;
597 us_n = nvclks * 1000 * 1000 / nvclk_freq; /* nvclk latency in us */
598 us_p = pclks * 1000 * 1000 / pclk_freq; /* nvclk latency in us */
599 us_pipe_min = us_m_min + us_n + us_p;
601 vus_m = mclk_loop * 1000 * 1000 / mclk_freq; /* Mclk latency in us */
604 crtc_drain_rate = pclk_freq * bpp / 8; /* MB/s */
606 vpagemiss = 1; /* self generating page miss */
607 vpagemiss += 1; /* One higher priority before */
609 crtpagemiss = 2; /* self generating page miss */
611 crtpagemiss += 1; /* if MA0 conflict */
613 vpm_us = vpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
615 us_video = vpm_us + vus_m; /* Video has separate read return path */
617 cpm_us = crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
618 us_crt = us_video /* Wait for video */
619 + cpm_us /* CRT Page miss */
620 + us_m + us_n + us_p; /* other latency */
622 clwm = us_crt * crtc_drain_rate / (1000 * 1000);
623 clwm++; /* fixed point <= float_point - 1. Fixes that */
625 crtc_drain_rate = pclk_freq * bpp / 8; /* bpp * pclk/8 */
627 crtpagemiss = 1; /* self generating page miss */
628 crtpagemiss += 1; /* MA0 page miss */
630 crtpagemiss += 1; /* if MA0 conflict */
631 cpm_us = crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
632 us_crt = cpm_us + us_m + us_n + us_p;
633 clwm = us_crt * crtc_drain_rate / (1000 * 1000);
634 clwm++; /* fixed point <= float_point - 1. Fixes that */
636 /* Finally, a heuristic check when width == 64 bits */
638 nvclk_fill = nvclk_freq * 8;
639 if (crtc_drain_rate * 100 >= nvclk_fill * 102)
640 clwm = 0xfff; /* Large number to fail */
641 else if (crtc_drain_rate * 100 >= nvclk_fill * 98) {
652 clwm_rnd_down = (clwm / 8) * 8;
653 if (clwm_rnd_down < clwm)
656 m1 = clwm + cbs - 1024; /* Amount of overfill */
657 m2us = us_pipe_min + us_min_mclk_extra;
659 /* pclk cycles to drain */
660 p1clk = m2us * pclk_freq / (1000 * 1000);
661 p2 = p1clk * bpp / 8; /* bytes drained. */
663 if (p2 < m1 && m1 > 0) {
666 if (min_mclk_extra == 0) {
668 found = 1; /* Can't adjust anymore! */
670 cbs = cbs / 2; /* reduce the burst size */
673 } else if (clwm > 1023) { /* Have some margin */
676 if (min_mclk_extra == 0)
677 found = 1; /* Can't adjust anymore! */
682 if (clwm < (1024 - cbs + 8))
683 clwm = 1024 - cbs + 8;
684 /* printf("CRT LWM: prog: 0x%x, bs: 256\n", clwm); */
685 fifo->graphics_lwm = clwm;
686 fifo->graphics_burst_size = cbs;
688 fifo->video_lwm = 1024;
689 fifo->video_burst_size = 512;
693 void nv4_10UpdateArbitrationSettings(ScrnInfoPtr pScrn, int VClk, int bpp, uint8_t *burst, uint16_t *lwm)
695 NVPtr pNv = NVPTR(pScrn);
696 struct nv_fifo_info fifo_data;
697 struct nv_sim_state sim_data;
698 int MClk = nv_get_clock(pScrn, MPLL);
699 int NVClk = nv_get_clock(pScrn, NVPLL);
700 uint32_t cfg1 = nvReadFB(pNv, NV_PFB_CFG1);
702 sim_data.pclk_khz = VClk;
703 sim_data.mclk_khz = MClk;
704 sim_data.nvclk_khz = NVClk;
705 sim_data.pix_bpp = bpp;
706 sim_data.enable_mp = false;
707 if ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE ||
708 (pNv->Chipset & 0xffff) == CHIPSET_NFORCE2) {
709 sim_data.enable_video = false;
710 sim_data.memory_type = (PCI_SLOT_READ_LONG(1, 0x7c) >> 12) & 1;
711 sim_data.memory_width = 64;
712 sim_data.mem_latency = 3;
713 sim_data.mem_page_miss = 10;
715 sim_data.enable_video = (pNv->Architecture != NV_ARCH_04);
716 sim_data.memory_type = nvReadFB(pNv, NV_PFB_CFG0) & 0x1;
717 sim_data.memory_width = (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64;
718 sim_data.mem_latency = cfg1 & 0xf;
719 sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1);
722 if (pNv->Architecture == NV_ARCH_04)
723 nv4CalcArbitration(&fifo_data, &sim_data);
725 nv10CalcArbitration(&fifo_data, &sim_data);
727 if (fifo_data.valid) {
728 int b = fifo_data.graphics_burst_size >> 4;
732 *lwm = fifo_data.graphics_lwm >> 3;
736 void nv30UpdateArbitrationSettings(uint8_t *burst, uint16_t *lwm)
738 unsigned int fifo_size, burst_size, graphics_lwm;
742 graphics_lwm = fifo_size - burst_size;
746 while (burst_size >>= 1)
748 *lwm = graphics_lwm >> 3;
751 /****************************************************************************\
753 * RIVA Mode State Routines *
755 \****************************************************************************/
758 * Calculate the Video Clock parameters for the PLL.
760 static void CalcVClock (
767 unsigned lowM, highM;
768 unsigned DeltaNew, DeltaOld;
772 DeltaOld = 0xFFFFFFFF;
774 VClk = (unsigned)clockIn;
776 if (pNv->CrystalFreqKHz == 13500) {
784 for (P = 0; P <= 4; P++) {
786 if ((Freq >= 128000) && (Freq <= 350000)) {
787 for (M = lowM; M <= highM; M++) {
788 N = ((VClk << P) * M) / pNv->CrystalFreqKHz;
790 Freq = ((pNv->CrystalFreqKHz * N) / M) >> P;
792 DeltaNew = Freq - VClk;
794 DeltaNew = VClk - Freq;
795 if (DeltaNew < DeltaOld) {
796 *pllOut = (P << 16) | (N << 8) | M;
806 static void CalcVClock2Stage (
814 unsigned DeltaNew, DeltaOld;
818 DeltaOld = 0xFFFFFFFF;
820 *pllBOut = 0x80000401; /* fixed at x4 for now */
822 VClk = (unsigned)clockIn;
824 for (P = 0; P <= 6; P++) {
826 if ((Freq >= 400000) && (Freq <= 1000000)) {
827 for (M = 1; M <= 13; M++) {
828 N = ((VClk << P) * M) / (pNv->CrystalFreqKHz << 2);
829 if((N >= 5) && (N <= 255)) {
830 Freq = (((pNv->CrystalFreqKHz << 2) * N) / M) >> P;
832 DeltaNew = Freq - VClk;
834 DeltaNew = VClk - Freq;
835 if (DeltaNew < DeltaOld) {
836 *pllOut = (P << 16) | (N << 8) | M;
847 * Calculate extended mode parameters (SVGA) and save in a
848 * mode state structure.
850 void NVCalcStateExt (
852 RIVA_HW_STATE *state,
861 NVPtr pNv = NVPTR(pScrn);
862 int pixelDepth, VClk = 0;
866 * Save mode parameters.
868 state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */
869 state->width = width;
870 state->height = height;
872 * Extended RIVA registers.
874 pixelDepth = (bpp + 1)/8;
876 CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB, pNv);
878 CalcVClock(dotClock, &VClk, &state->pll, pNv);
880 switch (pNv->Architecture)
883 nv4_10UpdateArbitrationSettings(pScrn, VClk,
885 &(state->arbitration0),
886 &(state->arbitration1));
887 state->cursor0 = 0x00;
888 state->cursor1 = 0xbC;
889 if (flags & V_DBLSCAN)
891 state->cursor2 = 0x00000000;
892 state->pllsel = 0x10000700;
893 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
894 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
900 if(((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
901 ((pNv->Chipset & 0xfff0) == CHIPSET_C512))
903 state->arbitration0 = 128;
904 state->arbitration1 = 0x0480;
905 } else if(pNv->Architecture < NV_ARCH_30) {
906 nv4_10UpdateArbitrationSettings(pScrn, VClk,
908 &(state->arbitration0),
909 &(state->arbitration1));
911 nv30UpdateArbitrationSettings(&(state->arbitration0),
912 &(state->arbitration1));
914 CursorStart = pNv->Cursor->offset;
915 state->cursor0 = 0x80 | (CursorStart >> 17);
916 state->cursor1 = (CursorStart >> 11) << 2;
917 state->cursor2 = CursorStart >> 24;
918 if (flags & V_DBLSCAN)
920 state->pllsel = 0x10000700;
921 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
922 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
926 if(bpp != 8) /* DirectColor */
927 state->general |= 0x00000030;
929 state->repaint0 = (((width / 8) * pixelDepth) & 0x700) >> 3;
930 state->pixel = (pixelDepth > 2) ? 3 : pixelDepth;
934 void NVLoadStateExt (
939 NVPtr pNv = NVPTR(pScrn);
942 if(pNv->Architecture >= NV_ARCH_40) {
943 switch(pNv->Chipset & 0xfff0) {
952 temp = nvReadCurRAMDAC(pNv, NV_RAMDAC_TEST_CONTROL);
953 nvWriteCurRAMDAC(pNv, NV_RAMDAC_TEST_CONTROL, temp | 0x00100000);
960 if(pNv->Architecture >= NV_ARCH_10) {
962 NVWriteCRTC(pNv, 0, NV_CRTC_FSEL, state->head);
963 NVWriteCRTC(pNv, 1, NV_CRTC_FSEL, state->head2);
965 temp = nvReadCurRAMDAC(pNv, NV_RAMDAC_NV10_CURSYNC);
966 nvWriteCurRAMDAC(pNv, NV_RAMDAC_NV10_CURSYNC, temp | (1 << 25));
968 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
969 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
970 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
971 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
972 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
973 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
974 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(0), pNv->VRAMPhysicalSize - 1);
975 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(1), pNv->VRAMPhysicalSize - 1);
976 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, 0);
978 nvWriteCurCRTC(pNv, NV_CRTC_CURSOR_CONFIG, state->cursorConfig);
979 nvWriteCurCRTC(pNv, NV_CRTC_0830, state->displayV - 3);
980 nvWriteCurCRTC(pNv, NV_CRTC_0834, state->displayV - 1);
983 if((pNv->Chipset & 0x0ff0) == CHIPSET_NV11) {
984 nvWriteCurRAMDAC(pNv, NV_RAMDAC_DITHER_NV11, state->dither);
987 nvWriteCurRAMDAC(pNv, NV_RAMDAC_FP_DITHER, state->dither);
990 nvWriteCurVGA(pNv, NV_CIO_CRE_53, state->timingH);
991 nvWriteCurVGA(pNv, NV_CIO_CRE_54, state->timingV);
992 nvWriteCurVGA(pNv, NV_CIO_CRE_21, 0xfa);
995 nvWriteCurVGA(pNv, NV_CIO_CRE_EBR_INDEX, state->extra);
998 nvWriteCurVGA(pNv, NV_CIO_CRE_RPC0_INDEX, state->repaint0);
999 nvWriteCurVGA(pNv, NV_CIO_CRE_RPC1_INDEX, state->repaint1);
1000 nvWriteCurVGA(pNv, NV_CIO_CRE_LSR_INDEX, state->screen);
1001 nvWriteCurVGA(pNv, NV_CIO_CRE_PIXEL_INDEX, state->pixel);
1002 nvWriteCurVGA(pNv, NV_CIO_CRE_HEB__INDEX, state->horiz);
1003 nvWriteCurVGA(pNv, NV_CIO_CRE_ENH_INDEX, state->fifo);
1004 nvWriteCurVGA(pNv, NV_CIO_CRE_FF_INDEX, state->arbitration0);
1005 nvWriteCurVGA(pNv, NV_CIO_CRE_FFLWM__INDEX, state->arbitration1);
1006 if(pNv->Architecture >= NV_ARCH_30) {
1007 nvWriteCurVGA(pNv, NV_CIO_CRE_47, state->arbitration1 >> 8);
1010 nvWriteCurVGA(pNv, NV_CIO_CRE_HCUR_ADDR0_INDEX, state->cursor0);
1011 nvWriteCurVGA(pNv, NV_CIO_CRE_HCUR_ADDR1_INDEX, state->cursor1);
1012 if(pNv->Architecture == NV_ARCH_40) { /* HW bug */
1013 volatile CARD32 curpos = nvReadCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS);
1014 nvWriteCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS, curpos);
1016 nvWriteCurVGA(pNv, NV_CIO_CRE_HCUR_ADDR2_INDEX, state->cursor2);
1017 nvWriteCurVGA(pNv, NV_CIO_CRE_ILACE__INDEX, state->interlace);
1019 if(!pNv->FlatPanel) {
1020 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
1021 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL, state->vpll);
1023 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2, state->vpll2);
1024 if(pNv->twoStagePLL) {
1025 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B, state->vpllB);
1026 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B, state->vpll2B);
1029 nvWriteCurRAMDAC(pNv, NV_RAMDAC_FP_CONTROL, state->scale);
1030 nvWriteCurRAMDAC(pNv, NV_RAMDAC_FP_HCRTC, state->crtcSync);
1032 nvWriteCurRAMDAC(pNv, NV_RAMDAC_GENERAL_CONTROL, state->general);
1034 nvWriteCurCRTC(pNv, NV_CRTC_INTR_EN_0, 0);
1035 nvWriteCurCRTC(pNv, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
1038 void NVUnloadStateExt
1041 RIVA_HW_STATE *state
1044 state->repaint0 = nvReadCurVGA(pNv, NV_CIO_CRE_RPC0_INDEX);
1045 state->repaint1 = nvReadCurVGA(pNv, NV_CIO_CRE_RPC1_INDEX);
1046 state->screen = nvReadCurVGA(pNv, NV_CIO_CRE_LSR_INDEX);
1047 state->pixel = nvReadCurVGA(pNv, NV_CIO_CRE_PIXEL_INDEX);
1048 state->horiz = nvReadCurVGA(pNv, NV_CIO_CRE_HEB__INDEX);
1049 state->fifo = nvReadCurVGA(pNv, NV_CIO_CRE_ENH_INDEX);
1050 state->arbitration0 = nvReadCurVGA(pNv, NV_CIO_CRE_FF_INDEX);
1051 state->arbitration1 = nvReadCurVGA(pNv, NV_CIO_CRE_FFLWM__INDEX);
1052 if(pNv->Architecture >= NV_ARCH_30) {
1053 state->arbitration1 |= (nvReadCurVGA(pNv, NV_CIO_CRE_47) & 1) << 8;
1055 state->cursor0 = nvReadCurVGA(pNv, NV_CIO_CRE_HCUR_ADDR0_INDEX);
1056 state->cursor1 = nvReadCurVGA(pNv, NV_CIO_CRE_HCUR_ADDR1_INDEX);
1057 state->cursor2 = nvReadCurVGA(pNv, NV_CIO_CRE_HCUR_ADDR2_INDEX);
1058 state->interlace = nvReadCurVGA(pNv, NV_CIO_CRE_ILACE__INDEX);
1060 state->vpll = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL);
1062 state->vpll2 = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2);
1063 if(pNv->twoStagePLL) {
1064 state->vpllB = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B);
1065 state->vpll2B = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B);
1067 state->pllsel = NVReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT);
1068 state->general = nvReadCurRAMDAC(pNv, NV_RAMDAC_GENERAL_CONTROL);
1069 state->scale = nvReadCurRAMDAC(pNv, NV_RAMDAC_FP_CONTROL);
1071 if(pNv->Architecture >= NV_ARCH_10) {
1073 state->head = NVReadCRTC(pNv, 0, NV_CRTC_FSEL);
1074 state->head2 = NVReadCRTC(pNv, 1, NV_CRTC_FSEL);
1075 state->crtcOwner = nvReadCurVGA(pNv, NV_CIO_CRE_44);
1077 state->extra = nvReadCurVGA(pNv, NV_CIO_CRE_EBR_INDEX);
1079 state->cursorConfig = nvReadCurCRTC(pNv, NV_CRTC_CURSOR_CONFIG);
1081 if((pNv->Chipset & 0x0ff0) == CHIPSET_NV11) {
1082 state->dither = nvReadCurRAMDAC(pNv, NV_RAMDAC_DITHER_NV11);
1085 state->dither = nvReadCurRAMDAC(pNv, NV_RAMDAC_FP_DITHER);
1088 if(pNv->FlatPanel) {
1089 state->timingH = nvReadCurVGA(pNv, NV_CIO_CRE_53);
1090 state->timingV = nvReadCurVGA(pNv, NV_CIO_CRE_54);
1094 if(pNv->FlatPanel) {
1095 state->crtcSync = nvReadCurRAMDAC(pNv, NV_RAMDAC_FP_HCRTC);
1099 void NVSetStartAddress (
1104 nvWriteCurCRTC(pNv, NV_CRTC_START, start);
1107 uint32_t nv_pitch_align(NVPtr pNv, uint32_t width, int bpp)
1116 /* Alignment requirements taken from the Haiku driver */
1117 if (pNv->Architecture == NV_ARCH_04)
1118 mask = 128 / bpp - 1;
1120 mask = 512 / bpp - 1;
1122 return (width + mask) & ~mask;
1125 void nv_save_restore_vga_fonts(ScrnInfoPtr pScrn, bool save)
1127 NVPtr pNv = NVPTR(pScrn);
1129 uint8_t misc, gr4, gr5, gr6, seq2, seq4;
1132 NVSetEnablePalette(pNv, 0, true);
1133 graphicsmode = NVReadVgaAttr(pNv, 0, NV_CIO_AR_MODE_INDEX) & 1;
1134 NVSetEnablePalette(pNv, 0, false);
1136 if (graphicsmode) /* graphics mode => framebuffer => no need to save */
1139 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%sing VGA fonts\n", save ? "Sav" : "Restor");
1141 NVBlankScreen(pNv, 1, true);
1142 NVBlankScreen(pNv, 0, true);
1144 /* save control regs */
1145 misc = NVReadPRMVIO(pNv, 0, NV_PRMVIO_MISC__READ);
1146 seq2 = NVReadVgaSeq(pNv, 0, NV_VIO_SR_PLANE_MASK_INDEX);
1147 seq4 = NVReadVgaSeq(pNv, 0, NV_VIO_SR_MEM_MODE_INDEX);
1148 gr4 = NVReadVgaGr(pNv, 0, NV_VIO_GX_READ_MAP_INDEX);
1149 gr5 = NVReadVgaGr(pNv, 0, NV_VIO_GX_MODE_INDEX);
1150 gr6 = NVReadVgaGr(pNv, 0, NV_VIO_GX_MISC_INDEX);
1152 NVWritePRMVIO(pNv, 0, NV_PRMVIO_MISC__WRITE, 0x67);
1153 NVWriteVgaSeq(pNv, 0, NV_VIO_SR_MEM_MODE_INDEX, 0x6);
1154 NVWriteVgaGr(pNv, 0, NV_VIO_GX_MODE_INDEX, 0x0);
1155 NVWriteVgaGr(pNv, 0, NV_VIO_GX_MISC_INDEX, 0x5);
1157 /* store font in plane 0 */
1158 NVWriteVgaSeq(pNv, 0, NV_VIO_SR_PLANE_MASK_INDEX, 0x1);
1159 NVWriteVgaGr(pNv, 0, NV_VIO_GX_READ_MAP_INDEX, 0x0);
1160 for (i = 0; i < 16384; i++)
1162 pNv->saved_vga_font[0][i] = MMIO_IN32(pNv->FB_BAR, i * 4);
1164 MMIO_OUT32(pNv->FB_BAR, i * 4, pNv->saved_vga_font[0][i]);
1166 /* store font in plane 1 */
1167 NVWriteVgaSeq(pNv, 0, NV_VIO_SR_PLANE_MASK_INDEX, 0x2);
1168 NVWriteVgaGr(pNv, 0, NV_VIO_GX_READ_MAP_INDEX, 0x1);
1169 for (i = 0; i < 16384; i++)
1171 pNv->saved_vga_font[1][i] = MMIO_IN32(pNv->FB_BAR, i * 4);
1173 MMIO_OUT32(pNv->FB_BAR, i * 4, pNv->saved_vga_font[1][i]);
1175 /* store font in plane 2 */
1176 NVWriteVgaSeq(pNv, 0, NV_VIO_SR_PLANE_MASK_INDEX, 0x4);
1177 NVWriteVgaGr(pNv, 0, NV_VIO_GX_READ_MAP_INDEX, 0x2);
1178 for (i = 0; i < 16384; i++)
1180 pNv->saved_vga_font[2][i] = MMIO_IN32(pNv->FB_BAR, i * 4);
1182 MMIO_OUT32(pNv->FB_BAR, i * 4, pNv->saved_vga_font[2][i]);
1184 /* store font in plane 3 */
1185 NVWriteVgaSeq(pNv, 0, NV_VIO_SR_PLANE_MASK_INDEX, 0x8);
1186 NVWriteVgaGr(pNv, 0, NV_VIO_GX_READ_MAP_INDEX, 0x3);
1187 for (i = 0; i < 16384; i++)
1189 pNv->saved_vga_font[3][i] = MMIO_IN32(pNv->FB_BAR, i * 4);
1191 MMIO_OUT32(pNv->FB_BAR, i * 4, pNv->saved_vga_font[3][i]);
1193 /* restore control regs */
1194 NVWritePRMVIO(pNv, 0, NV_PRMVIO_MISC__WRITE, misc);
1195 NVWriteVgaGr(pNv, 0, NV_VIO_GX_READ_MAP_INDEX, gr4);
1196 NVWriteVgaGr(pNv, 0, NV_VIO_GX_MODE_INDEX, gr5);
1197 NVWriteVgaGr(pNv, 0, NV_VIO_GX_MISC_INDEX, gr6);
1198 NVWriteVgaSeq(pNv, 0, NV_VIO_SR_PLANE_MASK_INDEX, seq2);
1199 NVWriteVgaSeq(pNv, 0, NV_VIO_SR_MEM_MODE_INDEX, seq4);
1202 NVBlankScreen(pNv, 1, false);
1203 NVBlankScreen(pNv, 0, false);