git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 2006 Dave Airlie
   3  * Copyright 2007 Maarten Maathuis
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
  26  * decleration is at the bottom of this file as it is rather ugly
  27  */
  28
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include <assert.h>
  34 #include "xf86.h"
  35 #include "os.h"
  36 #include "mibank.h"
  37 #include "globals.h"
  38 #include "xf86.h"
  39 #include "xf86Priv.h"
  40 #include "xf86DDC.h"
  41 #include "mipointer.h"
  42 #include "windowstr.h"
  43 #include <randrstr.h>
  44 #include <X11/extensions/render.h>
  45
  46 #include "xf86Crtc.h"
  47 #include "nv_include.h"
  48
  49 #include "vgaHW.h"
  50
  51 #define CRTC_INDEX 0x3d4
  52 #define CRTC_DATA 0x3d5
  53 #define CRTC_IN_STAT_1 0x3da
  54
  55 #define WHITE_VALUE 0x3F
  56 #define BLACK_VALUE 0x00
  57 #define OVERSCAN_VALUE 0x01
  58
  59 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  60 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  61 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  62 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  63 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  64 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  65
  66 static CARD8 NVReadPVIO(xf86CrtcPtr crtc, CARD32 address)
  67 {
  68         ScrnInfoPtr pScrn = crtc->scrn;
  69         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  70         NVPtr pNv = NVPTR(pScrn);
  71
  72         /* Only NV4x have two pvio ranges */
  73         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  74                 return NV_RD08(pNv->PVIO1, address);
  75         } else {
  76                 return NV_RD08(pNv->PVIO0, address);
  77         }
  78 }
  79
  80 static void NVWritePVIO(xf86CrtcPtr crtc, CARD32 address, CARD8 value)
  81 {
  82         ScrnInfoPtr pScrn = crtc->scrn;
  83         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  84         NVPtr pNv = NVPTR(pScrn);
  85
  86         /* Only NV4x have two pvio ranges */
  87         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  88                 NV_WR08(pNv->PVIO1, address, value);
  89         } else {
  90                 NV_WR08(pNv->PVIO0, address, value);
  91         }
  92 }
  93
  94 static void NVWriteMiscOut(xf86CrtcPtr crtc, CARD8 value)
  95 {
  96         NVWritePVIO(crtc, VGA_MISC_OUT_W, value);
  97 }
  98
  99 static CARD8 NVReadMiscOut(xf86CrtcPtr crtc)
 100 {
 101         return NVReadPVIO(crtc, VGA_MISC_OUT_R);
 102 }
 103
 104 void NVWriteVGA(NVPtr pNv, int head, CARD8 index, CARD8 value)
 105 {
 106         volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 107
 108         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 109         NV_WR08(pCRTCReg, CRTC_DATA, value);
 110 }
 111
 112 CARD8 NVReadVGA(NVPtr pNv, int head, CARD8 index)
 113 {
 114         volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 115
 116         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 117         return NV_RD08(pCRTCReg, CRTC_DATA);
 118 }
 119
 120 void NVWriteVgaCrtc(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 121 {
 122         ScrnInfoPtr pScrn = crtc->scrn;
 123         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 124         NVPtr pNv = NVPTR(pScrn);
 125
 126         NVWriteVGA(pNv, nv_crtc->head, index, value);
 127 }
 128
 129 CARD8 NVReadVgaCrtc(xf86CrtcPtr crtc, CARD8 index)
 130 {
 131         ScrnInfoPtr pScrn = crtc->scrn;
 132         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 133         NVPtr pNv = NVPTR(pScrn);
 134
 135         return NVReadVGA(pNv, nv_crtc->head, index);
 136 }
 137
 138 static void NVWriteVgaSeq(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 139 {
 140         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 141         NVWritePVIO(crtc, VGA_SEQ_DATA, value);
 142 }
 143
 144 static CARD8 NVReadVgaSeq(xf86CrtcPtr crtc, CARD8 index)
 145 {
 146         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 147         return NVReadPVIO(crtc, VGA_SEQ_DATA);
 148 }
 149
 150 static void NVWriteVgaGr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 151 {
 152         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 153         NVWritePVIO(crtc, VGA_GRAPH_DATA, value);
 154 }
 155
 156 static CARD8 NVReadVgaGr(xf86CrtcPtr crtc, CARD8 index)
 157 {
 158         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 159         return NVReadPVIO(crtc, VGA_GRAPH_DATA);
 160 }
 161
 162
 163 static void NVWriteVgaAttr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 164 {
 165   ScrnInfoPtr pScrn = crtc->scrn;
 166   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 167   NVPtr pNv = NVPTR(pScrn);
 168   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 169
 170   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 171   if (nv_crtc->paletteEnabled)
 172     index &= ~0x20;
 173   else
 174     index |= 0x20;
 175   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 176   NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
 177 }
 178
 179 static CARD8 NVReadVgaAttr(xf86CrtcPtr crtc, CARD8 index)
 180 {
 181   ScrnInfoPtr pScrn = crtc->scrn;
 182   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 183   NVPtr pNv = NVPTR(pScrn);
 184   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 185
 186   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 187   if (nv_crtc->paletteEnabled)
 188     index &= ~0x20;
 189   else
 190     index |= 0x20;
 191   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 192   return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
 193 }
 194
 195 void NVCrtcSetOwner(xf86CrtcPtr crtc)
 196 {
 197         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 198         ScrnInfoPtr pScrn = crtc->scrn;
 199         NVPtr pNv = NVPTR(pScrn);
 200         /* Non standard beheaviour required by NV11 */
 201         if (pNv) {
 202                 uint8_t owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 203                 ErrorF("pre-Owner: 0x%X\n", owner);
 204                 if (owner == 0x04) {
 205                         uint32_t pbus84 = nvReadMC(pNv, 0x1084);
 206                         ErrorF("pbus84: 0x%X\n", pbus84);
 207                         pbus84 &= ~(1<<28);
 208                         ErrorF("pbus84: 0x%X\n", pbus84);
 209                         nvWriteMC(pNv, 0x1084, pbus84);
 210                 }
 211                 /* The blob never writes owner to pcio1, so should we */
 212                 if (pNv->NVArch == 0x11) {
 213                         NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, 0xff);
 214                 }
 215                 NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, nv_crtc->crtc * 0x3);
 216                 owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 217                 ErrorF("post-Owner: 0x%X\n", owner);
 218         } else {
 219                 ErrorF("pNv pointer is NULL\n");
 220         }
 221 }
 222
 223 static void
 224 NVEnablePalette(xf86CrtcPtr crtc)
 225 {
 226   ScrnInfoPtr pScrn = crtc->scrn;
 227   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 228   NVPtr pNv = NVPTR(pScrn);
 229   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 230
 231   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 232   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
 233   nv_crtc->paletteEnabled = TRUE;
 234 }
 235
 236 static void
 237 NVDisablePalette(xf86CrtcPtr crtc)
 238 {
 239   ScrnInfoPtr pScrn = crtc->scrn;
 240   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 241   NVPtr pNv = NVPTR(pScrn);
 242   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 243
 244   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 245   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
 246   nv_crtc->paletteEnabled = FALSE;
 247 }
 248
 249 static void NVWriteVgaReg(xf86CrtcPtr crtc, CARD32 reg, CARD8 value)
 250 {
 251  ScrnInfoPtr pScrn = crtc->scrn;
 252   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 253   NVPtr pNv = NVPTR(pScrn);
 254   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 255
 256   NV_WR08(pCRTCReg, reg, value);
 257 }
 258
 259 /* perform a sequencer reset */
 260 static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
 261 {
 262   if (start)
 263     NVWriteVgaSeq(crtc, 0x00, 0x1);
 264   else
 265     NVWriteVgaSeq(crtc, 0x00, 0x3);
 266
 267 }
 268 static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
 269 {
 270         CARD8 tmp;
 271
 272         if (on) {
 273                 tmp = NVReadVgaSeq(crtc, 0x1);
 274                 NVVgaSeqReset(crtc, TRUE);
 275                 NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
 276
 277                 NVEnablePalette(crtc);
 278         } else {
 279                 /*
 280                  * Reenable sequencer, then turn on screen.
 281                  */
 282                 tmp = NVReadVgaSeq(crtc, 0x1);
 283                 NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20); /* reenable display */
 284                 NVVgaSeqReset(crtc, FALSE);
 285
 286                 NVDisablePalette(crtc);
 287         }
 288 }
 289
 290 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool Lock)
 291 {
 292         CARD8 cr11;
 293
 294         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57);
 295         cr11 = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE);
 296         if (Lock) cr11 |= 0x80;
 297         else cr11 &= ~0x80;
 298         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE, cr11);
 299 }
 300
 301 xf86OutputPtr
 302 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
 303 {
 304         ScrnInfoPtr pScrn = crtc->scrn;
 305         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 306         int i;
 307         for (i = 0; i < xf86_config->num_output; i++) {
 308                 xf86OutputPtr output = xf86_config->output[i];
 309
 310                 if (output->crtc == crtc) {
 311                         return output;
 312                 }
 313         }
 314
 315         return NULL;
 316 }
 317
 318 xf86CrtcPtr
 319 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
 320 {
 321         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 322         int i;
 323
 324         for (i = 0; i < xf86_config->num_crtc; i++) {
 325                 xf86CrtcPtr crtc = xf86_config->crtc[i];
 326                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 327                 if (nv_crtc->crtc == index)
 328                         return crtc;
 329         }
 330
 331         return NULL;
 332 }
 333
 334 /*
 335  * Calculate the Video Clock parameters for the PLL.
 336  */
 337 static void CalcVClock (
 338         uint32_t                clockIn,
 339         uint32_t                *clockOut,
 340         CARD32          *pllOut,
 341         NVPtr           pNv
 342 )
 343 {
 344         unsigned lowM, highM, highP;
 345         unsigned DeltaNew, DeltaOld;
 346         unsigned VClk, Freq;
 347         unsigned M, N, P;
 348
 349         /* M: PLL reference frequency postscaler divider */
 350         /* P: PLL VCO output postscaler divider */
 351         /* N: PLL VCO postscaler setting */
 352
 353         DeltaOld = 0xFFFFFFFF;
 354
 355         VClk = (unsigned)clockIn;
 356
 357         /* Taken from Haiku, after someone with an NV28 had an issue */
 358         switch(pNv->NVArch) {
 359                 case 0x28:
 360                         lowM = 1;
 361                         highP = 32;
 362                         if (VClk > 340000) {
 363                                 highM = 2;
 364                         } else if (VClk > 200000) {
 365                                 highM = 4;
 366                         } else if (VClk > 150000) {
 367                                 highM = 6;
 368                         } else {
 369                                 highM = 14;
 370                         }
 371                         break;
 372                 default:
 373                         lowM = 1;
 374                         highP = 16;
 375                         if (VClk > 340000) {
 376                                 highM = 2;
 377                         } else if (VClk > 250000) {
 378                                 highM = 6;
 379                         } else {
 380                                 highM = 14;
 381                         }
 382                         break;
 383         }
 384
 385         for (P = 1; P <= highP; P++) {
 386                 Freq = VClk << P;
 387                 if ((Freq >= 128000) && (Freq <= 350000)) {
 388                         for (M = lowM; M <= highM; M++) {
 389                                 N = ((VClk << P) * M) / pNv->CrystalFreqKHz;
 390                                 if (N <= 255) {
 391                                         Freq = ((pNv->CrystalFreqKHz * N) / M) >> P;
 392                                         if (Freq > VClk) {
 393                                                 DeltaNew = Freq - VClk;
 394                                         } else {
 395                                                 DeltaNew = VClk - Freq;
 396                                         }
 397                                         if (DeltaNew < DeltaOld) {
 398                                                 *pllOut   = (P << 16) | (N << 8) | M;
 399                                                 *clockOut = Freq;
 400                                                 DeltaOld  = DeltaNew;
 401                                         }
 402                                 }
 403                         }
 404                 }
 405         }
 406 }
 407
 408 static void CalcVClock2Stage (
 409         uint32_t                clockIn,
 410         uint32_t                *clockOut,
 411         CARD32          *pllOut,
 412         CARD32          *pllBOut,
 413         NVPtr           pNv
 414 )
 415 {
 416         unsigned DeltaNew, DeltaOld;
 417         unsigned VClk, Freq;
 418         unsigned M, N, P;
 419         unsigned lowM, highM, highP;
 420
 421         DeltaOld = 0xFFFFFFFF;
 422
 423         *pllBOut = 0x80000401;  /* fixed at x4 for now */
 424
 425         VClk = (unsigned)clockIn;
 426
 427         /* Taken from Haiku, after someone with an NV28 had an issue */
 428         switch(pNv->NVArch) {
 429                 case 0x28:
 430                         lowM = 1;
 431                         highP = 32;
 432                         if (VClk > 340000) {
 433                                 highM = 2;
 434                         } else if (VClk > 200000) {
 435                                 highM = 4;
 436                         } else if (VClk > 150000) {
 437                                 highM = 6;
 438                         } else {
 439                                 highM = 14;
 440                         }
 441                         break;
 442                 default:
 443                         lowM = 1;
 444                         highP = 15;
 445                         if (VClk > 340000) {
 446                                 highM = 2;
 447                         } else if (VClk > 250000) {
 448                                 highM = 6;
 449                         } else {
 450                                 highM = 14;
 451                         }
 452                         break;
 453         }
 454
 455         for (P = 0; P <= highP; P++) {
 456                 Freq = VClk << P;
 457                 if ((Freq >= 400000) && (Freq <= 1000000)) {
 458                         for (M = lowM; M <= highM; M++) {
 459                                 N = ((VClk << P) * M) / (pNv->CrystalFreqKHz << 2);
 460                                 if ((N >= 5) && (N <= 255)) {
 461                                         Freq = (((pNv->CrystalFreqKHz << 2) * N) / M) >> P;
 462                                         if (Freq > VClk) {
 463                                                 DeltaNew = Freq - VClk;
 464                                         } else {
 465                                                 DeltaNew = VClk - Freq;
 466                                         }
 467                                         if (DeltaNew < DeltaOld) {
 468                                                 *pllOut   = (P << 16) | (N << 8) | M;
 469                                                 *clockOut = Freq;
 470                                                 DeltaOld  = DeltaNew;
 471                                         }
 472                                 }
 473                         }
 474                 }
 475         }
 476 }
 477
 478 /* BIG NOTE: modifying vpll1 and vpll2 does not work, what bit is the switch to allow it? */
 479
 480 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
 481 /* They are only valid for NV4x, appearantly reordered for NV5x */
 482 /* gpu pll: 0x4000 + 0x4004
 483  * unknown pll: 0x4008 + 0x400c
 484  * vpll1: 0x4010 + 0x4014
 485  * vpll2: 0x4018 + 0x401c
 486  * unknown pll: 0x4020 + 0x4024
 487  * unknown pll: 0x4038 + 0x403c
 488  * Some of the unknown's are probably memory pll's.
 489  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
 490  * 1 and 2 refer to the registers of each pair. There is only one post divider.
 491  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
 492  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
 493  *     bit8: A switch that turns of the second divider and multiplier off.
 494  *     bit12: Also a switch, i haven't seen it yet.
 495  *     bit16-19: p-divider
 496  *     but 28-31: Something related to the mode that is used (see bit8).
 497  * 2) bit0-7: m-divider (a)
 498  *     bit8-15: n-multiplier (a)
 499  *     bit16-23: m-divider (b)
 500  *     bit24-31: n-multiplier (b)
 501  */
 502
 503 /* Modifying the gpu pll for example requires:
 504  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 505  * This is not needed for the vpll's which have their own bits.
 506  */
 507
 508 static void
 509 CalculateVClkNV4x(
 510         NVPtr pNv,
 511         uint32_t requested_clock,
 512         uint32_t *given_clock,
 513         uint32_t *pll_a,
 514         uint32_t *pll_b,
 515         uint32_t *reg580,
 516         Bool    *db1_ratio,
 517         Bool primary
 518 )
 519 {
 520         uint32_t DeltaOld, DeltaNew;
 521         uint32_t freq, temp;
 522         /* We have 2 mulitpliers, 2 dividers and one post divider */
 523         /* Note that p is only 4 bits */
 524         uint32_t m1, m2, n1, n2, p;
 525         uint32_t m1_best = 0, m2_best = 0, n1_best = 0, n2_best = 0, p_best = 0;
 526
 527         DeltaOld = 0xFFFFFFFF;
 528
 529         /* This is no solid limit, but a reasonable boundary */
 530         if (requested_clock < 120000) {
 531                 *db1_ratio = TRUE;
 532                 /* Turn the second set of divider and multiplier off */
 533                 /* Neutral settings */
 534                 n2 = 1;
 535                 m2 = 1;
 536         } else {
 537                 *db1_ratio = FALSE;
 538                 /* Fixed at x4 for the moment */
 539                 n2 = 4;
 540                 m2 = 1;
 541         }
 542
 543         n2_best = n2;
 544         m2_best = m2;
 545
 546         /* Single pll */
 547         if (*db1_ratio) {
 548                 temp = 0.4975 * 250000;
 549                 p = 0;
 550
 551                 while (requested_clock <= temp) {
 552                         temp /= 2;
 553                         p++;
 554                 }
 555
 556                 /* The minimum clock after m1 is 3 Mhz, and the clock is 27 Mhz, so m_max = 9 */
 557                 /* The maximum clock is 25 Mhz */
 558                 for (m1 = 2; m1 <= 9; m1++) {
 559                         n1 = ((requested_clock << p) * m1)/(pNv->CrystalFreqKHz);
 560                         if (n1 > 0 && n1 <= 255) {
 561                                 freq = ((pNv->CrystalFreqKHz * n1)/m1) >> p;
 562                                 if (freq > requested_clock) {
 563                                         DeltaNew = freq - requested_clock;
 564                                 } else {
 565                                         DeltaNew = requested_clock - freq;
 566                                 }
 567                                 if (DeltaNew < DeltaOld) {
 568                                         m1_best = m1;
 569                                         n1_best = n1;
 570                                         p_best = p;
 571                                         DeltaOld = DeltaNew;
 572                                 }
 573                         }
 574                 }
 575         /* Dual pll */
 576         } else {
 577                 for (p = 0; p <= 6; p++) {
 578                         /* Assuming a fixed 2nd stage */
 579                         freq = requested_clock << p;
 580                         /* The maximum output frequency of stage 2 is allowed to be between 400 Mhz and 1 GHz */
 581                         if (freq > 400000 && freq < 1000000) {
 582                                 /* The minimum clock after m1 is 3 Mhz, and the clock is 27 Mhz, so m_max = 9 */
 583                                 /* The maximum clock is 25 Mhz */
 584                                 for (m1 = 2; m1 <= 9; m1++) {
 585                                         n1 = ((requested_clock << p) * m1 * m2)/(pNv->CrystalFreqKHz * n2);
 586                                         if (n1 >= 5 && n1 <= 255) {
 587                                                 freq = ((pNv->CrystalFreqKHz * n1 * n2)/(m1 * m2)) >> p;
 588                                                 if (freq > requested_clock) {
 589                                                         DeltaNew = freq - requested_clock;
 590                                                 } else {
 591                                                         DeltaNew = requested_clock - freq;
 592                                                 }
 593                                                 if (DeltaNew < DeltaOld) {
 594                                                         m1_best = m1;
 595                                                         n1_best = n1;
 596                                                         p_best = p;
 597                                                         DeltaOld = DeltaNew;
 598                                                 }
 599                                         }
 600                                 }
 601                         }
 602                 }
 603         }
 604
 605         if (*db1_ratio) {
 606                 /* Bogus data, the same nvidia uses */
 607                 n2_best = 1;
 608                 m2_best = 31;
 609         }
 610
 611         /* What exactly are the purpose of bit30 (a) and bit31(b)? */
 612         *pll_a = (1 << 30) | (p_best << 16) | (n1_best << 8) | (m1_best << 0);
 613         *pll_b = (1 << 31) | (n2_best << 8) | (m2_best << 0);
 614
 615         if (*db1_ratio) {
 616                 if (primary) {
 617                         *reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 618                 } else {
 619                         *reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 620                 }
 621         } else {
 622                 if (primary) {
 623                         *reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
 624                 } else {
 625                         *reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
 626                 }
 627         }
 628
 629         if (*db1_ratio) {
 630                 ErrorF("vpll: n1 %d m1 %d p %d db1_ratio %d\n", n1_best, m1_best, p_best, *db1_ratio);
 631         } else {
 632                 ErrorF("vpll: n1 %d n2 %d m1 %d m2 %d p %d db1_ratio %d\n", n1_best, n2_best, m1_best, m2_best, p_best, *db1_ratio);
 633         }
 634 }
 635
 636 static void nv40_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 637 {
 638         state->vpll1_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 639         state->vpll1_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 640         state->vpll2_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 641         state->vpll2_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 642         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 643         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 644         state->reg580 = nvReadRAMDAC0(pNv, NV_RAMDAC_580);
 645 }
 646
 647 static void nv40_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 648 {
 649         CARD32 fp_debug_0[2];
 650         uint32_t index[2];
 651         fp_debug_0[0] = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
 652         fp_debug_0[1] = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
 653
 654         /* The TMDS_PLL switch is on the actual ramdac */
 655         if (state->crosswired) {
 656                 index[0] = 1;
 657                 index[1] = 0;
 658                 ErrorF("Crosswired pll state load\n");
 659         } else {
 660                 index[0] = 0;
 661                 index[1] = 1;
 662         }
 663
 664         if (state->vpll2_b) {
 665                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0,
 666                         fp_debug_0[index[1]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 667
 668                 /* Wait for the situation to stabilise */
 669                 usleep(5000);
 670
 671                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 672                 /* for vpll2 change bits 18 and 19 are disabled */
 673                 reg_c040 &= ~(0x3 << 18);
 674                 nvWriteMC(pNv, 0xc040, reg_c040);
 675
 676                 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 677                 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 678
 679                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2_a);
 680                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 681
 682                 ErrorF("writing pllsel %08X\n", state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 683                 /* Let's keep the primary vpll off */
 684                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 685
 686                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 687                 ErrorF("writing reg580 %08X\n", state->reg580);
 688
 689                 /* We need to wait a while */
 690                 usleep(5000);
 691                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 692
 693                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[1]]);
 694
 695                 /* Wait for the situation to stabilise */
 696                 usleep(5000);
 697         }
 698
 699         if (state->vpll1_b) {
 700                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0,
 701                         fp_debug_0[index[0]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 702
 703                 /* Wait for the situation to stabilise */
 704                 usleep(5000);
 705
 706                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 707                 /* for vpll2 change bits 16 and 17 are disabled */
 708                 reg_c040 &= ~(0x3 << 16);
 709                 nvWriteMC(pNv, 0xc040, reg_c040);
 710
 711                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 712                 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 713
 714                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll1_a);
 715                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpll1_b);
 716
 717                 ErrorF("writing pllsel %08X\n", state->pllsel);
 718                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 719
 720                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 721                 ErrorF("writing reg580 %08X\n", state->reg580);
 722
 723                 /* We need to wait a while */
 724                 usleep(5000);
 725                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 726
 727                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[0]]);
 728
 729                 /* Wait for the situation to stabilise */
 730                 usleep(5000);
 731         }
 732
 733         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 734         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 735 }
 736
 737 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 738 {
 739         state->vpll = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 740         if(pNv->twoHeads) {
 741                 state->vpll2 = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 742         }
 743         if(pNv->twoStagePLL) {
 744                 state->vpllB = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 745                 state->vpll2B = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 746         }
 747         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 748         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 749 }
 750
 751
 752 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 753 {
 754         if (state->vpll2) {
 755                 if(pNv->twoHeads) {
 756                         ErrorF("writing vpll2 %08X\n", state->vpll2);
 757                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2);
 758                 }
 759                 if(pNv->twoStagePLL) {
 760                         ErrorF("writing vpll2B %08X\n", state->vpll2B);
 761                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2B);
 762                 }
 763
 764                 ErrorF("writing pllsel %08X\n", state->pllsel);
 765                 /* Let's keep the primary vpll off */
 766                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 767         }
 768
 769         if (state->vpll) {
 770                 ErrorF("writing vpll %08X\n", state->vpll);
 771                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll);
 772                 if(pNv->twoStagePLL) {
 773                         ErrorF("writing vpllB %08X\n", state->vpllB);
 774                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpllB);
 775                 }
 776
 777                 ErrorF("writing pllsel %08X\n", state->pllsel);
 778                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 779         }
 780
 781         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 782         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 783 }
 784
 785 /*
 786  * Calculate extended mode parameters (SVGA) and save in a
 787  * mode state structure.
 788  * State is not specific to a single crtc, but shared.
 789  */
 790 void nv_crtc_calc_state_ext(
 791         xf86CrtcPtr     crtc,
 792         int                     bpp,
 793         int                     DisplayWidth, /* Does this change after setting the mode? */
 794         int                     CrtcHDisplay,
 795         int                     CrtcVDisplay,
 796         int                     dotClock,
 797         int                     flags
 798 )
 799 {
 800         ScrnInfoPtr pScrn = crtc->scrn;
 801         uint32_t pixelDepth, VClk = 0;
 802         CARD32 CursorStart;
 803         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 804         xf86CrtcConfigPtr   xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 805         NVCrtcRegPtr regp;
 806         NVPtr pNv = NVPTR(pScrn);
 807         RIVA_HW_STATE *state;
 808         int num_crtc_enabled, i;
 809
 810         state = &pNv->ModeReg;
 811
 812         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 813
 814         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 815         NVOutputPrivatePtr nv_output = output->driver_private;
 816
 817         /*
 818          * Extended RIVA registers.
 819          */
 820         pixelDepth = (bpp + 1)/8;
 821         if (pNv->Architecture == NV_ARCH_40) {
 822                 /* Does register 0x580 already have a value? */
 823                 if (!state->reg580) {
 824                         state->reg580 = pNv->misc_info.ramdac_0_reg_580;
 825                 }
 826                 if (nv_output->ramdac == 1) {
 827                         CalculateVClkNV4x(pNv, dotClock, &VClk, &state->vpll2_a, &state->vpll2_b, &state->reg580, &state->db1_ratio[1], FALSE);
 828                 } else {
 829                         CalculateVClkNV4x(pNv, dotClock, &VClk, &state->vpll1_a, &state->vpll1_b, &state->reg580, &state->db1_ratio[0], TRUE);
 830                 }
 831         } else if (pNv->twoStagePLL) {
 832                 CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB, pNv);
 833         } else {
 834                 CalcVClock(dotClock, &VClk, &state->pll, pNv);
 835         }
 836
 837         switch (pNv->Architecture) {
 838         case NV_ARCH_04:
 839                 nv4UpdateArbitrationSettings(VClk,
 840                                                 pixelDepth * 8,
 841                                                 &(state->arbitration0),
 842                                                 &(state->arbitration1),
 843                                                 pNv);
 844                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
 845                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
 846                 if (flags & V_DBLSCAN)
 847                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 848                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
 849                 state->pllsel   |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
 850                 state->config   = 0x00001114;
 851                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 852                 break;
 853         case NV_ARCH_10:
 854         case NV_ARCH_20:
 855         case NV_ARCH_30:
 856         default:
 857                 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
 858                         ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
 859                         state->arbitration0 = 128;
 860                         state->arbitration1 = 0x0480;
 861                 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
 862                         ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
 863                         nForceUpdateArbitrationSettings(VClk,
 864                                                 pixelDepth * 8,
 865                                                 &(state->arbitration0),
 866                                                 &(state->arbitration1),
 867                                                 pNv);
 868                 } else if (pNv->Architecture < NV_ARCH_30) {
 869                         nv10UpdateArbitrationSettings(VClk,
 870                                                 pixelDepth * 8,
 871                                                 &(state->arbitration0),
 872                                                 &(state->arbitration1),
 873                                                 pNv);
 874                 } else {
 875                         nv30UpdateArbitrationSettings(pNv,
 876                                                 &(state->arbitration0),
 877                                                 &(state->arbitration1));
 878                 }
 879
 880                 CursorStart = pNv->Cursor->offset;
 881
 882                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
 883                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
 884                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
 885
 886                 if (flags & V_DBLSCAN)
 887                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 888
 889                 state->config   = nvReadFB(pNv, NV_PFB_CFG0);
 890                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 891                 break;
 892         }
 893
 894         /* okay do we have 2 CRTCs running ? */
 895         num_crtc_enabled = 0;
 896         for (i = 0; i < xf86_config->num_crtc; i++) {
 897                 if (xf86_config->crtc[i]->enabled) {
 898                         num_crtc_enabled++;
 899                 }
 900         }
 901
 902         ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
 903
 904         if (pNv->Architecture < NV_ARCH_40) {
 905                 /* We need this before the next code */
 906                 if (nv_crtc->crtc == 1) {
 907                         state->vpll2 = state->pll;
 908                         state->vpll2B = state->pllB;
 909                 } else {
 910                         state->vpll = state->pll;
 911                         state->vpllB = state->pllB;
 912                 }
 913         }
 914
 915         if (pNv->Architecture == NV_ARCH_40) {
 916                 /* This register is only used on the primary ramdac */
 917                 /* This seems to be needed to select the proper clocks, otherwise bad things happen */
 918                 /* Assumption CRTC1 will overwrite the CRTC0 value */
 919                 /* Also make sure we don't set both bits */
 920
 921                 if (!state->sel_clk)
 922                         state->sel_clk = pNv->misc_info.sel_clk & ~(0xf << 16);
 923
 924                 /* The rough idea is this:
 925                  * 0x40000: One or both dvi outputs is/are on their preferred ramdac (=clock)
 926                  * 0x10000: One dvi output is on not on it's preferred ramdac (=clock).
 927                  * 0x00000: No dvi panels present.
 928                  * Other bits also exist, but we leave those intact.
 929                  * One dvi panel must always be on it's preferred ramdac, due to "or" restrictions.
 930                  */
 931
 932                 if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS) {
 933                         /* Clean out all the bits and enable another mode */
 934                         if (nv_output->ramdac == nv_output->preferred_ramdac) {
 935                                 state->sel_clk &= ~(0xf << 16);
 936                                 state->sel_clk |= (1 << 18);
 937                         } else {
 938                                 state->sel_clk &= ~(0xf << 16);
 939                                 state->sel_clk |= (1 << 16);
 940                         }
 941                 } else {
 942                         int other_index = (~nv_crtc->head) & 1;
 943                         xf86CrtcPtr crtc2 = nv_find_crtc_by_index(pScrn, other_index);
 944                         if (crtc2->enabled) {
 945                                 xf86OutputPtr output2 = NVGetOutputFromCRTC(crtc2);
 946                                 NVOutputPrivatePtr nv_output2 = output2->driver_private;
 947                                 if (nv_output2->type == OUTPUT_TMDS || nv_output2->type == OUTPUT_LVDS) {
 948                                         /* Clean out all the bits and enable another mode */
 949                                         if (nv_output2->ramdac == nv_output2->preferred_ramdac) {
 950                                                 state->sel_clk &= ~(0xf << 16);
 951                                                 state->sel_clk |= (1 << 18);
 952                                         } else {
 953                                                 state->sel_clk &= ~(0xf << 16);
 954                                                 state->sel_clk |= (1 << 16);
 955                                         }
 956                                 } else {
 957                                         /* Destroy all tmds traces */
 958                                         state->sel_clk &= ~(0xf << 16);
 959                                 }
 960                         } else {
 961                                 /* Destroy all tmds traces */
 962                                 state->sel_clk &= ~(0xf << 16);
 963                         }
 964                 }
 965
 966                 /* Are we crosswired? */
 967                 if (nv_crtc->head != nv_output->preferred_crtc &&
 968                         (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
 969                         state->crosswired = TRUE;
 970                 } else if (nv_crtc->head != nv_output->preferred_crtc) {
 971                         state->crosswired = FALSE;
 972                 }
 973
 974                 if (nv_crtc->head == 1) {
 975                         if (state->db1_ratio[1])
 976                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
 977                 } else if (nv_crtc->head == 0) {
 978                         if (state->db1_ratio[0])
 979                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
 980                 }
 981         } else {
 982                 /* This seems true for nv34 */
 983                 state->sel_clk = 0x0;
 984                 state->crosswired = FALSE;
 985         }
 986
 987         if (nv_output->ramdac == 1) {
 988                 if (!state->db1_ratio[1]) {
 989                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 990                 } else {
 991                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 992                 }
 993                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
 994         } else {
 995                 if (pNv->Architecture < NV_ARCH_40)
 996                         state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
 997                 else
 998                         state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
 999                 if (!state->db1_ratio[0]) {
1000                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1001                 } else {
1002                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1003                 }
1004         }
1005
1006         regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
1007         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
1008         if (pNv->Architecture >= NV_ARCH_30) {
1009                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
1010         }
1011
1012         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
1013         regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
1014 }
1015
1016 static void
1017 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
1018 {
1019         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1020         ScrnInfoPtr pScrn = crtc->scrn;
1021         NVPtr pNv = NVPTR(pScrn);
1022         unsigned char seq1 = 0, crtc17 = 0;
1023         unsigned char crtc1A;
1024
1025         ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->crtc, mode);
1026
1027         NVCrtcSetOwner(crtc);
1028
1029         crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
1030         switch(mode) {
1031                 case DPMSModeStandby:
1032                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
1033                 seq1 = 0x20;
1034                 crtc17 = 0x80;
1035                 crtc1A |= 0x80;
1036                 break;
1037         case DPMSModeSuspend:
1038                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
1039                 seq1 = 0x20;
1040                 crtc17 = 0x80;
1041                 crtc1A |= 0x40;
1042                 break;
1043         case DPMSModeOff:
1044                 /* Screen: Off; HSync: Off, VSync: Off */
1045                 seq1 = 0x20;
1046                 crtc17 = 0x00;
1047                 crtc1A |= 0xC0;
1048                 break;
1049         case DPMSModeOn:
1050         default:
1051                 /* Screen: On; HSync: On, VSync: On */
1052                 seq1 = 0x00;
1053                 crtc17 = 0x80;
1054                 break;
1055         }
1056
1057         NVVgaSeqReset(crtc, TRUE);
1058         /* Each head has it's own sequencer, so we can turn it off when we want */
1059         seq1 |= (NVReadVgaSeq(crtc, 0x01) & ~0x20);
1060         NVWriteVgaSeq(crtc, 0x1, seq1);
1061         crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
1062         usleep(10000);
1063         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
1064         NVVgaSeqReset(crtc, FALSE);
1065
1066         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
1067
1068         /* I hope this is the right place */
1069         if (crtc->enabled && mode == DPMSModeOn) {
1070                 pNv->crtc_active[nv_crtc->head] = TRUE;
1071         } else {
1072                 pNv->crtc_active[nv_crtc->head] = FALSE;
1073         }
1074 }
1075
1076 static Bool
1077 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
1078                      DisplayModePtr adjusted_mode)
1079 {
1080         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1081         ScrnInfoPtr pScrn = crtc->scrn;
1082         NVPtr pNv = NVPTR(pScrn);
1083         ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->crtc);
1084
1085         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1086         NVOutputPrivatePtr nv_output = output->driver_private;
1087
1088         /* For internal panels and gpu scaling on DVI we need the native mode */
1089         if ((nv_output->type == OUTPUT_LVDS) || (pNv->fpScaler && (nv_output->type == OUTPUT_TMDS))) {
1090                 adjusted_mode->HDisplay = nv_output->native_mode->HDisplay;
1091                 adjusted_mode->HSkew = nv_output->native_mode->HSkew;
1092                 adjusted_mode->HSyncStart = nv_output->native_mode->HSyncStart;
1093                 adjusted_mode->HSyncEnd = nv_output->native_mode->HSyncEnd;
1094                 adjusted_mode->HTotal = nv_output->native_mode->HTotal;
1095                 adjusted_mode->VDisplay = nv_output->native_mode->VDisplay;
1096                 adjusted_mode->VScan = nv_output->native_mode->VScan;
1097                 adjusted_mode->VSyncStart = nv_output->native_mode->VSyncStart;
1098                 adjusted_mode->VSyncEnd = nv_output->native_mode->VSyncEnd;
1099                 adjusted_mode->VTotal = nv_output->native_mode->VTotal;
1100                 adjusted_mode->Clock = nv_output->native_mode->Clock;
1101
1102                 xf86SetModeCrtc(adjusted_mode, INTERLACE_HALVE_V);
1103         }
1104
1105         return TRUE;
1106 }
1107
1108 static void
1109 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1110 {
1111         ScrnInfoPtr pScrn = crtc->scrn;
1112         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1113         NVCrtcRegPtr regp;
1114         NVPtr pNv = NVPTR(pScrn);
1115         NVFBLayout *pLayout = &pNv->CurrentLayout;
1116         int depth = pScrn->depth;
1117
1118         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1119
1120         /* Calculate our timings */
1121         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
1122         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
1123         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
1124         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
1125         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
1126         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
1127         int vertDisplay         = mode->CrtcVDisplay                    - 1;
1128         int vertStart           = mode->CrtcVSyncStart          - 1;
1129         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
1130         int vertTotal           = mode->CrtcVTotal                      - 2;
1131         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
1132         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
1133
1134         Bool is_fp = FALSE;
1135
1136         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1137         NVOutputPrivatePtr nv_output = output->driver_private;
1138
1139         if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1140                 is_fp = TRUE;
1141
1142         ErrorF("Mode clock: %d\n", mode->Clock);
1143         ErrorF("Adjusted mode clock: %d\n", adjusted_mode->Clock);
1144
1145         /* Reverted to what nv did, because that works for all resolutions on flatpanels */
1146         if (is_fp) {
1147                 vertStart = vertTotal - 3;
1148                 vertEnd = vertTotal - 2;
1149                 vertBlankStart = vertStart;
1150                 horizStart = horizTotal - 5;
1151                 horizEnd = horizTotal - 2;
1152                 horizBlankEnd = horizTotal + 4;
1153                 if (pNv->overlayAdaptor) {
1154                         /* This reportedly works around Xv some overlay bandwidth problems*/
1155                         horizTotal += 2;
1156                 }
1157         }
1158
1159         if(mode->Flags & V_INTERLACE)
1160                 vertTotal |= 1;
1161
1162         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
1163         ErrorF("horizStart: 0x%X \n", horizStart);
1164         ErrorF("horizEnd: 0x%X \n", horizEnd);
1165         ErrorF("horizTotal: 0x%X \n", horizTotal);
1166         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
1167         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
1168         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
1169         ErrorF("vertStart: 0x%X \n", vertStart);
1170         ErrorF("vertEnd: 0x%X \n", vertEnd);
1171         ErrorF("vertTotal: 0x%X \n", vertTotal);
1172         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
1173         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
1174
1175         /*
1176         * compute correct Hsync & Vsync polarity
1177         */
1178         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
1179                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
1180
1181                 regp->MiscOutReg = 0x23;
1182                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
1183                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
1184         } else {
1185                 int VDisplay = mode->VDisplay;
1186                 if (mode->Flags & V_DBLSCAN)
1187                         VDisplay *= 2;
1188                 if (mode->VScan > 1)
1189                         VDisplay *= mode->VScan;
1190                 if (VDisplay < 400) {
1191                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
1192                 } else if (VDisplay < 480) {
1193                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
1194                 } else if (VDisplay < 768) {
1195                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
1196                 } else {
1197                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
1198                 }
1199         }
1200
1201         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
1202
1203         /*
1204         * Time Sequencer
1205         */
1206         if (depth == 4) {
1207                 regp->Sequencer[0] = 0x02;
1208         } else {
1209                 regp->Sequencer[0] = 0x00;
1210         }
1211         /* 0x20 disables the sequencer */
1212         if (mode->Flags & V_CLKDIV2) {
1213                 regp->Sequencer[1] = 0x29;
1214         } else {
1215                 regp->Sequencer[1] = 0x21;
1216         }
1217         if (depth == 1) {
1218                 regp->Sequencer[2] = 1 << BIT_PLANE;
1219         } else {
1220                 regp->Sequencer[2] = 0x0F;
1221                 regp->Sequencer[3] = 0x00;                     /* Font select */
1222         }
1223         if (depth < 8) {
1224                 regp->Sequencer[4] = 0x06;                             /* Misc */
1225         } else {
1226                 regp->Sequencer[4] = 0x0E;                             /* Misc */
1227         }
1228
1229         /*
1230         * CRTC Controller
1231         */
1232         regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
1233         regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
1234         regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
1235         regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0)
1236                                 | SetBit(7);
1237         regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
1238         regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
1239                                 | SetBitField(horizEnd,4:0,4:0);
1240         regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
1241         regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
1242                                 | SetBitField(vertDisplay,8:8,1:1)
1243                                 | SetBitField(vertStart,8:8,2:2)
1244                                 | SetBitField(vertBlankStart,8:8,3:3)
1245                                 | SetBit(4)
1246                                 | SetBitField(vertTotal,9:9,5:5)
1247                                 | SetBitField(vertDisplay,9:9,6:6)
1248                                 | SetBitField(vertStart,9:9,7:7);
1249         regp->CRTC[NV_VGA_CRTCX_PRROWSCN]  = 0x00;
1250         regp->CRTC[NV_VGA_CRTCX_MAXSCLIN]  = SetBitField(vertBlankStart,9:9,5:5)
1251                                 | SetBit(6)
1252                                 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00);
1253         regp->CRTC[NV_VGA_CRTCX_VGACURCTRL] = 0x00;
1254         regp->CRTC[0xb] = 0x00;
1255         regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00;
1256         regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
1257         regp->CRTC[0xe] = 0x00;
1258         regp->CRTC[0xf] = 0x00;
1259         regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
1260         regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
1261         regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
1262         regp->CRTC[0x14] = 0x00;
1263         regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
1264         regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
1265         regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
1266         /* 0x80 enables the sequencer, we don't want that */
1267         if (depth < 8) {
1268                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xE3 & ~0x80;
1269         } else {
1270                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80;
1271         }
1272         regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
1273
1274         /*
1275          * Some extended CRTC registers (they are not saved with the rest of the vga regs).
1276          */
1277
1278         regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
1279                                 | SetBitField(vertBlankStart,10:10,3:3)
1280                                 | SetBitField(vertStart,10:10,2:2)
1281                                 | SetBitField(vertDisplay,10:10,1:1)
1282                                 | SetBitField(vertTotal,10:10,0:0);
1283
1284         regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
1285                                 | SetBitField(horizDisplay,8:8,1:1)
1286                                 | SetBitField(horizBlankStart,8:8,2:2)
1287                                 | SetBitField(horizStart,8:8,3:3);
1288
1289         regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
1290                                 | SetBitField(vertDisplay,11:11,2:2)
1291                                 | SetBitField(vertStart,11:11,4:4)
1292                                 | SetBitField(vertBlankStart,11:11,6:6);
1293
1294         if(mode->Flags & V_INTERLACE) {
1295                 horizTotal = (horizTotal >> 1) & ~1;
1296                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
1297                 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
1298         } else {
1299                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff;  /* interlace off */
1300         }
1301
1302         /*
1303         * Theory resumes here....
1304         */
1305
1306         /*
1307         * Graphics Display Controller
1308         */
1309         regp->Graphics[0] = 0x00;
1310         regp->Graphics[1] = 0x00;
1311         regp->Graphics[2] = 0x00;
1312         regp->Graphics[3] = 0x00;
1313         if (depth == 1) {
1314                 regp->Graphics[4] = BIT_PLANE;
1315                 regp->Graphics[5] = 0x00;
1316         } else {
1317                 regp->Graphics[4] = 0x00;
1318                 if (depth == 4) {
1319                         regp->Graphics[5] = 0x02;
1320                 } else {
1321                         regp->Graphics[5] = 0x40;
1322                 }
1323         }
1324         regp->Graphics[6] = 0x05;   /* only map 64k VGA memory !!!! */
1325         regp->Graphics[7] = 0x0F;
1326         regp->Graphics[8] = 0xFF;
1327
1328         /* I ditched the mono stuff */
1329         regp->Attribute[0]  = 0x00; /* standard colormap translation */
1330         regp->Attribute[1]  = 0x01;
1331         regp->Attribute[2]  = 0x02;
1332         regp->Attribute[3]  = 0x03;
1333         regp->Attribute[4]  = 0x04;
1334         regp->Attribute[5]  = 0x05;
1335         regp->Attribute[6]  = 0x06;
1336         regp->Attribute[7]  = 0x07;
1337         regp->Attribute[8]  = 0x08;
1338         regp->Attribute[9]  = 0x09;
1339         regp->Attribute[10] = 0x0A;
1340         regp->Attribute[11] = 0x0B;
1341         regp->Attribute[12] = 0x0C;
1342         regp->Attribute[13] = 0x0D;
1343         regp->Attribute[14] = 0x0E;
1344         regp->Attribute[15] = 0x0F;
1345         /* These two below are non-vga */
1346         regp->Attribute[16] = 0x01;
1347         regp->Attribute[17] = 0x00;
1348         regp->Attribute[18] = 0x0F;
1349         regp->Attribute[19] = 0x00;
1350         regp->Attribute[20] = 0x00;
1351 }
1352
1353 #define MAX_H_VALUE(i) ((0x1ff + i) << 3)
1354 #define MAX_V_VALUE(i) ((0xfff + i) << 0)
1355
1356 /**
1357  * Sets up registers for the given mode/adjusted_mode pair.
1358  *
1359  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1360  *
1361  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1362  * be easily turned on/off after this.
1363  */
1364 static void
1365 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1366 {
1367         ScrnInfoPtr pScrn = crtc->scrn;
1368         NVPtr pNv = NVPTR(pScrn);
1369         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1370         NVFBLayout *pLayout = &pNv->CurrentLayout;
1371         NVCrtcRegPtr regp, savep;
1372         unsigned int i;
1373         Bool is_fp = FALSE;
1374
1375         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1376         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1377
1378         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1379         NVOutputPrivatePtr nv_output = output->driver_private;
1380
1381         if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1382                 is_fp = TRUE;
1383
1384         /* Registers not directly related to the (s)vga mode */
1385
1386         /* bit2 = 0 -> fine pitched crtc granularity */
1387         /* The rest disables double buffering on CRTC access */
1388         regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
1389
1390         if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
1391                 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1392                 if (nv_crtc->head == 0) {
1393                         regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1394                 }
1395
1396                 if (is_fp) {
1397                         regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0) | (1 << 1);
1398                 }
1399         } else {
1400                 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
1401                 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
1402         }
1403
1404         /* I'm trusting haiku driver on this one, they say it enables an external TDMS clock */
1405         if (is_fp) {
1406                 regp->CRTC[NV_VGA_CRTCX_59] = 0x1;
1407         } else {
1408                 regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1409         }
1410
1411         /*
1412         * Initialize DAC palette.
1413         */
1414         if(pLayout->bitsPerPixel != 8 ) {
1415                 for (i = 0; i < 256; i++) {
1416                         regp->DAC[i*3]     = i;
1417                         regp->DAC[(i*3)+1] = i;
1418                         regp->DAC[(i*3)+2] = i;
1419                 }
1420         }
1421
1422         /*
1423         * Calculate the extended registers.
1424         */
1425
1426         if(pLayout->depth < 24) {
1427                 i = pLayout->depth;
1428         } else {
1429                 i = 32;
1430         }
1431
1432         if(pNv->Architecture >= NV_ARCH_10) {
1433                 pNv->CURSOR = (CARD32 *)pNv->Cursor->map;
1434         }
1435
1436         /* What is the meaning of this register? */
1437         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1438         regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
1439
1440         /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1441         /* But what are those special conditions? */
1442         if (pNv->Architecture <= NV_ARCH_30) {
1443                 if (is_fp) {
1444                         if(nv_crtc->head == 1) {
1445                                 regp->head |= NV_CRTC_FSEL_FPP1;
1446                         } else if (pNv->twoHeads) {
1447                                 regp->head |= NV_CRTC_FSEL_FPP2;
1448                         }
1449                 }
1450         } else {
1451                 /* This is observed on some g70 cards, non-flatpanel's too */
1452                 if (nv_crtc->head == 1) {
1453                         regp->head |= NV_CRTC_FSEL_FPP2;
1454                 }
1455         }
1456
1457         /* Except for rare conditions I2C is enabled on the primary crtc */
1458         if (nv_crtc->head == 0) {
1459                 if (pNv->overlayAdaptor) {
1460                         regp->head |= NV_CRTC_FSEL_OVERLAY;
1461                 }
1462                 regp->head |= NV_CRTC_FSEL_I2C;
1463         }
1464
1465         /* This is not what nv does, but it is what the blob does (for nv4x at least) */
1466         /* This fixes my cursor corruption issue */
1467         regp->cursorConfig = 0x0;
1468         if(mode->Flags & V_DBLSCAN)
1469                 regp->cursorConfig |= (1 << 4);
1470         if (pNv->alphaCursor) {
1471                 /* bit28 means we go into alpha blend mode and not rely on the current ROP */
1472                 regp->cursorConfig |= 0x14011000;
1473         } else {
1474                 regp->cursorConfig |= 0x02000000;
1475         }
1476
1477         /* Unblock some timings */
1478         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1479         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1480
1481         /* 0x20 seems to be enabled and 0x14 disabled */
1482         regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1483
1484         /* 0x00 is disabled, 0x22 crt and 0x88 dfp */
1485         /* 0x11 is LVDS? */
1486         if (is_fp) {
1487                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1488         } else {
1489                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1490         }
1491
1492         /* These values seem to vary */
1493         regp->CRTC[NV_VGA_CRTCX_3C] = savep->CRTC[NV_VGA_CRTCX_3C];
1494
1495         /* 0x80 seems to be used very often, if not always */
1496         regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1497
1498         /* Are these(0x55 and 0x56) also timing related registers, since disabling them does nothing? */
1499         regp->CRTC[NV_VGA_CRTCX_55] = 0x0;
1500
1501         /* Common values like 0x14 and 0x04 are converted to 0x10 and 0x00 */
1502         //regp->CRTC[NV_VGA_CRTCX_56] = savep->CRTC[NV_VGA_CRTCX_56] & ~(1<<4);
1503         regp->CRTC[NV_VGA_CRTCX_56] = 0x0;
1504
1505         regp->CRTC[NV_VGA_CRTCX_57] = 0x0;
1506
1507         /* bit0: Seems to be mostly used on crtc1 */
1508         /* bit1: 1=crtc1, 0=crtc, but i'm unsure about this */
1509         /* 0x7E (crtc0, only seen in one dump) and 0x7F (crtc1) seem to be some kind of disable setting */
1510         /* This is likely to be incomplete */
1511         /* This is a very strange register, changed very often by the blob */
1512         regp->CRTC[NV_VGA_CRTCX_58] = 0x0;
1513
1514         /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1*/
1515         if (nv_crtc->head == 1) {
1516                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52;
1517         } else {
1518                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52 + 4;
1519         }
1520
1521         /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1522         regp->unk81c = nvReadCRTC0(pNv, NV_CRTC_081C);
1523
1524         regp->unk830 = mode->CrtcVDisplay - 3;
1525         regp->unk834 = mode->CrtcVDisplay - 1;
1526
1527         /* This is what the blob does */
1528         regp->unk850 = nvReadCRTC(pNv, 0, NV_CRTC_0850);
1529
1530         /* Never ever modify gpio, unless you know very well what you're doing */
1531         regp->gpio = nvReadCRTC(pNv, 0, NV_CRTC_GPIO);
1532
1533         /*
1534          * Calculate the state that is common to all crtc's (stored in the state struct).
1535          */
1536         ErrorF("crtc %d %d %d\n", nv_crtc->crtc, mode->CrtcHDisplay, pScrn->displayWidth);
1537         nv_crtc_calc_state_ext(crtc,
1538                                 i,
1539                                 pScrn->displayWidth,
1540                                 mode->CrtcHDisplay,
1541                                 mode->CrtcVDisplay,
1542                                 adjusted_mode->Clock,
1543                                 mode->Flags);
1544
1545         /* Enable slaved mode */
1546         if (is_fp) {
1547                 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1548         }
1549 }
1550
1551 static void
1552 nv_crtc_mode_set_ramdac_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1553 {
1554         ScrnInfoPtr pScrn = crtc->scrn;
1555         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1556         NVCrtcRegPtr regp;
1557         NVPtr pNv = NVPTR(pScrn);
1558         NVFBLayout *pLayout = &pNv->CurrentLayout;
1559         Bool is_fp = FALSE;
1560         Bool is_lvds = FALSE;
1561         float aspect_ratio, panel_ratio;
1562         uint32_t h_scale, v_scale;
1563
1564         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1565
1566         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1567         NVOutputPrivatePtr nv_output = output->driver_private;
1568
1569         if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS)) {
1570                 is_fp = TRUE;
1571
1572                 if (nv_output->type == OUTPUT_LVDS)
1573                         is_lvds = TRUE;
1574
1575                 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
1576                 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
1577                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HDisplay;
1578                 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
1579                 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
1580                 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
1581                 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
1582
1583                 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
1584                 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
1585                 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VDisplay;
1586                 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
1587                 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
1588                 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
1589                 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
1590
1591                 ErrorF("Horizontal:\n");
1592                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
1593                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
1594                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
1595                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
1596                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
1597                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
1598                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
1599
1600                 ErrorF("Vertical:\n");
1601                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
1602                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
1603                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
1604                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
1605                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
1606                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
1607                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
1608         }
1609
1610         /*
1611         * bit0: positive vsync
1612         * bit4: positive hsync
1613         * bit8: enable panel scaling
1614         * bit26: a bit sometimes seen on some g70 cards
1615         * bit31: sometimes seen on LVDS panels
1616         * This must also be set for non-flatpanels
1617         * Some bits seem shifted for vga monitors
1618         */
1619
1620         if (is_fp) {
1621                 regp->fp_control = 0x11100000;
1622         } else {
1623                 regp->fp_control = 0x21100000;
1624         }
1625         if (nv_output->type == OUTPUT_LVDS) {
1626                 /* Let's assume LVDS to be on ramdac0, remember that in the ramdac routing is somewhat random (compared to bios setup), so don't trust it */
1627                 regp->fp_control = nvReadRAMDAC0(pNv, NV_RAMDAC_FP_CONTROL) & 0xfff00000;
1628         } else {
1629                 /* If the special bit exists, it exists on both ramdac's */
1630                 regp->fp_control |= nvReadRAMDAC0(pNv, NV_RAMDAC_FP_CONTROL) & (1 << 26);
1631         }
1632
1633         /* Deal with vsync/hsync polarity */
1634         /* These analog monitor offsets are guesswork */
1635         if (adjusted_mode->Flags & V_PVSYNC) {
1636                 regp->fp_control |= (1 << (0 + !is_fp));
1637         }
1638
1639         if (adjusted_mode->Flags & V_PHSYNC) {
1640                 regp->fp_control |= (1 << (4 + !is_fp));
1641         }
1642
1643         if (is_fp) {
1644                 ErrorF("Pre-panel scaling\n");
1645                 ErrorF("panel-size:%dx%d\n", nv_output->fpWidth, nv_output->fpHeight);
1646                 panel_ratio = (nv_output->fpWidth)/(float)(nv_output->fpHeight);
1647                 ErrorF("panel_ratio=%f\n", panel_ratio);
1648                 aspect_ratio = (mode->HDisplay)/(float)(mode->VDisplay);
1649                 ErrorF("aspect_ratio=%f\n", aspect_ratio);
1650                 /* Scale factors is the so called 20.12 format, taken from Haiku */
1651                 h_scale = ((1 << 12) * mode->HDisplay)/nv_output->fpWidth;
1652                 v_scale = ((1 << 12) * mode->VDisplay)/nv_output->fpHeight;
1653                 ErrorF("h_scale=%d\n", h_scale);
1654                 ErrorF("v_scale=%d\n", v_scale);
1655
1656                 /* Don't limit last fetched line */
1657                 regp->debug_2 = 0;
1658
1659                 /* We want automatic scaling */
1660                 regp->debug_1 = 0;
1661
1662                 regp->fp_hvalid_start = 0;
1663                 regp->fp_hvalid_end = (nv_output->fpWidth - 1);
1664
1665                 regp->fp_vvalid_start = 0;
1666                 regp->fp_vvalid_end = (nv_output->fpHeight - 1);
1667
1668                 if (!pNv->fpScaler) {
1669                         ErrorF("Flat panel is doing the scaling.\n");
1670                         regp->fp_control |= (1 << 8);
1671                 } else {
1672                         ErrorF("GPU is doing the scaling.\n");
1673                         /* GPU scaling happens automaticly at a ratio of 1.33 */
1674                         /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
1675                         if (h_scale != (1 << 12) && (panel_ratio > (aspect_ratio + 0.10))) {
1676                                 uint32_t diff;
1677
1678                                 ErrorF("Scaling resolution on a widescreen panel\n");
1679
1680                                 /* Scaling in both directions needs to the same */
1681                                 h_scale = v_scale;
1682
1683                                 /* Set a new horizontal scale factor and enable testmode (bit12) */
1684                                 regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
1685
1686                                 diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
1687                                 regp->fp_hvalid_start = diff/2;
1688                                 regp->fp_hvalid_end = nv_output->fpWidth - (diff/2) - 1;
1689                         }
1690
1691                         /* Same scaling, just for panels with aspect ratio's smaller than 1 */
1692                         if (v_scale != (1 << 12) && (panel_ratio < (aspect_ratio - 0.10))) {
1693                                 uint32_t diff;
1694
1695                                 ErrorF("Scaling resolution on a portrait panel\n");
1696
1697                                 /* Scaling in both directions needs to the same */
1698                                 v_scale = h_scale;
1699
1700                                 /* Set a new vertical scale factor and enable testmode (bit28) */
1701                                 regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
1702
1703                                 diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
1704                                 regp->fp_vvalid_start = diff/2;
1705                                 regp->fp_vvalid_end = nv_output->fpHeight - (diff/2) - 1;
1706                         }
1707                 }
1708
1709                 ErrorF("Post-panel scaling\n");
1710         }
1711
1712         if (pNv->Architecture >= NV_ARCH_10) {
1713                 /* Bios and blob don't seem to do anything (else) */
1714                 regp->nv10_cursync = (1<<25);
1715         }
1716
1717         /* These are the common blob values, minus a few fp specific bit's */
1718         /* Let's keep the TMDS pll and fpclock running in all situations */
1719         regp->debug_0 = 0x1101111;
1720
1721         if(is_fp) {
1722                 /* I am not completely certain, but seems to be set only for dfp's */
1723                 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED;
1724         }
1725
1726         ErrorF("output %d debug_0 %08X\n", nv_output->ramdac, regp->debug_0);
1727
1728         /* Flatpanel support needs at least a NV10 */
1729         if(pNv->twoHeads) {
1730                 /* Instead of 1, several other values are also used: 2, 7, 9 */
1731                 /* The purpose is unknown */
1732                 if(pNv->FPDither) {
1733                         regp->dither = 0x00010000;
1734                 }
1735         }
1736
1737         /* Kindly borrowed from haiku driver */
1738         /* bit4 and bit5 activate indirect mode trough color palette */
1739         switch (pLayout->depth) {
1740                 case 32:
1741                 case 16:
1742                         regp->general = 0x00101130;
1743                         break;
1744                 case 24:
1745                 case 15:
1746                         regp->general = 0x00100130;
1747                         break;
1748                 case 8:
1749                 default:
1750                         regp->general = 0x00101100;
1751                         break;
1752         }
1753
1754         if (pNv->alphaCursor) {
1755                 regp->general |= (1<<29);
1756         }
1757
1758         /* Some values the blob sets */
1759         /* This may apply to the real ramdac that is being used (for crosswired situations) */
1760         /* Nevertheless, it's unlikely to cause many problems, since the values are equal for both */
1761         regp->unk_a20 = 0x0;
1762         regp->unk_a24 = 0xfffff;
1763         regp->unk_a34 = 0x1;
1764 }
1765
1766 /**
1767  * Sets up registers for the given mode/adjusted_mode pair.
1768  *
1769  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1770  *
1771  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1772  * be easily turned on/off after this.
1773  */
1774 static void
1775 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
1776                  DisplayModePtr adjusted_mode,
1777                  int x, int y)
1778 {
1779         ScrnInfoPtr pScrn = crtc->scrn;
1780         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1781         NVPtr pNv = NVPTR(pScrn);
1782
1783         ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->crtc);
1784
1785         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->crtc);
1786         xf86PrintModeline(pScrn->scrnIndex, mode);
1787         NVCrtcSetOwner(crtc);
1788
1789         nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
1790         nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
1791         nv_crtc_mode_set_ramdac_regs(crtc, mode, adjusted_mode);
1792
1793         /* Just in case */
1794         NVCrtcLockUnlock(crtc, FALSE);
1795
1796         NVVgaProtect(crtc, TRUE);
1797         nv_crtc_load_state_ext(crtc, &pNv->ModeReg);
1798         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
1799         if (pNv->Architecture == NV_ARCH_40) {
1800                 nv40_crtc_load_state_pll(pNv, &pNv->ModeReg);
1801         } else {
1802                 nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
1803         }
1804         nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
1805
1806         NVVgaProtect(crtc, FALSE);
1807
1808         NVCrtcSetBase(crtc, x, y);
1809
1810 #if X_BYTE_ORDER == X_BIG_ENDIAN
1811         /* turn on LFB swapping */
1812         {
1813                 unsigned char tmp;
1814
1815                 tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
1816                 tmp |= (1 << 7);
1817                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
1818         }
1819 #endif
1820 }
1821
1822 void nv_crtc_save(xf86CrtcPtr crtc)
1823 {
1824         ScrnInfoPtr pScrn = crtc->scrn;
1825         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1826         NVPtr pNv = NVPTR(pScrn);
1827
1828         ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->crtc);
1829
1830         /* We just came back from terminal, so unlock */
1831         NVCrtcLockUnlock(crtc, FALSE);
1832
1833         NVCrtcSetOwner(crtc);
1834         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
1835         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
1836         if (pNv->Architecture == NV_ARCH_40) {
1837                 nv40_crtc_save_state_pll(pNv, &pNv->SavedReg);
1838         } else {
1839                 nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
1840         }
1841         nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
1842 }
1843
1844 void nv_crtc_restore(xf86CrtcPtr crtc)
1845 {
1846         ScrnInfoPtr pScrn = crtc->scrn;
1847         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1848         NVPtr pNv = NVPTR(pScrn);
1849
1850         ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->crtc);
1851
1852         NVCrtcSetOwner(crtc);
1853
1854         /* Just to be safe */
1855         NVCrtcLockUnlock(crtc, FALSE);
1856
1857         NVVgaProtect(crtc, TRUE);
1858         nv_crtc_load_state_ext(crtc, &pNv->SavedReg);
1859         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
1860         if (pNv->Architecture == NV_ARCH_40) {
1861                 nv40_crtc_load_state_pll(pNv, &pNv->SavedReg);
1862         } else {
1863                 nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
1864         }
1865         nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
1866         nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->vtOWNER);
1867         NVVgaProtect(crtc, FALSE);
1868
1869         /* We must lock the door if we leave ;-) */
1870         NVCrtcLockUnlock(crtc, TRUE);
1871 }
1872
1873 void nv_crtc_prepare(xf86CrtcPtr crtc)
1874 {
1875         ScrnInfoPtr pScrn = crtc->scrn;
1876         NVPtr pNv = NVPTR(pScrn);
1877         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1878
1879         ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->crtc);
1880
1881         crtc->funcs->dpms(crtc, DPMSModeOff);
1882
1883         /* Sync the engine before adjust mode */
1884         if (pNv->EXADriverPtr) {
1885                 exaMarkSync(pScrn->pScreen);
1886                 exaWaitSync(pScrn->pScreen);
1887         }
1888 }
1889
1890 void nv_crtc_commit(xf86CrtcPtr crtc)
1891 {
1892         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1893         ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->crtc);
1894
1895         crtc->funcs->dpms (crtc, DPMSModeOn);
1896         if (crtc->scrn->pScreen != NULL)
1897                 xf86_reload_cursors (crtc->scrn->pScreen);
1898 }
1899
1900 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
1901 {
1902         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1903         ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->crtc);
1904
1905         return FALSE;
1906 }
1907
1908 static void nv_crtc_unlock(xf86CrtcPtr crtc)
1909 {
1910         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1911         ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->crtc);
1912 }
1913
1914 static void
1915 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
1916                                         int size)
1917 {
1918         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1919         ScrnInfoPtr pScrn = crtc->scrn;
1920         NVPtr pNv = NVPTR(pScrn);
1921         int i, j;
1922
1923         NVCrtcRegPtr regp;
1924         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1925
1926         switch (pNv->CurrentLayout.depth) {
1927         case 15:
1928                 /* R5G5B5 */
1929                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
1930                 for (i = 0; i < 32; i++) {
1931                         for (j = 0; j < 8; j++) {
1932                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1933                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
1934                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1935                         }
1936                 }
1937                 break;
1938         case 16:
1939                 /* R5G6B5 */
1940                 /* First deal with the 5 bit colors */
1941                 for (i = 0; i < 32; i++) {
1942                         for (j = 0; j < 8; j++) {
1943                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1944                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1945                         }
1946                 }
1947                 /* Now deal with the 6 bit color */
1948                 for (i = 0; i < 64; i++) {
1949                         for (j = 0; j < 4; j++) {
1950                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
1951                         }
1952                 }
1953                 break;
1954         default:
1955                 /* R8G8B8 */
1956                 for (i = 0; i < 256; i++) {
1957                         regp->DAC[i * 3] = red[i] >> 8;
1958                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
1959                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
1960                 }
1961                 break;
1962         }
1963
1964         NVCrtcLoadPalette(crtc);
1965 }
1966
1967 /* NV04-NV10 doesn't support alpha cursors */
1968 static const xf86CrtcFuncsRec nv_crtc_funcs = {
1969         .dpms = nv_crtc_dpms,
1970         .save = nv_crtc_save, /* XXX */
1971         .restore = nv_crtc_restore, /* XXX */
1972         .mode_fixup = nv_crtc_mode_fixup,
1973         .mode_set = nv_crtc_mode_set,
1974         .prepare = nv_crtc_prepare,
1975         .commit = nv_crtc_commit,
1976         .destroy = NULL, /* XXX */
1977         .lock = nv_crtc_lock,
1978         .unlock = nv_crtc_unlock,
1979         .set_cursor_colors = nv_crtc_set_cursor_colors,
1980         .set_cursor_position = nv_crtc_set_cursor_position,
1981         .show_cursor = nv_crtc_show_cursor,
1982         .hide_cursor = nv_crtc_hide_cursor,
1983         .load_cursor_image = nv_crtc_load_cursor_image,
1984         .gamma_set = nv_crtc_gamma_set,
1985 };
1986
1987 /* NV11 and up has support for alpha cursors. */
1988 /* Due to different maximum sizes we cannot allow it to use normal cursors */
1989 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
1990         .dpms = nv_crtc_dpms,
1991         .save = nv_crtc_save, /* XXX */
1992         .restore = nv_crtc_restore, /* XXX */
1993         .mode_fixup = nv_crtc_mode_fixup,
1994         .mode_set = nv_crtc_mode_set,
1995         .prepare = nv_crtc_prepare,
1996         .commit = nv_crtc_commit,
1997         .destroy = NULL, /* XXX */
1998         .lock = nv_crtc_lock,
1999         .unlock = nv_crtc_unlock,
2000         .set_cursor_colors = NULL, /* Alpha cursors do not need this */
2001         .set_cursor_position = nv_crtc_set_cursor_position,
2002         .show_cursor = nv_crtc_show_cursor,
2003         .hide_cursor = nv_crtc_hide_cursor,
2004         .load_cursor_argb = nv_crtc_load_cursor_argb,
2005         .gamma_set = nv_crtc_gamma_set,
2006 };
2007
2008
2009 void
2010 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
2011 {
2012         NVPtr pNv = NVPTR(pScrn);
2013         xf86CrtcPtr crtc;
2014         NVCrtcPrivatePtr nv_crtc;
2015
2016         if (pNv->NVArch >= 0x11) {
2017                 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
2018         } else {
2019                 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
2020         }
2021         if (crtc == NULL)
2022                 return;
2023
2024         nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
2025         nv_crtc->crtc = crtc_num;
2026         nv_crtc->head = crtc_num;
2027
2028         crtc->driver_private = nv_crtc;
2029
2030         NVCrtcLockUnlock(crtc, FALSE);
2031 }
2032
2033 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2034 {
2035     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2036     int i;
2037     NVCrtcRegPtr regp;
2038
2039     regp = &state->crtc_reg[nv_crtc->head];
2040
2041     NVWriteMiscOut(crtc, regp->MiscOutReg);
2042
2043     for (i = 1; i < 5; i++)
2044       NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
2045
2046     /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
2047     NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
2048
2049     for (i = 0; i < 25; i++)
2050       NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
2051
2052     for (i = 0; i < 9; i++)
2053       NVWriteVgaGr(crtc, i, regp->Graphics[i]);
2054
2055     NVEnablePalette(crtc);
2056     for (i = 0; i < 21; i++)
2057       NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
2058     NVDisablePalette(crtc);
2059
2060 }
2061
2062 static void nv_crtc_fix_nv40_hw_cursor(xf86CrtcPtr crtc)
2063 {
2064   /* TODO - implement this properly */
2065   ScrnInfoPtr pScrn = crtc->scrn;
2066   NVPtr pNv = NVPTR(pScrn);
2067
2068   if(pNv->Architecture == NV_ARCH_40) {  /* HW bug */
2069     volatile CARD32 curpos = nvReadCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS);
2070     nvWriteCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS, curpos);
2071   }
2072
2073 }
2074 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2075 {
2076     ScrnInfoPtr pScrn = crtc->scrn;
2077     NVPtr pNv = NVPTR(pScrn);
2078     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2079     NVCrtcRegPtr regp;
2080
2081     regp = &state->crtc_reg[nv_crtc->head];
2082
2083     if(pNv->Architecture >= NV_ARCH_10) {
2084         if(pNv->twoHeads) {
2085            nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL, regp->head);
2086         }
2087         nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
2088         nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
2089         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
2090         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
2091         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2092         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2093         nvWriteMC(pNv, 0x1588, 0);
2094
2095         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
2096         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
2097         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO, regp->gpio);
2098         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0830, regp->unk830);
2099         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0834, regp->unk834);
2100         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0850, regp->unk850);
2101         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_081C, regp->unk81c);
2102
2103         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
2104         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
2105
2106         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
2107         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
2108         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3C, regp->CRTC[NV_VGA_CRTCX_3C]);
2109         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
2110         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
2111         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_56, regp->CRTC[NV_VGA_CRTCX_56]);
2112         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_57, regp->CRTC[NV_VGA_CRTCX_57]);
2113         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_58, regp->CRTC[NV_VGA_CRTCX_58]);
2114         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
2115         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
2116     }
2117
2118     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
2119     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
2120     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
2121     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
2122     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
2123     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
2124     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
2125     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
2126     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
2127     if(pNv->Architecture >= NV_ARCH_30) {
2128       NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
2129     }
2130
2131     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
2132     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
2133     nv_crtc_fix_nv40_hw_cursor(crtc);
2134     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
2135     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
2136
2137     nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_EN_0, 0);
2138     nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
2139
2140     pNv->CurrentState = state;
2141 }
2142
2143 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2144 {
2145     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2146     int i;
2147     NVCrtcRegPtr regp;
2148
2149     regp = &state->crtc_reg[nv_crtc->head];
2150
2151     regp->MiscOutReg = NVReadMiscOut(crtc);
2152
2153     for (i = 0; i < 25; i++)
2154         regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
2155
2156     NVEnablePalette(crtc);
2157     for (i = 0; i < 21; i++)
2158         regp->Attribute[i] = NVReadVgaAttr(crtc, i);
2159     NVDisablePalette(crtc);
2160
2161     for (i = 0; i < 9; i++)
2162         regp->Graphics[i] = NVReadVgaGr(crtc, i);
2163
2164     for (i = 1; i < 5; i++)
2165         regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
2166
2167 }
2168
2169 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2170 {
2171     ScrnInfoPtr pScrn = crtc->scrn;
2172     NVPtr pNv = NVPTR(pScrn);
2173     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2174     NVCrtcRegPtr regp;
2175
2176     regp = &state->crtc_reg[nv_crtc->head];
2177
2178     regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
2179     regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
2180     regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
2181     regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
2182     regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
2183     regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
2184     regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
2185
2186     regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
2187     regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
2188     if(pNv->Architecture >= NV_ARCH_30) {
2189          regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
2190     }
2191     regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
2192     regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
2193     regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
2194     regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
2195
2196     regp->gpio = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO);
2197     regp->unk830 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0830);
2198     regp->unk834 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0834);
2199     regp->unk850 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0850);
2200     regp->unk81c = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_081C);
2201
2202     if(pNv->Architecture >= NV_ARCH_10) {
2203         if(pNv->twoHeads) {
2204            regp->head     = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL);
2205            regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
2206         }
2207         regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
2208
2209         regp->cursorConfig = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG);
2210
2211         regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
2212         regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
2213         regp->CRTC[NV_VGA_CRTCX_3C] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3C);
2214         regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
2215         regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
2216         regp->CRTC[NV_VGA_CRTCX_56] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_56);
2217         regp->CRTC[NV_VGA_CRTCX_57] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_57);
2218         regp->CRTC[NV_VGA_CRTCX_58] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_58);
2219         regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
2220         regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
2221         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
2222         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
2223     }
2224 }
2225
2226 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2227 {
2228         ScrnInfoPtr pScrn = crtc->scrn;
2229         NVPtr pNv = NVPTR(pScrn);
2230         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2231         NVCrtcRegPtr regp;
2232         int i;
2233
2234         regp = &state->crtc_reg[nv_crtc->head];
2235
2236         regp->general = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL);
2237
2238         regp->fp_control        = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL);
2239         regp->debug_0   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0);
2240         regp->debug_1   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1);
2241         regp->debug_2   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2);
2242
2243         regp->unk_a20 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20);
2244         regp->unk_a24 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24);
2245         regp->unk_a34 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34);
2246
2247         if (pNv->NVArch == 0x11) {
2248                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11);
2249         } else if (pNv->twoHeads) {
2250                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER);
2251         }
2252         regp->nv10_cursync = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC);
2253
2254         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2255
2256         for (i = 0; i < 7; i++) {
2257                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2258                 regp->fp_horiz_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2259         }
2260
2261         for (i = 0; i < 7; i++) {
2262                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2263                 regp->fp_vert_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2264         }
2265
2266         regp->fp_hvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START);
2267         regp->fp_hvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END);
2268         regp->fp_vvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START);
2269         regp->fp_vvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END);
2270 }
2271
2272 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2273 {
2274         ScrnInfoPtr pScrn = crtc->scrn;
2275         NVPtr pNv = NVPTR(pScrn);
2276         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2277         NVCrtcRegPtr regp;
2278         int i;
2279
2280         regp = &state->crtc_reg[nv_crtc->head];
2281
2282         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL, regp->general);
2283
2284         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control);
2285         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0, regp->debug_0);
2286         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
2287         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
2288
2289         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20, regp->unk_a20);
2290         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24, regp->unk_a24);
2291         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34, regp->unk_a34);
2292
2293         if (pNv->NVArch == 0x11) {
2294                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11, regp->dither);
2295         } else if (pNv->twoHeads) {
2296                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER, regp->dither);
2297         }
2298         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
2299
2300         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2301
2302         for (i = 0; i < 7; i++) {
2303                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2304                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_horiz_regs[i]);
2305         }
2306
2307         for (i = 0; i < 7; i++) {
2308                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2309                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_vert_regs[i]);
2310         }
2311
2312         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START, regp->fp_hvalid_start);
2313         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END, regp->fp_hvalid_end);
2314         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START, regp->fp_vvalid_start);
2315         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END, regp->fp_vvalid_end);
2316 }
2317
2318 void
2319 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y)
2320 {
2321         ScrnInfoPtr pScrn = crtc->scrn;
2322         NVPtr pNv = NVPTR(pScrn);
2323         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2324         NVFBLayout *pLayout = &pNv->CurrentLayout;
2325         CARD32 start = 0;
2326
2327         ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
2328
2329         start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
2330         start += pNv->FB->offset;
2331
2332         /* 30 bits addresses in 32 bits according to haiku */
2333         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_START, start & 0xfffffffc);
2334
2335         /* set NV4/NV10 byte adress: (bit0 - 1) */
2336         NVWriteVgaAttr(crtc, 0x13, (start & 0x3) << 1);
2337
2338         crtc->x = x;
2339         crtc->y = y;
2340 }
2341
2342 static void NVCrtcWriteDacMask(xf86CrtcPtr crtc, CARD8 value)
2343 {
2344   ScrnInfoPtr pScrn = crtc->scrn;
2345   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2346   NVPtr pNv = NVPTR(pScrn);
2347   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2348
2349   NV_WR08(pDACReg, VGA_DAC_MASK, value);
2350 }
2351
2352 static CARD8 NVCrtcReadDacMask(xf86CrtcPtr crtc)
2353 {
2354   ScrnInfoPtr pScrn = crtc->scrn;
2355   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2356   NVPtr pNv = NVPTR(pScrn);
2357   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2358
2359   return NV_RD08(pDACReg, VGA_DAC_MASK);
2360 }
2361
2362 static void NVCrtcWriteDacReadAddr(xf86CrtcPtr crtc, CARD8 value)
2363 {
2364   ScrnInfoPtr pScrn = crtc->scrn;
2365   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2366   NVPtr pNv = NVPTR(pScrn);
2367   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2368
2369   NV_WR08(pDACReg, VGA_DAC_READ_ADDR, value);
2370 }
2371
2372 static void NVCrtcWriteDacWriteAddr(xf86CrtcPtr crtc, CARD8 value)
2373 {
2374   ScrnInfoPtr pScrn = crtc->scrn;
2375   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2376   NVPtr pNv = NVPTR(pScrn);
2377   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2378
2379   NV_WR08(pDACReg, VGA_DAC_WRITE_ADDR, value);
2380 }
2381
2382 static void NVCrtcWriteDacData(xf86CrtcPtr crtc, CARD8 value)
2383 {
2384   ScrnInfoPtr pScrn = crtc->scrn;
2385   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2386   NVPtr pNv = NVPTR(pScrn);
2387   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2388
2389   NV_WR08(pDACReg, VGA_DAC_DATA, value);
2390 }
2391
2392 static CARD8 NVCrtcReadDacData(xf86CrtcPtr crtc, CARD8 value)
2393 {
2394   ScrnInfoPtr pScrn = crtc->scrn;
2395   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2396   NVPtr pNv = NVPTR(pScrn);
2397   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2398
2399   return NV_RD08(pDACReg, VGA_DAC_DATA);
2400 }
2401
2402 void NVCrtcLoadPalette(xf86CrtcPtr crtc)
2403 {
2404         int i;
2405         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2406         NVCrtcRegPtr regp;
2407         ScrnInfoPtr pScrn = crtc->scrn;
2408         NVPtr pNv = NVPTR(pScrn);
2409
2410         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2411
2412         NVCrtcSetOwner(crtc);
2413         NVCrtcWriteDacMask(crtc, 0xff);
2414         NVCrtcWriteDacWriteAddr(crtc, 0x00);
2415
2416         for (i = 0; i<768; i++) {
2417                 NVCrtcWriteDacData(crtc, regp->DAC[i]);
2418         }
2419         NVDisablePalette(crtc);
2420 }
2421
2422 void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
2423 {
2424         unsigned char scrn;
2425
2426         NVCrtcSetOwner(crtc);
2427
2428         scrn = NVReadVgaSeq(crtc, 0x01);
2429         if (on) {
2430                 scrn &= ~0x20;
2431         } else {
2432                 scrn |= 0x20;
2433         }
2434
2435         NVVgaSeqReset(crtc, TRUE);
2436         NVWriteVgaSeq(crtc, 0x01, scrn);
2437         NVVgaSeqReset(crtc, FALSE);
2438 }
2439
2440 /*************************************************************************** \
2441 |*                                                                           *|
2442 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
2443 |*                                                                           *|
2444 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
2445 |*     international laws.  Users and possessors of this source code are     *|
2446 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
2447 |*     use this code in individual and commercial software.                  *|
2448 |*                                                                           *|
2449 |*     Any use of this source code must include,  in the user documenta-     *|
2450 |*     tion and  internal comments to the code,  notices to the end user     *|
2451 |*     as follows:                                                           *|
2452 |*                                                                           *|
2453 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
2454 |*                                                                           *|
2455 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
2456 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
2457 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
2458 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
2459 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
2460 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
2461 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
2462 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
2463 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
2464 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
2465 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
2466 |*                                                                           *|
2467 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
2468 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
2469 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
2470 |*     computer  software  documentation,"  as such  terms  are  used in     *|
2471 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
2472 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
2473 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
2474 |*     all U.S. Government End Users  acquire the source code  with only     *|
2475 |*     those rights set forth herein.                                        *|
2476 |*                                                                           *|
2477  \***************************************************************************/