2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2008 Stuart Bennett
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 #include "nv_include.h"
29 /* FIXME: put these somewhere */
30 #define CRTC_INDEX_COLOR (VGA_IOBASE_COLOR + VGA_CRTC_INDEX_OFFSET)
31 #define NV_VGA_CRTCX_OWNER_HEADA 0x0
32 #define NV_VGA_CRTCX_OWNER_HEADB 0x3
33 #define NV_PBUS_PCI_NV_19 0x0000184C
34 #define NV_PBUS_PCI_NV_20 0x00001850
35 #define NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED 0x00000000
36 #define NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED 0x00000001
37 #define NV_PEXTDEV_BOOT_0 0x00101000
38 /* undef, as we want the +0x00100000 version */
40 #define NV_PFB_CFG0 0x00100200
41 #define NV_PFB_REFCTRL 0x00100210
42 #define NV_PFB_REFCTRL_VALID_1 0x80000000
43 #define NV_PRAMIN_ROM_OFFSET 0x00700000
51 static int crtchead = 0;
53 /* this will need remembering across a suspend */
54 static uint32_t saved_nv_pfb_cfg0;
61 static uint16_t le16_to_cpu(const uint16_t x)
63 #if X_BYTE_ORDER == X_BIG_ENDIAN
70 static uint32_t le32_to_cpu(const uint32_t x)
72 #if X_BYTE_ORDER == X_BIG_ENDIAN
79 static Bool nv_cksum(const uint8_t *data, unsigned int length)
81 /* there's a few checksums in the BIOS, so here's a generic checking function */
85 for (i = 0; i < length; i++)
94 static int NVValidVBIOS(ScrnInfoPtr pScrn, const uint8_t *data)
96 /* check for BIOS signature */
97 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
98 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
99 "... BIOS signature not found\n");
103 if (nv_cksum(data, data[2] * 512)) {
104 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
105 "... BIOS checksum invalid\n");
106 /* probably ought to set a do_not_execute flag for table parsing here,
107 * assuming most BIOSen are valid */
110 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "... appears to be valid\n");
115 static void NVShadowVBIOS_PROM(ScrnInfoPtr pScrn, uint8_t *data)
117 NVPtr pNv = NVPTR(pScrn);
120 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
121 "Attempting to locate BIOS image in PROM\n");
123 /* enable ROM access */
124 nvWriteMC(pNv, NV_PBUS_PCI_NV_20, NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED);
125 for (i = 0; i < NV_PROM_SIZE; i++) {
126 /* according to nvclock, we need that to work around a 6600GT/6800LE bug */
127 data[i] = pNv->PROM[i];
128 data[i] = pNv->PROM[i];
129 data[i] = pNv->PROM[i];
130 data[i] = pNv->PROM[i];
131 data[i] = pNv->PROM[i];
133 /* disable ROM access */
134 nvWriteMC(pNv, NV_PBUS_PCI_NV_20, NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
137 static void NVShadowVBIOS_PRAMIN(ScrnInfoPtr pScrn, uint32_t *data)
139 NVPtr pNv = NVPTR(pScrn);
140 const uint32_t *pramin = (uint32_t *)&pNv->REGS[NV_PRAMIN_ROM_OFFSET/4];
141 uint32_t old_bar0_pramin = 0;
143 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
144 "Attempting to locate BIOS image in PRAMIN\n");
146 if (pNv->Architecture >= NV_ARCH_50) {
149 vbios_vram = (pNv->REGS[0x619f04/4] & ~0xff) << 8;
151 vbios_vram = pNv->REGS[0x1700/4] << 16;
152 vbios_vram += 0xf0000;
155 old_bar0_pramin = pNv->REGS[0x1700/4];
156 pNv->REGS[0x1700/4] = vbios_vram >> 16;
159 memcpy(data, pramin, NV_PROM_SIZE);
161 if (pNv->Architecture >= NV_ARCH_50) {
162 pNv->REGS[0x1700/4] = old_bar0_pramin;
166 static void NVVBIOS_PCIROM(ScrnInfoPtr pScrn, uint8_t *data)
168 NVPtr pNv = NVPTR(pScrn);
170 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
171 "Attempting to use PCI ROM BIOS image\n");
173 #if XSERVER_LIBPCIACCESS
174 pci_device_read_rom(pNv->PciInfo, data);
176 xf86ReadPciBIOS(0, pNv->PciTag, 0, data, NV_PROM_SIZE);
180 static Bool NVShadowVBIOS(ScrnInfoPtr pScrn, uint8_t *data)
182 NVShadowVBIOS_PROM(pScrn, data);
183 if (NVValidVBIOS(pScrn, data) == 2)
186 NVShadowVBIOS_PRAMIN(pScrn, (uint32_t *)data);
187 if (NVValidVBIOS(pScrn, data))
191 NVVBIOS_PCIROM(pScrn, data);
192 if (NVValidVBIOS(pScrn, data))
204 int length_multiplier;
205 Bool (*handler)(ScrnInfoPtr pScrn, bios_t *, uint16_t, init_exec_t *);
214 static void parse_init_table(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset, init_exec_t *iexec);
216 #define MACRO_INDEX_SIZE 2
218 #define CONDITION_SIZE 12
219 #define IO_FLAG_CONDITION_SIZE 9
227 static int nv_valid_reg(NVPtr pNv, uint32_t reg)
229 /* C51 has misaligned regs on purpose. Marvellous */
230 if ((reg & 0x3 && pNv->VBIOS.chip_version != 0x51) ||
231 (reg & 0x2 && pNv->VBIOS.chip_version == 0x51)) {
232 ErrorF("========== misaligned reg 0x%08X ==========\n", reg);
236 #define WITHIN(x,y,z) ((x>=y)&&(x<y+z))
237 if (WITHIN(reg,NV_PRAMIN_OFFSET,NV_PRAMIN_SIZE))
239 if (WITHIN(reg,NV_PCRTC0_OFFSET,NV_PCRTC0_SIZE))
241 if (WITHIN(reg,NV_PRAMDAC0_OFFSET,NV_PRAMDAC0_SIZE))
243 if (WITHIN(reg,NV_PFB_OFFSET,NV_PFB_SIZE))
245 if (WITHIN(reg,NV_PFIFO_OFFSET,NV_PFIFO_SIZE))
247 if (WITHIN(reg,NV_PGRAPH_OFFSET,NV_PGRAPH_SIZE))
249 if (WITHIN(reg,NV_PEXTDEV_OFFSET,NV_PEXTDEV_SIZE))
251 if (WITHIN(reg,NV_PTIMER_OFFSET,NV_PTIMER_SIZE))
253 if (WITHIN(reg,NV_PVIDEO_OFFSET,NV_PVIDEO_SIZE))
255 if (WITHIN(reg,NV_PMC_OFFSET,NV_PMC_SIZE))
257 if (WITHIN(reg,NV_FIFO_OFFSET,NV_FIFO_SIZE))
259 if (WITHIN(reg,NV_PCIO0_OFFSET,NV_PCIO0_SIZE))
261 if (WITHIN(reg,NV_PDIO0_OFFSET,NV_PDIO0_SIZE))
263 if (WITHIN(reg,NV_PVIO_OFFSET,NV_PVIO_SIZE))
265 if (WITHIN(reg,NV_PROM_OFFSET,NV_PROM_SIZE))
267 if (WITHIN(reg,NV_PRAMIN_ROM_OFFSET,NV_PROM_SIZE))
270 if (WITHIN(reg,0x88000,0x1000))
274 ErrorF("========== unknown reg 0x%08X ==========\n", reg);
279 static uint32_t nv32_rd(ScrnInfoPtr pScrn, uint32_t reg)
281 NVPtr pNv = NVPTR(pScrn);
284 if (!nv_valid_reg(pNv, reg))
287 /* C51 sometimes uses regs with bit0 set in the address. For these
288 * cases there should exist a translation in a BIOS table to an IO
289 * port address which the BIOS uses for accessing the reg
291 * These only seem to appear for the power control regs to a flat panel
292 * and in C51 mmio traces the normal regs for 0x1308 and 0x1310 are
293 * used - hence the mask below. An S3 suspend-resume mmio trace from a
294 * C51 will be required to see if this is true for the power microcode
295 * in 0x14.., or whether the direct IO port access method is needed
300 data = pNv->REGS[reg/4];
303 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
304 " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
309 static int nv32_wr(ScrnInfoPtr pScrn, uint32_t reg, uint32_t data)
311 NVPtr pNv = NVPTR(pScrn);
313 if (!nv_valid_reg(pNv, reg))
316 /* see note in nv32_rd */
323 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
324 " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
326 if (pNv->VBIOS.execute) {
328 pNv->REGS[reg/4] = data;
334 static uint8_t nv_idx_port_rd(ScrnInfoPtr pScrn, uint16_t port, uint8_t index)
336 NVPtr pNv = NVPTR(pScrn);
337 volatile uint8_t *ptr = crtchead ? pNv->PCIO1 : pNv->PCIO0;
340 VGA_WR08(ptr, port, index);
341 data = VGA_RD08(ptr, port + 1);
344 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
345 " Indexed read: Port: 0x%04X, Index: 0x%02X, Head: 0x%02X, Data: 0x%02X\n",
346 port, index, crtchead, data);
351 static void nv_idx_port_wr(ScrnInfoPtr pScrn, uint16_t port, uint8_t index, uint8_t data)
353 NVPtr pNv = NVPTR(pScrn);
354 volatile uint8_t *ptr;
356 /* The current head is maintained in a file scope variable crtchead.
357 * We trap changes to CRTCX_OWNER and update the head variable
358 * and hence the register set written.
359 * As CRTCX_OWNER only exists on CRTC0, we update crtchead to head0
360 * in advance of the write, and to head1 after the write
362 if (port == CRTC_INDEX_COLOR && index == NV_VGA_CRTCX_OWNER && data != NV_VGA_CRTCX_OWNER_HEADB)
364 ptr = crtchead ? pNv->PCIO1 : pNv->PCIO0;
367 nv_idx_port_rd(pScrn, port, index);
369 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
370 " Indexed write: Port: 0x%04X, Index: 0x%02X, Head: 0x%02X, Data: 0x%02X\n",
371 port, index, crtchead, data);
373 if (pNv->VBIOS.execute) {
375 VGA_WR08(ptr, port, index);
376 VGA_WR08(ptr, port + 1, data);
379 if (port == CRTC_INDEX_COLOR && index == NV_VGA_CRTCX_OWNER && data == NV_VGA_CRTCX_OWNER_HEADB)
383 #define ACCESS_UNLOCK 0
384 #define ACCESS_LOCK 1
385 static void crtc_access(ScrnInfoPtr pScrn, Bool lock)
387 NVPtr pNv = NVPTR(pScrn);
388 int savedhead = crtchead;
391 /* necessary external dependancy (twoHeads) */
393 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_OWNER, NV_VGA_CRTCX_OWNER_HEADA);
394 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_LOCK, lock ? 0x99 : 0x57);
395 cr11 = nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_VSYNCE);
396 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_VSYNCE, lock ? cr11 | 0x80 : cr11 & ~0x80);
399 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_OWNER, NV_VGA_CRTCX_OWNER_HEADB);
400 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_LOCK, lock ? 0x99 : 0x57);
401 cr11 = nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_VSYNCE);
402 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_VSYNCE, lock ? cr11 | 0x80 : cr11 & ~0x80);
405 crtchead = savedhead;
408 static Bool io_flag_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, uint8_t cond)
410 /* The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
411 * for the CRTC index; 1 byte for the mask to apply to the value
412 * retrieved from the CRTC; 1 byte for the shift right to apply to the
413 * masked CRTC value; 2 bytes for the offset to the flag array, to
414 * which the shifted value is added; 1 byte for the mask applied to the
415 * value read from the flag array; and 1 byte for the value to compare
416 * against the masked byte from the flag table.
419 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
420 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[condptr])));
421 uint8_t crtcindex = bios->data[condptr + 2];
422 uint8_t mask = bios->data[condptr + 3];
423 uint8_t shift = bios->data[condptr + 4];
424 uint16_t flagarray = le16_to_cpu(*((uint16_t *)(&bios->data[condptr + 5])));
425 uint8_t flagarraymask = bios->data[condptr + 7];
426 uint8_t cmpval = bios->data[condptr + 8];
430 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
431 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, Cmpval: 0x%02X\n",
432 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
434 data = nv_idx_port_rd(pScrn, crtcport, crtcindex);
436 data = bios->data[flagarray + ((data & mask) >> shift)];
437 data &= flagarraymask;
440 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
441 "0x%04X: Checking if 0x%02X equals 0x%02X\n",
442 offset, data, cmpval);
450 Bool get_pll_limits(ScrnInfoPtr pScrn, uint32_t reg, struct pll_lims *pll_lim);
452 int getMNP_single(ScrnInfoPtr pScrn, uint32_t reg, int clk, int *bestNM, int *bestlog2P)
454 /* Find M, N and P for a single stage PLL
456 * Note that some bioses (NV3x) have lookup tables of precomputed MNP
457 * values, but we're too lazy to use those atm
459 * "clk" parameter in kHz
460 * returns calculated clock
463 bios_t *bios = &NVPTR(pScrn)->VBIOS;
464 struct pll_lims pll_lim;
466 /* high regs (such as in the mac g5 table) are not -= 4 */
469 if (!get_pll_limits(pScrn, reg - 4, &pll_lim))
472 int minvco = pll_lim.vco1.minfreq, maxvco = pll_lim.vco1.maxfreq;
473 int minM = pll_lim.vco1.min_m, maxM = pll_lim.vco1.max_m;
474 int minN = pll_lim.vco1.min_n, maxN = pll_lim.vco1.max_n;
475 int minU = pll_lim.vco1.min_inputfreq, maxU = pll_lim.vco1.max_inputfreq;
477 int crystal = pll_lim.refclk;
480 int delta, bestdelta = INT_MAX;
483 /* this division verified for nv20, nv28 (Haiku), nv34 -- nv17 is guessed */
484 /* possibly correlated with introduction of 27MHz crystal */
485 if (bios->chip_version <= 0x16 || bios->chip_version == 0x20) {
491 } else if (bios->chip_version < 0x40) {
499 } else /* nv4x may be subject to the nv17+ limits, but assume not for now */
502 if ((clk << maxlog2P) < minvco) {
503 minvco = clk << maxlog2P;
506 if (clk + clk/200 > maxvco) /* +0.5% */
507 maxvco = clk + clk/200;
509 /* NV34 goes maxlog2P->0, NV20 goes 0->maxlog2P */
510 for (log2P = 0; log2P <= maxlog2P; log2P++) {
519 for (M = minM; M <= maxM; M++) {
520 if (crystal/M < minU)
522 if (crystal/M > maxU)
525 /* add crystal/2 to round better */
526 N = (clkP * M + crystal/2) / crystal;
533 /* more rounding additions */
534 calcclk = ((N * crystal + P/2) / P + M/2) / M;
535 delta = abs(calcclk - clk);
536 /* we do an exhaustive search rather than terminating
537 * on an optimality condition...
539 if (delta < bestdelta) {
542 *bestNM = N << 8 | M;
544 if (delta == 0) /* except this one */
553 int getMNP_double(ScrnInfoPtr pScrn, uint32_t reg, int clk, int *bestNM1, int *bestNM2, int *bestlog2P)
555 /* Find M, N and P for a two stage PLL
557 * Note that some bioses (NV30+) have lookup tables of precomputed MNP
558 * values, but we're too lazy to use those atm
560 * "clk" parameter in kHz
561 * returns calculated clock
564 struct pll_lims pll_lim;
566 /* high regs (such as in the mac g5 table) are not -= 4 */
569 if (!get_pll_limits(pScrn, reg - 4, &pll_lim))
572 int minvco1 = pll_lim.vco1.minfreq, maxvco1 = pll_lim.vco1.maxfreq;
573 int minvco2 = pll_lim.vco2.minfreq, maxvco2 = pll_lim.vco2.maxfreq;
574 int minU1 = pll_lim.vco1.min_inputfreq, minU2 = pll_lim.vco2.min_inputfreq;
575 int maxU1 = pll_lim.vco1.max_inputfreq, maxU2 = pll_lim.vco2.max_inputfreq;
576 int minM1 = pll_lim.vco1.min_m, maxM1 = pll_lim.vco1.max_m;
577 int minN1 = pll_lim.vco1.min_n, maxN1 = pll_lim.vco1.max_n;
578 int minM2 = pll_lim.vco2.min_m, maxM2 = pll_lim.vco2.max_m;
579 int minN2 = pll_lim.vco2.min_n, maxN2 = pll_lim.vco2.max_n;
580 int crystal = pll_lim.refclk;
581 Bool fixedgain2 = (minM2 == maxM2 && minN2 == maxN2);
582 int M1, N1, M2, N2, log2P;
583 int clkP, calcclk1, calcclk2, calcclkout;
584 int delta, bestdelta = INT_MAX;
587 int vco2 = (maxvco2 - maxvco2/200) / 2;
588 for (log2P = 0; log2P < 6 && clk <= (vco2 >> log2P); log2P++) /* log2P is maximum of 6 */
592 if (maxvco2 < clk + clk/200) /* +0.5% */
593 maxvco2 = clk + clk/200;
595 for (M1 = minM1; M1 <= maxM1; M1++) {
596 if (crystal/M1 < minU1)
598 if (crystal/M1 > maxU1)
601 for (N1 = minN1; N1 <= maxN1; N1++) {
602 calcclk1 = crystal * N1 / M1;
603 if (calcclk1 < minvco1)
605 if (calcclk1 > maxvco1)
608 for (M2 = minM2; M2 <= maxM2; M2++) {
609 if (calcclk1/M2 < minU2)
611 if (calcclk1/M2 > maxU2)
614 /* add calcclk1/2 to round better */
615 N2 = (clkP * M2 + calcclk1/2) / calcclk1;
622 if (N2/M2 < 4 || N2/M2 > 10)
625 calcclk2 = calcclk1 * N2 / M2;
626 if (calcclk2 < minvco2)
628 if (calcclk2 > maxvco2)
633 calcclkout = calcclk2 >> log2P;
634 delta = abs(calcclkout - clk);
635 /* we do an exhaustive search rather than terminating
636 * on an optimality condition...
638 if (delta < bestdelta) {
640 bestclk = calcclkout;
641 *bestNM1 = N1 << 8 | M1;
642 *bestNM2 = N2 << 8 | M2;
644 if (delta == 0) /* except this one */
654 static void setPLL_single(ScrnInfoPtr pScrn, uint32_t reg, int NM, int log2P)
656 bios_t *bios = &NVPTR(pScrn)->VBIOS;
657 uint32_t oldpll = nv32_rd(pScrn, reg);
658 uint32_t pll = (oldpll & 0xfff80000) | log2P << 16 | NM;
659 uint32_t saved1584 = 0;
663 return; /* already set */
665 /* FIXME needs verification on pre nv30 */
666 if (bios->chip_version >= 0x17 && bios->chip_version != 0x20) {
678 if (shift1584 >= 0) {
679 saved1584 = nv32_rd(pScrn, 0x00001584);
680 nv32_wr(pScrn, 0x00001584, (saved1584 & ~(0xf << shift1584)) | 1 << shift1584);
685 nv32_wr(pScrn, reg, (oldpll & 0xffff0000) | NM);
691 /* then write P as well */
692 nv32_wr(pScrn, reg, pll);
695 nv32_wr(pScrn, 0x00001584, saved1584);
698 static void setPLL_double_highregs(ScrnInfoPtr pScrn, uint32_t reg1, int NM1, int NM2, int log2P)
700 bios_t *bios = &NVPTR(pScrn)->VBIOS;
701 uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70);
702 uint32_t oldpll1 = nv32_rd(pScrn, reg1), oldpll2 = nv32_rd(pScrn, reg2);
703 uint32_t pll1 = (oldpll1 & 0xfff80000) | log2P << 16 | NM1;
704 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | NM2;
705 uint32_t saved1584 = 0, savedc040 = 0, maskc040 = ~0;
708 if (oldpll1 == pll1 && oldpll2 == pll2)
709 return; /* already set */
711 if (reg1 == 0x680500) {
713 maskc040 = ~(3 << 20);
715 if (reg1 == 0x680504) {
717 maskc040 = ~(3 << 22);
719 if (shift1584 >= 0) {
720 saved1584 = nv32_rd(pScrn, 0x1584);
721 nv32_wr(pScrn, 0x1584, (saved1584 & ~(0xf << shift1584)) | 1 << shift1584);
724 if (bios->chip_version >= 0x40) {
725 savedc040 = nv32_rd(pScrn, 0xc040);
726 nv32_wr(pScrn, 0xc040, savedc040 & maskc040);
728 if (reg1 == 0x680508)
729 nv32_wr(pScrn, 0x680580, nv32_rd(pScrn, 0x680580) & ~(1 << 28));
730 if (reg1 == 0x680520)
731 nv32_wr(pScrn, 0x680580, nv32_rd(pScrn, 0x680580) & ~(1 << 8));
735 /* NM2 will not be 0, the way we calculate MNPs at present */
736 /* something like this will be needed if we set single pll modes on double pll chips */
738 if (crtchead == NV_VGA_CRTCX_OWNER_HEADA)
739 nv32_wr(0x680580, nv32_rd(0x680580) | 0x00000100);
741 nv32_wr(0x680580, nv32_rd(0x680580) | 0x10000000);
746 nv32_wr(pScrn, reg2, pll2);
747 nv32_wr(pScrn, reg1, pll1);
749 if (shift1584 >= 0) {
750 nv32_wr(pScrn, 0x1584, saved1584);
751 if (bios->chip_version >= 0x40)
752 nv32_wr(pScrn, 0xc040, savedc040);
756 static void setPLL_double_lowregs(ScrnInfoPtr pScrn, uint32_t NMNMreg, int NM1, int NM2, int log2P)
758 /* When setting PLLs, there is a merry game of disabling and enabling
759 * various bits of hardware during the process. This function is a
760 * synthesis of six nv40 traces, nearly each card doing a subtly
761 * different thing. With luck all the necessary bits for each card are
762 * combined herein. Without luck it deviates from each card's formula
763 * so as to not work on any :)
766 uint32_t Preg = NMNMreg - 4;
767 uint32_t oldPval = nv32_rd(pScrn, Preg);
768 uint32_t NMNM = NM2 << 16 | NM1;
769 uint32_t Pval = (oldPval & ((Preg == 0x4020) ? ~(0x11 << 16) : ~(1 << 16))) | 0xc << 28 | log2P << 16;
770 uint32_t saved4600 = 0;
771 /* some cards have different maskc040s */
772 uint32_t maskc040 = ~(3 << 14), savedc040;
774 if (nv32_rd(pScrn, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval)
780 maskc040 = ~(3 << 26);
782 if (Preg == 0x4020) {
783 struct pll_lims pll_lim;
786 if (!get_pll_limits(pScrn, Preg, &pll_lim))
789 Pval2 = log2P + pll_lim.log2p_bias;
790 if (Pval2 > pll_lim.max_log2p_bias)
791 Pval2 = pll_lim.max_log2p_bias;
792 Pval |= 1 << 28 | Pval2 << 20;
794 saved4600 = nv32_rd(pScrn, 0x4600);
795 nv32_wr(pScrn, 0x4600, saved4600 | 1 << 31);
798 nv32_wr(pScrn, Preg, oldPval | 1 << 28);
799 nv32_wr(pScrn, Preg, Pval & ~(1 << 30));
800 if (Preg == 0x4020) {
801 Pval |= 1 << 23 | 1 << 12;
802 nv32_wr(pScrn, 0x4020, Pval & ~(3 << 30));
803 nv32_wr(pScrn, 0x4038, Pval & ~(3 << 30));
806 savedc040 = nv32_rd(pScrn, 0xc040);
807 nv32_wr(pScrn, 0xc040, savedc040 & maskc040);
809 nv32_wr(pScrn, NMNMreg, NMNM);
810 if (NMNMreg == 0x4024)
811 nv32_wr(pScrn, 0x403c, NMNM);
813 nv32_wr(pScrn, Preg, Pval);
814 if (Preg == 0x4020) {
816 nv32_wr(pScrn, 0x4020, Pval);
817 nv32_wr(pScrn, 0x4038, Pval);
818 nv32_wr(pScrn, 0x4600, saved4600);
821 nv32_wr(pScrn, 0xc040, savedc040);
823 if (Preg == 0x4020) {
824 nv32_wr(pScrn, 0x4020, Pval & ~(1 << 28));
825 nv32_wr(pScrn, 0x4038, Pval & ~(1 << 28));
829 static void setPLL(ScrnInfoPtr pScrn, bios_t *bios, uint32_t reg, uint32_t clk)
832 int NM1 = 0xbeef, NM2 = 0xdead, log2P;
834 if (bios->chip_version >= 0x40 || bios->chip_version == 0x31 || bios->chip_version == 0x36) {
835 getMNP_double(pScrn, reg, clk, &NM1, &NM2, &log2P);
837 setPLL_double_highregs(pScrn, reg, NM1, NM2, log2P);
839 setPLL_double_lowregs(pScrn, reg, NM1, NM2, log2P);
841 getMNP_single(pScrn, reg, clk, &NM1, &log2P);
842 setPLL_single(pScrn, reg, NM1, log2P);
847 static Bool init_prog(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
849 /* INIT_PROG opcode: 0x31
851 * offset (8 bit): opcode
852 * offset + 1 (32 bit): reg
853 * offset + 5 (32 bit): and mask
854 * offset + 9 (8 bit): shift right
855 * offset + 10 (8 bit): number of configurations
856 * offset + 11 (32 bit): register
857 * offset + 15 (32 bit): configuration 1
860 * Starting at offset + 15 there are "number of configurations"
861 * 32 bit values. To find out which configuration value to use
862 * read "CRTC reg" on the CRTC controller with index "CRTC index"
863 * and bitwise AND this value with "and mask" and then bit shift the
864 * result "shift right" bits to the right.
865 * Assign "register" with appropriate configuration value.
868 CARD32 reg = *((CARD32 *) (&bios->data[offset + 1]));
869 CARD32 and = *((CARD32 *) (&bios->data[offset + 5]));
870 CARD8 shiftr = *((CARD8 *) (&bios->data[offset + 9]));
871 CARD8 nr = *((CARD8 *) (&bios->data[offset + 10]));
872 CARD32 reg2 = *((CARD32 *) (&bios->data[offset + 11]));
874 CARD32 configval, tmp;
876 if (iexec->execute) {
877 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: REG: 0x%04X\n", offset,
880 tmp = nv32_rd(pScrn, reg);
881 configuration = (tmp & and) >> shiftr;
883 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONFIGURATION TO USE: 0x%02X\n",
884 offset, configuration);
886 if (configuration <= nr) {
889 *((CARD32 *) (&bios->data[offset + 15 + configuration * 4]));
891 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: REG: 0x%08X, VALUE: 0x%08X\n", offset,
894 tmp = nv32_rd(pScrn, reg2);
895 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CURRENT VALUE IS: 0x%08X\n",
897 nv32_wr(pScrn, reg2, configval);
904 static Bool init_io_restrict_prog(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
906 /* INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
908 * offset (8 bit): opcode
909 * offset + 1 (16 bit): CRTC port
910 * offset + 3 (8 bit): CRTC index
911 * offset + 4 (8 bit): mask
912 * offset + 5 (8 bit): shift
913 * offset + 6 (8 bit): count
914 * offset + 7 (32 bit): register
915 * offset + 11 (32 bit): configuration 1
918 * Starting at offset + 11 there are "count" 32 bit values.
919 * To find out which value to use read index "CRTC index" on "CRTC port",
920 * AND this value with "mask" and then bit shift right "shift" bits.
921 * Read the appropriate value using this index and write to "register"
924 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
925 uint8_t crtcindex = bios->data[offset + 3];
926 uint8_t mask = bios->data[offset + 4];
927 uint8_t shift = bios->data[offset + 5];
928 uint8_t count = bios->data[offset + 6];
929 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7])));
937 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
938 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
939 offset, crtcport, crtcindex, mask, shift, count, reg);
941 config = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) >> shift;
942 if (config > count) {
943 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
944 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
945 offset, config, count);
949 configval = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 11 + config * 4])));
952 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
953 "0x%04X: Writing config %02X\n", offset, config);
955 nv32_wr(pScrn, reg, configval);
960 static Bool init_repeat(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
962 /* INIT_REPEAT opcode: 0x33 ('3')
964 * offset (8 bit): opcode
965 * offset + 1 (8 bit): count
967 * Execute script following this opcode up to INIT_REPEAT_END
971 uint8_t count = bios->data[offset + 1];
974 /* no iexec->execute check by design */
976 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
977 "0x%04X: REPEATING FOLLOWING SEGMENT %d TIMES\n",
980 iexec->repeat = TRUE;
982 /* count - 1, as the script block will execute once when we leave this
983 * opcode -- this is compatible with bios behaviour as:
984 * a) the block is always executed at least once, even if count == 0
985 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
988 for (i = 0; i < count - 1; i++)
989 parse_init_table(pScrn, bios, offset + 2, iexec);
991 iexec->repeat = FALSE;
996 static Bool init_io_restrict_pll(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
998 /* INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
1000 * offset (8 bit): opcode
1001 * offset + 1 (16 bit): CRTC port
1002 * offset + 3 (8 bit): CRTC index
1003 * offset + 4 (8 bit): mask
1004 * offset + 5 (8 bit): shift
1005 * offset + 6 (8 bit): IO flag condition index
1006 * offset + 7 (8 bit): count
1007 * offset + 8 (32 bit): register
1008 * offset + 12 (16 bit): frequency 1
1011 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
1012 * Set PLL register "register" to coefficients for frequency n,
1013 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1014 * "mask" and shifted right by "shift". If "IO flag condition index" > 0,
1015 * and condition met, double frequency before setting it.
1018 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1019 uint8_t crtcindex = bios->data[offset + 3];
1020 uint8_t mask = bios->data[offset + 4];
1021 uint8_t shift = bios->data[offset + 5];
1022 int8_t io_flag_condition_idx = bios->data[offset + 6];
1023 uint8_t count = bios->data[offset + 7];
1024 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 8])));
1028 if (!iexec->execute)
1031 if (DEBUGLEVEL >= 6)
1032 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1033 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, IO Flag Condition: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1034 offset, crtcport, crtcindex, mask, shift, io_flag_condition_idx, count, reg);
1036 config = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) >> shift;
1037 if (config > count) {
1038 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1039 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1040 offset, config, count);
1044 freq = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 12 + config * 2])));
1046 if (io_flag_condition_idx > 0) {
1047 if (io_flag_condition(pScrn, bios, offset, io_flag_condition_idx)) {
1048 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1049 "0x%04X: CONDITION FULFILLED - FREQ DOUBLED\n", offset);
1052 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1053 "0x%04X: CONDITION IS NOT FULFILLED. FREQ UNCHANGED\n", offset);
1056 if (DEBUGLEVEL >= 6)
1057 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1058 "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
1059 offset, reg, config, freq);
1061 setPLL(pScrn, bios, reg, freq * 10);
1066 static Bool init_end_repeat(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1068 /* INIT_END_REPEAT opcode: 0x36 ('6')
1070 * offset (8 bit): opcode
1072 * Marks the end of the block for INIT_REPEAT to repeat
1075 /* no iexec->execute check by design */
1077 /* iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
1078 * we're not in repeat mode
1086 static Bool init_copy(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1088 /* INIT_COPY opcode: 0x37 ('7')
1090 * offset (8 bit): opcode
1091 * offset + 1 (32 bit): register
1092 * offset + 5 (8 bit): shift
1093 * offset + 6 (8 bit): srcmask
1094 * offset + 7 (16 bit): CRTC port
1095 * offset + 9 (8 bit): CRTC index
1096 * offset + 10 (8 bit): mask
1098 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
1099 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC port
1102 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1103 uint8_t shift = bios->data[offset + 5];
1104 uint8_t srcmask = bios->data[offset + 6];
1105 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 7])));
1106 uint8_t crtcindex = bios->data[offset + 9];
1107 uint8_t mask = bios->data[offset + 10];
1111 if (!iexec->execute)
1114 if (DEBUGLEVEL >= 6)
1115 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1116 "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1117 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1119 data = nv32_rd(pScrn, reg);
1124 data <<= (0x100 - shift);
1128 crtcdata = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) | (uint8_t)data;
1129 nv_idx_port_wr(pScrn, crtcport, crtcindex, crtcdata);
1134 static Bool init_not(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1136 /* INIT_NOT opcode: 0x38 ('8')
1138 * offset (8 bit): opcode
1140 * Invert the current execute / no-execute condition (i.e. "else")
1143 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1144 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
1146 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1147 "0x%04X: ------ EXECUTING FOLLOWING COMMANDS ------\n", offset);
1149 iexec->execute = !iexec->execute;
1153 static Bool init_io_flag_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1155 /* INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1157 * offset (8 bit): opcode
1158 * offset + 1 (8 bit): condition number
1160 * Check condition "condition number" in the IO flag condition table.
1161 * If condition not met skip subsequent opcodes until condition
1162 * is inverted (INIT_NOT), or we hit INIT_RESUME
1165 uint8_t cond = bios->data[offset + 1];
1167 if (!iexec->execute)
1170 if (io_flag_condition(pScrn, bios, offset, cond))
1171 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1172 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n", offset);
1174 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1175 "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
1176 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1177 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
1178 iexec->execute = FALSE;
1184 Bool init_idx_addr_latched(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1186 /* INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1188 * offset (8 bit): opcode
1189 * offset + 1 (32 bit): control register
1190 * offset + 5 (32 bit): data register
1191 * offset + 9 (32 bit): mask
1192 * offset + 13 (32 bit): data
1193 * offset + 17 (8 bit): count
1194 * offset + 18 (8 bit): address 1
1195 * offset + 19 (8 bit): data 1
1198 * For each of "count" address and data pairs, write "data n" to "data register",
1199 * read the current value of "control register", and write it back once ANDed
1200 * with "mask", ORed with "data", and ORed with "address n"
1203 uint32_t controlreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1204 uint32_t datareg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1205 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
1206 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 13])));
1207 uint8_t count = bios->data[offset + 17];
1211 if (!iexec->execute)
1214 if (DEBUGLEVEL >= 6)
1215 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1216 "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1217 offset, controlreg, datareg, mask, data, count);
1219 for (i = 0; i < count; i++) {
1220 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1221 uint8_t instdata = bios->data[offset + 19 + i * 2];
1223 if (DEBUGLEVEL >= 6)
1224 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1225 "0x%04X: Address: 0x%02X, Data: 0x%02X\n", offset, instaddress, instdata);
1227 nv32_wr(pScrn, datareg, instdata);
1228 value = (nv32_rd(pScrn, controlreg) & mask) | data | instaddress;
1229 nv32_wr(pScrn, controlreg, value);
1235 static Bool init_io_restrict_pll2(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1237 /* INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1239 * offset (8 bit): opcode
1240 * offset + 1 (16 bit): CRTC port
1241 * offset + 3 (8 bit): CRTC index
1242 * offset + 4 (8 bit): mask
1243 * offset + 5 (8 bit): shift
1244 * offset + 6 (8 bit): count
1245 * offset + 7 (32 bit): register
1246 * offset + 11 (32 bit): frequency 1
1249 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1250 * Set PLL register "register" to coefficients for frequency n,
1251 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1252 * "mask" and shifted right by "shift".
1255 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1256 uint8_t crtcindex = bios->data[offset + 3];
1257 uint8_t mask = bios->data[offset + 4];
1258 uint8_t shift = bios->data[offset + 5];
1259 uint8_t count = bios->data[offset + 6];
1260 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7])));
1264 if (!iexec->execute)
1267 if (DEBUGLEVEL >= 6)
1268 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1269 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1270 offset, crtcport, crtcindex, mask, shift, count, reg);
1275 config = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) >> shift;
1276 if (config > count) {
1277 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1278 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1279 offset, config, count);
1283 freq = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 11 + config * 4])));
1285 if (DEBUGLEVEL >= 6)
1286 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1287 "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1288 offset, reg, config, freq);
1290 setPLL(pScrn, bios, reg, freq);
1295 static Bool init_pll2(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1297 /* INIT_PLL2 opcode: 0x4B ('K')
1299 * offset (8 bit): opcode
1300 * offset + 1 (32 bit): register
1301 * offset + 5 (32 bit): freq
1303 * Set PLL register "register" to coefficients for frequency "freq"
1306 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1307 uint32_t freq = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1309 if (!iexec->execute)
1312 if (DEBUGLEVEL >= 6)
1313 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1314 "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1317 setPLL(pScrn, bios, reg, freq);
1322 static uint32_t get_tmds_index_reg(ScrnInfoPtr pScrn, uint8_t mlv)
1324 /* For mlv < 0x80, it is an index into a table of TMDS base addresses
1325 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by CR58 for CR57 = 0
1326 * to index a table of offsets to the basic 0x6808b0 address
1327 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by CR58 for CR57 = 0
1328 * to index a table of offsets to the basic 0x6808b0 address, and then flip the offset by 8
1331 NVPtr pNv = NVPTR(pScrn);
1332 int pramdac_offset[13] = {0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000};
1333 uint32_t pramdac_table[4] = {0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8};
1336 /* here we assume that the DCB table has already been parsed */
1339 /* This register needs to be written to set index for reading CR58 */
1340 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, 0x57, 0);
1341 dcb_entry = nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, 0x58);
1342 if (dcb_entry > pNv->dcb_table.entries) {
1343 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1344 "CR58 doesn't have a valid DCB entry currently (%02X)\n", dcb_entry);
1347 dacoffset = pramdac_offset[pNv->dcb_table.entry[dcb_entry].or];
1350 return (0x6808b0 + dacoffset);
1352 if (mlv > (sizeof(pramdac_table) / sizeof(uint32_t))) {
1353 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1354 "Magic Lookup Value too big (%02X)\n", mlv);
1357 return pramdac_table[mlv];
1361 static Bool init_tmds(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1363 /* INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1365 * offset (8 bit): opcode
1366 * offset + 1 (8 bit): magic lookup value
1367 * offset + 2 (8 bit): TMDS address
1368 * offset + 3 (8 bit): mask
1369 * offset + 4 (8 bit): data
1371 * Read the data reg for TMDS address "TMDS address", AND it with mask
1372 * and OR it with data, then write it back
1373 * "magic lookup value" determines which TMDS base address register is used --
1374 * see get_tmds_index_reg()
1377 uint8_t mlv = bios->data[offset + 1];
1378 uint32_t tmdsaddr = bios->data[offset + 2];
1379 uint8_t mask = bios->data[offset + 3];
1380 uint8_t data = bios->data[offset + 4];
1381 uint32_t reg, value;
1383 if (!iexec->execute)
1386 if (DEBUGLEVEL >= 6)
1387 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1388 "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1389 offset, mlv, tmdsaddr, mask, data);
1391 reg = get_tmds_index_reg(pScrn, mlv);
1393 nv32_wr(pScrn, reg, tmdsaddr | 0x10000);
1394 value = (nv32_rd(pScrn, reg + 4) & mask) | data;
1395 nv32_wr(pScrn, reg + 4, value);
1396 nv32_wr(pScrn, reg, tmdsaddr);
1401 Bool init_zm_tmds_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1403 /* INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1405 * offset (8 bit): opcode
1406 * offset + 1 (8 bit): magic lookup value
1407 * offset + 2 (8 bit): count
1408 * offset + 3 (8 bit): addr 1
1409 * offset + 4 (8 bit): data 1
1412 * For each of "count" TMDS address and data pairs write "data n" to "addr n"
1413 * "magic lookup value" determines which TMDS base address register is used --
1414 * see get_tmds_index_reg()
1417 uint8_t mlv = bios->data[offset + 1];
1418 uint8_t count = bios->data[offset + 2];
1422 if (!iexec->execute)
1425 if (DEBUGLEVEL >= 6)
1426 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1427 "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1428 offset, mlv, count);
1430 reg = get_tmds_index_reg(pScrn, mlv);
1432 for (i = 0; i < count; i++) {
1433 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1434 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1436 nv32_wr(pScrn, reg + 4, tmdsdata);
1437 nv32_wr(pScrn, reg, tmdsaddr);
1443 Bool init_cr_idx_adr_latch(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1445 /* INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1447 * offset (8 bit): opcode
1448 * offset + 1 (8 bit): CRTC index1
1449 * offset + 2 (8 bit): CRTC index2
1450 * offset + 3 (8 bit): baseaddr
1451 * offset + 4 (8 bit): count
1452 * offset + 5 (8 bit): data 1
1455 * For each of "count" address and data pairs, write "baseaddr + n" to
1456 * "CRTC index1" and "data n" to "CRTC index2"
1457 * Once complete, restore initial value read from "CRTC index1"
1459 uint8_t crtcindex1 = bios->data[offset + 1];
1460 uint8_t crtcindex2 = bios->data[offset + 2];
1461 uint8_t baseaddr = bios->data[offset + 3];
1462 uint8_t count = bios->data[offset + 4];
1463 uint8_t oldaddr, data;
1466 if (!iexec->execute)
1469 if (DEBUGLEVEL >= 6)
1470 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1471 "0x%04X: Index1: 0x%02X, Index2: 0x%02X, BaseAddr: 0x%02X, Count: 0x%02X\n",
1472 offset, crtcindex1, crtcindex2, baseaddr, count);
1474 oldaddr = nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, crtcindex1);
1476 for (i = 0; i < count; i++) {
1477 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex1, baseaddr + i);
1479 data = bios->data[offset + 5 + i];
1480 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex2, data);
1483 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex1, oldaddr);
1488 Bool init_cr(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1490 /* INIT_CR opcode: 0x52 ('R')
1492 * offset (8 bit): opcode
1493 * offset + 1 (8 bit): CRTC index
1494 * offset + 2 (8 bit): mask
1495 * offset + 3 (8 bit): data
1497 * Assign the value of at "CRTC index" ANDed with mask and ORed with data
1498 * back to "CRTC index"
1501 uint8_t crtcindex = bios->data[offset + 1];
1502 uint8_t mask = bios->data[offset + 2];
1503 uint8_t data = bios->data[offset + 3];
1506 if (!iexec->execute)
1509 if (DEBUGLEVEL >= 6)
1510 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1511 "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1512 offset, crtcindex, mask, data);
1514 value = (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, crtcindex) & mask) | data;
1515 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex, value);
1520 static Bool init_zm_cr(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1522 /* INIT_ZM_CR opcode: 0x53 ('S')
1524 * offset (8 bit): opcode
1525 * offset + 1 (8 bit): CRTC index
1526 * offset + 2 (8 bit): value
1528 * Assign "value" to CRTC register with index "CRTC index".
1531 uint8_t crtcindex = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1532 uint8_t data = bios->data[offset + 2];
1534 if (!iexec->execute)
1537 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex, data);
1542 static Bool init_zm_cr_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1544 /* INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1546 * offset (8 bit): opcode
1547 * offset + 1 (8 bit): count
1548 * offset + 2 (8 bit): CRTC index 1
1549 * offset + 3 (8 bit): value 1
1552 * For "count", assign "value n" to CRTC register with index "CRTC index n".
1555 uint8_t count = bios->data[offset + 1];
1558 if (!iexec->execute)
1561 for (i = 0; i < count; i++)
1562 init_zm_cr(pScrn, bios, offset + 2 + 2 * i - 1, iexec);
1567 static Bool init_condition_time(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1569 /* INIT_CONDITION_TIME opcode: 0x56 ('V')
1571 * offset (8 bit): opcode
1572 * offset + 1 (8 bit): condition number
1573 * offset + 2 (8 bit): retries / 50
1575 * Check condition "condition number" in the condition table.
1576 * The condition table entry has 4 bytes for the address of the
1577 * register to check, 4 bytes for a mask and 4 for a test value.
1578 * If condition not met sleep for 2ms, and repeat upto "retries" times.
1579 * If still not met after retries, clear execution flag for this table.
1582 uint8_t cond = bios->data[offset + 1];
1583 uint16_t retries = bios->data[offset + 2];
1584 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
1585 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[condptr])));
1586 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 4])));
1587 uint32_t cmpval = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 8])));
1590 if (!iexec->execute)
1595 if (DEBUGLEVEL >= 6)
1596 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1597 "0x%04X: Cond: 0x%02X, Retries: 0x%02X\n", offset, cond, retries);
1599 for (; retries > 0; retries--) {
1600 data = nv32_rd(pScrn, reg) & mask;
1602 if (DEBUGLEVEL >= 6)
1603 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1604 "0x%04X: Checking if 0x%08X equals 0x%08X\n",
1605 offset, data, cmpval);
1607 if (data != cmpval) {
1608 if (DEBUGLEVEL >= 6)
1609 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1610 "0x%04X: Condition not met, sleeping for 2ms\n", offset);
1613 if (DEBUGLEVEL >= 6)
1614 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1615 "0x%04X: Condition met, continuing\n", offset);
1620 if (data != cmpval) {
1621 if (DEBUGLEVEL >= 6)
1622 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1623 "0x%04X: Condition still not met, skiping following opcodes\n", offset);
1624 iexec->execute = FALSE;
1630 static Bool init_zm_reg_sequence(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1632 /* INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1634 * offset (8 bit): opcode
1635 * offset + 1 (32 bit): base register
1636 * offset + 5 (8 bit): count
1637 * offset + 6 (32 bit): value 1
1640 * Starting at offset + 6 there are "count" 32 bit values.
1641 * For "count" iterations set "base register" + 4 * current_iteration
1642 * to "value current_iteration"
1645 uint32_t basereg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1646 uint32_t count = bios->data[offset + 5];
1649 if (!iexec->execute)
1652 if (DEBUGLEVEL >= 6)
1653 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1654 "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1655 offset, basereg, count);
1657 for (i = 0; i < count; i++) {
1658 uint32_t reg = basereg + i * 4;
1659 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 6 + i * 4])));
1661 nv32_wr(pScrn, reg, data);
1668 static Bool init_indirect_reg(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
1670 /* INIT_INDIRECT_REG opcode: 0x5A
1672 * offset (8 bit): opcode
1673 * offset + 1 (32 bit): register
1674 * offset + 5 (16 bit): adress offset (in bios)
1676 * Lookup value at offset data in the bios and write it to reg
1678 CARD32 reg = *((CARD32 *) (&bios->data[offset + 1]));
1679 CARD16 data = le16_to_cpu(*((CARD16 *) (&bios->data[offset + 5])));
1680 CARD32 data2 = bios->data[data];
1682 if (iexec->execute) {
1683 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1684 "0x%04X: REG: 0x%04X, DATA AT: 0x%04X, VALUE IS: 0x%08X\n",
1685 offset, reg, data, data2);
1687 if (DEBUGLEVEL >= 6) {
1689 tmpval = nv32_rd(pScrn, reg);
1690 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CURRENT VALUE IS: 0x%08X\n", offset, tmpval);
1693 nv32_wr(pScrn, reg, data2);
1699 static Bool init_sub_direct(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1701 /* INIT_SUB_DIRECT opcode: 0x5B ('[')
1703 * offset (8 bit): opcode
1704 * offset + 1 (16 bit): subroutine offset (in bios)
1706 * Calls a subroutine that will execute commands until INIT_DONE
1710 uint16_t sub_offset = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1712 if (!iexec->execute)
1715 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: EXECUTING SUB-ROUTINE AT 0x%04X\n",
1716 offset, sub_offset);
1718 parse_init_table(pScrn, bios, sub_offset, iexec);
1720 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: END OF SUB-ROUTINE AT 0x%04X\n",
1721 offset, sub_offset);
1726 static Bool init_copy_nv_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1728 /* INIT_COPY_NV_REG opcode: 0x5F ('_')
1730 * offset (8 bit): opcode
1731 * offset + 1 (32 bit): src reg
1732 * offset + 5 (8 bit): shift
1733 * offset + 6 (32 bit): src mask
1734 * offset + 10 (32 bit): xor
1735 * offset + 14 (32 bit): dst reg
1736 * offset + 18 (32 bit): dst mask
1738 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
1739 * "src mask", then XOR with "xor". Write this OR'd with
1740 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
1743 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
1744 uint8_t shift = bios->data[offset + 5];
1745 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
1746 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
1747 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
1748 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
1749 uint32_t srcvalue, dstvalue;
1751 if (!iexec->execute)
1754 if (DEBUGLEVEL >= 6)
1755 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1756 "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
1757 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
1759 srcvalue = nv32_rd(pScrn, srcreg);
1764 srcvalue <<= (0x100 - shift);
1766 srcvalue = (srcvalue & srcmask) ^ xor;
1768 dstvalue = nv32_rd(pScrn, dstreg) & dstmask;
1770 nv32_wr(pScrn, dstreg, dstvalue | srcvalue);
1775 static Bool init_zm_index_io(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1777 /* INIT_ZM_INDEX_IO opcode: 0x62 ('b')
1779 * offset (8 bit): opcode
1780 * offset + 1 (16 bit): CRTC port
1781 * offset + 3 (8 bit): CRTC index
1782 * offset + 4 (8 bit): data
1784 * Write "data" to index "CRTC index" of "CRTC port"
1786 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1787 uint8_t crtcindex = bios->data[offset + 3];
1788 uint8_t data = bios->data[offset + 4];
1790 if (!iexec->execute)
1793 nv_idx_port_wr(pScrn, crtcport, crtcindex, data);
1798 static Bool init_compute_mem(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1800 /* INIT_COMPUTE_MEM opcode: 0x63 ('c')
1802 * offset (8 bit): opcode
1804 * This opcode is meant to set NV_PFB_CFG0 (0x100200) appropriately so
1805 * that the hardware can correctly calculate how much VRAM it has
1806 * (and subsequently report that value in 0x10020C)
1808 * The implementation of this opcode in general consists of two parts:
1809 * 1) determination of the memory bus width
1810 * 2) determination of how many of the card's RAM pads have ICs attached
1812 * 1) is done by a cunning combination of writes to offsets 0x1c and
1813 * 0x3c in the framebuffer, and seeing whether the written values are
1814 * read back correctly. This then affects bits 4-7 of NV_PFB_CFG0
1816 * 2) is done by a cunning combination of writes to an offset slightly
1817 * less than the maximum memory reported by 0x10020C, then seeing if
1818 * the test pattern can be read back. This then affects bits 12-15 of
1821 * In this context a "cunning combination" may include multiple reads
1822 * and writes to varying locations, often alternating the test pattern
1823 * and 0, doubtless to make sure buffers are filled, residual charges
1824 * on tracks are removed etc.
1826 * Unfortunately, the "cunning combination"s mentioned above, and the
1827 * changes to the bits in NV_PFB_CFG0 differ with nearly every bios
1830 * Therefore, we cheat and assume the value of NV_PFB_CFG0 with which
1831 * we started was correct, and use that instead
1834 /* no iexec->execute check by design */
1836 /* on every card I've seen, this step gets done for us earlier in the init scripts
1837 uint8_t crdata = nv_idx_port_rd(pScrn, VGA_SEQ_INDEX, 0x01);
1838 nv_idx_port_wr(pScrn, VGA_SEQ_INDEX, 0x01, crdata | 0x20);
1841 /* this also has probably been done in the scripts, but an mmio trace of
1842 * s3 resume shows nvidia doing it anyway (unlike the VGA_SEQ_INDEX write)
1844 nv32_wr(pScrn, NV_PFB_REFCTRL, NV_PFB_REFCTRL_VALID_1);
1846 /* write back the saved configuration value */
1847 nv32_wr(pScrn, NV_PFB_CFG0, saved_nv_pfb_cfg0);
1852 static Bool init_reset(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1854 /* INIT_RESET opcode: 0x65 ('e')
1856 * offset (8 bit): opcode
1857 * offset + 1 (32 bit): register
1858 * offset + 5 (32 bit): value1
1859 * offset + 9 (32 bit): value2
1861 * Assign "value1" to "register", then assign "value2" to "register"
1864 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1865 uint32_t value1 = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1866 uint32_t value2 = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
1867 uint32_t pci_nv_19, pci_nv_20;
1869 /* no iexec->execute check by design */
1871 pci_nv_19 = nv32_rd(pScrn, NV_PBUS_PCI_NV_19);
1872 nv32_wr(pScrn, NV_PBUS_PCI_NV_19, 0);
1873 nv32_wr(pScrn, reg, value1);
1877 nv32_wr(pScrn, reg, value2);
1878 nv32_wr(pScrn, NV_PBUS_PCI_NV_19, pci_nv_19);
1880 pci_nv_20 = nv32_rd(pScrn, NV_PBUS_PCI_NV_20);
1881 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
1882 nv32_wr(pScrn, NV_PBUS_PCI_NV_20, pci_nv_20);
1888 static Bool init_index_io8(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
1890 /* INIT_INDEX_IO8 opcode: 0x69
1892 * offset (8 bit): opcode
1893 * offset + 1 (16 bit): CRTC reg
1894 * offset + 3 (8 bit): and mask
1895 * offset + 4 (8 bit): or with
1900 NVPtr pNv = NVPTR(pScrn);
1901 volatile CARD8 *ptr = crtchead ? pNv->PCIO1 : pNv->PCIO0;
1902 CARD16 reg = le16_to_cpu(*((CARD16 *)(&bios->data[offset + 1])));
1903 CARD8 and = *((CARD8 *)(&bios->data[offset + 3]));
1904 CARD8 or = *((CARD8 *)(&bios->data[offset + 4]));
1907 if (iexec->execute) {
1908 data = (VGA_RD08(ptr, reg) & and) | or;
1910 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1911 "0x%04X: CRTC REG: 0x%04X, VALUE: 0x%02X\n",
1913 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CURRENT VALUE IS: 0x%02X\n", offset,
1914 VGA_RD08(ptr, reg));
1916 #ifdef PERFORM_WRITE
1917 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "init_index_io8 crtcreg 0x%X value 0x%X\n",reg,data);
1919 VGA_WR08(ptr, reg, data);
1926 static Bool init_sub(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1928 /* INIT_SUB opcode: 0x6B ('k')
1930 * offset (8 bit): opcode
1931 * offset + 1 (8 bit): script number
1933 * Execute script number "script number", as a subroutine
1936 uint8_t sub = bios->data[offset + 1];
1938 if (!iexec->execute)
1941 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1942 "0x%04X: EXECUTING SUB-SCRIPT %d\n", offset, sub);
1944 parse_init_table(pScrn, bios,
1945 le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + sub * 2]))),
1948 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1949 "0x%04X: END OF SUB-SCRIPT %d\n", offset, sub);
1955 static Bool init_ram_condition(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
1957 /* INIT_RAM_CONDITION opcode: 0x6D
1959 * offset (8 bit): opcode
1960 * offset + 1 (8 bit): and mask
1961 * offset + 2 (8 bit): cmpval
1963 * Test if (NV_PFB_BOOT & and mask) matches cmpval
1965 NVPtr pNv = NVPTR(pScrn);
1966 CARD8 and = *((CARD8 *) (&bios->data[offset + 1]));
1967 CARD8 cmpval = *((CARD8 *) (&bios->data[offset + 2]));
1970 if (iexec->execute) {
1971 data=(pNv->PFB[NV_PFB_BOOT/4])∧
1973 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1974 "0x%04X: CHECKING IF REGVAL: 0x%08X equals COND: 0x%08X\n",
1975 offset, data, cmpval);
1977 if (data == cmpval) {
1978 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1979 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n",
1982 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
1983 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1984 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
1985 iexec->execute = FALSE;
1992 static Bool init_nv_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1994 /* INIT_NV_REG opcode: 0x6E ('n')
1996 * offset (8 bit): opcode
1997 * offset + 1 (32 bit): register
1998 * offset + 5 (32 bit): mask
1999 * offset + 9 (32 bit): data
2001 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2004 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2005 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
2006 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
2008 if (!iexec->execute)
2011 if (DEBUGLEVEL >= 6)
2012 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2013 "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2014 offset, reg, mask, data);
2016 nv32_wr(pScrn, reg, (nv32_rd(pScrn, reg) & mask) | data);
2021 static Bool init_macro(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2023 /* INIT_MACRO opcode: 0x6F ('o')
2025 * offset (8 bit): opcode
2026 * offset + 1 (8 bit): macro number
2028 * Look up macro index "macro number" in the macro index table.
2029 * The macro index table entry has 1 byte for the index in the macro table,
2030 * and 1 byte for the number of times to repeat the macro.
2031 * The macro table entry has 4 bytes for the register address and
2032 * 4 bytes for the value to write to that register
2035 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2036 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2037 uint8_t macro_tbl_idx = bios->data[tmp];
2038 uint8_t count = bios->data[tmp + 1];
2042 if (!iexec->execute)
2045 if (DEBUGLEVEL >= 6)
2046 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2047 "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, Count: 0x%02X\n",
2048 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2050 for (i = 0; i < count; i++) {
2051 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2053 reg = le32_to_cpu(*((uint32_t *)(&bios->data[macroentryptr])));
2054 data = le32_to_cpu(*((uint32_t *)(&bios->data[macroentryptr + 4])));
2056 nv32_wr(pScrn, reg, data);
2062 static Bool init_done(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2064 /* INIT_DONE opcode: 0x71 ('q')
2066 * offset (8 bit): opcode
2068 * End the current script
2071 /* mild retval abuse to stop parsing this table */
2075 static Bool init_resume(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2077 /* INIT_RESUME opcode: 0x72 ('r')
2079 * offset (8 bit): opcode
2081 * End the current execute / no-execute condition
2087 iexec->execute = TRUE;;
2088 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2089 "0x%04X: ---- EXECUTING FOLLOWING COMMANDS ----\n", offset);
2095 static Bool init_ram_condition2(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
2097 /* INIT_RAM_CONDITION2 opcode: 0x73
2099 * offset (8 bit): opcode
2100 * offset + 1 (8 bit): and mask
2101 * offset + 2 (8 bit): cmpval
2103 * Test if (NV_EXTDEV_BOOT & and mask) matches cmpval
2105 NVPtr pNv = NVPTR(pScrn);
2106 CARD32 and = *((CARD32 *) (&bios->data[offset + 1]));
2107 CARD32 cmpval = *((CARD32 *) (&bios->data[offset + 5]));
2110 if (iexec->execute) {
2111 data=(nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT))∧
2113 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2114 "0x%04X: CHECKING IF REGVAL: 0x%08X equals COND: 0x%08X\n",
2115 offset, data, cmpval);
2117 if (data == cmpval) {
2118 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2119 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n",
2122 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
2123 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2124 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
2125 iexec->execute = FALSE;
2132 static Bool init_time(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2134 /* INIT_TIME opcode: 0x74 ('t')
2136 * offset (8 bit): opcode
2137 * offset + 1 (16 bit): time
2139 * Sleep for "time" microseconds.
2142 uint16_t time = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
2144 if (!iexec->execute)
2147 if (DEBUGLEVEL >= 6)
2148 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2149 "0x%04X: Sleeping for 0x%04X microseconds\n", offset, time);
2156 static Bool init_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2158 /* INIT_CONDITION opcode: 0x75 ('u')
2160 * offset (8 bit): opcode
2161 * offset + 1 (8 bit): condition number
2163 * Check condition "condition number" in the condition table.
2164 * The condition table entry has 4 bytes for the address of the
2165 * register to check, 4 bytes for a mask and 4 for a test value.
2166 * If condition not met skip subsequent opcodes until condition
2167 * is inverted (INIT_NOT), or we hit INIT_RESUME
2170 uint8_t cond = bios->data[offset + 1];
2171 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
2172 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[condptr])));
2173 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 4])));
2174 uint32_t cmpval = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 8])));
2177 if (!iexec->execute)
2180 if (DEBUGLEVEL >= 6)
2181 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2182 "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X, Cmpval: 0x%08X\n",
2183 offset, cond, reg, mask, cmpval);
2185 data = nv32_rd(pScrn, reg) & mask;
2187 if (DEBUGLEVEL >= 6)
2188 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2189 "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2190 offset, data, cmpval);
2192 if (data == cmpval) {
2193 if (DEBUGLEVEL >= 6)
2194 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2195 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n", offset);
2197 if (DEBUGLEVEL >= 6)
2198 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2199 "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
2200 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2201 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
2202 iexec->execute = FALSE;
2208 static Bool init_index_io(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2210 /* INIT_INDEX_IO opcode: 0x78 ('x')
2212 * offset (8 bit): opcode
2213 * offset + 1 (16 bit): CRTC port
2214 * offset + 3 (8 bit): CRTC index
2215 * offset + 4 (8 bit): mask
2216 * offset + 5 (8 bit): data
2218 * Read value at index "CRTC index" on "CRTC port", AND with "mask", OR with "data", write-back
2221 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
2222 uint8_t crtcindex = bios->data[offset + 3];
2223 uint8_t mask = bios->data[offset + 4];
2224 uint8_t data = bios->data[offset + 5];
2227 if (!iexec->execute)
2230 if (DEBUGLEVEL >= 6)
2231 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2232 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
2233 offset, crtcport, crtcindex, mask, data);
2235 value = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) | data;
2236 nv_idx_port_wr(pScrn, crtcport, crtcindex, value);
2241 static Bool init_pll(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2243 /* INIT_PLL opcode: 0x79 ('y')
2245 * offset (8 bit): opcode
2246 * offset + 1 (32 bit): register
2247 * offset + 5 (16 bit): freq
2249 * Set PLL register "register" to coefficients for frequency (10kHz) "freq"
2252 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2253 uint16_t freq = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 5])));
2255 if (!iexec->execute)
2258 if (DEBUGLEVEL >= 6)
2259 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2260 "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n",
2263 setPLL(pScrn, bios, reg, freq * 10);
2268 static Bool init_zm_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2270 /* INIT_ZM_REG opcode: 0x7A ('z')
2272 * offset (8 bit): opcode
2273 * offset + 1 (32 bit): register
2274 * offset + 5 (32 bit): value
2276 * Assign "value" to "register"
2279 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2280 uint32_t value = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
2282 if (!iexec->execute)
2285 nv32_wr(pScrn, reg, value);
2290 /* hack to avoid moving the itbl_entry array before this function */
2291 int init_ram_restrict_zm_reg_group_blocklen = 0;
2293 static Bool init_ram_restrict_zm_reg_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2295 /* INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
2297 * offset (8 bit): opcode
2298 * offset + 1 (32 bit): reg
2299 * offset + 5 (8 bit): regincrement
2300 * offset + 6 (8 bit): count
2301 * offset + 7 (32 bit): value 1,1
2304 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2305 * ram_restrict_table_ptr. The value read from here is 'n', and
2306 * "value 1,n" gets written to "reg". This repeats "count" times and on
2307 * each iteration 'm', "reg" increases by "regincrement" and
2308 * "value m,n" is used. The extent of n is limited by a number read
2309 * from the 'M' BIT table, herein called "blocklen"
2312 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2313 uint8_t regincrement = bios->data[offset + 5];
2314 uint8_t count = bios->data[offset + 6];
2315 uint32_t strap_ramcfg, data;
2320 /* previously set by 'M' BIT table */
2321 blocklen = init_ram_restrict_zm_reg_group_blocklen;
2323 if (!iexec->execute)
2327 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2328 "0x%04X: Zero block length - has the M table been parsed?\n", offset);
2332 strap_ramcfg = (nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
2333 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
2335 if (DEBUGLEVEL >= 6)
2336 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2337 "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
2338 offset, reg, regincrement, count, strap_ramcfg, index);
2340 for (i = 0; i < count; i++) {
2341 data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7 + index * 4 + blocklen * i])));
2343 nv32_wr(pScrn, reg, data);
2345 reg += regincrement;
2351 static Bool init_copy_zm_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2353 /* INIT_COPY_ZM_REG opcode: 0x90 ('')
2355 * offset (8 bit): opcode
2356 * offset + 1 (32 bit): src reg
2357 * offset + 5 (32 bit): dst reg
2359 * Put contents of "src reg" into "dst reg"
2362 uint32_t srcreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2363 uint32_t dstreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
2365 if (!iexec->execute)
2368 nv32_wr(pScrn, dstreg, nv32_rd(pScrn, srcreg));
2373 static Bool init_zm_reg_group_addr_latched(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2375 /* INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
2377 * offset (8 bit): opcode
2378 * offset + 1 (32 bit): src reg
2379 * offset + 5 (8 bit): count
2380 * offset + 6 (32 bit): data 1
2383 * For each of "count" values write "data n" to "src reg"
2386 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2387 uint8_t count = bios->data[offset + 5];
2390 if (!iexec->execute)
2393 for (i = 0; i < count; i++) {
2394 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 6 + 4 * i])));
2395 nv32_wr(pScrn, reg, data);
2401 static Bool init_reserved(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2403 /* INIT_RESERVED opcode: 0x92 ('')
2405 * offset (8 bit): opcode
2407 * Seemingly does nothing
2413 static init_tbl_entry_t itbl_entry[] = {
2414 /* command name , id , length , offset , mult , command handler */
2415 // { "INIT_PROG" , 0x31, 15 , 10 , 4 , init_prog },
2416 { "INIT_IO_RESTRICT_PROG" , 0x32, 11 , 6 , 4 , init_io_restrict_prog },
2417 { "INIT_REPEAT" , 0x33, 2 , 0 , 0 , init_repeat },
2418 { "INIT_IO_RESTRICT_PLL" , 0x34, 12 , 7 , 2 , init_io_restrict_pll },
2419 { "INIT_END_REPEAT" , 0x36, 1 , 0 , 0 , init_end_repeat },
2420 { "INIT_COPY" , 0x37, 11 , 0 , 0 , init_copy },
2421 { "INIT_NOT" , 0x38, 1 , 0 , 0 , init_not },
2422 { "INIT_IO_FLAG_CONDITION" , 0x39, 2 , 0 , 0 , init_io_flag_condition },
2423 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, 18 , 17 , 2 , init_idx_addr_latched },
2424 { "INIT_IO_RESTRICT_PLL2" , 0x4A, 11 , 6 , 4 , init_io_restrict_pll2 },
2425 { "INIT_PLL2" , 0x4B, 9 , 0 , 0 , init_pll2 },
2426 /* { "INIT_I2C_BYTE" , 0x4C, x , x , x , init_i2c_byte }, */
2427 /* { "INIT_ZM_I2C_BYTE" , 0x4D, x , x , x , init_zm_i2c_byte }, */
2428 /* { "INIT_ZM_I2C" , 0x4E, x , x , x , init_zm_i2c }, */
2429 { "INIT_TMDS" , 0x4F, 5 , 0 , 0 , init_tmds },
2430 { "INIT_ZM_TMDS_GROUP" , 0x50, 3 , 2 , 2 , init_zm_tmds_group },
2431 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, 5 , 4 , 1 , init_cr_idx_adr_latch },
2432 { "INIT_CR" , 0x52, 4 , 0 , 0 , init_cr },
2433 { "INIT_ZM_CR" , 0x53, 3 , 0 , 0 , init_zm_cr },
2434 { "INIT_ZM_CR_GROUP" , 0x54, 2 , 1 , 2 , init_zm_cr_group },
2435 { "INIT_CONDITION_TIME" , 0x56, 3 , 0 , 0 , init_condition_time },
2436 { "INIT_ZM_REG_SEQUENCE" , 0x58, 6 , 5 , 4 , init_zm_reg_sequence },
2437 // { "INIT_INDIRECT_REG" , 0x5A, 7 , 0 , 0 , init_indirect_reg },
2438 { "INIT_SUB_DIRECT" , 0x5B, 3 , 0 , 0 , init_sub_direct },
2439 { "INIT_COPY_NV_REG" , 0x5F, 22 , 0 , 0 , init_copy_nv_reg },
2440 { "INIT_ZM_INDEX_IO" , 0x62, 5 , 0 , 0 , init_zm_index_io },
2441 { "INIT_COMPUTE_MEM" , 0x63, 1 , 0 , 0 , init_compute_mem },
2442 { "INIT_RESET" , 0x65, 13 , 0 , 0 , init_reset },
2443 /* { "INIT_NEXT" , 0x66, x , x , x , init_next }, */
2444 /* { "INIT_NEXT" , 0x67, x , x , x , init_next }, */
2445 /* { "INIT_NEXT" , 0x68, x , x , x , init_next }, */
2446 // { "INIT_INDEX_IO8" , 0x69, 5 , 0 , 0 , init_index_io8 },
2447 { "INIT_SUB" , 0x6B, 2 , 0 , 0 , init_sub },
2448 // { "INIT_RAM_CONDITION" , 0x6D, 3 , 0 , 0 , init_ram_condition },
2449 { "INIT_NV_REG" , 0x6E, 13 , 0 , 0 , init_nv_reg },
2450 { "INIT_MACRO" , 0x6F, 2 , 0 , 0 , init_macro },
2451 { "INIT_DONE" , 0x71, 1 , 0 , 0 , init_done },
2452 { "INIT_RESUME" , 0x72, 1 , 0 , 0 , init_resume },
2453 // { "INIT_RAM_CONDITION2" , 0x73, 9 , 0 , 0 , init_ram_condition2 },
2454 { "INIT_TIME" , 0x74, 3 , 0 , 0 , init_time },
2455 { "INIT_CONDITION" , 0x75, 2 , 0 , 0 , init_condition },
2456 /* { "INIT_IO_CONDITION" , 0x76, x , x , x , init_io_condition }, */
2457 { "INIT_INDEX_IO" , 0x78, 6 , 0 , 0 , init_index_io },
2458 { "INIT_PLL" , 0x79, 7 , 0 , 0 , init_pll },
2459 { "INIT_ZM_REG" , 0x7A, 9 , 0 , 0 , init_zm_reg },
2460 /* INIT_RAM_RESTRICT_ZM_REG_GROUP's mult is loaded by M table in BIT */
2461 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, 7 , 6 , 0 , init_ram_restrict_zm_reg_group },
2462 { "INIT_COPY_ZM_REG" , 0x90, 9 , 0 , 0 , init_copy_zm_reg },
2463 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, 6 , 5 , 4 , init_zm_reg_group_addr_latched },
2464 { "INIT_RESERVED" , 0x92, 1 , 0 , 0 , init_reserved },
2465 { 0 , 0 , 0 , 0 , 0 , 0 }
2468 static unsigned int get_init_table_entry_length(bios_t *bios, unsigned int offset, int i)
2470 /* Calculates the length of a given init table entry. */
2471 return itbl_entry[i].length + bios->data[offset + itbl_entry[i].length_offset]*itbl_entry[i].length_multiplier;
2474 static void parse_init_table(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset, init_exec_t *iexec)
2476 /* Parses all commands in a init table. */
2478 /* We start out executing all commands found in the
2479 * init table. Some op codes may change the status
2480 * of this variable to SKIP, which will cause
2481 * the following op codes to perform no operation until
2482 * the value is changed back to EXECUTE.
2488 /* Loop until INIT_DONE causes us to break out of the loop
2489 * (or until offset > bios length just in case... )
2490 * (and no more than 10000 iterations just in case... ) */
2491 while ((offset < bios->length) && (count++ < 10000)) {
2492 id = bios->data[offset];
2494 /* Find matching id in itbl_entry */
2495 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
2498 if (itbl_entry[i].name) {
2499 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: [ (0x%02X) - %s ]\n",
2500 offset, itbl_entry[i].id, itbl_entry[i].name);
2502 /* execute eventual command handler */
2503 if (itbl_entry[i].handler)
2504 if (!(*itbl_entry[i].handler)(pScrn, bios, offset, iexec))
2507 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2508 "0x%04X: Init table command not found: 0x%02X\n", offset, id);
2512 /* Add the offset of the current command including all data
2513 * of that command. The offset will then be pointing on the
2516 offset += get_init_table_entry_length(bios, offset, i);
2520 static void parse_init_tables(ScrnInfoPtr pScrn, bios_t *bios)
2522 /* Loops and calls parse_init_table() for each present table. */
2526 init_exec_t iexec = {TRUE, FALSE};
2528 while ((table = le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + i]))))) {
2530 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: Parsing init table %d\n",
2533 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2534 "0x%04X: ------ EXECUTING FOLLOWING COMMANDS ------\n", table);
2536 parse_init_table(pScrn, bios, table, &iexec);
2541 void link_head_and_output(ScrnInfoPtr pScrn, int head, int dcb_entry, Bool overrideval)
2543 /* The BIOS scripts don't do this for us, sadly
2544 * Luckily we do know the values ;-)
2546 * head < 0 indicates we wish to force a setting with the overrideval
2547 * (for VT restore etc.)
2550 NVPtr pNv = NVPTR(pScrn);
2551 int preferred_output = (ffs(pNv->dcb_table.entry[dcb_entry].or) & OUTPUT_1) >> 1;
2552 uint8_t tmds04 = 0x80;
2553 uint32_t tmds_ctrl, tmds_ctrl2;
2555 /* Bit 3 crosswires output and bus. */
2556 if (head >= 0 && head != preferred_output)
2558 if (head < 0 && overrideval)
2561 if (pNv->dcb_table.entry[dcb_entry].type == OUTPUT_LVDS)
2564 tmds_ctrl = NV_PRAMDAC0_OFFSET + (preferred_output ? NV_PRAMDAC0_SIZE : 0) + NV_RAMDAC_FP_TMDS_CONTROL;
2565 tmds_ctrl2 = NV_PRAMDAC0_OFFSET + (preferred_output ? NV_PRAMDAC0_SIZE : 0) + NV_RAMDAC_FP_TMDS_CONTROL_2;
2567 Bool oldexecute = pNv->VBIOS.execute;
2568 pNv->VBIOS.execute = TRUE;
2569 nv32_wr(pScrn, tmds_ctrl + 4, tmds04);
2570 nv32_wr(pScrn, tmds_ctrl, 0x04);
2571 if (pNv->dcb_table.entry[dcb_entry].type == OUTPUT_LVDS && pNv->VBIOS.fp.dual_link)
2572 nv32_wr(pScrn, tmds_ctrl2 + 4, tmds04 ^ 0x08);
2574 /* I have encountered no dvi (dual-link or not) that sets to anything else. */
2575 /* Does this change beyond the 165 MHz boundary? */
2576 nv32_wr(pScrn, tmds_ctrl2 + 4, 0x0);
2578 nv32_wr(pScrn, tmds_ctrl2, 0x04);
2579 pNv->VBIOS.execute = oldexecute;
2582 static void call_lvds_manufacturer_script(ScrnInfoPtr pScrn, int head, int dcb_entry, enum LVDS_script script)
2584 NVPtr pNv = NVPTR(pScrn);
2585 bios_t *bios = &pNv->VBIOS;
2586 init_exec_t iexec = {TRUE, FALSE};
2588 uint8_t sub = bios->data[bios->fp.xlated_entry + script];
2589 uint16_t scriptofs = le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + sub * 2])));
2590 Bool power_off_for_reset;
2591 uint16_t off_on_delay;
2593 if (!bios->fp.xlated_entry || !sub || !scriptofs)
2596 if (script == LVDS_INIT && bios->data[scriptofs] != 'q') {
2597 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "LVDS init script not stubbed\n");
2601 power_off_for_reset = bios->data[bios->fp.xlated_entry] & 1;
2602 off_on_delay = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.xlated_entry + 7]);
2604 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
2605 call_lvds_manufacturer_script(pScrn, head, dcb_entry, LVDS_RESET);
2606 if (script == LVDS_RESET && power_off_for_reset)
2607 call_lvds_manufacturer_script(pScrn, head, dcb_entry, LVDS_PANEL_OFF);
2609 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Calling LVDS script %d:\n", script);
2610 pNv->VBIOS.execute = TRUE;
2611 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_OWNER,
2612 head ? NV_VGA_CRTCX_OWNER_HEADB : NV_VGA_CRTCX_OWNER_HEADA);
2613 parse_init_table(pScrn, bios, scriptofs, &iexec);
2614 pNv->VBIOS.execute = FALSE;
2616 if (script == LVDS_PANEL_OFF)
2617 usleep(off_on_delay * 1000);
2618 if (script == LVDS_RESET)
2619 link_head_and_output(pScrn, head, dcb_entry, FALSE);
2622 static uint16_t clkcmptable(bios_t *bios, uint16_t clktable, int pxclk)
2624 int compare_record_len, i = 0;
2625 uint16_t compareclk, scriptptr = 0;
2627 if (bios->major_version < 5) /* pre BIT */
2628 compare_record_len = 3;
2630 compare_record_len = 4;
2633 compareclk = le16_to_cpu(*((uint16_t *)&bios->data[clktable + compare_record_len * i]));
2634 if (pxclk >= compareclk * 10) {
2635 if (bios->major_version < 5) {
2636 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
2637 scriptptr = le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + tmdssub * 2])));
2639 scriptptr = le16_to_cpu(*((uint16_t *)&bios->data[clktable + 2 + compare_record_len * i]));
2643 } while (compareclk);
2648 static void rundigitaloutscript(ScrnInfoPtr pScrn, uint16_t scriptptr, int head, int dcb_entry)
2650 bios_t *bios = &NVPTR(pScrn)->VBIOS;
2651 init_exec_t iexec = {TRUE, FALSE};
2653 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: Parsing digital output script table\n", scriptptr);
2654 bios->execute = TRUE;
2655 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_OWNER,
2656 head ? NV_VGA_CRTCX_OWNER_HEADB : NV_VGA_CRTCX_OWNER_HEADA);
2657 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, 0x57, 0);
2658 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, 0x58, dcb_entry);
2659 parse_init_table(pScrn, bios, scriptptr, &iexec);
2660 bios->execute = FALSE;
2662 link_head_and_output(pScrn, head, dcb_entry, FALSE);
2665 static void run_lvds_table(ScrnInfoPtr pScrn, int head, int dcb_entry, enum LVDS_script script, int pxclk)
2667 /* The BIT LVDS table's header has the information to setup the
2668 * necessary registers. Following the standard 4 byte header are:
2669 * A bitmask byte and a dual-link transition pxclk value for use in
2670 * selecting the init script when not using straps; 4 script pointers
2671 * for panel power, selected by output and on/off; and 8 table pointers
2672 * for panel init, the needed one determined by output, and bits in the
2673 * conf byte. These tables are similar to the TMDS tables, consisting
2674 * of a list of pxclks and script pointers.
2677 NVPtr pNv = NVPTR(pScrn);
2678 bios_t *bios = &pNv->VBIOS;
2679 unsigned int fpstrapping, outputset = (pNv->dcb_table.entry[dcb_entry].or == 4) ? 1 : 0;
2680 uint16_t scriptptr = 0, clktable;
2681 uint8_t clktableptr = 0;
2683 fpstrapping = (nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
2685 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
2686 run_lvds_table(pScrn, head, dcb_entry, LVDS_RESET, pxclk);
2687 /* no sign of the "panel off for reset" bit, but it's safer to assume we should */
2688 if (script == LVDS_RESET)
2689 run_lvds_table(pScrn, head, dcb_entry, LVDS_PANEL_OFF, pxclk);
2691 /* for now we assume version 3.0 table - g80 support will need some changes */
2696 case LVDS_BACKLIGHT_ON: // check applicability of the script for this
2698 scriptptr = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
2700 case LVDS_BACKLIGHT_OFF: // check applicability of the script for this
2701 case LVDS_PANEL_OFF:
2702 scriptptr = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
2705 if (pNv->dcb_table.entry[dcb_entry].lvdsconf.use_straps_for_mode ||
2706 (fpstrapping != 0x0f && bios->data[bios->fp.xlated_entry + 1] != 0x0f)) {
2707 if (bios->fp.dual_link)
2709 if (bios->fp.BITbit1)
2712 uint8_t fallback = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
2713 int fallbackcmpval = (pNv->dcb_table.entry[dcb_entry].or == 4) ? 4 : 1;
2715 if (pxclk >= bios->fp.duallink_transition_clk) {
2717 fallbackcmpval *= 2;
2719 if (fallbackcmpval & fallback)
2723 /* adding outputset * 8 may not be correct */
2724 clktable = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 15 + clktableptr * 2 + outputset * 8]);
2726 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Pixel clock comparison table not found\n");
2729 scriptptr = clkcmptable(bios, clktable, pxclk);
2733 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "LVDS output init script not found\n");
2736 rundigitaloutscript(pScrn, scriptptr, head, dcb_entry);
2739 void call_lvds_script(ScrnInfoPtr pScrn, int head, int dcb_entry, enum LVDS_script script, int pxclk)
2741 /* LVDS operations are multiplexed in an effort to present a single API
2742 * which works with two vastly differing underlying structures.
2743 * This acts as the demux
2746 bios_t *bios = &NVPTR(pScrn)->VBIOS;
2747 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
2752 if (lvds_ver < 0x30)
2753 call_lvds_manufacturer_script(pScrn, head, dcb_entry, script);
2755 run_lvds_table(pScrn, head, dcb_entry, script, pxclk);
2759 uint16_t fptablepointer;
2760 uint16_t fpxlatetableptr;
2761 uint16_t fpxlatemanufacturertableptr;
2765 static void parse_fp_mode_table(ScrnInfoPtr pScrn, bios_t *bios, struct fppointers *fpp)
2767 unsigned int fpstrapping;
2769 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
2771 DisplayModePtr mode;
2773 fpstrapping = (nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
2775 if (fpp->fptablepointer == 0x0 || fpp->fpxlatetableptr == 0x0) {
2776 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2777 "Pointers to flat panel table invalid\n");
2781 fptable = &bios->data[fpp->fptablepointer];
2783 fptable_ver = fptable[0];
2785 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2786 "Found flat panel mode table revision %d.%d\n",
2787 fptable_ver >> 4, fptable_ver & 0xf);
2789 switch (fptable_ver) {
2790 /* BMP version 0x5.0x11 BIOSen have version 1 like tables, but no version field,
2791 * and miss one of the spread spectrum/PWM bytes.
2792 * This could affect early GF2Go parts (not seen any appropriate ROMs though).
2793 * Here we assume that a version of 0x05 matches this case (combining with a
2794 * BMP version check would be better), as the common case for the panel type
2795 * field is 0x0005, and that is in fact what we are reading the first byte of. */
2796 case 0x05: /* some NV10, 11, 15, 16 */
2800 case 0x10: /* some NV15/16, and NV11+ */
2804 case 0x20: /* NV40+ */
2805 headerlen = fptable[1];
2806 recordlen = fptable[2];
2807 fpentries = fptable[3];
2808 /* fptable[4] is the minimum RAMDAC_FP_HCRTC->RAMDAC_FP_HSYNC_START gap.
2809 * Only seen 0x4b (=75) which is what is used in nv_crtc.c anyway,
2810 * so we're not using this table value for now
2815 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2816 "FP Table revision not currently supported\n");
2820 fpindex = bios->data[fpp->fpxlatetableptr + fpstrapping * fpp->xlatwidth];
2821 if (fpindex > fpentries) {
2822 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2823 "Bad flat panel table index\n");
2827 /* reserved values - means that ddc or hard coded edid should be used */
2828 if (fpindex == 0xf && fpstrapping == 0xf) {
2829 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Ignoring FP table\n");
2833 if (!(mode = xcalloc(1, sizeof(DisplayModeRec))))
2836 int modeofs = headerlen + recordlen * fpindex + ofs;
2837 mode->Clock = le16_to_cpu(*(uint16_t *)&fptable[modeofs]) * 10;
2838 mode->HDisplay = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 2]);
2839 mode->HSyncStart = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 10] + 1);
2840 mode->HSyncEnd = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 12] + 1);
2841 mode->HTotal = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 14] + 1);
2842 mode->VDisplay = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 16]);
2843 mode->VSyncStart = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 24] + 1);
2844 mode->VSyncEnd = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 26] + 1);
2845 mode->VTotal = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 28] + 1);
2846 mode->Flags |= (fptable[modeofs + 30] & 0x10) ? V_PHSYNC : V_NHSYNC;
2847 mode->Flags |= (fptable[modeofs + 30] & 0x1) ? V_PVSYNC : V_NVSYNC;
2850 * bytes 1-2 are "panel type", including bits on whether Colour/mono, single/dual link, and type (TFT etc.)
2851 * bytes 3-6 are bits per colour in RGBX
2853 * 13-14 is HValid Start
2854 * 15-16 is HValid End
2855 * bytes 38-39 relate to spread spectrum settings
2856 * bytes 40-43 are something to do with PWM */
2858 mode->prev = mode->next = NULL;
2859 mode->status = MODE_OK;
2860 mode->type = M_T_DRIVER | M_T_PREFERRED;
2861 xf86SetModeDefaultName(mode);
2863 // if (XF86_CRTC_CONFIG_PTR(pScrn)->debug_modes) {
2864 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2865 "Found flat panel mode in BIOS tables:\n");
2866 xf86PrintModeline(pScrn->scrnIndex, mode);
2869 bios->fp.native_mode = mode;
2872 static void parse_lvds_manufacturer_table_init(ScrnInfoPtr pScrn, bios_t *bios, struct fppointers *fpp)
2874 /* The LVDS table changed considerably with BIT bioses. Previously
2875 * there was a header of version and record length, followed by several
2876 * records, indexed by a seperate xlat table, indexed in turn by the fp
2877 * strap in EXTDEV_BOOT. Each record had a config byte, followed by 6
2878 * script numbers for use by INIT_SUB which controlled panel init and
2879 * power, and finally a dword of ms to sleep between power off and on
2882 * The BIT LVDS table has the typical BIT table header: version byte,
2883 * header length byte, record length byte, and a byte for the maximum
2884 * number of records that can be held in the table. At byte 5 in the
2885 * header is the dual-link transition pxclk (in 10s kHz) - if straps
2886 * are not being used for the panel, this specifies the frequency at
2887 * which modes should be set up in the dual link style.
2889 * The table following the header serves as an integrated config and
2890 * xlat table: the records in the table are indexed by the FP strap
2891 * nibble in EXTDEV_BOOT, and each record has two bytes - the first as
2892 * a config byte, the second for indexing the fp mode table pointed to
2893 * by the BIT 'D' table
2896 unsigned int fpstrapping, lvdsmanufacturerindex = 0;
2897 uint8_t lvds_ver, headerlen, recordlen;
2899 fpstrapping = (nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
2901 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
2902 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2903 "Pointer to LVDS manufacturer table invalid\n");
2907 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
2909 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2910 "Found LVDS manufacturer table revision %d.%d\n",
2911 lvds_ver >> 4, lvds_ver & 0xf);
2914 case 0x0a: /* pre NV40 */
2915 lvdsmanufacturerindex = bios->data[fpp->fpxlatemanufacturertableptr + fpstrapping];
2918 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
2921 case 0x30: /* NV4x */
2922 lvdsmanufacturerindex = fpstrapping;
2923 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
2924 if (headerlen < 0x1f) {
2925 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2926 "LVDS table header not understood\n");
2929 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
2931 case 0x40: /* It changed again with gf8 :o( */
2933 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2934 "LVDS table revision not currently supported\n");
2938 uint16_t lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + headerlen + recordlen * lvdsmanufacturerindex;
2941 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
2942 bios->fp.dual_link = bios->data[lvdsofs] & 4;
2943 bios->fp.if_is_18bit = !(bios->data[lvdsofs] & 16);
2946 /* no sign of the "reset for panel on" bit, but it's safer to assume we should */
2947 bios->fp.reset_after_pclk_change = TRUE;
2948 bios->fp.dual_link = bios->data[lvdsofs] & 1;
2949 bios->fp.BITbit1 = bios->data[lvdsofs] & 2;
2950 /* BMP likely has something like this, but I have no dump to point to where it is */
2951 bios->fp.duallink_transition_clk = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
2952 fpp->fpxlatetableptr = bios->fp.lvdsmanufacturerpointer + headerlen + 1;
2953 fpp->xlatwidth = recordlen;
2958 void run_tmds_table(ScrnInfoPtr pScrn, int dcb_entry, int head, int pxclk)
2960 /* the dcb_entry parameter is the index of the appropriate DCB entry
2961 * the pxclk parameter is in kHz
2963 * This runs the TMDS regs setting code found on BIT bios cards
2965 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
2966 * ffs(or) == 3, use the second.
2969 NVPtr pNv = NVPTR(pScrn);
2970 bios_t *bios = &pNv->VBIOS;
2971 uint16_t clktable = 0, scriptptr;
2973 if (pNv->dcb_table.entry[dcb_entry].location) /* off chip */
2976 switch (ffs(pNv->dcb_table.entry[dcb_entry].or)) {
2978 clktable = bios->tmds.output0_script_ptr;
2982 clktable = bios->tmds.output1_script_ptr;
2987 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Pixel clock comparison table not found\n");
2991 scriptptr = clkcmptable(bios, clktable, pxclk);
2994 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TMDS output init script not found\n");
2998 rundigitaloutscript(pScrn, scriptptr, head, dcb_entry);
3001 static void parse_bios_version(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset)
3003 /* offset + 0 (8 bits): Micro version
3004 * offset + 1 (8 bits): Minor version
3005 * offset + 2 (8 bits): Chip version
3006 * offset + 3 (8 bits): Major version
3009 bios->major_version = bios->data[offset + 3];
3010 bios->chip_version = bios->data[offset + 2];
3011 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Bios version %02x.%02x.%02x.%02x\n",
3012 bios->data[offset + 3], bios->data[offset + 2],
3013 bios->data[offset + 1], bios->data[offset]);
3016 Bool get_pll_limits_reg(ScrnInfoPtr pScrn, enum pll_types plltype, uint32_t *reg)
3019 * Here we just try to find a register matching plltype in the PLL
3020 * limits table. The table is better explained in get_pll_limits below.
3023 bios_t *bios = &NVPTR(pScrn)->VBIOS;
3024 uint8_t pll_lim_ver = 0;
3026 if (!bios->pll_limit_tbl_ptr) {
3027 if (bios->chip_version >= 0x40 || bios->chip_version == 0x31 || bios->chip_version == 0x36) {
3028 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Pointer to PLL limits table invalid\n");
3032 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
3037 switch (pll_lim_ver) {
3044 uint8_t headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
3045 uint8_t recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
3046 uint8_t entries = bios->data[bios->pll_limit_tbl_ptr + 3];
3047 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
3050 for (i = 1; i < entries; i++) {
3051 uint32_t cmpreg = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + recordlen * i])));
3053 if (plltype == VPLL1 && (cmpreg == 0x680508 || cmpreg == 0x4010))
3055 if (plltype == VPLL2 && (cmpreg == 0x680520 || cmpreg == 0x4018))
3061 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
3062 "PLL limits table revision not currently supported\n");
3069 Bool get_pll_limits(ScrnInfoPtr pScrn, uint32_t reg, struct pll_lims *pll_lim)
3073 * Version 0x10: NV31
3074 * One byte header (version), one record of 24 bytes
3075 * Version 0x11: NV36 - Not implemented
3076 * Seems to have same record style as 0x10, but 3 records rather than 1
3077 * Version 0x20: Found on Geforce 6 cards
3078 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
3079 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
3080 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record length
3083 bios_t *bios = &NVPTR(pScrn)->VBIOS;
3084 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
3085 int pllindex = 0, i;
3086 uint32_t crystal_straps;
3088 if (!bios->pll_limit_tbl_ptr) {
3089 if (bios->chip_version >= 0x40 || bios->chip_version == 0x31 || bios->chip_version == 0x36) {
3090 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Pointer to PLL limits table invalid\n");
3094 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
3096 if (DEBUGLEVEL >= 6)
3097 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3098 "Found PLL limits table version 0x%X\n", pll_lim_ver);
3101 uint32_t crystal_strap_mask = 1 << 6;
3102 /* open coded pNv->twoHeads test */
3103 if (bios->chip_version > 0x10 && bios->chip_version != 0x15 &&
3104 bios->chip_version != 0x1a && bios->chip_version != 0x20)
3105 crystal_strap_mask |= 1 << 22;
3106 crystal_straps = nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) & crystal_strap_mask;
3108 switch (pll_lim_ver) {
3109 /* we use version 0 to indicate a pre limit table bios (single stage pll)
3110 * and load the hard coded limits instead */
3121 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
3122 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
3123 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
3126 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3127 "PLL limits table revision not currently supported\n");
3131 /* initialize all members to zero */
3132 memset (pll_lim, 0, sizeof(struct pll_lims));
3134 if (pll_lim_ver == 0) {
3135 pll_lim->vco1.minfreq = bios->fminvco;
3136 pll_lim->vco1.maxfreq = bios->fmaxvco;
3137 pll_lim->vco1.min_n = 0x1;
3138 pll_lim->vco1.max_n = 0xff;
3139 /* nv_hw.c in nv driver uses 7 and 8 for minM */
3140 pll_lim->vco1.min_m = 0x1;
3141 if (crystal_straps == 0)
3142 pll_lim->vco1.max_m = 0xd;
3144 pll_lim->vco1.max_m = 0xe;
3145 pll_lim->vco1.min_inputfreq = 0;
3146 pll_lim->vco1.max_inputfreq = INT_MAX;
3147 } else if (pll_lim_ver == 0x10) {
3148 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex;
3150 pll_lim->vco1.minfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs])));
3151 pll_lim->vco1.maxfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 4])));
3152 pll_lim->vco2.minfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 8])));
3153 pll_lim->vco2.maxfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 12])));
3154 pll_lim->vco1.min_inputfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 16])));
3155 pll_lim->vco2.min_inputfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 20])));
3156 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
3158 /* these values taken from nv31. nv30, nv36 might do better with different ones */
3159 pll_lim->vco1.min_n = 0x1;
3160 pll_lim->vco1.max_n = 0xff;
3161 pll_lim->vco1.min_m = 0x1;
3162 pll_lim->vco1.max_m = 0xd;
3163 pll_lim->vco2.min_n = 0x4;
3164 pll_lim->vco2.max_n = 0x46;
3165 if (bios->chip_version == 0x30)
3166 /* only 5 bits available for N2 on nv30 */
3167 pll_lim->vco2.max_n = 0x1f;
3168 if (bios->chip_version == 0x31)
3169 /* on nv31, N2 is compared to maxN2 (0x46) and maxM2 (0x4),
3170 * so set maxN2 to 0x4 and save a comparison
3172 pll_lim->vco2.max_n = 0x4;
3173 pll_lim->vco2.min_m = 0x1;
3174 pll_lim->vco2.max_m = 0x4;
3175 } else { /* ver 0x20, 0x21 */
3176 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
3178 /* first entry is default match, if nothing better. warn if reg field nonzero */
3179 if (le32_to_cpu(*((uint32_t *)&bios->data[plloffs])))
3180 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
3181 "Default PLL limit entry has non-zero register field\n");
3183 for (i = 1; i < entries; i++)
3184 if (le32_to_cpu(*((uint32_t *)&bios->data[plloffs + recordlen * i])) == reg) {
3189 plloffs += recordlen * pllindex;
3191 if (DEBUGLEVEL >= 6)
3192 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Loading PLL limits for reg 0x%08x\n",
3193 pllindex ? reg : 0);
3195 /* frequencies are stored in tables in MHz, kHz are more useful, so we convert */
3197 /* What output frequencies can each VCO generate? */
3198 pll_lim->vco1.minfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 4]))) * 1000;
3199 pll_lim->vco1.maxfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 6]))) * 1000;
3200 pll_lim->vco2.minfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 8]))) * 1000;
3201 pll_lim->vco2.maxfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 10]))) * 1000;
3203 /* What input frequencies do they accept (past the m-divider)? */
3204 pll_lim->vco1.min_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 12]))) * 1000;
3205 pll_lim->vco2.min_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 14]))) * 1000;
3206 pll_lim->vco1.max_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 16]))) * 1000;
3207 pll_lim->vco2.max_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 18]))) * 1000;
3209 /* What values are accepted as multiplier and divider? */
3210 pll_lim->vco1.min_n = bios->data[plloffs + 20];
3211 pll_lim->vco1.max_n = bios->data[plloffs + 21];
3212 pll_lim->vco1.min_m = bios->data[plloffs + 22];
3213 pll_lim->vco1.max_m = bios->data[plloffs + 23];
3214 pll_lim->vco2.min_n = bios->data[plloffs + 24];
3215 pll_lim->vco2.max_n = bios->data[plloffs + 25];
3216 pll_lim->vco2.min_m = bios->data[plloffs + 26];
3217 pll_lim->vco2.max_m = bios->data[plloffs + 27];
3219 pll_lim->unk1c = bios->data[plloffs + 28];
3220 pll_lim->max_log2p_bias = bios->data[plloffs + 29];
3221 pll_lim->log2p_bias = bios->data[plloffs + 30];
3223 if (recordlen > 0x22)
3224 pll_lim->refclk = le32_to_cpu(*((uint32_t *)&bios->data[plloffs + 31]));
3227 if (!pll_lim->refclk)
3228 switch (crystal_straps) {
3230 pll_lim->refclk = 13500;
3233 pll_lim->refclk = 14318;
3236 pll_lim->refclk = 27000;
3238 case (1 << 22 | 1 << 6):
3239 pll_lim->refclk = 25000;
3243 #if 1 /* for easy debugging */
3244 ErrorF("pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
3245 ErrorF("pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
3246 ErrorF("pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
3247 ErrorF("pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
3249 ErrorF("pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
3250 ErrorF("pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
3251 ErrorF("pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
3252 ErrorF("pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
3254 ErrorF("pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
3255 ErrorF("pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
3256 ErrorF("pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
3257 ErrorF("pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
3258 ErrorF("pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
3259 ErrorF("pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
3260 ErrorF("pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
3261 ErrorF("pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
3263 ErrorF("pll.unk1c: %d\n", pll_lim->unk1c);
3264 ErrorF("pll.max_log2p_bias: %d\n", pll_lim->max_log2p_bias);
3265 ErrorF("pll.log2p_bias: %d\n", pll_lim->log2p_bias);
3267 ErrorF("pll.refclk: %d\n", pll_lim->refclk);
3273 static int parse_bit_B_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3275 /* offset + 0 (32 bits): BIOS version dword
3277 * There's a bunch of bits in this table other than the bios version
3278 * that we don't use - their use currently unknown
3281 if (bitentry->length < 0x4) {
3282 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3283 "Do not understand B table entry\n");
3287 parse_bios_version(pScrn, bios, bitentry->offset);
3292 static int parse_bit_C_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3294 /* offset + 8 (16 bits): PLL limits table pointer
3296 * There's more in here, but that's unknown.
3299 if (bitentry->length < 10) {
3300 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Do not understand C table entry\n");
3304 bios->pll_limit_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 8])));
3309 static int parse_bit_display_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry, struct fppointers *fpp)
3311 /* Parses the flat panel table segment that the bit entry points to.
3312 * Starting at bitentry->offset:
3314 * offset + 0 (16 bits): FIXME table pointer
3315 * offset + 2 (16 bits): mode table pointer
3318 if (bitentry->length != 4) {
3319 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3320 "Do not understand BIT display table entry\n");
3324 fpp->fptablepointer = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 2])));
3329 static unsigned int parse_bit_init_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3331 /* Parses the init table segment that the bit entry points to.
3332 * Starting at bitentry->offset:
3334 * offset + 0 (16 bits): init script tables pointer
3335 * offset + 2 (16 bits): macro index table pointer
3336 * offset + 4 (16 bits): macro table pointer
3337 * offset + 6 (16 bits): condition table pointer
3338 * offset + 8 (16 bits): io condition table pointer
3339 * offset + 10 (16 bits): io flag condition table pointer
3340 * offset + 12 (16 bits): init function table pointer
3344 if (bitentry->length < 14) {
3345 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3346 "Unable to recognize BIT init table entry\n");
3350 bios->init_script_tbls_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
3351 bios->macro_index_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 2])));
3352 bios->macro_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 4])));
3353 bios->condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 6])));
3354 bios->io_condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 8])));
3355 bios->io_flag_condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 10])));
3356 bios->init_function_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 12])));
3361 static int parse_bit_i_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3363 /* offset + 13 (16 bits): pointer to table containing DAC load detection comparison values
3365 * There's other things in this table, purpose unknown
3370 if (bitentry->length < 15) {
3371 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3372 "BIT i table not long enough for DAC load detection comparison table\n");
3376 offset = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 13])));
3378 /* doesn't exist on g80 */
3382 /* The first value in the table, following the header, is the comparison value
3383 * Purpose of subsequent values unknown - TV load detection?
3386 uint8_t version = bios->data[offset];
3388 if (version != 0x00 && version != 0x10) {
3389 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
3390 "DAC load detection comparison table version %d.%d not known\n",
3391 version >> 4, version & 0xf);
3395 uint8_t headerlen = bios->data[offset + 1];
3397 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3398 "DAC load detection comparison table version %x found\n", version);
3400 bios->dactestval = le32_to_cpu(*((uint32_t *)(&bios->data[offset + headerlen])));
3405 static int parse_bit_lvds_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry, struct fppointers *fpp)
3407 /* Parses the LVDS table segment that the bit entry points to.
3408 * Starting at bitentry->offset:
3410 * offset + 0 (16 bits): LVDS strap xlate table pointer
3413 if (bitentry->length != 2) {
3414 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3415 "Do not understand BIT LVDS table entry\n");
3419 /* no idea if it's still called the LVDS manufacturer table, but the concept's close enough */
3420 bios->fp.lvdsmanufacturerpointer = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
3422 parse_lvds_manufacturer_table_init(pScrn, bios, fpp);
3427 static int parse_bit_M_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3429 /* offset + 2 (8 bits): number of options in an INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
3430 * offset + 3 (16 bits): pointer to strap xlate table for RAM restrict option selection
3432 * There's a bunch of bits in this table other than the RAM restrict
3433 * stuff that we don't use - their use currently unknown
3438 /* Older bios versions don't have a sufficiently long table for what we want */
3439 if (bitentry->length < 0x5)
3442 /* set up multiplier for INIT_RAM_RESTRICT_ZM_REG_GROUP */
3443 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != 0x8f); i++)
3445 itbl_entry[i].length_multiplier = bios->data[bitentry->offset + 2] * 4;
3446 init_ram_restrict_zm_reg_group_blocklen = itbl_entry[i].length_multiplier;
3448 bios->ram_restrict_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 3])));
3453 static int parse_bit_tmds_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3455 /* Parses the pointer to the TMDS table
3457 * Starting at bitentry->offset:
3459 * offset + 0 (16 bits): TMDS table pointer
3461 * The TMDS table is typically found just before the DCB table, with a
3462 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
3465 * At offset +7 is a pointer to a script, which I don't know how to run yet
3466 * At offset +9 is a pointer to another script, likewise
3467 * Offset +11 has a pointer to a table where the first word is a pxclk
3468 * frequency and the second word a pointer to a script, which should be
3469 * run if the comparison pxclk frequency is less than the pxclk desired.
3470 * This repeats for decreasing comparison frequencies
3471 * Offset +13 has a pointer to a similar table
3472 * The selection of table (and possibly +7/+9 script) is dictated by
3473 * "or" from the DCB.
3476 uint16_t tmdstableptr, script1, script2;
3478 if (bitentry->length != 2) {
3479 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3480 "Do not understand BIT TMDS table entry\n");
3484 tmdstableptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
3486 if (tmdstableptr == 0x0) {
3487 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Pointer to TMDS table invalid\n");
3491 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Found TMDS table revision %d.%d\n",
3492 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
3494 /* These two scripts are odd: they don't seem to get run even when they are not stubbed */
3495 script1 = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 7]));
3496 script2 = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 9]));
3497 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
3498 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TMDS table script pointers not stubbed\n");
3500 bios->tmds.output0_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 11]));
3501 bios->tmds.output1_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 13]));
3506 static void parse_bit_structure(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset)
3508 bit_entry_t bitentry;
3510 struct fppointers fpp;
3511 NVPtr pNv = NVPTR(pScrn);
3513 memset(&fpp, 0, sizeof(struct fppointers));
3516 bitentry.id[0] = bios->data[offset];
3517 bitentry.id[1] = bios->data[offset + 1];
3518 bitentry.length = le16_to_cpu(*((uint16_t *)&bios->data[offset + 2]));
3519 bitentry.offset = le16_to_cpu(*((uint16_t *)&bios->data[offset + 4]));
3521 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3522 "0x%04X: Found BIT command with id 0x%02X (%c)\n",
3523 offset, bitentry.id[0], bitentry.id[0]);
3525 switch (bitentry.id[0]) {
3527 /* id[0] = 0 and id[1] = 0 ==> end of BIT struture */
3528 if (bitentry.id[1] == 0)
3532 parse_bit_B_tbl_entry(pScrn, bios, &bitentry);
3535 parse_bit_C_tbl_entry(pScrn, bios, &bitentry);
3538 parse_bit_display_tbl_entry(pScrn, bios, &bitentry, &fpp);
3541 parse_bit_init_tbl_entry(pScrn, bios, &bitentry);
3544 parse_bit_i_tbl_entry(pScrn, bios, &bitentry);
3547 parse_bit_lvds_tbl_entry(pScrn, bios, &bitentry, &fpp);
3549 case 'M': /* memory? */
3550 parse_bit_M_tbl_entry(pScrn, bios, &bitentry);
3553 parse_bit_tmds_tbl_entry(pScrn, bios, &bitentry);
3557 offset += sizeof(bit_entry_t);
3560 /* C and M tables have to be parsed before init can run */
3561 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3562 "Parsing previously deferred init table entry\n");
3563 parse_init_tables(pScrn, bios);
3565 /* If it's not a laptop, you probably don't care about LVDS */
3566 /* FIXME: detect mobile BIOS? */
3570 /* Need D and L tables parsed before doing this */
3571 parse_fp_mode_table(pScrn, bios, &fpp);
3574 static void parse_bmp_structure(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset)
3576 /* Parse the BMP structure for useful things
3578 * offset + 5: BMP major version
3579 * offset + 6: BMP minor version
3580 * offset + 10: BCD encoded BIOS version
3582 * offset + 18: init script table pointer (for bios versions < 5.10h)
3583 * offset + 20: extra init script table pointer (for bios versions < 5.10h)
3585 * offset + 24: FIXME
3586 * offset + 26: FIXME
3587 * offset + 28: FIXME
3589 * offset + 54: index of I2C CRTC pair to use for CRT output
3590 * offset + 55: index of I2C CRTC pair to use for TV output
3591 * offset + 56: index of I2C CRTC pair to use for flat panel output
3592 * offset + 58: write CRTC index for I2C pair 0
3593 * offset + 59: read CRTC index for I2C pair 0
3594 * offset + 60: write CRTC index for I2C pair 1
3595 * offset + 61: read CRTC index for I2C pair 1
3597 * offset + 67: maximum internal PLL frequency (single stage PLL)
3598 * offset + 71: minimum internal PLL frequency (single stage PLL)
3600 * offset + 75: script table pointers, as for parse_bit_init_tbl_entry
3602 * offset + 89: TMDS single link output A table pointer
3603 * offset + 91: TMDS single link output B table pointer
3604 * offset + 105: flat panel timings table pointer
3605 * offset + 107: flat panel strapping translation table pointer
3606 * offset + 117: LVDS manufacturer panel config table pointer
3607 * offset + 119: LVDS manufacturer strapping translation table pointer
3609 * offset + 142: PLL limits table pointer
3612 NVPtr pNv = NVPTR(pScrn);
3614 struct fppointers fpp;
3615 memset(&fpp, 0, sizeof(struct fppointers));
3617 uint8_t bmp_version_major = bios->data[offset + 5];
3618 uint8_t bmp_version_minor = bios->data[offset + 6];
3620 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BMP version %d.%d\n",
3621 bmp_version_major, bmp_version_minor);
3623 /* version 6 could theoretically exist, but I suspect BIT happened instead */
3624 if (bmp_version_major < 2 || bmp_version_major > 5) {
3625 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "You have an unsupported BMP version. Please send in your bios\n");
3629 if (bmp_version_major == 2)
3630 bmplength = 48; /* exact for 2.01 - not sure if minor version used in versions < 5 */
3631 else if (bmp_version_major == 3)
3632 bmplength = 54; /* guessed - mem init tables added in this version */
3633 else if (bmp_version_major == 4 || bmp_version_minor < 0x1) /* don't know if 5.0 exists... */
3634 bmplength = 62; /* guessed - BMP I2C indices added in version 4*/
3635 else if (bmp_version_minor < 0x6)
3636 bmplength = 67; /* exact for 5.01 */
3637 else if (bmp_version_minor < 0x10)
3638 bmplength = 75; /* exact for 5.06 */
3639 else if (bmp_version_minor == 0x10)
3640 bmplength = 89; /* exact for 5.10h */
3641 else if (bmp_version_minor < 0x14)
3642 bmplength = 118; /* exact for 5.11h */
3643 else if (bmp_version_minor < 0x24) /* not sure of version where pll limits came in;
3644 * certainly exist by 0x24 though */
3645 /* length not exact: this is long enough to get lvds members */
3648 /* length not exact: this is long enough to get pll limit member */
3652 if (nv_cksum(bios->data + offset, 8)) {
3653 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Bad BMP checksum\n");
3657 parse_bios_version(pScrn, bios, offset + 10);
3659 bios->init_script_tbls_ptr = le16_to_cpu(*(uint16_t *)&bios->data[offset + 18]);
3660 bios->extra_init_script_tbl_ptr = le16_to_cpu(*(uint16_t *)&bios->data[offset + 20]);
3663 // FIXME needed for pre v16? - haiku uses this in its COMPUTE_MEM on early biosen
3664 if (bmp_version_major > 2) {
3665 uint16_t meminittbl = le16_to_cpu(*(uint16_t *)&bios->data[offset + 24]);
3666 uint16_t sdrmemseqtbl = le16_to_cpu(*(uint16_t *)&bios->data[offset + 26]);
3667 uint16_t ddrmemseqtbl = le16_to_cpu(*(uint16_t *)&bios->data[offset + 28]);
3671 uint16_t legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
3673 legacy_i2c_offset = offset + 54;
3674 bios->legacy_i2c_indices.crt = bios->data[legacy_i2c_offset];
3675 bios->legacy_i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
3676 bios->legacy_i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
3677 pNv->dcb_table.i2c_write[0] = bios->data[legacy_i2c_offset + 4];
3678 pNv->dcb_table.i2c_read[0] = bios->data[legacy_i2c_offset + 5];
3679 pNv->dcb_table.i2c_write[1] = bios->data[legacy_i2c_offset + 6];
3680 pNv->dcb_table.i2c_read[1] = bios->data[legacy_i2c_offset + 7];
3682 if (bmplength > 74) {
3683 bios->fmaxvco = le32_to_cpu(*((uint32_t *)&bios->data[offset + 67]));
3684 bios->fminvco = le32_to_cpu(*((uint32_t *)&bios->data[offset + 71]));
3686 bios->fmaxvco = 256000;
3687 bios->fminvco = 128000;
3689 if (bmplength > 88) {
3690 bit_entry_t initbitentry;
3691 initbitentry.length = 14;
3692 initbitentry.offset = offset + 75;
3693 parse_bit_init_tbl_entry(pScrn, bios, &initbitentry);
3695 if (bmplength > 92) {
3696 bios->tmds.output0_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[offset + 89]));
3697 bios->tmds.output1_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[offset + 91]));
3699 if (bmplength > 108) {
3700 fpp.fptablepointer = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 105])));
3701 fpp.fpxlatetableptr = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 107])));
3704 if (bmplength > 120) {
3705 bios->fp.lvdsmanufacturerpointer = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 117])));
3706 fpp.fpxlatemanufacturertableptr = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 119])));
3708 if (bmplength > 143)
3709 bios->pll_limit_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 142])));
3711 /* want pll_limit_tbl_ptr set (if available) before init is run */
3712 if (bmp_version_major < 5 || bmp_version_minor < 0x10) {
3713 init_exec_t iexec = {TRUE, FALSE};
3714 if (bios->init_script_tbls_ptr)
3715 parse_init_table(pScrn, bios, bios->init_script_tbls_ptr, &iexec);
3716 if (bios->extra_init_script_tbl_ptr)
3717 parse_init_table(pScrn, bios, bios->extra_init_script_tbl_ptr, &iexec);
3719 parse_init_tables(pScrn, bios);
3721 /* If it's not a laptop, you probably don't care about fptables */
3722 /* FIXME: detect mobile BIOS? */
3726 parse_fp_mode_table(pScrn, bios, &fpp);
3727 parse_lvds_manufacturer_table_init(pScrn, bios, &fpp);
3728 /* I've never seen a valid LVDS_INIT script, so we'll do a test for it here */
3729 call_lvds_script(pScrn, 0, 0, LVDS_INIT, 0);
3732 static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
3736 for (i = 0; i <= (n - len); i++) {
3737 for (j = 0; j < len; j++)
3738 if (data[i + j] != str[j])
3747 static Bool parse_dcb_entry(ScrnInfoPtr pScrn, uint8_t dcb_version, uint32_t conn, uint32_t conf, struct dcb_entry *entry)
3749 NVPtr pNv = NVPTR(pScrn);
3751 memset(entry, 0, sizeof (struct dcb_entry));
3753 /* safe defaults for a crt */
3755 entry->i2c_index = 0;
3758 entry->location = 0;
3760 entry->duallink_possible = FALSE;
3762 if (dcb_version >= 0x20) {
3763 entry->type = conn & 0xf;
3764 entry->i2c_index = (conn >> 4) & 0xf;
3765 entry->heads = (conn >> 8) & 0xf;
3766 entry->bus = (conn >> 16) & 0xf;
3767 entry->location = (conn >> 20) & 0xf;
3768 entry->or = (conn >> 24) & 0xf;
3769 /* Normal entries consist of a single bit, but dual link has the
3770 * adjacent more significant bit set too
3772 if ((1 << (ffs(entry->or) - 1)) * 3 == entry->or)
3773 entry->duallink_possible = TRUE;
3775 switch (entry->type) {
3777 if (conf & 0xfffffffa)
3778 ErrorF("Unknown LVDS configuration bits, please report\n");
3780 entry->lvdsconf.use_straps_for_mode = TRUE;
3782 entry->lvdsconf.use_power_scripts = TRUE;
3785 } else if (dcb_version >= 0x14 ) {
3786 if (conn != 0xf0003f00 && conn != 0xf2204301 && conn != 0xf2045f14 && conn != 0xf2205004 && conn != 0xf2208001 && conn != 0xf4204011) {
3787 ErrorF("Unknown DCB 1.4 / 1.5 entry, please report\n");
3788 /* cause output setting to fail, so message is seen */
3789 pNv->dcb_table.entries = 0;
3792 /* most of the below is a "best guess" atm */
3793 entry->type = conn & 0xf;
3794 if (entry->type == 4) { /* digital */
3796 entry->type = OUTPUT_LVDS;
3798 entry->type = OUTPUT_TMDS;
3800 /* what's in bits 5-13? could be some brooktree/chrontel/philips thing, in tv case */
3801 entry->i2c_index = (conn >> 14) & 0xf;
3802 /* raw heads field is in range 0-1, so move to 1-2 */
3803 entry->heads = ((conn >> 18) & 0x7) + 1;
3804 entry->location = (conn >> 21) & 0xf;
3805 entry->bus = (conn >> 25) & 0x7;
3806 /* set or to be same as heads -- hopefully safe enough */
3807 entry->or = entry->heads;
3809 switch (entry->type) {
3811 /* these are probably buried in conn's unknown bits */
3812 entry->lvdsconf.use_straps_for_mode = TRUE;
3813 entry->lvdsconf.use_power_scripts = TRUE;
3816 /* invent a DVI-A output, by copying the fields of the DVI-D output
3817 * reported to work by math_b on an NV20(!) */
3818 memcpy(&entry[1], &entry[0], sizeof(struct dcb_entry));
3819 entry[1].type = OUTPUT_ANALOG;
3820 pNv->dcb_table.entries++;
3822 } else if (dcb_version >= 0x12) {
3823 /* use the defaults for a crt
3824 * v1.2 tables often have other entries though - need a trace
3826 entry->type = conn & 0xf; // this is valid, but will probably confuse the randr stuff
3828 } else { /* pre DCB / v1.1 - use the safe defaults for a crt */
3829 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3830 "No information in BIOS output table; assuming a CRT output exists\n");
3831 entry->i2c_index = pNv->VBIOS.legacy_i2c_indices.crt;
3834 pNv->dcb_table.entries++;
3840 read_dcb_i2c_table(ScrnInfoPtr pScrn, bios_t *bios, uint8_t dcb_version, uint16_t i2ctabptr)
3842 NVPtr pNv = NVPTR(pScrn);
3844 uint8_t headerlen = 0;
3846 int recordoffset = 0, rdofs = 1, wrofs = 0;
3849 i2c_entries = MAX_NUM_DCB_ENTRIES;
3850 memset(pNv->dcb_table.i2c_read, 0, sizeof(pNv->dcb_table.i2c_read));
3851 memset(pNv->dcb_table.i2c_write, 0, sizeof(pNv->dcb_table.i2c_write));
3853 i2ctable = &bios->data[i2ctabptr];
3855 if (dcb_version >= 0x30) {
3856 if (i2ctable[0] != dcb_version) { /* necessary? */
3857 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3858 "DCB I2C table version mismatch (%02X vs %02X)\n",
3859 i2ctable[0], dcb_version);
3862 headerlen = i2ctable[1];
3863 i2c_entries = i2ctable[2];
3864 if (i2ctable[0] >= 0x40) {
3865 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3866 "G80 DCB I2C table detected, arrgh\n"); /* they're plain weird */
3870 /* it's your own fault if you call this function on a DCB 1.1 BIOS --
3871 * the below assumes DCB 1.2
3873 if (dcb_version < 0x14) {
3879 for (i = 0; i < i2c_entries; i++)
3880 if (i2ctable[headerlen + 4 * i + 3] != 0xff) {
3881 pNv->dcb_table.i2c_read[i] = i2ctable[headerlen + recordoffset + rdofs + 4 * i];
3882 pNv->dcb_table.i2c_write[i] = i2ctable[headerlen + recordoffset + wrofs + 4 * i];
3886 static unsigned int parse_dcb_table(ScrnInfoPtr pScrn, bios_t *bios)
3888 NVPtr pNv = NVPTR(pScrn);
3889 uint16_t dcbptr, i2ctabptr = 0;
3891 uint8_t dcb_version, headerlen = 0x4, entries = MAX_NUM_DCB_ENTRIES;
3892 Bool configblock = TRUE;
3893 int recordlength = 8, confofs = 4;
3896 pNv->dcb_table.entries = 0;
3898 /* get the offset from 0x36 */
3899 dcbptr = le16_to_cpu(*(uint16_t *)&bios->data[0x36]);
3901 if (dcbptr == 0x0) {
3902 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3903 "No Display Configuration Block pointer found\n");
3904 /* this situation likely means a really old card, pre DCB, so we'll add the safe CRT entry */
3905 parse_dcb_entry(pScrn, 0, 0, 0, &pNv->dcb_table.entry[0]);
3909 dcbtable = &bios->data[dcbptr];
3911 /* get DCB version */
3912 dcb_version = dcbtable[0];
3913 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3914 "Display Configuration Block version %d.%d found\n",
3915 dcb_version >> 4, dcb_version & 0xf);
3917 if (dcb_version >= 0x20) { /* NV17+ */
3920 if (dcb_version >= 0x30) { /* NV40+ */
3921 headerlen = dcbtable[1];
3922 entries = dcbtable[2];
3923 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[4]);
3924 sig = le32_to_cpu(*(uint32_t *)&dcbtable[6]);
3926 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3927 "DCB header length %02X, with %02X possible entries\n",
3928 headerlen, entries);
3930 /* dcb_block_count = *(dcbtable[1]); */
3931 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
3932 sig = le32_to_cpu(*(uint32_t *)&dcbtable[4]);
3936 if (sig != 0x4edcbdcb) {
3937 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3938 "Bad Display Configuration Block signature (%08X)\n", sig);
3941 } else if (dcb_version >= 0x14) { /* some NV15/16, and NV11+ */
3945 strncpy(sig, (char *)&dcbtable[-7], 7);
3946 /* dcb_block_count = *(dcbtable[1]); */
3947 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
3951 if (strcmp(sig, "DEV_REC")) {
3952 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3953 "Bad Display Configuration Block signature (%s)\n", sig);
3956 } else if (dcb_version >= 0x12) { /* some NV6/10, and NV15+ */
3957 /* dcb_block_count = *(dcbtable[1]); */
3958 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
3959 configblock = FALSE;
3960 } else { /* NV5+, maybe NV4 */
3961 /* DCB 1.1 seems to be quite unhelpful - we'll just add the safe CRT entry */
3962 parse_dcb_entry(pScrn, dcb_version, 0, 0, &pNv->dcb_table.entry[0]);
3966 if (entries >= MAX_NUM_DCB_ENTRIES)
3967 entries = MAX_NUM_DCB_ENTRIES;
3969 for (i = 0; i < entries; i++) {
3970 uint32_t connection, config = 0;
3972 connection = le32_to_cpu(*(uint32_t *)&dcbtable[headerlen + recordlength * i]);
3974 config = le32_to_cpu(*(uint32_t *)&dcbtable[headerlen + confofs + recordlength * i]);
3976 /* Should we allow discontinuous DCBs? Certainly DCB I2C tables
3977 * can be discontinuous */
3978 if ((connection & 0x0000000f) == 0x0000000f) /* end of records */
3981 ErrorF("Raw DCB entry %d: %08x %08x\n", i, connection, config);
3982 if (!parse_dcb_entry(pScrn, dcb_version, connection, config, &pNv->dcb_table.entry[pNv->dcb_table.entries]))
3986 read_dcb_i2c_table(pScrn, bios, dcb_version, i2ctabptr);
3988 /* DCB v2.0, in particular, lists each output combination separately.
3989 * Here we merge compatible entries to have fewer outputs, with more options
3991 for (i = 0; i < pNv->dcb_table.entries; i++) {
3992 struct dcb_entry *ient = &pNv->dcb_table.entry[i];
3995 for (j = i + 1; j < pNv->dcb_table.entries; j++) {
3996 struct dcb_entry *jent = &pNv->dcb_table.entry[j];
3998 if (jent->type == 100) /* already merged entry */
4001 if (jent->i2c_index == ient->i2c_index && jent->type == ient->type && jent->location == ient->location) {
4002 /* only merge heads field when output field is the same --
4003 * we could merge output field for same heads, but dual link,
4004 * the resultant need to make several merging passes, and lack
4005 * of applicable real life cases has deterred this so far
4007 if (jent->or == ient->or) {
4008 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
4009 "Merging DCB entries %d and %d\n", i, j);
4010 ient->heads |= jent->heads;
4011 jent->type = 100; /* dummy value */
4017 /* Compact entries merged into others out of dcb_table */
4019 for (i = 0; i < pNv->dcb_table.entries; i++) {
4020 if ( pNv->dcb_table.entry[i].type == 100 )
4023 if (newentries != i)
4024 memcpy(&pNv->dcb_table.entry[newentries], &pNv->dcb_table.entry[i], sizeof(struct dcb_entry));
4028 pNv->dcb_table.entries = newentries;
4030 return pNv->dcb_table.entries;
4033 static void load_nv17_hw_sequencer_ucode(ScrnInfoPtr pScrn, bios_t *bios, uint16_t hwsq_offset, int entry)
4035 /* BMP based cards, from NV17, need a microcode loading to correctly
4036 * control the GPIO etc for LVDS panels
4038 * BIT based cards seem to do this directly in the init scripts
4040 * The microcode entries are found by the "HWSQ" signature.
4041 * The header following has the number of entries, and the entry size
4043 * An entry consists of a dword to write to the sequencer control reg
4044 * (0x00001304), followed by the ucode bytes, written sequentially,
4045 * starting at reg 0x00001400
4048 uint8_t bytes_to_write;
4051 if (bios->data[hwsq_offset] <= entry) {
4052 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
4053 "Too few entries in HW sequencer table for requested entry\n");
4057 bytes_to_write = bios->data[hwsq_offset + 1];
4059 if (bytes_to_write != 36) {
4060 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown HW sequencer entry size\n");
4064 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Loading NV17 power sequencing microcode\n");
4066 uint16_t hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
4068 /* set sequencer control */
4069 nv32_wr(pScrn, 0x00001304, le32_to_cpu(*(uint32_t *)&bios->data[hwsq_entry_offset]));
4070 bytes_to_write -= 4;
4073 for (i = 0; i < bytes_to_write; i += 4)
4074 nv32_wr(pScrn, 0x00001400 + i, le32_to_cpu(*(uint32_t *)&bios->data[hwsq_entry_offset + i + 4]));
4076 /* twiddle 0x1098 */
4077 nv32_wr(pScrn, 0x00001098, nv32_rd(pScrn, 0x00001098) | 0x18);
4080 static void read_bios_edid(ScrnInfoPtr pScrn)
4082 bios_t *bios = &NVPTR(pScrn)->VBIOS;
4083 const uint8_t edid_sig[] = { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
4084 uint16_t offset = 0, newoffset;
4085 int searchlen = NV_PROM_SIZE, i;
4088 if (!(newoffset = findstr(&bios->data[offset], searchlen, edid_sig, 8)))
4090 offset += newoffset;
4091 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
4094 searchlen -= offset;
4098 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Found EDID in BIOS\n");
4100 bios->fp.edid = xalloc(EDID1_LEN);
4101 for (i = 0; i < EDID1_LEN; i++)
4102 bios->fp.edid[i] = bios->data[offset + i];
4105 Bool NVInitVBIOS(ScrnInfoPtr pScrn)
4107 NVPtr pNv = NVPTR(pScrn);
4109 memset(&pNv->VBIOS, 0, sizeof(bios_t));
4110 pNv->VBIOS.data = xalloc(NV_PROM_SIZE);
4112 if (!NVShadowVBIOS(pScrn, pNv->VBIOS.data)) {
4113 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4114 "No valid BIOS image found\n");
4115 xfree(pNv->VBIOS.data);
4119 pNv->VBIOS.length = pNv->VBIOS.data[2] * 512;
4120 if (pNv->VBIOS.length > NV_PROM_SIZE)
4121 pNv->VBIOS.length = NV_PROM_SIZE;
4126 Bool NVRunVBIOSInit(ScrnInfoPtr pScrn)
4128 NVPtr pNv = NVPTR(pScrn);
4129 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
4130 const uint8_t bit_signature[] = { 'B', 'I', 'T' };
4131 int offset, ret = 0;
4133 crtc_access(pScrn, ACCESS_UNLOCK);
4135 if ((offset = findstr(pNv->VBIOS.data, pNv->VBIOS.length, bit_signature, sizeof(bit_signature)))) {
4136 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BIT BIOS found\n");
4137 parse_bit_structure(pScrn, &pNv->VBIOS, offset + 4);
4138 } else if ((offset = findstr(pNv->VBIOS.data, pNv->VBIOS.length, bmp_signature, sizeof(bmp_signature)))) {
4139 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
4142 if ((hwsq_offset = findstr(pNv->VBIOS.data, pNv->VBIOS.length, hwsq_signature, sizeof(hwsq_signature))))
4143 /* always use entry 0? */
4144 load_nv17_hw_sequencer_ucode(pScrn, &pNv->VBIOS, hwsq_offset + sizeof(hwsq_signature), 0);
4146 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BMP BIOS found\n");
4147 parse_bmp_structure(pScrn, &pNv->VBIOS, offset);
4149 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
4150 "No known BIOS signature found\n");
4154 crtc_access(pScrn, ACCESS_LOCK);
4162 unsigned int NVParseBios(ScrnInfoPtr pScrn)
4164 NVPtr pNv = NVPTR(pScrn);
4165 uint32_t saved_nv_pextdev_boot_0;
4167 if (!NVInitVBIOS(pScrn))
4170 /* these will need remembering across a suspend */
4171 saved_nv_pextdev_boot_0 = nv32_rd(pScrn, NV_PEXTDEV_BOOT_0);
4172 saved_nv_pfb_cfg0 = nv32_rd(pScrn, NV_PFB_CFG0);
4174 pNv->VBIOS.execute = FALSE;
4176 nv32_wr(pScrn, NV_PEXTDEV_BOOT_0, saved_nv_pextdev_boot_0);
4178 if (!NVRunVBIOSInit(pScrn))
4181 if (parse_dcb_table(pScrn, &pNv->VBIOS))
4182 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
4183 "Found %d entries in DCB\n", pNv->dcb_table.entries);
4185 if (pNv->Mobile && !pNv->VBIOS.fp.native_mode)
4186 read_bios_edid(pScrn);