git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 2006 Dave Airlie
   3  * Copyright 2007 Maarten Maathuis
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
  26  * decleration is at the bottom of this file as it is rather ugly
  27  */
  28
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include <assert.h>
  34 #include "xf86.h"
  35 #include "os.h"
  36 #include "mibank.h"
  37 #include "globals.h"
  38 #include "xf86.h"
  39 #include "xf86Priv.h"
  40 #include "xf86DDC.h"
  41 #include "mipointer.h"
  42 #include "windowstr.h"
  43 #include <randrstr.h>
  44 #include <X11/extensions/render.h>
  45
  46 #include "xf86Crtc.h"
  47 #include "nv_include.h"
  48
  49 #include "vgaHW.h"
  50
  51 #define CRTC_INDEX 0x3d4
  52 #define CRTC_DATA 0x3d5
  53 #define CRTC_IN_STAT_1 0x3da
  54
  55 #define WHITE_VALUE 0x3F
  56 #define BLACK_VALUE 0x00
  57 #define OVERSCAN_VALUE 0x01
  58
  59 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  60 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  61 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  62 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  63 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  64 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  65
  66 static CARD8 NVReadPVIO(xf86CrtcPtr crtc, CARD32 address)
  67 {
  68         ScrnInfoPtr pScrn = crtc->scrn;
  69         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  70         NVPtr pNv = NVPTR(pScrn);
  71
  72         /* Only NV4x have two pvio ranges */
  73         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  74                 return NV_RD08(pNv->PVIO1, address);
  75         } else {
  76                 return NV_RD08(pNv->PVIO0, address);
  77         }
  78 }
  79
  80 static void NVWritePVIO(xf86CrtcPtr crtc, CARD32 address, CARD8 value)
  81 {
  82         ScrnInfoPtr pScrn = crtc->scrn;
  83         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  84         NVPtr pNv = NVPTR(pScrn);
  85
  86         /* Only NV4x have two pvio ranges */
  87         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  88                 NV_WR08(pNv->PVIO1, address, value);
  89         } else {
  90                 NV_WR08(pNv->PVIO0, address, value);
  91         }
  92 }
  93
  94 static void NVWriteMiscOut(xf86CrtcPtr crtc, CARD8 value)
  95 {
  96         NVWritePVIO(crtc, VGA_MISC_OUT_W, value);
  97 }
  98
  99 static CARD8 NVReadMiscOut(xf86CrtcPtr crtc)
 100 {
 101         return NVReadPVIO(crtc, VGA_MISC_OUT_R);
 102 }
 103
 104 void NVWriteVGA(NVPtr pNv, int head, CARD8 index, CARD8 value)
 105 {
 106         volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 107
 108         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 109         NV_WR08(pCRTCReg, CRTC_DATA, value);
 110 }
 111
 112 CARD8 NVReadVGA(NVPtr pNv, int head, CARD8 index)
 113 {
 114         volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 115
 116         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 117         return NV_RD08(pCRTCReg, CRTC_DATA);
 118 }
 119
 120 void NVWriteVgaCrtc(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 121 {
 122         ScrnInfoPtr pScrn = crtc->scrn;
 123         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 124         NVPtr pNv = NVPTR(pScrn);
 125
 126         NVWriteVGA(pNv, nv_crtc->head, index, value);
 127 }
 128
 129 CARD8 NVReadVgaCrtc(xf86CrtcPtr crtc, CARD8 index)
 130 {
 131         ScrnInfoPtr pScrn = crtc->scrn;
 132         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 133         NVPtr pNv = NVPTR(pScrn);
 134
 135         return NVReadVGA(pNv, nv_crtc->head, index);
 136 }
 137
 138 static void NVWriteVgaSeq(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 139 {
 140         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 141         NVWritePVIO(crtc, VGA_SEQ_DATA, value);
 142 }
 143
 144 static CARD8 NVReadVgaSeq(xf86CrtcPtr crtc, CARD8 index)
 145 {
 146         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 147         return NVReadPVIO(crtc, VGA_SEQ_DATA);
 148 }
 149
 150 static void NVWriteVgaGr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 151 {
 152         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 153         NVWritePVIO(crtc, VGA_GRAPH_DATA, value);
 154 }
 155
 156 static CARD8 NVReadVgaGr(xf86CrtcPtr crtc, CARD8 index)
 157 {
 158         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 159         return NVReadPVIO(crtc, VGA_GRAPH_DATA);
 160 }
 161
 162
 163 static void NVWriteVgaAttr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 164 {
 165   ScrnInfoPtr pScrn = crtc->scrn;
 166   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 167   NVPtr pNv = NVPTR(pScrn);
 168   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 169
 170   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 171   if (nv_crtc->paletteEnabled)
 172     index &= ~0x20;
 173   else
 174     index |= 0x20;
 175   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 176   NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
 177 }
 178
 179 static CARD8 NVReadVgaAttr(xf86CrtcPtr crtc, CARD8 index)
 180 {
 181   ScrnInfoPtr pScrn = crtc->scrn;
 182   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 183   NVPtr pNv = NVPTR(pScrn);
 184   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 185
 186   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 187   if (nv_crtc->paletteEnabled)
 188     index &= ~0x20;
 189   else
 190     index |= 0x20;
 191   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 192   return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
 193 }
 194
 195 void NVCrtcSetOwner(xf86CrtcPtr crtc)
 196 {
 197         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 198         ScrnInfoPtr pScrn = crtc->scrn;
 199         NVPtr pNv = NVPTR(pScrn);
 200         /* Non standard beheaviour required by NV11 */
 201         if (pNv) {
 202                 uint8_t owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 203                 ErrorF("pre-Owner: 0x%X\n", owner);
 204                 if (owner == 0x04) {
 205                         uint32_t pbus84 = nvReadMC(pNv, 0x1084);
 206                         ErrorF("pbus84: 0x%X\n", pbus84);
 207                         pbus84 &= ~(1<<28);
 208                         ErrorF("pbus84: 0x%X\n", pbus84);
 209                         nvWriteMC(pNv, 0x1084, pbus84);
 210                 }
 211                 /* The blob never writes owner to pcio1, so should we */
 212                 if (pNv->NVArch == 0x11) {
 213                         NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, 0xff);
 214                 }
 215                 NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, nv_crtc->crtc * 0x3);
 216                 owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 217                 ErrorF("post-Owner: 0x%X\n", owner);
 218         } else {
 219                 ErrorF("pNv pointer is NULL\n");
 220         }
 221 }
 222
 223 static void
 224 NVEnablePalette(xf86CrtcPtr crtc)
 225 {
 226   ScrnInfoPtr pScrn = crtc->scrn;
 227   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 228   NVPtr pNv = NVPTR(pScrn);
 229   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 230
 231   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 232   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
 233   nv_crtc->paletteEnabled = TRUE;
 234 }
 235
 236 static void
 237 NVDisablePalette(xf86CrtcPtr crtc)
 238 {
 239   ScrnInfoPtr pScrn = crtc->scrn;
 240   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 241   NVPtr pNv = NVPTR(pScrn);
 242   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 243
 244   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 245   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
 246   nv_crtc->paletteEnabled = FALSE;
 247 }
 248
 249 static void NVWriteVgaReg(xf86CrtcPtr crtc, CARD32 reg, CARD8 value)
 250 {
 251  ScrnInfoPtr pScrn = crtc->scrn;
 252   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 253   NVPtr pNv = NVPTR(pScrn);
 254   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 255
 256   NV_WR08(pCRTCReg, reg, value);
 257 }
 258
 259 /* perform a sequencer reset */
 260 static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
 261 {
 262   if (start)
 263     NVWriteVgaSeq(crtc, 0x00, 0x1);
 264   else
 265     NVWriteVgaSeq(crtc, 0x00, 0x3);
 266
 267 }
 268 static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
 269 {
 270         CARD8 tmp;
 271
 272         if (on) {
 273                 tmp = NVReadVgaSeq(crtc, 0x1);
 274                 NVVgaSeqReset(crtc, TRUE);
 275                 NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
 276
 277                 NVEnablePalette(crtc);
 278         } else {
 279                 /*
 280                  * Reenable sequencer, then turn on screen.
 281                  */
 282                 tmp = NVReadVgaSeq(crtc, 0x1);
 283                 NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20); /* reenable display */
 284                 NVVgaSeqReset(crtc, FALSE);
 285
 286                 NVDisablePalette(crtc);
 287         }
 288 }
 289
 290 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool Lock)
 291 {
 292         CARD8 cr11;
 293
 294         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57);
 295         cr11 = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE);
 296         if (Lock) cr11 |= 0x80;
 297         else cr11 &= ~0x80;
 298         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE, cr11);
 299 }
 300
 301 xf86OutputPtr
 302 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
 303 {
 304         ScrnInfoPtr pScrn = crtc->scrn;
 305         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 306         int i;
 307         for (i = 0; i < xf86_config->num_output; i++) {
 308                 xf86OutputPtr output = xf86_config->output[i];
 309
 310                 if (output->crtc == crtc) {
 311                         return output;
 312                 }
 313         }
 314
 315         return NULL;
 316 }
 317
 318 xf86CrtcPtr
 319 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
 320 {
 321         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 322         int i;
 323
 324         for (i = 0; i < xf86_config->num_crtc; i++) {
 325                 xf86CrtcPtr crtc = xf86_config->crtc[i];
 326                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 327                 if (nv_crtc->crtc == index)
 328                         return crtc;
 329         }
 330
 331         return NULL;
 332 }
 333
 334 /*
 335  * Calculate the Video Clock parameters for the PLL.
 336  */
 337 static void CalcVClock (
 338         uint32_t                clockIn,
 339         uint32_t                *clockOut,
 340         CARD32          *pllOut,
 341         NVPtr           pNv
 342 )
 343 {
 344         unsigned lowM, highM, highP;
 345         unsigned DeltaNew, DeltaOld;
 346         unsigned VClk, Freq;
 347         unsigned M, N, P;
 348
 349         /* M: PLL reference frequency postscaler divider */
 350         /* P: PLL VCO output postscaler divider */
 351         /* N: PLL VCO postscaler setting */
 352
 353         DeltaOld = 0xFFFFFFFF;
 354
 355         VClk = (unsigned)clockIn;
 356
 357         /* Taken from Haiku, after someone with an NV28 had an issue */
 358         switch(pNv->NVArch) {
 359                 case 0x28:
 360                         lowM = 1;
 361                         highP = 32;
 362                         if (VClk > 340000) {
 363                                 highM = 2;
 364                         } else if (VClk > 200000) {
 365                                 highM = 4;
 366                         } else if (VClk > 150000) {
 367                                 highM = 6;
 368                         } else {
 369                                 highM = 14;
 370                         }
 371                         break;
 372                 default:
 373                         lowM = 1;
 374                         highP = 16;
 375                         if (VClk > 340000) {
 376                                 highM = 2;
 377                         } else if (VClk > 250000) {
 378                                 highM = 6;
 379                         } else {
 380                                 highM = 14;
 381                         }
 382                         break;
 383         }
 384
 385         for (P = 1; P <= highP; P++) {
 386                 Freq = VClk << P;
 387                 if ((Freq >= 128000) && (Freq <= 350000)) {
 388                         for (M = lowM; M <= highM; M++) {
 389                                 N = ((VClk << P) * M) / pNv->CrystalFreqKHz;
 390                                 if (N <= 255) {
 391                                         Freq = ((pNv->CrystalFreqKHz * N) / M) >> P;
 392                                         if (Freq > VClk) {
 393                                                 DeltaNew = Freq - VClk;
 394                                         } else {
 395                                                 DeltaNew = VClk - Freq;
 396                                         }
 397                                         if (DeltaNew < DeltaOld) {
 398                                                 *pllOut   = (P << 16) | (N << 8) | M;
 399                                                 *clockOut = Freq;
 400                                                 DeltaOld  = DeltaNew;
 401                                         }
 402                                 }
 403                         }
 404                 }
 405         }
 406 }
 407
 408 static void CalcVClock2Stage (
 409         uint32_t                clockIn,
 410         uint32_t                *clockOut,
 411         CARD32          *pllOut,
 412         CARD32          *pllBOut,
 413         NVPtr           pNv
 414 )
 415 {
 416         unsigned DeltaNew, DeltaOld;
 417         unsigned VClk, Freq;
 418         unsigned M, N, P;
 419         unsigned lowM, highM, highP;
 420
 421         DeltaOld = 0xFFFFFFFF;
 422
 423         *pllBOut = 0x80000401;  /* fixed at x4 for now */
 424
 425         VClk = (unsigned)clockIn;
 426
 427         /* Taken from Haiku, after someone with an NV28 had an issue */
 428         switch(pNv->NVArch) {
 429                 case 0x28:
 430                         lowM = 1;
 431                         highP = 32;
 432                         if (VClk > 340000) {
 433                                 highM = 2;
 434                         } else if (VClk > 200000) {
 435                                 highM = 4;
 436                         } else if (VClk > 150000) {
 437                                 highM = 6;
 438                         } else {
 439                                 highM = 14;
 440                         }
 441                         break;
 442                 default:
 443                         lowM = 1;
 444                         highP = 15;
 445                         if (VClk > 340000) {
 446                                 highM = 2;
 447                         } else if (VClk > 250000) {
 448                                 highM = 6;
 449                         } else {
 450                                 highM = 14;
 451                         }
 452                         break;
 453         }
 454
 455         for (P = 0; P <= highP; P++) {
 456                 Freq = VClk << P;
 457                 if ((Freq >= 400000) && (Freq <= 1000000)) {
 458                         for (M = lowM; M <= highM; M++) {
 459                                 N = ((VClk << P) * M) / (pNv->CrystalFreqKHz << 2);
 460                                 if ((N >= 5) && (N <= 255)) {
 461                                         Freq = (((pNv->CrystalFreqKHz << 2) * N) / M) >> P;
 462                                         if (Freq > VClk) {
 463                                                 DeltaNew = Freq - VClk;
 464                                         } else {
 465                                                 DeltaNew = VClk - Freq;
 466                                         }
 467                                         if (DeltaNew < DeltaOld) {
 468                                                 *pllOut   = (P << 16) | (N << 8) | M;
 469                                                 *clockOut = Freq;
 470                                                 DeltaOld  = DeltaNew;
 471                                         }
 472                                 }
 473                         }
 474                 }
 475         }
 476 }
 477
 478 /* BIG NOTE: modifying vpll1 and vpll2 does not work, what bit is the switch to allow it? */
 479
 480 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
 481 /* They are only valid for NV4x, appearantly reordered for NV5x */
 482 /* gpu pll: 0x4000 + 0x4004
 483  * unknown pll: 0x4008 + 0x400c
 484  * vpll1: 0x4010 + 0x4014
 485  * vpll2: 0x4018 + 0x401c
 486  * unknown pll: 0x4020 + 0x4024
 487  * unknown pll: 0x4038 + 0x403c
 488  * Some of the unknown's are probably memory pll's.
 489  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
 490  * 1 and 2 refer to the registers of each pair. There is only one post divider.
 491  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
 492  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
 493  *     bit8: A switch that turns of the second divider and multiplier off.
 494  *     bit12: Also a switch, i haven't seen it yet.
 495  *     bit16-19: p-divider
 496  *     but 28-31: Something related to the mode that is used (see bit8).
 497  * 2) bit0-7: m-divider (a)
 498  *     bit8-15: n-multiplier (a)
 499  *     bit16-23: m-divider (b)
 500  *     bit24-31: n-multiplier (b)
 501  */
 502
 503 /* Modifying the gpu pll for example requires:
 504  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 505  * This is not needed for the vpll's which have their own bits.
 506  */
 507
 508 static void
 509 CalculateVClkNV4x(
 510         NVPtr pNv,
 511         uint32_t requested_clock,
 512         uint32_t *given_clock,
 513         uint32_t *pll_a,
 514         uint32_t *pll_b,
 515         uint32_t *reg580,
 516         Bool    *db1_ratio,
 517         Bool primary
 518 )
 519 {
 520         uint32_t DeltaOld, DeltaNew;
 521         uint32_t freq, temp;
 522         /* We have 2 mulitpliers, 2 dividers and one post divider */
 523         /* Note that p is only 4 bits */
 524         uint32_t m1, m2, n1, n2, p;
 525         uint32_t m1_best = 0, m2_best = 0, n1_best = 0, n2_best = 0, p_best = 0;
 526
 527         DeltaOld = 0xFFFFFFFF;
 528
 529         /* This is no solid limit, but a reasonable boundary */
 530         if (requested_clock < 120000) {
 531                 *db1_ratio = TRUE;
 532                 /* Turn the second set of divider and multiplier off */
 533                 /* Neutral settings */
 534                 n2 = 1;
 535                 m2 = 1;
 536         } else {
 537                 *db1_ratio = FALSE;
 538                 /* Fixed at x4 for the moment */
 539                 n2 = 4;
 540                 m2 = 1;
 541         }
 542
 543         n2_best = n2;
 544         m2_best = m2;
 545
 546         /* Single pll */
 547         if (*db1_ratio) {
 548                 temp = 0.4975 * 250000;
 549                 p = 0;
 550
 551                 while (requested_clock <= temp) {
 552                         temp /= 2;
 553                         p++;
 554                 }
 555
 556                 /* The minimum clock after m1 is 3 Mhz, and the clock is 27 Mhz, so m_max = 9 */
 557                 /* The maximum clock is 25 Mhz */
 558                 for (m1 = 2; m1 <= 9; m1++) {
 559                         n1 = ((requested_clock << p) * m1)/(pNv->CrystalFreqKHz);
 560                         //if (n1/m1 < 4 || n1/m1 > 10)
 561                         //      continue;
 562                         if (n1 > 0 && n1 <= 255) {
 563                                 freq = ((pNv->CrystalFreqKHz * n1)/m1) >> p;
 564                                 if (freq > requested_clock) {
 565                                         DeltaNew = freq - requested_clock;
 566                                 } else {
 567                                         DeltaNew = requested_clock - freq;
 568                                 }
 569                                 if (DeltaNew < DeltaOld) {
 570                                         m1_best = m1;
 571                                         n1_best = n1;
 572                                         p_best = p;
 573                                         DeltaOld = DeltaNew;
 574                                 }
 575                         }
 576                 }
 577         /* Dual pll */
 578         } else {
 579                 for (p = 0; p <= 6; p++) {
 580                         /* Assuming a fixed 2nd stage */
 581                         freq = requested_clock << p;
 582                         /* The maximum output frequency of stage 2 is allowed to be between 400 Mhz and 1 GHz */
 583                         if (freq > 400000 && freq < 1000000) {
 584                                 /* The minimum clock after m1 is 3 Mhz, and the clock is 27 Mhz, so m_max = 9 */
 585                                 /* The maximum clock is 25 Mhz */
 586                                 for (m1 = 2; m1 <= 9; m1++) {
 587                                         n1 = ((requested_clock << p) * m1 * m2)/(pNv->CrystalFreqKHz * n2);
 588                                         if (n1 >= 5 && n1 <= 255) {
 589                                                 freq = ((pNv->CrystalFreqKHz * n1 * n2)/(m1 * m2)) >> p;
 590                                                 if (freq > requested_clock) {
 591                                                         DeltaNew = freq - requested_clock;
 592                                                 } else {
 593                                                         DeltaNew = requested_clock - freq;
 594                                                 }
 595                                                 if (DeltaNew < DeltaOld) {
 596                                                         m1_best = m1;
 597                                                         n1_best = n1;
 598                                                         p_best = p;
 599                                                         DeltaOld = DeltaNew;
 600                                                 }
 601                                         }
 602                                 }
 603                         }
 604                 }
 605         }
 606
 607         if (*db1_ratio) {
 608                 /* Bogus data, the same nvidia uses */
 609                 n2_best = 1;
 610                 m2_best = 31;
 611         }
 612
 613         /* What exactly are the purpose of bit30 (a) and bit31(b)? */
 614         *pll_a = (1 << 30) | (p_best << 16) | (n1_best << 8) | (m1_best << 0);
 615         *pll_b = (1 << 31) | (n2_best << 8) | (m2_best << 0);
 616
 617         if (*db1_ratio) {
 618                 if (primary) {
 619                         *reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 620                 } else {
 621                         *reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 622                 }
 623         } else {
 624                 if (primary) {
 625                         *reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
 626                 } else {
 627                         *reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
 628                 }
 629         }
 630
 631         if (*db1_ratio) {
 632                 ErrorF("vpll: n1 %d m1 %d p %d db1_ratio %d\n", n1_best, m1_best, p_best, *db1_ratio);
 633         } else {
 634                 ErrorF("vpll: n1 %d n2 %d m1 %d m2 %d p %d db1_ratio %d\n", n1_best, n2_best, m1_best, m2_best, p_best, *db1_ratio);
 635         }
 636 }
 637
 638 static void nv40_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 639 {
 640         state->vpll1_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 641         state->vpll1_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 642         state->vpll2_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 643         state->vpll2_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 644         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 645         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 646         state->reg580 = nvReadRAMDAC0(pNv, NV_RAMDAC_580);
 647 }
 648
 649 static void nv40_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 650 {
 651         CARD32 fp_debug_0[2];
 652         uint32_t index[2];
 653         fp_debug_0[0] = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
 654         fp_debug_0[1] = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
 655
 656         /* The TMDS_PLL switch is on the actual ramdac */
 657         if (state->crosswired) {
 658                 index[0] = 1;
 659                 index[1] = 0;
 660                 ErrorF("Crosswired pll state load\n");
 661         } else {
 662                 index[0] = 0;
 663                 index[1] = 1;
 664         }
 665
 666         if (state->vpll2_b) {
 667                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0,
 668                         fp_debug_0[index[1]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 669
 670                 /* Wait for the situation to stabilise */
 671                 usleep(5000);
 672
 673                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 674                 /* for vpll2 change bits 18 and 19 are disabled */
 675                 reg_c040 &= ~(0x3 << 18);
 676                 nvWriteMC(pNv, 0xc040, reg_c040);
 677
 678                 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 679                 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 680
 681                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2_a);
 682                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 683
 684                 ErrorF("writing pllsel %08X\n", state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 685                 /* Let's keep the primary vpll off */
 686                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 687
 688                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 689                 ErrorF("writing reg580 %08X\n", state->reg580);
 690
 691                 /* We need to wait a while */
 692                 usleep(5000);
 693                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 694
 695                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[1]]);
 696
 697                 /* Wait for the situation to stabilise */
 698                 usleep(5000);
 699         }
 700
 701         if (state->vpll1_b) {
 702                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0,
 703                         fp_debug_0[index[0]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 704
 705                 /* Wait for the situation to stabilise */
 706                 usleep(5000);
 707
 708                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 709                 /* for vpll2 change bits 16 and 17 are disabled */
 710                 reg_c040 &= ~(0x3 << 16);
 711                 nvWriteMC(pNv, 0xc040, reg_c040);
 712
 713                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 714                 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 715
 716                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll1_a);
 717                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpll1_b);
 718
 719                 ErrorF("writing pllsel %08X\n", state->pllsel);
 720                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 721
 722                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 723                 ErrorF("writing reg580 %08X\n", state->reg580);
 724
 725                 /* We need to wait a while */
 726                 usleep(5000);
 727                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 728
 729                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[0]]);
 730
 731                 /* Wait for the situation to stabilise */
 732                 usleep(5000);
 733         }
 734
 735         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 736         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 737 }
 738
 739 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 740 {
 741         state->vpll = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 742         if(pNv->twoHeads) {
 743                 state->vpll2 = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 744         }
 745         if(pNv->twoStagePLL) {
 746                 state->vpllB = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 747                 state->vpll2B = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 748         }
 749         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 750         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 751 }
 752
 753
 754 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 755 {
 756         if (state->vpll2) {
 757                 if(pNv->twoHeads) {
 758                         ErrorF("writing vpll2 %08X\n", state->vpll2);
 759                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2);
 760                 }
 761                 if(pNv->twoStagePLL) {
 762                         ErrorF("writing vpll2B %08X\n", state->vpll2B);
 763                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2B);
 764                 }
 765
 766                 ErrorF("writing pllsel %08X\n", state->pllsel);
 767                 /* Let's keep the primary vpll off */
 768                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 769         }
 770
 771         if (state->vpll) {
 772                 ErrorF("writing vpll %08X\n", state->vpll);
 773                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll);
 774                 if(pNv->twoStagePLL) {
 775                         ErrorF("writing vpllB %08X\n", state->vpllB);
 776                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpllB);
 777                 }
 778
 779                 ErrorF("writing pllsel %08X\n", state->pllsel);
 780                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 781         }
 782
 783         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 784         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 785 }
 786
 787 /*
 788  * Calculate extended mode parameters (SVGA) and save in a
 789  * mode state structure.
 790  */
 791 void nv_crtc_calc_state_ext(
 792         xf86CrtcPtr     crtc,
 793         int                     bpp,
 794         int                     DisplayWidth, /* Does this change after setting the mode? */
 795         int                     CrtcHDisplay,
 796         int                     CrtcVDisplay,
 797         int                     dotClock,
 798         int                     flags
 799 )
 800 {
 801         ScrnInfoPtr pScrn = crtc->scrn;
 802         uint32_t pixelDepth, VClk = 0;
 803         CARD32 CursorStart;
 804         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 805         xf86CrtcConfigPtr   xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 806         NVCrtcRegPtr regp;
 807         NVPtr pNv = NVPTR(pScrn);
 808         RIVA_HW_STATE *state;
 809         int num_crtc_enabled, i;
 810
 811         state = &pNv->ModeReg;
 812
 813         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 814
 815         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 816         NVOutputPrivatePtr nv_output = output->driver_private;
 817
 818         /*
 819          * Extended RIVA registers.
 820          */
 821         pixelDepth = (bpp + 1)/8;
 822         if (pNv->Architecture == NV_ARCH_40) {
 823                 /* Does register 0x580 already have a value? */
 824                 if (!state->reg580) {
 825                         state->reg580 = pNv->misc_info.ramdac_0_reg_580;
 826                 }
 827                 if (nv_output->ramdac == 1) {
 828                         CalculateVClkNV4x(pNv, dotClock, &VClk, &state->vpll2_a, &state->vpll2_b, &state->reg580, &state->db1_ratio[1], FALSE);
 829                 } else {
 830                         CalculateVClkNV4x(pNv, dotClock, &VClk, &state->vpll1_a, &state->vpll1_b, &state->reg580, &state->db1_ratio[0], TRUE);
 831                 }
 832         } else if (pNv->twoStagePLL) {
 833                 CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB, pNv);
 834         } else {
 835                 CalcVClock(dotClock, &VClk, &state->pll, pNv);
 836         }
 837
 838         switch (pNv->Architecture) {
 839         case NV_ARCH_04:
 840                 nv4UpdateArbitrationSettings(VClk,
 841                                                 pixelDepth * 8,
 842                                                 &(state->arbitration0),
 843                                                 &(state->arbitration1),
 844                                                 pNv);
 845                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
 846                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
 847                 if (flags & V_DBLSCAN)
 848                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 849                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
 850                 state->pllsel   |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
 851                 state->config   = 0x00001114;
 852                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 853                 break;
 854         case NV_ARCH_10:
 855         case NV_ARCH_20:
 856         case NV_ARCH_30:
 857         default:
 858                 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
 859                         ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
 860                         state->arbitration0 = 128;
 861                         state->arbitration1 = 0x0480;
 862                 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
 863                         ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
 864                         nForceUpdateArbitrationSettings(VClk,
 865                                                 pixelDepth * 8,
 866                                                 &(state->arbitration0),
 867                                                 &(state->arbitration1),
 868                                                 pNv);
 869                 } else if (pNv->Architecture < NV_ARCH_30) {
 870                         nv10UpdateArbitrationSettings(VClk,
 871                                                 pixelDepth * 8,
 872                                                 &(state->arbitration0),
 873                                                 &(state->arbitration1),
 874                                                 pNv);
 875                 } else {
 876                         nv30UpdateArbitrationSettings(pNv,
 877                                                 &(state->arbitration0),
 878                                                 &(state->arbitration1));
 879                 }
 880
 881                 CursorStart = pNv->Cursor->offset;
 882
 883                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
 884                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
 885                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
 886
 887                 if (flags & V_DBLSCAN)
 888                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 889
 890                 state->config   = nvReadFB(pNv, NV_PFB_CFG0);
 891                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 892                 break;
 893         }
 894
 895         /* okay do we have 2 CRTCs running ? */
 896         num_crtc_enabled = 0;
 897         for (i = 0; i < xf86_config->num_crtc; i++) {
 898                 if (xf86_config->crtc[i]->enabled) {
 899                         num_crtc_enabled++;
 900                 }
 901         }
 902
 903         ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
 904
 905         if (pNv->Architecture < NV_ARCH_40) {
 906                 /* We need this before the next code */
 907                 if (nv_crtc->crtc == 1) {
 908                         state->vpll2 = state->pll;
 909                         state->vpll2B = state->pllB;
 910                 } else {
 911                         state->vpll = state->pll;
 912                         state->vpllB = state->pllB;
 913                 }
 914         }
 915
 916         if (pNv->Architecture == NV_ARCH_40) {
 917                 /* This register is only used on the primary ramdac */
 918                 /* This seems to be needed to select the proper clocks, otherwise bad things happen */
 919                 /* Assumption CRTC1 will overwrite the CRTC0 value */
 920                 /* Also make sure we don't set both bits */
 921
 922                 if (!state->sel_clk)
 923                         state->sel_clk = pNv->misc_info.sel_clk & ~(0xf << 16);
 924
 925                 /* The rough idea is this:
 926                  * 0x40000: Normal wiring for dvi panels.
 927                  * 0x10000: Cross wiring for dvi panels (not a 100% sure if this is also true for dual-crosswire).
 928                  * 0x00000: No dvi panels present.
 929                  * Other bits also exist, but we leave those intact.
 930                  */
 931
 932                 if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS) {
 933                         /* Clean out all the bits and enable another mode */
 934                         if (nv_crtc->head == nv_output->preferred_crtc) {
 935                                 state->sel_clk &= ~(0xf << 16);
 936                                 state->sel_clk |= (1 << 18);
 937                         } else {
 938                                 state->sel_clk &= ~(0xf << 16);
 939                                 state->sel_clk |= (1 << 16);
 940                         }
 941                 } else {
 942                         int other_index = (~nv_crtc->head) & 1;
 943                         xf86CrtcPtr crtc2 = nv_find_crtc_by_index(pScrn, other_index);
 944                         if (crtc2->enabled) {
 945                                 xf86OutputPtr output2 = NVGetOutputFromCRTC(crtc2);
 946                                 NVOutputPrivatePtr nv_output2 = output2->driver_private;
 947                                 if (nv_output2->type == OUTPUT_TMDS || nv_output2->type == OUTPUT_LVDS) {
 948                                         /* Clean out all the bits and enable another mode */
 949                                         if (other_index == nv_output2->preferred_crtc) {
 950                                                 state->sel_clk &= ~(0xf << 16);
 951                                                 state->sel_clk |= (1 << 18);
 952                                         } else {
 953                                                 state->sel_clk &= ~(0xf << 16);
 954                                                 state->sel_clk |= (1 << 16);
 955                                         }
 956                                 } else {
 957                                         /* Destroy all tmds traces */
 958                                         state->sel_clk &= ~(0xf << 16);
 959                                 }
 960                         } else {
 961                                 /* Destroy all tmds traces */
 962                                 state->sel_clk &= ~(0xf << 16);
 963                         }
 964                 }
 965
 966                 /* Are we crosswired? */
 967                 if (nv_crtc->head != nv_output->preferred_crtc &&
 968                         (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
 969                         state->crosswired = TRUE;
 970                 } else if (nv_crtc->head != nv_output->preferred_crtc) {
 971                         state->crosswired = FALSE;
 972                 }
 973
 974                 if (nv_crtc->head == 1) {
 975                         if (state->db1_ratio[1])
 976                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
 977                 } else if (nv_crtc->head == 0) {
 978                         if (state->db1_ratio[0])
 979                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
 980                 }
 981         } else {
 982                 /* This seems true for nv34 */
 983                 state->sel_clk = 0x0;
 984                 state->crosswired = FALSE;
 985         }
 986
 987         if (nv_output->ramdac == 1) {
 988                 if (!state->db1_ratio[1]) {
 989                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 990                 } else {
 991                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 992                 }
 993                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
 994         } else {
 995                 if (pNv->Architecture < NV_ARCH_40)
 996                         state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
 997                 else
 998                         state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
 999                 if (!state->db1_ratio[0]) {
1000                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1001                 } else {
1002                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1003                 }
1004         }
1005
1006         /* The purpose is unknown */
1007         //if (pNv->Architecture == NV_ARCH_40)
1008         //      state->pllsel |= (1 << 2);
1009
1010         regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
1011         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
1012         if (pNv->Architecture >= NV_ARCH_30) {
1013                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
1014         }
1015
1016         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
1017         regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
1018 }
1019
1020 static void
1021 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
1022 {
1023         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1024         ScrnInfoPtr pScrn = crtc->scrn;
1025         NVPtr pNv = NVPTR(pScrn);
1026         unsigned char seq1 = 0, crtc17 = 0;
1027         unsigned char crtc1A;
1028
1029         ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->crtc, mode);
1030
1031         NVCrtcSetOwner(crtc);
1032
1033         crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
1034         switch(mode) {
1035                 case DPMSModeStandby:
1036                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
1037                 seq1 = 0x20;
1038                 crtc17 = 0x80;
1039                 crtc1A |= 0x80;
1040                 break;
1041         case DPMSModeSuspend:
1042                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
1043                 seq1 = 0x20;
1044                 crtc17 = 0x80;
1045                 crtc1A |= 0x40;
1046                 break;
1047         case DPMSModeOff:
1048                 /* Screen: Off; HSync: Off, VSync: Off */
1049                 seq1 = 0x20;
1050                 crtc17 = 0x00;
1051                 crtc1A |= 0xC0;
1052                 break;
1053         case DPMSModeOn:
1054         default:
1055                 /* Screen: On; HSync: On, VSync: On */
1056                 seq1 = 0x00;
1057                 crtc17 = 0x80;
1058                 break;
1059         }
1060
1061         NVVgaSeqReset(crtc, TRUE);
1062         /* Each head has it's own sequencer, so we can turn it off when we want */
1063         seq1 |= (NVReadVgaSeq(crtc, 0x01) & ~0x20);
1064         NVWriteVgaSeq(crtc, 0x1, seq1);
1065         crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
1066         usleep(10000);
1067         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
1068         NVVgaSeqReset(crtc, FALSE);
1069
1070         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
1071
1072         /* I hope this is the right place */
1073         if (crtc->enabled && mode == DPMSModeOn) {
1074                 pNv->crtc_active[nv_crtc->head] = TRUE;
1075         } else {
1076                 pNv->crtc_active[nv_crtc->head] = FALSE;
1077         }
1078 }
1079
1080 static Bool
1081 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
1082                      DisplayModePtr adjusted_mode)
1083 {
1084         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1085         ScrnInfoPtr pScrn = crtc->scrn;
1086         NVPtr pNv = NVPTR(pScrn);
1087         ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->crtc);
1088
1089         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1090         NVOutputPrivatePtr nv_output = output->driver_private;
1091
1092         /* For internal panels and gpu scaling on DVI we need the native mode */
1093         if ((nv_output->type == OUTPUT_LVDS) || (pNv->fpScaler && (nv_output->type == OUTPUT_TMDS))) {
1094                 adjusted_mode->HDisplay = nv_output->native_mode->HDisplay;
1095                 adjusted_mode->HSkew = nv_output->native_mode->HSkew;
1096                 adjusted_mode->HSyncStart = nv_output->native_mode->HSyncStart;
1097                 adjusted_mode->HSyncEnd = nv_output->native_mode->HSyncEnd;
1098                 adjusted_mode->HTotal = nv_output->native_mode->HTotal;
1099                 adjusted_mode->VDisplay = nv_output->native_mode->VDisplay;
1100                 adjusted_mode->VScan = nv_output->native_mode->VScan;
1101                 adjusted_mode->VSyncStart = nv_output->native_mode->VSyncStart;
1102                 adjusted_mode->VSyncEnd = nv_output->native_mode->VSyncEnd;
1103                 adjusted_mode->VTotal = nv_output->native_mode->VTotal;
1104                 adjusted_mode->Clock = nv_output->native_mode->Clock;
1105
1106                 xf86SetModeCrtc(adjusted_mode, INTERLACE_HALVE_V);
1107         }
1108
1109         return TRUE;
1110 }
1111
1112 static void
1113 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode)
1114 {
1115         ScrnInfoPtr pScrn = crtc->scrn;
1116         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1117         NVCrtcRegPtr regp;
1118         NVPtr pNv = NVPTR(pScrn);
1119         int depth = pScrn->depth;
1120         unsigned int i;
1121
1122         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1123
1124         /*
1125         * compute correct Hsync & Vsync polarity
1126         */
1127         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
1128                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
1129
1130                 regp->MiscOutReg = 0x23;
1131                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
1132                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
1133         } else {
1134                 int VDisplay = mode->VDisplay;
1135                 if (mode->Flags & V_DBLSCAN)
1136                         VDisplay *= 2;
1137                 if (mode->VScan > 1)
1138                         VDisplay *= mode->VScan;
1139                 if (VDisplay < 400) {
1140                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
1141                 } else if (VDisplay < 480) {
1142                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
1143                 } else if (VDisplay < 768) {
1144                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
1145                 } else {
1146                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
1147                 }
1148         }
1149
1150         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
1151
1152         /*
1153         * Time Sequencer
1154         */
1155         if (depth == 4) {
1156                 regp->Sequencer[0] = 0x02;
1157         } else {
1158                 regp->Sequencer[0] = 0x00;
1159         }
1160         /* 0x20 disables the sequencer */
1161         if (mode->Flags & V_CLKDIV2) {
1162                 regp->Sequencer[1] = 0x29;
1163         } else {
1164                 regp->Sequencer[1] = 0x21;
1165         }
1166         if (depth == 1) {
1167                 regp->Sequencer[2] = 1 << BIT_PLANE;
1168         } else {
1169                 regp->Sequencer[2] = 0x0F;
1170                 regp->Sequencer[3] = 0x00;                     /* Font select */
1171         }
1172         if (depth < 8) {
1173                 regp->Sequencer[4] = 0x06;                             /* Misc */
1174         } else {
1175                 regp->Sequencer[4] = 0x0E;                             /* Misc */
1176         }
1177
1178         /*
1179         * CRTC Controller
1180         */
1181         regp->CRTC[0]  = (mode->CrtcHTotal >> 3) - 5;
1182         regp->CRTC[1]  = (mode->CrtcHDisplay >> 3) - 1;
1183         regp->CRTC[2]  = (mode->CrtcHBlankStart >> 3) - 1;
1184         regp->CRTC[3]  = (((mode->CrtcHBlankEnd >> 3) - 1) & 0x1F) | 0x80;
1185         i = (((mode->CrtcHSkew << 2) + 0x10) & ~0x1F);
1186         if (i < 0x80) {
1187                 regp->CRTC[3] |= i;
1188         }
1189         regp->CRTC[4]  = (mode->CrtcHSyncStart >> 3);
1190         regp->CRTC[5]  = ((((mode->CrtcHBlankEnd >> 3) - 1) & 0x20) << 2)
1191         | (((mode->CrtcHSyncEnd >> 3)) & 0x1F);
1192         regp->CRTC[6]  = (mode->CrtcVTotal - 2) & 0xFF;
1193         regp->CRTC[7]  = (((mode->CrtcVTotal - 2) & 0x100) >> 8)
1194                         | (((mode->CrtcVDisplay - 1) & 0x100) >> 7)
1195                         | ((mode->CrtcVSyncStart & 0x100) >> 6)
1196                         | (((mode->CrtcVBlankStart - 1) & 0x100) >> 5)
1197                         | 0x10
1198                         | (((mode->CrtcVTotal - 2) & 0x200)   >> 4)
1199                         | (((mode->CrtcVDisplay - 1) & 0x200) >> 3)
1200                         | ((mode->CrtcVSyncStart & 0x200) >> 2);
1201         regp->CRTC[8]  = 0x00;
1202         regp->CRTC[9]  = (((mode->CrtcVBlankStart - 1) & 0x200) >> 4) | 0x40;
1203         if (mode->Flags & V_DBLSCAN) {
1204                 regp->CRTC[9] |= 0x80;
1205         }
1206         if (mode->VScan >= 32) {
1207                 regp->CRTC[9] |= 0x1F;
1208         } else if (mode->VScan > 1) {
1209                 regp->CRTC[9] |= mode->VScan - 1;
1210         }
1211         regp->CRTC[10] = 0x00;
1212         regp->CRTC[11] = 0x00;
1213         regp->CRTC[12] = 0x00;
1214         regp->CRTC[13] = 0x00;
1215         regp->CRTC[14] = 0x00;
1216         regp->CRTC[15] = 0x00;
1217         regp->CRTC[16] = mode->CrtcVSyncStart & 0xFF;
1218         regp->CRTC[17] = (mode->CrtcVSyncEnd & 0x0F) | 0x20;
1219         regp->CRTC[18] = (mode->CrtcVDisplay - 1) & 0xFF;
1220         regp->CRTC[19] = mode->CrtcHDisplay >> 4;  /* just a guess */
1221         regp->CRTC[20] = 0x00;
1222         regp->CRTC[21] = (mode->CrtcVBlankStart - 1) & 0xFF;
1223         regp->CRTC[22] = (mode->CrtcVBlankEnd - 1) & 0xFF;
1224         /* 0x80 enables the sequencer, we don't want that */
1225         if (depth < 8) {
1226                 regp->CRTC[23] = 0xE3 & ~0x80;
1227         } else {
1228                 regp->CRTC[23] = 0xC3 & ~0x80;
1229         }
1230         regp->CRTC[24] = 0xFF;
1231
1232         /*
1233         * Theory resumes here....
1234         */
1235
1236         /*
1237         * Graphics Display Controller
1238         */
1239         regp->Graphics[0] = 0x00;
1240         regp->Graphics[1] = 0x00;
1241         regp->Graphics[2] = 0x00;
1242         regp->Graphics[3] = 0x00;
1243         if (depth == 1) {
1244                 regp->Graphics[4] = BIT_PLANE;
1245                 regp->Graphics[5] = 0x00;
1246         } else {
1247                 regp->Graphics[4] = 0x00;
1248                 if (depth == 4) {
1249                         regp->Graphics[5] = 0x02;
1250                 } else {
1251                         regp->Graphics[5] = 0x40;
1252                 }
1253         }
1254         regp->Graphics[6] = 0x05;   /* only map 64k VGA memory !!!! */
1255         regp->Graphics[7] = 0x0F;
1256         regp->Graphics[8] = 0xFF;
1257
1258         if (depth == 1) {
1259                 /* Initialise the Mono map according to which bit-plane gets used */
1260
1261                 Bool flipPixels = xf86GetFlipPixels();
1262
1263                 for (i=0; i<16; i++) {
1264                         if (((i & (1 << BIT_PLANE)) != 0) != flipPixels) {
1265                                 regp->Attribute[i] = WHITE_VALUE;
1266                         } else {
1267                                 regp->Attribute[i] = BLACK_VALUE;
1268                         }
1269                 }
1270
1271         } else {
1272                 regp->Attribute[0]  = 0x00; /* standard colormap translation */
1273                 regp->Attribute[1]  = 0x01;
1274                 regp->Attribute[2]  = 0x02;
1275                 regp->Attribute[3]  = 0x03;
1276                 regp->Attribute[4]  = 0x04;
1277                 regp->Attribute[5]  = 0x05;
1278                 regp->Attribute[6]  = 0x06;
1279                 regp->Attribute[7]  = 0x07;
1280                 regp->Attribute[8]  = 0x08;
1281                 regp->Attribute[9]  = 0x09;
1282                 regp->Attribute[10] = 0x0A;
1283                 regp->Attribute[11] = 0x0B;
1284                 regp->Attribute[12] = 0x0C;
1285                 regp->Attribute[13] = 0x0D;
1286                 regp->Attribute[14] = 0x0E;
1287                 regp->Attribute[15] = 0x0F;
1288                 if (depth == 4) {
1289                         regp->Attribute[16] = 0x81; /* wrong for the ET4000 */
1290                 } else {
1291                         regp->Attribute[16] = 0x41; /* wrong for the ET4000 */
1292                 }
1293                 if (depth > 4) {
1294                         regp->Attribute[17] = 0xff;
1295                 }
1296                 /* Attribute[17] (overscan) initialised in vgaHWGetHWRec() */
1297         }
1298         regp->Attribute[18] = 0x0F;
1299         regp->Attribute[19] = 0x00;
1300         regp->Attribute[20] = 0x00;
1301 }
1302
1303 #define MAX_H_VALUE(i) ((0x1ff + i) << 3)
1304 #define MAX_V_VALUE(i) ((0xfff + i) << 0)
1305
1306 /**
1307  * Sets up registers for the given mode/adjusted_mode pair.
1308  *
1309  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1310  *
1311  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1312  * be easily turned on/off after this.
1313  */
1314 static void
1315 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1316 {
1317         ScrnInfoPtr pScrn = crtc->scrn;
1318         NVPtr pNv = NVPTR(pScrn);
1319         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
1320         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1321         NVFBLayout *pLayout = &pNv->CurrentLayout;
1322         NVCrtcRegPtr regp, savep;
1323         unsigned int i;
1324
1325         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
1326         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
1327         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
1328         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
1329         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
1330         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
1331         int vertDisplay         = mode->CrtcVDisplay                    - 1;
1332         int vertStart           = mode->CrtcVSyncStart          - 1;
1333         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
1334         int vertTotal           = mode->CrtcVTotal                      - 2;
1335         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
1336         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
1337
1338         Bool is_fp = FALSE;
1339
1340         xf86OutputPtr  output;
1341         NVOutputPrivatePtr nv_output;
1342         for (i = 0; i < xf86_config->num_output; i++) {
1343                 output = xf86_config->output[i];
1344                 nv_output = output->driver_private;
1345
1346                 if (output->crtc == crtc) {
1347                         if ((nv_output->type == OUTPUT_LVDS) ||
1348                                 (nv_output->type == OUTPUT_TMDS)) {
1349
1350                                 is_fp = TRUE;
1351                                 break;
1352                         }
1353                 }
1354         }
1355
1356         ErrorF("Mode clock: %d\n", mode->Clock);
1357         ErrorF("Adjusted mode clock: %d\n", adjusted_mode->Clock);
1358
1359         ErrorF("crtc: Pre-sync workaround\n");
1360         /* Reverted to what nv did, because that works for all resolutions on flatpanels */
1361         if (is_fp) {
1362                 vertStart = vertTotal - 3;
1363                 vertEnd = vertTotal - 2;
1364                 vertBlankStart = vertStart;
1365                 horizStart = horizTotal - 5;
1366                 horizEnd = horizTotal - 2;
1367                 horizBlankEnd = horizTotal + 4;
1368                 if (pNv->overlayAdaptor) {
1369                         /* This reportedly works around Xv some overlay bandwidth problems*/
1370                         horizTotal += 2;
1371                 }
1372         }
1373         ErrorF("crtc: Post-sync workaround\n");
1374
1375         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
1376         ErrorF("horizStart: 0x%X \n", horizStart);
1377         ErrorF("horizEnd: 0x%X \n", horizEnd);
1378         ErrorF("horizTotal: 0x%X \n", horizTotal);
1379         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
1380         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
1381         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
1382         ErrorF("vertStart: 0x%X \n", vertStart);
1383         ErrorF("vertEnd: 0x%X \n", vertEnd);
1384         ErrorF("vertTotal: 0x%X \n", vertTotal);
1385         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
1386         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
1387
1388         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1389         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1390
1391         if(mode->Flags & V_INTERLACE)
1392                 vertTotal |= 1;
1393
1394         regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
1395         regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
1396         regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
1397         regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0)
1398                                 | SetBit(7);
1399         regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
1400         regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
1401                                 | SetBitField(horizEnd,4:0,4:0);
1402         regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
1403         regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
1404                                 | SetBitField(vertDisplay,8:8,1:1)
1405                                 | SetBitField(vertStart,8:8,2:2)
1406                                 | SetBitField(vertBlankStart,8:8,3:3)
1407                                 | SetBit(4)
1408                                 | SetBitField(vertTotal,9:9,5:5)
1409                                 | SetBitField(vertDisplay,9:9,6:6)
1410                                 | SetBitField(vertStart,9:9,7:7);
1411         regp->CRTC[NV_VGA_CRTCX_MAXSCLIN]  = SetBitField(vertBlankStart,9:9,5:5)
1412                                 | SetBit(6)
1413                                 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00);
1414         regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
1415         regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
1416         regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
1417         regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
1418         regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
1419         regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
1420         /* Not an extended register */
1421         regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
1422
1423         regp->Attribute[0x10] = 0x01;
1424         /* Blob sets this for normal monitors as well */
1425         regp->Attribute[0x11] = 0x00;
1426
1427         regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
1428                                 | SetBitField(vertBlankStart,10:10,3:3)
1429                                 | SetBitField(vertStart,10:10,2:2)
1430                                 | SetBitField(vertDisplay,10:10,1:1)
1431                                 | SetBitField(vertTotal,10:10,0:0);
1432
1433         regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
1434                                 | SetBitField(horizDisplay,8:8,1:1)
1435                                 | SetBitField(horizBlankStart,8:8,2:2)
1436                                 | SetBitField(horizStart,8:8,3:3);
1437
1438         regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
1439                                 | SetBitField(vertDisplay,11:11,2:2)
1440                                 | SetBitField(vertStart,11:11,4:4)
1441                                 | SetBitField(vertBlankStart,11:11,6:6);
1442
1443         if(mode->Flags & V_INTERLACE) {
1444                 horizTotal = (horizTotal >> 1) & ~1;
1445                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
1446                 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
1447         } else {
1448                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff;  /* interlace off */
1449         }
1450
1451         /* bit2 = 0 -> fine pitched crtc granularity */
1452         /* The rest disables double buffering on CRTC access */
1453         regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
1454
1455         if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
1456                 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1457                 if (nv_crtc->head == 0) {
1458                         regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1459                 }
1460
1461                 if (is_fp) {
1462                         regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0) | (1 << 1);
1463                 }
1464         } else {
1465                 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
1466                 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
1467         }
1468
1469         /* I'm trusting haiku driver on this one, they say it enables an external TDMS clock */
1470         if (is_fp) {
1471                 regp->CRTC[NV_VGA_CRTCX_59] = 0x1;
1472         } else {
1473                 regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1474         }
1475
1476         /*
1477         * Initialize DAC palette.
1478         */
1479         if(pLayout->bitsPerPixel != 8 ) {
1480                 for (i = 0; i < 256; i++) {
1481                         regp->DAC[i*3]     = i;
1482                         regp->DAC[(i*3)+1] = i;
1483                         regp->DAC[(i*3)+2] = i;
1484                 }
1485         }
1486
1487         /*
1488         * Calculate the extended registers.
1489         */
1490
1491         if(pLayout->depth < 24) {
1492                 i = pLayout->depth;
1493         } else {
1494                 i = 32;
1495         }
1496
1497         if(pNv->Architecture >= NV_ARCH_10) {
1498                 pNv->CURSOR = (CARD32 *)pNv->Cursor->map;
1499         }
1500
1501         ErrorF("crtc %d %d %d\n", nv_crtc->crtc, mode->CrtcHDisplay, pScrn->displayWidth);
1502         nv_crtc_calc_state_ext(crtc,
1503                                 i,
1504                                 pScrn->displayWidth,
1505                                 mode->CrtcHDisplay,
1506                                 mode->CrtcVDisplay,
1507                                 adjusted_mode->Clock,
1508                                 mode->Flags);
1509
1510         /* Enable slaved mode */
1511         if (is_fp) {
1512                 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1513         }
1514
1515         /* What is the meaning of this register? */
1516         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1517         regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
1518
1519         /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1520         /* But what are those special conditions? */
1521         if (pNv->Architecture <= NV_ARCH_30) {
1522                 if (is_fp) {
1523                         if(nv_crtc->head == 1) {
1524                                 regp->head |= NV_CRTC_FSEL_FPP1;
1525                         } else if (pNv->twoHeads) {
1526                                 regp->head |= NV_CRTC_FSEL_FPP2;
1527                         }
1528                 }
1529         } else {
1530                 /* This is observed on some g70 cards, non-flatpanel's too */
1531                 if (nv_crtc->head == 1) {
1532                         regp->head |= NV_CRTC_FSEL_FPP2;
1533                 }
1534         }
1535
1536         /* Except for rare conditions I2C is enabled on the primary crtc */
1537         if (nv_crtc->head == 0) {
1538                 if (pNv->overlayAdaptor) {
1539                         regp->head |= NV_CRTC_FSEL_OVERLAY;
1540                 }
1541                 regp->head |= NV_CRTC_FSEL_I2C;
1542         }
1543
1544         regp->cursorConfig = 0x00000100;
1545         if(mode->Flags & V_DBLSCAN)
1546                 regp->cursorConfig |= (1 << 4);
1547         if(pNv->alphaCursor) {
1548                 if((pNv->Chipset & 0x0ff0) != CHIPSET_NV11) {
1549                         regp->cursorConfig |= 0x04011000;
1550                 } else {
1551                         regp->cursorConfig |= 0x14011000;
1552                 }
1553         } else {
1554                 regp->cursorConfig |= 0x02000000;
1555         }
1556
1557         /* Unblock some timings */
1558         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1559         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1560
1561         /* 0x20 seems to be enabled and 0x14 disabled */
1562         regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1563
1564         /* 0x00 is disabled, 0x22 crt and 0x88 dfp */
1565         /* 0x11 is LVDS? */
1566         if (is_fp) {
1567                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1568         } else {
1569                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1570         }
1571
1572         /* These values seem to vary */
1573         regp->CRTC[NV_VGA_CRTCX_3C] = savep->CRTC[NV_VGA_CRTCX_3C];
1574
1575         /* 0x80 seems to be used very often, if not always */
1576         regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1577
1578         /* Are these(0x55 and 0x56) also timing related registers, since disabling them does nothing? */
1579         regp->CRTC[NV_VGA_CRTCX_55] = 0x0;
1580
1581         /* Common values like 0x14 and 0x04 are converted to 0x10 and 0x00 */
1582         //regp->CRTC[NV_VGA_CRTCX_56] = savep->CRTC[NV_VGA_CRTCX_56] & ~(1<<4);
1583         regp->CRTC[NV_VGA_CRTCX_56] = 0x0;
1584
1585         regp->CRTC[NV_VGA_CRTCX_57] = 0x0;
1586
1587         /* bit0: Seems to be mostly used on crtc1 */
1588         /* bit1: 1=crtc1, 0=crtc, but i'm unsure about this */
1589         /* 0x7E (crtc0, only seen in one dump) and 0x7F (crtc1) seem to be some kind of disable setting */
1590         /* This is likely to be incomplete */
1591         /* This is a very strange register, changed very often by the blob */
1592         regp->CRTC[NV_VGA_CRTCX_58] = 0x0;
1593
1594         /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1*/
1595         if (nv_crtc->head == 1) {
1596                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52;
1597         } else {
1598                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52 + 4;
1599         }
1600
1601         /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1602         regp->unk81c = nvReadCRTC0(pNv, NV_CRTC_081C);
1603
1604         regp->unk830 = mode->CrtcVDisplay - 3;
1605         regp->unk834 = mode->CrtcVDisplay - 1;
1606
1607         /* This is what the blob does */
1608         regp->unk850 = nvReadCRTC(pNv, 0, NV_CRTC_0850);
1609
1610         /* Never ever modify gpio, unless you know very well what you're doing */
1611         regp->gpio = nvReadCRTC(pNv, 0, NV_CRTC_GPIO);
1612 }
1613
1614 static void
1615 nv_crtc_mode_set_ramdac_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1616 {
1617         ScrnInfoPtr pScrn = crtc->scrn;
1618         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1619         NVCrtcRegPtr regp;
1620         NVPtr pNv = NVPTR(pScrn);
1621         NVFBLayout *pLayout = &pNv->CurrentLayout;
1622         Bool is_fp = FALSE;
1623         Bool is_lvds = FALSE;
1624         float aspect_ratio, panel_ratio;
1625         uint32_t h_scale, v_scale;
1626
1627         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1628
1629         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1630         NVOutputPrivatePtr nv_output = output->driver_private;
1631
1632         if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS)) {
1633                 is_fp = TRUE;
1634
1635                 if (nv_output->type == OUTPUT_LVDS)
1636                         is_lvds = TRUE;
1637
1638                 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
1639                 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
1640                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HDisplay;
1641                 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
1642                 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
1643                 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
1644                 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
1645
1646                 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
1647                 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
1648                 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VDisplay;
1649                 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
1650                 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
1651                 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
1652                 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
1653
1654                 ErrorF("Horizontal:\n");
1655                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
1656                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
1657                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
1658                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
1659                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
1660                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
1661                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
1662
1663                 ErrorF("Vertical:\n");
1664                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
1665                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
1666                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
1667                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
1668                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
1669                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
1670                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
1671         }
1672
1673         /*
1674         * bit0: positive vsync
1675         * bit4: positive hsync
1676         * bit8: enable panel scaling
1677         * bit26: a bit sometimes seen on some g70 cards
1678         * bit31: sometimes seen on LVDS panels
1679         * This must also be set for non-flatpanels
1680         * Some bits seem shifted for vga monitors
1681         */
1682
1683         if (is_fp) {
1684                 regp->fp_control = 0x11100000;
1685         } else {
1686                 regp->fp_control = 0x21100000;
1687         }
1688         if (nv_output->type == OUTPUT_LVDS) {
1689                 /* Let's assume LVDS to be on ramdac0, remember that in the ramdac routing is somewhat random (compared to bios setup), so don't trust it */
1690                 regp->fp_control = nvReadRAMDAC0(pNv, NV_RAMDAC_FP_CONTROL) & 0xfff00000;
1691         } else {
1692                 /* If the special bit exists, it exists on both ramdac's */
1693                 regp->fp_control |= nvReadRAMDAC0(pNv, NV_RAMDAC_FP_CONTROL) & (1 << 26);
1694         }
1695
1696         /* Deal with vsync/hsync polarity */
1697         /* These analog monitor offsets are guesswork */
1698         if (adjusted_mode->Flags & V_PVSYNC) {
1699                 regp->fp_control |= (1 << (0 + !is_fp));
1700         }
1701
1702         if (adjusted_mode->Flags & V_PHSYNC) {
1703                 regp->fp_control |= (1 << (4 + !is_fp));
1704         }
1705
1706         if (is_fp) {
1707                 ErrorF("Pre-panel scaling\n");
1708                 ErrorF("panel-size:%dx%d\n", nv_output->fpWidth, nv_output->fpHeight);
1709                 panel_ratio = (nv_output->fpWidth)/(float)(nv_output->fpHeight);
1710                 ErrorF("panel_ratio=%f\n", panel_ratio);
1711                 aspect_ratio = (mode->HDisplay)/(float)(mode->VDisplay);
1712                 ErrorF("aspect_ratio=%f\n", aspect_ratio);
1713                 /* Scale factors is the so called 20.12 format, taken from Haiku */
1714                 h_scale = ((1 << 12) * mode->HDisplay)/nv_output->fpWidth;
1715                 v_scale = ((1 << 12) * mode->VDisplay)/nv_output->fpHeight;
1716                 ErrorF("h_scale=%d\n", h_scale);
1717                 ErrorF("v_scale=%d\n", v_scale);
1718
1719                 /* Don't limit last fetched line */
1720                 regp->debug_2 = 0;
1721
1722                 /* We want automatic scaling */
1723                 regp->debug_1 = 0;
1724
1725                 regp->fp_hvalid_start = 0;
1726                 regp->fp_hvalid_end = (nv_output->fpWidth - 1);
1727
1728                 regp->fp_vvalid_start = 0;
1729                 regp->fp_vvalid_end = (nv_output->fpHeight - 1);
1730
1731                 if (!pNv->fpScaler) {
1732                         ErrorF("Flat panel is doing the scaling.\n");
1733                         regp->fp_control |= (1 << 8);
1734                 } else {
1735                         ErrorF("GPU is doing the scaling.\n");
1736                         /* GPU scaling happens automaticly at a ratio of 1.33 */
1737                         /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
1738                         if (h_scale != (1 << 12) && (panel_ratio > (aspect_ratio + 0.10))) {
1739                                 uint32_t diff;
1740
1741                                 ErrorF("Scaling resolution on a widescreen panel\n");
1742
1743                                 /* Scaling in both directions needs to the same */
1744                                 h_scale = v_scale;
1745
1746                                 /* Set a new horizontal scale factor and enable testmode (bit12) */
1747                                 regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
1748
1749                                 diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
1750                                 regp->fp_hvalid_start = diff/2;
1751                                 regp->fp_hvalid_end = nv_output->fpWidth - (diff/2) - 1;
1752                         }
1753
1754                         /* Same scaling, just for panels with aspect ratio's smaller than 1 */
1755                         if (v_scale != (1 << 12) && (panel_ratio < (aspect_ratio - 0.10))) {
1756                                 uint32_t diff;
1757
1758                                 ErrorF("Scaling resolution on a portrait panel\n");
1759
1760                                 /* Scaling in both directions needs to the same */
1761                                 v_scale = h_scale;
1762
1763                                 /* Set a new vertical scale factor and enable testmode (bit28) */
1764                                 regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
1765
1766                                 diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
1767                                 regp->fp_vvalid_start = diff/2;
1768                                 regp->fp_vvalid_end = nv_output->fpHeight - (diff/2) - 1;
1769                         }
1770                 }
1771
1772                 ErrorF("Post-panel scaling\n");
1773         }
1774
1775         if (pNv->Architecture >= NV_ARCH_10) {
1776                 /* Bios and blob don't seem to do anything (else) */
1777                 regp->nv10_cursync = (1<<25);
1778         }
1779
1780         /* These are the common blob values, minus a few fp specific bit's */
1781         /* Let's keep the TMDS pll and fpclock running in all situations */
1782         regp->debug_0 = 0x1101111;
1783
1784         if(is_fp) {
1785                 /* I am not completely certain, but seems to be set only for dfp's */
1786                 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED;
1787         }
1788
1789         ErrorF("output %d debug_0 %08X\n", nv_output->ramdac, regp->debug_0);
1790
1791         /* Flatpanel support needs at least a NV10 */
1792         if(pNv->twoHeads) {
1793                 /* Instead of 1, several other values are also used: 2, 7, 9 */
1794                 /* The purpose is unknown */
1795                 if(pNv->FPDither) {
1796                         regp->dither = 0x00010000;
1797                 }
1798         }
1799
1800         /* Kindly borrowed from haiku driver */
1801         /* bit4 and bit5 activate indirect mode trough color palette */
1802         switch (pLayout->depth) {
1803                 case 32:
1804                 case 16:
1805                         regp->general = 0x00101130;
1806                         break;
1807                 case 24:
1808                 case 15:
1809                         regp->general = 0x00100130;
1810                         break;
1811                 case 8:
1812                 default:
1813                         regp->general = 0x00101100;
1814                         break;
1815         }
1816
1817         if (pNv->alphaCursor) {
1818                 regp->general |= (1<<29);
1819         }
1820
1821         /* Some values the blob sets */
1822         /* This may apply to the real ramdac that is being used (for crosswired situations) */
1823         /* Nevertheless, it's unlikely to cause many problems, since the values are equal for both */
1824         regp->unk_a20 = 0x0;
1825         regp->unk_a24 = 0xfffff;
1826         regp->unk_a34 = 0x1;
1827 }
1828
1829 /**
1830  * Sets up registers for the given mode/adjusted_mode pair.
1831  *
1832  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1833  *
1834  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1835  * be easily turned on/off after this.
1836  */
1837 static void
1838 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
1839                  DisplayModePtr adjusted_mode,
1840                  int x, int y)
1841 {
1842         ScrnInfoPtr pScrn = crtc->scrn;
1843         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1844         NVPtr pNv = NVPTR(pScrn);
1845
1846         ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->crtc);
1847
1848         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->crtc);
1849         xf86PrintModeline(pScrn->scrnIndex, mode);
1850         NVCrtcSetOwner(crtc);
1851
1852         nv_crtc_mode_set_vga(crtc, mode);
1853         nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
1854         nv_crtc_mode_set_ramdac_regs(crtc, mode, adjusted_mode);
1855
1856         /* Just in case */
1857         NVCrtcLockUnlock(crtc, FALSE);
1858
1859         NVVgaProtect(crtc, TRUE);
1860         nv_crtc_load_state_ext(crtc, &pNv->ModeReg);
1861         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
1862         if (pNv->Architecture == NV_ARCH_40) {
1863                 nv40_crtc_load_state_pll(pNv, &pNv->ModeReg);
1864         } else {
1865                 nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
1866         }
1867         nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
1868
1869         NVVgaProtect(crtc, FALSE);
1870
1871         NVCrtcSetBase(crtc, x, y);
1872
1873 #if X_BYTE_ORDER == X_BIG_ENDIAN
1874         /* turn on LFB swapping */
1875         {
1876                 unsigned char tmp;
1877
1878                 tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
1879                 tmp |= (1 << 7);
1880                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
1881         }
1882 #endif
1883 }
1884
1885 void nv_crtc_save(xf86CrtcPtr crtc)
1886 {
1887         ScrnInfoPtr pScrn = crtc->scrn;
1888         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1889         NVPtr pNv = NVPTR(pScrn);
1890
1891         ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->crtc);
1892
1893         /* We just came back from terminal, so unlock */
1894         NVCrtcLockUnlock(crtc, FALSE);
1895
1896         NVCrtcSetOwner(crtc);
1897         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
1898         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
1899         if (pNv->Architecture == NV_ARCH_40) {
1900                 nv40_crtc_save_state_pll(pNv, &pNv->SavedReg);
1901         } else {
1902                 nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
1903         }
1904         nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
1905 }
1906
1907 void nv_crtc_restore(xf86CrtcPtr crtc)
1908 {
1909         ScrnInfoPtr pScrn = crtc->scrn;
1910         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1911         NVPtr pNv = NVPTR(pScrn);
1912
1913         ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->crtc);
1914
1915         NVCrtcSetOwner(crtc);
1916
1917         /* Just to be safe */
1918         NVCrtcLockUnlock(crtc, FALSE);
1919
1920         NVVgaProtect(crtc, TRUE);
1921         nv_crtc_load_state_ext(crtc, &pNv->SavedReg);
1922         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
1923         if (pNv->Architecture == NV_ARCH_40) {
1924                 nv40_crtc_load_state_pll(pNv, &pNv->SavedReg);
1925         } else {
1926                 nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
1927         }
1928         nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
1929         nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->vtOWNER);
1930         NVVgaProtect(crtc, FALSE);
1931
1932         /* We must lock the door if we leave ;-) */
1933         NVCrtcLockUnlock(crtc, TRUE);
1934 }
1935
1936 void nv_crtc_prepare(xf86CrtcPtr crtc)
1937 {
1938         ScrnInfoPtr pScrn = crtc->scrn;
1939         NVPtr pNv = NVPTR(pScrn);
1940         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1941
1942         ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->crtc);
1943
1944         crtc->funcs->dpms(crtc, DPMSModeOff);
1945
1946         /* Sync the engine before adjust mode */
1947         if (pNv->EXADriverPtr) {
1948                 exaMarkSync(pScrn->pScreen);
1949                 exaWaitSync(pScrn->pScreen);
1950         }
1951 }
1952
1953 void nv_crtc_commit(xf86CrtcPtr crtc)
1954 {
1955         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1956         ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->crtc);
1957
1958         crtc->funcs->dpms (crtc, DPMSModeOn);
1959         if (crtc->scrn->pScreen != NULL)
1960                 xf86_reload_cursors (crtc->scrn->pScreen);
1961 }
1962
1963 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
1964 {
1965         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1966         ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->crtc);
1967
1968         return FALSE;
1969 }
1970
1971 static void nv_crtc_unlock(xf86CrtcPtr crtc)
1972 {
1973         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1974         ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->crtc);
1975 }
1976
1977 static void
1978 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
1979                                         int size)
1980 {
1981         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1982         ScrnInfoPtr pScrn = crtc->scrn;
1983         NVPtr pNv = NVPTR(pScrn);
1984         int i, j;
1985
1986         NVCrtcRegPtr regp;
1987         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1988
1989         switch (pNv->CurrentLayout.depth) {
1990         case 15:
1991                 /* R5G5B5 */
1992                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
1993                 for (i = 0; i < 32; i++) {
1994                         for (j = 0; j < 8; j++) {
1995                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1996                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
1997                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1998                         }
1999                 }
2000                 break;
2001         case 16:
2002                 /* R5G6B5 */
2003                 /* First deal with the 5 bit colors */
2004                 for (i = 0; i < 32; i++) {
2005                         for (j = 0; j < 8; j++) {
2006                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2007                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2008                         }
2009                 }
2010                 /* Now deal with the 6 bit color */
2011                 for (i = 0; i < 64; i++) {
2012                         for (j = 0; j < 4; j++) {
2013                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
2014                         }
2015                 }
2016                 break;
2017         default:
2018                 /* R8G8B8 */
2019                 for (i = 0; i < 256; i++) {
2020                         regp->DAC[i * 3] = red[i] >> 8;
2021                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
2022                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
2023                 }
2024                 break;
2025         }
2026
2027         NVCrtcLoadPalette(crtc);
2028 }
2029
2030 /* NV04-NV10 doesn't support alpha cursors */
2031 static const xf86CrtcFuncsRec nv_crtc_funcs = {
2032         .dpms = nv_crtc_dpms,
2033         .save = nv_crtc_save, /* XXX */
2034         .restore = nv_crtc_restore, /* XXX */
2035         .mode_fixup = nv_crtc_mode_fixup,
2036         .mode_set = nv_crtc_mode_set,
2037         .prepare = nv_crtc_prepare,
2038         .commit = nv_crtc_commit,
2039         .destroy = NULL, /* XXX */
2040         .lock = nv_crtc_lock,
2041         .unlock = nv_crtc_unlock,
2042         .set_cursor_colors = nv_crtc_set_cursor_colors,
2043         .set_cursor_position = nv_crtc_set_cursor_position,
2044         .show_cursor = nv_crtc_show_cursor,
2045         .hide_cursor = nv_crtc_hide_cursor,
2046         .load_cursor_image = nv_crtc_load_cursor_image,
2047         .gamma_set = nv_crtc_gamma_set,
2048 };
2049
2050 /* NV11 and up has support for alpha cursors. */
2051 /* Due to different maximum sizes we cannot allow it to use normal cursors */
2052 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
2053         .dpms = nv_crtc_dpms,
2054         .save = nv_crtc_save, /* XXX */
2055         .restore = nv_crtc_restore, /* XXX */
2056         .mode_fixup = nv_crtc_mode_fixup,
2057         .mode_set = nv_crtc_mode_set,
2058         .prepare = nv_crtc_prepare,
2059         .commit = nv_crtc_commit,
2060         .destroy = NULL, /* XXX */
2061         .lock = nv_crtc_lock,
2062         .unlock = nv_crtc_unlock,
2063         .set_cursor_colors = NULL, /* Alpha cursors do not need this */
2064         .set_cursor_position = nv_crtc_set_cursor_position,
2065         .show_cursor = nv_crtc_show_cursor,
2066         .hide_cursor = nv_crtc_hide_cursor,
2067         .load_cursor_argb = nv_crtc_load_cursor_argb,
2068         .gamma_set = nv_crtc_gamma_set,
2069 };
2070
2071
2072 void
2073 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
2074 {
2075         NVPtr pNv = NVPTR(pScrn);
2076         xf86CrtcPtr crtc;
2077         NVCrtcPrivatePtr nv_crtc;
2078
2079         if (pNv->NVArch >= 0x11) {
2080                 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
2081         } else {
2082                 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
2083         }
2084         if (crtc == NULL)
2085                 return;
2086
2087         nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
2088         nv_crtc->crtc = crtc_num;
2089         nv_crtc->head = crtc_num;
2090
2091         crtc->driver_private = nv_crtc;
2092
2093         NVCrtcLockUnlock(crtc, FALSE);
2094 }
2095
2096 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2097 {
2098     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2099     int i;
2100     NVCrtcRegPtr regp;
2101
2102     regp = &state->crtc_reg[nv_crtc->head];
2103
2104     NVWriteMiscOut(crtc, regp->MiscOutReg);
2105
2106     for (i = 1; i < 5; i++)
2107       NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
2108
2109     /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
2110     NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
2111
2112     for (i = 0; i < 25; i++)
2113       NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
2114
2115     for (i = 0; i < 9; i++)
2116       NVWriteVgaGr(crtc, i, regp->Graphics[i]);
2117
2118     NVEnablePalette(crtc);
2119     for (i = 0; i < 21; i++)
2120       NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
2121     NVDisablePalette(crtc);
2122
2123 }
2124
2125 static void nv_crtc_fix_nv40_hw_cursor(xf86CrtcPtr crtc)
2126 {
2127   /* TODO - implement this properly */
2128   ScrnInfoPtr pScrn = crtc->scrn;
2129   NVPtr pNv = NVPTR(pScrn);
2130
2131   if(pNv->Architecture == NV_ARCH_40) {  /* HW bug */
2132     volatile CARD32 curpos = nvReadCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS);
2133     nvWriteCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS, curpos);
2134   }
2135
2136 }
2137 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2138 {
2139     ScrnInfoPtr pScrn = crtc->scrn;
2140     NVPtr pNv = NVPTR(pScrn);
2141     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2142     NVCrtcRegPtr regp;
2143
2144     regp = &state->crtc_reg[nv_crtc->head];
2145
2146     if(pNv->Architecture >= NV_ARCH_10) {
2147         if(pNv->twoHeads) {
2148            nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL, regp->head);
2149         }
2150         nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
2151         nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
2152         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
2153         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
2154         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2155         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2156         nvWriteMC(pNv, 0x1588, 0);
2157
2158         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
2159         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
2160         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO, regp->gpio);
2161         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0830, regp->unk830);
2162         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0834, regp->unk834);
2163         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0850, regp->unk850);
2164         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_081C, regp->unk81c);
2165
2166         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
2167         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
2168
2169         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
2170         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
2171         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3C, regp->CRTC[NV_VGA_CRTCX_3C]);
2172         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
2173         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
2174         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_56, regp->CRTC[NV_VGA_CRTCX_56]);
2175         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_57, regp->CRTC[NV_VGA_CRTCX_57]);
2176         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_58, regp->CRTC[NV_VGA_CRTCX_58]);
2177         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
2178         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
2179     }
2180
2181     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
2182     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
2183     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
2184     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
2185     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
2186     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
2187     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
2188     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
2189     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
2190     if(pNv->Architecture >= NV_ARCH_30) {
2191       NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
2192     }
2193
2194     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
2195     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
2196     nv_crtc_fix_nv40_hw_cursor(crtc);
2197     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
2198     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
2199
2200     nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_EN_0, 0);
2201     nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
2202
2203     pNv->CurrentState = state;
2204 }
2205
2206 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2207 {
2208     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2209     int i;
2210     NVCrtcRegPtr regp;
2211
2212     regp = &state->crtc_reg[nv_crtc->head];
2213
2214     regp->MiscOutReg = NVReadMiscOut(crtc);
2215
2216     for (i = 0; i < 25; i++)
2217         regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
2218
2219     NVEnablePalette(crtc);
2220     for (i = 0; i < 21; i++)
2221         regp->Attribute[i] = NVReadVgaAttr(crtc, i);
2222     NVDisablePalette(crtc);
2223
2224     for (i = 0; i < 9; i++)
2225         regp->Graphics[i] = NVReadVgaGr(crtc, i);
2226
2227     for (i = 1; i < 5; i++)
2228         regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
2229
2230 }
2231
2232 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2233 {
2234     ScrnInfoPtr pScrn = crtc->scrn;
2235     NVPtr pNv = NVPTR(pScrn);
2236     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2237     NVCrtcRegPtr regp;
2238
2239     regp = &state->crtc_reg[nv_crtc->head];
2240
2241     regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
2242     regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
2243     regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
2244     regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
2245     regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
2246     regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
2247     regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
2248
2249     regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
2250     regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
2251     if(pNv->Architecture >= NV_ARCH_30) {
2252          regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
2253     }
2254     regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
2255     regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
2256     regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
2257     regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
2258
2259     regp->gpio = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO);
2260     regp->unk830 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0830);
2261     regp->unk834 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0834);
2262     regp->unk850 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0850);
2263     regp->unk81c = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_081C);
2264
2265     if(pNv->Architecture >= NV_ARCH_10) {
2266         if(pNv->twoHeads) {
2267            regp->head     = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL);
2268            regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
2269         }
2270         regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
2271
2272         regp->cursorConfig = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG);
2273
2274         regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
2275         regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
2276         regp->CRTC[NV_VGA_CRTCX_3C] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3C);
2277         regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
2278         regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
2279         regp->CRTC[NV_VGA_CRTCX_56] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_56);
2280         regp->CRTC[NV_VGA_CRTCX_57] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_57);
2281         regp->CRTC[NV_VGA_CRTCX_58] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_58);
2282         regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
2283         regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
2284         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
2285         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
2286     }
2287 }
2288
2289 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2290 {
2291         ScrnInfoPtr pScrn = crtc->scrn;
2292         NVPtr pNv = NVPTR(pScrn);
2293         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2294         NVCrtcRegPtr regp;
2295         int i;
2296
2297         regp = &state->crtc_reg[nv_crtc->head];
2298
2299         regp->general = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL);
2300
2301         regp->fp_control        = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL);
2302         regp->debug_0   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0);
2303         regp->debug_1   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1);
2304         regp->debug_2   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2);
2305
2306         regp->unk_a20 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20);
2307         regp->unk_a24 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24);
2308         regp->unk_a34 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34);
2309
2310         if (pNv->NVArch == 0x11) {
2311                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11);
2312         } else if (pNv->twoHeads) {
2313                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER);
2314         }
2315         regp->nv10_cursync = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC);
2316
2317         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2318
2319         for (i = 0; i < 7; i++) {
2320                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2321                 regp->fp_horiz_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2322         }
2323
2324         for (i = 0; i < 7; i++) {
2325                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2326                 regp->fp_vert_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2327         }
2328
2329         regp->fp_hvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START);
2330         regp->fp_hvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END);
2331         regp->fp_vvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START);
2332         regp->fp_vvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END);
2333 }
2334
2335 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2336 {
2337         ScrnInfoPtr pScrn = crtc->scrn;
2338         NVPtr pNv = NVPTR(pScrn);
2339         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2340         NVCrtcRegPtr regp;
2341         int i;
2342
2343         regp = &state->crtc_reg[nv_crtc->head];
2344
2345         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL, regp->general);
2346
2347         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control);
2348         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0, regp->debug_0);
2349         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
2350         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
2351
2352         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20, regp->unk_a20);
2353         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24, regp->unk_a24);
2354         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34, regp->unk_a34);
2355
2356         if (pNv->NVArch == 0x11) {
2357                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11, regp->dither);
2358         } else if (pNv->twoHeads) {
2359                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER, regp->dither);
2360         }
2361         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
2362
2363         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2364
2365         for (i = 0; i < 7; i++) {
2366                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2367                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_horiz_regs[i]);
2368         }
2369
2370         for (i = 0; i < 7; i++) {
2371                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2372                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_vert_regs[i]);
2373         }
2374
2375         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START, regp->fp_hvalid_start);
2376         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END, regp->fp_hvalid_end);
2377         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START, regp->fp_vvalid_start);
2378         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END, regp->fp_vvalid_end);
2379 }
2380
2381 void
2382 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y)
2383 {
2384         ScrnInfoPtr pScrn = crtc->scrn;
2385         NVPtr pNv = NVPTR(pScrn);
2386         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2387         NVFBLayout *pLayout = &pNv->CurrentLayout;
2388         CARD32 start = 0;
2389
2390         ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
2391
2392         start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
2393         start += pNv->FB->offset;
2394
2395         /* 30 bits addresses in 32 bits according to haiku */
2396         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_START, start & 0xfffffffc);
2397
2398         /* set NV4/NV10 byte adress: (bit0 - 1) */
2399         NVWriteVgaAttr(crtc, 0x13, (start & 0x3) << 1);
2400
2401         crtc->x = x;
2402         crtc->y = y;
2403 }
2404
2405 static void NVCrtcWriteDacMask(xf86CrtcPtr crtc, CARD8 value)
2406 {
2407   ScrnInfoPtr pScrn = crtc->scrn;
2408   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2409   NVPtr pNv = NVPTR(pScrn);
2410   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2411
2412   NV_WR08(pDACReg, VGA_DAC_MASK, value);
2413 }
2414
2415 static CARD8 NVCrtcReadDacMask(xf86CrtcPtr crtc)
2416 {
2417   ScrnInfoPtr pScrn = crtc->scrn;
2418   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2419   NVPtr pNv = NVPTR(pScrn);
2420   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2421
2422   return NV_RD08(pDACReg, VGA_DAC_MASK);
2423 }
2424
2425 static void NVCrtcWriteDacReadAddr(xf86CrtcPtr crtc, CARD8 value)
2426 {
2427   ScrnInfoPtr pScrn = crtc->scrn;
2428   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2429   NVPtr pNv = NVPTR(pScrn);
2430   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2431
2432   NV_WR08(pDACReg, VGA_DAC_READ_ADDR, value);
2433 }
2434
2435 static void NVCrtcWriteDacWriteAddr(xf86CrtcPtr crtc, CARD8 value)
2436 {
2437   ScrnInfoPtr pScrn = crtc->scrn;
2438   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2439   NVPtr pNv = NVPTR(pScrn);
2440   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2441
2442   NV_WR08(pDACReg, VGA_DAC_WRITE_ADDR, value);
2443 }
2444
2445 static void NVCrtcWriteDacData(xf86CrtcPtr crtc, CARD8 value)
2446 {
2447   ScrnInfoPtr pScrn = crtc->scrn;
2448   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2449   NVPtr pNv = NVPTR(pScrn);
2450   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2451
2452   NV_WR08(pDACReg, VGA_DAC_DATA, value);
2453 }
2454
2455 static CARD8 NVCrtcReadDacData(xf86CrtcPtr crtc, CARD8 value)
2456 {
2457   ScrnInfoPtr pScrn = crtc->scrn;
2458   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2459   NVPtr pNv = NVPTR(pScrn);
2460   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2461
2462   return NV_RD08(pDACReg, VGA_DAC_DATA);
2463 }
2464
2465 void NVCrtcLoadPalette(xf86CrtcPtr crtc)
2466 {
2467         int i;
2468         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2469         NVCrtcRegPtr regp;
2470         ScrnInfoPtr pScrn = crtc->scrn;
2471         NVPtr pNv = NVPTR(pScrn);
2472
2473         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2474
2475         NVCrtcSetOwner(crtc);
2476         NVCrtcWriteDacMask(crtc, 0xff);
2477         NVCrtcWriteDacWriteAddr(crtc, 0x00);
2478
2479         for (i = 0; i<768; i++) {
2480                 NVCrtcWriteDacData(crtc, regp->DAC[i]);
2481         }
2482         NVDisablePalette(crtc);
2483 }
2484
2485 void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
2486 {
2487         unsigned char scrn;
2488
2489         NVCrtcSetOwner(crtc);
2490
2491         scrn = NVReadVgaSeq(crtc, 0x01);
2492         if (on) {
2493                 scrn &= ~0x20;
2494         } else {
2495                 scrn |= 0x20;
2496         }
2497
2498         NVVgaSeqReset(crtc, TRUE);
2499         NVWriteVgaSeq(crtc, 0x01, scrn);
2500         NVVgaSeqReset(crtc, FALSE);
2501 }
2502
2503 /*************************************************************************** \
2504 |*                                                                           *|
2505 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
2506 |*                                                                           *|
2507 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
2508 |*     international laws.  Users and possessors of this source code are     *|
2509 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
2510 |*     use this code in individual and commercial software.                  *|
2511 |*                                                                           *|
2512 |*     Any use of this source code must include,  in the user documenta-     *|
2513 |*     tion and  internal comments to the code,  notices to the end user     *|
2514 |*     as follows:                                                           *|
2515 |*                                                                           *|
2516 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
2517 |*                                                                           *|
2518 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
2519 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
2520 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
2521 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
2522 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
2523 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
2524 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
2525 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
2526 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
2527 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
2528 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
2529 |*                                                                           *|
2530 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
2531 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
2532 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
2533 |*     computer  software  documentation,"  as such  terms  are  used in     *|
2534 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
2535 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
2536 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
2537 |*     all U.S. Government End Users  acquire the source code  with only     *|
2538 |*     those rights set forth herein.                                        *|
2539 |*                                                                           *|
2540  \***************************************************************************/