git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 2006 Dave Airlie
   3  * Copyright 2007 Maarten Maathuis
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
  26  * decleration is at the bottom of this file as it is rather ugly
  27  */
  28
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include <assert.h>
  34 #include "xf86.h"
  35 #include "os.h"
  36 #include "mibank.h"
  37 #include "globals.h"
  38 #include "xf86.h"
  39 #include "xf86Priv.h"
  40 #include "xf86DDC.h"
  41 #include "mipointer.h"
  42 #include "windowstr.h"
  43 #include <randrstr.h>
  44 #include <X11/extensions/render.h>
  45
  46 #include "xf86Crtc.h"
  47 #include "nv_include.h"
  48
  49 #include "vgaHW.h"
  50
  51 #define CRTC_INDEX 0x3d4
  52 #define CRTC_DATA 0x3d5
  53 #define CRTC_IN_STAT_1 0x3da
  54
  55 #define WHITE_VALUE 0x3F
  56 #define BLACK_VALUE 0x00
  57 #define OVERSCAN_VALUE 0x01
  58
  59 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  60 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override);
  61 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  62 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  63 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  64 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  65
  66 static uint8_t NVReadPVIO(xf86CrtcPtr crtc, uint32_t address)
  67 {
  68         ScrnInfoPtr pScrn = crtc->scrn;
  69         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  70         NVPtr pNv = NVPTR(pScrn);
  71
  72         /* Only NV4x have two pvio ranges */
  73         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  74                 return NV_RD08(pNv->PVIO1, address);
  75         } else {
  76                 return NV_RD08(pNv->PVIO0, address);
  77         }
  78 }
  79
  80 static void NVWritePVIO(xf86CrtcPtr crtc, uint32_t address, uint8_t value)
  81 {
  82         ScrnInfoPtr pScrn = crtc->scrn;
  83         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  84         NVPtr pNv = NVPTR(pScrn);
  85
  86         /* Only NV4x have two pvio ranges */
  87         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  88                 NV_WR08(pNv->PVIO1, address, value);
  89         } else {
  90                 NV_WR08(pNv->PVIO0, address, value);
  91         }
  92 }
  93
  94 static void NVWriteMiscOut(xf86CrtcPtr crtc, uint8_t value)
  95 {
  96 #ifdef NOUVEAU_MODESET_TRACE
  97         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  98         ErrorF("NVWriteMiscOut: value: 0x%X head: %d\n", value, nv_crtc->head);
  99 #endif
 100         NVWritePVIO(crtc, VGA_MISC_OUT_W, value);
 101 }
 102
 103 static uint8_t NVReadMiscOut(xf86CrtcPtr crtc)
 104 {
 105         return NVReadPVIO(crtc, VGA_MISC_OUT_R);
 106 }
 107
 108 void NVWriteVGA(NVPtr pNv, int head, uint8_t index, uint8_t value)
 109 {
 110         volatile uint8_t *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 111
 112 #ifdef NOUVEAU_MODESET_TRACE
 113         ErrorF("NVWriteVGA: index: 0x%X data: 0x%X head: %d\n", index, value, head);
 114 #endif
 115
 116         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 117         NV_WR08(pCRTCReg, CRTC_DATA, value);
 118 }
 119
 120 uint8_t NVReadVGA(NVPtr pNv, int head, uint8_t index)
 121 {
 122         volatile uint8_t *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 123
 124         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 125         return NV_RD08(pCRTCReg, CRTC_DATA);
 126 }
 127
 128 /* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
 129  * I suspect they in fact do nothing, but are merely a way to carry useful
 130  * per-head variables around
 131  *
 132  * Known uses:
 133  * CR57         CR58
 134  * 0x00         index to the appropriate dcb entry (or 7f for inactive)
 135  * 0x02         dcb entry's "or" value (or 00 for inactive)
 136  * 0x03         bit0 set for dual link (LVDS, possibly elsewhere too)
 137  * 0x08 or 0x09 pxclk in MHz
 138  * 0x0f         laptop panel info -     low nibble for PEXTDEV_BOOT strap
 139  *                                      high nibble for xlat strap value
 140  */
 141
 142 void NVWriteVGACR5758(NVPtr pNv, int head, uint8_t index, uint8_t value)
 143 {
 144         NVWriteVGA(pNv, head, 0x57, index);
 145         NVWriteVGA(pNv, head, 0x58, value);
 146 }
 147
 148 uint8_t NVReadVGACR5758(NVPtr pNv, int head, uint8_t index)
 149 {
 150         NVWriteVGA(pNv, head, 0x57, index);
 151         return NVReadVGA(pNv, head, 0x58);
 152 }
 153
 154 void NVWriteVgaCrtc(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 155 {
 156         ScrnInfoPtr pScrn = crtc->scrn;
 157         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 158         NVPtr pNv = NVPTR(pScrn);
 159
 160         NVWriteVGA(pNv, nv_crtc->head, index, value);
 161 }
 162
 163 uint8_t NVReadVgaCrtc(xf86CrtcPtr crtc, uint8_t index)
 164 {
 165         ScrnInfoPtr pScrn = crtc->scrn;
 166         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 167         NVPtr pNv = NVPTR(pScrn);
 168
 169         return NVReadVGA(pNv, nv_crtc->head, index);
 170 }
 171
 172 static void NVWriteVgaSeq(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 173 {
 174 #ifdef NOUVEAU_MODESET_TRACE
 175         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 176         ErrorF("NVWriteVgaSeq: index: 0x%X value: 0x%x head %d\n", index, value, nv_crtc->head);
 177 #endif
 178         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 179         NVWritePVIO(crtc, VGA_SEQ_DATA, value);
 180 }
 181
 182 static uint8_t NVReadVgaSeq(xf86CrtcPtr crtc, uint8_t index)
 183 {
 184         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 185         return NVReadPVIO(crtc, VGA_SEQ_DATA);
 186 }
 187
 188 static void NVWriteVgaGr(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 189 {
 190 #ifdef NOUVEAU_MODESET_TRACE
 191         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 192         ErrorF("NVWriteVgaGr: index: 0x%X value: 0x%x head %d\n", index, value, nv_crtc->head);
 193 #endif
 194         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 195         NVWritePVIO(crtc, VGA_GRAPH_DATA, value);
 196 }
 197
 198 static uint8_t NVReadVgaGr(xf86CrtcPtr crtc, uint8_t index)
 199 {
 200         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 201         return NVReadPVIO(crtc, VGA_GRAPH_DATA);
 202 }
 203
 204
 205 static void NVWriteVgaAttr(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 206 {
 207         ScrnInfoPtr pScrn = crtc->scrn;
 208         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 209         NVPtr pNv = NVPTR(pScrn);
 210         volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 211
 212         NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 213         if (nv_crtc->paletteEnabled)
 214                 index &= ~0x20;
 215         else
 216                 index |= 0x20;
 217 #ifdef NOUVEAU_MODESET_TRACE
 218         ErrorF("NVWriteVgaAttr: index: 0x%X value: 0x%X head: %d\n", index, value, nv_crtc->head);
 219 #endif
 220         NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 221         NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
 222 }
 223
 224 static uint8_t NVReadVgaAttr(xf86CrtcPtr crtc, uint8_t index)
 225 {
 226   ScrnInfoPtr pScrn = crtc->scrn;
 227   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 228   NVPtr pNv = NVPTR(pScrn);
 229   volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 230
 231   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 232   if (nv_crtc->paletteEnabled)
 233     index &= ~0x20;
 234   else
 235     index |= 0x20;
 236   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 237   return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
 238 }
 239
 240 static void NVCrtcSetOwner(xf86CrtcPtr crtc)
 241 {
 242         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 243         ScrnInfoPtr pScrn = crtc->scrn;
 244         NVPtr pNv = NVPTR(pScrn);
 245         /* Non standard beheaviour required by NV11 */
 246         if (pNv) {
 247                 uint8_t owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 248                 ErrorF("pre-Owner: 0x%X\n", owner);
 249                 if (owner == 0x04) {
 250                         uint32_t pbus84 = nvReadMC(pNv, 0x1084);
 251                         ErrorF("pbus84: 0x%X\n", pbus84);
 252                         pbus84 &= ~(1<<28);
 253                         ErrorF("pbus84: 0x%X\n", pbus84);
 254                         nvWriteMC(pNv, 0x1084, pbus84);
 255                 }
 256                 /* The blob never writes owner to pcio1, so should we */
 257                 if (pNv->NVArch == 0x11) {
 258                         NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, 0xff);
 259                 }
 260                 NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, nv_crtc->head * 0x3);
 261                 owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 262                 ErrorF("post-Owner: 0x%X\n", owner);
 263         } else {
 264                 ErrorF("pNv pointer is NULL\n");
 265         }
 266 }
 267
 268 static void
 269 NVEnablePalette(xf86CrtcPtr crtc)
 270 {
 271   ScrnInfoPtr pScrn = crtc->scrn;
 272   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 273   NVPtr pNv = NVPTR(pScrn);
 274   volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 275
 276   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 277   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
 278   nv_crtc->paletteEnabled = TRUE;
 279 }
 280
 281 static void
 282 NVDisablePalette(xf86CrtcPtr crtc)
 283 {
 284   ScrnInfoPtr pScrn = crtc->scrn;
 285   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 286   NVPtr pNv = NVPTR(pScrn);
 287   volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 288
 289   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 290   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
 291   nv_crtc->paletteEnabled = FALSE;
 292 }
 293
 294 static void NVWriteVgaReg(xf86CrtcPtr crtc, uint32_t reg, uint8_t value)
 295 {
 296  ScrnInfoPtr pScrn = crtc->scrn;
 297   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 298   NVPtr pNv = NVPTR(pScrn);
 299   volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 300
 301   NV_WR08(pCRTCReg, reg, value);
 302 }
 303
 304 /* perform a sequencer reset */
 305 static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
 306 {
 307   if (start)
 308     NVWriteVgaSeq(crtc, 0x00, 0x1);
 309   else
 310     NVWriteVgaSeq(crtc, 0x00, 0x3);
 311
 312 }
 313 static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
 314 {
 315         uint8_t tmp;
 316
 317         if (on) {
 318                 tmp = NVReadVgaSeq(crtc, 0x1);
 319                 NVVgaSeqReset(crtc, TRUE);
 320                 NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
 321
 322                 NVEnablePalette(crtc);
 323         } else {
 324                 /*
 325                  * Reenable sequencer, then turn on screen.
 326                  */
 327                 tmp = NVReadVgaSeq(crtc, 0x1);
 328                 NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20); /* reenable display */
 329                 NVVgaSeqReset(crtc, FALSE);
 330
 331                 NVDisablePalette(crtc);
 332         }
 333 }
 334
 335 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool Lock)
 336 {
 337         NVPtr pNv = NVPTR(crtc->scrn);
 338         uint8_t cr11;
 339
 340         if (pNv->twoHeads)
 341                 NVCrtcSetOwner(crtc);
 342
 343         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57);
 344         cr11 = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE);
 345         if (Lock) cr11 |= 0x80;
 346         else cr11 &= ~0x80;
 347         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE, cr11);
 348 }
 349
 350 xf86OutputPtr
 351 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
 352 {
 353         ScrnInfoPtr pScrn = crtc->scrn;
 354         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 355         int i;
 356         for (i = 0; i < xf86_config->num_output; i++) {
 357                 xf86OutputPtr output = xf86_config->output[i];
 358
 359                 if (output->crtc == crtc) {
 360                         return output;
 361                 }
 362         }
 363
 364         return NULL;
 365 }
 366
 367 xf86CrtcPtr
 368 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
 369 {
 370         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 371         int i;
 372
 373         for (i = 0; i < xf86_config->num_crtc; i++) {
 374                 xf86CrtcPtr crtc = xf86_config->crtc[i];
 375                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 376                 if (nv_crtc->head == index)
 377                         return crtc;
 378         }
 379
 380         return NULL;
 381 }
 382
 383 /*
 384  * Calculate the Video Clock parameters for the PLL.
 385  */
 386 /* Code taken from NVClock, with permission of the author (being a GPL->MIT code transfer). */
 387
 388 static void
 389 CalculateVClkNV4x_SingleVCO(NVPtr pNv, struct pll_lims *pll_lim, uint32_t clockIn, uint32_t *n1_best, uint32_t *m1_best, uint32_t *p_best)
 390 {
 391         uint32_t clock, M, N, P;
 392         uint32_t delta, bestDelta, minM, maxM, minN, maxN, maxP;
 393         uint32_t minVCOInputFreq, minVCOFreq, maxVCOFreq;
 394         uint32_t VCOFreq;
 395         uint32_t refClk = pNv->CrystalFreqKHz;
 396         bestDelta = clockIn;
 397
 398         minVCOInputFreq = pll_lim->vco1.min_inputfreq;
 399         minVCOFreq = pll_lim->vco1.minfreq;
 400         maxVCOFreq = pll_lim->vco1.maxfreq;
 401         minM = pll_lim->vco1.min_m;
 402         maxM = pll_lim->vco1.max_m;
 403         minN = pll_lim->vco1.min_n;
 404         maxN = pll_lim->vco1.max_n;
 405
 406         maxP = 6;
 407
 408         /* The optimal frequency for the PLL to work at is somewhere in the center of its range.
 409         /  Choose a post divider in such a way to achieve this.
 410         /  The G8x nv driver does something similar but they they derive a minP and maxP. That
 411         /  doesn't seem required as you get so many matching clocks that you don't enter a second
 412         /  iteration for P. (The minP / maxP values in the nv driver only differ at most 1, so it is for
 413         /  some rare corner cases.
 414         */
 415         for (P=0, VCOFreq=maxVCOFreq/2; clockIn<=VCOFreq && P <= maxP; P++)
 416         {
 417                 VCOFreq /= 2;
 418         }
 419
 420         /* Calculate the m and n values. There are a lot of values which give the same speed;
 421         /  We choose the speed for which the difference with the request speed is as small as possible.
 422         */
 423         for (M=minM; M<=maxM; M++)
 424         {
 425                 /* The VCO has a minimum input frequency */
 426                 if ((refClk/M) < minVCOInputFreq)
 427                         break;
 428
 429                 for (N=minN; N<=maxN; N++)
 430                 {
 431                         /* Calculate the frequency generated by VCO1 */
 432                         clock = (int)(refClk * N / (float)M);
 433
 434                         /* Verify if the clock lies within the output limits of VCO1 */
 435                         if (clock < minVCOFreq)
 436                                 continue;
 437                         else if (clock > maxVCOFreq) /* It is no use to continue as the clock will only become higher */
 438                                 break;
 439
 440                         clock >>= P;
 441                         delta = abs((int)(clockIn - clock));
 442                         /* When the difference is 0 or less than .5% accept the speed */
 443                         if (((delta == 0) || ((float)delta/(float)clockIn <= 0.005)))
 444                         {
 445                                 *m1_best = M;
 446                                 *n1_best = N;
 447                                 *p_best = P;
 448                                 return;
 449                         }
 450
 451                         /* When the new difference is smaller than the old one, use this one */
 452                         if (delta < bestDelta)
 453                         {
 454                                 bestDelta = delta;
 455                                 *m1_best = M;
 456                                 *n1_best = N;
 457                                 *p_best = P;
 458                         }
 459                 }
 460         }
 461 }
 462
 463 static void
 464 CalculateVClkNV4x_DoubleVCO(NVPtr pNv, struct pll_lims *pll_lim, uint32_t clockIn, uint32_t *n1_best, uint32_t *n2_best, uint32_t *m1_best, uint32_t *m2_best, uint32_t *p_best)
 465 {
 466         uint32_t clock1, clock2, M, M2, N, N2, P;
 467         uint32_t delta, bestDelta, minM, minM2, maxM, maxM2, minN, minN2, maxN, maxN2, maxP;
 468         uint32_t minVCOInputFreq, minVCO2InputFreq, maxVCO2InputFreq, minVCOFreq, minVCO2Freq, maxVCOFreq, maxVCO2Freq;
 469         uint32_t VCO2Freq, maxClock;
 470         uint32_t refClk = pNv->CrystalFreqKHz;
 471         bestDelta = clockIn;
 472
 473         minVCOInputFreq = pll_lim->vco1.min_inputfreq;
 474         minVCOFreq = pll_lim->vco1.minfreq;
 475         maxVCOFreq = pll_lim->vco1.maxfreq;
 476         minM = pll_lim->vco1.min_m;
 477         maxM = pll_lim->vco1.max_m;
 478         minN = pll_lim->vco1.min_n;
 479         maxN = pll_lim->vco1.max_n;
 480
 481         minVCO2InputFreq = pll_lim->vco2.min_inputfreq;
 482         maxVCO2InputFreq = pll_lim->vco2.max_inputfreq;
 483         minVCO2Freq = pll_lim->vco2.minfreq;
 484         maxVCO2Freq = pll_lim->vco2.maxfreq;
 485         minM2 = pll_lim->vco2.min_m;
 486         maxM2 = pll_lim->vco2.max_m;
 487         minN2 = pll_lim->vco2.min_n;
 488         maxN2 = pll_lim->vco2.max_n;
 489
 490         maxP = 6;
 491
 492         maxClock = maxVCO2Freq;
 493         /* If the requested clock is behind the bios limits, try it anyway */
 494         if (clockIn > maxVCO2Freq)
 495                 maxClock = clockIn + clockIn/200; /* Add a .5% margin */
 496
 497         /* The optimal frequency for the PLL to work at is somewhere in the center of its range.
 498         /  Choose a post divider in such a way to achieve this.
 499         /  The G8x nv driver does something similar but they they derive a minP and maxP. That
 500         /  doesn't seem required as you get so many matching clocks that you don't enter a second
 501         /  iteration for P. (The minP / maxP values in the nv driver only differ at most 1, so it is for
 502         /  some rare corner cases.
 503         */
 504         for (P=0, VCO2Freq=maxClock/2; clockIn<=VCO2Freq && P <= maxP; P++)
 505         {
 506                 VCO2Freq /= 2;
 507         }
 508
 509         /* The PLLs on Geforce6/7 hardware can operate in a single stage made with only 1 VCO
 510         /  and a cascade mode of two VCOs. This second mode is in general used for relatively high
 511         /  frequencies. The loop below calculates the divider and multiplier ratios for the cascade
 512         /  mode. The code takes into account limits defined in the video bios.
 513         */
 514         for (M=minM; M<=maxM; M++)
 515         {
 516                 /* The VCO has a minimum input frequency */
 517                 if ((refClk/M) < minVCOInputFreq)
 518                         break;
 519
 520                 for (N=minN; N<=maxN; N++)
 521                 {
 522                         /* Calculate the frequency generated by VCO1 */
 523                         clock1 = (int)(refClk * N / (float)M);
 524                         /* Verify if the clock lies within the output limits of VCO1 */
 525                         if ( (clock1 < minVCOFreq) )
 526                                 continue;
 527                         else if (clock1 > maxVCOFreq) /* For future N, the clock will only increase so stop; xorg nv continues but that is useless */
 528                                 break;
 529
 530                         for (M2=minM2; M2<=maxM2; M2++)
 531                         {
 532                                 /* The clock fed to the second VCO needs to lie within a certain input range */
 533                                 if (clock1 / M2 < minVCO2InputFreq)
 534                                         break;
 535                                 else if (clock1 / M2 > maxVCO2InputFreq)
 536                                         continue;
 537
 538                                 N2 = (int)((float)((clockIn << P) * M * M2) / (float)(refClk * N)+.5);
 539                                 if( (N2 < minN2) || (N2 > maxN2) )
 540                                         continue;
 541
 542                                 /* The clock before being fed to the post-divider needs to lie within a certain range.
 543                                 /  Further there are some limits on N2/M2.
 544                                 */
 545                                 clock2 = (int)((float)(N*N2)/(M*M2) * refClk);
 546                                 if( (clock2 < minVCO2Freq) || (clock2 > maxClock))// || ((N2 / M2) < 4) || ((N2 / M2) > 10) )
 547                                         continue;
 548
 549                                 /* The post-divider delays the 'high' clock to create a low clock if requested.
 550                                 /  This post-divider exists because the VCOs can only generate frequencies within
 551                                 /  a limited frequency range. This range has been tuned to lie around half of its max
 552                                 /  input frequency. It tries to calculate all clocks (including lower ones) around this
 553                                 /  'center' frequency.
 554                                 */
 555                                 clock2 >>= P;
 556                                 delta = abs((int)(clockIn - clock2));
 557
 558                                 /* When the difference is 0 or less than .5% accept the speed */
 559                                 if (((delta == 0) || ((float)delta/(float)clockIn <= 0.005)))
 560                                 {
 561                                         *m1_best = M;
 562                                         *m2_best = M2;
 563                                         *n1_best = N;
 564                                         *n2_best = N2;
 565                                         *p_best = P;
 566                                         return;
 567                                 }
 568
 569                                 /* When the new difference is smaller than the old one, use this one */
 570                                 if (delta < bestDelta)
 571                                 {
 572                                         bestDelta = delta;
 573                                         *m1_best = M;
 574                                         *m2_best = M2;
 575                                         *n1_best = N;
 576                                         *n2_best = N2;
 577                                         *p_best = P;
 578                                 }
 579                         }
 580                 }
 581         }
 582 }
 583
 584 /* BIG NOTE: modifying vpll1 and vpll2 does not work, what bit is the switch to allow it? */
 585
 586 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
 587 /* They are only valid for NV4x, appearantly reordered for NV5x */
 588 /* gpu pll: 0x4000 + 0x4004
 589  * unknown pll: 0x4008 + 0x400c
 590  * vpll1: 0x4010 + 0x4014
 591  * vpll2: 0x4018 + 0x401c
 592  * unknown pll: 0x4020 + 0x4024
 593  * unknown pll: 0x4038 + 0x403c
 594  * Some of the unknown's are probably memory pll's.
 595  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
 596  * 1 and 2 refer to the registers of each pair. There is only one post divider.
 597  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
 598  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
 599  *     bit8: A switch that turns of the second divider and multiplier off.
 600  *     bit12: Also a switch, i haven't seen it yet.
 601  *     bit16-19: p-divider
 602  *     but 28-31: Something related to the mode that is used (see bit8).
 603  * 2) bit0-7: m-divider (a)
 604  *     bit8-15: n-multiplier (a)
 605  *     bit16-23: m-divider (b)
 606  *     bit24-31: n-multiplier (b)
 607  */
 608
 609 /* Modifying the gpu pll for example requires:
 610  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 611  * This is not needed for the vpll's which have their own bits.
 612  */
 613
 614 static void
 615 CalculateVClkNV4x(
 616         ScrnInfoPtr pScrn,
 617         uint32_t requested_clock,
 618         uint32_t *given_clock,
 619         uint32_t *pll_a,
 620         uint32_t *pll_b,
 621         uint32_t *reg580,
 622         Bool    *db1_ratio,
 623         Bool primary
 624 )
 625 {
 626         NVPtr pNv = NVPTR(pScrn);
 627         struct pll_lims pll_lim;
 628         /* We have 2 mulitpliers, 2 dividers and one post divider */
 629         /* Note that p is only 3 bits */
 630         uint32_t m1_best = 0, m2_best = 0, n1_best = 0, n2_best = 0, p_best = 0;
 631         uint32_t special_bits = 0;
 632
 633         if (primary) {
 634                 if (!get_pll_limits_plltype(pScrn, VPLL1, &pll_lim))
 635                         return;
 636         } else
 637                 if (!get_pll_limits_plltype(pScrn, VPLL2, &pll_lim))
 638                         return;
 639
 640         if (requested_clock < pll_lim.vco1.maxfreq && pNv->NVArch > 0x40) { /* single VCO */
 641                 *db1_ratio = TRUE;
 642                 /* Turn the second set of divider and multiplier off */
 643                 /* Bogus data, the same nvidia uses */
 644                 n2_best = 1;
 645                 m2_best = 31;
 646                 CalculateVClkNV4x_SingleVCO(pNv, &pll_lim, requested_clock, &n1_best, &m1_best, &p_best);
 647         } else { /* dual VCO */
 648                 *db1_ratio = FALSE;
 649                 CalculateVClkNV4x_DoubleVCO(pNv, &pll_lim, requested_clock, &n1_best, &n2_best, &m1_best, &m2_best, &p_best);
 650         }
 651
 652         /* Are this all (relevant) G70 cards? */
 653         if (pNv->NVArch == 0x4B || pNv->NVArch == 0x46 || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
 654                 /* This is a big guess, but should be reasonable until we can narrow it down. */
 655                 if (*db1_ratio) {
 656                         special_bits = 0x1;
 657                 } else {
 658                         special_bits = 0x3;
 659                 }
 660         }
 661
 662         /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
 663         *pll_a = (special_bits << 30) | (p_best << 16) | (n1_best << 8) | (m1_best << 0);
 664         /* This VCO2 bit is an educated guess, but it needs to stay on for NV4x. */
 665         *pll_b = NV31_RAMDAC_ENABLE_VCO2 | (n2_best << 8) | (m2_best << 0);
 666
 667         if (*db1_ratio) {
 668                 if (primary) {
 669                         *reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 670                 } else {
 671                         *reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 672                 }
 673         } else {
 674                 if (primary) {
 675                         *reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
 676                 } else {
 677                         *reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
 678                 }
 679         }
 680
 681         if (*db1_ratio) {
 682                 ErrorF("vpll: n1 %d m1 %d p %d db1_ratio %d\n", n1_best, m1_best, p_best, *db1_ratio);
 683         } else {
 684                 ErrorF("vpll: n1 %d n2 %d m1 %d m2 %d p %d db1_ratio %d\n", n1_best, n2_best, m1_best, m2_best, p_best, *db1_ratio);
 685         }
 686 }
 687
 688 static void nv40_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 689 {
 690         state->vpll1_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 691         state->vpll1_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 692         state->vpll2_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 693         state->vpll2_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 694         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 695         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 696         state->reg580 = nvReadRAMDAC0(pNv, NV_RAMDAC_580);
 697         state->reg594 = nvReadRAMDAC0(pNv, NV_RAMDAC_594);
 698 }
 699
 700 static void nv40_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 701 {
 702         ScrnInfoPtr pScrn = crtc->scrn;
 703         NVPtr pNv = NVPTR(pScrn);
 704         uint32_t fp_debug_0[2];
 705         uint32_t index[2];
 706         fp_debug_0[0] = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
 707         fp_debug_0[1] = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
 708
 709         /* The TMDS_PLL switch is on the actual ramdac */
 710         if (state->crosswired) {
 711                 index[0] = 1;
 712                 index[1] = 0;
 713                 ErrorF("Crosswired pll state load\n");
 714         } else {
 715                 index[0] = 0;
 716                 index[1] = 1;
 717         }
 718
 719         if (state->vpll2_b && state->vpll_changed[1]) {
 720                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0,
 721                         fp_debug_0[index[1]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 722
 723                 /* Wait for the situation to stabilise */
 724                 usleep(5000);
 725
 726                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 727                 /* for vpll2 change bits 18 and 19 are disabled */
 728                 reg_c040 &= ~(0x3 << 18);
 729                 nvWriteMC(pNv, 0xc040, reg_c040);
 730
 731                 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 732                 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 733
 734                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2_a);
 735                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 736
 737                 ErrorF("writing pllsel %08X\n", state->pllsel);
 738                 /* Don't turn vpll1 off. */
 739                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 740
 741                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 742                 ErrorF("writing reg580 %08X\n", state->reg580);
 743
 744                 /* We need to wait a while */
 745                 usleep(5000);
 746                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 747
 748                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[1]]);
 749
 750                 /* Wait for the situation to stabilise */
 751                 usleep(5000);
 752         }
 753
 754         if (state->vpll1_b && state->vpll_changed[0]) {
 755                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0,
 756                         fp_debug_0[index[0]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 757
 758                 /* Wait for the situation to stabilise */
 759                 usleep(5000);
 760
 761                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 762                 /* for vpll2 change bits 16 and 17 are disabled */
 763                 reg_c040 &= ~(0x3 << 16);
 764                 nvWriteMC(pNv, 0xc040, reg_c040);
 765
 766                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 767                 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 768
 769                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll1_a);
 770                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpll1_b);
 771
 772                 ErrorF("writing pllsel %08X\n", state->pllsel);
 773                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 774
 775                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 776                 ErrorF("writing reg580 %08X\n", state->reg580);
 777
 778                 /* We need to wait a while */
 779                 usleep(5000);
 780                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 781
 782                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[0]]);
 783
 784                 /* Wait for the situation to stabilise */
 785                 usleep(5000);
 786         }
 787
 788         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 789         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 790
 791         ErrorF("writing reg594 %08X\n", state->reg594);
 792         nvWriteRAMDAC0(pNv, NV_RAMDAC_594, state->reg594);
 793
 794         /* All clocks have been set at this point. */
 795         state->vpll_changed[0] = FALSE;
 796         state->vpll_changed[1] = FALSE;
 797 }
 798
 799 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 800 {
 801         state->vpll1_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 802         if (pNv->twoHeads) {
 803                 state->vpll2_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 804         }
 805         if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 806                 state->vpll1_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 807                 state->vpll2_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 808         }
 809         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 810         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 811 }
 812
 813
 814 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 815 {
 816         /* This sequence is important, the NV28 is very sensitive in this area. */
 817         /* Keep pllsel last and sel_clk first. */
 818         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 819         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 820
 821         if (state->vpll2_a && state->vpll_changed[1]) {
 822                 if (pNv->twoHeads) {
 823                         ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 824                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2_a);
 825                 }
 826                 if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 827                         ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 828                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 829                 }
 830         }
 831
 832         if (state->vpll1_a && state->vpll_changed[0]) {
 833                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 834                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll1_a);
 835                 if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 836                         ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 837                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpll1_b);
 838                 }
 839         }
 840
 841         ErrorF("writing pllsel %08X\n", state->pllsel);
 842         nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 843
 844         /* All clocks have been set at this point. */
 845         state->vpll_changed[0] = FALSE;
 846         state->vpll_changed[1] = FALSE;
 847 }
 848
 849 #define IS_NV44P (pNv->NVArch >= 0x44 ? 1 : 0)
 850 #define SEL_CLK_OFFSET (nv_get_sel_clk_offset(pNv->NVArch, nv_output->bus))
 851
 852 #define WIPE_OTHER_CLOCKS(_sel_clk, _head, _bus) (nv_wipe_other_clocks(_sel_clk, pNv->NVArch, _head, _bus))
 853
 854 /*
 855  * Calculate extended mode parameters (SVGA) and save in a
 856  * mode state structure.
 857  * State is not specific to a single crtc, but shared.
 858  */
 859 void nv_crtc_calc_state_ext(
 860         xf86CrtcPtr             crtc,
 861         DisplayModePtr  mode,
 862         int                             bpp,
 863         int                             DisplayWidth, /* Does this change after setting the mode? */
 864         int                             CrtcHDisplay,
 865         int                             CrtcVDisplay,
 866         int                             dotClock,
 867         int                             flags
 868 )
 869 {
 870         ScrnInfoPtr pScrn = crtc->scrn;
 871         uint32_t pixelDepth, VClk = 0;
 872         uint32_t CursorStart;
 873         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 874         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 875         NVCrtcRegPtr regp;
 876         NVPtr pNv = NVPTR(pScrn);
 877         RIVA_HW_STATE *state;
 878         int num_crtc_enabled, i;
 879         uint32_t old_clock_a = 0, old_clock_b = 0;
 880
 881         state = &pNv->ModeReg;
 882
 883         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 884
 885         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 886         NVOutputPrivatePtr nv_output = NULL;
 887         Bool is_fp = FALSE;
 888         if (output) {
 889                 nv_output = output->driver_private;
 890                 if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)
 891                         is_fp = TRUE;
 892         }
 893
 894         /* Store old clock. */
 895         if (nv_crtc->head == 1) {
 896                 old_clock_a = state->vpll2_a;
 897                 old_clock_b = state->vpll2_b;
 898         } else {
 899                 old_clock_a = state->vpll1_a;
 900                 old_clock_b = state->vpll1_b;
 901         }
 902
 903         /*
 904          * Extended RIVA registers.
 905          */
 906         /* This is pitch related, not mode related. */
 907         pixelDepth = (bpp + 1)/8;
 908         if (pNv->Architecture == NV_ARCH_40) {
 909                 /* Does register 0x580 already have a value? */
 910                 if (!state->reg580) {
 911                         state->reg580 = pNv->misc_info.ramdac_0_reg_580;
 912                 }
 913                 if (nv_crtc->head == 1) {
 914                         CalculateVClkNV4x(pScrn, dotClock, &VClk, &state->vpll2_a, &state->vpll2_b, &state->reg580, &state->db1_ratio[1], FALSE);
 915                 } else {
 916                         CalculateVClkNV4x(pScrn, dotClock, &VClk, &state->vpll1_a, &state->vpll1_b, &state->reg580, &state->db1_ratio[0], TRUE);
 917                 }
 918         } else if (pNv->twoStagePLL) {
 919                 int NM1, NM2, log2P;
 920                 VClk = getMNP_double(pScrn, 0, dotClock, &NM1, &NM2, &log2P);
 921                 if (pNv->NVArch == 0x30) {
 922                         /* See nvregisters.xml for details. */
 923                         state->pll = log2P << 16 | NM1 | (NM2 & 7) << 4 | ((NM2 >> 8) & 7) << 19 | ((NM2 >> 11) & 3) << 24 | NV30_RAMDAC_ENABLE_VCO2;
 924                 } else {
 925                         state->pll = log2P << 16 | NM1;
 926                         state->pllB = NV31_RAMDAC_ENABLE_VCO2 | NM2;
 927                 }
 928         } else {
 929                 int NM, log2P;
 930                 VClk = getMNP_single(pScrn, dotClock, &NM, &log2P);
 931                 state->pll = log2P << 16 | NM;
 932         }
 933
 934         if (pNv->Architecture < NV_ARCH_40) {
 935                 if (nv_crtc->head == 1) {
 936                         state->vpll2_a = state->pll;
 937                         state->vpll2_b = state->pllB;
 938                 } else {
 939                         state->vpll1_a = state->pll;
 940                         state->vpll1_b = state->pllB;
 941                 }
 942         }
 943
 944         /* always reset vpll, just to be sure. */
 945         state->vpll_changed[nv_crtc->head] = TRUE;
 946
 947         switch (pNv->Architecture) {
 948         case NV_ARCH_04:
 949                 nv4UpdateArbitrationSettings(VClk,
 950                                                 pixelDepth * 8,
 951                                                 &(state->arbitration0),
 952                                                 &(state->arbitration1),
 953                                                 pNv);
 954                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
 955                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
 956                 if (flags & V_DBLSCAN)
 957                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 958                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
 959                 state->pllsel   |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
 960                 state->config   = 0x00001114;
 961                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 962                 break;
 963         case NV_ARCH_10:
 964         case NV_ARCH_20:
 965         case NV_ARCH_30:
 966         default:
 967                 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
 968                         ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
 969                         state->arbitration0 = 128;
 970                         state->arbitration1 = 0x0480;
 971                 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
 972                         ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
 973                         nForceUpdateArbitrationSettings(VClk,
 974                                                 pixelDepth * 8,
 975                                                 &(state->arbitration0),
 976                                                 &(state->arbitration1),
 977                                                 pNv);
 978                 } else if (pNv->Architecture < NV_ARCH_30) {
 979                         nv10UpdateArbitrationSettings(VClk,
 980                                                 pixelDepth * 8,
 981                                                 &(state->arbitration0),
 982                                                 &(state->arbitration1),
 983                                                 pNv);
 984                 } else {
 985                         nv30UpdateArbitrationSettings(pNv,
 986                                                 &(state->arbitration0),
 987                                                 &(state->arbitration1));
 988                 }
 989
 990                 if (nv_crtc->head == 1) {
 991                         CursorStart = pNv->Cursor2->offset;
 992                 } else {
 993                         CursorStart = pNv->Cursor->offset;
 994                 }
 995
 996                 if (!NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 997                         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
 998                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
 999                         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
1000                 } else {
1001                         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x0;
1002                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0x0;
1003                         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x0;
1004                 }
1005
1006                 if (flags & V_DBLSCAN)
1007                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
1008
1009                 state->config   = nvReadFB(pNv, NV_PFB_CFG0);
1010                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
1011                 break;
1012         }
1013
1014         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1015                 /* This is a bit of a guess. */
1016                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] |= 0xB8;
1017         }
1018
1019         /* okay do we have 2 CRTCs running ? */
1020         num_crtc_enabled = 0;
1021         for (i = 0; i < xf86_config->num_crtc; i++) {
1022                 if (xf86_config->crtc[i]->enabled) {
1023                         num_crtc_enabled++;
1024                 }
1025         }
1026
1027         ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
1028
1029         /* The main stuff seems to be valid for NV3x also. */
1030         if (pNv->Architecture >= NV_ARCH_30) {
1031                 /* This register is only used on the primary ramdac */
1032                 /* This seems to be needed to select the proper clocks, otherwise bad things happen */
1033
1034                 if (!state->sel_clk)
1035                         state->sel_clk = pNv->misc_info.sel_clk & ~(0xf << 16);
1036
1037                 if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1038                         if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
1039                                 /* bioses are very conservative with regards to sel_clk. */
1040                                 /* At this stage we expect a clean sel_clk value. */
1041                                 if (nv_crtc->head == 1) {
1042                                         if (nv_output->preferred_output == 1) {
1043                                                 state->sel_clk |= (0x4 << 16);
1044                                         } else {
1045                                                 state->sel_clk |= (0x1 << 16);
1046                                         }
1047                                 }
1048                         }
1049                 } else {
1050                         if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
1051                                 /* Only wipe when are a relevant (digital) output. */
1052                                 state->sel_clk &= ~(0xf << 16);
1053                                 Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1054                                 /* Even with two dvi, this should not conflict. */
1055                                 if (crossed_clocks) {
1056                                         state->sel_clk |= (0x1 << 16);
1057                                 } else {
1058                                         state->sel_clk |= (0x4 << 16);
1059                                 }
1060                         }
1061
1062                         /* Some cards, specifically dual dvi/lvds cards set another bitrange.
1063                          * I suspect inverse beheaviour to the normal bitrange, but i am not a 100% certain about this.
1064                          * This is all based on default settings found in mmio-traces.
1065                          * The blob never changes these, as it doesn't run unusual output configurations.
1066                          * It seems to prefer situations that avoid changing these bits (for a good reason?).
1067                          * I still don't know the purpose of value 2, it's similar to 4, but what exactly does it do?
1068                          */
1069
1070                         /* Some extra info:
1071                          * nv30:
1072                          *      bit 0           NVClk spread spectrum on/off
1073                          *      bit 2           MemClk spread spectrum on/off
1074                          *      bit 4           PixClk1 spread spectrum on/off
1075                          *      bit 6           PixClk2 spread spectrum on/off
1076
1077                          *      nv40:
1078                          *      what causes setting of bits not obvious but:
1079                          *      bits 4&5                relate to headA
1080                          *      bits 6&7                relate to headB
1081                         */
1082                         /* Only let digital outputs mess with this, otherwise strange output routings may mess it up. */
1083                         if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
1084                                 if (pNv->Architecture == NV_ARCH_40) {
1085                                         for (i = 0; i < 4; i++) {
1086                                                 uint32_t var = (state->sel_clk & (0xf << 4*i)) >> 4*i;
1087                                                 if (var == 0x1 || var == 0x4) {
1088                                                         state->sel_clk &= ~(0xf << 4*i);
1089                                                         Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1090                                                         if (crossed_clocks) {
1091                                                                 state->sel_clk |= (0x4 << 4*i);
1092                                                         } else {
1093                                                                 state->sel_clk |= (0x1 << 4*i);
1094                                                         }
1095                                                         break; /* This should only occur once. */
1096                                                 }
1097                                         }
1098                                 /* Based on NV31M. */
1099                                 } else if (pNv->Architecture == NV_ARCH_30) {
1100                                         for (i = 0; i < 4; i++) {
1101                                                 uint32_t var = (state->sel_clk & (0xf << 4*i)) >> 4*i;
1102                                                 if (var == 0x4 || var == 0x5) {
1103                                                         state->sel_clk &= ~(0xf << 4*i);
1104                                                         Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1105                                                         if (crossed_clocks) {
1106                                                                 state->sel_clk |= (0x4 << 4*i);
1107                                                         } else {
1108                                                                 state->sel_clk |= (0x5 << 4*i);
1109                                                         }
1110                                                         break; /* This should only occur once. */
1111                                                 }
1112                                         }
1113                                 }
1114                         }
1115                 }
1116
1117                 /* Are we crosswired? */
1118                 if (output && nv_crtc->head != nv_output->preferred_output) {
1119                         state->crosswired = TRUE;
1120                 } else {
1121                         state->crosswired = FALSE;
1122                 }
1123
1124                 if (nv_crtc->head == 1) {
1125                         if (state->db1_ratio[1])
1126                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1127                 } else if (nv_crtc->head == 0) {
1128                         if (state->db1_ratio[0])
1129                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1130                 }
1131         } else {
1132                 /* Do NV1x/NV2x cards need anything in sel_clk? */
1133                 state->sel_clk = 0x0;
1134                 state->crosswired = FALSE;
1135         }
1136
1137         /* The NV40 seems to have more similarities to NV3x than other cards. */
1138         if (pNv->NVArch < 0x41) {
1139                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL;
1140                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL;
1141         }
1142
1143         if (nv_crtc->head == 1) {
1144                 if (!state->db1_ratio[1]) {
1145                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1146                 } else {
1147                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1148                 }
1149                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
1150         } else {
1151                 if (!state->db1_ratio[0]) {
1152                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1153                 } else {
1154                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1155                 }
1156                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
1157         }
1158
1159         /* The blob uses this always, so let's do the same */
1160         if (pNv->Architecture == NV_ARCH_40) {
1161                 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
1162         }
1163
1164         /* The primary output resource doesn't seem to care */
1165         if (output && pNv->Architecture == NV_ARCH_40 && nv_output->output_resource == 1) { /* This is the "output" */
1166                 /* non-zero values are for analog, don't know about tv-out and the likes */
1167                 if (output && nv_output->type != OUTPUT_ANALOG) {
1168                         state->reg594 = 0x0;
1169                 } else if (output) {
1170                         /* Are we a flexible output? */
1171                         if (ffs(pNv->dcb_table.entry[nv_output->dcb_entry].or) & OUTPUT_0) {
1172                                 state->reg594 = 0x1;
1173                                 pNv->restricted_mode = FALSE;
1174                         } else {
1175                                 state->reg594 = 0x0;
1176                                 pNv->restricted_mode = TRUE;
1177                         }
1178
1179                         /* More values exist, but they seem related to the 3rd dac (tv-out?) somehow */
1180                         /* bit 16-19 are bits that are set on some G70 cards */
1181                         /* Those bits are also set to the 3rd OUTPUT register */
1182                         if (nv_crtc->head == 1) {
1183                                 state->reg594 |= 0x100;
1184                         }
1185                 }
1186         }
1187
1188         regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
1189         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
1190         if (pNv->Architecture >= NV_ARCH_30) {
1191                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
1192         }
1193
1194         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1195                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = ((CrtcHDisplay/16) & 0x700) >> 3;
1196         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1197                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((CrtcHDisplay*bpp)/64) & 0x700) >> 3;
1198         } else { /* framebuffer can be larger than crtc scanout area. */
1199                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
1200         }
1201         regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
1202 }
1203
1204 static void
1205 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
1206 {
1207         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1208
1209         ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->head, mode);
1210
1211         if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */
1212                 return;
1213
1214         nv_crtc->last_dpms = mode;
1215
1216         ScrnInfoPtr pScrn = crtc->scrn;
1217         NVPtr pNv = NVPTR(pScrn);
1218         unsigned char seq1 = 0, crtc17 = 0;
1219         unsigned char crtc1A;
1220
1221         if (pNv->twoHeads)
1222                 NVCrtcSetOwner(crtc);
1223
1224         crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
1225         switch(mode) {
1226                 case DPMSModeStandby:
1227                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
1228                 seq1 = 0x20;
1229                 crtc17 = 0x80;
1230                 crtc1A |= 0x80;
1231                 break;
1232         case DPMSModeSuspend:
1233                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
1234                 seq1 = 0x20;
1235                 crtc17 = 0x80;
1236                 crtc1A |= 0x40;
1237                 break;
1238         case DPMSModeOff:
1239                 /* Screen: Off; HSync: Off, VSync: Off */
1240                 seq1 = 0x20;
1241                 crtc17 = 0x00;
1242                 crtc1A |= 0xC0;
1243                 break;
1244         case DPMSModeOn:
1245         default:
1246                 /* Screen: On; HSync: On, VSync: On */
1247                 seq1 = 0x00;
1248                 crtc17 = 0x80;
1249                 break;
1250         }
1251
1252         NVVgaSeqReset(crtc, TRUE);
1253         /* Each head has it's own sequencer, so we can turn it off when we want */
1254         seq1 |= (NVReadVgaSeq(crtc, 0x01) & ~0x20);
1255         NVWriteVgaSeq(crtc, 0x1, seq1);
1256         crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
1257         usleep(10000);
1258         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
1259         NVVgaSeqReset(crtc, FALSE);
1260
1261         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
1262
1263         /* I hope this is the right place */
1264         if (crtc->enabled && mode == DPMSModeOn) {
1265                 pNv->crtc_active[nv_crtc->head] = TRUE;
1266         } else {
1267                 pNv->crtc_active[nv_crtc->head] = FALSE;
1268         }
1269 }
1270
1271 static Bool
1272 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
1273                      DisplayModePtr adjusted_mode)
1274 {
1275         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1276         ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->head);
1277
1278         return TRUE;
1279 }
1280
1281 static void
1282 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1283 {
1284         ScrnInfoPtr pScrn = crtc->scrn;
1285         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1286         NVCrtcRegPtr regp;
1287         NVPtr pNv = NVPTR(pScrn);
1288         NVFBLayout *pLayout = &pNv->CurrentLayout;
1289         int depth = pScrn->depth;
1290
1291         /* This is pitch/memory size related. */
1292         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE))
1293                 depth = pNv->console_mode[nv_crtc->head].bpp;
1294
1295         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1296
1297         /* Calculate our timings */
1298         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
1299         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
1300         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
1301         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
1302         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
1303         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
1304         int vertDisplay         = mode->CrtcVDisplay                    - 1;
1305         int vertStart           = mode->CrtcVSyncStart          - 1;
1306         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
1307         int vertTotal           = mode->CrtcVTotal                      - 2;
1308         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
1309         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
1310
1311         Bool is_fp = FALSE;
1312
1313         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1314         NVOutputPrivatePtr nv_output = NULL;
1315         if (output) {
1316                 nv_output = output->driver_private;
1317
1318                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1319                         is_fp = TRUE;
1320         }
1321
1322         ErrorF("Mode clock: %d\n", mode->Clock);
1323         ErrorF("Adjusted mode clock: %d\n", adjusted_mode->Clock);
1324
1325         /* Reverted to what nv did, because that works for all resolutions on flatpanels */
1326         if (is_fp) {
1327                 vertStart = vertTotal - 3;
1328                 vertEnd = vertTotal - 2;
1329                 vertBlankStart = vertStart;
1330                 horizStart = horizTotal - 5;
1331                 horizEnd = horizTotal - 2;
1332                 horizBlankEnd = horizTotal + 4;
1333                 if (pNv->overlayAdaptor && pNv->Architecture >= NV_ARCH_10) {
1334                         /* This reportedly works around Xv some overlay bandwidth problems*/
1335                         horizTotal += 2;
1336                 }
1337         }
1338
1339         if (mode->Flags & V_INTERLACE)
1340                 vertTotal |= 1;
1341
1342         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
1343         ErrorF("horizStart: 0x%X \n", horizStart);
1344         ErrorF("horizEnd: 0x%X \n", horizEnd);
1345         ErrorF("horizTotal: 0x%X \n", horizTotal);
1346         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
1347         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
1348         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
1349         ErrorF("vertStart: 0x%X \n", vertStart);
1350         ErrorF("vertEnd: 0x%X \n", vertEnd);
1351         ErrorF("vertTotal: 0x%X \n", vertTotal);
1352         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
1353         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
1354
1355         /*
1356         * compute correct Hsync & Vsync polarity
1357         */
1358         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
1359                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
1360
1361                 regp->MiscOutReg = 0x23;
1362                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
1363                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
1364         } else {
1365                 int VDisplay = mode->VDisplay;
1366                 if (mode->Flags & V_DBLSCAN)
1367                         VDisplay *= 2;
1368                 if (mode->VScan > 1)
1369                         VDisplay *= mode->VScan;
1370                 if (VDisplay < 400) {
1371                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
1372                 } else if (VDisplay < 480) {
1373                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
1374                 } else if (VDisplay < 768) {
1375                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
1376                 } else {
1377                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
1378                 }
1379         }
1380
1381         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
1382
1383         /*
1384         * Time Sequencer
1385         */
1386         regp->Sequencer[0] = 0x00;
1387         /* 0x20 disables the sequencer */
1388         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1389                 if (mode->HDisplay == 720) {
1390                         regp->Sequencer[1] = 0x21; /* enable 9/8 mode */
1391                 } else {
1392                         regp->Sequencer[1] = 0x20;
1393                 }
1394         } else {
1395                 if (mode->Flags & V_CLKDIV2) {
1396                         regp->Sequencer[1] = 0x29;
1397                 } else {
1398                         regp->Sequencer[1] = 0x21;
1399                 }
1400         }
1401         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1402                 regp->Sequencer[2] = 0x03; /* select 2 out of 4 planes */
1403         } else {
1404                 regp->Sequencer[2] = 0x0F;
1405         }
1406         regp->Sequencer[3] = 0x00;                     /* Font select */
1407         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1408                 regp->Sequencer[4] = 0x02;
1409         } else {
1410                 regp->Sequencer[4] = 0x0E;                             /* Misc */
1411         }
1412
1413         /*
1414         * CRTC Controller
1415         */
1416         regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
1417         regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
1418         regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
1419         regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0)
1420                                 | SetBit(7);
1421         regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
1422         regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
1423                                 | SetBitField(horizEnd,4:0,4:0);
1424         regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
1425         regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
1426                                 | SetBitField(vertDisplay,8:8,1:1)
1427                                 | SetBitField(vertStart,8:8,2:2)
1428                                 | SetBitField(vertBlankStart,8:8,3:3)
1429                                 | SetBit(4)
1430                                 | SetBitField(vertTotal,9:9,5:5)
1431                                 | SetBitField(vertDisplay,9:9,6:6)
1432                                 | SetBitField(vertStart,9:9,7:7);
1433         regp->CRTC[NV_VGA_CRTCX_PRROWSCN]  = 0x00;
1434         regp->CRTC[NV_VGA_CRTCX_MAXSCLIN]  = SetBitField(vertBlankStart,9:9,5:5)
1435                                 | SetBit(6)
1436                                 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00)
1437                                 | (NVMatchModePrivate(mode, NV_MODE_VGA) ? 0xF : 0x00); /* 8x15 chars */
1438         if (NVMatchModePrivate(mode, NV_MODE_VGA)) { /* Were do these cursor offsets come from? */
1439                 regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0xD; /* start scanline */
1440                 regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0xE; /* end scanline */
1441         } else {
1442                 regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0x00;
1443                 regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0x00;
1444         }
1445         regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00;
1446         regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
1447         regp->CRTC[0xe] = 0x00;
1448         regp->CRTC[0xf] = 0x00;
1449         regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
1450         /* What is the meaning of bit5, it is empty in the vga spec. */
1451         regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) |
1452                                                                         (NVMatchModePrivate(mode, NV_MODE_VGA) ? 0 : SetBit(5));
1453         regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
1454         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1455                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = (mode->CrtcHDisplay/16);
1456         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1457                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((mode->CrtcHDisplay*depth)/64);
1458         } else { /* framebuffer can be larger than crtc scanout area. */
1459                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
1460         }
1461         if (depth == 4) { /* How can these values be calculated? */
1462                 regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x1F;
1463         } else {
1464                 regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x00;
1465         }
1466         regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
1467         regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
1468         /* 0x80 enables the sequencer, we don't want that */
1469         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1470                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xA3 & ~0x80;
1471         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1472                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xE3 & ~0x80;
1473         } else {
1474                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80;
1475         }
1476         regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
1477
1478         /*
1479          * Some extended CRTC registers (they are not saved with the rest of the vga regs).
1480          */
1481
1482         regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
1483                                 | SetBitField(vertBlankStart,10:10,3:3)
1484                                 | SetBitField(vertStart,10:10,2:2)
1485                                 | SetBitField(vertDisplay,10:10,1:1)
1486                                 | SetBitField(vertTotal,10:10,0:0);
1487
1488         regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
1489                                 | SetBitField(horizDisplay,8:8,1:1)
1490                                 | SetBitField(horizBlankStart,8:8,2:2)
1491                                 | SetBitField(horizStart,8:8,3:3);
1492
1493         regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
1494                                 | SetBitField(vertDisplay,11:11,2:2)
1495                                 | SetBitField(vertStart,11:11,4:4)
1496                                 | SetBitField(vertBlankStart,11:11,6:6);
1497
1498         if(mode->Flags & V_INTERLACE) {
1499                 horizTotal = (horizTotal >> 1) & ~1;
1500                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
1501                 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
1502         } else {
1503                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff;  /* interlace off */
1504         }
1505
1506         /*
1507         * Theory resumes here....
1508         */
1509
1510         /*
1511         * Graphics Display Controller
1512         */
1513         regp->Graphics[0] = 0x00;
1514         regp->Graphics[1] = 0x00;
1515         regp->Graphics[2] = 0x00;
1516         regp->Graphics[3] = 0x00;
1517         regp->Graphics[4] = 0x00;
1518         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1519                 regp->Graphics[5] = 0x10;
1520                 regp->Graphics[6] = 0x0E; /* map 32k mem */
1521                 regp->Graphics[7] = 0x00;
1522         } else {
1523                 regp->Graphics[5] = 0x40; /* 256 color mode */
1524                 regp->Graphics[6] = 0x05; /* map 64k mem + graphic mode */
1525                 regp->Graphics[7] = 0x0F;
1526         }
1527         regp->Graphics[8] = 0xFF;
1528
1529         /* I ditched the mono stuff */
1530         regp->Attribute[0]  = 0x00; /* standard colormap translation */
1531         regp->Attribute[1]  = 0x01;
1532         regp->Attribute[2]  = 0x02;
1533         regp->Attribute[3]  = 0x03;
1534         regp->Attribute[4]  = 0x04;
1535         regp->Attribute[5]  = 0x05;
1536         regp->Attribute[6]  = 0x06;
1537         regp->Attribute[7]  = 0x07;
1538         regp->Attribute[8]  = 0x08;
1539         regp->Attribute[9]  = 0x09;
1540         regp->Attribute[10] = 0x0A;
1541         regp->Attribute[11] = 0x0B;
1542         regp->Attribute[12] = 0x0C;
1543         regp->Attribute[13] = 0x0D;
1544         regp->Attribute[14] = 0x0E;
1545         regp->Attribute[15] = 0x0F;
1546         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1547                 regp->Attribute[16] = 0x0C; /* Line Graphics Enable + Blink enable */
1548         } else {
1549                 regp->Attribute[16] = 0x01; /* Enable graphic mode */
1550         }
1551         /* Non-vga */
1552         regp->Attribute[17] = 0x00;
1553         regp->Attribute[18] = 0x0F; /* enable all color planes */
1554         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1555                 regp->Attribute[19] = 0x08; /* shift bits by 8 */
1556         } else {
1557                 regp->Attribute[19] = 0x00;
1558         }
1559         regp->Attribute[20] = 0x00;
1560 }
1561
1562 #define MAX_H_VALUE(i) ((0x1ff + i) << 3)
1563 #define MAX_V_VALUE(i) ((0xfff + i) << 0)
1564
1565 /**
1566  * Sets up registers for the given mode/adjusted_mode pair.
1567  *
1568  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1569  *
1570  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1571  * be easily turned on/off after this.
1572  */
1573 static void
1574 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1575 {
1576         ScrnInfoPtr pScrn = crtc->scrn;
1577         NVPtr pNv = NVPTR(pScrn);
1578         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1579         NVFBLayout *pLayout = &pNv->CurrentLayout;
1580         NVCrtcRegPtr regp, savep;
1581         uint32_t i, depth;
1582         Bool is_fp = FALSE;
1583         Bool is_lvds = FALSE;
1584
1585         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1586         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1587
1588         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1589         NVOutputPrivatePtr nv_output = NULL;
1590         if (output) {
1591                 nv_output = output->driver_private;
1592
1593                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1594                         is_fp = TRUE;
1595
1596                 if (nv_output->type == OUTPUT_LVDS)
1597                         is_lvds = TRUE;
1598         }
1599
1600         /* Registers not directly related to the (s)vga mode */
1601
1602         /* bit2 = 0 -> fine pitched crtc granularity */
1603         /* The rest disables double buffering on CRTC access */
1604         regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
1605
1606         if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
1607                 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1608                 if (nv_crtc->head == 0) {
1609                         regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1610                 }
1611
1612                 if (is_fp) {
1613                         regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0);
1614                         if (!NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1615                                 regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 1);
1616                         }
1617                 }
1618         } else {
1619                 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
1620                 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
1621         }
1622
1623         /* Sometimes 0x10 is used, what is this? */
1624         regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1625         /* Some kind of tmds switch for older cards */
1626         if (pNv->Architecture < NV_ARCH_40) {
1627                 regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
1628         }
1629
1630         /*
1631         * Initialize DAC palette.
1632         * Will only be written when depth != 8.
1633         */
1634         for (i = 0; i < 256; i++) {
1635                 regp->DAC[i*3] = i;
1636                 regp->DAC[(i*3)+1] = i;
1637                 regp->DAC[(i*3)+2] = i;
1638         }
1639
1640         /*
1641         * Calculate the extended registers.
1642         */
1643
1644         if (pLayout->depth < 24) {
1645                 depth = pLayout->depth;
1646         } else {
1647                 depth = 32;
1648         }
1649
1650         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1651                 /* bpp is pitch related. */
1652                 depth = pNv->console_mode[nv_crtc->head].bpp;
1653         }
1654
1655         /* What is the meaning of this register? */
1656         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1657         regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
1658
1659         regp->head = 0;
1660
1661         /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1662         /* But what are those special conditions? */
1663         if (pNv->Architecture <= NV_ARCH_30) {
1664                 if (is_fp) {
1665                         if(nv_crtc->head == 1) {
1666                                 regp->head |= NV_CRTC_FSEL_FPP1;
1667                         } else if (pNv->twoHeads) {
1668                                 regp->head |= NV_CRTC_FSEL_FPP2;
1669                         }
1670                 }
1671         } else {
1672                 /* Most G70 cards have FPP2 set on the secondary CRTC. */
1673                 if (nv_crtc->head == 1 && pNv->NVArch > 0x44) {
1674                         regp->head |= NV_CRTC_FSEL_FPP2;
1675                 }
1676         }
1677
1678         /* Except for rare conditions I2C is enabled on the primary crtc */
1679         if (nv_crtc->head == 0) {
1680                 regp->head |= NV_CRTC_FSEL_I2C;
1681         }
1682
1683         /* Set overlay to desired crtc. */
1684         if (pNv->overlayAdaptor) {
1685                 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(pNv);
1686                 if (pPriv->overlayCRTC == nv_crtc->head)
1687                         regp->head |= NV_CRTC_FSEL_OVERLAY;
1688         }
1689
1690         /* This is not what nv does, but it is what the blob does (for nv4x at least) */
1691         /* This fixes my cursor corruption issue */
1692         regp->cursorConfig = 0x0;
1693         if(mode->Flags & V_DBLSCAN)
1694                 regp->cursorConfig |= (1 << 4);
1695         if (pNv->alphaCursor && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1696                 /* bit28 means we go into alpha blend mode and not rely on the current ROP */
1697                 regp->cursorConfig |= 0x14011000;
1698         } else {
1699                 regp->cursorConfig |= 0x02000000;
1700         }
1701
1702         /* Unblock some timings */
1703         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1704         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1705
1706         /* What is the purpose of this register? */
1707         /* 0x14 may be disabled? */
1708         regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1709
1710         /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
1711         if (is_lvds) {
1712                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x11;
1713         } else if (is_fp) {
1714                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1715         } else {
1716                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1717         }
1718
1719         /* These values seem to vary */
1720         /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
1721         regp->CRTC[NV_VGA_CRTCX_3C] = savep->CRTC[NV_VGA_CRTCX_3C];
1722
1723         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1724                 regp->CRTC[NV_VGA_CRTCX_45] = 0x0;
1725         } else {
1726                 regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1727         }
1728
1729         /* Some cards have 0x41 instead of 0x1 (for crtc 0), what is the meaning of that? */
1730         if (nv_crtc->head == 0)
1731                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x1;
1732         else
1733                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x0;
1734
1735         if (is_fp && !NVMatchModePrivate(mode, NV_MODE_CONSOLE))
1736                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x80;
1737
1738         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) { /* we need consistent restore. */
1739                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[nv_crtc->head];
1740         } else {
1741                 /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1.*/
1742                 if (nv_crtc->head == 1) {
1743                         regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[0];
1744                 } else {
1745                         regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[0] + 4;
1746                 }
1747         }
1748
1749         if (pNv->twoHeads)
1750                 /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1751                 regp->unk81c = nvReadCRTC0(pNv, NV_CRTC_081C);
1752
1753         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1754                 regp->unk830 = 0;
1755                 regp->unk834 = 0;
1756         } else {
1757                 regp->unk830 = mode->CrtcVDisplay - 3;
1758                 regp->unk834 = mode->CrtcVDisplay - 1;
1759         }
1760
1761         if (pNv->twoHeads)
1762                 /* This is what the blob does */
1763                 regp->unk850 = nvReadCRTC(pNv, 0, NV_CRTC_0850);
1764
1765         /* Never ever modify gpio, unless you know very well what you're doing */
1766         regp->gpio = nvReadCRTC(pNv, 0, NV_CRTC_GPIO);
1767
1768         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1769                 regp->config = 0x0; /* VGA mode */
1770         } else {
1771                 regp->config = 0x2; /* HSYNC mode */
1772         }
1773
1774         /* Some misc regs */
1775         regp->CRTC[NV_VGA_CRTCX_43] = 0x1;
1776         if (pNv->Architecture == NV_ARCH_40) {
1777                 regp->CRTC[NV_VGA_CRTCX_85] = 0xFF;
1778                 regp->CRTC[NV_VGA_CRTCX_86] = 0x1;
1779         }
1780
1781         /*
1782          * Calculate the state that is common to all crtc's (stored in the state struct).
1783          */
1784         ErrorF("crtc %d %d %d\n", nv_crtc->head, mode->CrtcHDisplay, pScrn->displayWidth);
1785         nv_crtc_calc_state_ext(crtc,
1786                                 mode,
1787                                 depth,
1788                                 pScrn->displayWidth,
1789                                 mode->CrtcHDisplay,
1790                                 mode->CrtcVDisplay,
1791                                 adjusted_mode->Clock,
1792                                 mode->Flags);
1793
1794         /* Enable slaved mode */
1795         if (is_fp) {
1796                 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1797         }
1798 }
1799
1800 static void
1801 nv_crtc_mode_set_ramdac_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1802 {
1803         ScrnInfoPtr pScrn = crtc->scrn;
1804         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1805         NVCrtcRegPtr regp, savep;
1806         NVPtr pNv = NVPTR(pScrn);
1807         NVFBLayout *pLayout = &pNv->CurrentLayout;
1808         Bool is_fp = FALSE;
1809         Bool is_lvds = FALSE;
1810         float aspect_ratio, panel_ratio;
1811         uint32_t h_scale, v_scale;
1812
1813         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1814         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1815
1816         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1817         NVOutputPrivatePtr nv_output = NULL;
1818         if (output) {
1819                 nv_output = output->driver_private;
1820
1821                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1822                         is_fp = TRUE;
1823
1824                 if (nv_output->type == OUTPUT_LVDS)
1825                         is_lvds = TRUE;
1826         }
1827
1828         if (is_fp) {
1829                 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
1830                 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
1831                 /* This is what the blob does. */
1832                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HSyncStart - 75 - 1;
1833                 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
1834                 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
1835                 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
1836                 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
1837
1838                 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
1839                 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
1840                 /* This is what the blob does. */
1841                 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VTotal - 5 - 1;
1842                 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
1843                 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
1844                 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
1845                 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
1846
1847                 /* Quirks, maybe move them somewere else? */
1848                 if (is_lvds) {
1849                         switch(pNv->NVArch) {
1850                                 case 0x46: /* 7300GO */
1851                                         /* Only native mode needed, is there some logic to this? */
1852                                         if (mode->HDisplay == 1280 && mode->VDisplay == 800) {
1853                                                 regp->fp_horiz_regs[REG_DISP_CRTC] = 0x4c6;
1854                                         }
1855                                         break;
1856                                 default:
1857                                         break;
1858                         }
1859                 }
1860
1861                 ErrorF("Horizontal:\n");
1862                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
1863                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
1864                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
1865                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
1866                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
1867                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
1868                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
1869
1870                 ErrorF("Vertical:\n");
1871                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
1872                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
1873                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
1874                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
1875                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
1876                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
1877                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
1878         }
1879
1880         /*
1881         * bit0: positive vsync
1882         * bit4: positive hsync
1883         * bit8: enable center mode
1884         * bit9: enable native mode
1885         * bit24: 12/24 bit interface (12bit=on, 24bit=off)
1886         * bit26: a bit sometimes seen on some g70 cards
1887         * bit28: fp display enable bit
1888         * bit31: set for dual link LVDS
1889         * nv10reg contains a few more things, but i don't quite get what it all means.
1890         */
1891
1892         if (pNv->Architecture >= NV_ARCH_30)
1893                 regp->fp_control[nv_crtc->head] = 0x00100000;
1894         else
1895                 regp->fp_control[nv_crtc->head] = 0x00000000;
1896
1897         /* Deal with vsync/hsync polarity */
1898         /* LVDS screens do set this, but modes with +ve syncs are very rare */
1899         if (is_fp) {
1900                 if (adjusted_mode->Flags & V_PVSYNC)
1901                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
1902                 if (adjusted_mode->Flags & V_PHSYNC)
1903                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
1904         } else {
1905                 /* The blob doesn't always do this, but often */
1906                 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_VSYNC_DISABLE;
1907                 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_HSYNC_DISABLE;
1908         }
1909
1910         if (is_fp) {
1911                 if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) /* seems to be used almost always */
1912                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1913                 else if (nv_output->scaling_mode == SCALE_PANEL) /* panel needs to scale */
1914                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
1915                 /* This is also true for panel scaling, so we must put the panel scale check first */
1916                 else if (mode->Clock == adjusted_mode->Clock) /* native mode */
1917                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
1918                 else /* gpu needs to scale */
1919                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1920         }
1921
1922         if (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
1923                 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
1924
1925         /* If the special bit exists, it exists on both ramdacs */
1926         regp->fp_control[nv_crtc->head] |= nvReadRAMDAC0(pNv, NV_RAMDAC_FP_CONTROL) & (1 << 26);
1927
1928         if (is_fp)
1929                 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS;
1930         else
1931                 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE;
1932
1933         Bool lvds_use_straps = pNv->dcb_table.entry[nv_output->dcb_entry].lvdsconf.use_straps_for_mode;
1934         if (is_lvds && ((lvds_use_straps && pNv->VBIOS.fp.dual_link) || (!lvds_use_straps && adjusted_mode->Clock >= pNv->VBIOS.fp.duallink_transition_clk)))
1935                 regp->fp_control[nv_crtc->head] |= (8 << 28);
1936
1937         if (is_fp) {
1938                 ErrorF("Pre-panel scaling\n");
1939                 ErrorF("panel-size:%dx%d\n", nv_output->fpWidth, nv_output->fpHeight);
1940                 panel_ratio = (nv_output->fpWidth)/(float)(nv_output->fpHeight);
1941                 ErrorF("panel_ratio=%f\n", panel_ratio);
1942                 aspect_ratio = (mode->HDisplay)/(float)(mode->VDisplay);
1943                 ErrorF("aspect_ratio=%f\n", aspect_ratio);
1944                 /* Scale factors is the so called 20.12 format, taken from Haiku */
1945                 h_scale = ((1 << 12) * mode->HDisplay)/nv_output->fpWidth;
1946                 v_scale = ((1 << 12) * mode->VDisplay)/nv_output->fpHeight;
1947                 ErrorF("h_scale=%d\n", h_scale);
1948                 ErrorF("v_scale=%d\n", v_scale);
1949
1950                 /* This can override HTOTAL and VTOTAL */
1951                 regp->debug_2 = 0;
1952
1953                 /* We want automatic scaling */
1954                 regp->debug_1 = 0;
1955
1956                 regp->fp_hvalid_start = 0;
1957                 regp->fp_hvalid_end = (nv_output->fpWidth - 1);
1958
1959                 regp->fp_vvalid_start = 0;
1960                 regp->fp_vvalid_end = (nv_output->fpHeight - 1);
1961
1962                 /* 0 = panel scaling */
1963                 if (nv_output->scaling_mode == SCALE_PANEL) {
1964                         ErrorF("Flat panel is doing the scaling.\n");
1965                 } else {
1966                         ErrorF("GPU is doing the scaling.\n");
1967
1968                         if (nv_output->scaling_mode == SCALE_ASPECT) {
1969                                 /* GPU scaling happens automaticly at a ratio of 1.33 */
1970                                 /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
1971                                 if (h_scale != (1 << 12) && (panel_ratio > (aspect_ratio + 0.10))) {
1972                                         uint32_t diff;
1973
1974                                         ErrorF("Scaling resolution on a widescreen panel\n");
1975
1976                                         /* Scaling in both directions needs to the same */
1977                                         h_scale = v_scale;
1978
1979                                         /* Set a new horizontal scale factor and enable testmode (bit12) */
1980                                         regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
1981
1982                                         diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
1983                                         regp->fp_hvalid_start = diff/2;
1984                                         regp->fp_hvalid_end = nv_output->fpWidth - (diff/2) - 1;
1985                                 }
1986
1987                                 /* Same scaling, just for panels with aspect ratio's smaller than 1 */
1988                                 if (v_scale != (1 << 12) && (panel_ratio < (aspect_ratio - 0.10))) {
1989                                         uint32_t diff;
1990
1991                                         ErrorF("Scaling resolution on a portrait panel\n");
1992
1993                                         /* Scaling in both directions needs to the same */
1994                                         v_scale = h_scale;
1995
1996                                         /* Set a new vertical scale factor and enable testmode (bit28) */
1997                                         regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
1998
1999                                         diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
2000                                         regp->fp_vvalid_start = diff/2;
2001                                         regp->fp_vvalid_end = nv_output->fpHeight - (diff/2) - 1;
2002                                 }
2003                         }
2004                 }
2005
2006                 ErrorF("Post-panel scaling\n");
2007         }
2008
2009         if (!is_fp && NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
2010                 regp->debug_1 = 0x08000800;
2011         }
2012
2013         if (pNv->Architecture >= NV_ARCH_10) {
2014                 /* Bios and blob don't seem to do anything (else) */
2015                 if (!NVMatchModePrivate(mode, NV_MODE_CONSOLE))
2016                         regp->nv10_cursync = (1<<25);
2017                 else
2018                         regp->nv10_cursync = 0;
2019         }
2020
2021         /* These are the common blob values, minus a few fp specific bit's */
2022         /* Let's keep the TMDS pll and fpclock running in all situations */
2023         regp->debug_0[nv_crtc->head] = 0x1101100;
2024
2025         if (is_fp && nv_output->scaling_mode != SCALE_NOSCALE) {
2026                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_XSCALE_ENABLED;
2027                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_YSCALE_ENABLED;
2028         } else if (is_fp) { /* no_scale mode, so we must center it */
2029                 uint32_t diff;
2030
2031                 diff = nv_output->fpWidth - mode->HDisplay;
2032                 regp->fp_hvalid_start = diff/2;
2033                 regp->fp_hvalid_end = (nv_output->fpWidth - diff/2 - 1);
2034
2035                 diff = nv_output->fpHeight - mode->VDisplay;
2036                 regp->fp_vvalid_start = diff/2;
2037                 regp->fp_vvalid_end = (nv_output->fpHeight - diff/2 - 1);
2038         }
2039
2040         /* Is this crtc bound or output bound? */
2041         /* Does the bios TMDS script try to change this sometimes? */
2042         if (is_fp) {
2043                 /* I am not completely certain, but seems to be set only for dfp's */
2044                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED;
2045         }
2046
2047         if (output)
2048                 ErrorF("output %d debug_0 %08X\n", nv_output->output_resource, regp->debug_0[nv_crtc->head]);
2049
2050         /* Flatpanel support needs at least a NV10 */
2051         if (pNv->twoHeads) {
2052                 /* The blob does this differently. */
2053                 /* TODO: Find out what precisely and why. */
2054                 /* Let's not destroy any bits that were already present. */
2055                 if (pNv->FPDither || (is_lvds && pNv->VBIOS.fp.if_is_18bit)) {
2056                         if (pNv->NVArch == 0x11) {
2057                                 regp->dither = savep->dither | 0x00010000;
2058                         } else {
2059                                 regp->dither = savep->dither | 0x00000001;
2060                         }
2061                 } else {
2062                         regp->dither = savep->dither;
2063                 }
2064         }
2065
2066         uint8_t depth;
2067         /* This is mode related, not pitch. */
2068         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
2069                 depth = pNv->console_mode[nv_crtc->head].depth;
2070         } else {
2071                 depth = pLayout->depth;
2072         }
2073
2074         switch (depth) {
2075                 case 4:
2076                         regp->general = 0x00000100;
2077                         break;
2078                 case 24:
2079                 case 15:
2080                         regp->general = 0x00100100;
2081                         break;
2082                 case 32:
2083                 case 16:
2084                 case 8:
2085                 default:
2086                         regp->general = 0x00101100;
2087                         break;
2088         }
2089
2090         if (depth > 8 && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
2091                 regp->general |= 0x30; /* enable palette mode */
2092         }
2093
2094         if (pNv->alphaCursor && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
2095                 /* PIPE_LONG mode, something to do with the size of the cursor? */
2096                 regp->general |= (1<<29);
2097         }
2098
2099         /* Some values the blob sets */
2100         /* This may apply to the real ramdac that is being used (for crosswired situations) */
2101         /* Nevertheless, it's unlikely to cause many problems, since the values are equal for both */
2102         regp->unk_a20 = 0x0;
2103         regp->unk_a24 = 0xfffff;
2104         regp->unk_a34 = 0x1;
2105
2106         if (pNv->twoHeads) {
2107                 /* Do we also "own" the other register pair? */
2108                 /* If we own neither, they will just be ignored at load time. */
2109                 uint8_t other_head = (~nv_crtc->head) & 1;
2110                 if (pNv->fp_regs_owner[other_head] == nv_crtc->head) {
2111                         if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS) {
2112                                 regp->fp_control[other_head] = regp->fp_control[nv_crtc->head];
2113                                 regp->debug_0[other_head] = regp->debug_0[nv_crtc->head];
2114                                 /* Set TMDS_PLL and FPCLK, only seen for a NV31M so far. */
2115                                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK;
2116                                 regp->debug_0[other_head] |= NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL;
2117                         } else {
2118                                 ErrorF("This is BAD, we own more than one fp reg set, but are not a LVDS or TMDS output.\n");
2119                         }
2120                 }
2121         }
2122 }
2123
2124 /**
2125  * Sets up registers for the given mode/adjusted_mode pair.
2126  *
2127  * The clocks, CRTCs and outputs attached to this CRTC must be off.
2128  *
2129  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
2130  * be easily turned on/off after this.
2131  */
2132 static void
2133 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
2134                  DisplayModePtr adjusted_mode,
2135                  int x, int y)
2136 {
2137         ScrnInfoPtr pScrn = crtc->scrn;
2138         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2139         NVPtr pNv = NVPTR(pScrn);
2140         NVFBLayout *pLayout = &pNv->CurrentLayout;
2141
2142         ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->head);
2143
2144         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->head);
2145         xf86PrintModeline(pScrn->scrnIndex, mode);
2146         if (pNv->twoHeads)
2147                 NVCrtcSetOwner(crtc);
2148
2149         nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
2150         nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
2151         nv_crtc_mode_set_ramdac_regs(crtc, mode, adjusted_mode);
2152
2153         NVVgaProtect(crtc, TRUE);
2154         nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
2155         nv_crtc_load_state_ext(crtc, &pNv->ModeReg, FALSE);
2156         if (pLayout->depth > 8)
2157                 NVCrtcLoadPalette(crtc);
2158         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
2159         if (pNv->Architecture == NV_ARCH_40) {
2160                 nv40_crtc_load_state_pll(crtc, &pNv->ModeReg);
2161         } else {
2162                 nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
2163         }
2164
2165         NVVgaProtect(crtc, FALSE);
2166
2167         NVCrtcSetBase(crtc, x, y, NVMatchModePrivate(mode, NV_MODE_CONSOLE));
2168
2169 #if X_BYTE_ORDER == X_BIG_ENDIAN
2170         /* turn on LFB swapping */
2171         {
2172                 unsigned char tmp;
2173
2174                 tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
2175                 tmp |= (1 << 7);
2176                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
2177         }
2178 #endif
2179 }
2180
2181 /* This functions generates data that is not saved, but still is needed. */
2182 void nv_crtc_restore_generate(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2183 {
2184         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2185         ScrnInfoPtr pScrn = crtc->scrn;
2186         NVPtr pNv = NVPTR(pScrn);
2187         int i;
2188         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
2189
2190         /* It's a good idea to also save a default palette on shutdown. */
2191         for (i = 0; i < 256; i++) {
2192                 regp->DAC[i*3] = i;
2193                 regp->DAC[(i*3)+1] = i;
2194                 regp->DAC[(i*3)+2] = i;
2195         }
2196
2197         /* Noticed that reading this variable is problematic on one card. */
2198         if (pNv->NVArch == 0x11)
2199                 state->sel_clk = 0x0;
2200 }
2201
2202 void nv_crtc_save(xf86CrtcPtr crtc)
2203 {
2204         ScrnInfoPtr pScrn = crtc->scrn;
2205         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2206         NVPtr pNv = NVPTR(pScrn);
2207
2208         ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->head);
2209
2210         /* We just came back from terminal, so unlock */
2211         NVCrtcLockUnlock(crtc, FALSE);
2212
2213         if (pNv->twoHeads)
2214                 NVCrtcSetOwner(crtc);
2215         nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
2216         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
2217         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
2218         if (pNv->Architecture == NV_ARCH_40) {
2219                 nv40_crtc_save_state_pll(pNv, &pNv->SavedReg);
2220         } else {
2221                 nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
2222         }
2223 }
2224
2225 void nv_crtc_restore(xf86CrtcPtr crtc)
2226 {
2227         ScrnInfoPtr pScrn = crtc->scrn;
2228         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2229         NVPtr pNv = NVPTR(pScrn);
2230         RIVA_HW_STATE *state;
2231         NVCrtcRegPtr savep;
2232
2233         state = &pNv->SavedReg;
2234         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
2235
2236         ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->head);
2237
2238         if (pNv->twoHeads)
2239                 NVCrtcSetOwner(crtc);
2240
2241         /* Just to be safe */
2242         NVCrtcLockUnlock(crtc, FALSE);
2243
2244         NVVgaProtect(crtc, TRUE);
2245         nv_crtc_restore_generate(crtc, &pNv->SavedReg);
2246         nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
2247         nv_crtc_load_state_ext(crtc, &pNv->SavedReg, TRUE);
2248         if (savep->general & 0x30) /* Palette mode */
2249                 NVCrtcLoadPalette(crtc);
2250         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
2251
2252         /* Force restoring vpll. */
2253         state->vpll_changed[nv_crtc->head] = TRUE;
2254
2255         if (pNv->Architecture == NV_ARCH_40) {
2256                 nv40_crtc_load_state_pll(crtc, &pNv->SavedReg);
2257         } else {
2258                 nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
2259         }
2260         if (pNv->twoHeads)
2261                 nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->vtOWNER);
2262         NVVgaProtect(crtc, FALSE);
2263
2264         nv_crtc->last_dpms = NV_DPMS_CLEARED;
2265 }
2266
2267 static void
2268 NVResetCrtcConfig(xf86CrtcPtr crtc, Bool set)
2269 {
2270         ScrnInfoPtr pScrn = crtc->scrn;
2271         NVPtr pNv = NVPTR(pScrn);
2272
2273         if (pNv->twoHeads) {
2274                 uint32_t val = 0;
2275
2276                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2277
2278                 if (set) {
2279                         NVCrtcRegPtr regp;
2280
2281                         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2282                         val = regp->head;
2283                 }
2284
2285                 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL, val);
2286         }
2287 }
2288
2289 void nv_crtc_prepare(xf86CrtcPtr crtc)
2290 {
2291         ScrnInfoPtr pScrn = crtc->scrn;
2292         NVPtr pNv = NVPTR(pScrn);
2293         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2294
2295         ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->head);
2296
2297         /* Just in case */
2298         NVCrtcLockUnlock(crtc, 0);
2299
2300         NVResetCrtcConfig(crtc, FALSE);
2301
2302         crtc->funcs->dpms(crtc, DPMSModeOff);
2303
2304         /* Sync the engine before adjust mode */
2305         if (pNv->EXADriverPtr) {
2306                 exaMarkSync(pScrn->pScreen);
2307                 exaWaitSync(pScrn->pScreen);
2308         }
2309
2310         NVCrtcBlankScreen(crtc, FALSE); /* Blank screen */
2311
2312         /* Some more preperation. */
2313         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG, 0x1); /* Go to non-vga mode/out of enhanced mode */
2314         if (pNv->Architecture == NV_ARCH_40) {
2315                 uint32_t reg900 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900);
2316                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 & ~0x10000);
2317         }
2318 }
2319
2320 void nv_crtc_commit(xf86CrtcPtr crtc)
2321 {
2322         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2323         ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->head);
2324
2325         crtc->funcs->dpms (crtc, DPMSModeOn);
2326
2327         if (crtc->scrn->pScreen != NULL)
2328                 xf86_reload_cursors (crtc->scrn->pScreen);
2329
2330         NVResetCrtcConfig(crtc, TRUE);
2331 }
2332
2333 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
2334 {
2335         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2336         ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->head);
2337
2338         return FALSE;
2339 }
2340
2341 static void nv_crtc_unlock(xf86CrtcPtr crtc)
2342 {
2343         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2344         ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->head);
2345 }
2346
2347 static void
2348 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
2349                                         int size)
2350 {
2351         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2352         ScrnInfoPtr pScrn = crtc->scrn;
2353         NVPtr pNv = NVPTR(pScrn);
2354         int i, j;
2355
2356         NVCrtcRegPtr regp;
2357         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2358
2359         switch (pNv->CurrentLayout.depth) {
2360         case 15:
2361                 /* R5G5B5 */
2362                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
2363                 for (i = 0; i < 32; i++) {
2364                         for (j = 0; j < 8; j++) {
2365                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2366                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
2367                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2368                         }
2369                 }
2370                 break;
2371         case 16:
2372                 /* R5G6B5 */
2373                 /* First deal with the 5 bit colors */
2374                 for (i = 0; i < 32; i++) {
2375                         for (j = 0; j < 8; j++) {
2376                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2377                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2378                         }
2379                 }
2380                 /* Now deal with the 6 bit color */
2381                 for (i = 0; i < 64; i++) {
2382                         for (j = 0; j < 4; j++) {
2383                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
2384                         }
2385                 }
2386                 break;
2387         default:
2388                 /* R8G8B8 */
2389                 for (i = 0; i < 256; i++) {
2390                         regp->DAC[i * 3] = red[i] >> 8;
2391                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
2392                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
2393                 }
2394                 break;
2395         }
2396
2397         NVCrtcLoadPalette(crtc);
2398 }
2399
2400 /**
2401  * Allocates memory for a locked-in-framebuffer shadow of the given
2402  * width and height for this CRTC's rotated shadow framebuffer.
2403  */
2404
2405 static void *
2406 nv_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
2407 {
2408         ErrorF("nv_crtc_shadow_allocate is called\n");
2409         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2410         ScrnInfoPtr pScrn = crtc->scrn;
2411 #if !NOUVEAU_EXA_PIXMAPS
2412         ScreenPtr pScreen = pScrn->pScreen;
2413 #endif /* !NOUVEAU_EXA_PIXMAPS */
2414         NVPtr pNv = NVPTR(pScrn);
2415         void *offset;
2416
2417         unsigned long rotate_pitch;
2418         int size, align = 64;
2419
2420         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2421         size = rotate_pitch * height;
2422
2423         assert(nv_crtc->shadow == NULL);
2424 #if NOUVEAU_EXA_PIXMAPS
2425         if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN,
2426                         align, size, &nv_crtc->shadow)) {
2427                 ErrorF("Failed to allocate memory for shadow buffer!\n");
2428                 return NULL;
2429         }
2430
2431         if (nv_crtc->shadow && nouveau_bo_map(nv_crtc->shadow, NOUVEAU_BO_RDWR)) {
2432                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2433                                 "Failed to map shadow buffer.\n");
2434                 return NULL;
2435         }
2436
2437         offset = nv_crtc->shadow->map;
2438 #else
2439         nv_crtc->shadow = exaOffscreenAlloc(pScreen, size, align, TRUE, NULL, NULL);
2440         if (nv_crtc->shadow == NULL) {
2441                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2442                         "Couldn't allocate shadow memory for rotated CRTC\n");
2443                 return NULL;
2444         }
2445         offset = pNv->FB->map + nv_crtc->shadow->offset;
2446 #endif /* NOUVEAU_EXA_PIXMAPS */
2447
2448         return offset;
2449 }
2450
2451 /**
2452  * Creates a pixmap for this CRTC's rotated shadow framebuffer.
2453  */
2454 static PixmapPtr
2455 nv_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
2456 {
2457         ErrorF("nv_crtc_shadow_create is called\n");
2458         ScrnInfoPtr pScrn = crtc->scrn;
2459 #if NOUVEAU_EXA_PIXMAPS
2460         ScreenPtr pScreen = pScrn->pScreen;
2461         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2462 #endif /* NOUVEAU_EXA_PIXMAPS */
2463         unsigned long rotate_pitch;
2464         PixmapPtr rotate_pixmap;
2465 #if NOUVEAU_EXA_PIXMAPS
2466         struct nouveau_pixmap *nvpix;
2467 #endif /* NOUVEAU_EXA_PIXMAPS */
2468
2469         if (!data)
2470                 data = crtc->funcs->shadow_allocate (crtc, width, height);
2471
2472         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2473
2474 #if NOUVEAU_EXA_PIXMAPS
2475         /* Create a dummy pixmap, to get a private that will be accepted by the system.*/
2476         rotate_pixmap = pScreen->CreatePixmap(pScreen,
2477                                                                 0, /* width */
2478                                                                 0, /* height */
2479         #ifdef CREATE_PIXMAP_USAGE_SCRATCH /* there seems to have been no api bump */
2480                                                                 pScrn->depth,
2481                                                                 0);
2482         #else
2483                                                                 pScrn->depth);
2484         #endif /* CREATE_PIXMAP_USAGE_SCRATCH */
2485 #else
2486         rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen,
2487                                                                 width, height,
2488                                                                 pScrn->depth,
2489                                                                 pScrn->bitsPerPixel,
2490                                                                 rotate_pitch,
2491                                                                 data);
2492 #endif /* NOUVEAU_EXA_PIXMAPS */
2493
2494         if (rotate_pixmap == NULL) {
2495                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2496                         "Couldn't allocate shadow pixmap for rotated CRTC\n");
2497         }
2498
2499 #if NOUVEAU_EXA_PIXMAPS
2500         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2501         if (!nvpix) {
2502                 ErrorF("No shadow private, stage 1\n");
2503         } else {
2504                 nvpix->bo = nv_crtc->shadow;
2505                 nvpix->mapped = TRUE;
2506         }
2507
2508         /* Modify the pixmap to actually be the one we need. */
2509         pScreen->ModifyPixmapHeader(rotate_pixmap,
2510                                         width,
2511                                         height,
2512                                         pScrn->depth,
2513                                         pScrn->bitsPerPixel,
2514                                         rotate_pitch,
2515                                         data);
2516
2517         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2518         if (!nvpix || !nvpix->bo)
2519                 ErrorF("No shadow private, stage 2\n");
2520 #endif /* NOUVEAU_EXA_PIXMAPS */
2521
2522         return rotate_pixmap;
2523 }
2524
2525 static void
2526 nv_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
2527 {
2528         ErrorF("nv_crtc_shadow_destroy is called\n");
2529         ScrnInfoPtr pScrn = crtc->scrn;
2530         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2531         ScreenPtr pScreen = pScrn->pScreen;
2532
2533         if (rotate_pixmap) { /* This should also unmap the buffer object if relevant. */
2534                 pScreen->DestroyPixmap(rotate_pixmap);
2535         }
2536
2537 #if !NOUVEAU_EXA_PIXMAPS
2538         if (data && nv_crtc->shadow) {
2539                 exaOffscreenFree(pScreen, nv_crtc->shadow);
2540         }
2541 #endif /* !NOUVEAU_EXA_PIXMAPS */
2542
2543         nv_crtc->shadow = NULL;
2544 }
2545
2546 /* NV04-NV10 doesn't support alpha cursors */
2547 static const xf86CrtcFuncsRec nv_crtc_funcs = {
2548         .dpms = nv_crtc_dpms,
2549         .save = nv_crtc_save, /* XXX */
2550         .restore = nv_crtc_restore, /* XXX */
2551         .mode_fixup = nv_crtc_mode_fixup,
2552         .mode_set = nv_crtc_mode_set,
2553         .prepare = nv_crtc_prepare,
2554         .commit = nv_crtc_commit,
2555         .destroy = NULL, /* XXX */
2556         .lock = nv_crtc_lock,
2557         .unlock = nv_crtc_unlock,
2558         .set_cursor_colors = nv_crtc_set_cursor_colors,
2559         .set_cursor_position = nv_crtc_set_cursor_position,
2560         .show_cursor = nv_crtc_show_cursor,
2561         .hide_cursor = nv_crtc_hide_cursor,
2562         .load_cursor_image = nv_crtc_load_cursor_image,
2563         .gamma_set = nv_crtc_gamma_set,
2564         .shadow_create = nv_crtc_shadow_create,
2565         .shadow_allocate = nv_crtc_shadow_allocate,
2566         .shadow_destroy = nv_crtc_shadow_destroy,
2567 };
2568
2569 /* NV11 and up has support for alpha cursors. */
2570 /* Due to different maximum sizes we cannot allow it to use normal cursors */
2571 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
2572         .dpms = nv_crtc_dpms,
2573         .save = nv_crtc_save, /* XXX */
2574         .restore = nv_crtc_restore, /* XXX */
2575         .mode_fixup = nv_crtc_mode_fixup,
2576         .mode_set = nv_crtc_mode_set,
2577         .prepare = nv_crtc_prepare,
2578         .commit = nv_crtc_commit,
2579         .destroy = NULL, /* XXX */
2580         .lock = nv_crtc_lock,
2581         .unlock = nv_crtc_unlock,
2582         .set_cursor_colors = NULL, /* Alpha cursors do not need this */
2583         .set_cursor_position = nv_crtc_set_cursor_position,
2584         .show_cursor = nv_crtc_show_cursor,
2585         .hide_cursor = nv_crtc_hide_cursor,
2586         .load_cursor_argb = nv_crtc_load_cursor_argb,
2587         .gamma_set = nv_crtc_gamma_set,
2588         .shadow_create = nv_crtc_shadow_create,
2589         .shadow_allocate = nv_crtc_shadow_allocate,
2590         .shadow_destroy = nv_crtc_shadow_destroy,
2591 };
2592
2593
2594 void
2595 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
2596 {
2597         NVPtr pNv = NVPTR(pScrn);
2598         xf86CrtcPtr crtc;
2599         NVCrtcPrivatePtr nv_crtc;
2600
2601         if (pNv->NVArch >= 0x11) {
2602                 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
2603         } else {
2604                 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
2605         }
2606         if (crtc == NULL)
2607                 return;
2608
2609         nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
2610         nv_crtc->head = crtc_num;
2611         nv_crtc->last_dpms = NV_DPMS_CLEARED;
2612         pNv->fp_regs_owner[nv_crtc->head] = nv_crtc->head;
2613
2614         crtc->driver_private = nv_crtc;
2615
2616         NVCrtcLockUnlock(crtc, FALSE);
2617 }
2618
2619 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2620 {
2621         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2622         int i;
2623         NVCrtcRegPtr regp;
2624
2625         regp = &state->crtc_reg[nv_crtc->head];
2626
2627         NVWriteMiscOut(crtc, regp->MiscOutReg);
2628
2629         for (i = 1; i < 5; i++)
2630                 NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
2631
2632         /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
2633         NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
2634
2635         for (i = 0; i < 25; i++)
2636                 NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
2637
2638         for (i = 0; i < 9; i++)
2639                 NVWriteVgaGr(crtc, i, regp->Graphics[i]);
2640
2641         NVEnablePalette(crtc);
2642         for (i = 0; i < 21; i++)
2643                 NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
2644
2645         NVDisablePalette(crtc);
2646 }
2647
2648 static void nv_crtc_fix_nv40_hw_cursor(xf86CrtcPtr crtc)
2649 {
2650         /* TODO - implement this properly */
2651         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2652         ScrnInfoPtr pScrn = crtc->scrn;
2653         NVPtr pNv = NVPTR(pScrn);
2654
2655         if (pNv->Architecture == NV_ARCH_40) {  /* HW bug */
2656                 volatile uint32_t curpos = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS);
2657                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS, curpos);
2658         }
2659 }
2660 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override)
2661 {
2662         ScrnInfoPtr pScrn = crtc->scrn;
2663         NVPtr pNv = NVPTR(pScrn);
2664         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2665         NVCrtcRegPtr regp;
2666         int i;
2667
2668         regp = &state->crtc_reg[nv_crtc->head];
2669
2670         if (pNv->Architecture >= NV_ARCH_10) {
2671                 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
2672                 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
2673                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
2674                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
2675                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2676                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2677                 nvWriteMC(pNv, 0x1588, 0);
2678
2679                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
2680                 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
2681                 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0830, regp->unk830);
2682                 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0834, regp->unk834);
2683                 if (pNv->Architecture == NV_ARCH_40) {
2684                         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0850, regp->unk850);
2685                         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_081C, regp->unk81c);
2686                 }
2687
2688                 if (pNv->Architecture == NV_ARCH_40) {
2689                         uint32_t reg900 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900);
2690                         if (regp->config == 0x2) { /* enhanced "horizontal only" non-vga mode */
2691                                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 | 0x10000);
2692                         } else {
2693                                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 & ~0x10000);
2694                         }
2695                 }
2696         }
2697
2698         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG, regp->config);
2699         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO, regp->gpio);
2700
2701         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
2702         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
2703         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
2704         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
2705         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
2706         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
2707         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
2708         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
2709         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
2710         if (pNv->Architecture >= NV_ARCH_30)
2711                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
2712
2713         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
2714         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
2715         nv_crtc_fix_nv40_hw_cursor(crtc);
2716         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
2717         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
2718
2719         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
2720         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
2721         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3C, regp->CRTC[NV_VGA_CRTCX_3C]);
2722         if (pNv->Architecture >= NV_ARCH_10) {
2723                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
2724                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_43, regp->CRTC[NV_VGA_CRTCX_43]);
2725                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
2726                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_4B, regp->CRTC[NV_VGA_CRTCX_4B]);
2727                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
2728         }
2729         /* NV11 and NV20 stop at 0x52. */
2730         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
2731                 if (override)
2732                         for (i = 0; i < 0x10; i++)
2733                                 NVWriteVGACR5758(pNv, nv_crtc->head, i, regp->CR58[i]);
2734
2735                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
2736                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
2737
2738                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
2739
2740                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_85, regp->CRTC[NV_VGA_CRTCX_85]);
2741                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_86, regp->CRTC[NV_VGA_CRTCX_86]);
2742         }
2743
2744         /* Setting 1 on this value gives you interrupts for every vblank period. */
2745         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_EN_0, 0);
2746         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
2747
2748         pNv->CurrentState = state;
2749 }
2750
2751 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2752 {
2753         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2754         int i;
2755         NVCrtcRegPtr regp;
2756
2757         regp = &state->crtc_reg[nv_crtc->head];
2758
2759         regp->MiscOutReg = NVReadMiscOut(crtc);
2760
2761         for (i = 0; i < 25; i++)
2762                 regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
2763
2764         NVEnablePalette(crtc);
2765         for (i = 0; i < 21; i++)
2766                 regp->Attribute[i] = NVReadVgaAttr(crtc, i);
2767         NVDisablePalette(crtc);
2768
2769         for (i = 0; i < 9; i++)
2770                 regp->Graphics[i] = NVReadVgaGr(crtc, i);
2771
2772         for (i = 1; i < 5; i++)
2773                 regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
2774 }
2775
2776 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2777 {
2778         ScrnInfoPtr pScrn = crtc->scrn;
2779         NVPtr pNv = NVPTR(pScrn);
2780         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2781         NVCrtcRegPtr regp;
2782         int i;
2783
2784         regp = &state->crtc_reg[nv_crtc->head];
2785
2786         regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
2787         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
2788         regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
2789         regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
2790         regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
2791         regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
2792         regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
2793
2794         regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
2795         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
2796         regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
2797         if (pNv->Architecture >= NV_ARCH_30)
2798                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
2799         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
2800         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
2801         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
2802         regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
2803
2804         if (pNv->Architecture >= NV_ARCH_10) {
2805                 regp->unk830 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0830);
2806                 regp->unk834 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0834);
2807                 if (pNv->Architecture == NV_ARCH_40) {
2808                         regp->unk850 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0850);
2809                         regp->unk81c = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_081C);
2810                 }
2811                 if (pNv->twoHeads) {
2812                         regp->head = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL);
2813                         regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
2814                 }
2815                 regp->cursorConfig = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG);
2816         }
2817
2818         regp->gpio = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO);
2819         regp->config = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG);
2820
2821         regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
2822         regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
2823         regp->CRTC[NV_VGA_CRTCX_3C] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3C);
2824         if (pNv->Architecture >= NV_ARCH_10) {
2825                 regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
2826                 regp->CRTC[NV_VGA_CRTCX_43] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_43);
2827                 regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
2828                 regp->CRTC[NV_VGA_CRTCX_4B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_4B);
2829                 regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
2830         }
2831         /* NV11 and NV20 don't have this, they stop at 0x52. */
2832         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
2833                 for (i = 0; i < 0x10; i++)
2834                         regp->CR58[i] = NVReadVGACR5758(pNv, nv_crtc->head, i);
2835
2836                 regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
2837                 regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
2838                 regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
2839
2840                 regp->CRTC[NV_VGA_CRTCX_85] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_85);
2841                 regp->CRTC[NV_VGA_CRTCX_86] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_86);
2842         }
2843 }
2844
2845 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2846 {
2847         ScrnInfoPtr pScrn = crtc->scrn;
2848         NVPtr pNv = NVPTR(pScrn);
2849         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2850         NVCrtcRegPtr regp;
2851         int i;
2852
2853         regp = &state->crtc_reg[nv_crtc->head];
2854
2855         regp->general = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL);
2856
2857         regp->fp_control[0]     = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL);
2858         regp->debug_0[0]        = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
2859
2860         if (pNv->twoHeads) {
2861                 regp->fp_control[1]     = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_CONTROL);
2862                 regp->debug_0[1]        = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
2863
2864                 regp->debug_1   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1);
2865                 regp->debug_2   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2);
2866
2867                 regp->unk_a20 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20);
2868                 regp->unk_a24 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24);
2869                 regp->unk_a34 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34);
2870         }
2871
2872         if (pNv->NVArch == 0x11) {
2873                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11);
2874         } else if (pNv->twoHeads) {
2875                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER);
2876         }
2877         if (pNv->Architecture >= NV_ARCH_10)
2878                 regp->nv10_cursync = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC);
2879
2880         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2881
2882         for (i = 0; i < 7; i++) {
2883                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2884                 regp->fp_horiz_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2885         }
2886
2887         for (i = 0; i < 7; i++) {
2888                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2889                 regp->fp_vert_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2890         }
2891
2892         regp->fp_hvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START);
2893         regp->fp_hvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END);
2894         regp->fp_vvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START);
2895         regp->fp_vvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END);
2896 }
2897
2898 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2899 {
2900         ScrnInfoPtr pScrn = crtc->scrn;
2901         NVPtr pNv = NVPTR(pScrn);
2902         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2903         NVCrtcRegPtr regp;
2904         int i;
2905
2906         regp = &state->crtc_reg[nv_crtc->head];
2907
2908         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL, regp->general);
2909
2910         if (pNv->fp_regs_owner[0] == nv_crtc->head) {
2911                 nvWriteRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL, regp->fp_control[0]);
2912                 nvWriteRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0, regp->debug_0[0]);
2913         }
2914         if (pNv->twoHeads) {
2915                 if (pNv->fp_regs_owner[1] == nv_crtc->head) {
2916                         nvWriteRAMDAC(pNv, 1, NV_RAMDAC_FP_CONTROL, regp->fp_control[1]);
2917                         nvWriteRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0, regp->debug_0[1]);
2918                 }
2919                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
2920                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
2921                 if (pNv->NVArch == 0x30) { /* For unknown purposes. */
2922                         uint32_t reg890 = nvReadRAMDAC(pNv, nv_crtc->head, NV30_RAMDAC_890);
2923                         nvWriteRAMDAC(pNv, nv_crtc->head, NV30_RAMDAC_89C, reg890);
2924                 }
2925
2926                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20, regp->unk_a20);
2927                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24, regp->unk_a24);
2928                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34, regp->unk_a34);
2929         }
2930
2931         if (pNv->NVArch == 0x11) {
2932                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11, regp->dither);
2933         } else if (pNv->twoHeads) {
2934                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER, regp->dither);
2935         }
2936         if (pNv->Architecture >= NV_ARCH_10)
2937                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
2938
2939         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2940
2941         for (i = 0; i < 7; i++) {
2942                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2943                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_horiz_regs[i]);
2944         }
2945
2946         for (i = 0; i < 7; i++) {
2947                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2948                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_vert_regs[i]);
2949         }
2950
2951         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START, regp->fp_hvalid_start);
2952         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END, regp->fp_hvalid_end);
2953         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START, regp->fp_vvalid_start);
2954         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END, regp->fp_vvalid_end);
2955 }
2956
2957 void
2958 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y, Bool bios_restore)
2959 {
2960         ScrnInfoPtr pScrn = crtc->scrn;
2961         NVPtr pNv = NVPTR(pScrn);
2962         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2963         NVFBLayout *pLayout = &pNv->CurrentLayout;
2964         uint32_t start = 0;
2965
2966         ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
2967
2968         if (bios_restore) {
2969                 start = pNv->console_mode[nv_crtc->head].fb_start;
2970         } else {
2971                 start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
2972                 if (crtc->rotatedData != NULL) { /* we do not exist on the real framebuffer */
2973 #if NOUVEAU_EXA_PIXMAPS
2974                         start = nv_crtc->shadow->offset;
2975 #else
2976                         start = pNv->FB->offset + nv_crtc->shadow->offset; /* We do exist relative to the framebuffer */
2977 #endif
2978                 } else {
2979                         start += pNv->FB->offset;
2980                 }
2981         }
2982
2983         /* 30 bits addresses in 32 bits according to haiku */
2984         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_START, start & 0xfffffffc);
2985
2986         /* set NV4/NV10 byte adress: (bit0 - 1) */
2987         NVWriteVgaAttr(crtc, 0x13, (start & 0x3) << 1);
2988
2989         crtc->x = x;
2990         crtc->y = y;
2991 }
2992
2993 static void NVCrtcWriteDacMask(xf86CrtcPtr crtc, uint8_t value)
2994 {
2995   ScrnInfoPtr pScrn = crtc->scrn;
2996   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2997   NVPtr pNv = NVPTR(pScrn);
2998   volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2999
3000   NV_WR08(pDACReg, VGA_DAC_MASK, value);
3001 }
3002
3003 static uint8_t NVCrtcReadDacMask(xf86CrtcPtr crtc)
3004 {
3005   ScrnInfoPtr pScrn = crtc->scrn;
3006   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3007   NVPtr pNv = NVPTR(pScrn);
3008   volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3009
3010   return NV_RD08(pDACReg, VGA_DAC_MASK);
3011 }
3012
3013 static void NVCrtcWriteDacReadAddr(xf86CrtcPtr crtc, uint8_t value)
3014 {
3015   ScrnInfoPtr pScrn = crtc->scrn;
3016   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3017   NVPtr pNv = NVPTR(pScrn);
3018   volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3019
3020   NV_WR08(pDACReg, VGA_DAC_READ_ADDR, value);
3021 }
3022
3023 static void NVCrtcWriteDacWriteAddr(xf86CrtcPtr crtc, uint8_t value)
3024 {
3025   ScrnInfoPtr pScrn = crtc->scrn;
3026   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3027   NVPtr pNv = NVPTR(pScrn);
3028   volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3029
3030   NV_WR08(pDACReg, VGA_DAC_WRITE_ADDR, value);
3031 }
3032
3033 static void NVCrtcWriteDacData(xf86CrtcPtr crtc, uint8_t value)
3034 {
3035   ScrnInfoPtr pScrn = crtc->scrn;
3036   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3037   NVPtr pNv = NVPTR(pScrn);
3038   volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3039
3040   NV_WR08(pDACReg, VGA_DAC_DATA, value);
3041 }
3042
3043 static uint8_t NVCrtcReadDacData(xf86CrtcPtr crtc, uint8_t value)
3044 {
3045   ScrnInfoPtr pScrn = crtc->scrn;
3046   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3047   NVPtr pNv = NVPTR(pScrn);
3048   volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3049
3050   return NV_RD08(pDACReg, VGA_DAC_DATA);
3051 }
3052
3053 void NVCrtcLoadPalette(xf86CrtcPtr crtc)
3054 {
3055         int i;
3056         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3057         NVCrtcRegPtr regp;
3058         ScrnInfoPtr pScrn = crtc->scrn;
3059         NVPtr pNv = NVPTR(pScrn);
3060
3061         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
3062
3063         if (pNv->twoHeads)
3064                 NVCrtcSetOwner(crtc);
3065         NVCrtcWriteDacMask(crtc, 0xff);
3066         NVCrtcWriteDacWriteAddr(crtc, 0x00);
3067
3068         for (i = 0; i<768; i++) {
3069                 NVCrtcWriteDacData(crtc, regp->DAC[i]);
3070         }
3071         NVDisablePalette(crtc);
3072 }
3073
3074 /* on = unblank */
3075 void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
3076 {
3077         NVPtr pNv = NVPTR(crtc->scrn);
3078         unsigned char scrn;
3079
3080         if (pNv->twoHeads)
3081                 NVCrtcSetOwner(crtc);
3082
3083         scrn = NVReadVgaSeq(crtc, 0x01);
3084         if (on) {
3085                 scrn &= ~0x20;
3086         } else {
3087                 scrn |= 0x20;
3088         }
3089
3090         NVVgaSeqReset(crtc, TRUE);
3091         NVWriteVgaSeq(crtc, 0x01, scrn);
3092         NVVgaSeqReset(crtc, FALSE);
3093 }
3094
3095 /* Reset a mode after a drastic output resource change for example. */
3096 void NVCrtcModeFix(xf86CrtcPtr crtc)
3097 {
3098         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3099         Bool need_unlock;
3100
3101         if (!crtc->enabled)
3102                 return;
3103
3104         if (!xf86ModesEqual(&crtc->mode, &crtc->desiredMode)) /* not currently in X */
3105                 return;
3106
3107         DisplayModePtr adjusted_mode = xf86DuplicateMode(&crtc->mode);
3108         uint8_t dpms_mode = nv_crtc->last_dpms;
3109
3110         /* Set the crtc mode again. */
3111         crtc->funcs->dpms(crtc, DPMSModeOff);
3112         need_unlock = crtc->funcs->lock(crtc);
3113         crtc->funcs->mode_fixup(crtc, &crtc->mode, adjusted_mode);
3114         crtc->funcs->prepare(crtc);
3115         crtc->funcs->mode_set(crtc, &crtc->mode, adjusted_mode, crtc->x, crtc->y);
3116         crtc->funcs->commit(crtc);
3117         if (need_unlock)
3118                 crtc->funcs->unlock(crtc);
3119         crtc->funcs->dpms(crtc, dpms_mode);
3120
3121         /* Free mode. */
3122         xfree(adjusted_mode);
3123 }
3124
3125 /*************************************************************************** \
3126 |*                                                                           *|
3127 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
3128 |*                                                                           *|
3129 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
3130 |*     international laws.  Users and possessors of this source code are     *|
3131 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
3132 |*     use this code in individual and commercial software.                  *|
3133 |*                                                                           *|
3134 |*     Any use of this source code must include,  in the user documenta-     *|
3135 |*     tion and  internal comments to the code,  notices to the end user     *|
3136 |*     as follows:                                                           *|
3137 |*                                                                           *|
3138 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
3139 |*                                                                           *|
3140 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
3141 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
3142 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
3143 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
3144 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
3145 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
3146 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
3147 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
3148 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
3149 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
3150 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
3151 |*                                                                           *|
3152 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
3153 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
3154 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
3155 |*     computer  software  documentation,"  as such  terms  are  used in     *|
3156 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
3157 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
3158 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
3159 |*     all U.S. Government End Users  acquire the source code  with only     *|
3160 |*     those rights set forth herein.                                        *|
3161 |*                                                                           *|
3162  \***************************************************************************/