git.oblomov.eu Git - nouveau/blob - src/nv_hw.c

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   2 |*                                                                           *|
   3 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
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  14 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
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  37 |*                                                                           *|
  38  \***************************************************************************/
  39 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_hw.c,v 1.21 2006/06/16 00:19:33 mvojkovi Exp $ */
  40
  41 #ifdef HAVE_CONFIG_H
  42 #include "config.h"
  43 #endif
  44
  45 #include "nv_local.h"
  46 #include "compiler.h"
  47 #include "nv_include.h"
  48
  49
  50 void NVLockUnlock (
  51     NVPtr pNv,
  52     Bool  Lock
  53 )
  54 {
  55     CARD8 cr11;
  56
  57     VGA_WR08(pNv->PCIO, 0x3D4, 0x1F);
  58     VGA_WR08(pNv->PCIO, 0x3D5, Lock ? 0x99 : 0x57);
  59
  60     VGA_WR08(pNv->PCIO, 0x3D4, 0x11);
  61     cr11 = VGA_RD08(pNv->PCIO, 0x3D5);
  62     if(Lock) cr11 |= 0x80;
  63     else cr11 &= ~0x80;
  64     VGA_WR08(pNv->PCIO, 0x3D5, cr11);
  65 }
  66
  67 int NVShowHideCursor (
  68     NVPtr pNv,
  69     int   ShowHide
  70 )
  71 {
  72     int current = pNv->CurrentState->cursor1;
  73
  74     pNv->CurrentState->cursor1 = (pNv->CurrentState->cursor1 & 0xFE) |
  75                                  (ShowHide & 0x01);
  76     VGA_WR08(pNv->PCIO, 0x3D4, 0x31);
  77     VGA_WR08(pNv->PCIO, 0x3D5, pNv->CurrentState->cursor1);
  78
  79     if(pNv->Architecture == NV_ARCH_40) {  /* HW bug */
  80        volatile CARD32 curpos = pNv->PRAMDAC[0x0300/4];
  81        pNv->PRAMDAC[0x0300/4] = curpos;
  82     }
  83
  84     return (current & 0x01);
  85 }
  86
  87 /****************************************************************************\
  88 *                                                                            *
  89 * The video arbitration routines calculate some "magic" numbers.  Fixes      *
  90 * the snow seen when accessing the framebuffer without it.                   *
  91 * It just works (I hope).                                                    *
  92 *                                                                            *
  93 \****************************************************************************/
  94
  95 typedef struct {
  96   int graphics_lwm;
  97   int video_lwm;
  98   int graphics_burst_size;
  99   int video_burst_size;
 100   int valid;
 101 } nv4_fifo_info;
 102
 103 typedef struct {
 104   int pclk_khz;
 105   int mclk_khz;
 106   int nvclk_khz;
 107   char mem_page_miss;
 108   char mem_latency;
 109   int memory_width;
 110   char enable_video;
 111   char gr_during_vid;
 112   char pix_bpp;
 113   char mem_aligned;
 114   char enable_mp;
 115 } nv4_sim_state;
 116
 117 typedef struct {
 118   int graphics_lwm;
 119   int video_lwm;
 120   int graphics_burst_size;
 121   int video_burst_size;
 122   int valid;
 123 } nv10_fifo_info;
 124
 125 typedef struct {
 126   int pclk_khz;
 127   int mclk_khz;
 128   int nvclk_khz;
 129   char mem_page_miss;
 130   char mem_latency;
 131   int memory_type;
 132   int memory_width;
 133   char enable_video;
 134   char gr_during_vid;
 135   char pix_bpp;
 136   char mem_aligned;
 137   char enable_mp;
 138 } nv10_sim_state;
 139
 140
 141 static void nvGetClocks(NVPtr pNv, unsigned int *MClk, unsigned int *NVClk)
 142 {
 143     unsigned int pll, N, M, MB, NB, P;
 144
 145     if(pNv->Architecture >= NV_ARCH_40) {
 146        pll = pNv->PMC[0x4020/4];
 147        P = (pll >> 16) & 0x07;
 148        pll = pNv->PMC[0x4024/4];
 149        M = pll & 0xFF;
 150        N = (pll >> 8) & 0xFF;
 151        if(((pNv->Chipset & 0xfff0) == 0x0290) ||
 152           ((pNv->Chipset & 0xfff0) == 0x0390))
 153        {
 154           MB = 1;
 155           NB = 1;
 156        } else {
 157           MB = (pll >> 16) & 0xFF;
 158           NB = (pll >> 24) & 0xFF;
 159        }
 160        *MClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
 161
 162        pll = pNv->PMC[0x4000/4];
 163        P = (pll >> 16) & 0x07;
 164        pll = pNv->PMC[0x4004/4];
 165        M = pll & 0xFF;
 166        N = (pll >> 8) & 0xFF;
 167        MB = (pll >> 16) & 0xFF;
 168        NB = (pll >> 24) & 0xFF;
 169
 170        *NVClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
 171     } else
 172     if(pNv->twoStagePLL) {
 173        pll = pNv->PRAMDAC0[0x0504/4];
 174        M = pll & 0xFF;
 175        N = (pll >> 8) & 0xFF;
 176        P = (pll >> 16) & 0x0F;
 177        pll = pNv->PRAMDAC0[0x0574/4];
 178        if(pll & 0x80000000) {
 179            MB = pll & 0xFF;
 180            NB = (pll >> 8) & 0xFF;
 181        } else {
 182            MB = 1;
 183            NB = 1;
 184        }
 185        *MClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
 186
 187        pll = pNv->PRAMDAC0[0x0500/4];
 188        M = pll & 0xFF;
 189        N = (pll >> 8) & 0xFF;
 190        P = (pll >> 16) & 0x0F;
 191        pll = pNv->PRAMDAC0[0x0570/4];
 192        if(pll & 0x80000000) {
 193            MB = pll & 0xFF;
 194            NB = (pll >> 8) & 0xFF;
 195        } else {
 196            MB = 1;
 197            NB = 1;
 198        }
 199        *NVClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
 200     } else
 201     if(((pNv->Chipset & 0x0ff0) == 0x0300) ||
 202        ((pNv->Chipset & 0x0ff0) == 0x0330))
 203     {
 204        pll = pNv->PRAMDAC0[0x0504/4];
 205        M = pll & 0x0F;
 206        N = (pll >> 8) & 0xFF;
 207        P = (pll >> 16) & 0x07;
 208        if(pll & 0x00000080) {
 209            MB = (pll >> 4) & 0x07;
 210            NB = (pll >> 19) & 0x1f;
 211        } else {
 212            MB = 1;
 213            NB = 1;
 214        }
 215        *MClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
 216
 217        pll = pNv->PRAMDAC0[0x0500/4];
 218        M = pll & 0x0F;
 219        N = (pll >> 8) & 0xFF;
 220        P = (pll >> 16) & 0x07;
 221        if(pll & 0x00000080) {
 222            MB = (pll >> 4) & 0x07;
 223            NB = (pll >> 19) & 0x1f;
 224        } else {
 225            MB = 1;
 226            NB = 1;
 227        }
 228        *NVClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
 229     } else {
 230        pll = pNv->PRAMDAC0[0x0504/4];
 231        M = pll & 0xFF;
 232        N = (pll >> 8) & 0xFF;
 233        P = (pll >> 16) & 0x0F;
 234        *MClk = (N * pNv->CrystalFreqKHz / M) >> P;
 235
 236        pll = pNv->PRAMDAC0[0x0500/4];
 237        M = pll & 0xFF;
 238        N = (pll >> 8) & 0xFF;
 239        P = (pll >> 16) & 0x0F;
 240        *NVClk = (N * pNv->CrystalFreqKHz / M) >> P;
 241     }
 242
 243 #if 0
 244     ErrorF("NVClock = %i MHz, MEMClock = %i MHz\n", *NVClk/1000, *MClk/1000);
 245 #endif
 246 }
 247
 248
 249 static void nv4CalcArbitration (
 250     nv4_fifo_info *fifo,
 251     nv4_sim_state *arb
 252 )
 253 {
 254     int data, pagemiss, cas,width, video_enable, bpp;
 255     int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
 256     int found, mclk_extra, mclk_loop, cbs, m1, p1;
 257     int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
 258     int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate;
 259     int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt,clwm;
 260
 261     fifo->valid = 1;
 262     pclk_freq = arb->pclk_khz;
 263     mclk_freq = arb->mclk_khz;
 264     nvclk_freq = arb->nvclk_khz;
 265     pagemiss = arb->mem_page_miss;
 266     cas = arb->mem_latency;
 267     width = arb->memory_width >> 6;
 268     video_enable = arb->enable_video;
 269     bpp = arb->pix_bpp;
 270     mp_enable = arb->enable_mp;
 271     clwm = 0;
 272     vlwm = 0;
 273     cbs = 128;
 274     pclks = 2;
 275     nvclks = 2;
 276     nvclks += 2;
 277     nvclks += 1;
 278     mclks = 5;
 279     mclks += 3;
 280     mclks += 1;
 281     mclks += cas;
 282     mclks += 1;
 283     mclks += 1;
 284     mclks += 1;
 285     mclks += 1;
 286     mclk_extra = 3;
 287     nvclks += 2;
 288     nvclks += 1;
 289     nvclks += 1;
 290     nvclks += 1;
 291     if (mp_enable)
 292         mclks+=4;
 293     nvclks += 0;
 294     pclks += 0;
 295     found = 0;
 296     vbs = 0;
 297     while (found != 1)
 298     {
 299         fifo->valid = 1;
 300         found = 1;
 301         mclk_loop = mclks+mclk_extra;
 302         us_m = mclk_loop *1000*1000 / mclk_freq;
 303         us_n = nvclks*1000*1000 / nvclk_freq;
 304         us_p = nvclks*1000*1000 / pclk_freq;
 305         if (video_enable)
 306         {
 307             video_drain_rate = pclk_freq * 2;
 308             crtc_drain_rate = pclk_freq * bpp/8;
 309             vpagemiss = 2;
 310             vpagemiss += 1;
 311             crtpagemiss = 2;
 312             vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq;
 313             if (nvclk_freq * 2 > mclk_freq * width)
 314                 video_fill_us = cbs*1000*1000 / 16 / nvclk_freq ;
 315             else
 316                 video_fill_us = cbs*1000*1000 / (8 * width) / mclk_freq;
 317             us_video = vpm_us + us_m + us_n + us_p + video_fill_us;
 318             vlwm = us_video * video_drain_rate/(1000*1000);
 319             vlwm++;
 320             vbs = 128;
 321             if (vlwm > 128) vbs = 64;
 322             if (vlwm > (256-64)) vbs = 32;
 323             if (nvclk_freq * 2 > mclk_freq * width)
 324                 video_fill_us = vbs *1000*1000/ 16 / nvclk_freq ;
 325             else
 326                 video_fill_us = vbs*1000*1000 / (8 * width) / mclk_freq;
 327             cpm_us = crtpagemiss  * pagemiss *1000*1000/ mclk_freq;
 328             us_crt =
 329             us_video
 330             +video_fill_us
 331             +cpm_us
 332             +us_m + us_n +us_p
 333             ;
 334             clwm = us_crt * crtc_drain_rate/(1000*1000);
 335             clwm++;
 336         }
 337         else
 338         {
 339             crtc_drain_rate = pclk_freq * bpp/8;
 340             crtpagemiss = 2;
 341             crtpagemiss += 1;
 342             cpm_us = crtpagemiss  * pagemiss *1000*1000/ mclk_freq;
 343             us_crt =  cpm_us + us_m + us_n + us_p ;
 344             clwm = us_crt * crtc_drain_rate/(1000*1000);
 345             clwm++;
 346         }
 347         m1 = clwm + cbs - 512;
 348         p1 = m1 * pclk_freq / mclk_freq;
 349         p1 = p1 * bpp / 8;
 350         if ((p1 < m1) && (m1 > 0))
 351         {
 352             fifo->valid = 0;
 353             found = 0;
 354             if (mclk_extra ==0)   found = 1;
 355             mclk_extra--;
 356         }
 357         else if (video_enable)
 358         {
 359             if ((clwm > 511) || (vlwm > 255))
 360             {
 361                 fifo->valid = 0;
 362                 found = 0;
 363                 if (mclk_extra ==0)   found = 1;
 364                 mclk_extra--;
 365             }
 366         }
 367         else
 368         {
 369             if (clwm > 519)
 370             {
 371                 fifo->valid = 0;
 372                 found = 0;
 373                 if (mclk_extra ==0)   found = 1;
 374                 mclk_extra--;
 375             }
 376         }
 377         if (clwm < 384) clwm = 384;
 378         if (vlwm < 128) vlwm = 128;
 379         data = (int)(clwm);
 380         fifo->graphics_lwm = data;
 381         fifo->graphics_burst_size = 128;
 382         data = (int)((vlwm+15));
 383         fifo->video_lwm = data;
 384         fifo->video_burst_size = vbs;
 385     }
 386 }
 387
 388 static void nv4UpdateArbitrationSettings (
 389     unsigned      VClk,
 390     unsigned      pixelDepth,
 391     unsigned     *burst,
 392     unsigned     *lwm,
 393     NVPtr        pNv
 394 )
 395 {
 396     nv4_fifo_info fifo_data;
 397     nv4_sim_state sim_data;
 398     unsigned int MClk, NVClk, cfg1;
 399
 400     nvGetClocks(pNv, &MClk, &NVClk);
 401
 402     cfg1 = pNv->PFB[0x00000204/4];
 403     sim_data.pix_bpp        = (char)pixelDepth;
 404     sim_data.enable_video   = 0;
 405     sim_data.enable_mp      = 0;
 406     sim_data.memory_width   = (pNv->PEXTDEV[0x0000/4] & 0x10) ? 128 : 64;
 407     sim_data.mem_latency    = (char)cfg1 & 0x0F;
 408     sim_data.mem_aligned    = 1;
 409     sim_data.mem_page_miss  = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01));
 410     sim_data.gr_during_vid  = 0;
 411     sim_data.pclk_khz       = VClk;
 412     sim_data.mclk_khz       = MClk;
 413     sim_data.nvclk_khz      = NVClk;
 414     nv4CalcArbitration(&fifo_data, &sim_data);
 415     if (fifo_data.valid)
 416     {
 417         int  b = fifo_data.graphics_burst_size >> 4;
 418         *burst = 0;
 419         while (b >>= 1) (*burst)++;
 420         *lwm   = fifo_data.graphics_lwm >> 3;
 421     }
 422 }
 423
 424 static void nv10CalcArbitration (
 425     nv10_fifo_info *fifo,
 426     nv10_sim_state *arb
 427 )
 428 {
 429     int data, pagemiss, width, video_enable, bpp;
 430     int nvclks, mclks, pclks, vpagemiss, crtpagemiss;
 431     int nvclk_fill;
 432     int found, mclk_extra, mclk_loop, cbs, m1;
 433     int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
 434     int us_m, us_m_min, us_n, us_p, crtc_drain_rate;
 435     int vus_m;
 436     int vpm_us, us_video, cpm_us, us_crt,clwm;
 437     int clwm_rnd_down;
 438     int m2us, us_pipe_min, p1clk, p2;
 439     int min_mclk_extra;
 440     int us_min_mclk_extra;
 441
 442     fifo->valid = 1;
 443     pclk_freq = arb->pclk_khz; /* freq in KHz */
 444     mclk_freq = arb->mclk_khz;
 445     nvclk_freq = arb->nvclk_khz;
 446     pagemiss = arb->mem_page_miss;
 447     width = arb->memory_width/64;
 448     video_enable = arb->enable_video;
 449     bpp = arb->pix_bpp;
 450     mp_enable = arb->enable_mp;
 451     clwm = 0;
 452
 453     cbs = 512;
 454
 455     pclks = 4; /* lwm detect. */
 456
 457     nvclks = 3; /* lwm -> sync. */
 458     nvclks += 2; /* fbi bus cycles (1 req + 1 busy) */
 459
 460     mclks  = 1;   /* 2 edge sync.  may be very close to edge so just put one. */
 461
 462     mclks += 1;   /* arb_hp_req */
 463     mclks += 5;   /* ap_hp_req   tiling pipeline */
 464
 465     mclks += 2;    /* tc_req     latency fifo */
 466     mclks += 2;    /* fb_cas_n_  memory request to fbio block */
 467     mclks += 7;    /* sm_d_rdv   data returned from fbio block */
 468
 469     /* fb.rd.d.Put_gc   need to accumulate 256 bits for read */
 470     if (arb->memory_type == 0)
 471       if (arb->memory_width == 64) /* 64 bit bus */
 472         mclks += 4;
 473       else
 474         mclks += 2;
 475     else
 476       if (arb->memory_width == 64) /* 64 bit bus */
 477         mclks += 2;
 478       else
 479         mclks += 1;
 480
 481     if ((!video_enable) && (arb->memory_width == 128))
 482     {
 483       mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */
 484       min_mclk_extra = 17;
 485     }
 486     else
 487     {
 488       mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */
 489       /* mclk_extra = 4; */ /* Margin of error */
 490       min_mclk_extra = 18;
 491     }
 492
 493     nvclks += 1; /* 2 edge sync.  may be very close to edge so just put one. */
 494     nvclks += 1; /* fbi_d_rdv_n */
 495     nvclks += 1; /* Fbi_d_rdata */
 496     nvclks += 1; /* crtfifo load */
 497
 498     if(mp_enable)
 499       mclks+=4; /* Mp can get in with a burst of 8. */
 500     /* Extra clocks determined by heuristics */
 501
 502     nvclks += 0;
 503     pclks += 0;
 504     found = 0;
 505     while(found != 1) {
 506       fifo->valid = 1;
 507       found = 1;
 508       mclk_loop = mclks+mclk_extra;
 509       us_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */
 510       us_m_min = mclks * 1000*1000 / mclk_freq; /* Minimum Mclk latency in us */
 511       us_min_mclk_extra = min_mclk_extra *1000*1000 / mclk_freq;
 512       us_n = nvclks*1000*1000 / nvclk_freq;/* nvclk latency in us */
 513       us_p = pclks*1000*1000 / pclk_freq;/* nvclk latency in us */
 514       us_pipe_min = us_m_min + us_n + us_p;
 515
 516       vus_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */
 517
 518       if(video_enable) {
 519         crtc_drain_rate = pclk_freq * bpp/8; /* MB/s */
 520
 521         vpagemiss = 1; /* self generating page miss */
 522         vpagemiss += 1; /* One higher priority before */
 523
 524         crtpagemiss = 2; /* self generating page miss */
 525         if(mp_enable)
 526             crtpagemiss += 1; /* if MA0 conflict */
 527
 528         vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq;
 529
 530         us_video = vpm_us + vus_m; /* Video has separate read return path */
 531
 532         cpm_us = crtpagemiss  * pagemiss *1000*1000/ mclk_freq;
 533         us_crt =
 534           us_video  /* Wait for video */
 535           +cpm_us /* CRT Page miss */
 536           +us_m + us_n +us_p /* other latency */
 537           ;
 538
 539         clwm = us_crt * crtc_drain_rate/(1000*1000);
 540         clwm++; /* fixed point <= float_point - 1.  Fixes that */
 541       } else {
 542         crtc_drain_rate = pclk_freq * bpp/8; /* bpp * pclk/8 */
 543
 544         crtpagemiss = 1; /* self generating page miss */
 545         crtpagemiss += 1; /* MA0 page miss */
 546         if(mp_enable)
 547             crtpagemiss += 1; /* if MA0 conflict */
 548         cpm_us = crtpagemiss  * pagemiss *1000*1000/ mclk_freq;
 549         us_crt =  cpm_us + us_m + us_n + us_p ;
 550         clwm = us_crt * crtc_drain_rate/(1000*1000);
 551         clwm++; /* fixed point <= float_point - 1.  Fixes that */
 552
 553           /* Finally, a heuristic check when width == 64 bits */
 554           if(width == 1){
 555               nvclk_fill = nvclk_freq * 8;
 556               if(crtc_drain_rate * 100 >= nvclk_fill * 102)
 557                       clwm = 0xfff; /*Large number to fail */
 558
 559               else if(crtc_drain_rate * 100  >= nvclk_fill * 98) {
 560                   clwm = 1024;
 561                   cbs = 512;
 562               }
 563           }
 564       }
 565
 566
 567       /*
 568         Overfill check:
 569
 570         */
 571
 572       clwm_rnd_down = ((int)clwm/8)*8;
 573       if (clwm_rnd_down < clwm)
 574           clwm += 8;
 575
 576       m1 = clwm + cbs -  1024; /* Amount of overfill */
 577       m2us = us_pipe_min + us_min_mclk_extra;
 578
 579       /* pclk cycles to drain */
 580       p1clk = m2us * pclk_freq/(1000*1000);
 581       p2 = p1clk * bpp / 8; /* bytes drained. */
 582
 583       if((p2 < m1) && (m1 > 0)) {
 584           fifo->valid = 0;
 585           found = 0;
 586           if(min_mclk_extra == 0)   {
 587             if(cbs <= 32) {
 588               found = 1; /* Can't adjust anymore! */
 589             } else {
 590               cbs = cbs/2;  /* reduce the burst size */
 591             }
 592           } else {
 593             min_mclk_extra--;
 594           }
 595       } else {
 596         if (clwm > 1023){ /* Have some margin */
 597           fifo->valid = 0;
 598           found = 0;
 599           if(min_mclk_extra == 0)
 600               found = 1; /* Can't adjust anymore! */
 601           else
 602               min_mclk_extra--;
 603         }
 604       }
 605
 606       if(clwm < (1024-cbs+8)) clwm = 1024-cbs+8;
 607       data = (int)(clwm);
 608       /*  printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n", clwm, data ); */
 609       fifo->graphics_lwm = data;   fifo->graphics_burst_size = cbs;
 610
 611       fifo->video_lwm = 1024;  fifo->video_burst_size = 512;
 612     }
 613 }
 614
 615 static void nv10UpdateArbitrationSettings (
 616     unsigned      VClk,
 617     unsigned      pixelDepth,
 618     unsigned     *burst,
 619     unsigned     *lwm,
 620     NVPtr        pNv
 621 )
 622 {
 623     nv10_fifo_info fifo_data;
 624     nv10_sim_state sim_data;
 625     unsigned int MClk, NVClk, cfg1;
 626
 627     nvGetClocks(pNv, &MClk, &NVClk);
 628
 629     cfg1 = pNv->PFB[0x0204/4];
 630     sim_data.pix_bpp        = (char)pixelDepth;
 631     sim_data.enable_video   = 1;
 632     sim_data.enable_mp      = 0;
 633     sim_data.memory_type    = (pNv->PFB[0x0200/4] & 0x01) ? 1 : 0;
 634     sim_data.memory_width   = (pNv->PEXTDEV[0x0000/4] & 0x10) ? 128 : 64;
 635     sim_data.mem_latency    = (char)cfg1 & 0x0F;
 636     sim_data.mem_aligned    = 1;
 637     sim_data.mem_page_miss  = (char)(((cfg1>>4) &0x0F) + ((cfg1>>31) & 0x01));
 638     sim_data.gr_during_vid  = 0;
 639     sim_data.pclk_khz       = VClk;
 640     sim_data.mclk_khz       = MClk;
 641     sim_data.nvclk_khz      = NVClk;
 642     nv10CalcArbitration(&fifo_data, &sim_data);
 643     if (fifo_data.valid) {
 644         int  b = fifo_data.graphics_burst_size >> 4;
 645         *burst = 0;
 646         while (b >>= 1) (*burst)++;
 647         *lwm   = fifo_data.graphics_lwm >> 3;
 648     }
 649 }
 650
 651
 652 static void nv30UpdateArbitrationSettings (
 653     NVPtr        pNv,
 654     unsigned     *burst,
 655     unsigned     *lwm
 656 )
 657 {
 658     unsigned int MClk, NVClk;
 659     unsigned int fifo_size, burst_size, graphics_lwm;
 660
 661     fifo_size = 2048;
 662     burst_size = 512;
 663     graphics_lwm = fifo_size - burst_size;
 664
 665     nvGetClocks(pNv, &MClk, &NVClk);
 666
 667     *burst = 0;
 668     burst_size >>= 5;
 669     while(burst_size >>= 1) (*burst)++;
 670     *lwm = graphics_lwm >> 3;
 671 }
 672
 673 static void nForceUpdateArbitrationSettings (
 674     unsigned      VClk,
 675     unsigned      pixelDepth,
 676     unsigned     *burst,
 677     unsigned     *lwm,
 678     NVPtr        pNv
 679 )
 680 {
 681     nv10_fifo_info fifo_data;
 682     nv10_sim_state sim_data;
 683     unsigned int M, N, P, pll, MClk, NVClk, memctrl;
 684
 685     if((pNv->Chipset & 0x0FF0) == 0x01A0) {
 686        unsigned int uMClkPostDiv;
 687
 688        uMClkPostDiv = (pciReadLong(pciTag(0, 0, 3), 0x6C) >> 8) & 0xf;
 689        if(!uMClkPostDiv) uMClkPostDiv = 4;
 690        MClk = 400000 / uMClkPostDiv;
 691     } else {
 692        MClk = pciReadLong(pciTag(0, 0, 5), 0x4C) / 1000;
 693     }
 694
 695     pll = pNv->PRAMDAC0[0x0500/4];
 696     M = (pll >> 0)  & 0xFF; N = (pll >> 8)  & 0xFF; P = (pll >> 16) & 0x0F;
 697     NVClk  = (N * pNv->CrystalFreqKHz / M) >> P;
 698     sim_data.pix_bpp        = (char)pixelDepth;
 699     sim_data.enable_video   = 0;
 700     sim_data.enable_mp      = 0;
 701     sim_data.memory_type    = (pciReadLong(pciTag(0, 0, 1), 0x7C) >> 12) & 1;
 702     sim_data.memory_width   = 64;
 703
 704     memctrl = pciReadLong(pciTag(0, 0, 3), 0x00) >> 16;
 705
 706     if((memctrl == 0x1A9) || (memctrl == 0x1AB) || (memctrl == 0x1ED)) {
 707         int dimm[3];
 708
 709         dimm[0] = (pciReadLong(pciTag(0, 0, 2), 0x40) >> 8) & 0x4F;
 710         dimm[1] = (pciReadLong(pciTag(0, 0, 2), 0x44) >> 8) & 0x4F;
 711         dimm[2] = (pciReadLong(pciTag(0, 0, 2), 0x48) >> 8) & 0x4F;
 712
 713         if((dimm[0] + dimm[1]) != dimm[2]) {
 714              ErrorF("WARNING: "
 715               "your nForce DIMMs are not arranged in optimal banks!\n");
 716         }
 717     }
 718
 719     sim_data.mem_latency    = 3;
 720     sim_data.mem_aligned    = 1;
 721     sim_data.mem_page_miss  = 10;
 722     sim_data.gr_during_vid  = 0;
 723     sim_data.pclk_khz       = VClk;
 724     sim_data.mclk_khz       = MClk;
 725     sim_data.nvclk_khz      = NVClk;
 726     nv10CalcArbitration(&fifo_data, &sim_data);
 727     if (fifo_data.valid)
 728     {
 729         int  b = fifo_data.graphics_burst_size >> 4;
 730         *burst = 0;
 731         while (b >>= 1) (*burst)++;
 732         *lwm   = fifo_data.graphics_lwm >> 3;
 733     }
 734 }
 735
 736
 737 /****************************************************************************\
 738 *                                                                            *
 739 *                          RIVA Mode State Routines                          *
 740 *                                                                            *
 741 \****************************************************************************/
 742
 743 /*
 744  * Calculate the Video Clock parameters for the PLL.
 745  */
 746 static void CalcVClock (
 747     int           clockIn,
 748     int          *clockOut,
 749     U032         *pllOut,
 750     NVPtr        pNv
 751 )
 752 {
 753     unsigned lowM, highM;
 754     unsigned DeltaNew, DeltaOld;
 755     unsigned VClk, Freq;
 756     unsigned M, N, P;
 757
 758     DeltaOld = 0xFFFFFFFF;
 759
 760     VClk = (unsigned)clockIn;
 761
 762     if (pNv->CrystalFreqKHz == 13500) {
 763         lowM  = 7;
 764         highM = 13;
 765     } else {
 766         lowM  = 8;
 767         highM = 14;
 768     }
 769
 770     for (P = 0; P <= 4; P++) {
 771         Freq = VClk << P;
 772         if ((Freq >= 128000) && (Freq <= 350000)) {
 773             for (M = lowM; M <= highM; M++) {
 774                 N = ((VClk << P) * M) / pNv->CrystalFreqKHz;
 775                 if(N <= 255) {
 776                     Freq = ((pNv->CrystalFreqKHz * N) / M) >> P;
 777                     if (Freq > VClk)
 778                         DeltaNew = Freq - VClk;
 779                     else
 780                         DeltaNew = VClk - Freq;
 781                     if (DeltaNew < DeltaOld) {
 782                         *pllOut   = (P << 16) | (N << 8) | M;
 783                         *clockOut = Freq;
 784                         DeltaOld  = DeltaNew;
 785                     }
 786                 }
 787             }
 788         }
 789     }
 790 }
 791
 792 static void CalcVClock2Stage (
 793     int           clockIn,
 794     int          *clockOut,
 795     U032         *pllOut,
 796     U032         *pllBOut,
 797     NVPtr        pNv
 798 )
 799 {
 800     unsigned DeltaNew, DeltaOld;
 801     unsigned VClk, Freq;
 802     unsigned M, N, P;
 803
 804     DeltaOld = 0xFFFFFFFF;
 805
 806     *pllBOut = 0x80000401;  /* fixed at x4 for now */
 807
 808     VClk = (unsigned)clockIn;
 809
 810     for (P = 0; P <= 6; P++) {
 811         Freq = VClk << P;
 812         if ((Freq >= 400000) && (Freq <= 1000000)) {
 813             for (M = 1; M <= 13; M++) {
 814                 N = ((VClk << P) * M) / (pNv->CrystalFreqKHz << 2);
 815                 if((N >= 5) && (N <= 255)) {
 816                     Freq = (((pNv->CrystalFreqKHz << 2) * N) / M) >> P;
 817                     if (Freq > VClk)
 818                         DeltaNew = Freq - VClk;
 819                     else
 820                         DeltaNew = VClk - Freq;
 821                     if (DeltaNew < DeltaOld) {
 822                         *pllOut   = (P << 16) | (N << 8) | M;
 823                         *clockOut = Freq;
 824                         DeltaOld  = DeltaNew;
 825                     }
 826                 }
 827             }
 828         }
 829     }
 830 }
 831
 832 /*
 833  * Calculate extended mode parameters (SVGA) and save in a
 834  * mode state structure.
 835  */
 836 void NVCalcStateExt (
 837     NVPtr pNv,
 838     RIVA_HW_STATE *state,
 839     int            bpp,
 840     int            width,
 841     int            hDisplaySize,
 842     int            height,
 843     int            dotClock,
 844     int            flags
 845 )
 846 {
 847     int pixelDepth, VClk;
 848     /*
 849      * Save mode parameters.
 850      */
 851     state->bpp    = bpp;    /* this is not bitsPerPixel, it's 8,15,16,32 */
 852     state->width  = width;
 853     state->height = height;
 854     /*
 855      * Extended RIVA registers.
 856      */
 857     pixelDepth = (bpp + 1)/8;
 858     if(pNv->twoStagePLL)
 859         CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB, pNv);
 860     else
 861         CalcVClock(dotClock, &VClk, &state->pll, pNv);
 862
 863     switch (pNv->Architecture)
 864     {
 865         case NV_ARCH_04:
 866             nv4UpdateArbitrationSettings(VClk,
 867                                          pixelDepth * 8,
 868                                         &(state->arbitration0),
 869                                         &(state->arbitration1),
 870                                          pNv);
 871             state->cursor0  = 0x00;
 872             state->cursor1  = 0xbC;
 873             if (flags & V_DBLSCAN)
 874                 state->cursor1 |= 2;
 875             state->cursor2  = 0x00000000;
 876             state->pllsel   = 0x10000700;
 877             state->config   = 0x00001114;
 878             state->general  = bpp == 16 ? 0x00101100 : 0x00100100;
 879             state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
 880             break;
 881         case NV_ARCH_10:
 882         case NV_ARCH_20:
 883         case NV_ARCH_30:
 884         default:
 885             if(((pNv->Chipset & 0xfff0) == 0x0240) ||
 886                ((pNv->Chipset & 0xfff0) == 0x03D0))
 887             {
 888                 state->arbitration0 = 128;
 889                 state->arbitration1 = 0x0480;
 890             } else
 891             if(((pNv->Chipset & 0xffff) == 0x01A0) ||
 892                ((pNv->Chipset & 0xffff) == 0x01f0))
 893             {
 894                 nForceUpdateArbitrationSettings(VClk,
 895                                           pixelDepth * 8,
 896                                          &(state->arbitration0),
 897                                          &(state->arbitration1),
 898                                           pNv);
 899             } else if(pNv->Architecture < NV_ARCH_30) {
 900                 nv10UpdateArbitrationSettings(VClk,
 901                                           pixelDepth * 8,
 902                                          &(state->arbitration0),
 903                                          &(state->arbitration1),
 904                                           pNv);
 905             } else {
 906                 nv30UpdateArbitrationSettings(pNv,
 907                                          &(state->arbitration0),
 908                                          &(state->arbitration1));
 909             }
 910             state->cursor0  = 0x80 | (pNv->CursorStart >> 17);
 911             state->cursor1  = (pNv->CursorStart >> 11) << 2;
 912             state->cursor2  = pNv->CursorStart >> 24;
 913             if (flags & V_DBLSCAN)
 914                 state->cursor1 |= 2;
 915             state->pllsel   = 0x10000700;
 916             state->config   = pNv->PFB[0x00000200/4];
 917             state->general  = bpp == 16 ? 0x00101100 : 0x00100100;
 918             state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
 919             break;
 920     }
 921
 922     if(bpp != 8) /* DirectColor */
 923         state->general |= 0x00000030;
 924
 925     state->repaint0 = (((width / 8) * pixelDepth) & 0x700) >> 3;
 926     state->pixel    = (pixelDepth > 2) ? 3 : pixelDepth;
 927 }
 928
 929
 930 void NVLoadStateExt (
 931     NVPtr pNv,
 932     RIVA_HW_STATE *state
 933 )
 934 {
 935     int i, j;
 936
 937     pNv->PMC[0x0140/4] = 0x00000000;
 938     pNv->PMC[0x0200/4] = 0xFFFF00FF;
 939     pNv->PMC[0x0200/4] = 0xFFFFFFFF;
 940
 941     pNv->PTIMER[0x0200] = 0x00000008;
 942     pNv->PTIMER[0x0210] = 0x00000003;
 943     pNv->PTIMER[0x0140] = 0x00000000;
 944     pNv->PTIMER[0x0100] = 0xFFFFFFFF;
 945
 946     if(pNv->Architecture == NV_ARCH_04) {
 947         pNv->PFB[0x0200/4] = state->config;
 948     } else
 949     if((pNv->Architecture < NV_ARCH_40) ||
 950        ((pNv->Chipset & 0xfff0) == 0x0040))
 951     {
 952         for(i = 0; i < 8; i++) {
 953            pNv->PFB[(0x0240 + (i * 0x10))/4] = 0;
 954            pNv->PFB[(0x0244 + (i * 0x10))/4] = pNv->FbMapSize - 1;
 955         }
 956     } else {
 957         int regions = 12;
 958
 959         if(((pNv->Chipset & 0xfff0) == 0x0090) ||
 960            ((pNv->Chipset & 0xfff0) == 0x01D0) ||
 961            ((pNv->Chipset & 0xfff0) == 0x0290) ||
 962            ((pNv->Chipset & 0xfff0) == 0x0390) ||
 963            ((pNv->Chipset & 0xfff0) == 0x03D0))
 964         {
 965            regions = 15;
 966         }
 967
 968        for(i = 0; i < regions; i++) {
 969           pNv->PFB[(0x0600 + (i * 0x10))/4] = 0;
 970           pNv->PFB[(0x0604 + (i * 0x10))/4] = pNv->FbMapSize - 1;
 971        }
 972     }
 973
 974     if(pNv->Architecture >= NV_ARCH_40) {
 975        pNv->PRAMIN[0x0000] = 0x80000010;
 976        pNv->PRAMIN[0x0001] = 0x00101202;
 977        pNv->PRAMIN[0x0002] = 0x80000011;
 978        pNv->PRAMIN[0x0003] = 0x00101204;
 979        pNv->PRAMIN[0x0004] = 0x80000012;
 980        pNv->PRAMIN[0x0005] = 0x00101206;
 981        pNv->PRAMIN[0x0006] = 0x80000013;
 982        pNv->PRAMIN[0x0007] = 0x00101208;
 983        pNv->PRAMIN[0x0008] = 0x80000014;
 984        pNv->PRAMIN[0x0009] = 0x0010120A;
 985        pNv->PRAMIN[0x000A] = 0x80000015;
 986        pNv->PRAMIN[0x000B] = 0x0010120C;
 987        pNv->PRAMIN[0x000C] = 0x80000016;
 988        pNv->PRAMIN[0x000D] = 0x0010120E;
 989        pNv->PRAMIN[0x000E] = 0x80000017;
 990        pNv->PRAMIN[0x000F] = 0x00101210;
 991        pNv->PRAMIN[0x0800] = 0x00003000;
 992        pNv->PRAMIN[0x0801] = pNv->FbMapSize - 1;
 993        pNv->PRAMIN[0x0802] = 0x00000002;
 994        pNv->PRAMIN[0x0808] = 0x02080062;
 995        pNv->PRAMIN[0x0809] = 0x00000000;
 996        pNv->PRAMIN[0x080A] = 0x00001200;
 997        pNv->PRAMIN[0x080B] = 0x00001200;
 998        pNv->PRAMIN[0x080C] = 0x00000000;
 999        pNv->PRAMIN[0x080D] = 0x00000000;
1000        pNv->PRAMIN[0x0810] = 0x02080043;
1001        pNv->PRAMIN[0x0811] = 0x00000000;
1002        pNv->PRAMIN[0x0812] = 0x00000000;
1003        pNv->PRAMIN[0x0813] = 0x00000000;
1004        pNv->PRAMIN[0x0814] = 0x00000000;
1005        pNv->PRAMIN[0x0815] = 0x00000000;
1006        pNv->PRAMIN[0x0818] = 0x02080044;
1007        pNv->PRAMIN[0x0819] = 0x02000000;
1008        pNv->PRAMIN[0x081A] = 0x00000000;
1009        pNv->PRAMIN[0x081B] = 0x00000000;
1010        pNv->PRAMIN[0x081C] = 0x00000000;
1011        pNv->PRAMIN[0x081D] = 0x00000000;
1012        pNv->PRAMIN[0x0820] = 0x02080019;
1013        pNv->PRAMIN[0x0821] = 0x00000000;
1014        pNv->PRAMIN[0x0822] = 0x00000000;
1015        pNv->PRAMIN[0x0823] = 0x00000000;
1016        pNv->PRAMIN[0x0824] = 0x00000000;
1017        pNv->PRAMIN[0x0825] = 0x00000000;
1018        pNv->PRAMIN[0x0828] = 0x020A005C;
1019        pNv->PRAMIN[0x0829] = 0x00000000;
1020        pNv->PRAMIN[0x082A] = 0x00000000;
1021        pNv->PRAMIN[0x082B] = 0x00000000;
1022        pNv->PRAMIN[0x082C] = 0x00000000;
1023        pNv->PRAMIN[0x082D] = 0x00000000;
1024        pNv->PRAMIN[0x0830] = 0x0208009F;
1025        pNv->PRAMIN[0x0831] = 0x00000000;
1026        pNv->PRAMIN[0x0832] = 0x00001200;
1027        pNv->PRAMIN[0x0833] = 0x00001200;
1028        pNv->PRAMIN[0x0834] = 0x00000000;
1029        pNv->PRAMIN[0x0835] = 0x00000000;
1030        pNv->PRAMIN[0x0838] = 0x0208004A;
1031        pNv->PRAMIN[0x0839] = 0x02000000;
1032        pNv->PRAMIN[0x083A] = 0x00000000;
1033        pNv->PRAMIN[0x083B] = 0x00000000;
1034        pNv->PRAMIN[0x083C] = 0x00000000;
1035        pNv->PRAMIN[0x083D] = 0x00000000;
1036        pNv->PRAMIN[0x0840] = 0x02080077;
1037        pNv->PRAMIN[0x0841] = 0x00000000;
1038        pNv->PRAMIN[0x0842] = 0x00001200;
1039        pNv->PRAMIN[0x0843] = 0x00001200;
1040        pNv->PRAMIN[0x0844] = 0x00000000;
1041        pNv->PRAMIN[0x0845] = 0x00000000;
1042        pNv->PRAMIN[0x084C] = 0x00003002;
1043        pNv->PRAMIN[0x084D] = 0x00007FFF;
1044        pNv->PRAMIN[0x084E] = pNv->FbUsableSize | 0x00000002;
1045
1046 #if X_BYTE_ORDER == X_BIG_ENDIAN
1047        pNv->PRAMIN[0x080A] |= 0x01000000;
1048        pNv->PRAMIN[0x0812] |= 0x01000000;
1049        pNv->PRAMIN[0x081A] |= 0x01000000;
1050        pNv->PRAMIN[0x0822] |= 0x01000000;
1051        pNv->PRAMIN[0x082A] |= 0x01000000;
1052        pNv->PRAMIN[0x0832] |= 0x01000000;
1053        pNv->PRAMIN[0x083A] |= 0x01000000;
1054        pNv->PRAMIN[0x0842] |= 0x01000000;
1055        pNv->PRAMIN[0x0819] = 0x01000000;
1056        pNv->PRAMIN[0x0839] = 0x01000000;
1057 #endif
1058     } else {
1059        pNv->PRAMIN[0x0000] = 0x80000010;
1060        pNv->PRAMIN[0x0001] = 0x80011201;
1061        pNv->PRAMIN[0x0002] = 0x80000011;
1062        pNv->PRAMIN[0x0003] = 0x80011202;
1063        pNv->PRAMIN[0x0004] = 0x80000012;
1064        pNv->PRAMIN[0x0005] = 0x80011203;
1065        pNv->PRAMIN[0x0006] = 0x80000013;
1066        pNv->PRAMIN[0x0007] = 0x80011204;
1067        pNv->PRAMIN[0x0008] = 0x80000014;
1068        pNv->PRAMIN[0x0009] = 0x80011205;
1069        pNv->PRAMIN[0x000A] = 0x80000015;
1070        pNv->PRAMIN[0x000B] = 0x80011206;
1071        pNv->PRAMIN[0x000C] = 0x80000016;
1072        pNv->PRAMIN[0x000D] = 0x80011207;
1073        pNv->PRAMIN[0x000E] = 0x80000017;
1074        pNv->PRAMIN[0x000F] = 0x80011208;
1075        pNv->PRAMIN[0x0800] = 0x00003000;
1076        pNv->PRAMIN[0x0801] = pNv->FbMapSize - 1;
1077        pNv->PRAMIN[0x0802] = 0x00000002;
1078        pNv->PRAMIN[0x0803] = 0x00000002;
1079        if(pNv->Architecture >= NV_ARCH_10)
1080           pNv->PRAMIN[0x0804] = 0x01008062;
1081        else
1082           pNv->PRAMIN[0x0804] = 0x01008042;
1083        pNv->PRAMIN[0x0805] = 0x00000000;
1084        pNv->PRAMIN[0x0806] = 0x12001200;
1085        pNv->PRAMIN[0x0807] = 0x00000000;
1086        pNv->PRAMIN[0x0808] = 0x01008043;
1087        pNv->PRAMIN[0x0809] = 0x00000000;
1088        pNv->PRAMIN[0x080A] = 0x00000000;
1089        pNv->PRAMIN[0x080B] = 0x00000000;
1090        pNv->PRAMIN[0x080C] = 0x01008044;
1091        pNv->PRAMIN[0x080D] = 0x00000002;
1092        pNv->PRAMIN[0x080E] = 0x00000000;
1093        pNv->PRAMIN[0x080F] = 0x00000000;
1094        pNv->PRAMIN[0x0810] = 0x01008019;
1095        pNv->PRAMIN[0x0811] = 0x00000000;
1096        pNv->PRAMIN[0x0812] = 0x00000000;
1097        pNv->PRAMIN[0x0813] = 0x00000000;
1098        pNv->PRAMIN[0x0814] = 0x0100A05C;
1099        pNv->PRAMIN[0x0815] = 0x00000000;
1100        pNv->PRAMIN[0x0816] = 0x00000000;
1101        pNv->PRAMIN[0x0817] = 0x00000000;
1102        if(pNv->WaitVSyncPossible)
1103           pNv->PRAMIN[0x0818] = 0x0100809F;
1104        else
1105           pNv->PRAMIN[0x0818] = 0x0100805F;
1106        pNv->PRAMIN[0x0819] = 0x00000000;
1107        pNv->PRAMIN[0x081A] = 0x12001200;
1108        pNv->PRAMIN[0x081B] = 0x00000000;
1109        pNv->PRAMIN[0x081C] = 0x0100804A;
1110        pNv->PRAMIN[0x081D] = 0x00000002;
1111        pNv->PRAMIN[0x081E] = 0x00000000;
1112        pNv->PRAMIN[0x081F] = 0x00000000;
1113        pNv->PRAMIN[0x0820] = 0x01018077;
1114        pNv->PRAMIN[0x0821] = 0x00000000;
1115        pNv->PRAMIN[0x0822] = 0x12001200;
1116        pNv->PRAMIN[0x0823] = 0x00000000;
1117        pNv->PRAMIN[0x0824] = 0x00003002;
1118        pNv->PRAMIN[0x0825] = 0x00007FFF;
1119        pNv->PRAMIN[0x0826] = pNv->FbUsableSize | 0x00000002;
1120        pNv->PRAMIN[0x0827] = 0x00000002;
1121
1122 #if X_BYTE_ORDER == X_BIG_ENDIAN
1123        pNv->PRAMIN[0x0804] |= 0x00080000;
1124        pNv->PRAMIN[0x0808] |= 0x00080000;
1125        pNv->PRAMIN[0x080C] |= 0x00080000;
1126        pNv->PRAMIN[0x0810] |= 0x00080000;
1127        pNv->PRAMIN[0x0814] |= 0x00080000;
1128        pNv->PRAMIN[0x0818] |= 0x00080000;
1129        pNv->PRAMIN[0x081C] |= 0x00080000;
1130        pNv->PRAMIN[0x0820] |= 0x00080000;
1131        pNv->PRAMIN[0x080D] = 0x00000001;
1132        pNv->PRAMIN[0x081D] = 0x00000001;
1133 #endif
1134     }
1135
1136     if(pNv->Architecture < NV_ARCH_10) {
1137        if((pNv->Chipset & 0x0fff) == 0x0020) {
1138            pNv->PRAMIN[0x0824] |= 0x00020000;
1139            pNv->PRAMIN[0x0826] += pNv->FbAddress;
1140        }
1141        pNv->PGRAPH[0x0080/4] = 0x000001FF;
1142        pNv->PGRAPH[0x0080/4] = 0x1230C000;
1143        pNv->PGRAPH[0x0084/4] = 0x72111101;
1144        pNv->PGRAPH[0x0088/4] = 0x11D5F071;
1145        pNv->PGRAPH[0x008C/4] = 0x0004FF31;
1146        pNv->PGRAPH[0x008C/4] = 0x4004FF31;
1147
1148        pNv->PGRAPH[0x0140/4] = 0x00000000;
1149        pNv->PGRAPH[0x0100/4] = 0xFFFFFFFF;
1150        pNv->PGRAPH[0x0170/4] = 0x10010100;
1151        pNv->PGRAPH[0x0710/4] = 0xFFFFFFFF;
1152        pNv->PGRAPH[0x0720/4] = 0x00000001;
1153
1154        pNv->PGRAPH[0x0810/4] = 0x00000000;
1155        pNv->PGRAPH[0x0608/4] = 0xFFFFFFFF;
1156     } else {
1157        pNv->PGRAPH[0x0080/4] = 0xFFFFFFFF;
1158        pNv->PGRAPH[0x0080/4] = 0x00000000;
1159
1160        pNv->PGRAPH[0x0140/4] = 0x00000000;
1161        pNv->PGRAPH[0x0100/4] = 0xFFFFFFFF;
1162        pNv->PGRAPH[0x0144/4] = 0x10010100;
1163        pNv->PGRAPH[0x0714/4] = 0xFFFFFFFF;
1164        pNv->PGRAPH[0x0720/4] = 0x00000001;
1165        pNv->PGRAPH[0x0710/4] &= 0x0007ff00;
1166        pNv->PGRAPH[0x0710/4] |= 0x00020100;
1167
1168        if(pNv->Architecture == NV_ARCH_10) {
1169            pNv->PGRAPH[0x0084/4] = 0x00118700;
1170            pNv->PGRAPH[0x0088/4] = 0x24E00810;
1171            pNv->PGRAPH[0x008C/4] = 0x55DE0030;
1172
1173            for(i = 0; i < 32; i++)
1174              pNv->PGRAPH[(0x0B00/4) + i] = pNv->PFB[(0x0240/4) + i];
1175
1176            pNv->PGRAPH[0x640/4] = 0;
1177            pNv->PGRAPH[0x644/4] = 0;
1178            pNv->PGRAPH[0x684/4] = pNv->FbMapSize - 1;
1179            pNv->PGRAPH[0x688/4] = pNv->FbMapSize - 1;
1180
1181            pNv->PGRAPH[0x0810/4] = 0x00000000;
1182            pNv->PGRAPH[0x0608/4] = 0xFFFFFFFF;
1183        } else {
1184            if(pNv->Architecture >= NV_ARCH_40) {
1185               pNv->PGRAPH[0x0084/4] = 0x401287c0;
1186               pNv->PGRAPH[0x008C/4] = 0x60de8051;
1187               pNv->PGRAPH[0x0090/4] = 0x00008000;
1188               pNv->PGRAPH[0x0610/4] = 0x00be3c5f;
1189
1190               j = pNv->REGS[0x1540/4] & 0xff;
1191               if(j) {
1192                   for(i = 0; !(j & 1); j >>= 1, i++);
1193                   pNv->PGRAPH[0x5000/4] = i;
1194               }
1195
1196               if((pNv->Chipset & 0xfff0) == 0x0040) {
1197                  pNv->PGRAPH[0x09b0/4] = 0x83280fff;
1198                  pNv->PGRAPH[0x09b4/4] = 0x000000a0;
1199               } else {
1200                  pNv->PGRAPH[0x0820/4] = 0x83280eff;
1201                  pNv->PGRAPH[0x0824/4] = 0x000000a0;
1202               }
1203
1204               switch(pNv->Chipset & 0xfff0) {
1205               case 0x0040:
1206               case 0x0210:
1207                  pNv->PGRAPH[0x09b8/4] = 0x0078e366;
1208                  pNv->PGRAPH[0x09bc/4] = 0x0000014c;
1209                  pNv->PFB[0x033C/4] &= 0xffff7fff;
1210                  break;
1211               case 0x00C0:
1212               case 0x0120:
1213                  pNv->PGRAPH[0x0828/4] = 0x007596ff;
1214                  pNv->PGRAPH[0x082C/4] = 0x00000108;
1215                  break;
1216               case 0x0160:
1217               case 0x01D0:
1218               case 0x0240:
1219               case 0x03D0:
1220                  pNv->PMC[0x1700/4] = pNv->PFB[0x020C/4];
1221                  pNv->PMC[0x1704/4] = 0;
1222                  pNv->PMC[0x1708/4] = 0;
1223                  pNv->PMC[0x170C/4] = pNv->PFB[0x020C/4];
1224                  pNv->PGRAPH[0x0860/4] = 0;
1225                  pNv->PGRAPH[0x0864/4] = 0;
1226                  pNv->PRAMDAC[0x0608/4] |= 0x00100000;
1227                  break;
1228               case 0x0140:
1229                  pNv->PGRAPH[0x0828/4] = 0x0072cb77;
1230                  pNv->PGRAPH[0x082C/4] = 0x00000108;
1231                  break;
1232               case 0x0220:
1233                  pNv->PGRAPH[0x0860/4] = 0;
1234                  pNv->PGRAPH[0x0864/4] = 0;
1235                  pNv->PRAMDAC[0x0608/4] |= 0x00100000;
1236                  break;
1237               case 0x0090:
1238               case 0x0290:
1239               case 0x0390:
1240                  pNv->PRAMDAC[0x0608/4] |= 0x00100000;
1241                  pNv->PGRAPH[0x0828/4] = 0x07830610;
1242                  pNv->PGRAPH[0x082C/4] = 0x0000016A;
1243                  break;
1244               default:
1245                  break;
1246               };
1247
1248               pNv->PGRAPH[0x0b38/4] = 0x2ffff800;
1249               pNv->PGRAPH[0x0b3c/4] = 0x00006000;
1250               pNv->PGRAPH[0x032C/4] = 0x01000000;
1251               pNv->PGRAPH[0x0220/4] = 0x00001200;
1252            } else
1253            if(pNv->Architecture == NV_ARCH_30) {
1254               pNv->PGRAPH[0x0084/4] = 0x40108700;
1255               pNv->PGRAPH[0x0890/4] = 0x00140000;
1256               pNv->PGRAPH[0x008C/4] = 0xf00e0431;
1257               pNv->PGRAPH[0x0090/4] = 0x00008000;
1258               pNv->PGRAPH[0x0610/4] = 0xf04b1f36;
1259               pNv->PGRAPH[0x0B80/4] = 0x1002d888;
1260               pNv->PGRAPH[0x0B88/4] = 0x62ff007f;
1261            } else {
1262               pNv->PGRAPH[0x0084/4] = 0x00118700;
1263               pNv->PGRAPH[0x008C/4] = 0xF20E0431;
1264               pNv->PGRAPH[0x0090/4] = 0x00000000;
1265               pNv->PGRAPH[0x009C/4] = 0x00000040;
1266
1267               if((pNv->Chipset & 0x0ff0) >= 0x0250) {
1268                  pNv->PGRAPH[0x0890/4] = 0x00080000;
1269                  pNv->PGRAPH[0x0610/4] = 0x304B1FB6;
1270                  pNv->PGRAPH[0x0B80/4] = 0x18B82880;
1271                  pNv->PGRAPH[0x0B84/4] = 0x44000000;
1272                  pNv->PGRAPH[0x0098/4] = 0x40000080;
1273                  pNv->PGRAPH[0x0B88/4] = 0x000000ff;
1274               } else {
1275                  pNv->PGRAPH[0x0880/4] = 0x00080000;
1276                  pNv->PGRAPH[0x0094/4] = 0x00000005;
1277                  pNv->PGRAPH[0x0B80/4] = 0x45CAA208;
1278                  pNv->PGRAPH[0x0B84/4] = 0x24000000;
1279                  pNv->PGRAPH[0x0098/4] = 0x00000040;
1280                  pNv->PGRAPH[0x0750/4] = 0x00E00038;
1281                  pNv->PGRAPH[0x0754/4] = 0x00000030;
1282                  pNv->PGRAPH[0x0750/4] = 0x00E10038;
1283                  pNv->PGRAPH[0x0754/4] = 0x00000030;
1284               }
1285            }
1286
1287            if((pNv->Architecture < NV_ARCH_40) ||
1288               ((pNv->Chipset & 0xfff0) == 0x0040))
1289            {
1290               for(i = 0; i < 32; i++) {
1291                 pNv->PGRAPH[(0x0900/4) + i] = pNv->PFB[(0x0240/4) + i];
1292                 pNv->PGRAPH[(0x6900/4) + i] = pNv->PFB[(0x0240/4) + i];
1293               }
1294            } else {
1295               if(((pNv->Chipset & 0xfff0) == 0x0090) ||
1296                  ((pNv->Chipset & 0xfff0) == 0x01D0) ||
1297                  ((pNv->Chipset & 0xfff0) == 0x0290) ||
1298                  ((pNv->Chipset & 0xfff0) == 0x0390) ||
1299                  ((pNv->Chipset & 0xfff0) == 0x03D0))
1300               {
1301                  for(i = 0; i < 60; i++) {
1302                    pNv->PGRAPH[(0x0D00/4) + i] = pNv->PFB[(0x0600/4) + i];
1303                    pNv->PGRAPH[(0x6900/4) + i] = pNv->PFB[(0x0600/4) + i];
1304                  }
1305               } else {
1306                  for(i = 0; i < 48; i++) {
1307                    pNv->PGRAPH[(0x0900/4) + i] = pNv->PFB[(0x0600/4) + i];
1308                    if(((pNv->Chipset & 0xfff0) != 0x0160) &&
1309                       ((pNv->Chipset & 0xfff0) != 0x0220) &&
1310                       ((pNv->Chipset & 0xfff0) != 0x0240))
1311                    {
1312                       pNv->PGRAPH[(0x6900/4) + i] = pNv->PFB[(0x0600/4) + i];
1313                    }
1314                  }
1315               }
1316            }
1317
1318            if(pNv->Architecture >= NV_ARCH_40) {
1319               if((pNv->Chipset & 0xfff0) == 0x0040) {
1320                  pNv->PGRAPH[0x09A4/4] = pNv->PFB[0x0200/4];
1321                  pNv->PGRAPH[0x09A8/4] = pNv->PFB[0x0204/4];
1322                  pNv->PGRAPH[0x69A4/4] = pNv->PFB[0x0200/4];
1323                  pNv->PGRAPH[0x69A8/4] = pNv->PFB[0x0204/4];
1324
1325                  pNv->PGRAPH[0x0820/4] = 0;
1326                  pNv->PGRAPH[0x0824/4] = 0;
1327                  pNv->PGRAPH[0x0864/4] = pNv->FbMapSize - 1;
1328                  pNv->PGRAPH[0x0868/4] = pNv->FbMapSize - 1;
1329               } else {
1330                  if(((pNv->Chipset & 0xfff0) == 0x0090) ||
1331                     ((pNv->Chipset & 0xfff0) == 0x01D0) ||
1332                     ((pNv->Chipset & 0xfff0) == 0x0290) ||
1333                     ((pNv->Chipset & 0xfff0) == 0x0390))
1334                  {
1335                     pNv->PGRAPH[0x0DF0/4] = pNv->PFB[0x0200/4];
1336                     pNv->PGRAPH[0x0DF4/4] = pNv->PFB[0x0204/4];
1337                  } else {
1338                     pNv->PGRAPH[0x09F0/4] = pNv->PFB[0x0200/4];
1339                     pNv->PGRAPH[0x09F4/4] = pNv->PFB[0x0204/4];
1340                  }
1341                  pNv->PGRAPH[0x69F0/4] = pNv->PFB[0x0200/4];
1342                  pNv->PGRAPH[0x69F4/4] = pNv->PFB[0x0204/4];
1343
1344                  pNv->PGRAPH[0x0840/4] = 0;
1345                  pNv->PGRAPH[0x0844/4] = 0;
1346                  pNv->PGRAPH[0x08a0/4] = pNv->FbMapSize - 1;
1347                  pNv->PGRAPH[0x08a4/4] = pNv->FbMapSize - 1;
1348               }
1349            } else {
1350               pNv->PGRAPH[0x09A4/4] = pNv->PFB[0x0200/4];
1351               pNv->PGRAPH[0x09A8/4] = pNv->PFB[0x0204/4];
1352               pNv->PGRAPH[0x0750/4] = 0x00EA0000;
1353               pNv->PGRAPH[0x0754/4] = pNv->PFB[0x0200/4];
1354               pNv->PGRAPH[0x0750/4] = 0x00EA0004;
1355               pNv->PGRAPH[0x0754/4] = pNv->PFB[0x0204/4];
1356
1357               pNv->PGRAPH[0x0820/4] = 0;
1358               pNv->PGRAPH[0x0824/4] = 0;
1359               pNv->PGRAPH[0x0864/4] = pNv->FbMapSize - 1;
1360               pNv->PGRAPH[0x0868/4] = pNv->FbMapSize - 1;
1361            }
1362
1363            pNv->PGRAPH[0x0B20/4] = 0x00000000;
1364            pNv->PGRAPH[0x0B04/4] = 0xFFFFFFFF;
1365        }
1366     }
1367     pNv->PGRAPH[0x053C/4] = 0;
1368     pNv->PGRAPH[0x0540/4] = 0;
1369     pNv->PGRAPH[0x0544/4] = 0x00007FFF;
1370     pNv->PGRAPH[0x0548/4] = 0x00007FFF;
1371
1372     pNv->PFIFO[0x0140] = 0x00000000;
1373     pNv->PFIFO[0x0141] = 0x00000001;
1374     pNv->PFIFO[0x0480] = 0x00000000;
1375     pNv->PFIFO[0x0494] = 0x00000000;
1376     if(pNv->Architecture >= NV_ARCH_40)
1377        pNv->PFIFO[0x0481] = 0x00010000;
1378     else
1379        pNv->PFIFO[0x0481] = 0x00000100;
1380     pNv->PFIFO[0x0490] = 0x00000000;
1381     pNv->PFIFO[0x0491] = 0x00000000;
1382     if(pNv->Architecture >= NV_ARCH_40)
1383        pNv->PFIFO[0x048B] = 0x00001213;
1384     else
1385        pNv->PFIFO[0x048B] = 0x00001209;
1386     pNv->PFIFO[0x0400] = 0x00000000;
1387     pNv->PFIFO[0x0414] = 0x00000000;
1388     pNv->PFIFO[0x0084] = 0x03000100;
1389     pNv->PFIFO[0x0085] = 0x00000110;
1390     pNv->PFIFO[0x0086] = 0x00000112;
1391     pNv->PFIFO[0x0143] = 0x0000FFFF;
1392     pNv->PFIFO[0x0496] = 0x0000FFFF;
1393     pNv->PFIFO[0x0050] = 0x00000000;
1394     pNv->PFIFO[0x0040] = 0xFFFFFFFF;
1395     pNv->PFIFO[0x0415] = 0x00000001;
1396     pNv->PFIFO[0x048C] = 0x00000000;
1397     pNv->PFIFO[0x04A0] = 0x00000000;
1398 #if X_BYTE_ORDER == X_BIG_ENDIAN
1399     pNv->PFIFO[0x0489] = 0x800F0078;
1400 #else
1401     pNv->PFIFO[0x0489] = 0x000F0078;
1402 #endif
1403     pNv->PFIFO[0x0488] = 0x00000001;
1404     pNv->PFIFO[0x0480] = 0x00000001;
1405     pNv->PFIFO[0x0494] = 0x00000001;
1406     pNv->PFIFO[0x0495] = 0x00000001;
1407     pNv->PFIFO[0x0140] = 0x00000001;
1408
1409     if(pNv->Architecture >= NV_ARCH_10) {
1410         if(pNv->twoHeads) {
1411            pNv->PCRTC0[0x0860/4] = state->head;
1412            pNv->PCRTC0[0x2860/4] = state->head2;
1413         }
1414         pNv->PRAMDAC[0x0404/4] |= (1 << 25);
1415
1416         pNv->PMC[0x8704/4] = 1;
1417         pNv->PMC[0x8140/4] = 0;
1418         pNv->PMC[0x8920/4] = 0;
1419         pNv->PMC[0x8924/4] = 0;
1420         pNv->PMC[0x8908/4] = pNv->FbMapSize - 1;
1421         pNv->PMC[0x890C/4] = pNv->FbMapSize - 1;
1422         pNv->PMC[0x1588/4] = 0;
1423
1424         pNv->PCRTC[0x0810/4] = state->cursorConfig;
1425         pNv->PCRTC[0x0830/4] = state->displayV - 3;
1426         pNv->PCRTC[0x0834/4] = state->displayV - 1;
1427
1428         if(pNv->FlatPanel) {
1429            if((pNv->Chipset & 0x0ff0) == 0x0110) {
1430                pNv->PRAMDAC[0x0528/4] = state->dither;
1431            } else
1432            if(pNv->twoHeads) {
1433                pNv->PRAMDAC[0x083C/4] = state->dither;
1434            }
1435
1436            VGA_WR08(pNv->PCIO, 0x03D4, 0x53);
1437            VGA_WR08(pNv->PCIO, 0x03D5, state->timingH);
1438            VGA_WR08(pNv->PCIO, 0x03D4, 0x54);
1439            VGA_WR08(pNv->PCIO, 0x03D5, state->timingV);
1440            VGA_WR08(pNv->PCIO, 0x03D4, 0x21);
1441            VGA_WR08(pNv->PCIO, 0x03D5, 0xfa);
1442         }
1443
1444         VGA_WR08(pNv->PCIO, 0x03D4, 0x41);
1445         VGA_WR08(pNv->PCIO, 0x03D5, state->extra);
1446     }
1447
1448     VGA_WR08(pNv->PCIO, 0x03D4, 0x19);
1449     VGA_WR08(pNv->PCIO, 0x03D5, state->repaint0);
1450     VGA_WR08(pNv->PCIO, 0x03D4, 0x1A);
1451     VGA_WR08(pNv->PCIO, 0x03D5, state->repaint1);
1452     VGA_WR08(pNv->PCIO, 0x03D4, 0x25);
1453     VGA_WR08(pNv->PCIO, 0x03D5, state->screen);
1454     VGA_WR08(pNv->PCIO, 0x03D4, 0x28);
1455     VGA_WR08(pNv->PCIO, 0x03D5, state->pixel);
1456     VGA_WR08(pNv->PCIO, 0x03D4, 0x2D);
1457     VGA_WR08(pNv->PCIO, 0x03D5, state->horiz);
1458     VGA_WR08(pNv->PCIO, 0x03D4, 0x1C);
1459     VGA_WR08(pNv->PCIO, 0x03D5, state->fifo);
1460     VGA_WR08(pNv->PCIO, 0x03D4, 0x1B);
1461     VGA_WR08(pNv->PCIO, 0x03D5, state->arbitration0);
1462     VGA_WR08(pNv->PCIO, 0x03D4, 0x20);
1463     VGA_WR08(pNv->PCIO, 0x03D5, state->arbitration1);
1464     if(pNv->Architecture >= NV_ARCH_30) {
1465       VGA_WR08(pNv->PCIO, 0x03D4, 0x47);
1466       VGA_WR08(pNv->PCIO, 0x03D5, state->arbitration1 >> 8);
1467     }
1468     VGA_WR08(pNv->PCIO, 0x03D4, 0x30);
1469     VGA_WR08(pNv->PCIO, 0x03D5, state->cursor0);
1470     VGA_WR08(pNv->PCIO, 0x03D4, 0x31);
1471     VGA_WR08(pNv->PCIO, 0x03D5, state->cursor1);
1472     VGA_WR08(pNv->PCIO, 0x03D4, 0x2F);
1473     VGA_WR08(pNv->PCIO, 0x03D5, state->cursor2);
1474     VGA_WR08(pNv->PCIO, 0x03D4, 0x39);
1475     VGA_WR08(pNv->PCIO, 0x03D5, state->interlace);
1476
1477     if(!pNv->FlatPanel) {
1478        pNv->PRAMDAC0[0x050C/4] = state->pllsel;
1479        pNv->PRAMDAC0[0x0508/4] = state->vpll;
1480        if(pNv->twoHeads)
1481           pNv->PRAMDAC0[0x0520/4] = state->vpll2;
1482        if(pNv->twoStagePLL) {
1483           pNv->PRAMDAC0[0x0578/4] = state->vpllB;
1484           pNv->PRAMDAC0[0x057C/4] = state->vpll2B;
1485        }
1486     } else {
1487        pNv->PRAMDAC[0x0848/4] = state->scale;
1488        pNv->PRAMDAC[0x0828/4] = state->crtcSync;
1489     }
1490     pNv->PRAMDAC[0x0600/4] = state->general;
1491
1492     pNv->PCRTC[0x0140/4] = 0;
1493     pNv->PCRTC[0x0100/4] = 1;
1494
1495     pNv->CurrentState = state;
1496 }
1497
1498 void NVUnloadStateExt
1499 (
1500     NVPtr pNv,
1501     RIVA_HW_STATE *state
1502 )
1503 {
1504     VGA_WR08(pNv->PCIO, 0x03D4, 0x19);
1505     state->repaint0     = VGA_RD08(pNv->PCIO, 0x03D5);
1506     VGA_WR08(pNv->PCIO, 0x03D4, 0x1A);
1507     state->repaint1     = VGA_RD08(pNv->PCIO, 0x03D5);
1508     VGA_WR08(pNv->PCIO, 0x03D4, 0x25);
1509     state->screen       = VGA_RD08(pNv->PCIO, 0x03D5);
1510     VGA_WR08(pNv->PCIO, 0x03D4, 0x28);
1511     state->pixel        = VGA_RD08(pNv->PCIO, 0x03D5);
1512     VGA_WR08(pNv->PCIO, 0x03D4, 0x2D);
1513     state->horiz        = VGA_RD08(pNv->PCIO, 0x03D5);
1514     VGA_WR08(pNv->PCIO, 0x03D4, 0x1C);
1515     state->fifo         = VGA_RD08(pNv->PCIO, 0x03D5);
1516     VGA_WR08(pNv->PCIO, 0x03D4, 0x1B);
1517     state->arbitration0 = VGA_RD08(pNv->PCIO, 0x03D5);
1518     VGA_WR08(pNv->PCIO, 0x03D4, 0x20);
1519     state->arbitration1 = VGA_RD08(pNv->PCIO, 0x03D5);
1520     if(pNv->Architecture >= NV_ARCH_30) {
1521        VGA_WR08(pNv->PCIO, 0x03D4, 0x47);
1522        state->arbitration1 |= (VGA_RD08(pNv->PCIO, 0x03D5) & 1) << 8;
1523     }
1524     VGA_WR08(pNv->PCIO, 0x03D4, 0x30);
1525     state->cursor0      = VGA_RD08(pNv->PCIO, 0x03D5);
1526     VGA_WR08(pNv->PCIO, 0x03D4, 0x31);
1527     state->cursor1      = VGA_RD08(pNv->PCIO, 0x03D5);
1528     VGA_WR08(pNv->PCIO, 0x03D4, 0x2F);
1529     state->cursor2      = VGA_RD08(pNv->PCIO, 0x03D5);
1530     VGA_WR08(pNv->PCIO, 0x03D4, 0x39);
1531     state->interlace    = VGA_RD08(pNv->PCIO, 0x03D5);
1532     state->vpll         = pNv->PRAMDAC0[0x0508/4];
1533     if(pNv->twoHeads)
1534        state->vpll2     = pNv->PRAMDAC0[0x0520/4];
1535     if(pNv->twoStagePLL) {
1536         state->vpllB    = pNv->PRAMDAC0[0x0578/4];
1537         state->vpll2B   = pNv->PRAMDAC0[0x057C/4];
1538     }
1539     state->pllsel       = pNv->PRAMDAC0[0x050C/4];
1540     state->general      = pNv->PRAMDAC[0x0600/4];
1541     state->scale        = pNv->PRAMDAC[0x0848/4];
1542     state->config       = pNv->PFB[0x0200/4];
1543
1544     if(pNv->Architecture >= NV_ARCH_10) {
1545         if(pNv->twoHeads) {
1546            state->head     = pNv->PCRTC0[0x0860/4];
1547            state->head2    = pNv->PCRTC0[0x2860/4];
1548            VGA_WR08(pNv->PCIO, 0x03D4, 0x44);
1549            state->crtcOwner = VGA_RD08(pNv->PCIO, 0x03D5);
1550         }
1551         VGA_WR08(pNv->PCIO, 0x03D4, 0x41);
1552         state->extra = VGA_RD08(pNv->PCIO, 0x03D5);
1553         state->cursorConfig = pNv->PCRTC[0x0810/4];
1554
1555         if((pNv->Chipset & 0x0ff0) == 0x0110) {
1556            state->dither = pNv->PRAMDAC[0x0528/4];
1557         } else
1558         if(pNv->twoHeads) {
1559             state->dither = pNv->PRAMDAC[0x083C/4];
1560         }
1561
1562         if(pNv->FlatPanel) {
1563            VGA_WR08(pNv->PCIO, 0x03D4, 0x53);
1564            state->timingH = VGA_RD08(pNv->PCIO, 0x03D5);
1565            VGA_WR08(pNv->PCIO, 0x03D4, 0x54);
1566            state->timingV = VGA_RD08(pNv->PCIO, 0x03D5);
1567         }
1568     }
1569
1570     if(pNv->FlatPanel) {
1571        state->crtcSync = pNv->PRAMDAC[0x0828/4];
1572     }
1573 }
1574
1575 void NVSetStartAddress (
1576     NVPtr   pNv,
1577     CARD32 start
1578 )
1579 {
1580     pNv->PCRTC[0x800/4] = start;
1581 }
1582
1583