2 * Copyright 2006 Dave Airlie
3 * Copyright 2007 Maarten Maathuis
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
26 * decleration is at the bottom of this file as it is rather ugly
41 #include "mipointer.h"
42 #include "windowstr.h"
44 #include <X11/extensions/render.h>
47 #include "nv_include.h"
51 #define CRTC_INDEX 0x3d4
52 #define CRTC_DATA 0x3d5
53 #define CRTC_IN_STAT_1 0x3da
55 #define WHITE_VALUE 0x3F
56 #define BLACK_VALUE 0x00
57 #define OVERSCAN_VALUE 0x01
59 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
60 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override);
61 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
62 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
63 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
64 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
65 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
66 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
68 uint32_t NVReadCRTC(NVPtr pNv, uint8_t head, uint32_t reg)
71 reg += NV_PCRTC0_SIZE;
72 DDXMMIOH("NVReadCRTC: head %d reg %08x val %08x\n", head, reg, (uint32_t)MMIO_IN32(pNv->REGS, reg));
73 return MMIO_IN32(pNv->REGS, reg);
76 void NVWriteCRTC(NVPtr pNv, uint8_t head, uint32_t reg, uint32_t val)
79 reg += NV_PCRTC0_SIZE;
80 DDXMMIOH("NVWriteCRTC: head %d reg %08x val %08x\n", head, reg, val);
81 MMIO_OUT32(pNv->REGS, reg, val);
84 uint32_t NVCrtcReadCRTC(xf86CrtcPtr crtc, uint32_t reg)
86 ScrnInfoPtr pScrn = crtc->scrn;
87 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
88 NVPtr pNv = NVPTR(pScrn);
90 return NVReadCRTC(pNv, nv_crtc->head, reg);
93 void NVCrtcWriteCRTC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
95 ScrnInfoPtr pScrn = crtc->scrn;
96 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
97 NVPtr pNv = NVPTR(pScrn);
99 NVWriteCRTC(pNv, nv_crtc->head, reg, val);
102 uint32_t NVReadRAMDAC(NVPtr pNv, uint8_t head, uint32_t reg)
105 reg += NV_PRAMDAC0_SIZE;
106 DDXMMIOH("NVReadRamdac: head %d reg %08x val %08x\n", head, reg, (uint32_t)MMIO_IN32(pNv->REGS, reg));
107 return MMIO_IN32(pNv->REGS, reg);
110 void NVWriteRAMDAC(NVPtr pNv, uint8_t head, uint32_t reg, uint32_t val)
113 reg += NV_PRAMDAC0_SIZE;
114 DDXMMIOH("NVWriteRamdac: head %d reg %08x val %08x\n", head, reg, val);
115 MMIO_OUT32(pNv->REGS, reg, val);
118 uint32_t NVCrtcReadRAMDAC(xf86CrtcPtr crtc, uint32_t reg)
120 ScrnInfoPtr pScrn = crtc->scrn;
121 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
122 NVPtr pNv = NVPTR(pScrn);
124 return NVReadRAMDAC(pNv, nv_crtc->head, reg);
127 void NVCrtcWriteRAMDAC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
129 ScrnInfoPtr pScrn = crtc->scrn;
130 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
131 NVPtr pNv = NVPTR(pScrn);
133 NVWriteRAMDAC(pNv, nv_crtc->head, reg, val);
136 static uint8_t NVReadPVIO(xf86CrtcPtr crtc, uint32_t address)
138 ScrnInfoPtr pScrn = crtc->scrn;
139 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
140 NVPtr pNv = NVPTR(pScrn);
142 /* Only NV4x have two pvio ranges */
143 if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
144 DDXMMIOH("NVReadPVIO: head %d reg %08x val %02x\n", 1, address + NV_PVIO_OFFSET + NV_PVIO_SIZE, NV_RD08(pNv->PVIO1, address));
145 return NV_RD08(pNv->PVIO1, address);
147 DDXMMIOH("NVReadPVIO: head %d reg %08x val %02x\n", 0, address + NV_PVIO_OFFSET, NV_RD08(pNv->PVIO0, address));
148 return NV_RD08(pNv->PVIO0, address);
152 static void NVWritePVIO(xf86CrtcPtr crtc, uint32_t address, uint8_t value)
154 ScrnInfoPtr pScrn = crtc->scrn;
155 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
156 NVPtr pNv = NVPTR(pScrn);
158 DDXMMIOH("NVWritePVIO: head %d reg %08x val %02x\n", nv_crtc->head, address + NV_PVIO_OFFSET + (nv_crtc->head ? NV_PVIO_SIZE : 0), value);
159 /* Only NV4x have two pvio ranges */
160 if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
161 NV_WR08(pNv->PVIO1, address, value);
163 NV_WR08(pNv->PVIO0, address, value);
167 void NVWriteVGA(NVPtr pNv, int head, uint8_t index, uint8_t value)
169 volatile uint8_t *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
171 DDXMMIOH("NVWriteVGA: head %d index 0x%02x data 0x%02x\n", head, index, value);
172 NV_WR08(pCRTCReg, CRTC_INDEX, index);
173 NV_WR08(pCRTCReg, CRTC_DATA, value);
176 uint8_t NVReadVGA(NVPtr pNv, int head, uint8_t index)
178 volatile uint8_t *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
180 NV_WR08(pCRTCReg, CRTC_INDEX, index);
181 DDXMMIOH("NVReadVGA: head %d index 0x%02x data 0x%02x\n", head, index, NV_RD08(pCRTCReg, CRTC_DATA));
182 return NV_RD08(pCRTCReg, CRTC_DATA);
185 /* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
186 * I suspect they in fact do nothing, but are merely a way to carry useful
187 * per-head variables around
191 * 0x00 index to the appropriate dcb entry (or 7f for inactive)
192 * 0x02 dcb entry's "or" value (or 00 for inactive)
193 * 0x03 bit0 set for dual link (LVDS, possibly elsewhere too)
194 * 0x08 or 0x09 pxclk in MHz
195 * 0x0f laptop panel info - low nibble for PEXTDEV_BOOT_0 strap
196 * high nibble for xlat strap value
199 void NVWriteVGACR5758(NVPtr pNv, int head, uint8_t index, uint8_t value)
201 NVWriteVGA(pNv, head, 0x57, index);
202 NVWriteVGA(pNv, head, 0x58, value);
205 uint8_t NVReadVGACR5758(NVPtr pNv, int head, uint8_t index)
207 NVWriteVGA(pNv, head, 0x57, index);
208 return NVReadVGA(pNv, head, 0x58);
211 void NVWriteVgaCrtc(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
213 ScrnInfoPtr pScrn = crtc->scrn;
214 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
215 NVPtr pNv = NVPTR(pScrn);
217 NVWriteVGA(pNv, nv_crtc->head, index, value);
220 uint8_t NVReadVgaCrtc(xf86CrtcPtr crtc, uint8_t index)
222 ScrnInfoPtr pScrn = crtc->scrn;
223 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
224 NVPtr pNv = NVPTR(pScrn);
226 return NVReadVGA(pNv, nv_crtc->head, index);
229 static void NVWriteVgaSeq(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
231 NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
232 NVWritePVIO(crtc, VGA_SEQ_DATA, value);
235 static uint8_t NVReadVgaSeq(xf86CrtcPtr crtc, uint8_t index)
237 NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
238 return NVReadPVIO(crtc, VGA_SEQ_DATA);
241 static void NVWriteVgaGr(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
243 NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
244 NVWritePVIO(crtc, VGA_GRAPH_DATA, value);
247 static uint8_t NVReadVgaGr(xf86CrtcPtr crtc, uint8_t index)
249 NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
250 return NVReadPVIO(crtc, VGA_GRAPH_DATA);
254 static void NVWriteVgaAttr(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
256 ScrnInfoPtr pScrn = crtc->scrn;
257 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
258 NVPtr pNv = NVPTR(pScrn);
259 volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
261 DDXMMIOH("NVWriteVgaAttr: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, CRTC_IN_STAT_1, NV_RD08(pCRTCReg, CRTC_IN_STAT_1));
262 NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
263 if (nv_crtc->paletteEnabled)
268 DDXMMIOH("NVWriteVgaAttr: head %d index 0x%02x data 0x%02x\n", nv_crtc->head, index, value);
269 NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
270 NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
273 static uint8_t NVReadVgaAttr(xf86CrtcPtr crtc, uint8_t index)
275 ScrnInfoPtr pScrn = crtc->scrn;
276 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
277 NVPtr pNv = NVPTR(pScrn);
278 volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
280 DDXMMIOH("NVReadVgaAttr: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, CRTC_IN_STAT_1, NV_RD08(pCRTCReg, CRTC_IN_STAT_1));
281 NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
282 if (nv_crtc->paletteEnabled)
287 NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
288 DDXMMIOH("NVReadVgaAttr: head %d index 0x%02x data 0x%02x\n", nv_crtc->head, index, NV_RD08(pCRTCReg, VGA_ATTR_DATA_R));
289 return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
292 static void NVCrtcSetOwner(xf86CrtcPtr crtc)
294 NVPtr pNv = NVPTR(crtc->scrn);
295 uint8_t newowner = ((NVCrtcPrivatePtr)crtc->driver_private)->head * 0x3;
297 /* CRTCX_OWNER is always changed on CRTC0 */
298 NVWriteVGA(pNv, 0, NV_VGA_CRTCX_OWNER, newowner);
300 ErrorF("Setting owner: 0x%X\n", newowner);
304 NVEnablePalette(xf86CrtcPtr crtc)
306 ScrnInfoPtr pScrn = crtc->scrn;
307 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
308 NVPtr pNv = NVPTR(pScrn);
309 volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
311 DDXMMIOH("NVEnablePalette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, CRTC_IN_STAT_1, NV_RD08(pCRTCReg, CRTC_IN_STAT_1));
312 NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
313 DDXMMIOH("NVEnablePalette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_ATTR_INDEX, 0);
314 NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
315 nv_crtc->paletteEnabled = TRUE;
319 NVDisablePalette(xf86CrtcPtr crtc)
321 ScrnInfoPtr pScrn = crtc->scrn;
322 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
323 NVPtr pNv = NVPTR(pScrn);
324 volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
326 DDXMMIOH("NVDisablePalette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, NV_PCIO0_OFFSET + (nv_crtc->head ? NV_PCIO0_SIZE : 0) + CRTC_IN_STAT_1, NV_RD08(pCRTCReg, CRTC_IN_STAT_1));
327 NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
328 DDXMMIOH("NVDisablePalette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, NV_PCIO0_OFFSET + (nv_crtc->head ? NV_PCIO0_SIZE : 0) + VGA_ATTR_INDEX, 0x20);
329 NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
330 nv_crtc->paletteEnabled = FALSE;
333 /* perform a sequencer reset */
334 static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
337 NVWriteVgaSeq(crtc, 0x00, 0x1);
339 NVWriteVgaSeq(crtc, 0x00, 0x3);
342 static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
347 tmp = NVReadVgaSeq(crtc, 0x1);
348 NVVgaSeqReset(crtc, TRUE);
349 NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
351 NVEnablePalette(crtc);
354 * Reenable sequencer, then turn on screen.
356 tmp = NVReadVgaSeq(crtc, 0x1);
357 NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20); /* reenable display */
358 NVVgaSeqReset(crtc, FALSE);
360 NVDisablePalette(crtc);
364 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool Lock)
366 NVPtr pNv = NVPTR(crtc->scrn);
370 NVCrtcSetOwner(crtc);
372 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57);
373 cr11 = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE);
374 if (Lock) cr11 |= 0x80;
376 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE, cr11);
380 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
382 ScrnInfoPtr pScrn = crtc->scrn;
383 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
385 for (i = 0; i < xf86_config->num_output; i++) {
386 xf86OutputPtr output = xf86_config->output[i];
388 if (output->crtc == crtc) {
397 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
399 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
402 for (i = 0; i < xf86_config->num_crtc; i++) {
403 xf86CrtcPtr crtc = xf86_config->crtc[i];
404 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
405 if (nv_crtc->head == index)
412 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
413 /* They are only valid for NV4x, appearantly reordered for NV5x */
414 /* gpu pll: 0x4000 + 0x4004
415 * unknown pll: 0x4008 + 0x400c
416 * vpll1: 0x4010 + 0x4014
417 * vpll2: 0x4018 + 0x401c
418 * unknown pll: 0x4020 + 0x4024
419 * unknown pll: 0x4038 + 0x403c
420 * Some of the unknown's are probably memory pll's.
421 * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
422 * 1 and 2 refer to the registers of each pair. There is only one post divider.
423 * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
424 * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
425 * bit8: A switch that turns of the second divider and multiplier off.
426 * bit12: Also a switch, i haven't seen it yet.
427 * bit16-19: p-divider
428 * but 28-31: Something related to the mode that is used (see bit8).
429 * 2) bit0-7: m-divider (a)
430 * bit8-15: n-multiplier (a)
431 * bit16-23: m-divider (b)
432 * bit24-31: n-multiplier (b)
435 /* Modifying the gpu pll for example requires:
436 * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
437 * This is not needed for the vpll's which have their own bits.
440 static void nv40_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
442 state->vpll1_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL);
443 state->vpll1_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B);
444 state->vpll2_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2);
445 state->vpll2_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B);
446 state->pllsel = NVReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT);
447 state->sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
448 state->reg580 = NVReadRAMDAC(pNv, 0, NV_RAMDAC_580);
449 state->reg594 = NVReadRAMDAC(pNv, 0, NV_RAMDAC_594);
452 static void nv40_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
454 ScrnInfoPtr pScrn = crtc->scrn;
455 NVPtr pNv = NVPTR(pScrn);
456 uint32_t fp_debug_0[2];
458 fp_debug_0[0] = NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
459 fp_debug_0[1] = NVReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
461 /* The TMDS_PLL switch is on the actual ramdac */
462 if (state->crosswired) {
465 ErrorF("Crosswired pll state load\n");
471 if (state->vpll2_b && state->vpll_changed[1]) {
472 NVWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0,
473 fp_debug_0[index[1]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
475 /* Wait for the situation to stabilise */
478 uint32_t reg_c040 = pNv->misc_info.reg_c040;
479 /* for vpll2 change bits 18 and 19 are disabled */
480 reg_c040 &= ~(0x3 << 18);
481 nvWriteMC(pNv, 0xc040, reg_c040);
483 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
484 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
486 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2, state->vpll2_a);
487 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B, state->vpll2_b);
489 ErrorF("writing pllsel %08X\n", state->pllsel);
490 /* Don't turn vpll1 off. */
491 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
493 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_580, state->reg580);
494 ErrorF("writing reg580 %08X\n", state->reg580);
496 /* We need to wait a while */
498 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
500 NVWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[1]]);
502 /* Wait for the situation to stabilise */
506 if (state->vpll1_b && state->vpll_changed[0]) {
507 NVWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0,
508 fp_debug_0[index[0]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
510 /* Wait for the situation to stabilise */
513 uint32_t reg_c040 = pNv->misc_info.reg_c040;
514 /* for vpll2 change bits 16 and 17 are disabled */
515 reg_c040 &= ~(0x3 << 16);
516 nvWriteMC(pNv, 0xc040, reg_c040);
518 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
519 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
521 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL, state->vpll1_a);
522 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B, state->vpll1_b);
524 ErrorF("writing pllsel %08X\n", state->pllsel);
525 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
527 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_580, state->reg580);
528 ErrorF("writing reg580 %08X\n", state->reg580);
530 /* We need to wait a while */
532 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
534 NVWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[0]]);
536 /* Wait for the situation to stabilise */
540 ErrorF("writing sel_clk %08X\n", state->sel_clk);
541 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, state->sel_clk);
543 ErrorF("writing reg594 %08X\n", state->reg594);
544 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_594, state->reg594);
546 /* All clocks have been set at this point. */
547 state->vpll_changed[0] = FALSE;
548 state->vpll_changed[1] = FALSE;
551 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
553 state->vpll1_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL);
555 state->vpll2_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2);
557 if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
558 state->vpll1_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B);
559 state->vpll2_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B);
561 state->pllsel = NVReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT);
562 state->sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
566 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
568 /* This sequence is important, the NV28 is very sensitive in this area. */
569 /* Keep pllsel last and sel_clk first. */
570 ErrorF("writing sel_clk %08X\n", state->sel_clk);
571 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, state->sel_clk);
573 if (state->vpll2_a && state->vpll_changed[1]) {
575 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
576 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2, state->vpll2_a);
578 if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
579 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
580 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B, state->vpll2_b);
584 if (state->vpll1_a && state->vpll_changed[0]) {
585 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
586 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL, state->vpll1_a);
587 if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
588 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
589 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B, state->vpll1_b);
593 ErrorF("writing pllsel %08X\n", state->pllsel);
594 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
596 /* All clocks have been set at this point. */
597 state->vpll_changed[0] = FALSE;
598 state->vpll_changed[1] = FALSE;
601 static void nv_crtc_mode_set_sel_clk(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
603 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
604 NVPtr pNv = NVPTR(crtc->scrn);
605 xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
606 NVOutputPrivatePtr nv_output;
609 /* Don't change SEL_CLK on NV0x/NV1x/NV2x cards */
610 if (pNv->Architecture < NV_ARCH_30) {
611 state->sel_clk = pNv->misc_info.sel_clk;
615 /* SEL_CLK is only used on the primary ramdac */
616 /* This seems to be needed to select the proper clocks, otherwise bad things happen */
618 state->sel_clk = pNv->misc_info.sel_clk & ~(0xf << 16);
622 nv_output = output->driver_private;
624 /* Only let digital outputs mess further with SEL_CLK, otherwise strange output routings may mess it up. */
625 if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS) {
626 Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
628 state->sel_clk &= ~(0xf << 16);
629 /* Even with two dvi, this should not conflict. */
631 state->sel_clk |= (0x1 << 16);
633 state->sel_clk |= (0x4 << 16);
636 * bit 0 NVClk spread spectrum on/off
637 * bit 2 MemClk spread spectrum on/off
638 * bit 4 PixClk1 spread spectrum on/off
639 * bit 6 PixClk2 spread spectrum on/off
641 * nv40 (observations from bios behaviour and mmio traces):
642 * bit 4 seems to get set when output is on head A - likely related to PixClk1
643 * bit 6 seems to get set when output is on head B - likely related to PixClk2
644 * bits 5&7 set as for bits 4&6, but do not appear on cards using 4&6
646 * bits 8&10 seen on dual dvi outputs; possibly means "bits 4&6, dual dvi"
648 * Note that the circumstances for setting the bits at all is unclear
650 if (pNv->Architecture == NV_ARCH_40) {
651 for (i = 1; i <= 2; i++) {
652 uint32_t var = (state->sel_clk >> 4*i) & 0xf;
653 int shift = 0; /* assume (var & 0x5) by default */
660 state->sel_clk &= ~(0xf << 4*i);
662 state->sel_clk |= (0x4 << (4*i + shift));
664 state->sel_clk |= (0x1 << (4*i + shift));
671 * Calculate extended mode parameters (SVGA) and save in a
672 * mode state structure.
673 * State is not specific to a single crtc, but shared.
675 void nv_crtc_calc_state_ext(
679 int DisplayWidth, /* Does this change after setting the mode? */
686 ScrnInfoPtr pScrn = crtc->scrn;
687 uint32_t pixelDepth, VClk = 0;
688 uint32_t CursorStart;
689 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
690 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
692 NVPtr pNv = NVPTR(pScrn);
693 RIVA_HW_STATE *state;
694 int num_crtc_enabled, i;
695 uint32_t old_clock_a = 0, old_clock_b = 0;
696 struct pll_lims pll_lim;
697 int NM1 = 0xbeef, NM2 = 0xdead, log2P = 0;
698 uint32_t g70_pll_special_bits = 0;
699 Bool nv4x_single_stage_pll_mode = FALSE;
701 state = &pNv->ModeReg;
703 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
705 xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
706 NVOutputPrivatePtr nv_output = NULL;
708 nv_output = output->driver_private;
710 /* Store old clock. */
711 if (nv_crtc->head == 1) {
712 old_clock_a = state->vpll2_a;
713 old_clock_b = state->vpll2_b;
715 old_clock_a = state->vpll1_a;
716 old_clock_b = state->vpll1_b;
720 * Extended RIVA registers.
722 /* This is pitch related, not mode related. */
723 pixelDepth = (bpp + 1)/8;
725 if (nv_crtc->head == 0) {
726 if (!get_pll_limits(pScrn, VPLL1, &pll_lim))
729 if (!get_pll_limits(pScrn, VPLL2, &pll_lim))
732 if (pNv->twoStagePLL) {
733 if (dotClock < pll_lim.vco1.maxfreq && pNv->NVArch > 0x40) { /* use a single VCO */
734 nv4x_single_stage_pll_mode = TRUE;
735 /* Turn the second set of divider and multiplier off */
736 /* Bogus data, the same nvidia uses */
738 VClk = getMNP_single(pScrn, &pll_lim, dotClock, &NM1, &log2P);
740 VClk = getMNP_double(pScrn, &pll_lim, dotClock, &NM1, &NM2, &log2P);
742 VClk = getMNP_single(pScrn, &pll_lim, dotClock, &NM1, &log2P);
744 /* Are these all the (relevant) G70 cards? */
745 if (pNv->NVArch == 0x4B || pNv->NVArch == 0x46 || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
746 /* This is a big guess, but should be reasonable until we can narrow it down. */
747 /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
748 if (nv4x_single_stage_pll_mode)
749 g70_pll_special_bits = 0x1;
751 g70_pll_special_bits = 0x3;
754 if (pNv->NVArch == 0x30)
755 /* See nvregisters.xml for details. */
756 state->pll = log2P << 16 | NM1 | (NM2 & 7) << 4 | ((NM2 >> 8) & 7) << 19 | ((NM2 >> 11) & 3) << 24 | NV30_RAMDAC_ENABLE_VCO2;
758 state->pll = g70_pll_special_bits << 30 | log2P << 16 | NM1;
759 state->pllB = NV31_RAMDAC_ENABLE_VCO2 | NM2;
761 /* Does register 0x580 already have a value? */
763 state->reg580 = pNv->misc_info.ramdac_0_reg_580;
764 if (nv4x_single_stage_pll_mode) {
765 if (nv_crtc->head == 0)
766 state->reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
768 state->reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
770 if (nv_crtc->head == 0)
771 state->reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
773 state->reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
776 if (!pNv->twoStagePLL || nv4x_single_stage_pll_mode)
777 ErrorF("vpll: n %d m %d log2p %d\n", NM1 >> 8, NM1 & 0xff, log2P);
779 ErrorF("vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", NM1 >> 8, NM2 >> 8, NM1 & 0xff, NM2 & 0xff, log2P);
781 if (nv_crtc->head == 1) {
782 state->vpll2_a = state->pll;
783 state->vpll2_b = state->pllB;
785 state->vpll1_a = state->pll;
786 state->vpll1_b = state->pllB;
789 /* always reset vpll, just to be sure. */
790 state->vpll_changed[nv_crtc->head] = TRUE;
792 switch (pNv->Architecture) {
794 nv4UpdateArbitrationSettings(VClk,
796 &(state->arbitration0),
797 &(state->arbitration1),
799 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
800 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
801 if (flags & V_DBLSCAN)
802 regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
803 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
804 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
805 state->config = 0x00001114;
806 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
812 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
813 ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
814 state->arbitration0 = 128;
815 state->arbitration1 = 0x0480;
816 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
817 ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
818 nForceUpdateArbitrationSettings(VClk,
820 &(state->arbitration0),
821 &(state->arbitration1),
823 } else if (pNv->Architecture < NV_ARCH_30) {
824 nv10UpdateArbitrationSettings(VClk,
826 &(state->arbitration0),
827 &(state->arbitration1),
830 nv30UpdateArbitrationSettings(pNv,
831 &(state->arbitration0),
832 &(state->arbitration1));
835 if (nv_crtc->head == 1) {
836 CursorStart = pNv->Cursor2->offset;
838 CursorStart = pNv->Cursor->offset;
841 if (!NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
842 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
843 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
844 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
846 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x0;
847 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0x0;
848 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x0;
851 if (flags & V_DBLSCAN)
852 regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
854 state->config = nvReadFB(pNv, NV_PFB_CFG0);
855 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
859 if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
860 /* This is a bit of a guess. */
861 regp->CRTC[NV_VGA_CRTCX_REPAINT1] |= 0xB8;
864 /* okay do we have 2 CRTCs running ? */
865 num_crtc_enabled = 0;
866 for (i = 0; i < xf86_config->num_crtc; i++) {
867 if (xf86_config->crtc[i]->enabled) {
872 ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
874 /* Are we crosswired? */
875 if (output && nv_crtc->head != nv_output->preferred_output) {
876 state->crosswired = TRUE;
878 state->crosswired = FALSE;
880 /* The NV40 seems to have more similarities to NV3x than other cards. */
881 if (pNv->NVArch < 0x41) {
882 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL;
883 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL;
886 if (nv_crtc->head == 1) {
887 if (!nv4x_single_stage_pll_mode) {
888 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
890 state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
892 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
894 if (!nv4x_single_stage_pll_mode) {
895 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
897 state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
899 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
902 /* The blob uses this always, so let's do the same */
903 if (pNv->Architecture == NV_ARCH_40) {
904 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
907 /* The primary output resource doesn't seem to care */
908 if (output && pNv->Architecture == NV_ARCH_40 && nv_output->output_resource == 1) { /* This is the "output" */
909 /* non-zero values are for analog, don't know about tv-out and the likes */
910 if (output && nv_output->type != OUTPUT_ANALOG) {
913 /* Are we a flexible output? */
914 if (ffs(pNv->dcb_table.entry[nv_output->dcb_entry].or) & OUTPUT_0) {
916 pNv->restricted_mode = FALSE;
919 pNv->restricted_mode = TRUE;
922 /* More values exist, but they seem related to the 3rd dac (tv-out?) somehow */
923 /* bit 16-19 are bits that are set on some G70 cards */
924 /* Those bits are also set to the 3rd OUTPUT register */
925 if (nv_crtc->head == 1) {
926 state->reg594 |= 0x100;
931 regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
932 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
933 if (pNv->Architecture >= NV_ARCH_30) {
934 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
937 if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
938 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = ((CrtcHDisplay/16) & 0x700) >> 3;
939 } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
940 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((CrtcHDisplay*bpp)/64) & 0x700) >> 3;
941 } else { /* framebuffer can be larger than crtc scanout area. */
942 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
944 regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
948 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
950 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
952 ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->head, mode);
954 if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */
957 nv_crtc->last_dpms = mode;
959 ScrnInfoPtr pScrn = crtc->scrn;
960 NVPtr pNv = NVPTR(pScrn);
961 unsigned char seq1 = 0, crtc17 = 0;
962 unsigned char crtc1A;
965 NVCrtcSetOwner(crtc);
967 crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
969 case DPMSModeStandby:
970 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
975 case DPMSModeSuspend:
976 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
982 /* Screen: Off; HSync: Off, VSync: Off */
989 /* Screen: On; HSync: On, VSync: On */
995 NVVgaSeqReset(crtc, TRUE);
996 /* Each head has it's own sequencer, so we can turn it off when we want */
997 seq1 |= (NVReadVgaSeq(crtc, 0x01) & ~0x20);
998 NVWriteVgaSeq(crtc, 0x1, seq1);
999 crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
1001 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
1002 NVVgaSeqReset(crtc, FALSE);
1004 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
1006 /* I hope this is the right place */
1007 if (crtc->enabled && mode == DPMSModeOn) {
1008 pNv->crtc_active[nv_crtc->head] = TRUE;
1010 pNv->crtc_active[nv_crtc->head] = FALSE;
1015 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
1016 DisplayModePtr adjusted_mode)
1018 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1019 ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->head);
1025 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1027 ScrnInfoPtr pScrn = crtc->scrn;
1028 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1030 NVPtr pNv = NVPTR(pScrn);
1031 NVFBLayout *pLayout = &pNv->CurrentLayout;
1032 int depth = pScrn->depth;
1034 /* This is pitch/memory size related. */
1035 if (NVMatchModePrivate(mode, NV_MODE_CONSOLE))
1036 depth = pNv->console_mode[nv_crtc->head].bpp;
1038 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1040 /* Calculate our timings */
1041 int horizDisplay = (mode->CrtcHDisplay >> 3) - 1;
1042 int horizStart = (mode->CrtcHSyncStart >> 3) - 1;
1043 int horizEnd = (mode->CrtcHSyncEnd >> 3) - 1;
1044 int horizTotal = (mode->CrtcHTotal >> 3) - 5;
1045 int horizBlankStart = (mode->CrtcHDisplay >> 3) - 1;
1046 int horizBlankEnd = (mode->CrtcHTotal >> 3) - 1;
1047 int vertDisplay = mode->CrtcVDisplay - 1;
1048 int vertStart = mode->CrtcVSyncStart - 1;
1049 int vertEnd = mode->CrtcVSyncEnd - 1;
1050 int vertTotal = mode->CrtcVTotal - 2;
1051 int vertBlankStart = mode->CrtcVDisplay - 1;
1052 int vertBlankEnd = mode->CrtcVTotal - 1;
1054 xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1055 NVOutputPrivatePtr nv_output = NULL;
1057 nv_output = output->driver_private;
1059 ErrorF("Mode clock: %d\n", mode->Clock);
1060 ErrorF("Adjusted mode clock: %d\n", adjusted_mode->Clock);
1062 /* Reverted to what nv did, because that works for all resolutions on flatpanels */
1063 if (output && (nv_output->type == OUTPUT_LVDS || nv_output->type == OUTPUT_TMDS)) {
1064 vertStart = vertTotal - 3;
1065 vertEnd = vertTotal - 2;
1066 vertBlankStart = vertStart;
1067 horizStart = horizTotal - 5;
1068 horizEnd = horizTotal - 2;
1069 horizBlankEnd = horizTotal + 4;
1070 if (pNv->overlayAdaptor && pNv->Architecture >= NV_ARCH_10) {
1071 /* This reportedly works around Xv some overlay bandwidth problems*/
1076 if (mode->Flags & V_INTERLACE)
1079 ErrorF("horizDisplay: 0x%X \n", horizDisplay);
1080 ErrorF("horizStart: 0x%X \n", horizStart);
1081 ErrorF("horizEnd: 0x%X \n", horizEnd);
1082 ErrorF("horizTotal: 0x%X \n", horizTotal);
1083 ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
1084 ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
1085 ErrorF("vertDisplay: 0x%X \n", vertDisplay);
1086 ErrorF("vertStart: 0x%X \n", vertStart);
1087 ErrorF("vertEnd: 0x%X \n", vertEnd);
1088 ErrorF("vertTotal: 0x%X \n", vertTotal);
1089 ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
1090 ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
1093 * compute correct Hsync & Vsync polarity
1095 if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
1096 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
1098 regp->MiscOutReg = 0x23;
1099 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
1100 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
1102 int VDisplay = mode->VDisplay;
1103 if (mode->Flags & V_DBLSCAN)
1105 if (mode->VScan > 1)
1106 VDisplay *= mode->VScan;
1107 if (VDisplay < 400) {
1108 regp->MiscOutReg = 0xA3; /* +hsync -vsync */
1109 } else if (VDisplay < 480) {
1110 regp->MiscOutReg = 0x63; /* -hsync +vsync */
1111 } else if (VDisplay < 768) {
1112 regp->MiscOutReg = 0xE3; /* -hsync -vsync */
1114 regp->MiscOutReg = 0x23; /* +hsync +vsync */
1118 regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
1123 regp->Sequencer[0] = 0x00;
1124 /* 0x20 disables the sequencer */
1125 if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1126 if (mode->HDisplay == 720) {
1127 regp->Sequencer[1] = 0x21; /* enable 9/8 mode */
1129 regp->Sequencer[1] = 0x20;
1132 if (mode->Flags & V_CLKDIV2) {
1133 regp->Sequencer[1] = 0x29;
1135 regp->Sequencer[1] = 0x21;
1138 if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1139 regp->Sequencer[2] = 0x03; /* select 2 out of 4 planes */
1141 regp->Sequencer[2] = 0x0F;
1143 regp->Sequencer[3] = 0x00; /* Font select */
1144 if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1145 regp->Sequencer[4] = 0x02;
1147 regp->Sequencer[4] = 0x0E; /* Misc */
1153 regp->CRTC[NV_VGA_CRTCX_HTOTAL] = Set8Bits(horizTotal);
1154 regp->CRTC[NV_VGA_CRTCX_HDISPE] = Set8Bits(horizDisplay);
1155 regp->CRTC[NV_VGA_CRTCX_HBLANKS] = Set8Bits(horizBlankStart);
1156 regp->CRTC[NV_VGA_CRTCX_HBLANKE] = SetBitField(horizBlankEnd,4:0,4:0)
1158 regp->CRTC[NV_VGA_CRTCX_HSYNCS] = Set8Bits(horizStart);
1159 regp->CRTC[NV_VGA_CRTCX_HSYNCE] = SetBitField(horizBlankEnd,5:5,7:7)
1160 | SetBitField(horizEnd,4:0,4:0);
1161 regp->CRTC[NV_VGA_CRTCX_VTOTAL] = SetBitField(vertTotal,7:0,7:0);
1162 regp->CRTC[NV_VGA_CRTCX_OVERFLOW] = SetBitField(vertTotal,8:8,0:0)
1163 | SetBitField(vertDisplay,8:8,1:1)
1164 | SetBitField(vertStart,8:8,2:2)
1165 | SetBitField(vertBlankStart,8:8,3:3)
1167 | SetBitField(vertTotal,9:9,5:5)
1168 | SetBitField(vertDisplay,9:9,6:6)
1169 | SetBitField(vertStart,9:9,7:7);
1170 regp->CRTC[NV_VGA_CRTCX_PRROWSCN] = 0x00;
1171 regp->CRTC[NV_VGA_CRTCX_MAXSCLIN] = SetBitField(vertBlankStart,9:9,5:5)
1173 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00)
1174 | (NVMatchModePrivate(mode, NV_MODE_VGA) ? 0xF : 0x00); /* 8x15 chars */
1175 if (NVMatchModePrivate(mode, NV_MODE_VGA)) { /* Were do these cursor offsets come from? */
1176 regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0xD; /* start scanline */
1177 regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0xE; /* end scanline */
1179 regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0x00;
1180 regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0x00;
1182 regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00;
1183 regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
1184 regp->CRTC[0xe] = 0x00;
1185 regp->CRTC[0xf] = 0x00;
1186 regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
1187 /* What is the meaning of bit5, it is empty in the vga spec. */
1188 regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) |
1189 (NVMatchModePrivate(mode, NV_MODE_VGA) ? 0 : SetBit(5));
1190 regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
1191 if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1192 regp->CRTC[NV_VGA_CRTCX_PITCHL] = (mode->CrtcHDisplay/16);
1193 } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1194 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((mode->CrtcHDisplay*depth)/64);
1195 } else { /* framebuffer can be larger than crtc scanout area. */
1196 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
1198 if (depth == 4) { /* How can these values be calculated? */
1199 regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x1F;
1201 regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x00;
1203 regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
1204 regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
1205 /* 0x80 enables the sequencer, we don't want that */
1206 if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1207 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xA3 & ~0x80;
1208 } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1209 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xE3 & ~0x80;
1211 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80;
1213 regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
1216 * Some extended CRTC registers (they are not saved with the rest of the vga regs).
1219 regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
1220 | SetBitField(vertBlankStart,10:10,3:3)
1221 | SetBitField(vertStart,10:10,2:2)
1222 | SetBitField(vertDisplay,10:10,1:1)
1223 | SetBitField(vertTotal,10:10,0:0);
1225 regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
1226 | SetBitField(horizDisplay,8:8,1:1)
1227 | SetBitField(horizBlankStart,8:8,2:2)
1228 | SetBitField(horizStart,8:8,3:3);
1230 regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
1231 | SetBitField(vertDisplay,11:11,2:2)
1232 | SetBitField(vertStart,11:11,4:4)
1233 | SetBitField(vertBlankStart,11:11,6:6);
1235 if(mode->Flags & V_INTERLACE) {
1236 horizTotal = (horizTotal >> 1) & ~1;
1237 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
1238 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
1240 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff; /* interlace off */
1244 * Graphics Display Controller
1246 regp->Graphics[0] = 0x00;
1247 regp->Graphics[1] = 0x00;
1248 regp->Graphics[2] = 0x00;
1249 regp->Graphics[3] = 0x00;
1250 regp->Graphics[4] = 0x00;
1251 if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1252 regp->Graphics[5] = 0x10;
1253 regp->Graphics[6] = 0x0E; /* map 32k mem */
1254 regp->Graphics[7] = 0x00;
1256 regp->Graphics[5] = 0x40; /* 256 color mode */
1257 regp->Graphics[6] = 0x05; /* map 64k mem + graphic mode */
1258 regp->Graphics[7] = 0x0F;
1260 regp->Graphics[8] = 0xFF;
1262 regp->Attribute[0] = 0x00; /* standard colormap translation */
1263 regp->Attribute[1] = 0x01;
1264 regp->Attribute[2] = 0x02;
1265 regp->Attribute[3] = 0x03;
1266 regp->Attribute[4] = 0x04;
1267 regp->Attribute[5] = 0x05;
1268 regp->Attribute[6] = 0x06;
1269 regp->Attribute[7] = 0x07;
1270 regp->Attribute[8] = 0x08;
1271 regp->Attribute[9] = 0x09;
1272 regp->Attribute[10] = 0x0A;
1273 regp->Attribute[11] = 0x0B;
1274 regp->Attribute[12] = 0x0C;
1275 regp->Attribute[13] = 0x0D;
1276 regp->Attribute[14] = 0x0E;
1277 regp->Attribute[15] = 0x0F;
1278 if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1279 regp->Attribute[16] = 0x0C; /* Line Graphics Enable + Blink enable */
1281 regp->Attribute[16] = 0x01; /* Enable graphic mode */
1284 regp->Attribute[17] = 0x00;
1285 regp->Attribute[18] = 0x0F; /* enable all color planes */
1286 if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1287 regp->Attribute[19] = 0x08; /* shift bits by 8 */
1289 regp->Attribute[19] = 0x00;
1291 regp->Attribute[20] = 0x00;
1295 * Sets up registers for the given mode/adjusted_mode pair.
1297 * The clocks, CRTCs and outputs attached to this CRTC must be off.
1299 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1300 * be easily turned on/off after this.
1303 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1305 ScrnInfoPtr pScrn = crtc->scrn;
1306 NVPtr pNv = NVPTR(pScrn);
1307 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1308 NVFBLayout *pLayout = &pNv->CurrentLayout;
1309 NVCrtcRegPtr regp, savep;
1312 Bool is_lvds = FALSE;
1314 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1315 savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1317 xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1318 NVOutputPrivatePtr nv_output = NULL;
1320 nv_output = output->driver_private;
1322 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1325 if (nv_output->type == OUTPUT_LVDS)
1329 /* Registers not directly related to the (s)vga mode */
1331 /* bit2 = 0 -> fine pitched crtc granularity */
1332 /* The rest disables double buffering on CRTC access */
1333 regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
1335 if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
1336 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1337 if (nv_crtc->head == 0) {
1338 regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1342 regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0);
1343 if (!NVMatchModePrivate(mode, NV_MODE_VGA)) {
1344 regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 1);
1348 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
1349 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
1352 /* Sometimes 0x10 is used, what is this? */
1353 regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1354 /* Some kind of tmds switch for older cards */
1355 if (pNv->Architecture < NV_ARCH_40) {
1356 regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
1360 * Initialize DAC palette.
1361 * Will only be written when depth != 8.
1363 for (i = 0; i < 256; i++) {
1365 regp->DAC[(i*3)+1] = i;
1366 regp->DAC[(i*3)+2] = i;
1370 * Calculate the extended registers.
1373 if (pLayout->depth < 24) {
1374 depth = pLayout->depth;
1379 if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1380 /* bpp is pitch related. */
1381 depth = pNv->console_mode[nv_crtc->head].bpp;
1384 /* What is the meaning of this register? */
1385 /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1386 regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
1390 /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1391 /* But what are those special conditions? */
1392 if (pNv->Architecture <= NV_ARCH_30) {
1394 if(nv_crtc->head == 1) {
1395 regp->head |= NV_CRTC_FSEL_FPP1;
1396 } else if (pNv->twoHeads) {
1397 regp->head |= NV_CRTC_FSEL_FPP2;
1401 /* Most G70 cards have FPP2 set on the secondary CRTC. */
1402 if (nv_crtc->head == 1 && pNv->NVArch > 0x44) {
1403 regp->head |= NV_CRTC_FSEL_FPP2;
1407 /* Except for rare conditions I2C is enabled on the primary crtc */
1408 if (nv_crtc->head == 0) {
1409 regp->head |= NV_CRTC_FSEL_I2C;
1412 /* Set overlay to desired crtc. */
1413 if (pNv->overlayAdaptor) {
1414 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(pNv);
1415 if (pPriv->overlayCRTC == nv_crtc->head)
1416 regp->head |= NV_CRTC_FSEL_OVERLAY;
1419 /* This is not what nv does, but it is what the blob does (for nv4x at least) */
1420 /* This fixes my cursor corruption issue */
1421 regp->cursorConfig = 0x0;
1422 if(mode->Flags & V_DBLSCAN)
1423 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_DOUBLE_SCAN;
1424 if (pNv->alphaCursor && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1425 regp->cursorConfig |= (NV_CRTC_CURSOR_CONFIG_32BPP |
1426 NV_CRTC_CURSOR_CONFIG_64PIXELS |
1427 NV_CRTC_CURSOR_CONFIG_64LINES |
1428 NV_CRTC_CURSOR_CONFIG_ALPHA_BLEND);
1430 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_32LINES;
1433 /* Unblock some timings */
1434 regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1435 regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1437 /* What is the purpose of this register? */
1438 /* 0x14 may be disabled? */
1439 regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1441 /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
1443 regp->CRTC[NV_VGA_CRTCX_3B] = 0x11;
1445 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1447 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1450 /* These values seem to vary */
1451 /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
1452 regp->CRTC[NV_VGA_CRTCX_SCRATCH4] = savep->CRTC[NV_VGA_CRTCX_SCRATCH4];
1454 if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1455 regp->CRTC[NV_VGA_CRTCX_45] = 0x0;
1457 regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1460 /* What does this do?:
1463 * bit7: lvds + tmds (only in X)
1465 if (nv_crtc->head == 0)
1466 regp->CRTC[NV_VGA_CRTCX_4B] = 0x1;
1468 regp->CRTC[NV_VGA_CRTCX_4B] = 0x0;
1471 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x40;
1473 if (is_fp && !NVMatchModePrivate(mode, NV_MODE_VGA))
1474 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x80;
1476 if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) { /* we need consistent restore. */
1477 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[nv_crtc->head];
1479 /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1.*/
1480 if (nv_crtc->head == 1) {
1481 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[0];
1483 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[0] + 4;
1488 /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1489 regp->gpio_ext = NVReadCRTC(pNv, 0, NV_PCRTC_GPIO_EXT);
1491 if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1495 regp->unk830 = mode->CrtcVDisplay - 3;
1496 regp->unk834 = mode->CrtcVDisplay - 1;
1500 /* This is what the blob does */
1501 regp->unk850 = NVReadCRTC(pNv, 0, NV_CRTC_0850);
1503 /* Never ever modify gpio, unless you know very well what you're doing */
1504 regp->gpio = NVReadCRTC(pNv, 0, NV_CRTC_GPIO);
1506 if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1507 regp->config = 0x0; /* VGA mode */
1509 regp->config = 0x2; /* HSYNC mode */
1512 /* Some misc regs */
1513 regp->CRTC[NV_VGA_CRTCX_43] = 0x1;
1514 if (pNv->Architecture == NV_ARCH_40) {
1515 regp->CRTC[NV_VGA_CRTCX_85] = 0xFF;
1516 regp->CRTC[NV_VGA_CRTCX_86] = 0x1;
1520 * Calculate the state that is common to all crtc's (stored in the state struct).
1522 ErrorF("crtc %d %d %d\n", nv_crtc->head, mode->CrtcHDisplay, pScrn->displayWidth);
1523 nv_crtc_calc_state_ext(crtc,
1526 pScrn->displayWidth,
1529 adjusted_mode->Clock,
1532 /* Enable slaved mode */
1534 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1539 nv_crtc_mode_set_ramdac_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1541 ScrnInfoPtr pScrn = crtc->scrn;
1542 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1543 NVCrtcRegPtr regp, savep;
1544 NVPtr pNv = NVPTR(pScrn);
1545 NVFBLayout *pLayout = &pNv->CurrentLayout;
1547 Bool is_lvds = FALSE;
1548 float aspect_ratio, panel_ratio;
1549 uint32_t h_scale, v_scale;
1551 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1552 savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1554 xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1555 NVOutputPrivatePtr nv_output = NULL;
1557 nv_output = output->driver_private;
1559 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1562 if (nv_output->type == OUTPUT_LVDS)
1567 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
1568 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
1569 /* This is what the blob does. */
1570 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HSyncStart - 75 - 1;
1571 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
1572 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
1573 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
1574 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
1576 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
1577 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
1578 /* This is what the blob does. */
1579 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VTotal - 5 - 1;
1580 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
1581 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
1582 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
1583 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
1585 ErrorF("Horizontal:\n");
1586 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
1587 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
1588 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
1589 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
1590 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
1591 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
1592 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
1594 ErrorF("Vertical:\n");
1595 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
1596 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
1597 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
1598 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
1599 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
1600 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
1601 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
1605 * bit0: positive vsync
1606 * bit4: positive hsync
1607 * bit8: enable center mode
1608 * bit9: enable native mode
1609 * bit24: 12/24 bit interface (12bit=on, 24bit=off)
1610 * bit26: a bit sometimes seen on some g70 cards
1611 * bit28: fp display enable bit
1612 * bit31: set for dual link LVDS
1613 * nv10reg contains a few more things, but i don't quite get what it all means.
1616 if (pNv->Architecture >= NV_ARCH_30)
1617 regp->fp_control[nv_crtc->head] = 0x00100000;
1619 regp->fp_control[nv_crtc->head] = 0x00000000;
1621 /* Deal with vsync/hsync polarity */
1622 /* LVDS screens do set this, but modes with +ve syncs are very rare */
1624 if (adjusted_mode->Flags & V_PVSYNC)
1625 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
1626 if (adjusted_mode->Flags & V_PHSYNC)
1627 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
1629 /* The blob doesn't always do this, but often */
1630 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_VSYNC_DISABLE;
1631 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_HSYNC_DISABLE;
1635 if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) /* seems to be used almost always */
1636 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1637 else if (nv_output->scaling_mode == SCALE_PANEL) /* panel needs to scale */
1638 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
1639 /* This is also true for panel scaling, so we must put the panel scale check first */
1640 else if (mode->Clock == adjusted_mode->Clock) /* native mode */
1641 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
1642 else /* gpu needs to scale */
1643 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1646 if (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
1647 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
1649 /* If the special bit exists, it exists on both ramdacs */
1650 regp->fp_control[nv_crtc->head] |= NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL) & (1 << 26);
1653 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS;
1655 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE;
1657 Bool lvds_use_straps = pNv->dcb_table.entry[nv_output->dcb_entry].lvdsconf.use_straps_for_mode;
1658 if (is_lvds && ((lvds_use_straps && pNv->VBIOS.fp.dual_link) || (!lvds_use_straps && adjusted_mode->Clock >= pNv->VBIOS.fp.duallink_transition_clk)))
1659 regp->fp_control[nv_crtc->head] |= (8 << 28);
1662 ErrorF("Pre-panel scaling\n");
1663 ErrorF("panel-size:%dx%d\n", nv_output->fpWidth, nv_output->fpHeight);
1664 panel_ratio = (nv_output->fpWidth)/(float)(nv_output->fpHeight);
1665 ErrorF("panel_ratio=%f\n", panel_ratio);
1666 aspect_ratio = (mode->HDisplay)/(float)(mode->VDisplay);
1667 ErrorF("aspect_ratio=%f\n", aspect_ratio);
1668 /* Scale factors is the so called 20.12 format, taken from Haiku */
1669 h_scale = ((1 << 12) * mode->HDisplay)/nv_output->fpWidth;
1670 v_scale = ((1 << 12) * mode->VDisplay)/nv_output->fpHeight;
1671 ErrorF("h_scale=%d\n", h_scale);
1672 ErrorF("v_scale=%d\n", v_scale);
1674 /* This can override HTOTAL and VTOTAL */
1677 /* We want automatic scaling */
1680 regp->fp_hvalid_start = 0;
1681 regp->fp_hvalid_end = (nv_output->fpWidth - 1);
1683 regp->fp_vvalid_start = 0;
1684 regp->fp_vvalid_end = (nv_output->fpHeight - 1);
1686 /* 0 = panel scaling */
1687 if (nv_output->scaling_mode == SCALE_PANEL) {
1688 ErrorF("Flat panel is doing the scaling.\n");
1690 ErrorF("GPU is doing the scaling.\n");
1692 if (nv_output->scaling_mode == SCALE_ASPECT) {
1693 /* GPU scaling happens automaticly at a ratio of 1.33 */
1694 /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
1695 if (h_scale != (1 << 12) && (panel_ratio > (aspect_ratio + 0.10))) {
1698 ErrorF("Scaling resolution on a widescreen panel\n");
1700 /* Scaling in both directions needs to the same */
1703 /* Set a new horizontal scale factor and enable testmode (bit12) */
1704 regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
1706 diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
1707 regp->fp_hvalid_start = diff/2;
1708 regp->fp_hvalid_end = nv_output->fpWidth - (diff/2) - 1;
1711 /* Same scaling, just for panels with aspect ratio's smaller than 1 */
1712 if (v_scale != (1 << 12) && (panel_ratio < (aspect_ratio - 0.10))) {
1715 ErrorF("Scaling resolution on a portrait panel\n");
1717 /* Scaling in both directions needs to the same */
1720 /* Set a new vertical scale factor and enable testmode (bit28) */
1721 regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
1723 diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
1724 regp->fp_vvalid_start = diff/2;
1725 regp->fp_vvalid_end = nv_output->fpHeight - (diff/2) - 1;
1730 ErrorF("Post-panel scaling\n");
1733 if (!is_fp && NVMatchModePrivate(mode, NV_MODE_VGA)) {
1734 regp->debug_1 = 0x08000800;
1737 if (pNv->Architecture >= NV_ARCH_10) {
1738 /* Only bit that bios and blob set. */
1739 regp->nv10_cursync = (1<<25);
1742 /* These are the common blob values, minus a few fp specific bit's */
1743 /* Let's keep the TMDS pll and fpclock running in all situations */
1744 regp->debug_0[nv_crtc->head] = 0x1101100;
1746 if (is_fp && nv_output->scaling_mode != SCALE_NOSCALE) {
1747 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_XSCALE_ENABLED;
1748 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_YSCALE_ENABLED;
1749 } else if (is_fp) { /* no_scale mode, so we must center it */
1752 diff = nv_output->fpWidth - mode->HDisplay;
1753 regp->fp_hvalid_start = diff/2;
1754 regp->fp_hvalid_end = (nv_output->fpWidth - diff/2 - 1);
1756 diff = nv_output->fpHeight - mode->VDisplay;
1757 regp->fp_vvalid_start = diff/2;
1758 regp->fp_vvalid_end = (nv_output->fpHeight - diff/2 - 1);
1761 /* Is this crtc bound or output bound? */
1762 /* Does the bios TMDS script try to change this sometimes? */
1764 /* I am not completely certain, but seems to be set only for dfp's */
1765 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED;
1769 ErrorF("output %d debug_0 %08X\n", nv_output->output_resource, regp->debug_0[nv_crtc->head]);
1771 /* Flatpanel support needs at least a NV10 */
1772 if (pNv->twoHeads) {
1773 if (pNv->FPDither || (is_lvds && !pNv->VBIOS.fp.if_is_24bit)) {
1774 if (pNv->NVArch == 0x11)
1775 regp->dither = savep->dither | 0x00010000;
1778 regp->dither = savep->dither | 0x00000001;
1779 for (i = 0; i < 3; i++) {
1780 regp->dither_regs[i] = 0xe4e4e4e4;
1781 regp->dither_regs[i + 3] = 0x44444444;
1785 regp->dither = savep->dither;
1789 /* This is mode related, not pitch. */
1790 if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1791 depth = pNv->console_mode[nv_crtc->head].depth;
1793 depth = pLayout->depth;
1798 regp->general = 0x00000100;
1802 regp->general = 0x00100100;
1808 regp->general = 0x00101100;
1812 if (depth > 8 && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1813 regp->general |= 0x30; /* enable palette mode */
1816 if (pNv->alphaCursor && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1817 /* PIPE_LONG mode, something to do with the size of the cursor? */
1818 regp->general |= (1<<29);
1821 /* Some values the blob sets */
1822 /* This may apply to the real ramdac that is being used (for crosswired situations) */
1823 /* Nevertheless, it's unlikely to cause many problems, since the values are equal for both */
1824 regp->unk_a20 = 0x0;
1825 regp->unk_a24 = 0xfffff;
1826 regp->unk_a34 = 0x1;
1828 if (pNv->twoHeads) {
1829 /* Do we also "own" the other register pair? */
1830 /* If we own neither, they will just be ignored at load time. */
1831 uint8_t other_head = (~nv_crtc->head) & 1;
1832 if (pNv->fp_regs_owner[other_head] == nv_crtc->head) {
1833 if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS) {
1834 regp->fp_control[other_head] = regp->fp_control[nv_crtc->head];
1835 regp->debug_0[other_head] = regp->debug_0[nv_crtc->head];
1836 /* Set TMDS_PLL and FPCLK, only seen for a NV31M so far. */
1837 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK;
1838 regp->debug_0[other_head] |= NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL;
1840 ErrorF("This is BAD, we own more than one fp reg set, but are not a LVDS or TMDS output.\n");
1847 * Sets up registers for the given mode/adjusted_mode pair.
1849 * The clocks, CRTCs and outputs attached to this CRTC must be off.
1851 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1852 * be easily turned on/off after this.
1855 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
1856 DisplayModePtr adjusted_mode,
1859 ScrnInfoPtr pScrn = crtc->scrn;
1860 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1861 NVPtr pNv = NVPTR(pScrn);
1862 NVFBLayout *pLayout = &pNv->CurrentLayout;
1864 ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->head);
1866 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->head);
1867 xf86PrintModeline(pScrn->scrnIndex, mode);
1869 NVCrtcSetOwner(crtc);
1871 nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
1873 /* set sel_clk before calculating PLLs */
1874 nv_crtc_mode_set_sel_clk(crtc, &pNv->ModeReg);
1875 if (pNv->Architecture == NV_ARCH_40) {
1876 ErrorF("writing sel_clk %08X\n", pNv->ModeReg.sel_clk);
1877 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, pNv->ModeReg.sel_clk);
1879 nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
1880 nv_crtc_mode_set_ramdac_regs(crtc, mode, adjusted_mode);
1882 NVVgaProtect(crtc, TRUE);
1883 nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
1884 nv_crtc_load_state_ext(crtc, &pNv->ModeReg, FALSE);
1885 if (pLayout->depth > 8)
1886 nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
1887 nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
1888 if (pNv->Architecture == NV_ARCH_40) {
1889 nv40_crtc_load_state_pll(crtc, &pNv->ModeReg);
1891 nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
1894 NVVgaProtect(crtc, FALSE);
1896 NVCrtcSetBase(crtc, x, y, NVMatchModePrivate(mode, NV_MODE_CONSOLE));
1898 #if X_BYTE_ORDER == X_BIG_ENDIAN
1899 /* turn on LFB swapping */
1903 tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
1905 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
1910 void nv_crtc_save(xf86CrtcPtr crtc)
1912 ScrnInfoPtr pScrn = crtc->scrn;
1913 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1914 NVPtr pNv = NVPTR(pScrn);
1916 ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->head);
1918 /* We just came back from terminal, so unlock */
1919 NVCrtcLockUnlock(crtc, FALSE);
1921 nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
1922 nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
1923 nv_crtc_save_state_palette(crtc, &pNv->SavedReg);
1924 nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
1925 if (pNv->Architecture == NV_ARCH_40) {
1926 nv40_crtc_save_state_pll(pNv, &pNv->SavedReg);
1928 nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
1932 void nv_crtc_restore(xf86CrtcPtr crtc)
1934 ScrnInfoPtr pScrn = crtc->scrn;
1935 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1936 NVPtr pNv = NVPTR(pScrn);
1937 RIVA_HW_STATE *state;
1940 state = &pNv->SavedReg;
1941 savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1943 ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->head);
1945 /* Just to be safe */
1946 NVCrtcLockUnlock(crtc, FALSE);
1948 NVVgaProtect(crtc, TRUE);
1949 nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
1950 nv_crtc_load_state_ext(crtc, &pNv->SavedReg, TRUE);
1951 nv_crtc_load_state_palette(crtc, &pNv->SavedReg);
1952 nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
1954 /* Force restoring vpll. */
1955 state->vpll_changed[nv_crtc->head] = TRUE;
1957 if (pNv->Architecture == NV_ARCH_40) {
1958 nv40_crtc_load_state_pll(crtc, &pNv->SavedReg);
1960 nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
1962 NVVgaProtect(crtc, FALSE);
1964 nv_crtc->last_dpms = NV_DPMS_CLEARED;
1968 NVResetCrtcConfig(xf86CrtcPtr crtc, Bool set)
1970 ScrnInfoPtr pScrn = crtc->scrn;
1971 NVPtr pNv = NVPTR(pScrn);
1973 if (pNv->twoHeads) {
1976 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1981 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1985 NVCrtcWriteCRTC(crtc, NV_CRTC_FSEL, val);
1989 void nv_crtc_prepare(xf86CrtcPtr crtc)
1991 ScrnInfoPtr pScrn = crtc->scrn;
1992 NVPtr pNv = NVPTR(pScrn);
1993 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1995 ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->head);
1998 NVCrtcLockUnlock(crtc, 0);
2000 NVResetCrtcConfig(crtc, FALSE);
2002 crtc->funcs->dpms(crtc, DPMSModeOff);
2004 /* Sync the engine before adjust mode */
2005 if (pNv->EXADriverPtr) {
2006 exaMarkSync(pScrn->pScreen);
2007 exaWaitSync(pScrn->pScreen);
2010 NVCrtcBlankScreen(crtc, FALSE); /* Blank screen */
2012 /* Some more preperation. */
2013 NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, 0x1); /* Go to non-vga mode/out of enhanced mode */
2014 if (pNv->Architecture == NV_ARCH_40) {
2015 uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
2016 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
2020 void nv_crtc_commit(xf86CrtcPtr crtc)
2022 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2023 ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->head);
2025 crtc->funcs->dpms (crtc, DPMSModeOn);
2027 if (crtc->scrn->pScreen != NULL)
2028 xf86_reload_cursors (crtc->scrn->pScreen);
2030 NVResetCrtcConfig(crtc, TRUE);
2033 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
2035 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2036 ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->head);
2041 static void nv_crtc_unlock(xf86CrtcPtr crtc)
2043 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2044 ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->head);
2048 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
2051 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2052 ScrnInfoPtr pScrn = crtc->scrn;
2053 NVPtr pNv = NVPTR(pScrn);
2057 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2059 switch (pNv->CurrentLayout.depth) {
2062 /* We've got 5 bit (32 values) colors and 256 registers for each color */
2063 for (i = 0; i < 32; i++) {
2064 for (j = 0; j < 8; j++) {
2065 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2066 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
2067 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2073 /* First deal with the 5 bit colors */
2074 for (i = 0; i < 32; i++) {
2075 for (j = 0; j < 8; j++) {
2076 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2077 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2080 /* Now deal with the 6 bit color */
2081 for (i = 0; i < 64; i++) {
2082 for (j = 0; j < 4; j++) {
2083 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
2089 for (i = 0; i < 256; i++) {
2090 regp->DAC[i * 3] = red[i] >> 8;
2091 regp->DAC[(i * 3) + 1] = green[i] >> 8;
2092 regp->DAC[(i * 3) + 2] = blue[i] >> 8;
2097 nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
2101 * Allocates memory for a locked-in-framebuffer shadow of the given
2102 * width and height for this CRTC's rotated shadow framebuffer.
2106 nv_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
2108 ErrorF("nv_crtc_shadow_allocate is called\n");
2109 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2110 ScrnInfoPtr pScrn = crtc->scrn;
2111 #if !NOUVEAU_EXA_PIXMAPS
2112 ScreenPtr pScreen = pScrn->pScreen;
2113 #endif /* !NOUVEAU_EXA_PIXMAPS */
2114 NVPtr pNv = NVPTR(pScrn);
2117 unsigned long rotate_pitch;
2118 int size, align = 64;
2120 rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2121 size = rotate_pitch * height;
2123 assert(nv_crtc->shadow == NULL);
2124 #if NOUVEAU_EXA_PIXMAPS
2125 if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN,
2126 align, size, &nv_crtc->shadow)) {
2127 ErrorF("Failed to allocate memory for shadow buffer!\n");
2131 if (nv_crtc->shadow && nouveau_bo_map(nv_crtc->shadow, NOUVEAU_BO_RDWR)) {
2132 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2133 "Failed to map shadow buffer.\n");
2137 offset = nv_crtc->shadow->map;
2139 nv_crtc->shadow = exaOffscreenAlloc(pScreen, size, align, TRUE, NULL, NULL);
2140 if (nv_crtc->shadow == NULL) {
2141 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2142 "Couldn't allocate shadow memory for rotated CRTC\n");
2145 offset = pNv->FB->map + nv_crtc->shadow->offset;
2146 #endif /* NOUVEAU_EXA_PIXMAPS */
2152 * Creates a pixmap for this CRTC's rotated shadow framebuffer.
2155 nv_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
2157 ErrorF("nv_crtc_shadow_create is called\n");
2158 ScrnInfoPtr pScrn = crtc->scrn;
2159 #if NOUVEAU_EXA_PIXMAPS
2160 ScreenPtr pScreen = pScrn->pScreen;
2161 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2162 #endif /* NOUVEAU_EXA_PIXMAPS */
2163 unsigned long rotate_pitch;
2164 PixmapPtr rotate_pixmap;
2165 #if NOUVEAU_EXA_PIXMAPS
2166 struct nouveau_pixmap *nvpix;
2167 #endif /* NOUVEAU_EXA_PIXMAPS */
2170 data = crtc->funcs->shadow_allocate (crtc, width, height);
2172 rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2174 #if NOUVEAU_EXA_PIXMAPS
2175 /* Create a dummy pixmap, to get a private that will be accepted by the system.*/
2176 rotate_pixmap = pScreen->CreatePixmap(pScreen,
2179 #ifdef CREATE_PIXMAP_USAGE_SCRATCH /* there seems to have been no api bump */
2184 #endif /* CREATE_PIXMAP_USAGE_SCRATCH */
2186 rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen,
2189 pScrn->bitsPerPixel,
2192 #endif /* NOUVEAU_EXA_PIXMAPS */
2194 if (rotate_pixmap == NULL) {
2195 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2196 "Couldn't allocate shadow pixmap for rotated CRTC\n");
2199 #if NOUVEAU_EXA_PIXMAPS
2200 nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2202 ErrorF("No shadow private, stage 1\n");
2204 nvpix->bo = nv_crtc->shadow;
2205 nvpix->mapped = TRUE;
2208 /* Modify the pixmap to actually be the one we need. */
2209 pScreen->ModifyPixmapHeader(rotate_pixmap,
2213 pScrn->bitsPerPixel,
2217 nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2218 if (!nvpix || !nvpix->bo)
2219 ErrorF("No shadow private, stage 2\n");
2220 #endif /* NOUVEAU_EXA_PIXMAPS */
2222 return rotate_pixmap;
2226 nv_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
2228 ErrorF("nv_crtc_shadow_destroy is called\n");
2229 ScrnInfoPtr pScrn = crtc->scrn;
2230 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2231 ScreenPtr pScreen = pScrn->pScreen;
2233 if (rotate_pixmap) { /* This should also unmap the buffer object if relevant. */
2234 pScreen->DestroyPixmap(rotate_pixmap);
2237 #if !NOUVEAU_EXA_PIXMAPS
2238 if (data && nv_crtc->shadow) {
2239 exaOffscreenFree(pScreen, nv_crtc->shadow);
2241 #endif /* !NOUVEAU_EXA_PIXMAPS */
2243 nv_crtc->shadow = NULL;
2246 /* NV04-NV10 doesn't support alpha cursors */
2247 static const xf86CrtcFuncsRec nv_crtc_funcs = {
2248 .dpms = nv_crtc_dpms,
2249 .save = nv_crtc_save, /* XXX */
2250 .restore = nv_crtc_restore, /* XXX */
2251 .mode_fixup = nv_crtc_mode_fixup,
2252 .mode_set = nv_crtc_mode_set,
2253 .prepare = nv_crtc_prepare,
2254 .commit = nv_crtc_commit,
2255 .destroy = NULL, /* XXX */
2256 .lock = nv_crtc_lock,
2257 .unlock = nv_crtc_unlock,
2258 .set_cursor_colors = nv_crtc_set_cursor_colors,
2259 .set_cursor_position = nv_crtc_set_cursor_position,
2260 .show_cursor = nv_crtc_show_cursor,
2261 .hide_cursor = nv_crtc_hide_cursor,
2262 .load_cursor_image = nv_crtc_load_cursor_image,
2263 .gamma_set = nv_crtc_gamma_set,
2264 .shadow_create = nv_crtc_shadow_create,
2265 .shadow_allocate = nv_crtc_shadow_allocate,
2266 .shadow_destroy = nv_crtc_shadow_destroy,
2269 /* NV11 and up has support for alpha cursors. */
2270 /* Due to different maximum sizes we cannot allow it to use normal cursors */
2271 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
2272 .dpms = nv_crtc_dpms,
2273 .save = nv_crtc_save, /* XXX */
2274 .restore = nv_crtc_restore, /* XXX */
2275 .mode_fixup = nv_crtc_mode_fixup,
2276 .mode_set = nv_crtc_mode_set,
2277 .prepare = nv_crtc_prepare,
2278 .commit = nv_crtc_commit,
2279 .destroy = NULL, /* XXX */
2280 .lock = nv_crtc_lock,
2281 .unlock = nv_crtc_unlock,
2282 .set_cursor_colors = NULL, /* Alpha cursors do not need this */
2283 .set_cursor_position = nv_crtc_set_cursor_position,
2284 .show_cursor = nv_crtc_show_cursor,
2285 .hide_cursor = nv_crtc_hide_cursor,
2286 .load_cursor_argb = nv_crtc_load_cursor_argb,
2287 .gamma_set = nv_crtc_gamma_set,
2288 .shadow_create = nv_crtc_shadow_create,
2289 .shadow_allocate = nv_crtc_shadow_allocate,
2290 .shadow_destroy = nv_crtc_shadow_destroy,
2295 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
2297 NVPtr pNv = NVPTR(pScrn);
2299 NVCrtcPrivatePtr nv_crtc;
2301 if (pNv->NVArch >= 0x11) {
2302 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
2304 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
2309 nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
2310 nv_crtc->head = crtc_num;
2311 nv_crtc->last_dpms = NV_DPMS_CLEARED;
2312 pNv->fp_regs_owner[nv_crtc->head] = nv_crtc->head;
2314 crtc->driver_private = nv_crtc;
2316 NVCrtcLockUnlock(crtc, FALSE);
2319 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2321 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2325 regp = &state->crtc_reg[nv_crtc->head];
2327 NVWritePVIO(crtc, VGA_MISC_OUT_W, regp->MiscOutReg);
2329 for (i = 0; i < 5; i++)
2330 NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
2332 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
2333 NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
2335 for (i = 0; i < 25; i++)
2336 NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
2338 for (i = 0; i < 9; i++)
2339 NVWriteVgaGr(crtc, i, regp->Graphics[i]);
2341 NVEnablePalette(crtc);
2342 for (i = 0; i < 21; i++)
2343 NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
2345 NVDisablePalette(crtc);
2348 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override)
2350 ScrnInfoPtr pScrn = crtc->scrn;
2351 NVPtr pNv = NVPTR(pScrn);
2352 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2356 regp = &state->crtc_reg[nv_crtc->head];
2358 if (pNv->Architecture >= NV_ARCH_10) {
2359 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
2360 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
2361 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
2362 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
2363 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2364 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2365 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2366 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2367 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, 0);
2369 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
2370 NVCrtcWriteCRTC(crtc, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
2371 NVCrtcWriteCRTC(crtc, NV_CRTC_0830, regp->unk830);
2372 NVCrtcWriteCRTC(crtc, NV_CRTC_0834, regp->unk834);
2373 if (pNv->Architecture == NV_ARCH_40) {
2374 NVCrtcWriteCRTC(crtc, NV_CRTC_0850, regp->unk850);
2375 NVCrtcWriteCRTC(crtc, NV_PCRTC_GPIO_EXT, regp->gpio_ext);
2378 if (pNv->Architecture == NV_ARCH_40) {
2379 uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
2380 if (regp->config == 0x2) { /* enhanced "horizontal only" non-vga mode */
2381 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 | 0x10000);
2383 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
2388 NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, regp->config);
2389 NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO, regp->gpio);
2391 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
2392 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
2393 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
2394 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
2395 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
2396 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
2397 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
2398 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
2399 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
2400 if (pNv->Architecture >= NV_ARCH_30)
2401 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
2403 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
2404 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
2405 if (pNv->Architecture == NV_ARCH_40) /* HW bug */
2406 nv_crtc_fix_nv40_hw_cursor(crtc);
2407 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
2408 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
2410 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
2411 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
2412 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SCRATCH4, regp->CRTC[NV_VGA_CRTCX_SCRATCH4]);
2413 if (pNv->Architecture >= NV_ARCH_10) {
2414 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
2415 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_43, regp->CRTC[NV_VGA_CRTCX_43]);
2416 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
2417 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_4B, regp->CRTC[NV_VGA_CRTCX_4B]);
2418 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
2420 /* NV11 and NV20 stop at 0x52. */
2421 if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
2423 for (i = 0; i < 0x10; i++)
2424 NVWriteVGACR5758(pNv, nv_crtc->head, i, regp->CR58[i]);
2426 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
2427 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
2429 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
2431 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_85, regp->CRTC[NV_VGA_CRTCX_85]);
2432 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_86, regp->CRTC[NV_VGA_CRTCX_86]);
2435 /* Setting 1 on this value gives you interrupts for every vblank period. */
2436 NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_EN_0, 0);
2437 NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
2439 pNv->CurrentState = state;
2442 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2444 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2448 regp = &state->crtc_reg[nv_crtc->head];
2450 regp->MiscOutReg = NVReadPVIO(crtc, VGA_MISC_OUT_R);
2452 for (i = 0; i < 25; i++)
2453 regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
2455 NVEnablePalette(crtc);
2456 for (i = 0; i < 21; i++)
2457 regp->Attribute[i] = NVReadVgaAttr(crtc, i);
2458 NVDisablePalette(crtc);
2460 for (i = 0; i < 9; i++)
2461 regp->Graphics[i] = NVReadVgaGr(crtc, i);
2463 for (i = 0; i < 5; i++)
2464 regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
2467 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2469 ScrnInfoPtr pScrn = crtc->scrn;
2470 NVPtr pNv = NVPTR(pScrn);
2471 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2475 regp = &state->crtc_reg[nv_crtc->head];
2477 regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
2478 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
2479 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
2480 regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
2481 regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
2482 regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
2483 regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
2485 regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
2486 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
2487 regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
2488 if (pNv->Architecture >= NV_ARCH_30)
2489 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
2490 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
2491 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
2492 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
2493 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
2495 if (pNv->Architecture >= NV_ARCH_10) {
2496 regp->unk830 = NVCrtcReadCRTC(crtc, NV_CRTC_0830);
2497 regp->unk834 = NVCrtcReadCRTC(crtc, NV_CRTC_0834);
2498 if (pNv->Architecture == NV_ARCH_40) {
2499 regp->unk850 = NVCrtcReadCRTC(crtc, NV_CRTC_0850);
2500 regp->gpio_ext = NVCrtcReadCRTC(crtc, NV_PCRTC_GPIO_EXT);
2502 if (pNv->twoHeads) {
2503 regp->head = NVCrtcReadCRTC(crtc, NV_CRTC_FSEL);
2504 regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
2506 regp->cursorConfig = NVCrtcReadCRTC(crtc, NV_CRTC_CURSOR_CONFIG);
2509 regp->gpio = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO);
2510 regp->config = NVCrtcReadCRTC(crtc, NV_CRTC_CONFIG);
2512 regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
2513 regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
2514 regp->CRTC[NV_VGA_CRTCX_SCRATCH4] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SCRATCH4);
2515 if (pNv->Architecture >= NV_ARCH_10) {
2516 regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
2517 regp->CRTC[NV_VGA_CRTCX_43] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_43);
2518 regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
2519 regp->CRTC[NV_VGA_CRTCX_4B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_4B);
2520 regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
2522 /* NV11 and NV20 don't have this, they stop at 0x52. */
2523 if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
2524 for (i = 0; i < 0x10; i++)
2525 regp->CR58[i] = NVReadVGACR5758(pNv, nv_crtc->head, i);
2527 regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
2528 regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
2529 regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
2531 regp->CRTC[NV_VGA_CRTCX_85] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_85);
2532 regp->CRTC[NV_VGA_CRTCX_86] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_86);
2536 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2538 ScrnInfoPtr pScrn = crtc->scrn;
2539 NVPtr pNv = NVPTR(pScrn);
2540 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2544 regp = &state->crtc_reg[nv_crtc->head];
2546 regp->general = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL);
2548 regp->fp_control[0] = NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL);
2549 regp->debug_0[0] = NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
2551 if (pNv->twoHeads) {
2552 regp->fp_control[1] = NVReadRAMDAC(pNv, 1, NV_RAMDAC_FP_CONTROL);
2553 regp->debug_0[1] = NVReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
2555 regp->debug_1 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1);
2556 regp->debug_2 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2);
2558 regp->unk_a20 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A20);
2559 regp->unk_a24 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A24);
2560 regp->unk_a34 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A34);
2563 if (pNv->NVArch == 0x11) {
2564 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_DITHER_NV11);
2565 } else if (pNv->twoHeads) {
2566 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DITHER);
2567 for (i = 0; i < 3; i++) {
2568 regp->dither_regs[i] = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_850 + i * 4);
2569 regp->dither_regs[i + 3] = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_85C + i * 4);
2572 if (pNv->Architecture >= NV_ARCH_10)
2573 regp->nv10_cursync = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC);
2575 /* The regs below are 0 for non-flatpanels, so you can load and save them */
2577 for (i = 0; i < 7; i++) {
2578 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2579 regp->fp_horiz_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
2582 for (i = 0; i < 7; i++) {
2583 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2584 regp->fp_vert_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
2587 regp->fp_hvalid_start = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_HVALID_START);
2588 regp->fp_hvalid_end = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_HVALID_END);
2589 regp->fp_vvalid_start = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_VVALID_START);
2590 regp->fp_vvalid_end = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_VVALID_END);
2593 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2595 ScrnInfoPtr pScrn = crtc->scrn;
2596 NVPtr pNv = NVPTR(pScrn);
2597 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2601 regp = &state->crtc_reg[nv_crtc->head];
2603 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL, regp->general);
2605 if (pNv->fp_regs_owner[0] == nv_crtc->head) {
2606 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL, regp->fp_control[0]);
2607 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0, regp->debug_0[0]);
2609 if (pNv->twoHeads) {
2610 if (pNv->fp_regs_owner[1] == nv_crtc->head) {
2611 NVWriteRAMDAC(pNv, 1, NV_RAMDAC_FP_CONTROL, regp->fp_control[1]);
2612 NVWriteRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0, regp->debug_0[1]);
2614 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
2615 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
2616 if (pNv->NVArch == 0x30) { /* For unknown purposes. */
2617 uint32_t reg890 = NVCrtcReadRAMDAC(crtc, NV30_RAMDAC_890);
2618 NVCrtcWriteRAMDAC(crtc, NV30_RAMDAC_89C, reg890);
2621 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A20, regp->unk_a20);
2622 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A24, regp->unk_a24);
2623 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A34, regp->unk_a34);
2626 if (pNv->NVArch == 0x11) {
2627 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_DITHER_NV11, regp->dither);
2628 } else if (pNv->twoHeads) {
2629 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DITHER, regp->dither);
2630 for (i = 0; i < 3; i++) {
2631 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_850 + i * 4, regp->dither_regs[i]);
2632 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_85C + i * 4, regp->dither_regs[i + 3]);
2635 if (pNv->Architecture >= NV_ARCH_10)
2636 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
2638 /* The regs below are 0 for non-flatpanels, so you can load and save them */
2640 for (i = 0; i < 7; i++) {
2641 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2642 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_horiz_regs[i]);
2645 for (i = 0; i < 7; i++) {
2646 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2647 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_vert_regs[i]);
2650 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_HVALID_START, regp->fp_hvalid_start);
2651 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_HVALID_END, regp->fp_hvalid_end);
2652 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_VVALID_START, regp->fp_vvalid_start);
2653 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_VVALID_END, regp->fp_vvalid_end);
2657 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y, Bool bios_restore)
2659 ScrnInfoPtr pScrn = crtc->scrn;
2660 NVPtr pNv = NVPTR(pScrn);
2661 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2662 NVFBLayout *pLayout = &pNv->CurrentLayout;
2665 ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
2668 start = pNv->console_mode[nv_crtc->head].fb_start;
2670 start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
2671 if (crtc->rotatedData != NULL) { /* we do not exist on the real framebuffer */
2672 #if NOUVEAU_EXA_PIXMAPS
2673 start = nv_crtc->shadow->offset;
2675 start = pNv->FB->offset + nv_crtc->shadow->offset; /* We do exist relative to the framebuffer */
2678 start += pNv->FB->offset;
2682 /* 30 bits addresses in 32 bits according to haiku */
2683 NVCrtcWriteCRTC(crtc, NV_CRTC_START, start & 0xfffffffc);
2685 /* set NV4/NV10 byte adress: (bit0 - 1) */
2686 NVWriteVgaAttr(crtc, 0x13, (start & 0x3) << 1);
2692 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2694 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2695 NVPtr pNv = NVPTR(crtc->scrn);
2696 volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2699 VGA_WR08(pDACReg, VGA_DAC_MASK, 0xff);
2700 VGA_WR08(pDACReg, VGA_DAC_READ_ADDR, 0x0);
2702 for (i = 0; i < 768; i++) {
2703 state->crtc_reg[nv_crtc->head].DAC[i] = NV_RD08(pDACReg, VGA_DAC_DATA);
2704 DDXMMIOH("nv_crtc_save_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, NV_PDIO0_OFFSET + (nv_crtc->head ? NV_PDIO0_SIZE : 0) + VGA_DAC_DATA, state->crtc_reg[nv_crtc->head].DAC[i]);
2707 NVDisablePalette(crtc);
2709 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2711 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2712 NVPtr pNv = NVPTR(crtc->scrn);
2713 volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2716 VGA_WR08(pDACReg, VGA_DAC_MASK, 0xff);
2717 VGA_WR08(pDACReg, VGA_DAC_WRITE_ADDR, 0x0);
2719 for (i = 0; i < 768; i++) {
2720 DDXMMIOH("nv_crtc_load_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, NV_PDIO0_OFFSET + (nv_crtc->head ? NV_PDIO0_SIZE : 0) + VGA_DAC_DATA, state->crtc_reg[nv_crtc->head].DAC[i]);
2721 NV_WR08(pDACReg, VGA_DAC_DATA, state->crtc_reg[nv_crtc->head].DAC[i]);
2724 NVDisablePalette(crtc);
2728 void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
2730 NVPtr pNv = NVPTR(crtc->scrn);
2734 NVCrtcSetOwner(crtc);
2736 scrn = NVReadVgaSeq(crtc, 0x01);
2743 NVVgaSeqReset(crtc, TRUE);
2744 NVWriteVgaSeq(crtc, 0x01, scrn);
2745 NVVgaSeqReset(crtc, FALSE);
2748 /* Reset a mode after a drastic output resource change for example. */
2749 void NVCrtcModeFix(xf86CrtcPtr crtc)
2751 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2757 if (!xf86ModesEqual(&crtc->mode, &crtc->desiredMode)) /* not currently in X */
2760 DisplayModePtr adjusted_mode = xf86DuplicateMode(&crtc->mode);
2761 uint8_t dpms_mode = nv_crtc->last_dpms;
2763 /* Set the crtc mode again. */
2764 crtc->funcs->dpms(crtc, DPMSModeOff);
2765 need_unlock = crtc->funcs->lock(crtc);
2766 crtc->funcs->mode_fixup(crtc, &crtc->mode, adjusted_mode);
2767 crtc->funcs->prepare(crtc);
2768 crtc->funcs->mode_set(crtc, &crtc->mode, adjusted_mode, crtc->x, crtc->y);
2769 crtc->funcs->commit(crtc);
2771 crtc->funcs->unlock(crtc);
2772 crtc->funcs->dpms(crtc, dpms_mode);
2775 xfree(adjusted_mode);
2778 /*************************************************************************** \
2780 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
2782 |* NOTICE TO USER: The source code is copyrighted under U.S. and *|
2783 |* international laws. Users and possessors of this source code are *|
2784 |* hereby granted a nonexclusive, royalty-free copyright license to *|
2785 |* use this code in individual and commercial software. *|
2787 |* Any use of this source code must include, in the user documenta- *|
2788 |* tion and internal comments to the code, notices to the end user *|
2791 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
2793 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
2794 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
2795 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
2796 |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
2797 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
2798 |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
2799 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
2800 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
2801 |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
2802 |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
2803 |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
2805 |* U.S. Government End Users. This source code is a "commercial *|
2806 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
2807 |* consisting of "commercial computer software" and "commercial *|
2808 |* computer software documentation," as such terms are used in *|
2809 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
2810 |* ment only as a commercial end item. Consistent with 48 C.F.R. *|
2811 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
2812 |* all U.S. Government End Users acquire the source code with only *|
2813 |* those rights set forth herein. *|
2815 \***************************************************************************/