git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 2006 Dave Airlie
   3  * Copyright 2007 Maarten Maathuis
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
  26  * decleration is at the bottom of this file as it is rather ugly
  27  */
  28
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include <assert.h>
  34 #include "xf86.h"
  35 #include "os.h"
  36 #include "mibank.h"
  37 #include "globals.h"
  38 #include "xf86.h"
  39 #include "xf86Priv.h"
  40 #include "xf86DDC.h"
  41 #include "mipointer.h"
  42 #include "windowstr.h"
  43 #include <randrstr.h>
  44 #include <X11/extensions/render.h>
  45
  46 #include "xf86Crtc.h"
  47 #include "nv_include.h"
  48
  49 #include "vgaHW.h"
  50
  51 #define CRTC_INDEX 0x3d4
  52 #define CRTC_DATA 0x3d5
  53 #define CRTC_IN_STAT_1 0x3da
  54
  55 #define WHITE_VALUE 0x3F
  56 #define BLACK_VALUE 0x00
  57 #define OVERSCAN_VALUE 0x01
  58
  59 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  60 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override);
  61 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  62 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  63 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  64 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  65
  66 static CARD8 NVReadPVIO(xf86CrtcPtr crtc, CARD32 address)
  67 {
  68         ScrnInfoPtr pScrn = crtc->scrn;
  69         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  70         NVPtr pNv = NVPTR(pScrn);
  71
  72         /* Only NV4x have two pvio ranges */
  73         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  74                 return NV_RD08(pNv->PVIO1, address);
  75         } else {
  76                 return NV_RD08(pNv->PVIO0, address);
  77         }
  78 }
  79
  80 static void NVWritePVIO(xf86CrtcPtr crtc, CARD32 address, CARD8 value)
  81 {
  82         ScrnInfoPtr pScrn = crtc->scrn;
  83         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  84         NVPtr pNv = NVPTR(pScrn);
  85
  86         /* Only NV4x have two pvio ranges */
  87         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  88                 NV_WR08(pNv->PVIO1, address, value);
  89         } else {
  90                 NV_WR08(pNv->PVIO0, address, value);
  91         }
  92 }
  93
  94 static void NVWriteMiscOut(xf86CrtcPtr crtc, CARD8 value)
  95 {
  96         NVWritePVIO(crtc, VGA_MISC_OUT_W, value);
  97 }
  98
  99 static CARD8 NVReadMiscOut(xf86CrtcPtr crtc)
 100 {
 101         return NVReadPVIO(crtc, VGA_MISC_OUT_R);
 102 }
 103
 104 void NVWriteVGA(NVPtr pNv, int head, CARD8 index, CARD8 value)
 105 {
 106         volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 107
 108         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 109         NV_WR08(pCRTCReg, CRTC_DATA, value);
 110 }
 111
 112 CARD8 NVReadVGA(NVPtr pNv, int head, CARD8 index)
 113 {
 114         volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 115
 116         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 117         return NV_RD08(pCRTCReg, CRTC_DATA);
 118 }
 119
 120 /* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
 121  * I suspect they in fact do nothing, but are merely a way to carry useful
 122  * per-head variables around
 123  *
 124  * Known uses:
 125  * CR57         CR58
 126  * 0x00         index to the appropriate dcb entry (or 7f for inactive)
 127  * 0x02         dcb entry's "or" value (or 00 for inactive)
 128  * 0x03         bit0 set for dual link (LVDS, possibly elsewhere too)
 129  * 0x0f         laptop panel info -     high nibble for PEXTDEV_BOOT strap
 130  *                                      low nibble for xlat strap value
 131  */
 132
 133 void NVWriteVGACR5758(NVPtr pNv, int head, uint8_t index, uint8_t value)
 134 {
 135         NVWriteVGA(pNv, head, 0x57, index);
 136         NVWriteVGA(pNv, head, 0x58, value);
 137 }
 138
 139 uint8_t NVReadVGACR5758(NVPtr pNv, int head, uint8_t index)
 140 {
 141         NVWriteVGA(pNv, head, 0x57, index);
 142         return NVReadVGA(pNv, head, 0x58);
 143 }
 144
 145 void NVWriteVgaCrtc(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 146 {
 147         ScrnInfoPtr pScrn = crtc->scrn;
 148         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 149         NVPtr pNv = NVPTR(pScrn);
 150
 151         NVWriteVGA(pNv, nv_crtc->head, index, value);
 152 }
 153
 154 CARD8 NVReadVgaCrtc(xf86CrtcPtr crtc, CARD8 index)
 155 {
 156         ScrnInfoPtr pScrn = crtc->scrn;
 157         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 158         NVPtr pNv = NVPTR(pScrn);
 159
 160         return NVReadVGA(pNv, nv_crtc->head, index);
 161 }
 162
 163 static void NVWriteVgaSeq(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 164 {
 165         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 166         NVWritePVIO(crtc, VGA_SEQ_DATA, value);
 167 }
 168
 169 static CARD8 NVReadVgaSeq(xf86CrtcPtr crtc, CARD8 index)
 170 {
 171         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 172         return NVReadPVIO(crtc, VGA_SEQ_DATA);
 173 }
 174
 175 static void NVWriteVgaGr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 176 {
 177         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 178         NVWritePVIO(crtc, VGA_GRAPH_DATA, value);
 179 }
 180
 181 static CARD8 NVReadVgaGr(xf86CrtcPtr crtc, CARD8 index)
 182 {
 183         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 184         return NVReadPVIO(crtc, VGA_GRAPH_DATA);
 185 }
 186
 187
 188 static void NVWriteVgaAttr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 189 {
 190   ScrnInfoPtr pScrn = crtc->scrn;
 191   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 192   NVPtr pNv = NVPTR(pScrn);
 193   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 194
 195   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 196   if (nv_crtc->paletteEnabled)
 197     index &= ~0x20;
 198   else
 199     index |= 0x20;
 200   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 201   NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
 202 }
 203
 204 static CARD8 NVReadVgaAttr(xf86CrtcPtr crtc, CARD8 index)
 205 {
 206   ScrnInfoPtr pScrn = crtc->scrn;
 207   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 208   NVPtr pNv = NVPTR(pScrn);
 209   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 210
 211   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 212   if (nv_crtc->paletteEnabled)
 213     index &= ~0x20;
 214   else
 215     index |= 0x20;
 216   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 217   return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
 218 }
 219
 220 void NVCrtcSetOwner(xf86CrtcPtr crtc)
 221 {
 222         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 223         ScrnInfoPtr pScrn = crtc->scrn;
 224         NVPtr pNv = NVPTR(pScrn);
 225         /* Non standard beheaviour required by NV11 */
 226         if (pNv) {
 227                 uint8_t owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 228                 ErrorF("pre-Owner: 0x%X\n", owner);
 229                 if (owner == 0x04) {
 230                         uint32_t pbus84 = nvReadMC(pNv, 0x1084);
 231                         ErrorF("pbus84: 0x%X\n", pbus84);
 232                         pbus84 &= ~(1<<28);
 233                         ErrorF("pbus84: 0x%X\n", pbus84);
 234                         nvWriteMC(pNv, 0x1084, pbus84);
 235                 }
 236                 /* The blob never writes owner to pcio1, so should we */
 237                 if (pNv->NVArch == 0x11) {
 238                         NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, 0xff);
 239                 }
 240                 NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, nv_crtc->crtc * 0x3);
 241                 owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 242                 ErrorF("post-Owner: 0x%X\n", owner);
 243         } else {
 244                 ErrorF("pNv pointer is NULL\n");
 245         }
 246 }
 247
 248 static void
 249 NVEnablePalette(xf86CrtcPtr crtc)
 250 {
 251   ScrnInfoPtr pScrn = crtc->scrn;
 252   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 253   NVPtr pNv = NVPTR(pScrn);
 254   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 255
 256   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 257   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
 258   nv_crtc->paletteEnabled = TRUE;
 259 }
 260
 261 static void
 262 NVDisablePalette(xf86CrtcPtr crtc)
 263 {
 264   ScrnInfoPtr pScrn = crtc->scrn;
 265   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 266   NVPtr pNv = NVPTR(pScrn);
 267   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 268
 269   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 270   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
 271   nv_crtc->paletteEnabled = FALSE;
 272 }
 273
 274 static void NVWriteVgaReg(xf86CrtcPtr crtc, CARD32 reg, CARD8 value)
 275 {
 276  ScrnInfoPtr pScrn = crtc->scrn;
 277   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 278   NVPtr pNv = NVPTR(pScrn);
 279   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 280
 281   NV_WR08(pCRTCReg, reg, value);
 282 }
 283
 284 /* perform a sequencer reset */
 285 static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
 286 {
 287   if (start)
 288     NVWriteVgaSeq(crtc, 0x00, 0x1);
 289   else
 290     NVWriteVgaSeq(crtc, 0x00, 0x3);
 291
 292 }
 293 static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
 294 {
 295         CARD8 tmp;
 296
 297         if (on) {
 298                 tmp = NVReadVgaSeq(crtc, 0x1);
 299                 NVVgaSeqReset(crtc, TRUE);
 300                 NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
 301
 302                 NVEnablePalette(crtc);
 303         } else {
 304                 /*
 305                  * Reenable sequencer, then turn on screen.
 306                  */
 307                 tmp = NVReadVgaSeq(crtc, 0x1);
 308                 NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20); /* reenable display */
 309                 NVVgaSeqReset(crtc, FALSE);
 310
 311                 NVDisablePalette(crtc);
 312         }
 313 }
 314
 315 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool Lock)
 316 {
 317         CARD8 cr11;
 318
 319         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57);
 320         cr11 = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE);
 321         if (Lock) cr11 |= 0x80;
 322         else cr11 &= ~0x80;
 323         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE, cr11);
 324 }
 325
 326 xf86OutputPtr
 327 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
 328 {
 329         ScrnInfoPtr pScrn = crtc->scrn;
 330         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 331         int i;
 332         for (i = 0; i < xf86_config->num_output; i++) {
 333                 xf86OutputPtr output = xf86_config->output[i];
 334
 335                 if (output->crtc == crtc) {
 336                         return output;
 337                 }
 338         }
 339
 340         return NULL;
 341 }
 342
 343 xf86CrtcPtr
 344 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
 345 {
 346         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 347         int i;
 348
 349         for (i = 0; i < xf86_config->num_crtc; i++) {
 350                 xf86CrtcPtr crtc = xf86_config->crtc[i];
 351                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 352                 if (nv_crtc->crtc == index)
 353                         return crtc;
 354         }
 355
 356         return NULL;
 357 }
 358
 359 /*
 360  * Calculate the Video Clock parameters for the PLL.
 361  */
 362 static void CalcVClock (
 363         uint32_t                clockIn,
 364         uint32_t                *clockOut,
 365         CARD32          *pllOut,
 366         NVPtr           pNv
 367 )
 368 {
 369         unsigned lowM, highM, highP;
 370         unsigned DeltaNew, DeltaOld;
 371         unsigned VClk, Freq;
 372         unsigned M, N, P;
 373
 374         /* M: PLL reference frequency postscaler divider */
 375         /* P: PLL VCO output postscaler divider */
 376         /* N: PLL VCO postscaler setting */
 377
 378         DeltaOld = 0xFFFFFFFF;
 379
 380         VClk = (unsigned)clockIn;
 381
 382         /* Taken from Haiku, after someone with an NV28 had an issue */
 383         switch(pNv->NVArch) {
 384                 case 0x28:
 385                         lowM = 1;
 386                         highP = 32;
 387                         if (VClk > 340000) {
 388                                 highM = 2;
 389                         } else if (VClk > 200000) {
 390                                 highM = 4;
 391                         } else if (VClk > 150000) {
 392                                 highM = 6;
 393                         } else {
 394                                 highM = 14;
 395                         }
 396                         break;
 397                 default:
 398                         lowM = 1;
 399                         highP = 16;
 400                         if (VClk > 340000) {
 401                                 highM = 2;
 402                         } else if (VClk > 250000) {
 403                                 highM = 6;
 404                         } else {
 405                                 highM = 14;
 406                         }
 407                         break;
 408         }
 409
 410         for (P = 1; P <= highP; P++) {
 411                 Freq = VClk << P;
 412                 if ((Freq >= 128000) && (Freq <= 350000)) {
 413                         for (M = lowM; M <= highM; M++) {
 414                                 N = ((VClk << P) * M) / pNv->CrystalFreqKHz;
 415                                 if (N <= 255) {
 416                                         Freq = ((pNv->CrystalFreqKHz * N) / M) >> P;
 417                                         if (Freq > VClk) {
 418                                                 DeltaNew = Freq - VClk;
 419                                         } else {
 420                                                 DeltaNew = VClk - Freq;
 421                                         }
 422                                         if (DeltaNew < DeltaOld) {
 423                                                 *pllOut   = (P << 16) | (N << 8) | M;
 424                                                 *clockOut = Freq;
 425                                                 DeltaOld  = DeltaNew;
 426                                         }
 427                                 }
 428                         }
 429                 }
 430         }
 431 }
 432
 433 static void CalcVClock2Stage (
 434         uint32_t                clockIn,
 435         uint32_t                *clockOut,
 436         CARD32          *pllOut,
 437         CARD32          *pllBOut,
 438         NVPtr           pNv
 439 )
 440 {
 441         unsigned DeltaNew, DeltaOld;
 442         unsigned VClk, Freq;
 443         unsigned M, N, P;
 444         unsigned lowM, highM, highP;
 445
 446         DeltaOld = 0xFFFFFFFF;
 447
 448         *pllBOut = 0x80000401;  /* fixed at x4 for now */
 449
 450         VClk = (unsigned)clockIn;
 451
 452         /* Taken from Haiku, after someone with an NV28 had an issue */
 453         switch(pNv->NVArch) {
 454                 case 0x28:
 455                         lowM = 1;
 456                         highP = 32;
 457                         if (VClk > 340000) {
 458                                 highM = 2;
 459                         } else if (VClk > 200000) {
 460                                 highM = 4;
 461                         } else if (VClk > 150000) {
 462                                 highM = 6;
 463                         } else {
 464                                 highM = 14;
 465                         }
 466                         break;
 467                 default:
 468                         lowM = 1;
 469                         highP = 15;
 470                         if (VClk > 340000) {
 471                                 highM = 2;
 472                         } else if (VClk > 250000) {
 473                                 highM = 6;
 474                         } else {
 475                                 highM = 14;
 476                         }
 477                         break;
 478         }
 479
 480         for (P = 0; P <= highP; P++) {
 481                 Freq = VClk << P;
 482                 if ((Freq >= 400000) && (Freq <= 1000000)) {
 483                         for (M = lowM; M <= highM; M++) {
 484                                 N = ((VClk << P) * M) / (pNv->CrystalFreqKHz << 2);
 485                                 if ((N >= 5) && (N <= 255)) {
 486                                         Freq = (((pNv->CrystalFreqKHz << 2) * N) / M) >> P;
 487                                         if (Freq > VClk) {
 488                                                 DeltaNew = Freq - VClk;
 489                                         } else {
 490                                                 DeltaNew = VClk - Freq;
 491                                         }
 492                                         if (DeltaNew < DeltaOld) {
 493                                                 *pllOut   = (P << 16) | (N << 8) | M;
 494                                                 *clockOut = Freq;
 495                                                 DeltaOld  = DeltaNew;
 496                                         }
 497                                 }
 498                         }
 499                 }
 500         }
 501 }
 502
 503 /* BIG NOTE: modifying vpll1 and vpll2vpll2 does not work, what bit is the switch to allow it? */
 504
 505 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
 506 /* They are only valid for NV4x, appearantly reordered for NV5x */
 507 /* gpu pll: 0x4000 + 0x4004
 508  * unknown pll: 0x4008 + 0x400c
 509  * vpll1: 0x4010 + 0x4014
 510  * vpll2: 0x4018 + 0x401c
 511  * unknown pll: 0x4020 + 0x4024
 512  * unknown pll: 0x4038 + 0x403c
 513  * Some of the unknown's are probably memory pll's.
 514  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
 515  * 1 and 2 refer to the registers of each pair. There is only one post divider.
 516  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
 517  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
 518  *     bit8: A switch that turns of the second divider and multiplier off.
 519  *     bit12: Also a switch, i haven't seen it yet.
 520  *     bit16-19: p-divider
 521  *     but 28-31: Something related to the mode that is used (see bit8).
 522  * 2) bit0-7: m-divider (a)
 523  *     bit8-15: n-multiplier (a)
 524  *     bit16-23: m-divider (b)
 525  *     bit24-31: n-multiplier (b)
 526  */
 527
 528 /* Modifying the gpu pll for example requires:
 529  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 530  * This is not needed for the vpll's which have their own bits.
 531  */
 532
 533 static void
 534 CalculateVClkNV4x(
 535         NVPtr pNv,
 536         uint32_t requested_clock,
 537         uint32_t *given_clock,
 538         uint32_t *pll_a,
 539         uint32_t *pll_b,
 540         uint32_t *reg580,
 541         Bool    *db1_ratio,
 542         Bool primary,
 543         uint8_t special_bits
 544 )
 545 {
 546         uint32_t DeltaOld, DeltaNew;
 547         uint32_t freq, temp;
 548         /* We have 2 mulitpliers, 2 dividers and one post divider */
 549         /* Note that p is only 4 bits */
 550         uint32_t m1, m2, n1, n2, p;
 551         uint32_t m1_best = 0, m2_best = 0, n1_best = 0, n2_best = 0, p_best = 0;
 552
 553         DeltaOld = 0xFFFFFFFF;
 554
 555         /* This is no solid limit, but a reasonable boundary */
 556         if (requested_clock < 120000) {
 557                 *db1_ratio = TRUE;
 558                 /* Turn the second set of divider and multiplier off */
 559                 /* Neutral settings */
 560                 n2 = 1;
 561                 m2 = 1;
 562         } else {
 563                 *db1_ratio = FALSE;
 564                 /* Fixed at x4 for the moment */
 565                 n2 = 4;
 566                 m2 = 1;
 567         }
 568
 569         n2_best = n2;
 570         m2_best = m2;
 571
 572         /* Single pll */
 573         if (*db1_ratio) {
 574                 temp = 0.4975 * 250000;
 575                 p = 0;
 576
 577                 while (requested_clock <= temp) {
 578                         temp /= 2;
 579                         p++;
 580                 }
 581
 582                 /* The minimum clock after m1 is 3 Mhz, and the clock is 27 Mhz, so m_max = 9 */
 583                 /* The maximum clock is 25 Mhz */
 584                 for (m1 = 2; m1 <= 9; m1++) {
 585                         n1 = ((requested_clock << p) * m1)/(pNv->CrystalFreqKHz);
 586                         if (n1 > 0 && n1 <= 255) {
 587                                 freq = ((pNv->CrystalFreqKHz * n1)/m1) >> p;
 588                                 if (freq > requested_clock) {
 589                                         DeltaNew = freq - requested_clock;
 590                                 } else {
 591                                         DeltaNew = requested_clock - freq;
 592                                 }
 593                                 if (DeltaNew < DeltaOld) {
 594                                         m1_best = m1;
 595                                         n1_best = n1;
 596                                         p_best = p;
 597                                         DeltaOld = DeltaNew;
 598                                 }
 599                         }
 600                 }
 601         /* Dual pll */
 602         } else {
 603                 for (p = 0; p <= 6; p++) {
 604                         /* Assuming a fixed 2nd stage */
 605                         freq = requested_clock << p;
 606                         /* The maximum output frequency of stage 2 is allowed to be between 400 Mhz and 1 GHz */
 607                         if (freq > 400000 && freq < 1000000) {
 608                                 /* The minimum clock after m1 is 3 Mhz, and the clock is 27 Mhz, so m_max = 9 */
 609                                 /* The maximum clock is 25 Mhz */
 610                                 for (m1 = 2; m1 <= 9; m1++) {
 611                                         n1 = ((requested_clock << p) * m1 * m2)/(pNv->CrystalFreqKHz * n2);
 612                                         if (n1 >= 5 && n1 <= 255) {
 613                                                 freq = ((pNv->CrystalFreqKHz * n1 * n2)/(m1 * m2)) >> p;
 614                                                 if (freq > requested_clock) {
 615                                                         DeltaNew = freq - requested_clock;
 616                                                 } else {
 617                                                         DeltaNew = requested_clock - freq;
 618                                                 }
 619                                                 if (DeltaNew < DeltaOld) {
 620                                                         m1_best = m1;
 621                                                         n1_best = n1;
 622                                                         p_best = p;
 623                                                         DeltaOld = DeltaNew;
 624                                                 }
 625                                         }
 626                                 }
 627                         }
 628                 }
 629         }
 630
 631         if (*db1_ratio) {
 632                 /* Bogus data, the same nvidia uses */
 633                 n2_best = 1;
 634                 m2_best = 31;
 635         }
 636
 637         /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
 638         /* Let's keep the special bits, if the bios already set them */
 639         *pll_a = (special_bits << 30) | (p_best << 16) | (n1_best << 8) | (m1_best << 0);
 640         *pll_b = (1 << 31) | (n2_best << 8) | (m2_best << 0);
 641
 642         if (*db1_ratio) {
 643                 if (primary) {
 644                         *reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 645                 } else {
 646                         *reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 647                 }
 648         } else {
 649                 if (primary) {
 650                         *reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
 651                 } else {
 652                         *reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
 653                 }
 654         }
 655
 656         if (*db1_ratio) {
 657                 ErrorF("vpll: n1 %d m1 %d p %d db1_ratio %d\n", n1_best, m1_best, p_best, *db1_ratio);
 658         } else {
 659                 ErrorF("vpll: n1 %d n2 %d m1 %d m2 %d p %d db1_ratio %d\n", n1_best, n2_best, m1_best, m2_best, p_best, *db1_ratio);
 660         }
 661 }
 662
 663 static void nv40_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 664 {
 665         state->vpll1_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 666         state->vpll1_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 667         state->vpll2_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 668         state->vpll2_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 669         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 670         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 671         state->reg580 = nvReadRAMDAC0(pNv, NV_RAMDAC_580);
 672         state->reg594 = nvReadRAMDAC0(pNv, NV_RAMDAC_594);
 673 }
 674
 675 static void nv40_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 676 {
 677         CARD32 fp_debug_0[2];
 678         uint32_t index[2];
 679         fp_debug_0[0] = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
 680         fp_debug_0[1] = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
 681
 682         /* The TMDS_PLL switch is on the actual ramdac */
 683         if (state->crosswired) {
 684                 index[0] = 1;
 685                 index[1] = 0;
 686                 ErrorF("Crosswired pll state load\n");
 687         } else {
 688                 index[0] = 0;
 689                 index[1] = 1;
 690         }
 691
 692         if (state->vpll2_b) {
 693                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0,
 694                         fp_debug_0[index[1]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 695
 696                 /* Wait for the situation to stabilise */
 697                 usleep(5000);
 698
 699                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 700                 /* for vpll2 change bits 18 and 19 are disabled */
 701                 reg_c040 &= ~(0x3 << 18);
 702                 nvWriteMC(pNv, 0xc040, reg_c040);
 703
 704                 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 705                 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 706
 707                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2_a);
 708                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 709
 710                 ErrorF("writing pllsel %08X\n", state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 711                 /* Let's keep the primary vpll off */
 712                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 713
 714                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 715                 ErrorF("writing reg580 %08X\n", state->reg580);
 716
 717                 /* We need to wait a while */
 718                 usleep(5000);
 719                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 720
 721                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[1]]);
 722
 723                 /* Wait for the situation to stabilise */
 724                 usleep(5000);
 725         }
 726
 727         if (state->vpll1_b) {
 728                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0,
 729                         fp_debug_0[index[0]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 730
 731                 /* Wait for the situation to stabilise */
 732                 usleep(5000);
 733
 734                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 735                 /* for vpll2 change bits 16 and 17 are disabled */
 736                 reg_c040 &= ~(0x3 << 16);
 737                 nvWriteMC(pNv, 0xc040, reg_c040);
 738
 739                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 740                 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 741
 742                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll1_a);
 743                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpll1_b);
 744
 745                 ErrorF("writing pllsel %08X\n", state->pllsel);
 746                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 747
 748                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 749                 ErrorF("writing reg580 %08X\n", state->reg580);
 750
 751                 /* We need to wait a while */
 752                 usleep(5000);
 753                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 754
 755                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[0]]);
 756
 757                 /* Wait for the situation to stabilise */
 758                 usleep(5000);
 759         }
 760
 761         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 762         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 763
 764         ErrorF("writing reg594 %08X\n", state->reg594);
 765         nvWriteRAMDAC0(pNv, NV_RAMDAC_594, state->reg594);
 766 }
 767
 768 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 769 {
 770         state->vpll = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 771         if(pNv->twoHeads) {
 772                 state->vpll2 = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 773         }
 774         if(pNv->twoStagePLL) {
 775                 state->vpllB = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 776                 state->vpll2B = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 777         }
 778         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 779         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 780 }
 781
 782
 783 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 784 {
 785         if (state->vpll2) {
 786                 if(pNv->twoHeads) {
 787                         ErrorF("writing vpll2 %08X\n", state->vpll2);
 788                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2);
 789                 }
 790                 if(pNv->twoStagePLL) {
 791                         ErrorF("writing vpll2B %08X\n", state->vpll2B);
 792                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2B);
 793                 }
 794
 795                 ErrorF("writing pllsel %08X\n", state->pllsel);
 796                 /* Let's keep the primary vpll off */
 797                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 798         }
 799
 800         if (state->vpll) {
 801                 ErrorF("writing vpll %08X\n", state->vpll);
 802                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll);
 803                 if(pNv->twoStagePLL) {
 804                         ErrorF("writing vpllB %08X\n", state->vpllB);
 805                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpllB);
 806                 }
 807
 808                 ErrorF("writing pllsel %08X\n", state->pllsel);
 809                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 810         }
 811
 812         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 813         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 814 }
 815
 816 #define IS_NV44P (pNv->NVArch >= 0x44 ? 1 : 0)
 817
 818 /*
 819  * Calculate extended mode parameters (SVGA) and save in a
 820  * mode state structure.
 821  * State is not specific to a single crtc, but shared.
 822  */
 823 void nv_crtc_calc_state_ext(
 824         xf86CrtcPtr     crtc,
 825         int                     bpp,
 826         int                     DisplayWidth, /* Does this change after setting the mode? */
 827         int                     CrtcHDisplay,
 828         int                     CrtcVDisplay,
 829         int                     dotClock,
 830         int                     flags
 831 )
 832 {
 833         ScrnInfoPtr pScrn = crtc->scrn;
 834         uint32_t pixelDepth, VClk = 0;
 835         CARD32 CursorStart;
 836         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 837         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 838         NVCrtcRegPtr regp;
 839         NVPtr pNv = NVPTR(pScrn);
 840         RIVA_HW_STATE *state, *sv_state;
 841         int num_crtc_enabled, i;
 842
 843         state = &pNv->ModeReg;
 844         sv_state = &pNv->SavedReg;
 845
 846         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 847
 848         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 849         NVOutputPrivatePtr nv_output = NULL;
 850         if (output) {
 851                 nv_output = output->driver_private;
 852         }
 853
 854         /*
 855          * Extended RIVA registers.
 856          */
 857         pixelDepth = (bpp + 1)/8;
 858         if (pNv->Architecture == NV_ARCH_40) {
 859                 /* Does register 0x580 already have a value? */
 860                 if (!state->reg580) {
 861                         state->reg580 = pNv->misc_info.ramdac_0_reg_580;
 862                 }
 863                 if (nv_crtc->head == 1) {
 864                         CalculateVClkNV4x(pNv, dotClock, &VClk, &state->vpll2_a, &state->vpll2_b, &state->reg580, &state->db1_ratio[1], FALSE, (sv_state->vpll2_a >> 30));
 865                 } else {
 866                         CalculateVClkNV4x(pNv, dotClock, &VClk, &state->vpll1_a, &state->vpll1_b, &state->reg580, &state->db1_ratio[0], TRUE, (sv_state->vpll1_a >> 30));
 867                 }
 868         } else if (pNv->twoStagePLL) {
 869                 CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB, pNv);
 870         } else {
 871                 CalcVClock(dotClock, &VClk, &state->pll, pNv);
 872         }
 873
 874         switch (pNv->Architecture) {
 875         case NV_ARCH_04:
 876                 nv4UpdateArbitrationSettings(VClk,
 877                                                 pixelDepth * 8,
 878                                                 &(state->arbitration0),
 879                                                 &(state->arbitration1),
 880                                                 pNv);
 881                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
 882                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
 883                 if (flags & V_DBLSCAN)
 884                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 885                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
 886                 state->pllsel   |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
 887                 state->config   = 0x00001114;
 888                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 889                 break;
 890         case NV_ARCH_10:
 891         case NV_ARCH_20:
 892         case NV_ARCH_30:
 893         default:
 894                 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
 895                         ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
 896                         state->arbitration0 = 128;
 897                         state->arbitration1 = 0x0480;
 898                 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
 899                         ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
 900                         nForceUpdateArbitrationSettings(VClk,
 901                                                 pixelDepth * 8,
 902                                                 &(state->arbitration0),
 903                                                 &(state->arbitration1),
 904                                                 pNv);
 905                 } else if (pNv->Architecture < NV_ARCH_30) {
 906                         nv10UpdateArbitrationSettings(VClk,
 907                                                 pixelDepth * 8,
 908                                                 &(state->arbitration0),
 909                                                 &(state->arbitration1),
 910                                                 pNv);
 911                 } else {
 912                         nv30UpdateArbitrationSettings(pNv,
 913                                                 &(state->arbitration0),
 914                                                 &(state->arbitration1));
 915                 }
 916
 917                 CursorStart = pNv->Cursor->offset;
 918
 919                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
 920                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
 921                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
 922
 923                 if (flags & V_DBLSCAN)
 924                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 925
 926                 state->config   = nvReadFB(pNv, NV_PFB_CFG0);
 927                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 928                 break;
 929         }
 930
 931         /* okay do we have 2 CRTCs running ? */
 932         num_crtc_enabled = 0;
 933         for (i = 0; i < xf86_config->num_crtc; i++) {
 934                 if (xf86_config->crtc[i]->enabled) {
 935                         num_crtc_enabled++;
 936                 }
 937         }
 938
 939         ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
 940
 941         if (pNv->Architecture < NV_ARCH_40) {
 942                 /* We need this before the next code */
 943                 if (nv_crtc->head == 1) {
 944                         state->vpll2 = state->pll;
 945                         state->vpll2B = state->pllB;
 946                 } else {
 947                         state->vpll = state->pll;
 948                         state->vpllB = state->pllB;
 949                 }
 950         }
 951
 952         if (pNv->Architecture == NV_ARCH_40) {
 953                 /* This register is only used on the primary ramdac */
 954                 /* This seems to be needed to select the proper clocks, otherwise bad things happen */
 955
 956                 if (!state->sel_clk)
 957                         state->sel_clk = pNv->misc_info.sel_clk & ~(0xfff << 8);
 958
 959                 /* There are a few possibilities:
 960                  * Early NV4x cards: 0x41000 for example
 961                  * Later NV4x cards: 0x40100 for example
 962                  * The lower entry is the first bus, the higher entry is the second bus
 963                  * 0: No dvi present
 964                  * 1: Primary clock
 965                  * 2: Unknown, similar to 4?
 966                  * 4: Secondary clock
 967                  */
 968
 969                 /* This won't work when tv-out's come into play */
 970                 state->sel_clk &= ~(0xf << (16 - 4 * !nv_output->preferred_output * (1 + IS_NV44P)));
 971                 if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
 972                         if (nv_crtc->head == 1) { /* clock */
 973                                 state->sel_clk |= 0x4 << (16 - 4 * !nv_output->preferred_output * (1 + IS_NV44P));
 974                         } else {
 975                                 state->sel_clk |= 0x1 << (16 - 4 * !nv_output->preferred_output * (1 + IS_NV44P));
 976                         }
 977                 }
 978
 979                 /* The hardware gets upset if for example 0x00100 is set instead of 0x40100 */
 980                 if ((state->sel_clk & (0xff << 8)) && !(state->sel_clk & (0xf << 16))) {
 981                         if ((state->sel_clk & (0xf << (12 -  4*IS_NV44P))) == (0x1 << (12 -  4*IS_NV44P))) {
 982                                 state->sel_clk |= (0x4 << 16);
 983                         } else {
 984                                 state->sel_clk |= (0x1 << 16);
 985                         }
 986                 }
 987
 988                 /* Are we crosswired? */
 989                 if (output && nv_crtc->head != nv_output->preferred_output &&
 990                         (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
 991                         state->crosswired = TRUE;
 992                 } else if (output && nv_crtc->head != nv_output->preferred_output) {
 993                         state->crosswired = FALSE;
 994                 } else {
 995                         state->crosswired = FALSE;
 996                 }
 997
 998                 if (nv_crtc->head == 1) {
 999                         if (state->db1_ratio[1])
1000                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1001                 } else if (nv_crtc->head == 0) {
1002                         if (state->db1_ratio[0])
1003                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1004                 }
1005         } else {
1006                 /* This seems true for nv34 */
1007                 state->sel_clk = 0x0;
1008                 state->crosswired = FALSE;
1009         }
1010
1011         if (nv_crtc->head == 1) {
1012                 if (!state->db1_ratio[1]) {
1013                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1014                 } else {
1015                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1016                 }
1017                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
1018         } else {
1019                 if (pNv->Architecture < NV_ARCH_40)
1020                         state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
1021                 else
1022                         state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
1023                 if (!state->db1_ratio[0]) {
1024                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1025                 } else {
1026                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1027                 }
1028         }
1029
1030         /* The blob uses this always, so let's do the same */
1031         if (pNv->Architecture == NV_ARCH_40) {
1032                 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
1033         }
1034
1035         /* The primary output doesn't seem to care */
1036         if (nv_output->preferred_output == 1) { /* This is the "output" */
1037                 /* non-zero values are for analog, don't know about tv-out and the likes */
1038                 if (output && nv_output->type != OUTPUT_ANALOG) {
1039                         state->reg594 = 0x0;
1040                 } else {
1041                         /* More values exist, but they seem related to the 3rd dac (tv-out?) somehow */
1042                         /* bit 16-19 are bits that are set on some G70 cards */
1043                         /* Those bits are also set to the 3rd OUTPUT register */
1044                         if (nv_crtc->head == 1) {
1045                                 state->reg594 = 0x101;
1046                         } else {
1047                                 state->reg594 = 0x1;
1048                         }
1049                 }
1050         }
1051
1052         regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
1053         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
1054         if (pNv->Architecture >= NV_ARCH_30) {
1055                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
1056         }
1057
1058         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
1059         regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
1060 }
1061
1062 static void
1063 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
1064 {
1065         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1066         ScrnInfoPtr pScrn = crtc->scrn;
1067         NVPtr pNv = NVPTR(pScrn);
1068         unsigned char seq1 = 0, crtc17 = 0;
1069         unsigned char crtc1A;
1070
1071         ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->crtc, mode);
1072
1073         NVCrtcSetOwner(crtc);
1074
1075         crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
1076         switch(mode) {
1077                 case DPMSModeStandby:
1078                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
1079                 seq1 = 0x20;
1080                 crtc17 = 0x80;
1081                 crtc1A |= 0x80;
1082                 break;
1083         case DPMSModeSuspend:
1084                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
1085                 seq1 = 0x20;
1086                 crtc17 = 0x80;
1087                 crtc1A |= 0x40;
1088                 break;
1089         case DPMSModeOff:
1090                 /* Screen: Off; HSync: Off, VSync: Off */
1091                 seq1 = 0x20;
1092                 crtc17 = 0x00;
1093                 crtc1A |= 0xC0;
1094                 break;
1095         case DPMSModeOn:
1096         default:
1097                 /* Screen: On; HSync: On, VSync: On */
1098                 seq1 = 0x00;
1099                 crtc17 = 0x80;
1100                 break;
1101         }
1102
1103         NVVgaSeqReset(crtc, TRUE);
1104         /* Each head has it's own sequencer, so we can turn it off when we want */
1105         seq1 |= (NVReadVgaSeq(crtc, 0x01) & ~0x20);
1106         NVWriteVgaSeq(crtc, 0x1, seq1);
1107         crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
1108         usleep(10000);
1109         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
1110         NVVgaSeqReset(crtc, FALSE);
1111
1112         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
1113
1114         /* I hope this is the right place */
1115         if (crtc->enabled && mode == DPMSModeOn) {
1116                 pNv->crtc_active[nv_crtc->head] = TRUE;
1117         } else {
1118                 pNv->crtc_active[nv_crtc->head] = FALSE;
1119         }
1120 }
1121
1122 static Bool
1123 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
1124                      DisplayModePtr adjusted_mode)
1125 {
1126         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1127         ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->crtc);
1128
1129         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1130         NVOutputPrivatePtr nv_output = NULL;
1131         if (output) {
1132                 nv_output = output->driver_private;
1133         }
1134
1135         /* For internal panels and gpu scaling on DVI we need the native mode */
1136         if (output && ((nv_output->type == OUTPUT_LVDS) || (nv_output->scaling_mode > 0 && (nv_output->type == OUTPUT_TMDS)))) {
1137                 adjusted_mode->HDisplay = nv_output->native_mode->HDisplay;
1138                 adjusted_mode->HSkew = nv_output->native_mode->HSkew;
1139                 adjusted_mode->HSyncStart = nv_output->native_mode->HSyncStart;
1140                 adjusted_mode->HSyncEnd = nv_output->native_mode->HSyncEnd;
1141                 adjusted_mode->HTotal = nv_output->native_mode->HTotal;
1142                 adjusted_mode->VDisplay = nv_output->native_mode->VDisplay;
1143                 adjusted_mode->VScan = nv_output->native_mode->VScan;
1144                 adjusted_mode->VSyncStart = nv_output->native_mode->VSyncStart;
1145                 adjusted_mode->VSyncEnd = nv_output->native_mode->VSyncEnd;
1146                 adjusted_mode->VTotal = nv_output->native_mode->VTotal;
1147                 adjusted_mode->Clock = nv_output->native_mode->Clock;
1148
1149                 xf86SetModeCrtc(adjusted_mode, INTERLACE_HALVE_V);
1150         }
1151
1152         return TRUE;
1153 }
1154
1155 static void
1156 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1157 {
1158         ScrnInfoPtr pScrn = crtc->scrn;
1159         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1160         NVCrtcRegPtr regp;
1161         NVPtr pNv = NVPTR(pScrn);
1162         NVFBLayout *pLayout = &pNv->CurrentLayout;
1163         int depth = pScrn->depth;
1164
1165         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1166
1167         /* Calculate our timings */
1168         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
1169         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
1170         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
1171         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
1172         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
1173         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
1174         int vertDisplay         = mode->CrtcVDisplay                    - 1;
1175         int vertStart           = mode->CrtcVSyncStart          - 1;
1176         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
1177         int vertTotal           = mode->CrtcVTotal                      - 2;
1178         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
1179         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
1180
1181         Bool is_fp = FALSE;
1182
1183         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1184         NVOutputPrivatePtr nv_output = NULL;
1185         if (output) {
1186                 nv_output = output->driver_private;
1187
1188                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1189                         is_fp = TRUE;
1190         }
1191
1192         ErrorF("Mode clock: %d\n", mode->Clock);
1193         ErrorF("Adjusted mode clock: %d\n", adjusted_mode->Clock);
1194
1195         /* Reverted to what nv did, because that works for all resolutions on flatpanels */
1196         if (is_fp) {
1197                 vertStart = vertTotal - 3;
1198                 vertEnd = vertTotal - 2;
1199                 vertBlankStart = vertStart;
1200                 horizStart = horizTotal - 5;
1201                 horizEnd = horizTotal - 2;
1202                 horizBlankEnd = horizTotal + 4;
1203                 if (pNv->overlayAdaptor) {
1204                         /* This reportedly works around Xv some overlay bandwidth problems*/
1205                         horizTotal += 2;
1206                 }
1207         }
1208
1209         if(mode->Flags & V_INTERLACE)
1210                 vertTotal |= 1;
1211
1212         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
1213         ErrorF("horizStart: 0x%X \n", horizStart);
1214         ErrorF("horizEnd: 0x%X \n", horizEnd);
1215         ErrorF("horizTotal: 0x%X \n", horizTotal);
1216         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
1217         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
1218         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
1219         ErrorF("vertStart: 0x%X \n", vertStart);
1220         ErrorF("vertEnd: 0x%X \n", vertEnd);
1221         ErrorF("vertTotal: 0x%X \n", vertTotal);
1222         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
1223         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
1224
1225         /*
1226         * compute correct Hsync & Vsync polarity
1227         */
1228         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
1229                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
1230
1231                 regp->MiscOutReg = 0x23;
1232                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
1233                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
1234         } else {
1235                 int VDisplay = mode->VDisplay;
1236                 if (mode->Flags & V_DBLSCAN)
1237                         VDisplay *= 2;
1238                 if (mode->VScan > 1)
1239                         VDisplay *= mode->VScan;
1240                 if (VDisplay < 400) {
1241                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
1242                 } else if (VDisplay < 480) {
1243                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
1244                 } else if (VDisplay < 768) {
1245                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
1246                 } else {
1247                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
1248                 }
1249         }
1250
1251         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
1252
1253         /*
1254         * Time Sequencer
1255         */
1256         if (depth == 4) {
1257                 regp->Sequencer[0] = 0x02;
1258         } else {
1259                 regp->Sequencer[0] = 0x00;
1260         }
1261         /* 0x20 disables the sequencer */
1262         if (mode->Flags & V_CLKDIV2) {
1263                 regp->Sequencer[1] = 0x29;
1264         } else {
1265                 regp->Sequencer[1] = 0x21;
1266         }
1267         if (depth == 1) {
1268                 regp->Sequencer[2] = 1 << BIT_PLANE;
1269         } else {
1270                 regp->Sequencer[2] = 0x0F;
1271                 regp->Sequencer[3] = 0x00;                     /* Font select */
1272         }
1273         if (depth < 8) {
1274                 regp->Sequencer[4] = 0x06;                             /* Misc */
1275         } else {
1276                 regp->Sequencer[4] = 0x0E;                             /* Misc */
1277         }
1278
1279         /*
1280         * CRTC Controller
1281         */
1282         regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
1283         regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
1284         regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
1285         regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0)
1286                                 | SetBit(7);
1287         regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
1288         regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
1289                                 | SetBitField(horizEnd,4:0,4:0);
1290         regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
1291         regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
1292                                 | SetBitField(vertDisplay,8:8,1:1)
1293                                 | SetBitField(vertStart,8:8,2:2)
1294                                 | SetBitField(vertBlankStart,8:8,3:3)
1295                                 | SetBit(4)
1296                                 | SetBitField(vertTotal,9:9,5:5)
1297                                 | SetBitField(vertDisplay,9:9,6:6)
1298                                 | SetBitField(vertStart,9:9,7:7);
1299         regp->CRTC[NV_VGA_CRTCX_PRROWSCN]  = 0x00;
1300         regp->CRTC[NV_VGA_CRTCX_MAXSCLIN]  = SetBitField(vertBlankStart,9:9,5:5)
1301                                 | SetBit(6)
1302                                 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00);
1303         regp->CRTC[NV_VGA_CRTCX_VGACURCTRL] = 0x00;
1304         regp->CRTC[0xb] = 0x00;
1305         regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00;
1306         regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
1307         regp->CRTC[0xe] = 0x00;
1308         regp->CRTC[0xf] = 0x00;
1309         regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
1310         regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
1311         regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
1312         regp->CRTC[0x14] = 0x00;
1313         regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
1314         regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
1315         regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
1316         /* 0x80 enables the sequencer, we don't want that */
1317         if (depth < 8) {
1318                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xE3 & ~0x80;
1319         } else {
1320                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80;
1321         }
1322         regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
1323
1324         /*
1325          * Some extended CRTC registers (they are not saved with the rest of the vga regs).
1326          */
1327
1328         regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
1329                                 | SetBitField(vertBlankStart,10:10,3:3)
1330                                 | SetBitField(vertStart,10:10,2:2)
1331                                 | SetBitField(vertDisplay,10:10,1:1)
1332                                 | SetBitField(vertTotal,10:10,0:0);
1333
1334         regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
1335                                 | SetBitField(horizDisplay,8:8,1:1)
1336                                 | SetBitField(horizBlankStart,8:8,2:2)
1337                                 | SetBitField(horizStart,8:8,3:3);
1338
1339         regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
1340                                 | SetBitField(vertDisplay,11:11,2:2)
1341                                 | SetBitField(vertStart,11:11,4:4)
1342                                 | SetBitField(vertBlankStart,11:11,6:6);
1343
1344         if(mode->Flags & V_INTERLACE) {
1345                 horizTotal = (horizTotal >> 1) & ~1;
1346                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
1347                 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
1348         } else {
1349                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff;  /* interlace off */
1350         }
1351
1352         /*
1353         * Theory resumes here....
1354         */
1355
1356         /*
1357         * Graphics Display Controller
1358         */
1359         regp->Graphics[0] = 0x00;
1360         regp->Graphics[1] = 0x00;
1361         regp->Graphics[2] = 0x00;
1362         regp->Graphics[3] = 0x00;
1363         if (depth == 1) {
1364                 regp->Graphics[4] = BIT_PLANE;
1365                 regp->Graphics[5] = 0x00;
1366         } else {
1367                 regp->Graphics[4] = 0x00;
1368                 if (depth == 4) {
1369                         regp->Graphics[5] = 0x02;
1370                 } else {
1371                         regp->Graphics[5] = 0x40;
1372                 }
1373         }
1374         regp->Graphics[6] = 0x05;   /* only map 64k VGA memory !!!! */
1375         regp->Graphics[7] = 0x0F;
1376         regp->Graphics[8] = 0xFF;
1377
1378         /* I ditched the mono stuff */
1379         regp->Attribute[0]  = 0x00; /* standard colormap translation */
1380         regp->Attribute[1]  = 0x01;
1381         regp->Attribute[2]  = 0x02;
1382         regp->Attribute[3]  = 0x03;
1383         regp->Attribute[4]  = 0x04;
1384         regp->Attribute[5]  = 0x05;
1385         regp->Attribute[6]  = 0x06;
1386         regp->Attribute[7]  = 0x07;
1387         regp->Attribute[8]  = 0x08;
1388         regp->Attribute[9]  = 0x09;
1389         regp->Attribute[10] = 0x0A;
1390         regp->Attribute[11] = 0x0B;
1391         regp->Attribute[12] = 0x0C;
1392         regp->Attribute[13] = 0x0D;
1393         regp->Attribute[14] = 0x0E;
1394         regp->Attribute[15] = 0x0F;
1395         /* These two below are non-vga */
1396         regp->Attribute[16] = 0x01;
1397         regp->Attribute[17] = 0x00;
1398         regp->Attribute[18] = 0x0F;
1399         regp->Attribute[19] = 0x00;
1400         regp->Attribute[20] = 0x00;
1401 }
1402
1403 #define MAX_H_VALUE(i) ((0x1ff + i) << 3)
1404 #define MAX_V_VALUE(i) ((0xfff + i) << 0)
1405
1406 /**
1407  * Sets up registers for the given mode/adjusted_mode pair.
1408  *
1409  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1410  *
1411  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1412  * be easily turned on/off after this.
1413  */
1414 static void
1415 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1416 {
1417         ScrnInfoPtr pScrn = crtc->scrn;
1418         NVPtr pNv = NVPTR(pScrn);
1419         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1420         NVFBLayout *pLayout = &pNv->CurrentLayout;
1421         NVCrtcRegPtr regp, savep;
1422         unsigned int i;
1423         Bool is_fp = FALSE;
1424
1425         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1426         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1427
1428         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1429         NVOutputPrivatePtr nv_output = NULL;
1430         if (output) {
1431                 nv_output = output->driver_private;
1432
1433                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1434                         is_fp = TRUE;
1435         }
1436
1437         /* Registers not directly related to the (s)vga mode */
1438
1439         /* bit2 = 0 -> fine pitched crtc granularity */
1440         /* The rest disables double buffering on CRTC access */
1441         regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
1442
1443         if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
1444                 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1445                 if (nv_crtc->head == 0) {
1446                         regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1447                 }
1448
1449                 if (is_fp) {
1450                         regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0) | (1 << 1);
1451                 }
1452         } else {
1453                 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
1454                 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
1455         }
1456
1457         /* Sometimes 0x10 is used, what is this? */
1458         regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1459         /* Some kind of tmds switch for older cards */
1460         if (pNv->Architecture < NV_ARCH_40) {
1461                 regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
1462         }
1463
1464         /*
1465         * Initialize DAC palette.
1466         */
1467         if(pLayout->bitsPerPixel != 8 ) {
1468                 for (i = 0; i < 256; i++) {
1469                         regp->DAC[i*3]     = i;
1470                         regp->DAC[(i*3)+1] = i;
1471                         regp->DAC[(i*3)+2] = i;
1472                 }
1473         }
1474
1475         /*
1476         * Calculate the extended registers.
1477         */
1478
1479         if(pLayout->depth < 24) {
1480                 i = pLayout->depth;
1481         } else {
1482                 i = 32;
1483         }
1484
1485         if(pNv->Architecture >= NV_ARCH_10) {
1486                 pNv->CURSOR = (CARD32 *)pNv->Cursor->map;
1487         }
1488
1489         /* What is the meaning of this register? */
1490         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1491         regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
1492
1493         /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1494         /* But what are those special conditions? */
1495         if (pNv->Architecture <= NV_ARCH_30) {
1496                 if (is_fp) {
1497                         if(nv_crtc->head == 1) {
1498                                 regp->head |= NV_CRTC_FSEL_FPP1;
1499                         } else if (pNv->twoHeads) {
1500                                 regp->head |= NV_CRTC_FSEL_FPP2;
1501                         }
1502                 }
1503         } else {
1504                 /* Some G70 cards have either FPP1 or FPP2 set, copy this if it's already present */
1505                 if (nv_crtc->head == 1 && pNv->NVArch > 0x44) {
1506                         regp->head |= savep->head & (NV_CRTC_FSEL_FPP1 | NV_CRTC_FSEL_FPP2);
1507                 }
1508         }
1509
1510         /* Except for rare conditions I2C is enabled on the primary crtc */
1511         if (nv_crtc->head == 0) {
1512                 if (pNv->overlayAdaptor) {
1513                         regp->head |= NV_CRTC_FSEL_OVERLAY;
1514                 }
1515                 regp->head |= NV_CRTC_FSEL_I2C;
1516         }
1517
1518         /* This is not what nv does, but it is what the blob does (for nv4x at least) */
1519         /* This fixes my cursor corruption issue */
1520         regp->cursorConfig = 0x0;
1521         if(mode->Flags & V_DBLSCAN)
1522                 regp->cursorConfig |= (1 << 4);
1523         if (pNv->alphaCursor) {
1524                 /* bit28 means we go into alpha blend mode and not rely on the current ROP */
1525                 regp->cursorConfig |= 0x14011000;
1526         } else {
1527                 regp->cursorConfig |= 0x02000000;
1528         }
1529
1530         /* Unblock some timings */
1531         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1532         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1533
1534         /* What is the purpose of this register? */
1535         if (nv_crtc->head == 1) {
1536                 regp->CRTC[NV_VGA_CRTCX_26] = 0x14;
1537         } else {
1538                 regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1539         }
1540
1541         /* 0x00 is disabled, 0x22 crt and 0x88 dfp */
1542         /* 0x11 is LVDS? */
1543         if (is_fp) {
1544                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1545         } else {
1546                 /* 0x20 is also seen sometimes, why? */
1547                 if (nv_crtc->head == 1) {
1548                         regp->CRTC[NV_VGA_CRTCX_3B] = 0x24;
1549                 } else {
1550                         regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1551                 }
1552         }
1553
1554         /* These values seem to vary */
1555         if (nv_crtc->head == 1) {
1556                 regp->CRTC[NV_VGA_CRTCX_3C] = 0x0;
1557         } else {
1558                 regp->CRTC[NV_VGA_CRTCX_3C] = 0x70;
1559         }
1560
1561         /* 0x80 seems to be used very often, if not always */
1562         regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1563
1564         if (nv_crtc->head == 1) {
1565                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x0;
1566         } else {
1567                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x1;
1568         }
1569
1570         if (is_fp)
1571                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x80;
1572
1573         /* Are these(0x55 and 0x56) also timing related registers, since disabling them does nothing? */
1574         regp->CRTC[NV_VGA_CRTCX_55] = 0x0;
1575
1576         /* Common values like 0x14 and 0x04 are converted to 0x10 and 0x00 */
1577         regp->CRTC[NV_VGA_CRTCX_56] = 0x0;
1578
1579         /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1*/
1580         if (nv_crtc->head == 1) {
1581                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52;
1582         } else {
1583                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52 + 4;
1584         }
1585
1586         /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1587         regp->unk81c = nvReadCRTC0(pNv, NV_CRTC_081C);
1588
1589         regp->unk830 = mode->CrtcVDisplay - 3;
1590         regp->unk834 = mode->CrtcVDisplay - 1;
1591
1592         /* This is what the blob does */
1593         regp->unk850 = nvReadCRTC(pNv, 0, NV_CRTC_0850);
1594
1595         /* Never ever modify gpio, unless you know very well what you're doing */
1596         regp->gpio = nvReadCRTC(pNv, 0, NV_CRTC_GPIO);
1597
1598         /* Switch to non-vga mode (the so called HSYNC mode) */
1599         regp->config = 0x2;
1600
1601         /*
1602          * Calculate the state that is common to all crtc's (stored in the state struct).
1603          */
1604         ErrorF("crtc %d %d %d\n", nv_crtc->crtc, mode->CrtcHDisplay, pScrn->displayWidth);
1605         nv_crtc_calc_state_ext(crtc,
1606                                 i,
1607                                 pScrn->displayWidth,
1608                                 mode->CrtcHDisplay,
1609                                 mode->CrtcVDisplay,
1610                                 adjusted_mode->Clock,
1611                                 mode->Flags);
1612
1613         /* Enable slaved mode */
1614         if (is_fp) {
1615                 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1616         }
1617 }
1618
1619 static void
1620 nv_crtc_mode_set_ramdac_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1621 {
1622         ScrnInfoPtr pScrn = crtc->scrn;
1623         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1624         NVCrtcRegPtr regp;
1625         NVPtr pNv = NVPTR(pScrn);
1626         NVFBLayout *pLayout = &pNv->CurrentLayout;
1627         Bool is_fp = FALSE;
1628         Bool is_lvds = FALSE;
1629         float aspect_ratio, panel_ratio;
1630         uint32_t h_scale, v_scale;
1631
1632         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1633
1634         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1635         NVOutputPrivatePtr nv_output = NULL;
1636         if (output) {
1637                 nv_output = output->driver_private;
1638
1639                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1640                         is_fp = TRUE;
1641
1642                 if (nv_output->type == OUTPUT_LVDS)
1643                         is_lvds = TRUE;
1644         }
1645
1646         if (is_fp) {
1647                 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
1648                 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
1649                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HDisplay;
1650                 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
1651                 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
1652                 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
1653                 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
1654
1655                 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
1656                 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
1657                 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VDisplay;
1658                 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
1659                 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
1660                 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
1661                 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
1662
1663                 ErrorF("Horizontal:\n");
1664                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
1665                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
1666                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
1667                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
1668                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
1669                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
1670                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
1671
1672                 ErrorF("Vertical:\n");
1673                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
1674                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
1675                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
1676                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
1677                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
1678                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
1679                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
1680         }
1681
1682         /*
1683         * bit0: positive vsync
1684         * bit4: positive hsync
1685         * bit8: enable panel scaling
1686         * bit9: something related to dual link dvi?
1687         * bit26: a bit sometimes seen on some g70 cards
1688         * bit31: set for dual link LVDS
1689         * This must also be set for non-flatpanels
1690         * Some bits seem shifted for vga monitors
1691         */
1692
1693         if (is_fp) {
1694                 regp->fp_control = 0x11100000;
1695         } else {
1696                 regp->fp_control = 0x21100000;
1697         }
1698
1699         if (is_lvds && pNv->VBIOS.fp.dual_link)
1700                 regp->fp_control |= 0x80000000;
1701         else {
1702                 /* If the special bit exists, it exists on both ramdac's */
1703                 regp->fp_control |= nvReadRAMDAC0(pNv, NV_RAMDAC_FP_CONTROL) & (1 << 26);
1704         }
1705
1706         /* Does this turn something off, since it's similar to what is used in dpms (being a "2" bit)? */
1707         if (is_fp && !is_lvds && pNv->dcb_table.entry[nv_output->dcb_entry].duallink_possible)
1708                 regp->fp_control |= (1 << 9);
1709
1710         /* Deal with vsync/hsync polarity */
1711         /* These analog monitor offsets are guesswork */
1712         if (adjusted_mode->Flags & V_PVSYNC) {
1713                 regp->fp_control |= (1 << (0 + !is_fp));
1714         }
1715
1716         if (adjusted_mode->Flags & V_PHSYNC) {
1717                 regp->fp_control |= (1 << (4 + !is_fp));
1718         }
1719
1720         if (is_fp) {
1721                 ErrorF("Pre-panel scaling\n");
1722                 ErrorF("panel-size:%dx%d\n", nv_output->fpWidth, nv_output->fpHeight);
1723                 panel_ratio = (nv_output->fpWidth)/(float)(nv_output->fpHeight);
1724                 ErrorF("panel_ratio=%f\n", panel_ratio);
1725                 aspect_ratio = (mode->HDisplay)/(float)(mode->VDisplay);
1726                 ErrorF("aspect_ratio=%f\n", aspect_ratio);
1727                 /* Scale factors is the so called 20.12 format, taken from Haiku */
1728                 h_scale = ((1 << 12) * mode->HDisplay)/nv_output->fpWidth;
1729                 v_scale = ((1 << 12) * mode->VDisplay)/nv_output->fpHeight;
1730                 ErrorF("h_scale=%d\n", h_scale);
1731                 ErrorF("v_scale=%d\n", v_scale);
1732
1733                 /* Don't limit last fetched line */
1734                 regp->debug_2 = 0;
1735
1736                 /* We want automatic scaling */
1737                 regp->debug_1 = 0;
1738
1739                 regp->fp_hvalid_start = 0;
1740                 regp->fp_hvalid_end = (nv_output->fpWidth - 1);
1741
1742                 regp->fp_vvalid_start = 0;
1743                 regp->fp_vvalid_end = (nv_output->fpHeight - 1);
1744
1745                 /* 0 = panel scaling */
1746                 if (nv_output->scaling_mode == 0) {
1747                         ErrorF("Flat panel is doing the scaling.\n");
1748                         regp->fp_control |= (1 << 8);
1749                 } else {
1750                         ErrorF("GPU is doing the scaling.\n");
1751
1752                         /* 1 = fullscale gpu */
1753                         /* 2 = aspect ratio scaling */
1754                         if (nv_output->scaling_mode == 2) {
1755                                 /* GPU scaling happens automaticly at a ratio of 1.33 */
1756                                 /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
1757                                 if (h_scale != (1 << 12) && (panel_ratio > (aspect_ratio + 0.10))) {
1758                                         uint32_t diff;
1759
1760                                         ErrorF("Scaling resolution on a widescreen panel\n");
1761
1762                                         /* Scaling in both directions needs to the same */
1763                                         h_scale = v_scale;
1764
1765                                         /* Set a new horizontal scale factor and enable testmode (bit12) */
1766                                         regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
1767
1768                                         diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
1769                                         regp->fp_hvalid_start = diff/2;
1770                                         regp->fp_hvalid_end = nv_output->fpWidth - (diff/2) - 1;
1771                                 }
1772
1773                                 /* Same scaling, just for panels with aspect ratio's smaller than 1 */
1774                                 if (v_scale != (1 << 12) && (panel_ratio < (aspect_ratio - 0.10))) {
1775                                         uint32_t diff;
1776
1777                                         ErrorF("Scaling resolution on a portrait panel\n");
1778
1779                                         /* Scaling in both directions needs to the same */
1780                                         v_scale = h_scale;
1781
1782                                         /* Set a new vertical scale factor and enable testmode (bit28) */
1783                                         regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
1784
1785                                         diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
1786                                         regp->fp_vvalid_start = diff/2;
1787                                         regp->fp_vvalid_end = nv_output->fpHeight - (diff/2) - 1;
1788                                 }
1789                         }
1790                 }
1791
1792                 ErrorF("Post-panel scaling\n");
1793         }
1794
1795         if (pNv->Architecture >= NV_ARCH_10) {
1796                 /* Bios and blob don't seem to do anything (else) */
1797                 regp->nv10_cursync = (1<<25);
1798         }
1799
1800         /* These are the common blob values, minus a few fp specific bit's */
1801         /* Let's keep the TMDS pll and fpclock running in all situations */
1802         regp->debug_0 = 0x1101111;
1803
1804         if(is_fp) {
1805                 /* I am not completely certain, but seems to be set only for dfp's */
1806                 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED;
1807         }
1808
1809         if (output)
1810                 ErrorF("output %d debug_0 %08X\n", nv_output->preferred_output, regp->debug_0);
1811
1812         /* Flatpanel support needs at least a NV10 */
1813         if(pNv->twoHeads) {
1814                 /* Instead of 1, several other values are also used: 2, 7, 9 */
1815                 /* The purpose is unknown */
1816                 if(pNv->FPDither) {
1817                         regp->dither = 0x00010000;
1818                 }
1819         }
1820
1821         /* Kindly borrowed from haiku driver */
1822         /* bit4 and bit5 activate indirect mode trough color palette */
1823         switch (pLayout->depth) {
1824                 case 32:
1825                 case 16:
1826                         regp->general = 0x00101130;
1827                         break;
1828                 case 24:
1829                 case 15:
1830                         regp->general = 0x00100130;
1831                         break;
1832                 case 8:
1833                 default:
1834                         regp->general = 0x00101100;
1835                         break;
1836         }
1837
1838         if (pNv->alphaCursor) {
1839                 regp->general |= (1<<29);
1840         }
1841
1842         /* Some values the blob sets */
1843         /* This may apply to the real ramdac that is being used (for crosswired situations) */
1844         /* Nevertheless, it's unlikely to cause many problems, since the values are equal for both */
1845         regp->unk_a20 = 0x0;
1846         regp->unk_a24 = 0xfffff;
1847         regp->unk_a34 = 0x1;
1848 }
1849
1850 /**
1851  * Sets up registers for the given mode/adjusted_mode pair.
1852  *
1853  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1854  *
1855  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1856  * be easily turned on/off after this.
1857  */
1858 static void
1859 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
1860                  DisplayModePtr adjusted_mode,
1861                  int x, int y)
1862 {
1863         ScrnInfoPtr pScrn = crtc->scrn;
1864         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1865         NVPtr pNv = NVPTR(pScrn);
1866
1867         ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->crtc);
1868
1869         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->crtc);
1870         xf86PrintModeline(pScrn->scrnIndex, mode);
1871         NVCrtcSetOwner(crtc);
1872
1873         nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
1874         nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
1875         nv_crtc_mode_set_ramdac_regs(crtc, mode, adjusted_mode);
1876
1877         /* Just in case */
1878         NVCrtcLockUnlock(crtc, FALSE);
1879
1880         NVVgaProtect(crtc, TRUE);
1881         nv_crtc_load_state_ext(crtc, &pNv->ModeReg, FALSE);
1882         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
1883         if (pNv->Architecture == NV_ARCH_40) {
1884                 nv40_crtc_load_state_pll(pNv, &pNv->ModeReg);
1885         } else {
1886                 nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
1887         }
1888         nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
1889
1890         NVVgaProtect(crtc, FALSE);
1891
1892         NVCrtcSetBase(crtc, x, y);
1893
1894 #if X_BYTE_ORDER == X_BIG_ENDIAN
1895         /* turn on LFB swapping */
1896         {
1897                 unsigned char tmp;
1898
1899                 tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
1900                 tmp |= (1 << 7);
1901                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
1902         }
1903 #endif
1904 }
1905
1906 void nv_crtc_save(xf86CrtcPtr crtc)
1907 {
1908         ScrnInfoPtr pScrn = crtc->scrn;
1909         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1910         NVPtr pNv = NVPTR(pScrn);
1911
1912         ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->crtc);
1913
1914         /* We just came back from terminal, so unlock */
1915         NVCrtcLockUnlock(crtc, FALSE);
1916
1917         NVCrtcSetOwner(crtc);
1918         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
1919         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
1920         if (pNv->Architecture == NV_ARCH_40) {
1921                 nv40_crtc_save_state_pll(pNv, &pNv->SavedReg);
1922         } else {
1923                 nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
1924         }
1925         nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
1926 }
1927
1928 void nv_crtc_restore(xf86CrtcPtr crtc)
1929 {
1930         ScrnInfoPtr pScrn = crtc->scrn;
1931         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1932         NVPtr pNv = NVPTR(pScrn);
1933         RIVA_HW_STATE *state;
1934         NVOutputRegPtr regp;
1935
1936         state = &pNv->SavedReg;
1937
1938         /* Some aspects of an output needs to be restore before the crtc. */
1939         /* In my case this has to do with the mode that i get at very low resolutions. */
1940         /* If i do this at the end, it will not be restored properly */
1941         /* Assumption: crtc0 is restored first. */
1942         if (nv_crtc->head == 0) {
1943                 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
1944                 int i;
1945                 ErrorF("Restore all TMDS timings, before restoring anything else\n");
1946                 for (i = 0; i < config->num_output; i++) {
1947                         NVOutputPrivatePtr nv_output2 = config->output[i]->driver_private;
1948                         regp = &state->dac_reg[nv_output2->preferred_output];
1949                         Bool crosswired = regp->TMDS[0x4] & (1 << 3);
1950                         /* Let's guess the bios state ;-) */
1951                         if (nv_output2->type == OUTPUT_TMDS) {
1952                                 uint32_t clock = nv_calc_tmds_clock_from_pll(config->output[i]);
1953                                 nv_set_tmds_registers(config->output[i], clock, TRUE, crosswired);
1954                         }
1955                         if (nv_output2->type == OUTPUT_TMDS || nv_output2->type == OUTPUT_LVDS)
1956                                 link_head_and_output(pScrn, -1, nv_output2->dcb_entry, crosswired);
1957                 }
1958         }
1959
1960         ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->crtc);
1961
1962         NVCrtcSetOwner(crtc);
1963
1964         /* Just to be safe */
1965         NVCrtcLockUnlock(crtc, FALSE);
1966
1967         NVVgaProtect(crtc, TRUE);
1968         nv_crtc_load_state_ext(crtc, &pNv->SavedReg, TRUE);
1969         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
1970         if (pNv->Architecture == NV_ARCH_40) {
1971                 nv40_crtc_load_state_pll(pNv, &pNv->SavedReg);
1972         } else {
1973                 nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
1974         }
1975         nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
1976         nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->vtOWNER);
1977         NVVgaProtect(crtc, FALSE);
1978
1979         /* We must lock the door if we leave ;-) */
1980         NVCrtcLockUnlock(crtc, TRUE);
1981 }
1982
1983 void nv_crtc_prepare(xf86CrtcPtr crtc)
1984 {
1985         ScrnInfoPtr pScrn = crtc->scrn;
1986         NVPtr pNv = NVPTR(pScrn);
1987         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1988
1989         ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->crtc);
1990
1991         crtc->funcs->dpms(crtc, DPMSModeOff);
1992
1993         /* Sync the engine before adjust mode */
1994         if (pNv->EXADriverPtr) {
1995                 exaMarkSync(pScrn->pScreen);
1996                 exaWaitSync(pScrn->pScreen);
1997         }
1998 }
1999
2000 void nv_crtc_commit(xf86CrtcPtr crtc)
2001 {
2002         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2003         ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->crtc);
2004
2005         crtc->funcs->dpms (crtc, DPMSModeOn);
2006
2007         if (crtc->scrn->pScreen != NULL)
2008                 xf86_reload_cursors (crtc->scrn->pScreen);
2009 }
2010
2011 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
2012 {
2013         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2014         ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->crtc);
2015
2016         return FALSE;
2017 }
2018
2019 static void nv_crtc_unlock(xf86CrtcPtr crtc)
2020 {
2021         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2022         ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->crtc);
2023 }
2024
2025 static void
2026 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
2027                                         int size)
2028 {
2029         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2030         ScrnInfoPtr pScrn = crtc->scrn;
2031         NVPtr pNv = NVPTR(pScrn);
2032         int i, j;
2033
2034         NVCrtcRegPtr regp;
2035         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2036
2037         switch (pNv->CurrentLayout.depth) {
2038         case 15:
2039                 /* R5G5B5 */
2040                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
2041                 for (i = 0; i < 32; i++) {
2042                         for (j = 0; j < 8; j++) {
2043                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2044                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
2045                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2046                         }
2047                 }
2048                 break;
2049         case 16:
2050                 /* R5G6B5 */
2051                 /* First deal with the 5 bit colors */
2052                 for (i = 0; i < 32; i++) {
2053                         for (j = 0; j < 8; j++) {
2054                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2055                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2056                         }
2057                 }
2058                 /* Now deal with the 6 bit color */
2059                 for (i = 0; i < 64; i++) {
2060                         for (j = 0; j < 4; j++) {
2061                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
2062                         }
2063                 }
2064                 break;
2065         default:
2066                 /* R8G8B8 */
2067                 for (i = 0; i < 256; i++) {
2068                         regp->DAC[i * 3] = red[i] >> 8;
2069                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
2070                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
2071                 }
2072                 break;
2073         }
2074
2075         NVCrtcLoadPalette(crtc);
2076 }
2077
2078 /* NV04-NV10 doesn't support alpha cursors */
2079 static const xf86CrtcFuncsRec nv_crtc_funcs = {
2080         .dpms = nv_crtc_dpms,
2081         .save = nv_crtc_save, /* XXX */
2082         .restore = nv_crtc_restore, /* XXX */
2083         .mode_fixup = nv_crtc_mode_fixup,
2084         .mode_set = nv_crtc_mode_set,
2085         .prepare = nv_crtc_prepare,
2086         .commit = nv_crtc_commit,
2087         .destroy = NULL, /* XXX */
2088         .lock = nv_crtc_lock,
2089         .unlock = nv_crtc_unlock,
2090         .set_cursor_colors = nv_crtc_set_cursor_colors,
2091         .set_cursor_position = nv_crtc_set_cursor_position,
2092         .show_cursor = nv_crtc_show_cursor,
2093         .hide_cursor = nv_crtc_hide_cursor,
2094         .load_cursor_image = nv_crtc_load_cursor_image,
2095         .gamma_set = nv_crtc_gamma_set,
2096 };
2097
2098 /* NV11 and up has support for alpha cursors. */
2099 /* Due to different maximum sizes we cannot allow it to use normal cursors */
2100 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
2101         .dpms = nv_crtc_dpms,
2102         .save = nv_crtc_save, /* XXX */
2103         .restore = nv_crtc_restore, /* XXX */
2104         .mode_fixup = nv_crtc_mode_fixup,
2105         .mode_set = nv_crtc_mode_set,
2106         .prepare = nv_crtc_prepare,
2107         .commit = nv_crtc_commit,
2108         .destroy = NULL, /* XXX */
2109         .lock = nv_crtc_lock,
2110         .unlock = nv_crtc_unlock,
2111         .set_cursor_colors = NULL, /* Alpha cursors do not need this */
2112         .set_cursor_position = nv_crtc_set_cursor_position,
2113         .show_cursor = nv_crtc_show_cursor,
2114         .hide_cursor = nv_crtc_hide_cursor,
2115         .load_cursor_argb = nv_crtc_load_cursor_argb,
2116         .gamma_set = nv_crtc_gamma_set,
2117 };
2118
2119
2120 void
2121 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
2122 {
2123         NVPtr pNv = NVPTR(pScrn);
2124         xf86CrtcPtr crtc;
2125         NVCrtcPrivatePtr nv_crtc;
2126
2127         if (pNv->NVArch >= 0x11) {
2128                 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
2129         } else {
2130                 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
2131         }
2132         if (crtc == NULL)
2133                 return;
2134
2135         nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
2136         nv_crtc->crtc = crtc_num;
2137         nv_crtc->head = crtc_num;
2138
2139         crtc->driver_private = nv_crtc;
2140
2141         NVCrtcLockUnlock(crtc, FALSE);
2142 }
2143
2144 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2145 {
2146     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2147     int i;
2148     NVCrtcRegPtr regp;
2149
2150     regp = &state->crtc_reg[nv_crtc->head];
2151
2152     NVWriteMiscOut(crtc, regp->MiscOutReg);
2153
2154     for (i = 1; i < 5; i++)
2155       NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
2156
2157     /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
2158     NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
2159
2160     for (i = 0; i < 25; i++)
2161       NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
2162
2163     for (i = 0; i < 9; i++)
2164       NVWriteVgaGr(crtc, i, regp->Graphics[i]);
2165
2166     NVEnablePalette(crtc);
2167     for (i = 0; i < 21; i++)
2168       NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
2169     NVDisablePalette(crtc);
2170
2171 }
2172
2173 static void nv_crtc_fix_nv40_hw_cursor(xf86CrtcPtr crtc)
2174 {
2175         /* TODO - implement this properly */
2176         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2177         ScrnInfoPtr pScrn = crtc->scrn;
2178         NVPtr pNv = NVPTR(pScrn);
2179
2180         if (pNv->Architecture == NV_ARCH_40) {  /* HW bug */
2181                 volatile CARD32 curpos = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS);
2182                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS, curpos);
2183         }
2184 }
2185 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override)
2186 {
2187     ScrnInfoPtr pScrn = crtc->scrn;
2188     NVPtr pNv = NVPTR(pScrn);
2189     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2190     NVCrtcRegPtr regp;
2191     int i;
2192
2193     regp = &state->crtc_reg[nv_crtc->head];
2194
2195     if(pNv->Architecture >= NV_ARCH_10) {
2196         if(pNv->twoHeads) {
2197            nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL, regp->head);
2198         }
2199         nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
2200         nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
2201         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
2202         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
2203         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2204         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2205         nvWriteMC(pNv, 0x1588, 0);
2206
2207         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
2208         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
2209         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO, regp->gpio);
2210         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0830, regp->unk830);
2211         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0834, regp->unk834);
2212         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0850, regp->unk850);
2213         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_081C, regp->unk81c);
2214
2215         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG, regp->config);
2216
2217         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
2218         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
2219
2220         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
2221         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
2222         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3C, regp->CRTC[NV_VGA_CRTCX_3C]);
2223         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
2224         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_4B, regp->CRTC[NV_VGA_CRTCX_4B]);
2225         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
2226         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_56, regp->CRTC[NV_VGA_CRTCX_56]);
2227         if (override) {
2228                 for (i = 0; i < 0x10; i++)
2229                         NVWriteVGACR5758(pNv, nv_crtc->head, i, regp->CR58[i]);
2230         }
2231         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
2232         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
2233     }
2234
2235     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
2236     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
2237     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
2238     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
2239     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
2240     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
2241     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
2242     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
2243     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
2244     if(pNv->Architecture >= NV_ARCH_30) {
2245       NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
2246     }
2247
2248     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
2249     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
2250     nv_crtc_fix_nv40_hw_cursor(crtc);
2251     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
2252     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
2253
2254     nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_EN_0, 0);
2255     nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
2256
2257     pNv->CurrentState = state;
2258 }
2259
2260 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2261 {
2262     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2263     int i;
2264     NVCrtcRegPtr regp;
2265
2266     regp = &state->crtc_reg[nv_crtc->head];
2267
2268     regp->MiscOutReg = NVReadMiscOut(crtc);
2269
2270     for (i = 0; i < 25; i++)
2271         regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
2272
2273     NVEnablePalette(crtc);
2274     for (i = 0; i < 21; i++)
2275         regp->Attribute[i] = NVReadVgaAttr(crtc, i);
2276     NVDisablePalette(crtc);
2277
2278     for (i = 0; i < 9; i++)
2279         regp->Graphics[i] = NVReadVgaGr(crtc, i);
2280
2281     for (i = 1; i < 5; i++)
2282         regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
2283
2284 }
2285
2286 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2287 {
2288     ScrnInfoPtr pScrn = crtc->scrn;
2289     NVPtr pNv = NVPTR(pScrn);
2290     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2291     NVCrtcRegPtr regp;
2292     int i;
2293
2294     regp = &state->crtc_reg[nv_crtc->head];
2295
2296     regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
2297     regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
2298     regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
2299     regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
2300     regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
2301     regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
2302     regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
2303
2304     regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
2305     regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
2306     if(pNv->Architecture >= NV_ARCH_30) {
2307          regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
2308     }
2309     regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
2310     regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
2311     regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
2312     regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
2313
2314     regp->gpio = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO);
2315     regp->unk830 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0830);
2316     regp->unk834 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0834);
2317     regp->unk850 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0850);
2318     regp->unk81c = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_081C);
2319
2320         regp->config = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG);
2321
2322     if(pNv->Architecture >= NV_ARCH_10) {
2323         if(pNv->twoHeads) {
2324            regp->head     = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL);
2325            regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
2326         }
2327         regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
2328
2329         regp->cursorConfig = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG);
2330
2331         regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
2332         regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
2333         regp->CRTC[NV_VGA_CRTCX_3C] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3C);
2334         regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
2335         regp->CRTC[NV_VGA_CRTCX_4B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_4B);
2336         regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
2337         regp->CRTC[NV_VGA_CRTCX_56] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_56);
2338         for (i = 0; i < 0x10; i++)
2339                 regp->CR58[i] = NVReadVGACR5758(pNv, nv_crtc->head, i);
2340         regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
2341         regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
2342         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
2343         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
2344     }
2345 }
2346
2347 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2348 {
2349         ScrnInfoPtr pScrn = crtc->scrn;
2350         NVPtr pNv = NVPTR(pScrn);
2351         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2352         NVCrtcRegPtr regp;
2353         int i;
2354
2355         regp = &state->crtc_reg[nv_crtc->head];
2356
2357         regp->general = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL);
2358
2359         regp->fp_control        = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL);
2360         regp->debug_0   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0);
2361         regp->debug_1   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1);
2362         regp->debug_2   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2);
2363
2364         regp->unk_a20 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20);
2365         regp->unk_a24 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24);
2366         regp->unk_a34 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34);
2367
2368         if (pNv->NVArch == 0x11) {
2369                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11);
2370         } else if (pNv->twoHeads) {
2371                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER);
2372         }
2373         regp->nv10_cursync = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC);
2374
2375         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2376
2377         for (i = 0; i < 7; i++) {
2378                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2379                 regp->fp_horiz_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2380         }
2381
2382         for (i = 0; i < 7; i++) {
2383                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2384                 regp->fp_vert_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2385         }
2386
2387         regp->fp_hvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START);
2388         regp->fp_hvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END);
2389         regp->fp_vvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START);
2390         regp->fp_vvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END);
2391 }
2392
2393 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2394 {
2395         ScrnInfoPtr pScrn = crtc->scrn;
2396         NVPtr pNv = NVPTR(pScrn);
2397         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2398         NVCrtcRegPtr regp;
2399         int i;
2400
2401         regp = &state->crtc_reg[nv_crtc->head];
2402
2403         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL, regp->general);
2404
2405         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control);
2406         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0, regp->debug_0);
2407         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
2408         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
2409
2410         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20, regp->unk_a20);
2411         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24, regp->unk_a24);
2412         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34, regp->unk_a34);
2413
2414         if (pNv->NVArch == 0x11) {
2415                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11, regp->dither);
2416         } else if (pNv->twoHeads) {
2417                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER, regp->dither);
2418         }
2419         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
2420
2421         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2422
2423         for (i = 0; i < 7; i++) {
2424                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2425                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_horiz_regs[i]);
2426         }
2427
2428         for (i = 0; i < 7; i++) {
2429                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2430                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_vert_regs[i]);
2431         }
2432
2433         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START, regp->fp_hvalid_start);
2434         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END, regp->fp_hvalid_end);
2435         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START, regp->fp_vvalid_start);
2436         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END, regp->fp_vvalid_end);
2437 }
2438
2439 void
2440 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y)
2441 {
2442         ScrnInfoPtr pScrn = crtc->scrn;
2443         NVPtr pNv = NVPTR(pScrn);
2444         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2445         NVFBLayout *pLayout = &pNv->CurrentLayout;
2446         CARD32 start = 0;
2447
2448         ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
2449
2450         start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
2451         start += pNv->FB->offset;
2452
2453         /* 30 bits addresses in 32 bits according to haiku */
2454         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_START, start & 0xfffffffc);
2455
2456         /* set NV4/NV10 byte adress: (bit0 - 1) */
2457         NVWriteVgaAttr(crtc, 0x13, (start & 0x3) << 1);
2458
2459         crtc->x = x;
2460         crtc->y = y;
2461 }
2462
2463 static void NVCrtcWriteDacMask(xf86CrtcPtr crtc, CARD8 value)
2464 {
2465   ScrnInfoPtr pScrn = crtc->scrn;
2466   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2467   NVPtr pNv = NVPTR(pScrn);
2468   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2469
2470   NV_WR08(pDACReg, VGA_DAC_MASK, value);
2471 }
2472
2473 static CARD8 NVCrtcReadDacMask(xf86CrtcPtr crtc)
2474 {
2475   ScrnInfoPtr pScrn = crtc->scrn;
2476   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2477   NVPtr pNv = NVPTR(pScrn);
2478   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2479
2480   return NV_RD08(pDACReg, VGA_DAC_MASK);
2481 }
2482
2483 static void NVCrtcWriteDacReadAddr(xf86CrtcPtr crtc, CARD8 value)
2484 {
2485   ScrnInfoPtr pScrn = crtc->scrn;
2486   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2487   NVPtr pNv = NVPTR(pScrn);
2488   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2489
2490   NV_WR08(pDACReg, VGA_DAC_READ_ADDR, value);
2491 }
2492
2493 static void NVCrtcWriteDacWriteAddr(xf86CrtcPtr crtc, CARD8 value)
2494 {
2495   ScrnInfoPtr pScrn = crtc->scrn;
2496   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2497   NVPtr pNv = NVPTR(pScrn);
2498   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2499
2500   NV_WR08(pDACReg, VGA_DAC_WRITE_ADDR, value);
2501 }
2502
2503 static void NVCrtcWriteDacData(xf86CrtcPtr crtc, CARD8 value)
2504 {
2505   ScrnInfoPtr pScrn = crtc->scrn;
2506   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2507   NVPtr pNv = NVPTR(pScrn);
2508   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2509
2510   NV_WR08(pDACReg, VGA_DAC_DATA, value);
2511 }
2512
2513 static CARD8 NVCrtcReadDacData(xf86CrtcPtr crtc, CARD8 value)
2514 {
2515   ScrnInfoPtr pScrn = crtc->scrn;
2516   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2517   NVPtr pNv = NVPTR(pScrn);
2518   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2519
2520   return NV_RD08(pDACReg, VGA_DAC_DATA);
2521 }
2522
2523 void NVCrtcLoadPalette(xf86CrtcPtr crtc)
2524 {
2525         int i;
2526         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2527         NVCrtcRegPtr regp;
2528         ScrnInfoPtr pScrn = crtc->scrn;
2529         NVPtr pNv = NVPTR(pScrn);
2530
2531         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2532
2533         NVCrtcSetOwner(crtc);
2534         NVCrtcWriteDacMask(crtc, 0xff);
2535         NVCrtcWriteDacWriteAddr(crtc, 0x00);
2536
2537         for (i = 0; i<768; i++) {
2538                 NVCrtcWriteDacData(crtc, regp->DAC[i]);
2539         }
2540         NVDisablePalette(crtc);
2541 }
2542
2543 void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
2544 {
2545         unsigned char scrn;
2546
2547         NVCrtcSetOwner(crtc);
2548
2549         scrn = NVReadVgaSeq(crtc, 0x01);
2550         if (on) {
2551                 scrn &= ~0x20;
2552         } else {
2553                 scrn |= 0x20;
2554         }
2555
2556         NVVgaSeqReset(crtc, TRUE);
2557         NVWriteVgaSeq(crtc, 0x01, scrn);
2558         NVVgaSeqReset(crtc, FALSE);
2559 }
2560
2561 /*************************************************************************** \
2562 |*                                                                           *|
2563 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
2564 |*                                                                           *|
2565 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
2566 |*     international laws.  Users and possessors of this source code are     *|
2567 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
2568 |*     use this code in individual and commercial software.                  *|
2569 |*                                                                           *|
2570 |*     Any use of this source code must include,  in the user documenta-     *|
2571 |*     tion and  internal comments to the code,  notices to the end user     *|
2572 |*     as follows:                                                           *|
2573 |*                                                                           *|
2574 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
2575 |*                                                                           *|
2576 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
2577 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
2578 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
2579 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
2580 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
2581 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
2582 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
2583 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
2584 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
2585 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
2586 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
2587 |*                                                                           *|
2588 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
2589 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
2590 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
2591 |*     computer  software  documentation,"  as such  terms  are  used in     *|
2592 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
2593 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
2594 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
2595 |*     all U.S. Government End Users  acquire the source code  with only     *|
2596 |*     those rights set forth herein.                                        *|
2597 |*                                                                           *|
2598  \***************************************************************************/