1 /***************************************************************************\
3 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
5 |* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6 |* international laws. Users and possessors of this source code are *|
7 |* hereby granted a nonexclusive, royalty-free copyright license to *|
8 |* use this code in individual and commercial software. *|
10 |* Any use of this source code must include, in the user documenta- *|
11 |* tion and internal comments to the code, notices to the end user *|
14 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
16 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19 |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21 |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
24 |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25 |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26 |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
28 |* U.S. Government End Users. This source code is a "commercial *|
29 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30 |* consisting of "commercial computer software" and "commercial *|
31 |* computer software documentation," as such terms are used in *|
32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33 |* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35 |* all U.S. Government End Users acquire the source code with only *|
36 |* those rights set forth herein. *|
38 \***************************************************************************/
39 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_hw.c,v 1.21 2006/06/16 00:19:33 mvojkovi Exp $ */
41 #include "nv_include.h"
45 uint8_t NVReadVGA0(NVPtr pNv, uint8_t index)
47 volatile const uint8_t *ptr = pNv->PCIO0;
48 VGA_WR08(ptr, 0x03D4, index);
49 return VGA_RD08(ptr, 0x03D5);
52 void NVWriteVGA0(NVPtr pNv, uint8_t index, uint8_t data)
54 volatile const uint8_t *ptr = pNv->PCIO0;
55 VGA_WR08(ptr, 0x03D4, index);
56 VGA_WR08(ptr, 0x03D5, data);
59 uint8_t NVReadVGA1(NVPtr pNv, uint8_t index)
61 volatile const uint8_t *ptr = pNv->PCIO1;
62 VGA_WR08(ptr, 0x03D4, index);
63 return VGA_RD08(ptr, 0x03D5);
66 void NVWriteVGA1(NVPtr pNv, uint8_t index, uint8_t data)
68 volatile const uint8_t *ptr = pNv->PCIO1;
69 VGA_WR08(ptr, 0x03D4, index);
70 VGA_WR08(ptr, 0x03D5, data);
73 uint8_t nvReadVGA(NVPtr pNv, uint8_t index)
75 volatile const uint8_t *ptr = pNv->cur_head ? pNv->PCIO1 : pNv->PCIO0;
76 VGA_WR08(ptr, 0x03D4, index);
77 return VGA_RD08(ptr, 0x03D5);
80 void nvWriteVGA(NVPtr pNv, uint8_t index, uint8_t data)
82 volatile const uint8_t *ptr = pNv->cur_head ? pNv->PCIO1 : pNv->PCIO0;
83 VGA_WR08(ptr, 0x03D4, index);
84 VGA_WR08(ptr, 0x03D5, data);
87 CARD32 nvReadRAMDAC(NVPtr pNv, uint8_t head, uint32_t ramdac_reg)
89 volatile const void *ptr = head ? pNv->PRAMDAC1 : pNv->PRAMDAC0;
90 return MMIO_IN32(ptr, ramdac_reg);
93 void nvWriteRAMDAC(NVPtr pNv, uint8_t head, uint32_t ramdac_reg, CARD32 val)
95 volatile const void *ptr = head ? pNv->PRAMDAC1 : pNv->PRAMDAC0;
96 MMIO_OUT32(ptr, ramdac_reg, val);
99 CARD32 nvReadCRTC(NVPtr pNv, uint8_t head, uint32_t reg)
101 volatile const void *ptr = head ? pNv->PCRTC1 : pNv->PCRTC0;
102 return MMIO_IN32(ptr, reg);
105 void nvWriteCRTC(NVPtr pNv, uint8_t head, uint32_t reg, CARD32 val)
107 volatile const void *ptr = head ? pNv->PCRTC1 : pNv->PCRTC0;
108 MMIO_OUT32(ptr, reg, val);
118 nvWriteVGA(pNv, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57 );
120 cr11 = nvReadVGA(pNv, NV_VGA_CRTCX_VSYNCE);
121 if(Lock) cr11 |= 0x80;
123 nvWriteVGA(pNv, NV_VGA_CRTCX_VSYNCE, cr11);
126 int NVShowHideCursor (
131 int current = pNv->CurrentState->cursor1;
133 pNv->CurrentState->cursor1 = (pNv->CurrentState->cursor1 & 0xFE) |
136 nvWriteVGA(pNv, NV_VGA_CRTCX_CURCTL1, pNv->CurrentState->cursor1);
138 if(pNv->Architecture == NV_ARCH_40) { /* HW bug */
139 volatile CARD32 curpos = nvReadCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS);
140 nvWriteCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS, curpos);
143 return (current & 0x01);
146 /****************************************************************************\
148 * The video arbitration routines calculate some "magic" numbers. Fixes *
149 * the snow seen when accessing the framebuffer without it. *
150 * It just works (I hope). *
152 \****************************************************************************/
157 int graphics_burst_size;
158 int video_burst_size;
179 int graphics_burst_size;
180 int video_burst_size;
200 static void nvGetClocks(NVPtr pNv, unsigned int *MClk, unsigned int *NVClk)
202 unsigned int pll, N, M, MB, NB, P;
204 if(pNv->Architecture >= NV_ARCH_40) {
205 pll = nvReadMC(pNv, 0x4020);
206 P = (pll >> 16) & 0x07;
207 pll = nvReadMC(pNv, 0x4024);
209 N = (pll >> 8) & 0xFF;
210 if(((pNv->Chipset & 0xfff0) == CHIPSET_G71) ||
211 ((pNv->Chipset & 0xfff0) == CHIPSET_G73))
216 MB = (pll >> 16) & 0xFF;
217 NB = (pll >> 24) & 0xFF;
219 *MClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
221 pll = nvReadMC(pNv, 0x4000);
222 P = (pll >> 16) & 0x07;
223 pll = nvReadMC(pNv, 0x4004);
225 N = (pll >> 8) & 0xFF;
226 MB = (pll >> 16) & 0xFF;
227 NB = (pll >> 24) & 0xFF;
229 *NVClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
231 if(pNv->twoStagePLL) {
232 pll = nvReadRAMDAC0(pNv, NV_RAMDAC_MPLL);
234 N = (pll >> 8) & 0xFF;
235 P = (pll >> 16) & 0x0F;
236 pll = nvReadRAMDAC0(pNv, NV_RAMDAC_MPLL_B);
237 if(pll & 0x80000000) {
239 NB = (pll >> 8) & 0xFF;
244 *MClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
246 pll = nvReadRAMDAC0(pNv, NV_RAMDAC_NVPLL);
248 N = (pll >> 8) & 0xFF;
249 P = (pll >> 16) & 0x0F;
250 pll = nvReadRAMDAC0(pNv, NV_RAMDAC_NVPLL_B);
251 if(pll & 0x80000000) {
253 NB = (pll >> 8) & 0xFF;
258 *NVClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
260 if(((pNv->Chipset & 0x0ff0) == CHIPSET_NV30) ||
261 ((pNv->Chipset & 0x0ff0) == CHIPSET_NV35))
263 pll = nvReadRAMDAC0(pNv, NV_RAMDAC_MPLL);
265 N = (pll >> 8) & 0xFF;
266 P = (pll >> 16) & 0x07;
267 if(pll & 0x00000080) {
268 MB = (pll >> 4) & 0x07;
269 NB = (pll >> 19) & 0x1f;
274 *MClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
276 pll = nvReadRAMDAC0(pNv, NV_RAMDAC_NVPLL);
278 N = (pll >> 8) & 0xFF;
279 P = (pll >> 16) & 0x07;
280 if(pll & 0x00000080) {
281 MB = (pll >> 4) & 0x07;
282 NB = (pll >> 19) & 0x1f;
287 *NVClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
289 pll = nvReadRAMDAC0(pNv, NV_RAMDAC_MPLL);
291 N = (pll >> 8) & 0xFF;
292 P = (pll >> 16) & 0x0F;
293 *MClk = (N * pNv->CrystalFreqKHz / M) >> P;
295 pll = nvReadRAMDAC0(pNv, NV_RAMDAC_NVPLL);
297 N = (pll >> 8) & 0xFF;
298 P = (pll >> 16) & 0x0F;
299 *NVClk = (N * pNv->CrystalFreqKHz / M) >> P;
303 ErrorF("NVClock = %i MHz, MEMClock = %i MHz\n", *NVClk/1000, *MClk/1000);
308 void nv4CalcArbitration (
313 int data, pagemiss, cas,width, video_enable, bpp;
314 int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
315 int found, mclk_extra, mclk_loop, cbs, m1, p1;
316 int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
317 int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate;
318 int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt,clwm;
321 pclk_freq = arb->pclk_khz;
322 mclk_freq = arb->mclk_khz;
323 nvclk_freq = arb->nvclk_khz;
324 pagemiss = arb->mem_page_miss;
325 cas = arb->mem_latency;
326 width = arb->memory_width >> 6;
327 video_enable = arb->enable_video;
329 mp_enable = arb->enable_mp;
360 mclk_loop = mclks+mclk_extra;
361 us_m = mclk_loop *1000*1000 / mclk_freq;
362 us_n = nvclks*1000*1000 / nvclk_freq;
363 us_p = nvclks*1000*1000 / pclk_freq;
366 video_drain_rate = pclk_freq * 2;
367 crtc_drain_rate = pclk_freq * bpp/8;
371 vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq;
372 if (nvclk_freq * 2 > mclk_freq * width)
373 video_fill_us = cbs*1000*1000 / 16 / nvclk_freq ;
375 video_fill_us = cbs*1000*1000 / (8 * width) / mclk_freq;
376 us_video = vpm_us + us_m + us_n + us_p + video_fill_us;
377 vlwm = us_video * video_drain_rate/(1000*1000);
380 if (vlwm > 128) vbs = 64;
381 if (vlwm > (256-64)) vbs = 32;
382 if (nvclk_freq * 2 > mclk_freq * width)
383 video_fill_us = vbs *1000*1000/ 16 / nvclk_freq ;
385 video_fill_us = vbs*1000*1000 / (8 * width) / mclk_freq;
386 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
393 clwm = us_crt * crtc_drain_rate/(1000*1000);
398 crtc_drain_rate = pclk_freq * bpp/8;
401 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
402 us_crt = cpm_us + us_m + us_n + us_p ;
403 clwm = us_crt * crtc_drain_rate/(1000*1000);
406 m1 = clwm + cbs - 512;
407 p1 = m1 * pclk_freq / mclk_freq;
409 if ((p1 < m1) && (m1 > 0))
413 if (mclk_extra ==0) found = 1;
416 else if (video_enable)
418 if ((clwm > 511) || (vlwm > 255))
422 if (mclk_extra ==0) found = 1;
432 if (mclk_extra ==0) found = 1;
436 if (clwm < 384) clwm = 384;
437 if (vlwm < 128) vlwm = 128;
439 fifo->graphics_lwm = data;
440 fifo->graphics_burst_size = 128;
441 data = (int)((vlwm+15));
442 fifo->video_lwm = data;
443 fifo->video_burst_size = vbs;
447 void nv4UpdateArbitrationSettings (
455 nv4_fifo_info fifo_data;
456 nv4_sim_state sim_data;
457 unsigned int MClk, NVClk, cfg1;
459 nvGetClocks(pNv, &MClk, &NVClk);
461 cfg1 = nvReadFB(pNv, NV_PFB_CFG1);
462 sim_data.pix_bpp = (char)pixelDepth;
463 sim_data.enable_video = 0;
464 sim_data.enable_mp = 0;
465 sim_data.memory_width = (nvReadEXTDEV(pNv, 0x0000) & 0x10) ? 128 : 64;
466 sim_data.mem_latency = (char)cfg1 & 0x0F;
467 sim_data.mem_aligned = 1;
468 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01));
469 sim_data.gr_during_vid = 0;
470 sim_data.pclk_khz = VClk;
471 sim_data.mclk_khz = MClk;
472 sim_data.nvclk_khz = NVClk;
473 nv4CalcArbitration(&fifo_data, &sim_data);
476 int b = fifo_data.graphics_burst_size >> 4;
478 while (b >>= 1) (*burst)++;
479 *lwm = fifo_data.graphics_lwm >> 3;
483 void nv10CalcArbitration (
484 nv10_fifo_info *fifo,
488 int data, pagemiss, width, video_enable, bpp;
489 int nvclks, mclks, pclks, vpagemiss, crtpagemiss;
491 int found, mclk_extra, mclk_loop, cbs, m1;
492 int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
493 int us_m, us_m_min, us_n, us_p, crtc_drain_rate;
495 int vpm_us, us_video, cpm_us, us_crt,clwm;
497 int m2us, us_pipe_min, p1clk, p2;
499 int us_min_mclk_extra;
502 pclk_freq = arb->pclk_khz; /* freq in KHz */
503 mclk_freq = arb->mclk_khz;
504 nvclk_freq = arb->nvclk_khz;
505 pagemiss = arb->mem_page_miss;
506 width = arb->memory_width/64;
507 video_enable = arb->enable_video;
509 mp_enable = arb->enable_mp;
514 pclks = 4; /* lwm detect. */
516 nvclks = 3; /* lwm -> sync. */
517 nvclks += 2; /* fbi bus cycles (1 req + 1 busy) */
519 mclks = 1; /* 2 edge sync. may be very close to edge so just put one. */
521 mclks += 1; /* arb_hp_req */
522 mclks += 5; /* ap_hp_req tiling pipeline */
524 mclks += 2; /* tc_req latency fifo */
525 mclks += 2; /* fb_cas_n_ memory request to fbio block */
526 mclks += 7; /* sm_d_rdv data returned from fbio block */
528 /* fb.rd.d.Put_gc need to accumulate 256 bits for read */
529 if (arb->memory_type == 0)
530 if (arb->memory_width == 64) /* 64 bit bus */
535 if (arb->memory_width == 64) /* 64 bit bus */
540 if ((!video_enable) && (arb->memory_width == 128))
542 mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */
547 mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */
548 /* mclk_extra = 4; */ /* Margin of error */
552 nvclks += 1; /* 2 edge sync. may be very close to edge so just put one. */
553 nvclks += 1; /* fbi_d_rdv_n */
554 nvclks += 1; /* Fbi_d_rdata */
555 nvclks += 1; /* crtfifo load */
558 mclks+=4; /* Mp can get in with a burst of 8. */
559 /* Extra clocks determined by heuristics */
567 mclk_loop = mclks+mclk_extra;
568 us_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */
569 us_m_min = mclks * 1000*1000 / mclk_freq; /* Minimum Mclk latency in us */
570 us_min_mclk_extra = min_mclk_extra *1000*1000 / mclk_freq;
571 us_n = nvclks*1000*1000 / nvclk_freq;/* nvclk latency in us */
572 us_p = pclks*1000*1000 / pclk_freq;/* nvclk latency in us */
573 us_pipe_min = us_m_min + us_n + us_p;
575 vus_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */
578 crtc_drain_rate = pclk_freq * bpp/8; /* MB/s */
580 vpagemiss = 1; /* self generating page miss */
581 vpagemiss += 1; /* One higher priority before */
583 crtpagemiss = 2; /* self generating page miss */
585 crtpagemiss += 1; /* if MA0 conflict */
587 vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq;
589 us_video = vpm_us + vus_m; /* Video has separate read return path */
591 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
593 us_video /* Wait for video */
594 +cpm_us /* CRT Page miss */
595 +us_m + us_n +us_p /* other latency */
598 clwm = us_crt * crtc_drain_rate/(1000*1000);
599 clwm++; /* fixed point <= float_point - 1. Fixes that */
601 crtc_drain_rate = pclk_freq * bpp/8; /* bpp * pclk/8 */
603 crtpagemiss = 1; /* self generating page miss */
604 crtpagemiss += 1; /* MA0 page miss */
606 crtpagemiss += 1; /* if MA0 conflict */
607 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
608 us_crt = cpm_us + us_m + us_n + us_p ;
609 clwm = us_crt * crtc_drain_rate/(1000*1000);
610 clwm++; /* fixed point <= float_point - 1. Fixes that */
612 /* Finally, a heuristic check when width == 64 bits */
614 nvclk_fill = nvclk_freq * 8;
615 if(crtc_drain_rate * 100 >= nvclk_fill * 102)
616 clwm = 0xfff; /*Large number to fail */
618 else if(crtc_drain_rate * 100 >= nvclk_fill * 98) {
631 clwm_rnd_down = ((int)clwm/8)*8;
632 if (clwm_rnd_down < clwm)
635 m1 = clwm + cbs - 1024; /* Amount of overfill */
636 m2us = us_pipe_min + us_min_mclk_extra;
638 /* pclk cycles to drain */
639 p1clk = m2us * pclk_freq/(1000*1000);
640 p2 = p1clk * bpp / 8; /* bytes drained. */
642 if((p2 < m1) && (m1 > 0)) {
645 if(min_mclk_extra == 0) {
647 found = 1; /* Can't adjust anymore! */
649 cbs = cbs/2; /* reduce the burst size */
655 if (clwm > 1023){ /* Have some margin */
658 if(min_mclk_extra == 0)
659 found = 1; /* Can't adjust anymore! */
665 if(clwm < (1024-cbs+8)) clwm = 1024-cbs+8;
667 /* printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n", clwm, data ); */
668 fifo->graphics_lwm = data; fifo->graphics_burst_size = cbs;
670 fifo->video_lwm = 1024; fifo->video_burst_size = 512;
674 void nv10UpdateArbitrationSettings (
682 nv10_fifo_info fifo_data;
683 nv10_sim_state sim_data;
684 unsigned int MClk, NVClk, cfg1;
686 nvGetClocks(pNv, &MClk, &NVClk);
688 cfg1 = nvReadFB(pNv, NV_PFB_CFG1);
689 sim_data.pix_bpp = (char)pixelDepth;
690 sim_data.enable_video = 1;
691 sim_data.enable_mp = 0;
692 sim_data.memory_type = (nvReadFB(pNv, NV_PFB_CFG0) & 0x01) ? 1 : 0;
693 sim_data.memory_width = (nvReadEXTDEV(pNv, 0x0000) & 0x10) ? 128 : 64;
694 sim_data.mem_latency = (char)cfg1 & 0x0F;
695 sim_data.mem_aligned = 1;
696 sim_data.mem_page_miss = (char)(((cfg1>>4) &0x0F) + ((cfg1>>31) & 0x01));
697 sim_data.gr_during_vid = 0;
698 sim_data.pclk_khz = VClk;
699 sim_data.mclk_khz = MClk;
700 sim_data.nvclk_khz = NVClk;
701 nv10CalcArbitration(&fifo_data, &sim_data);
702 if (fifo_data.valid) {
703 int b = fifo_data.graphics_burst_size >> 4;
705 while (b >>= 1) (*burst)++;
706 *lwm = fifo_data.graphics_lwm >> 3;
711 void nv30UpdateArbitrationSettings (NVPtr pNv,
715 unsigned int MClk, NVClk;
716 unsigned int fifo_size, burst_size, graphics_lwm;
720 graphics_lwm = fifo_size - burst_size;
722 nvGetClocks(pNv, &MClk, &NVClk);
726 while(burst_size >>= 1) (*burst)++;
727 *lwm = graphics_lwm >> 3;
730 #ifdef XSERVER_LIBPCIACCESS
732 struct pci_device GetDeviceByPCITAG(uint32_t bus, uint32_t dev, uint32_t func)
734 const struct pci_slot_match match[] = { {0, bus, dev, func, 0} };
735 struct pci_device_iterator *iterator = pci_slot_match_iterator_create(&match);
736 /* assume one device to exist */
737 struct pci_device *device = pci_device_next(iterator);
742 #endif /* XSERVER_LIBPCIACCESS */
744 void nForceUpdateArbitrationSettings (unsigned VClk,
751 nv10_fifo_info fifo_data;
752 nv10_sim_state sim_data;
753 unsigned int M, N, P, pll, MClk, NVClk, memctrl;
755 #ifdef XSERVER_LIBPCIACCESS
756 struct pci_device tmp;
757 #endif /* XSERVER_LIBPCIACCESS */
759 if((pNv->Chipset & 0x0FF0) == CHIPSET_NFORCE) {
760 unsigned int uMClkPostDiv;
762 #ifdef XSERVER_LIBPCIACCESS
763 tmp = GetDeviceByPCITAG(0, 0, 3);
764 PCI_DEV_READ_LONG(&tmp, 0x6C, &uMClkPostDiv);
765 uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
767 uMClkPostDiv = (pciReadLong(pciTag(0, 0, 3), 0x6C) >> 8) & 0xf;
768 #endif /* XSERVER_LIBPCIACCESS */
769 if(!uMClkPostDiv) uMClkPostDiv = 4;
770 MClk = 400000 / uMClkPostDiv;
772 #ifdef XSERVER_LIBPCIACCESS
773 tmp = GetDeviceByPCITAG(0, 0, 5);
774 PCI_DEV_READ_LONG(&tmp, 0x4C, &MClk);
777 MClk = pciReadLong(pciTag(0, 0, 5), 0x4C) / 1000;
778 #endif /* XSERVER_LIBPCIACCESS */
781 pll = nvReadRAMDAC0(pNv, NV_RAMDAC_NVPLL);
782 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
783 NVClk = (N * pNv->CrystalFreqKHz / M) >> P;
784 sim_data.pix_bpp = (char)pixelDepth;
785 sim_data.enable_video = 0;
786 sim_data.enable_mp = 0;
787 #ifdef XSERVER_LIBPCIACCESS
788 tmp = GetDeviceByPCITAG(0, 0, 1);
789 PCI_DEV_READ_LONG(&tmp, 0x7C, &(sim_data.memory_type));
790 sim_data.memory_type = (sim_data.memory_type >> 12) & 1;
792 sim_data.memory_type = (pciReadLong(pciTag(0, 0, 1), 0x7C) >> 12) & 1;
793 #endif /* XSERVER_LIBPCIACCESS */
794 sim_data.memory_width = 64;
796 #ifdef XSERVER_LIBPCIACCESS
797 /* This offset is 0, is this even usefull? */
798 tmp = GetDeviceByPCITAG(0, 0, 3);
799 PCI_DEV_READ_LONG(&tmp, 0x00, &memctrl);
802 memctrl = pciReadLong(pciTag(0, 0, 3), 0x00) >> 16;
803 #endif /* XSERVER_LIBPCIACCESS */
805 if((memctrl == 0x1A9) || (memctrl == 0x1AB) || (memctrl == 0x1ED)) {
807 #ifdef XSERVER_LIBPCIACCESS
808 tmp = GetDeviceByPCITAG(0, 0, 2);
809 PCI_DEV_READ_LONG(&tmp, 0x40, &dimm[0]);
810 PCI_DEV_READ_LONG(&tmp, 0x44, &dimm[1]);
811 PCI_DEV_READ_LONG(&tmp, 0x48, &dimm[2]);
813 for (i = 0; i < 3; i++) {
814 dimm[i] = (dimm[i] >> 8) & 0x4F;
817 dimm[0] = (pciReadLong(pciTag(0, 0, 2), 0x40) >> 8) & 0x4F;
818 dimm[1] = (pciReadLong(pciTag(0, 0, 2), 0x44) >> 8) & 0x4F;
819 dimm[2] = (pciReadLong(pciTag(0, 0, 2), 0x48) >> 8) & 0x4F;
822 if((dimm[0] + dimm[1]) != dimm[2]) {
824 "your nForce DIMMs are not arranged in optimal banks!\n");
828 sim_data.mem_latency = 3;
829 sim_data.mem_aligned = 1;
830 sim_data.mem_page_miss = 10;
831 sim_data.gr_during_vid = 0;
832 sim_data.pclk_khz = VClk;
833 sim_data.mclk_khz = MClk;
834 sim_data.nvclk_khz = NVClk;
835 nv10CalcArbitration(&fifo_data, &sim_data);
838 int b = fifo_data.graphics_burst_size >> 4;
840 while (b >>= 1) (*burst)++;
841 *lwm = fifo_data.graphics_lwm >> 3;
846 /****************************************************************************\
848 * RIVA Mode State Routines *
850 \****************************************************************************/
853 * Calculate the Video Clock parameters for the PLL.
855 static void CalcVClock (
862 unsigned lowM, highM;
863 unsigned DeltaNew, DeltaOld;
867 DeltaOld = 0xFFFFFFFF;
869 VClk = (unsigned)clockIn;
871 if (pNv->CrystalFreqKHz == 13500) {
879 for (P = 0; P <= 4; P++) {
881 if ((Freq >= 128000) && (Freq <= 350000)) {
882 for (M = lowM; M <= highM; M++) {
883 N = ((VClk << P) * M) / pNv->CrystalFreqKHz;
885 Freq = ((pNv->CrystalFreqKHz * N) / M) >> P;
887 DeltaNew = Freq - VClk;
889 DeltaNew = VClk - Freq;
890 if (DeltaNew < DeltaOld) {
891 *pllOut = (P << 16) | (N << 8) | M;
901 static void CalcVClock2Stage (
909 unsigned DeltaNew, DeltaOld;
913 DeltaOld = 0xFFFFFFFF;
915 *pllBOut = 0x80000401; /* fixed at x4 for now */
917 VClk = (unsigned)clockIn;
919 for (P = 0; P <= 6; P++) {
921 if ((Freq >= 400000) && (Freq <= 1000000)) {
922 for (M = 1; M <= 13; M++) {
923 N = ((VClk << P) * M) / (pNv->CrystalFreqKHz << 2);
924 if((N >= 5) && (N <= 255)) {
925 Freq = (((pNv->CrystalFreqKHz << 2) * N) / M) >> P;
927 DeltaNew = Freq - VClk;
929 DeltaNew = VClk - Freq;
930 if (DeltaNew < DeltaOld) {
931 *pllOut = (P << 16) | (N << 8) | M;
942 * Calculate extended mode parameters (SVGA) and save in a
943 * mode state structure.
945 void NVCalcStateExt (
947 RIVA_HW_STATE *state,
956 int pixelDepth, VClk;
960 * Save mode parameters.
962 state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */
963 state->width = width;
964 state->height = height;
966 * Extended RIVA registers.
968 pixelDepth = (bpp + 1)/8;
970 CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB, pNv);
972 CalcVClock(dotClock, &VClk, &state->pll, pNv);
974 switch (pNv->Architecture)
977 nv4UpdateArbitrationSettings(VClk,
979 &(state->arbitration0),
980 &(state->arbitration1),
982 state->cursor0 = 0x00;
983 state->cursor1 = 0xbC;
984 if (flags & V_DBLSCAN)
986 state->cursor2 = 0x00000000;
987 state->pllsel = 0x10000700;
988 state->config = 0x00001114;
989 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
990 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
996 if(((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
997 ((pNv->Chipset & 0xfff0) == CHIPSET_C512))
999 state->arbitration0 = 128;
1000 state->arbitration1 = 0x0480;
1002 if(((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
1003 ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2))
1005 nForceUpdateArbitrationSettings(VClk,
1007 &(state->arbitration0),
1008 &(state->arbitration1),
1010 } else if(pNv->Architecture < NV_ARCH_30) {
1011 nv10UpdateArbitrationSettings(VClk,
1013 &(state->arbitration0),
1014 &(state->arbitration1),
1017 nv30UpdateArbitrationSettings(pNv,
1018 &(state->arbitration0),
1019 &(state->arbitration1));
1021 CursorStart = pNv->Cursor->offset;
1022 state->cursor0 = 0x80 | (CursorStart >> 17);
1023 state->cursor1 = (CursorStart >> 11) << 2;
1024 state->cursor2 = CursorStart >> 24;
1025 if (flags & V_DBLSCAN)
1026 state->cursor1 |= 2;
1027 state->pllsel = 0x10000700;
1028 state->config = nvReadFB(pNv, NV_PFB_CFG0);
1029 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
1030 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
1034 if(bpp != 8) /* DirectColor */
1035 state->general |= 0x00000030;
1037 state->repaint0 = (((width / 8) * pixelDepth) & 0x700) >> 3;
1038 state->pixel = (pixelDepth > 2) ? 3 : pixelDepth;
1042 void NVLoadStateExt (
1044 RIVA_HW_STATE *state
1047 NVPtr pNv = NVPTR(pScrn);
1050 if(pNv->Architecture >= NV_ARCH_40) {
1051 switch(pNv->Chipset & 0xfff0) {
1060 temp = nvReadCurRAMDAC(pNv, NV_RAMDAC_TEST_CONTROL);
1061 nvWriteCurRAMDAC(pNv, NV_RAMDAC_TEST_CONTROL, temp | 0x00100000);
1068 if(pNv->Architecture >= NV_ARCH_10) {
1070 nvWriteCRTC(pNv, 0, NV_CRTC_FSEL, state->head);
1071 nvWriteCRTC(pNv, 1, NV_CRTC_FSEL, state->head2);
1073 temp = nvReadCurRAMDAC(pNv, NV_RAMDAC_NV10_CURSYNC);
1074 nvWriteCurRAMDAC(pNv, NV_RAMDAC_NV10_CURSYNC, temp | (1 << 25));
1076 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
1077 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
1078 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
1079 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
1080 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1081 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1082 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1083 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1084 nvWriteMC(pNv, 0x1588, 0);
1086 nvWriteCurCRTC(pNv, NV_CRTC_CURSOR_CONFIG, state->cursorConfig);
1087 nvWriteCurCRTC(pNv, NV_CRTC_0830, state->displayV - 3);
1088 nvWriteCurCRTC(pNv, NV_CRTC_0834, state->displayV - 1);
1090 if(pNv->FlatPanel) {
1091 if((pNv->Chipset & 0x0ff0) == CHIPSET_NV11) {
1092 nvWriteCurRAMDAC(pNv, NV_RAMDAC_DITHER_NV11, state->dither);
1095 nvWriteCurRAMDAC(pNv, NV_RAMDAC_FP_DITHER, state->dither);
1098 nvWriteVGA(pNv, NV_VGA_CRTCX_FP_HTIMING, state->timingH);
1099 nvWriteVGA(pNv, NV_VGA_CRTCX_FP_VTIMING, state->timingV);
1100 nvWriteVGA(pNv, NV_VGA_CRTCX_BUFFER, 0xfa);
1103 nvWriteVGA(pNv, NV_VGA_CRTCX_EXTRA, state->extra);
1106 nvWriteVGA(pNv, NV_VGA_CRTCX_REPAINT0, state->repaint0);
1107 nvWriteVGA(pNv, NV_VGA_CRTCX_REPAINT1, state->repaint1);
1108 nvWriteVGA(pNv, NV_VGA_CRTCX_LSR, state->screen);
1109 nvWriteVGA(pNv, NV_VGA_CRTCX_PIXEL, state->pixel);
1110 nvWriteVGA(pNv, NV_VGA_CRTCX_HEB, state->horiz);
1111 nvWriteVGA(pNv, NV_VGA_CRTCX_FIFO1, state->fifo);
1112 nvWriteVGA(pNv, NV_VGA_CRTCX_FIFO0, state->arbitration0);
1113 nvWriteVGA(pNv, NV_VGA_CRTCX_FIFO_LWM, state->arbitration1);
1114 if(pNv->Architecture >= NV_ARCH_30) {
1115 nvWriteVGA(pNv, NV_VGA_CRTCX_FIFO_LWM_NV30, state->arbitration1 >> 8);
1118 nvWriteVGA(pNv, NV_VGA_CRTCX_CURCTL0, state->cursor0);
1119 nvWriteVGA(pNv, NV_VGA_CRTCX_CURCTL1, state->cursor1);
1120 if(pNv->Architecture == NV_ARCH_40) { /* HW bug */
1121 volatile CARD32 curpos = nvReadCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS);
1122 nvWriteCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS, curpos);
1124 nvWriteVGA(pNv, NV_VGA_CRTCX_CURCTL2, state->cursor2);
1125 nvWriteVGA(pNv, NV_VGA_CRTCX_INTERLACE, state->interlace);
1127 if(!pNv->FlatPanel) {
1128 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
1129 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll);
1131 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2);
1132 if(pNv->twoStagePLL) {
1133 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpllB);
1134 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2B);
1137 nvWriteCurRAMDAC(pNv, NV_RAMDAC_FP_CONTROL, state->scale);
1138 nvWriteCurRAMDAC(pNv, NV_RAMDAC_FP_HCRTC, state->crtcSync);
1140 nvWriteCurRAMDAC(pNv, NV_RAMDAC_GENERAL_CONTROL, state->general);
1142 nvWriteCurCRTC(pNv, NV_CRTC_INTR_EN_0, 0);
1143 nvWriteCurCRTC(pNv, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
1145 pNv->CurrentState = state;
1148 void NVUnloadStateExt
1151 RIVA_HW_STATE *state
1154 state->repaint0 = nvReadVGA(pNv, NV_VGA_CRTCX_REPAINT0);
1155 state->repaint1 = nvReadVGA(pNv, NV_VGA_CRTCX_REPAINT1);
1156 state->screen = nvReadVGA(pNv, NV_VGA_CRTCX_LSR);
1157 state->pixel = nvReadVGA(pNv, NV_VGA_CRTCX_PIXEL);
1158 state->horiz = nvReadVGA(pNv, NV_VGA_CRTCX_HEB);
1159 state->fifo = nvReadVGA(pNv, NV_VGA_CRTCX_FIFO1);
1160 state->arbitration0 = nvReadVGA(pNv, NV_VGA_CRTCX_FIFO0);
1161 state->arbitration1 = nvReadVGA(pNv, NV_VGA_CRTCX_FIFO_LWM);
1162 if(pNv->Architecture >= NV_ARCH_30) {
1163 state->arbitration1 |= (nvReadVGA(pNv, NV_VGA_CRTCX_FIFO_LWM_NV30) & 1) << 8;
1165 state->cursor0 = nvReadVGA(pNv, NV_VGA_CRTCX_CURCTL0);
1166 state->cursor1 = nvReadVGA(pNv, NV_VGA_CRTCX_CURCTL1);
1167 state->cursor2 = nvReadVGA(pNv, NV_VGA_CRTCX_CURCTL2);
1168 state->interlace = nvReadVGA(pNv, NV_VGA_CRTCX_INTERLACE);
1170 state->vpll = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
1172 state->vpll2 = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
1173 if(pNv->twoStagePLL) {
1174 state->vpllB = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
1175 state->vpll2B = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
1177 state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
1178 state->general = nvReadCurRAMDAC(pNv, NV_RAMDAC_GENERAL_CONTROL);
1179 state->scale = nvReadCurRAMDAC(pNv, NV_RAMDAC_FP_CONTROL);
1180 state->config = nvReadFB(pNv, NV_PFB_CFG0);
1182 if(pNv->Architecture >= NV_ARCH_10) {
1184 state->head = nvReadCRTC(pNv, 0, NV_CRTC_FSEL);
1185 state->head2 = nvReadCRTC(pNv, 1, NV_CRTC_FSEL);
1186 state->crtcOwner = nvReadVGA(pNv, NV_VGA_CRTCX_OWNER);
1188 state->extra = nvReadVGA(pNv, NV_VGA_CRTCX_EXTRA);
1190 state->cursorConfig = nvReadCurCRTC(pNv, NV_CRTC_CURSOR_CONFIG);
1192 if((pNv->Chipset & 0x0ff0) == CHIPSET_NV11) {
1193 state->dither = nvReadCurRAMDAC(pNv, NV_RAMDAC_DITHER_NV11);
1196 state->dither = nvReadCurRAMDAC(pNv, NV_RAMDAC_FP_DITHER);
1199 if(pNv->FlatPanel) {
1200 state->timingH = nvReadVGA(pNv, NV_VGA_CRTCX_FP_HTIMING);
1201 state->timingV = nvReadVGA(pNv, NV_VGA_CRTCX_FP_VTIMING);
1205 if(pNv->FlatPanel) {
1206 state->crtcSync = nvReadCurRAMDAC(pNv, NV_RAMDAC_FP_HCRTC);
1210 void NVSetStartAddress (
1215 nvWriteCurCRTC(pNv, NV_CRTC_START, start);