git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 2006 Dave Airlie
   3  * Copyright 2007 Maarten Maathuis
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
  26  * decleration is at the bottom of this file as it is rather ugly
  27  */
  28
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include <assert.h>
  34 #include "xf86.h"
  35 #include "os.h"
  36 #include "mibank.h"
  37 #include "globals.h"
  38 #include "xf86.h"
  39 #include "xf86Priv.h"
  40 #include "xf86DDC.h"
  41 #include "mipointer.h"
  42 #include "windowstr.h"
  43 #include <randrstr.h>
  44 #include <X11/extensions/render.h>
  45
  46 #include "xf86Crtc.h"
  47 #include "nv_include.h"
  48
  49 #include "vgaHW.h"
  50
  51 #define CRTC_INDEX 0x3d4
  52 #define CRTC_DATA 0x3d5
  53 #define CRTC_IN_STAT_1 0x3da
  54
  55 #define WHITE_VALUE 0x3F
  56 #define BLACK_VALUE 0x00
  57 #define OVERSCAN_VALUE 0x01
  58
  59 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  60 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override);
  61 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  62 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  63 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  64 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  65 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  66 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  67
  68 uint32_t NVReadCRTC(NVPtr pNv, uint8_t head, uint32_t reg)
  69 {
  70         if (head)
  71                 reg += NV_PCRTC0_SIZE;
  72         DDXMMIOH("NVReadCRTC: head %d reg %08x val %08x\n", head, reg, (uint32_t)MMIO_IN32(pNv->REGS, reg));
  73         return MMIO_IN32(pNv->REGS, reg);
  74 }
  75
  76 void NVWriteCRTC(NVPtr pNv, uint8_t head, uint32_t reg, uint32_t val)
  77 {
  78         if (head)
  79                 reg += NV_PCRTC0_SIZE;
  80         DDXMMIOH("NVWriteCRTC: head %d reg %08x val %08x\n", head, reg, val);
  81         MMIO_OUT32(pNv->REGS, reg, val);
  82 }
  83
  84 uint32_t NVCrtcReadCRTC(xf86CrtcPtr crtc, uint32_t reg)
  85 {
  86         ScrnInfoPtr pScrn = crtc->scrn;
  87         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  88         NVPtr pNv = NVPTR(pScrn);
  89
  90         return NVReadCRTC(pNv, nv_crtc->head, reg);
  91 }
  92
  93 void NVCrtcWriteCRTC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
  94 {
  95         ScrnInfoPtr pScrn = crtc->scrn;
  96         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  97         NVPtr pNv = NVPTR(pScrn);
  98
  99         NVWriteCRTC(pNv, nv_crtc->head, reg, val);
 100 }
 101
 102 uint32_t NVReadRAMDAC(NVPtr pNv, uint8_t head, uint32_t reg)
 103 {
 104         if (head)
 105                 reg += NV_PRAMDAC0_SIZE;
 106         DDXMMIOH("NVReadRamdac: head %d reg %08x val %08x\n", head, reg, (uint32_t)MMIO_IN32(pNv->REGS, reg));
 107         return MMIO_IN32(pNv->REGS, reg);
 108 }
 109
 110 void NVWriteRAMDAC(NVPtr pNv, uint8_t head, uint32_t reg, uint32_t val)
 111 {
 112         if (head)
 113                 reg += NV_PRAMDAC0_SIZE;
 114         DDXMMIOH("NVWriteRamdac: head %d reg %08x val %08x\n", head, reg, val);
 115         MMIO_OUT32(pNv->REGS, reg, val);
 116 }
 117
 118 uint32_t NVCrtcReadRAMDAC(xf86CrtcPtr crtc, uint32_t reg)
 119 {
 120         ScrnInfoPtr pScrn = crtc->scrn;
 121         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 122         NVPtr pNv = NVPTR(pScrn);
 123
 124         return NVReadRAMDAC(pNv, nv_crtc->head, reg);
 125 }
 126
 127 void NVCrtcWriteRAMDAC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
 128 {
 129         ScrnInfoPtr pScrn = crtc->scrn;
 130         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 131         NVPtr pNv = NVPTR(pScrn);
 132
 133         NVWriteRAMDAC(pNv, nv_crtc->head, reg, val);
 134 }
 135
 136 static uint8_t NVReadPVIO(xf86CrtcPtr crtc, uint32_t address)
 137 {
 138         ScrnInfoPtr pScrn = crtc->scrn;
 139         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 140         NVPtr pNv = NVPTR(pScrn);
 141
 142         /* Only NV4x have two pvio ranges */
 143         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
 144                 DDXMMIOH("NVReadPVIO: head %d reg %08x val %02x\n", 1, address + NV_PVIO_OFFSET + NV_PVIO_SIZE, NV_RD08(pNv->PVIO1, address));
 145                 return NV_RD08(pNv->PVIO1, address);
 146         } else {
 147                 DDXMMIOH("NVReadPVIO: head %d reg %08x val %02x\n", 0, address + NV_PVIO_OFFSET, NV_RD08(pNv->PVIO0, address));
 148                 return NV_RD08(pNv->PVIO0, address);
 149         }
 150 }
 151
 152 static void NVWritePVIO(xf86CrtcPtr crtc, uint32_t address, uint8_t value)
 153 {
 154         ScrnInfoPtr pScrn = crtc->scrn;
 155         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 156         NVPtr pNv = NVPTR(pScrn);
 157
 158         /* Only NV4x have two pvio ranges */
 159         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
 160                 DDXMMIOH("NVWritePVIO: head %d reg %08x val %02x\n", nv_crtc->head, address + NV_PVIO_OFFSET + NV_PVIO_SIZE, value);
 161                 NV_WR08(pNv->PVIO1, address, value);
 162         } else {
 163                 DDXMMIOH("NVWritePVIO: head %d reg %08x val %02x\n", nv_crtc->head, address + NV_PVIO_OFFSET, value);
 164                 NV_WR08(pNv->PVIO0, address, value);
 165         }
 166 }
 167
 168 void NVWriteVGA(NVPtr pNv, int head, uint8_t index, uint8_t value)
 169 {
 170         volatile uint8_t *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 171
 172         DDXMMIOH("NVWriteVGA: head %d index 0x%02x data 0x%02x\n", head, index, value);
 173         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 174         NV_WR08(pCRTCReg, CRTC_DATA, value);
 175 }
 176
 177 uint8_t NVReadVGA(NVPtr pNv, int head, uint8_t index)
 178 {
 179         volatile uint8_t *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 180
 181         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 182         DDXMMIOH("NVReadVGA: head %d index 0x%02x data 0x%02x\n", head, index, NV_RD08(pCRTCReg, CRTC_DATA));
 183         return NV_RD08(pCRTCReg, CRTC_DATA);
 184 }
 185
 186 /* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
 187  * I suspect they in fact do nothing, but are merely a way to carry useful
 188  * per-head variables around
 189  *
 190  * Known uses:
 191  * CR57         CR58
 192  * 0x00         index to the appropriate dcb entry (or 7f for inactive)
 193  * 0x02         dcb entry's "or" value (or 00 for inactive)
 194  * 0x03         bit0 set for dual link (LVDS, possibly elsewhere too)
 195  * 0x08 or 0x09 pxclk in MHz
 196  * 0x0f         laptop panel info -     low nibble for PEXTDEV_BOOT_0 strap
 197  *                                      high nibble for xlat strap value
 198  */
 199
 200 void NVWriteVGACR5758(NVPtr pNv, int head, uint8_t index, uint8_t value)
 201 {
 202         NVWriteVGA(pNv, head, 0x57, index);
 203         NVWriteVGA(pNv, head, 0x58, value);
 204 }
 205
 206 uint8_t NVReadVGACR5758(NVPtr pNv, int head, uint8_t index)
 207 {
 208         NVWriteVGA(pNv, head, 0x57, index);
 209         return NVReadVGA(pNv, head, 0x58);
 210 }
 211
 212 void NVWriteVgaCrtc(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 213 {
 214         ScrnInfoPtr pScrn = crtc->scrn;
 215         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 216         NVPtr pNv = NVPTR(pScrn);
 217
 218         NVWriteVGA(pNv, nv_crtc->head, index, value);
 219 }
 220
 221 uint8_t NVReadVgaCrtc(xf86CrtcPtr crtc, uint8_t index)
 222 {
 223         ScrnInfoPtr pScrn = crtc->scrn;
 224         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 225         NVPtr pNv = NVPTR(pScrn);
 226
 227         return NVReadVGA(pNv, nv_crtc->head, index);
 228 }
 229
 230 static void NVWriteVgaSeq(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 231 {
 232         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 233         NVWritePVIO(crtc, VGA_SEQ_DATA, value);
 234 }
 235
 236 static uint8_t NVReadVgaSeq(xf86CrtcPtr crtc, uint8_t index)
 237 {
 238         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 239         return NVReadPVIO(crtc, VGA_SEQ_DATA);
 240 }
 241
 242 static void NVWriteVgaGr(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 243 {
 244         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 245         NVWritePVIO(crtc, VGA_GRAPH_DATA, value);
 246 }
 247
 248 static uint8_t NVReadVgaGr(xf86CrtcPtr crtc, uint8_t index)
 249 {
 250         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 251         return NVReadPVIO(crtc, VGA_GRAPH_DATA);
 252 }
 253
 254
 255 static void NVWriteVgaAttr(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 256 {
 257         ScrnInfoPtr pScrn = crtc->scrn;
 258         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 259         NVPtr pNv = NVPTR(pScrn);
 260         volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 261
 262         DDXMMIOH("NVWriteVgaAttr: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, CRTC_IN_STAT_1, NV_RD08(pCRTCReg, CRTC_IN_STAT_1));
 263         NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 264         if (nv_crtc->paletteEnabled)
 265                 index &= ~0x20;
 266         else
 267                 index |= 0x20;
 268
 269         DDXMMIOH("NVWriteVgaAttr: head %d index 0x%02x data 0x%02x\n", nv_crtc->head, index, value);
 270         NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 271         NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
 272 }
 273
 274 static uint8_t NVReadVgaAttr(xf86CrtcPtr crtc, uint8_t index)
 275 {
 276         ScrnInfoPtr pScrn = crtc->scrn;
 277         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 278         NVPtr pNv = NVPTR(pScrn);
 279         volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 280
 281         DDXMMIOH("NVReadVgaAttr: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, CRTC_IN_STAT_1, NV_RD08(pCRTCReg, CRTC_IN_STAT_1));
 282         NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 283         if (nv_crtc->paletteEnabled)
 284                 index &= ~0x20;
 285         else
 286                 index |= 0x20;
 287
 288         NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 289         DDXMMIOH("NVReadVgaAttr: head %d index 0x%02x data 0x%02x\n", nv_crtc->head, index, NV_RD08(pCRTCReg, VGA_ATTR_DATA_R));
 290         return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
 291 }
 292
 293 void NVSetOwner(ScrnInfoPtr pScrn, uint8_t head)
 294 {
 295         NVPtr pNv = NVPTR(pScrn);
 296         /* CRTCX_OWNER is always changed on CRTC0 */
 297         NVWriteVGA(pNv, 0, NV_VGA_CRTCX_OWNER, head*0x3);
 298
 299         ErrorF("Setting owner: 0x%X\n", head*0x3);
 300 }
 301
 302 static void NVCrtcSetOwner(xf86CrtcPtr crtc)
 303 {
 304         ScrnInfoPtr pScrn = crtc->scrn;
 305         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 306
 307         /* CRTCX_OWNER is always changed on CRTC0 */
 308         NVSetOwner(pScrn, nv_crtc->head);
 309 }
 310
 311 static void
 312 NVEnablePalette(xf86CrtcPtr crtc)
 313 {
 314         ScrnInfoPtr pScrn = crtc->scrn;
 315         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 316         NVPtr pNv = NVPTR(pScrn);
 317         volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 318
 319         DDXMMIOH("NVEnablePalette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, CRTC_IN_STAT_1, NV_RD08(pCRTCReg, CRTC_IN_STAT_1));
 320         NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 321         DDXMMIOH("NVEnablePalette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_ATTR_INDEX, 0);
 322         NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
 323         nv_crtc->paletteEnabled = TRUE;
 324 }
 325
 326 static void
 327 NVDisablePalette(xf86CrtcPtr crtc)
 328 {
 329         ScrnInfoPtr pScrn = crtc->scrn;
 330         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 331         NVPtr pNv = NVPTR(pScrn);
 332         volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 333
 334         DDXMMIOH("NVDisablePalette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, NV_PCIO0_OFFSET + (nv_crtc->head ? NV_PCIO0_SIZE : 0) + CRTC_IN_STAT_1, NV_RD08(pCRTCReg, CRTC_IN_STAT_1));
 335         NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 336         DDXMMIOH("NVDisablePalette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, NV_PCIO0_OFFSET + (nv_crtc->head ? NV_PCIO0_SIZE : 0) + VGA_ATTR_INDEX, 0x20);
 337         NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
 338         nv_crtc->paletteEnabled = FALSE;
 339 }
 340
 341 /* perform a sequencer reset */
 342 static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
 343 {
 344   if (start)
 345     NVWriteVgaSeq(crtc, 0x00, 0x1);
 346   else
 347     NVWriteVgaSeq(crtc, 0x00, 0x3);
 348
 349 }
 350 static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
 351 {
 352         uint8_t tmp;
 353
 354         if (on) {
 355                 tmp = NVReadVgaSeq(crtc, 0x1);
 356                 NVVgaSeqReset(crtc, TRUE);
 357                 NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
 358
 359                 NVEnablePalette(crtc);
 360         } else {
 361                 /*
 362                  * Reenable sequencer, then turn on screen.
 363                  */
 364                 tmp = NVReadVgaSeq(crtc, 0x1);
 365                 NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20); /* reenable display */
 366                 NVVgaSeqReset(crtc, FALSE);
 367
 368                 NVDisablePalette(crtc);
 369         }
 370 }
 371
 372 void NVLockUnlockHead(ScrnInfoPtr pScrn, uint8_t head, Bool lock)
 373 {
 374         NVPtr pNv = NVPTR(pScrn);
 375         uint8_t cr11;
 376
 377         if (pNv->twoHeads)
 378                 NVSetOwner(pScrn, head);
 379
 380         NVWriteVGA(pNv, head, NV_VGA_CRTCX_LOCK, lock ? 0x99 : 0x57);
 381         cr11 = NVReadVGA(pNv, head, NV_VGA_CRTCX_VSYNCE);
 382         if (lock) cr11 |= 0x80;
 383         else cr11 &= ~0x80;
 384         NVWriteVGA(pNv, head, NV_VGA_CRTCX_VSYNCE, cr11);
 385 }
 386
 387 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool lock)
 388 {
 389         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 390         ScrnInfoPtr pScrn = crtc->scrn;
 391
 392         NVLockUnlockHead(pScrn, nv_crtc->head, lock);
 393 }
 394
 395 xf86OutputPtr
 396 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
 397 {
 398         ScrnInfoPtr pScrn = crtc->scrn;
 399         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 400         int i;
 401         for (i = 0; i < xf86_config->num_output; i++) {
 402                 xf86OutputPtr output = xf86_config->output[i];
 403
 404                 if (output->crtc == crtc) {
 405                         return output;
 406                 }
 407         }
 408
 409         return NULL;
 410 }
 411
 412 xf86CrtcPtr
 413 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
 414 {
 415         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 416         int i;
 417
 418         for (i = 0; i < xf86_config->num_crtc; i++) {
 419                 xf86CrtcPtr crtc = xf86_config->crtc[i];
 420                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 421                 if (nv_crtc->head == index)
 422                         return crtc;
 423         }
 424
 425         return NULL;
 426 }
 427
 428 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
 429 /* They are only valid for NV4x, appearantly reordered for NV5x */
 430 /* gpu pll: 0x4000 + 0x4004
 431  * unknown pll: 0x4008 + 0x400c
 432  * vpll1: 0x4010 + 0x4014
 433  * vpll2: 0x4018 + 0x401c
 434  * unknown pll: 0x4020 + 0x4024
 435  * unknown pll: 0x4038 + 0x403c
 436  * Some of the unknown's are probably memory pll's.
 437  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
 438  * 1 and 2 refer to the registers of each pair. There is only one post divider.
 439  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
 440  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
 441  *     bit8: A switch that turns of the second divider and multiplier off.
 442  *     bit12: Also a switch, i haven't seen it yet.
 443  *     bit16-19: p-divider
 444  *     but 28-31: Something related to the mode that is used (see bit8).
 445  * 2) bit0-7: m-divider (a)
 446  *     bit8-15: n-multiplier (a)
 447  *     bit16-23: m-divider (b)
 448  *     bit24-31: n-multiplier (b)
 449  */
 450
 451 /* Modifying the gpu pll for example requires:
 452  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 453  * This is not needed for the vpll's which have their own bits.
 454  */
 455
 456 static void nv40_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 457 {
 458         state->vpll1_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL);
 459         state->vpll1_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B);
 460         state->vpll2_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2);
 461         state->vpll2_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B);
 462         state->pllsel = NVReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT);
 463         state->sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
 464         state->reg580 = NVReadRAMDAC(pNv, 0, NV_RAMDAC_580);
 465         state->reg594 = NVReadRAMDAC(pNv, 0, NV_RAMDAC_594);
 466 }
 467
 468 static void nv40_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 469 {
 470         ScrnInfoPtr pScrn = crtc->scrn;
 471         NVPtr pNv = NVPTR(pScrn);
 472         uint32_t fp_debug_0[2];
 473         uint32_t index[2];
 474         fp_debug_0[0] = NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
 475         fp_debug_0[1] = NVReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
 476
 477         /* The TMDS_PLL switch is on the actual ramdac */
 478         if (state->crosswired) {
 479                 index[0] = 1;
 480                 index[1] = 0;
 481                 ErrorF("Crosswired pll state load\n");
 482         } else {
 483                 index[0] = 0;
 484                 index[1] = 1;
 485         }
 486
 487         if (state->vpll2_b && state->vpll_changed[1]) {
 488                 NVWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0,
 489                         fp_debug_0[index[1]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 490
 491                 /* Wait for the situation to stabilise */
 492                 usleep(5000);
 493
 494                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 495                 /* for vpll2 change bits 18 and 19 are disabled */
 496                 reg_c040 &= ~(0x3 << 18);
 497                 nvWriteMC(pNv, 0xc040, reg_c040);
 498
 499                 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 500                 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 501
 502                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2, state->vpll2_a);
 503                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 504
 505                 ErrorF("writing pllsel %08X\n", state->pllsel);
 506                 /* Don't turn vpll1 off. */
 507                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
 508
 509                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_580, state->reg580);
 510                 ErrorF("writing reg580 %08X\n", state->reg580);
 511
 512                 /* We need to wait a while */
 513                 usleep(5000);
 514                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 515
 516                 NVWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[1]]);
 517
 518                 /* Wait for the situation to stabilise */
 519                 usleep(5000);
 520         }
 521
 522         if (state->vpll1_b && state->vpll_changed[0]) {
 523                 NVWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0,
 524                         fp_debug_0[index[0]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 525
 526                 /* Wait for the situation to stabilise */
 527                 usleep(5000);
 528
 529                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 530                 /* for vpll2 change bits 16 and 17 are disabled */
 531                 reg_c040 &= ~(0x3 << 16);
 532                 nvWriteMC(pNv, 0xc040, reg_c040);
 533
 534                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 535                 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 536
 537                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL, state->vpll1_a);
 538                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B, state->vpll1_b);
 539
 540                 ErrorF("writing pllsel %08X\n", state->pllsel);
 541                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
 542
 543                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_580, state->reg580);
 544                 ErrorF("writing reg580 %08X\n", state->reg580);
 545
 546                 /* We need to wait a while */
 547                 usleep(5000);
 548                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 549
 550                 NVWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[0]]);
 551
 552                 /* Wait for the situation to stabilise */
 553                 usleep(5000);
 554         }
 555
 556         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 557         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, state->sel_clk);
 558
 559         ErrorF("writing reg594 %08X\n", state->reg594);
 560         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_594, state->reg594);
 561
 562         /* All clocks have been set at this point. */
 563         state->vpll_changed[0] = FALSE;
 564         state->vpll_changed[1] = FALSE;
 565 }
 566
 567 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 568 {
 569         state->vpll1_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL);
 570         if (pNv->twoHeads) {
 571                 state->vpll2_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2);
 572         }
 573         if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 574                 state->vpll1_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B);
 575                 state->vpll2_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B);
 576         }
 577         state->pllsel = NVReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT);
 578         state->sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
 579 }
 580
 581
 582 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 583 {
 584         /* This sequence is important, the NV28 is very sensitive in this area. */
 585         /* Keep pllsel last and sel_clk first. */
 586         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 587         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, state->sel_clk);
 588
 589         if (state->vpll2_a && state->vpll_changed[1]) {
 590                 if (pNv->twoHeads) {
 591                         ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 592                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2, state->vpll2_a);
 593                 }
 594                 if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 595                         ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 596                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 597                 }
 598         }
 599
 600         if (state->vpll1_a && state->vpll_changed[0]) {
 601                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 602                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL, state->vpll1_a);
 603                 if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 604                         ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 605                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B, state->vpll1_b);
 606                 }
 607         }
 608
 609         ErrorF("writing pllsel %08X\n", state->pllsel);
 610         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
 611
 612         /* All clocks have been set at this point. */
 613         state->vpll_changed[0] = FALSE;
 614         state->vpll_changed[1] = FALSE;
 615 }
 616
 617 static void nv_crtc_mode_set_sel_clk(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 618 {
 619         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 620         NVPtr pNv = NVPTR(crtc->scrn);
 621         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 622         NVOutputPrivatePtr nv_output;
 623         int i;
 624
 625         /* Don't change SEL_CLK on NV0x/NV1x/NV2x cards */
 626         if (pNv->Architecture < NV_ARCH_30) {
 627                 state->sel_clk = pNv->misc_info.sel_clk;
 628                 return;
 629         }
 630
 631         /* SEL_CLK is only used on the primary ramdac */
 632         /* This seems to be needed to select the proper clocks, otherwise bad things happen */
 633         if (!state->sel_clk)
 634                 state->sel_clk = pNv->misc_info.sel_clk & ~(0xf << 16);
 635
 636         if (!output)
 637                 return;
 638         nv_output = output->driver_private;
 639
 640         /* Only let digital outputs mess further with SEL_CLK, otherwise strange output routings may mess it up. */
 641         if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS) {
 642                 Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
 643
 644                 state->sel_clk &= ~(0xf << 16);
 645                 /* Even with two dvi, this should not conflict. */
 646                 if (crossed_clocks)
 647                         state->sel_clk |= (0x1 << 16);
 648                 else
 649                         state->sel_clk |= (0x4 << 16);
 650
 651                 /* nv30:
 652                  *      bit 0           NVClk spread spectrum on/off
 653                  *      bit 2           MemClk spread spectrum on/off
 654                  *      bit 4           PixClk1 spread spectrum on/off
 655                  *      bit 6           PixClk2 spread spectrum on/off
 656                  *
 657                  * nv40 (observations from bios behaviour and mmio traces):
 658                  *      bit 4           seems to get set when output is on head A - likely related to PixClk1
 659                  *      bit 6           seems to get set when output is on head B - likely related to PixClk2
 660                  *      bits 5&7        set as for bits 4&6, but do not appear on cards using 4&6
 661                  *
 662                  *      bits 8&10       seen on dual dvi outputs; possibly means "bits 4&6, dual dvi"
 663                  *
 664                  *      Note that the circumstances for setting the bits at all is unclear
 665                  */
 666                 if (pNv->Architecture == NV_ARCH_40) {
 667                         for (i = 1; i <= 2; i++) {
 668                                 uint32_t var = (state->sel_clk >> 4*i) & 0xf;
 669                                 int shift = 0; /* assume (var & 0x5) by default */
 670
 671                                 if (!var)
 672                                         continue;
 673                                 if (var & 0xa)
 674                                         shift = 1;
 675
 676                                 state->sel_clk &= ~(0xf << 4*i);
 677                                 if (crossed_clocks)
 678                                         state->sel_clk |= (0x4 << (4*i + shift));
 679                                 else
 680                                         state->sel_clk |= (0x1 << (4*i + shift));
 681                         }
 682                 }
 683         }
 684 }
 685
 686 /*
 687  * Calculate extended mode parameters (SVGA) and save in a
 688  * mode state structure.
 689  * State is not specific to a single crtc, but shared.
 690  */
 691 void nv_crtc_calc_state_ext(
 692         xf86CrtcPtr             crtc,
 693         DisplayModePtr  mode,
 694         int                             bpp,
 695         int                             DisplayWidth, /* Does this change after setting the mode? */
 696         int                             CrtcHDisplay,
 697         int                             CrtcVDisplay,
 698         int                             dotClock,
 699         int                             flags
 700 )
 701 {
 702         ScrnInfoPtr pScrn = crtc->scrn;
 703         uint32_t pixelDepth, VClk = 0;
 704         uint32_t CursorStart;
 705         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 706         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 707         NVCrtcRegPtr regp;
 708         NVPtr pNv = NVPTR(pScrn);
 709         RIVA_HW_STATE *state;
 710         int num_crtc_enabled, i;
 711         uint32_t old_clock_a = 0, old_clock_b = 0;
 712         struct pll_lims pll_lim;
 713         int NM1 = 0xbeef, NM2 = 0xdead, log2P = 0;
 714         uint32_t g70_pll_special_bits = 0;
 715         Bool nv4x_single_stage_pll_mode = FALSE;
 716
 717         state = &pNv->ModeReg;
 718
 719         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 720
 721         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 722         NVOutputPrivatePtr nv_output = NULL;
 723         if (output)
 724                 nv_output = output->driver_private;
 725
 726         /* Store old clock. */
 727         if (nv_crtc->head == 1) {
 728                 old_clock_a = state->vpll2_a;
 729                 old_clock_b = state->vpll2_b;
 730         } else {
 731                 old_clock_a = state->vpll1_a;
 732                 old_clock_b = state->vpll1_b;
 733         }
 734
 735         /*
 736          * Extended RIVA registers.
 737          */
 738         /* This is pitch related, not mode related. */
 739         pixelDepth = (bpp + 1)/8;
 740
 741         if (nv_crtc->head == 0) {
 742                 if (!get_pll_limits(pScrn, VPLL1, &pll_lim))
 743                         return;
 744         } else
 745                 if (!get_pll_limits(pScrn, VPLL2, &pll_lim))
 746                         return;
 747
 748         if (pNv->twoStagePLL) {
 749                 if (dotClock < pll_lim.vco1.maxfreq && pNv->NVArch > 0x40) { /* use a single VCO */
 750                         nv4x_single_stage_pll_mode = TRUE;
 751                         /* Turn the second set of divider and multiplier off */
 752                         /* Bogus data, the same nvidia uses */
 753                         NM2 = 0x11f;
 754                         VClk = getMNP_single(pScrn, &pll_lim, dotClock, &NM1, &log2P);
 755                 } else
 756                         VClk = getMNP_double(pScrn, &pll_lim, dotClock, &NM1, &NM2, &log2P);
 757         } else
 758                 VClk = getMNP_single(pScrn, &pll_lim, dotClock, &NM1, &log2P);
 759
 760         /* Are these all the (relevant) G70 cards? */
 761         if (pNv->NVArch == 0x4B || pNv->NVArch == 0x46 || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
 762                 /* This is a big guess, but should be reasonable until we can narrow it down. */
 763                 /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
 764                 if (nv4x_single_stage_pll_mode)
 765                         g70_pll_special_bits = 0x1;
 766                 else
 767                         g70_pll_special_bits = 0x3;
 768         }
 769
 770         if (pNv->NVArch == 0x30)
 771                 /* See nvregisters.xml for details. */
 772                 state->pll = log2P << 16 | NM1 | (NM2 & 7) << 4 | ((NM2 >> 8) & 7) << 19 | ((NM2 >> 11) & 3) << 24 | NV30_RAMDAC_ENABLE_VCO2;
 773         else
 774                 state->pll = g70_pll_special_bits << 30 | log2P << 16 | NM1;
 775         state->pllB = NV31_RAMDAC_ENABLE_VCO2 | NM2;
 776
 777         /* Does register 0x580 already have a value? */
 778         if (!state->reg580)
 779                 state->reg580 = pNv->misc_info.ramdac_0_reg_580;
 780         if (nv4x_single_stage_pll_mode) {
 781                 if (nv_crtc->head == 0)
 782                         state->reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 783                 else
 784                         state->reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 785         } else {
 786                 if (nv_crtc->head == 0)
 787                         state->reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
 788                 else
 789                         state->reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
 790         }
 791
 792         if (!pNv->twoStagePLL || nv4x_single_stage_pll_mode)
 793                 ErrorF("vpll: n %d m %d log2p %d\n", NM1 >> 8, NM1 & 0xff, log2P);
 794         else
 795                 ErrorF("vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", NM1 >> 8, NM2 >> 8, NM1 & 0xff, NM2 & 0xff, log2P);
 796
 797         if (nv_crtc->head == 1) {
 798                 state->vpll2_a = state->pll;
 799                 state->vpll2_b = state->pllB;
 800         } else {
 801                 state->vpll1_a = state->pll;
 802                 state->vpll1_b = state->pllB;
 803         }
 804
 805         /* always reset vpll, just to be sure. */
 806         state->vpll_changed[nv_crtc->head] = TRUE;
 807
 808         switch (pNv->Architecture) {
 809         case NV_ARCH_04:
 810                 nv4UpdateArbitrationSettings(VClk,
 811                                                 pixelDepth * 8,
 812                                                 &(state->arbitration0),
 813                                                 &(state->arbitration1),
 814                                                 pNv);
 815                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
 816                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
 817                 if (flags & V_DBLSCAN)
 818                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 819                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
 820                 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
 821                 state->config = 0x00001114;
 822                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 823                 break;
 824         case NV_ARCH_10:
 825         case NV_ARCH_20:
 826         case NV_ARCH_30:
 827         default:
 828                 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
 829                         ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
 830                         state->arbitration0 = 128;
 831                         state->arbitration1 = 0x0480;
 832                 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
 833                         ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
 834                         nForceUpdateArbitrationSettings(VClk,
 835                                                 pixelDepth * 8,
 836                                                 &(state->arbitration0),
 837                                                 &(state->arbitration1),
 838                                                 pNv);
 839                 } else if (pNv->Architecture < NV_ARCH_30) {
 840                         nv10UpdateArbitrationSettings(VClk,
 841                                                 pixelDepth * 8,
 842                                                 &(state->arbitration0),
 843                                                 &(state->arbitration1),
 844                                                 pNv);
 845                 } else {
 846                         nv30UpdateArbitrationSettings(pNv,
 847                                                 &(state->arbitration0),
 848                                                 &(state->arbitration1));
 849                 }
 850
 851                 if (nv_crtc->head == 1) {
 852                         CursorStart = pNv->Cursor2->offset;
 853                 } else {
 854                         CursorStart = pNv->Cursor->offset;
 855                 }
 856
 857                 if (!NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 858                         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
 859                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
 860                         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
 861                 } else {
 862                         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x0;
 863                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0x0;
 864                         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x0;
 865                 }
 866
 867                 if (flags & V_DBLSCAN)
 868                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 869
 870                 state->config   = nvReadFB(pNv, NV_PFB_CFG0);
 871                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 872                 break;
 873         }
 874
 875         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 876                 /* This is a bit of a guess. */
 877                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] |= 0xB8;
 878         }
 879
 880         /* okay do we have 2 CRTCs running ? */
 881         num_crtc_enabled = 0;
 882         for (i = 0; i < xf86_config->num_crtc; i++) {
 883                 if (xf86_config->crtc[i]->enabled) {
 884                         num_crtc_enabled++;
 885                 }
 886         }
 887
 888         ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
 889
 890         /* Are we crosswired? */
 891         if (output && nv_crtc->head != nv_output->preferred_output) {
 892                 state->crosswired = TRUE;
 893         } else
 894                 state->crosswired = FALSE;
 895
 896         /* The NV40 seems to have more similarities to NV3x than other cards. */
 897         if (pNv->NVArch < 0x41) {
 898                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL;
 899                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL;
 900         }
 901
 902         if (nv_crtc->head == 1) {
 903                 if (!nv4x_single_stage_pll_mode) {
 904                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 905                 } else {
 906                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 907                 }
 908                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
 909         } else {
 910                 if (!nv4x_single_stage_pll_mode) {
 911                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 912                 } else {
 913                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 914                 }
 915                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
 916         }
 917
 918         /* The blob uses this always, so let's do the same */
 919         if (pNv->Architecture == NV_ARCH_40) {
 920                 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
 921         }
 922
 923         /* The primary output resource doesn't seem to care */
 924         if (output && pNv->Architecture == NV_ARCH_40 && nv_output->output_resource == 1) { /* This is the "output" */
 925                 /* non-zero values are for analog, don't know about tv-out and the likes */
 926                 if (output && nv_output->type != OUTPUT_ANALOG) {
 927                         state->reg594 = 0x0;
 928                 } else if (output) {
 929                         /* Are we a flexible output? */
 930                         if (ffs(pNv->dcb_table.entry[nv_output->dcb_entry].or) & OUTPUT_0) {
 931                                 state->reg594 = 0x1;
 932                                 pNv->restricted_mode = FALSE;
 933                         } else {
 934                                 state->reg594 = 0x0;
 935                                 pNv->restricted_mode = TRUE;
 936                         }
 937
 938                         /* More values exist, but they seem related to the 3rd dac (tv-out?) somehow */
 939                         /* bit 16-19 are bits that are set on some G70 cards */
 940                         /* Those bits are also set to the 3rd OUTPUT register */
 941                         if (nv_crtc->head == 1) {
 942                                 state->reg594 |= 0x100;
 943                         }
 944                 }
 945         }
 946
 947         regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
 948         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
 949         if (pNv->Architecture >= NV_ARCH_30) {
 950                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
 951         }
 952
 953         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 954                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = ((CrtcHDisplay/16) & 0x700) >> 3;
 955         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 956                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((CrtcHDisplay*bpp)/64) & 0x700) >> 3;
 957         } else { /* framebuffer can be larger than crtc scanout area. */
 958                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
 959         }
 960         regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
 961 }
 962
 963 static void
 964 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
 965 {
 966         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 967
 968         ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->head, mode);
 969
 970         if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */
 971                 return;
 972
 973         nv_crtc->last_dpms = mode;
 974
 975         ScrnInfoPtr pScrn = crtc->scrn;
 976         NVPtr pNv = NVPTR(pScrn);
 977         unsigned char seq1 = 0, crtc17 = 0;
 978         unsigned char crtc1A;
 979
 980         if (pNv->twoHeads)
 981                 NVCrtcSetOwner(crtc);
 982
 983         crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
 984         switch(mode) {
 985                 case DPMSModeStandby:
 986                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
 987                 seq1 = 0x20;
 988                 crtc17 = 0x80;
 989                 crtc1A |= 0x80;
 990                 break;
 991         case DPMSModeSuspend:
 992                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
 993                 seq1 = 0x20;
 994                 crtc17 = 0x80;
 995                 crtc1A |= 0x40;
 996                 break;
 997         case DPMSModeOff:
 998                 /* Screen: Off; HSync: Off, VSync: Off */
 999                 seq1 = 0x20;
1000                 crtc17 = 0x00;
1001                 crtc1A |= 0xC0;
1002                 break;
1003         case DPMSModeOn:
1004         default:
1005                 /* Screen: On; HSync: On, VSync: On */
1006                 seq1 = 0x00;
1007                 crtc17 = 0x80;
1008                 break;
1009         }
1010
1011         NVVgaSeqReset(crtc, TRUE);
1012         /* Each head has it's own sequencer, so we can turn it off when we want */
1013         seq1 |= (NVReadVgaSeq(crtc, 0x01) & ~0x20);
1014         NVWriteVgaSeq(crtc, 0x1, seq1);
1015         crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
1016         usleep(10000);
1017         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
1018         NVVgaSeqReset(crtc, FALSE);
1019
1020         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
1021
1022         /* I hope this is the right place */
1023         if (crtc->enabled && mode == DPMSModeOn) {
1024                 pNv->crtc_active[nv_crtc->head] = TRUE;
1025         } else {
1026                 pNv->crtc_active[nv_crtc->head] = FALSE;
1027         }
1028 }
1029
1030 static Bool
1031 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
1032                      DisplayModePtr adjusted_mode)
1033 {
1034         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1035         ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->head);
1036
1037         return TRUE;
1038 }
1039
1040 static void
1041 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1042 {
1043         ScrnInfoPtr pScrn = crtc->scrn;
1044         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1045         NVCrtcRegPtr regp;
1046         NVPtr pNv = NVPTR(pScrn);
1047         NVFBLayout *pLayout = &pNv->CurrentLayout;
1048         int depth = pScrn->depth;
1049
1050         /* This is pitch/memory size related. */
1051         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE))
1052                 depth = pNv->console_mode[nv_crtc->head].bpp;
1053
1054         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1055
1056         /* Calculate our timings */
1057         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
1058         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
1059         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
1060         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
1061         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
1062         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
1063         int vertDisplay         = mode->CrtcVDisplay                    - 1;
1064         int vertStart           = mode->CrtcVSyncStart          - 1;
1065         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
1066         int vertTotal           = mode->CrtcVTotal                      - 2;
1067         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
1068         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
1069
1070         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1071         NVOutputPrivatePtr nv_output = NULL;
1072         if (output)
1073                 nv_output = output->driver_private;
1074
1075         ErrorF("Mode clock: %d\n", mode->Clock);
1076         ErrorF("Adjusted mode clock: %d\n", adjusted_mode->Clock);
1077
1078         /* Reverted to what nv did, because that works for all resolutions on flatpanels */
1079         if (output && (nv_output->type == OUTPUT_LVDS || nv_output->type == OUTPUT_TMDS)) {
1080                 vertStart = vertTotal - 3;
1081                 vertEnd = vertTotal - 2;
1082                 vertBlankStart = vertStart;
1083                 horizStart = horizTotal - 5;
1084                 horizEnd = horizTotal - 2;
1085                 horizBlankEnd = horizTotal + 4;
1086                 if (pNv->overlayAdaptor && pNv->Architecture >= NV_ARCH_10) {
1087                         /* This reportedly works around Xv some overlay bandwidth problems*/
1088                         horizTotal += 2;
1089                 }
1090         }
1091
1092         if (mode->Flags & V_INTERLACE)
1093                 vertTotal |= 1;
1094
1095         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
1096         ErrorF("horizStart: 0x%X \n", horizStart);
1097         ErrorF("horizEnd: 0x%X \n", horizEnd);
1098         ErrorF("horizTotal: 0x%X \n", horizTotal);
1099         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
1100         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
1101         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
1102         ErrorF("vertStart: 0x%X \n", vertStart);
1103         ErrorF("vertEnd: 0x%X \n", vertEnd);
1104         ErrorF("vertTotal: 0x%X \n", vertTotal);
1105         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
1106         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
1107
1108         /*
1109         * compute correct Hsync & Vsync polarity
1110         */
1111         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
1112                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
1113
1114                 regp->MiscOutReg = 0x23;
1115                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
1116                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
1117         } else {
1118                 int VDisplay = mode->VDisplay;
1119                 if (mode->Flags & V_DBLSCAN)
1120                         VDisplay *= 2;
1121                 if (mode->VScan > 1)
1122                         VDisplay *= mode->VScan;
1123                 if (VDisplay < 400) {
1124                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
1125                 } else if (VDisplay < 480) {
1126                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
1127                 } else if (VDisplay < 768) {
1128                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
1129                 } else {
1130                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
1131                 }
1132         }
1133
1134         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
1135
1136         /*
1137         * Time Sequencer
1138         */
1139         regp->Sequencer[0] = 0x00;
1140         /* 0x20 disables the sequencer */
1141         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1142                 if (mode->HDisplay == 720) {
1143                         regp->Sequencer[1] = 0x21; /* enable 9/8 mode */
1144                 } else {
1145                         regp->Sequencer[1] = 0x20;
1146                 }
1147         } else {
1148                 if (mode->Flags & V_CLKDIV2) {
1149                         regp->Sequencer[1] = 0x29;
1150                 } else {
1151                         regp->Sequencer[1] = 0x21;
1152                 }
1153         }
1154         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1155                 regp->Sequencer[2] = 0x03; /* select 2 out of 4 planes */
1156         } else {
1157                 regp->Sequencer[2] = 0x0F;
1158         }
1159         regp->Sequencer[3] = 0x00;                     /* Font select */
1160         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1161                 regp->Sequencer[4] = 0x02;
1162         } else {
1163                 regp->Sequencer[4] = 0x0E;                             /* Misc */
1164         }
1165
1166         /*
1167         * CRTC Controller
1168         */
1169         regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
1170         regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
1171         regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
1172         regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0)
1173                                 | SetBit(7);
1174         regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
1175         regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
1176                                 | SetBitField(horizEnd,4:0,4:0);
1177         regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
1178         regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
1179                                 | SetBitField(vertDisplay,8:8,1:1)
1180                                 | SetBitField(vertStart,8:8,2:2)
1181                                 | SetBitField(vertBlankStart,8:8,3:3)
1182                                 | SetBit(4)
1183                                 | SetBitField(vertTotal,9:9,5:5)
1184                                 | SetBitField(vertDisplay,9:9,6:6)
1185                                 | SetBitField(vertStart,9:9,7:7);
1186         regp->CRTC[NV_VGA_CRTCX_PRROWSCN]  = 0x00;
1187         regp->CRTC[NV_VGA_CRTCX_MAXSCLIN]  = SetBitField(vertBlankStart,9:9,5:5)
1188                                 | SetBit(6)
1189                                 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00)
1190                                 | (NVMatchModePrivate(mode, NV_MODE_VGA) ? 0xF : 0x00); /* 8x15 chars */
1191         if (NVMatchModePrivate(mode, NV_MODE_VGA)) { /* Were do these cursor offsets come from? */
1192                 regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0xD; /* start scanline */
1193                 regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0xE; /* end scanline */
1194         } else {
1195                 regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0x00;
1196                 regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0x00;
1197         }
1198         regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00;
1199         regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
1200         regp->CRTC[0xe] = 0x00;
1201         regp->CRTC[0xf] = 0x00;
1202         regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
1203         /* What is the meaning of bit5, it is empty in the vga spec. */
1204         regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) |
1205                                                                         (NVMatchModePrivate(mode, NV_MODE_VGA) ? 0 : SetBit(5));
1206         regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
1207         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1208                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = (mode->CrtcHDisplay/16);
1209         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1210                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((mode->CrtcHDisplay*depth)/64);
1211         } else { /* framebuffer can be larger than crtc scanout area. */
1212                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
1213         }
1214         if (depth == 4) { /* How can these values be calculated? */
1215                 regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x1F;
1216         } else {
1217                 regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x00;
1218         }
1219         regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
1220         regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
1221         /* 0x80 enables the sequencer, we don't want that */
1222         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1223                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xA3 & ~0x80;
1224         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1225                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xE3 & ~0x80;
1226         } else {
1227                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80;
1228         }
1229         regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
1230
1231         /*
1232          * Some extended CRTC registers (they are not saved with the rest of the vga regs).
1233          */
1234
1235         regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
1236                                 | SetBitField(vertBlankStart,10:10,3:3)
1237                                 | SetBitField(vertStart,10:10,2:2)
1238                                 | SetBitField(vertDisplay,10:10,1:1)
1239                                 | SetBitField(vertTotal,10:10,0:0);
1240
1241         regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
1242                                 | SetBitField(horizDisplay,8:8,1:1)
1243                                 | SetBitField(horizBlankStart,8:8,2:2)
1244                                 | SetBitField(horizStart,8:8,3:3);
1245
1246         regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
1247                                 | SetBitField(vertDisplay,11:11,2:2)
1248                                 | SetBitField(vertStart,11:11,4:4)
1249                                 | SetBitField(vertBlankStart,11:11,6:6);
1250
1251         if(mode->Flags & V_INTERLACE) {
1252                 horizTotal = (horizTotal >> 1) & ~1;
1253                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
1254                 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
1255         } else {
1256                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff;  /* interlace off */
1257         }
1258
1259         /*
1260         * Graphics Display Controller
1261         */
1262         regp->Graphics[0] = 0x00;
1263         regp->Graphics[1] = 0x00;
1264         regp->Graphics[2] = 0x00;
1265         regp->Graphics[3] = 0x00;
1266         regp->Graphics[4] = 0x00;
1267         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1268                 regp->Graphics[5] = 0x10;
1269                 regp->Graphics[6] = 0x0E; /* map 32k mem */
1270                 regp->Graphics[7] = 0x00;
1271         } else {
1272                 regp->Graphics[5] = 0x40; /* 256 color mode */
1273                 regp->Graphics[6] = 0x05; /* map 64k mem + graphic mode */
1274                 regp->Graphics[7] = 0x0F;
1275         }
1276         regp->Graphics[8] = 0xFF;
1277
1278         regp->Attribute[0]  = 0x00; /* standard colormap translation */
1279         regp->Attribute[1]  = 0x01;
1280         regp->Attribute[2]  = 0x02;
1281         regp->Attribute[3]  = 0x03;
1282         regp->Attribute[4]  = 0x04;
1283         regp->Attribute[5]  = 0x05;
1284         regp->Attribute[6]  = 0x06;
1285         regp->Attribute[7]  = 0x07;
1286         regp->Attribute[8]  = 0x08;
1287         regp->Attribute[9]  = 0x09;
1288         regp->Attribute[10] = 0x0A;
1289         regp->Attribute[11] = 0x0B;
1290         regp->Attribute[12] = 0x0C;
1291         regp->Attribute[13] = 0x0D;
1292         regp->Attribute[14] = 0x0E;
1293         regp->Attribute[15] = 0x0F;
1294         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1295                 regp->Attribute[16] = 0x0C; /* Line Graphics Enable + Blink enable */
1296         } else {
1297                 regp->Attribute[16] = 0x01; /* Enable graphic mode */
1298         }
1299         /* Non-vga */
1300         regp->Attribute[17] = 0x00;
1301         regp->Attribute[18] = 0x0F; /* enable all color planes */
1302         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1303                 regp->Attribute[19] = 0x08; /* shift bits by 8 */
1304         } else {
1305                 regp->Attribute[19] = 0x00;
1306         }
1307         regp->Attribute[20] = 0x00;
1308 }
1309
1310 /**
1311  * Sets up registers for the given mode/adjusted_mode pair.
1312  *
1313  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1314  *
1315  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1316  * be easily turned on/off after this.
1317  */
1318 static void
1319 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1320 {
1321         ScrnInfoPtr pScrn = crtc->scrn;
1322         NVPtr pNv = NVPTR(pScrn);
1323         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1324         NVFBLayout *pLayout = &pNv->CurrentLayout;
1325         NVCrtcRegPtr regp, savep;
1326         uint32_t i, depth;
1327         Bool is_fp = FALSE;
1328         Bool is_lvds = FALSE;
1329
1330         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1331         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1332
1333         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1334         NVOutputPrivatePtr nv_output = NULL;
1335         if (output) {
1336                 nv_output = output->driver_private;
1337
1338                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1339                         is_fp = TRUE;
1340
1341                 if (nv_output->type == OUTPUT_LVDS)
1342                         is_lvds = TRUE;
1343         }
1344
1345         /* Registers not directly related to the (s)vga mode */
1346
1347         /* bit2 = 0 -> fine pitched crtc granularity */
1348         /* The rest disables double buffering on CRTC access */
1349         regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
1350
1351         if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
1352                 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1353                 if (nv_crtc->head == 0) {
1354                         regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1355                 }
1356
1357                 if (is_fp) {
1358                         regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0);
1359                         if (!NVMatchModePrivate(mode, NV_MODE_VGA)) {
1360                                 regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 1);
1361                         }
1362                 }
1363         } else {
1364                 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
1365                 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
1366         }
1367
1368         /* Sometimes 0x10 is used, what is this? */
1369         regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1370         /* Some kind of tmds switch for older cards */
1371         if (pNv->Architecture < NV_ARCH_40) {
1372                 regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
1373         }
1374
1375         /*
1376         * Initialize DAC palette.
1377         * Will only be written when depth != 8.
1378         */
1379         for (i = 0; i < 256; i++) {
1380                 regp->DAC[i*3] = i;
1381                 regp->DAC[(i*3)+1] = i;
1382                 regp->DAC[(i*3)+2] = i;
1383         }
1384
1385         /*
1386         * Calculate the extended registers.
1387         */
1388
1389         if (pLayout->depth < 24) {
1390                 depth = pLayout->depth;
1391         } else {
1392                 depth = 32;
1393         }
1394
1395         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1396                 /* bpp is pitch related. */
1397                 depth = pNv->console_mode[nv_crtc->head].bpp;
1398         }
1399
1400         /* What is the meaning of this register? */
1401         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1402         regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
1403
1404         regp->head = 0;
1405
1406         /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1407         /* But what are those special conditions? */
1408         if (pNv->Architecture <= NV_ARCH_30) {
1409                 if (is_fp) {
1410                         if(nv_crtc->head == 1) {
1411                                 regp->head |= NV_CRTC_FSEL_FPP1;
1412                         } else if (pNv->twoHeads) {
1413                                 regp->head |= NV_CRTC_FSEL_FPP2;
1414                         }
1415                 }
1416         } else {
1417                 /* Most G70 cards have FPP2 set on the secondary CRTC. */
1418                 if (nv_crtc->head == 1 && pNv->NVArch > 0x44) {
1419                         regp->head |= NV_CRTC_FSEL_FPP2;
1420                 }
1421         }
1422
1423         /* Except for rare conditions I2C is enabled on the primary crtc */
1424         if (nv_crtc->head == 0) {
1425                 regp->head |= NV_CRTC_FSEL_I2C;
1426         }
1427
1428         /* Set overlay to desired crtc. */
1429         if (pNv->overlayAdaptor) {
1430                 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(pNv);
1431                 if (pPriv->overlayCRTC == nv_crtc->head)
1432                         regp->head |= NV_CRTC_FSEL_OVERLAY;
1433         }
1434
1435         /* This is not what nv does, but it is what the blob does (for nv4x at least) */
1436         /* This fixes my cursor corruption issue */
1437         regp->cursorConfig = 0x0;
1438         if(mode->Flags & V_DBLSCAN)
1439                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_DOUBLE_SCAN;
1440         if (pNv->alphaCursor && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1441                 regp->cursorConfig |=   (NV_CRTC_CURSOR_CONFIG_32BPP |
1442                                                         NV_CRTC_CURSOR_CONFIG_64PIXELS |
1443                                                         NV_CRTC_CURSOR_CONFIG_64LINES |
1444                                                         NV_CRTC_CURSOR_CONFIG_ALPHA_BLEND);
1445         } else {
1446                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_32LINES;
1447         }
1448
1449         /* Unblock some timings */
1450         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1451         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1452
1453         /* What is the purpose of this register? */
1454         /* 0x14 may be disabled? */
1455         regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1456
1457         /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
1458         if (is_lvds) {
1459                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x11;
1460         } else if (is_fp) {
1461                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1462         } else {
1463                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1464         }
1465
1466         /* These values seem to vary */
1467         /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
1468         regp->CRTC[NV_VGA_CRTCX_SCRATCH4] = savep->CRTC[NV_VGA_CRTCX_SCRATCH4];
1469
1470         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1471                 regp->CRTC[NV_VGA_CRTCX_45] = 0x0;
1472         } else {
1473                 regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1474         }
1475
1476         /* What does this do?:
1477          * bit0: crtc0
1478          * bit6: lvds
1479          * bit7: lvds + tmds (only in X)
1480          */
1481         if (nv_crtc->head == 0)
1482                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x1;
1483         else
1484                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x0;
1485
1486         if (is_lvds)
1487                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x40;
1488
1489         if (is_fp && !NVMatchModePrivate(mode, NV_MODE_VGA))
1490                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x80;
1491
1492         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) { /* we need consistent restore. */
1493                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[nv_crtc->head];
1494         } else {
1495                 /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1.*/
1496                 if (nv_crtc->head == 1) {
1497                         regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[0];
1498                 } else {
1499                         regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[0] + 4;
1500                 }
1501         }
1502
1503         if (pNv->twoHeads)
1504                 /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1505                 regp->gpio_ext = NVReadCRTC(pNv, 0, NV_PCRTC_GPIO_EXT);
1506
1507         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1508                 regp->unk830 = 0;
1509                 regp->unk834 = 0;
1510         } else {
1511                 regp->unk830 = mode->CrtcVDisplay - 3;
1512                 regp->unk834 = mode->CrtcVDisplay - 1;
1513         }
1514
1515         if (pNv->twoHeads)
1516                 /* This is what the blob does */
1517                 regp->unk850 = NVReadCRTC(pNv, 0, NV_CRTC_0850);
1518
1519         /* Never ever modify gpio, unless you know very well what you're doing */
1520         regp->gpio = NVReadCRTC(pNv, 0, NV_CRTC_GPIO);
1521
1522         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1523                 regp->config = 0x0; /* VGA mode */
1524         } else {
1525                 regp->config = 0x2; /* HSYNC mode */
1526         }
1527
1528         /* Some misc regs */
1529         regp->CRTC[NV_VGA_CRTCX_43] = 0x1;
1530         if (pNv->Architecture == NV_ARCH_40) {
1531                 regp->CRTC[NV_VGA_CRTCX_85] = 0xFF;
1532                 regp->CRTC[NV_VGA_CRTCX_86] = 0x1;
1533         }
1534
1535         /*
1536          * Calculate the state that is common to all crtc's (stored in the state struct).
1537          */
1538         ErrorF("crtc %d %d %d\n", nv_crtc->head, mode->CrtcHDisplay, pScrn->displayWidth);
1539         nv_crtc_calc_state_ext(crtc,
1540                                 mode,
1541                                 depth,
1542                                 pScrn->displayWidth,
1543                                 mode->CrtcHDisplay,
1544                                 mode->CrtcVDisplay,
1545                                 adjusted_mode->Clock,
1546                                 mode->Flags);
1547
1548         /* Enable slaved mode */
1549         if (is_fp) {
1550                 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1551         }
1552 }
1553
1554 static void
1555 nv_crtc_mode_set_ramdac_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1556 {
1557         ScrnInfoPtr pScrn = crtc->scrn;
1558         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1559         NVCrtcRegPtr regp, savep;
1560         NVPtr pNv = NVPTR(pScrn);
1561         NVFBLayout *pLayout = &pNv->CurrentLayout;
1562         Bool is_fp = FALSE;
1563         Bool is_lvds = FALSE;
1564         float aspect_ratio, panel_ratio;
1565         uint32_t h_scale, v_scale;
1566
1567         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1568         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1569
1570         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1571         NVOutputPrivatePtr nv_output = NULL;
1572         if (output) {
1573                 nv_output = output->driver_private;
1574
1575                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1576                         is_fp = TRUE;
1577
1578                 if (nv_output->type == OUTPUT_LVDS)
1579                         is_lvds = TRUE;
1580         }
1581
1582         if (is_fp) {
1583                 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
1584                 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
1585                 /* This is what the blob does. */
1586                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HSyncStart - 75 - 1;
1587                 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
1588                 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
1589                 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
1590                 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
1591
1592                 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
1593                 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
1594                 /* This is what the blob does. */
1595                 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VTotal - 5 - 1;
1596                 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
1597                 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
1598                 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
1599                 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
1600
1601                 ErrorF("Horizontal:\n");
1602                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
1603                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
1604                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
1605                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
1606                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
1607                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
1608                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
1609
1610                 ErrorF("Vertical:\n");
1611                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
1612                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
1613                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
1614                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
1615                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
1616                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
1617                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
1618         }
1619
1620         /*
1621         * bit0: positive vsync
1622         * bit4: positive hsync
1623         * bit8: enable center mode
1624         * bit9: enable native mode
1625         * bit24: 12/24 bit interface (12bit=on, 24bit=off)
1626         * bit26: a bit sometimes seen on some g70 cards
1627         * bit28: fp display enable bit
1628         * bit31: set for dual link LVDS
1629         * nv10reg contains a few more things, but i don't quite get what it all means.
1630         */
1631
1632         if (pNv->Architecture >= NV_ARCH_30)
1633                 regp->fp_control[nv_crtc->head] = 0x00100000;
1634         else
1635                 regp->fp_control[nv_crtc->head] = 0x00000000;
1636
1637         /* Deal with vsync/hsync polarity */
1638         /* LVDS screens do set this, but modes with +ve syncs are very rare */
1639         if (is_fp) {
1640                 if (adjusted_mode->Flags & V_PVSYNC)
1641                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
1642                 if (adjusted_mode->Flags & V_PHSYNC)
1643                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
1644         } else {
1645                 /* The blob doesn't always do this, but often */
1646                 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_VSYNC_DISABLE;
1647                 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_HSYNC_DISABLE;
1648         }
1649
1650         if (is_fp) {
1651                 if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) /* seems to be used almost always */
1652                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1653                 else if (nv_output->scaling_mode == SCALE_PANEL) /* panel needs to scale */
1654                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
1655                 /* This is also true for panel scaling, so we must put the panel scale check first */
1656                 else if (mode->Clock == adjusted_mode->Clock) /* native mode */
1657                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
1658                 else /* gpu needs to scale */
1659                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1660         }
1661
1662         if (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
1663                 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
1664
1665         /* If the special bit exists, it exists on both ramdacs */
1666         regp->fp_control[nv_crtc->head] |= NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL) & (1 << 26);
1667
1668         if (is_fp)
1669                 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS;
1670         else
1671                 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE;
1672
1673         Bool lvds_use_straps = pNv->dcb_table.entry[nv_output->dcb_entry].lvdsconf.use_straps_for_mode;
1674         if (is_lvds && ((lvds_use_straps && pNv->VBIOS.fp.dual_link) || (!lvds_use_straps && adjusted_mode->Clock >= pNv->VBIOS.fp.duallink_transition_clk)))
1675                 regp->fp_control[nv_crtc->head] |= (8 << 28);
1676
1677         if (is_fp) {
1678                 ErrorF("Pre-panel scaling\n");
1679                 ErrorF("panel-size:%dx%d\n", nv_output->fpWidth, nv_output->fpHeight);
1680                 panel_ratio = (nv_output->fpWidth)/(float)(nv_output->fpHeight);
1681                 ErrorF("panel_ratio=%f\n", panel_ratio);
1682                 aspect_ratio = (mode->HDisplay)/(float)(mode->VDisplay);
1683                 ErrorF("aspect_ratio=%f\n", aspect_ratio);
1684                 /* Scale factors is the so called 20.12 format, taken from Haiku */
1685                 h_scale = ((1 << 12) * mode->HDisplay)/nv_output->fpWidth;
1686                 v_scale = ((1 << 12) * mode->VDisplay)/nv_output->fpHeight;
1687                 ErrorF("h_scale=%d\n", h_scale);
1688                 ErrorF("v_scale=%d\n", v_scale);
1689
1690                 /* This can override HTOTAL and VTOTAL */
1691                 regp->debug_2 = 0;
1692
1693                 /* We want automatic scaling */
1694                 regp->debug_1 = 0;
1695
1696                 regp->fp_hvalid_start = 0;
1697                 regp->fp_hvalid_end = (nv_output->fpWidth - 1);
1698
1699                 regp->fp_vvalid_start = 0;
1700                 regp->fp_vvalid_end = (nv_output->fpHeight - 1);
1701
1702                 /* 0 = panel scaling */
1703                 if (nv_output->scaling_mode == SCALE_PANEL) {
1704                         ErrorF("Flat panel is doing the scaling.\n");
1705                 } else {
1706                         ErrorF("GPU is doing the scaling.\n");
1707
1708                         if (nv_output->scaling_mode == SCALE_ASPECT) {
1709                                 /* GPU scaling happens automaticly at a ratio of 1.33 */
1710                                 /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
1711                                 if (h_scale != (1 << 12) && (panel_ratio > (aspect_ratio + 0.10))) {
1712                                         uint32_t diff;
1713
1714                                         ErrorF("Scaling resolution on a widescreen panel\n");
1715
1716                                         /* Scaling in both directions needs to the same */
1717                                         h_scale = v_scale;
1718
1719                                         /* Set a new horizontal scale factor and enable testmode (bit12) */
1720                                         regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
1721
1722                                         diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
1723                                         regp->fp_hvalid_start = diff/2;
1724                                         regp->fp_hvalid_end = nv_output->fpWidth - (diff/2) - 1;
1725                                 }
1726
1727                                 /* Same scaling, just for panels with aspect ratio's smaller than 1 */
1728                                 if (v_scale != (1 << 12) && (panel_ratio < (aspect_ratio - 0.10))) {
1729                                         uint32_t diff;
1730
1731                                         ErrorF("Scaling resolution on a portrait panel\n");
1732
1733                                         /* Scaling in both directions needs to the same */
1734                                         v_scale = h_scale;
1735
1736                                         /* Set a new vertical scale factor and enable testmode (bit28) */
1737                                         regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
1738
1739                                         diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
1740                                         regp->fp_vvalid_start = diff/2;
1741                                         regp->fp_vvalid_end = nv_output->fpHeight - (diff/2) - 1;
1742                                 }
1743                         }
1744                 }
1745
1746                 ErrorF("Post-panel scaling\n");
1747         }
1748
1749         if (!is_fp && NVMatchModePrivate(mode, NV_MODE_VGA)) {
1750                 regp->debug_1 = 0x08000800;
1751         }
1752
1753         if (pNv->Architecture >= NV_ARCH_10) {
1754                 /* Only bit that bios and blob set. */
1755                 regp->nv10_cursync = (1<<25);
1756         }
1757
1758         /* These are the common blob values, minus a few fp specific bit's */
1759         /* Let's keep the TMDS pll and fpclock running in all situations */
1760         regp->debug_0[nv_crtc->head] = 0x1101100;
1761
1762         if (is_fp && nv_output->scaling_mode != SCALE_NOSCALE) {
1763                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_XSCALE_ENABLED;
1764                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_YSCALE_ENABLED;
1765         } else if (is_fp) { /* no_scale mode, so we must center it */
1766                 uint32_t diff;
1767
1768                 diff = nv_output->fpWidth - mode->HDisplay;
1769                 regp->fp_hvalid_start = diff/2;
1770                 regp->fp_hvalid_end = (nv_output->fpWidth - diff/2 - 1);
1771
1772                 diff = nv_output->fpHeight - mode->VDisplay;
1773                 regp->fp_vvalid_start = diff/2;
1774                 regp->fp_vvalid_end = (nv_output->fpHeight - diff/2 - 1);
1775         }
1776
1777         /* Is this crtc bound or output bound? */
1778         /* Does the bios TMDS script try to change this sometimes? */
1779         if (is_fp) {
1780                 /* I am not completely certain, but seems to be set only for dfp's */
1781                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED;
1782         }
1783
1784         if (output)
1785                 ErrorF("output %d debug_0 %08X\n", nv_output->output_resource, regp->debug_0[nv_crtc->head]);
1786
1787         /* Flatpanel support needs at least a NV10 */
1788         if (pNv->twoHeads) {
1789                 if (pNv->FPDither || (is_lvds && !pNv->VBIOS.fp.if_is_24bit)) {
1790                         if (pNv->NVArch == 0x11)
1791                                 regp->dither = savep->dither | 0x00010000;
1792                         else {
1793                                 int i;
1794                                 regp->dither = savep->dither | 0x00000001;
1795                                 for (i = 0; i < 3; i++) {
1796                                         regp->dither_regs[i] = 0xe4e4e4e4;
1797                                         regp->dither_regs[i + 3] = 0x44444444;
1798                                 }
1799                         }
1800                 } else
1801                         regp->dither = savep->dither;
1802         }
1803
1804         uint8_t depth;
1805         /* This is mode related, not pitch. */
1806         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1807                 depth = pNv->console_mode[nv_crtc->head].depth;
1808         } else {
1809                 depth = pLayout->depth;
1810         }
1811
1812         switch (depth) {
1813                 case 4:
1814                         regp->general = 0x00000100;
1815                         break;
1816                 case 24:
1817                 case 15:
1818                         regp->general = 0x00100100;
1819                         break;
1820                 case 32:
1821                 case 16:
1822                 case 8:
1823                 default:
1824                         regp->general = 0x00101100;
1825                         break;
1826         }
1827
1828         if (depth > 8 && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1829                 regp->general |= 0x30; /* enable palette mode */
1830         }
1831
1832         if (pNv->alphaCursor && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1833                 /* PIPE_LONG mode, something to do with the size of the cursor? */
1834                 regp->general |= (1<<29);
1835         }
1836
1837         /* Some values the blob sets */
1838         /* This may apply to the real ramdac that is being used (for crosswired situations) */
1839         /* Nevertheless, it's unlikely to cause many problems, since the values are equal for both */
1840         regp->unk_a20 = 0x0;
1841         regp->unk_a24 = 0xfffff;
1842         regp->unk_a34 = 0x1;
1843
1844         if (pNv->twoHeads) {
1845                 /* Do we also "own" the other register pair? */
1846                 /* If we own neither, they will just be ignored at load time. */
1847                 uint8_t other_head = (~nv_crtc->head) & 1;
1848                 if (pNv->fp_regs_owner[other_head] == nv_crtc->head) {
1849                         if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS) {
1850                                 regp->fp_control[other_head] = regp->fp_control[nv_crtc->head];
1851                                 regp->debug_0[other_head] = regp->debug_0[nv_crtc->head];
1852                                 /* Set TMDS_PLL and FPCLK, only seen for a NV31M so far. */
1853                                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK;
1854                                 regp->debug_0[other_head] |= NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL;
1855                         } else {
1856                                 ErrorF("This is BAD, we own more than one fp reg set, but are not a LVDS or TMDS output.\n");
1857                         }
1858                 }
1859         }
1860 }
1861
1862 /**
1863  * Sets up registers for the given mode/adjusted_mode pair.
1864  *
1865  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1866  *
1867  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1868  * be easily turned on/off after this.
1869  */
1870 static void
1871 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
1872                  DisplayModePtr adjusted_mode,
1873                  int x, int y)
1874 {
1875         ScrnInfoPtr pScrn = crtc->scrn;
1876         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1877         NVPtr pNv = NVPTR(pScrn);
1878         NVFBLayout *pLayout = &pNv->CurrentLayout;
1879
1880         ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->head);
1881
1882         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->head);
1883         xf86PrintModeline(pScrn->scrnIndex, mode);
1884         if (pNv->twoHeads)
1885                 NVCrtcSetOwner(crtc);
1886
1887         nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
1888
1889         /* set sel_clk before calculating PLLs */
1890         nv_crtc_mode_set_sel_clk(crtc, &pNv->ModeReg);
1891         if (pNv->Architecture == NV_ARCH_40) {
1892                 ErrorF("writing sel_clk %08X\n", pNv->ModeReg.sel_clk);
1893                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, pNv->ModeReg.sel_clk);
1894         }
1895         nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
1896         nv_crtc_mode_set_ramdac_regs(crtc, mode, adjusted_mode);
1897
1898         NVVgaProtect(crtc, TRUE);
1899         nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
1900         nv_crtc_load_state_ext(crtc, &pNv->ModeReg, FALSE);
1901         if (pLayout->depth > 8)
1902                 nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
1903         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
1904         if (pNv->Architecture == NV_ARCH_40) {
1905                 nv40_crtc_load_state_pll(crtc, &pNv->ModeReg);
1906         } else {
1907                 nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
1908         }
1909
1910         NVVgaProtect(crtc, FALSE);
1911
1912         NVCrtcSetBase(crtc, x, y, NVMatchModePrivate(mode, NV_MODE_CONSOLE));
1913
1914 #if X_BYTE_ORDER == X_BIG_ENDIAN
1915         /* turn on LFB swapping */
1916         {
1917                 unsigned char tmp;
1918
1919                 tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
1920                 tmp |= (1 << 7);
1921                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
1922         }
1923 #endif
1924 }
1925
1926 void nv_crtc_save(xf86CrtcPtr crtc)
1927 {
1928         ScrnInfoPtr pScrn = crtc->scrn;
1929         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1930         NVPtr pNv = NVPTR(pScrn);
1931
1932         ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->head);
1933
1934         /* We just came back from terminal, so unlock */
1935         NVCrtcLockUnlock(crtc, FALSE);
1936
1937         nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
1938         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
1939         nv_crtc_save_state_palette(crtc, &pNv->SavedReg);
1940         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
1941         if (pNv->Architecture == NV_ARCH_40) {
1942                 nv40_crtc_save_state_pll(pNv, &pNv->SavedReg);
1943         } else {
1944                 nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
1945         }
1946 }
1947
1948 void nv_crtc_restore(xf86CrtcPtr crtc)
1949 {
1950         ScrnInfoPtr pScrn = crtc->scrn;
1951         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1952         NVPtr pNv = NVPTR(pScrn);
1953         RIVA_HW_STATE *state;
1954         NVCrtcRegPtr savep;
1955
1956         state = &pNv->SavedReg;
1957         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1958
1959         ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->head);
1960
1961         /* Just to be safe */
1962         NVCrtcLockUnlock(crtc, FALSE);
1963
1964         NVVgaProtect(crtc, TRUE);
1965         nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
1966         nv_crtc_load_state_ext(crtc, &pNv->SavedReg, TRUE);
1967         nv_crtc_load_state_palette(crtc, &pNv->SavedReg);
1968         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
1969
1970         /* Force restoring vpll. */
1971         state->vpll_changed[nv_crtc->head] = TRUE;
1972
1973         if (pNv->Architecture == NV_ARCH_40) {
1974                 nv40_crtc_load_state_pll(crtc, &pNv->SavedReg);
1975         } else {
1976                 nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
1977         }
1978         NVVgaProtect(crtc, FALSE);
1979
1980         nv_crtc->last_dpms = NV_DPMS_CLEARED;
1981 }
1982
1983 static void
1984 NVResetCrtcConfig(xf86CrtcPtr crtc, Bool set)
1985 {
1986         ScrnInfoPtr pScrn = crtc->scrn;
1987         NVPtr pNv = NVPTR(pScrn);
1988
1989         if (pNv->twoHeads) {
1990                 uint32_t val = 0;
1991
1992                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1993
1994                 if (set) {
1995                         NVCrtcRegPtr regp;
1996
1997                         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1998                         val = regp->head;
1999                 }
2000
2001                 NVCrtcWriteCRTC(crtc, NV_CRTC_FSEL, val);
2002         }
2003 }
2004
2005 void nv_crtc_prepare(xf86CrtcPtr crtc)
2006 {
2007         ScrnInfoPtr pScrn = crtc->scrn;
2008         NVPtr pNv = NVPTR(pScrn);
2009         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2010
2011         ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->head);
2012
2013         /* Just in case */
2014         NVCrtcLockUnlock(crtc, 0);
2015
2016         NVResetCrtcConfig(crtc, FALSE);
2017
2018         crtc->funcs->dpms(crtc, DPMSModeOff);
2019
2020         /* Sync the engine before adjust mode */
2021         if (pNv->EXADriverPtr) {
2022                 exaMarkSync(pScrn->pScreen);
2023                 exaWaitSync(pScrn->pScreen);
2024         }
2025
2026         NVCrtcBlankScreen(crtc, FALSE); /* Blank screen */
2027
2028         /* Some more preperation. */
2029         NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, 0x1); /* Go to non-vga mode/out of enhanced mode */
2030         if (pNv->Architecture == NV_ARCH_40) {
2031                 uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
2032                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
2033         }
2034 }
2035
2036 void nv_crtc_commit(xf86CrtcPtr crtc)
2037 {
2038         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2039         ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->head);
2040
2041         crtc->funcs->dpms (crtc, DPMSModeOn);
2042
2043         if (crtc->scrn->pScreen != NULL)
2044                 xf86_reload_cursors (crtc->scrn->pScreen);
2045
2046         NVResetCrtcConfig(crtc, TRUE);
2047 }
2048
2049 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
2050 {
2051         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2052         ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->head);
2053
2054         return FALSE;
2055 }
2056
2057 static void nv_crtc_unlock(xf86CrtcPtr crtc)
2058 {
2059         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2060         ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->head);
2061 }
2062
2063 static void
2064 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
2065                                         int size)
2066 {
2067         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2068         ScrnInfoPtr pScrn = crtc->scrn;
2069         NVPtr pNv = NVPTR(pScrn);
2070         int i, j;
2071
2072         NVCrtcRegPtr regp;
2073         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2074
2075         switch (pNv->CurrentLayout.depth) {
2076         case 15:
2077                 /* R5G5B5 */
2078                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
2079                 for (i = 0; i < 32; i++) {
2080                         for (j = 0; j < 8; j++) {
2081                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2082                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
2083                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2084                         }
2085                 }
2086                 break;
2087         case 16:
2088                 /* R5G6B5 */
2089                 /* First deal with the 5 bit colors */
2090                 for (i = 0; i < 32; i++) {
2091                         for (j = 0; j < 8; j++) {
2092                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2093                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2094                         }
2095                 }
2096                 /* Now deal with the 6 bit color */
2097                 for (i = 0; i < 64; i++) {
2098                         for (j = 0; j < 4; j++) {
2099                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
2100                         }
2101                 }
2102                 break;
2103         default:
2104                 /* R8G8B8 */
2105                 for (i = 0; i < 256; i++) {
2106                         regp->DAC[i * 3] = red[i] >> 8;
2107                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
2108                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
2109                 }
2110                 break;
2111         }
2112
2113         nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
2114 }
2115
2116 /**
2117  * Allocates memory for a locked-in-framebuffer shadow of the given
2118  * width and height for this CRTC's rotated shadow framebuffer.
2119  */
2120
2121 static void *
2122 nv_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
2123 {
2124         ErrorF("nv_crtc_shadow_allocate is called\n");
2125         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2126         ScrnInfoPtr pScrn = crtc->scrn;
2127 #if !NOUVEAU_EXA_PIXMAPS
2128         ScreenPtr pScreen = pScrn->pScreen;
2129 #endif /* !NOUVEAU_EXA_PIXMAPS */
2130         NVPtr pNv = NVPTR(pScrn);
2131         void *offset;
2132
2133         unsigned long rotate_pitch;
2134         int size, align = 64;
2135
2136         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2137         size = rotate_pitch * height;
2138
2139         assert(nv_crtc->shadow == NULL);
2140 #if NOUVEAU_EXA_PIXMAPS
2141         if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN,
2142                         align, size, &nv_crtc->shadow)) {
2143                 ErrorF("Failed to allocate memory for shadow buffer!\n");
2144                 return NULL;
2145         }
2146
2147         if (nv_crtc->shadow && nouveau_bo_map(nv_crtc->shadow, NOUVEAU_BO_RDWR)) {
2148                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2149                                 "Failed to map shadow buffer.\n");
2150                 return NULL;
2151         }
2152
2153         offset = nv_crtc->shadow->map;
2154 #else
2155         nv_crtc->shadow = exaOffscreenAlloc(pScreen, size, align, TRUE, NULL, NULL);
2156         if (nv_crtc->shadow == NULL) {
2157                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2158                         "Couldn't allocate shadow memory for rotated CRTC\n");
2159                 return NULL;
2160         }
2161         offset = pNv->FB->map + nv_crtc->shadow->offset;
2162 #endif /* NOUVEAU_EXA_PIXMAPS */
2163
2164         return offset;
2165 }
2166
2167 /**
2168  * Creates a pixmap for this CRTC's rotated shadow framebuffer.
2169  */
2170 static PixmapPtr
2171 nv_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
2172 {
2173         ErrorF("nv_crtc_shadow_create is called\n");
2174         ScrnInfoPtr pScrn = crtc->scrn;
2175 #if NOUVEAU_EXA_PIXMAPS
2176         ScreenPtr pScreen = pScrn->pScreen;
2177         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2178 #endif /* NOUVEAU_EXA_PIXMAPS */
2179         unsigned long rotate_pitch;
2180         PixmapPtr rotate_pixmap;
2181 #if NOUVEAU_EXA_PIXMAPS
2182         struct nouveau_pixmap *nvpix;
2183 #endif /* NOUVEAU_EXA_PIXMAPS */
2184
2185         if (!data)
2186                 data = crtc->funcs->shadow_allocate (crtc, width, height);
2187
2188         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2189
2190 #if NOUVEAU_EXA_PIXMAPS
2191         /* Create a dummy pixmap, to get a private that will be accepted by the system.*/
2192         rotate_pixmap = pScreen->CreatePixmap(pScreen,
2193                                                                 0, /* width */
2194                                                                 0, /* height */
2195         #ifdef CREATE_PIXMAP_USAGE_SCRATCH /* there seems to have been no api bump */
2196                                                                 pScrn->depth,
2197                                                                 0);
2198         #else
2199                                                                 pScrn->depth);
2200         #endif /* CREATE_PIXMAP_USAGE_SCRATCH */
2201 #else
2202         rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen,
2203                                                                 width, height,
2204                                                                 pScrn->depth,
2205                                                                 pScrn->bitsPerPixel,
2206                                                                 rotate_pitch,
2207                                                                 data);
2208 #endif /* NOUVEAU_EXA_PIXMAPS */
2209
2210         if (rotate_pixmap == NULL) {
2211                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2212                         "Couldn't allocate shadow pixmap for rotated CRTC\n");
2213         }
2214
2215 #if NOUVEAU_EXA_PIXMAPS
2216         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2217         if (!nvpix) {
2218                 ErrorF("No shadow private, stage 1\n");
2219         } else {
2220                 nvpix->bo = nv_crtc->shadow;
2221                 nvpix->mapped = TRUE;
2222         }
2223
2224         /* Modify the pixmap to actually be the one we need. */
2225         pScreen->ModifyPixmapHeader(rotate_pixmap,
2226                                         width,
2227                                         height,
2228                                         pScrn->depth,
2229                                         pScrn->bitsPerPixel,
2230                                         rotate_pitch,
2231                                         data);
2232
2233         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2234         if (!nvpix || !nvpix->bo)
2235                 ErrorF("No shadow private, stage 2\n");
2236 #endif /* NOUVEAU_EXA_PIXMAPS */
2237
2238         return rotate_pixmap;
2239 }
2240
2241 static void
2242 nv_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
2243 {
2244         ErrorF("nv_crtc_shadow_destroy is called\n");
2245         ScrnInfoPtr pScrn = crtc->scrn;
2246         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2247         ScreenPtr pScreen = pScrn->pScreen;
2248
2249         if (rotate_pixmap) { /* This should also unmap the buffer object if relevant. */
2250                 pScreen->DestroyPixmap(rotate_pixmap);
2251         }
2252
2253 #if !NOUVEAU_EXA_PIXMAPS
2254         if (data && nv_crtc->shadow) {
2255                 exaOffscreenFree(pScreen, nv_crtc->shadow);
2256         }
2257 #endif /* !NOUVEAU_EXA_PIXMAPS */
2258
2259         nv_crtc->shadow = NULL;
2260 }
2261
2262 /* NV04-NV10 doesn't support alpha cursors */
2263 static const xf86CrtcFuncsRec nv_crtc_funcs = {
2264         .dpms = nv_crtc_dpms,
2265         .save = nv_crtc_save, /* XXX */
2266         .restore = nv_crtc_restore, /* XXX */
2267         .mode_fixup = nv_crtc_mode_fixup,
2268         .mode_set = nv_crtc_mode_set,
2269         .prepare = nv_crtc_prepare,
2270         .commit = nv_crtc_commit,
2271         .destroy = NULL, /* XXX */
2272         .lock = nv_crtc_lock,
2273         .unlock = nv_crtc_unlock,
2274         .set_cursor_colors = nv_crtc_set_cursor_colors,
2275         .set_cursor_position = nv_crtc_set_cursor_position,
2276         .show_cursor = nv_crtc_show_cursor,
2277         .hide_cursor = nv_crtc_hide_cursor,
2278         .load_cursor_image = nv_crtc_load_cursor_image,
2279         .gamma_set = nv_crtc_gamma_set,
2280         .shadow_create = nv_crtc_shadow_create,
2281         .shadow_allocate = nv_crtc_shadow_allocate,
2282         .shadow_destroy = nv_crtc_shadow_destroy,
2283 };
2284
2285 /* NV11 and up has support for alpha cursors. */
2286 /* Due to different maximum sizes we cannot allow it to use normal cursors */
2287 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
2288         .dpms = nv_crtc_dpms,
2289         .save = nv_crtc_save, /* XXX */
2290         .restore = nv_crtc_restore, /* XXX */
2291         .mode_fixup = nv_crtc_mode_fixup,
2292         .mode_set = nv_crtc_mode_set,
2293         .prepare = nv_crtc_prepare,
2294         .commit = nv_crtc_commit,
2295         .destroy = NULL, /* XXX */
2296         .lock = nv_crtc_lock,
2297         .unlock = nv_crtc_unlock,
2298         .set_cursor_colors = NULL, /* Alpha cursors do not need this */
2299         .set_cursor_position = nv_crtc_set_cursor_position,
2300         .show_cursor = nv_crtc_show_cursor,
2301         .hide_cursor = nv_crtc_hide_cursor,
2302         .load_cursor_argb = nv_crtc_load_cursor_argb,
2303         .gamma_set = nv_crtc_gamma_set,
2304         .shadow_create = nv_crtc_shadow_create,
2305         .shadow_allocate = nv_crtc_shadow_allocate,
2306         .shadow_destroy = nv_crtc_shadow_destroy,
2307 };
2308
2309
2310 void
2311 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
2312 {
2313         NVPtr pNv = NVPTR(pScrn);
2314         xf86CrtcPtr crtc;
2315         NVCrtcPrivatePtr nv_crtc;
2316
2317         if (pNv->NVArch >= 0x11) {
2318                 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
2319         } else {
2320                 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
2321         }
2322         if (crtc == NULL)
2323                 return;
2324
2325         nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
2326         nv_crtc->head = crtc_num;
2327         nv_crtc->last_dpms = NV_DPMS_CLEARED;
2328         pNv->fp_regs_owner[nv_crtc->head] = nv_crtc->head;
2329
2330         crtc->driver_private = nv_crtc;
2331
2332         NVCrtcLockUnlock(crtc, FALSE);
2333 }
2334
2335 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2336 {
2337         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2338         int i;
2339         NVCrtcRegPtr regp;
2340
2341         regp = &state->crtc_reg[nv_crtc->head];
2342
2343         NVWritePVIO(crtc, VGA_MISC_OUT_W, regp->MiscOutReg);
2344
2345         for (i = 0; i < 5; i++)
2346                 NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
2347
2348         /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
2349         NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
2350
2351         for (i = 0; i < 25; i++)
2352                 NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
2353
2354         for (i = 0; i < 9; i++)
2355                 NVWriteVgaGr(crtc, i, regp->Graphics[i]);
2356
2357         NVEnablePalette(crtc);
2358         for (i = 0; i < 21; i++)
2359                 NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
2360
2361         NVDisablePalette(crtc);
2362 }
2363
2364 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override)
2365 {
2366         ScrnInfoPtr pScrn = crtc->scrn;
2367         NVPtr pNv = NVPTR(pScrn);
2368         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2369         NVCrtcRegPtr regp;
2370         int i;
2371
2372         regp = &state->crtc_reg[nv_crtc->head];
2373
2374         if (pNv->Architecture >= NV_ARCH_10) {
2375                 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
2376                 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
2377                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
2378                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
2379                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2380                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2381                 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2382                 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2383                 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, 0);
2384
2385                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
2386                 NVCrtcWriteCRTC(crtc, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
2387                 NVCrtcWriteCRTC(crtc, NV_CRTC_0830, regp->unk830);
2388                 NVCrtcWriteCRTC(crtc, NV_CRTC_0834, regp->unk834);
2389                 if (pNv->Architecture == NV_ARCH_40) {
2390                         NVCrtcWriteCRTC(crtc, NV_CRTC_0850, regp->unk850);
2391                         NVCrtcWriteCRTC(crtc, NV_PCRTC_GPIO_EXT, regp->gpio_ext);
2392                 }
2393
2394                 if (pNv->Architecture == NV_ARCH_40) {
2395                         uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
2396                         if (regp->config == 0x2) { /* enhanced "horizontal only" non-vga mode */
2397                                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 | 0x10000);
2398                         } else {
2399                                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
2400                         }
2401                 }
2402         }
2403
2404         NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, regp->config);
2405         NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO, regp->gpio);
2406
2407         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
2408         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
2409         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
2410         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
2411         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
2412         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
2413         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
2414         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
2415         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
2416         if (pNv->Architecture >= NV_ARCH_30)
2417                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
2418
2419         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
2420         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
2421         if (pNv->Architecture == NV_ARCH_40) /* HW bug */
2422                 nv_crtc_fix_nv40_hw_cursor(pScrn, nv_crtc->head);
2423         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
2424         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
2425
2426         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
2427         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
2428         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SCRATCH4, regp->CRTC[NV_VGA_CRTCX_SCRATCH4]);
2429         if (pNv->Architecture >= NV_ARCH_10) {
2430                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
2431                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_43, regp->CRTC[NV_VGA_CRTCX_43]);
2432                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
2433                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_4B, regp->CRTC[NV_VGA_CRTCX_4B]);
2434                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
2435         }
2436         /* NV11 and NV20 stop at 0x52. */
2437         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
2438                 if (override)
2439                         for (i = 0; i < 0x10; i++)
2440                                 NVWriteVGACR5758(pNv, nv_crtc->head, i, regp->CR58[i]);
2441
2442                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
2443                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
2444
2445                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
2446
2447                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_85, regp->CRTC[NV_VGA_CRTCX_85]);
2448                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_86, regp->CRTC[NV_VGA_CRTCX_86]);
2449         }
2450
2451         /* Setting 1 on this value gives you interrupts for every vblank period. */
2452         NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_EN_0, 0);
2453         NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
2454
2455         pNv->CurrentState = state;
2456 }
2457
2458 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2459 {
2460         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2461         int i;
2462         NVCrtcRegPtr regp;
2463
2464         regp = &state->crtc_reg[nv_crtc->head];
2465
2466         regp->MiscOutReg = NVReadPVIO(crtc, VGA_MISC_OUT_R);
2467
2468         for (i = 0; i < 25; i++)
2469                 regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
2470
2471         NVEnablePalette(crtc);
2472         for (i = 0; i < 21; i++)
2473                 regp->Attribute[i] = NVReadVgaAttr(crtc, i);
2474         NVDisablePalette(crtc);
2475
2476         for (i = 0; i < 9; i++)
2477                 regp->Graphics[i] = NVReadVgaGr(crtc, i);
2478
2479         for (i = 0; i < 5; i++)
2480                 regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
2481 }
2482
2483 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2484 {
2485         ScrnInfoPtr pScrn = crtc->scrn;
2486         NVPtr pNv = NVPTR(pScrn);
2487         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2488         NVCrtcRegPtr regp;
2489         int i;
2490
2491         regp = &state->crtc_reg[nv_crtc->head];
2492
2493         regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
2494         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
2495         regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
2496         regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
2497         regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
2498         regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
2499         regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
2500
2501         regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
2502         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
2503         regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
2504         if (pNv->Architecture >= NV_ARCH_30)
2505                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
2506         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
2507         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
2508         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
2509         regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
2510
2511         if (pNv->Architecture >= NV_ARCH_10) {
2512                 regp->unk830 = NVCrtcReadCRTC(crtc, NV_CRTC_0830);
2513                 regp->unk834 = NVCrtcReadCRTC(crtc, NV_CRTC_0834);
2514                 if (pNv->Architecture == NV_ARCH_40) {
2515                         regp->unk850 = NVCrtcReadCRTC(crtc, NV_CRTC_0850);
2516                         regp->gpio_ext = NVCrtcReadCRTC(crtc, NV_PCRTC_GPIO_EXT);
2517                 }
2518                 if (pNv->twoHeads) {
2519                         regp->head = NVCrtcReadCRTC(crtc, NV_CRTC_FSEL);
2520                         regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
2521                 }
2522                 regp->cursorConfig = NVCrtcReadCRTC(crtc, NV_CRTC_CURSOR_CONFIG);
2523         }
2524
2525         regp->gpio = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO);
2526         regp->config = NVCrtcReadCRTC(crtc, NV_CRTC_CONFIG);
2527
2528         regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
2529         regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
2530         regp->CRTC[NV_VGA_CRTCX_SCRATCH4] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SCRATCH4);
2531         if (pNv->Architecture >= NV_ARCH_10) {
2532                 regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
2533                 regp->CRTC[NV_VGA_CRTCX_43] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_43);
2534                 regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
2535                 regp->CRTC[NV_VGA_CRTCX_4B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_4B);
2536                 regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
2537         }
2538         /* NV11 and NV20 don't have this, they stop at 0x52. */
2539         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
2540                 for (i = 0; i < 0x10; i++)
2541                         regp->CR58[i] = NVReadVGACR5758(pNv, nv_crtc->head, i);
2542
2543                 regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
2544                 regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
2545                 regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
2546
2547                 regp->CRTC[NV_VGA_CRTCX_85] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_85);
2548                 regp->CRTC[NV_VGA_CRTCX_86] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_86);
2549         }
2550 }
2551
2552 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2553 {
2554         ScrnInfoPtr pScrn = crtc->scrn;
2555         NVPtr pNv = NVPTR(pScrn);
2556         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2557         NVCrtcRegPtr regp;
2558         int i;
2559
2560         regp = &state->crtc_reg[nv_crtc->head];
2561
2562         regp->general = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL);
2563
2564         regp->fp_control[0]     = NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL);
2565         regp->debug_0[0]        = NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
2566
2567         if (pNv->twoHeads) {
2568                 regp->fp_control[1]     = NVReadRAMDAC(pNv, 1, NV_RAMDAC_FP_CONTROL);
2569                 regp->debug_0[1]        = NVReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
2570
2571                 regp->debug_1   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1);
2572                 regp->debug_2   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2);
2573
2574                 regp->unk_a20 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A20);
2575                 regp->unk_a24 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A24);
2576                 regp->unk_a34 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A34);
2577         }
2578
2579         if (pNv->NVArch == 0x11) {
2580                 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_DITHER_NV11);
2581         } else if (pNv->twoHeads) {
2582                 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DITHER);
2583                 for (i = 0; i < 3; i++) {
2584                         regp->dither_regs[i] = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_850 + i * 4);
2585                         regp->dither_regs[i + 3] = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_85C + i * 4);
2586                 }
2587         }
2588         if (pNv->Architecture >= NV_ARCH_10)
2589                 regp->nv10_cursync = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC);
2590
2591         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2592
2593         for (i = 0; i < 7; i++) {
2594                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2595                 regp->fp_horiz_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
2596         }
2597
2598         for (i = 0; i < 7; i++) {
2599                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2600                 regp->fp_vert_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
2601         }
2602
2603         regp->fp_hvalid_start = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_HVALID_START);
2604         regp->fp_hvalid_end = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_HVALID_END);
2605         regp->fp_vvalid_start = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_VVALID_START);
2606         regp->fp_vvalid_end = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_VVALID_END);
2607 }
2608
2609 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2610 {
2611         ScrnInfoPtr pScrn = crtc->scrn;
2612         NVPtr pNv = NVPTR(pScrn);
2613         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2614         NVCrtcRegPtr regp;
2615         int i;
2616
2617         regp = &state->crtc_reg[nv_crtc->head];
2618
2619         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL, regp->general);
2620
2621         if (pNv->fp_regs_owner[0] == nv_crtc->head) {
2622                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL, regp->fp_control[0]);
2623                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0, regp->debug_0[0]);
2624         }
2625         if (pNv->twoHeads) {
2626                 if (pNv->fp_regs_owner[1] == nv_crtc->head) {
2627                         NVWriteRAMDAC(pNv, 1, NV_RAMDAC_FP_CONTROL, regp->fp_control[1]);
2628                         NVWriteRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0, regp->debug_0[1]);
2629                 }
2630                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
2631                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
2632                 if (pNv->NVArch == 0x30) { /* For unknown purposes. */
2633                         uint32_t reg890 = NVCrtcReadRAMDAC(crtc, NV30_RAMDAC_890);
2634                         NVCrtcWriteRAMDAC(crtc, NV30_RAMDAC_89C, reg890);
2635                 }
2636
2637                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A20, regp->unk_a20);
2638                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A24, regp->unk_a24);
2639                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A34, regp->unk_a34);
2640         }
2641
2642         if (pNv->NVArch == 0x11) {
2643                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_DITHER_NV11, regp->dither);
2644         } else if (pNv->twoHeads) {
2645                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DITHER, regp->dither);
2646                 for (i = 0; i < 3; i++) {
2647                         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_850 + i * 4, regp->dither_regs[i]);
2648                         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_85C + i * 4, regp->dither_regs[i + 3]);
2649                 }
2650         }
2651         if (pNv->Architecture >= NV_ARCH_10)
2652                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
2653
2654         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2655
2656         for (i = 0; i < 7; i++) {
2657                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2658                 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_horiz_regs[i]);
2659         }
2660
2661         for (i = 0; i < 7; i++) {
2662                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2663                 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_vert_regs[i]);
2664         }
2665
2666         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_HVALID_START, regp->fp_hvalid_start);
2667         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_HVALID_END, regp->fp_hvalid_end);
2668         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_VVALID_START, regp->fp_vvalid_start);
2669         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_VVALID_END, regp->fp_vvalid_end);
2670 }
2671
2672 void
2673 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y, Bool bios_restore)
2674 {
2675         ScrnInfoPtr pScrn = crtc->scrn;
2676         NVPtr pNv = NVPTR(pScrn);
2677         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2678         NVFBLayout *pLayout = &pNv->CurrentLayout;
2679         uint32_t start = 0;
2680
2681         ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
2682
2683         if (bios_restore) {
2684                 start = pNv->console_mode[nv_crtc->head].fb_start;
2685         } else {
2686                 start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
2687                 if (crtc->rotatedData != NULL) { /* we do not exist on the real framebuffer */
2688 #if NOUVEAU_EXA_PIXMAPS
2689                         start = nv_crtc->shadow->offset;
2690 #else
2691                         start = pNv->FB->offset + nv_crtc->shadow->offset; /* We do exist relative to the framebuffer */
2692 #endif
2693                 } else {
2694                         start += pNv->FB->offset;
2695                 }
2696         }
2697
2698         /* 30 bits addresses in 32 bits according to haiku */
2699         NVCrtcWriteCRTC(crtc, NV_CRTC_START, start & 0xfffffffc);
2700
2701         /* set NV4/NV10 byte adress: (bit0 - 1) */
2702         NVWriteVgaAttr(crtc, 0x13, (start & 0x3) << 1);
2703
2704         crtc->x = x;
2705         crtc->y = y;
2706 }
2707
2708 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2709 {
2710         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2711         NVPtr pNv = NVPTR(crtc->scrn);
2712         volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2713         int i;
2714
2715         VGA_WR08(pDACReg, VGA_DAC_MASK, 0xff);
2716         VGA_WR08(pDACReg, VGA_DAC_READ_ADDR, 0x0);
2717
2718         for (i = 0; i < 768; i++) {
2719                 state->crtc_reg[nv_crtc->head].DAC[i] = NV_RD08(pDACReg, VGA_DAC_DATA);
2720                 DDXMMIOH("nv_crtc_save_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, NV_PDIO0_OFFSET + (nv_crtc->head ? NV_PDIO0_SIZE : 0) + VGA_DAC_DATA, state->crtc_reg[nv_crtc->head].DAC[i]);
2721         }
2722
2723         NVDisablePalette(crtc);
2724 }
2725 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2726 {
2727         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2728         NVPtr pNv = NVPTR(crtc->scrn);
2729         volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2730         int i;
2731
2732         VGA_WR08(pDACReg, VGA_DAC_MASK, 0xff);
2733         VGA_WR08(pDACReg, VGA_DAC_WRITE_ADDR, 0x0);
2734
2735         for (i = 0; i < 768; i++) {
2736                 DDXMMIOH("nv_crtc_load_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, NV_PDIO0_OFFSET + (nv_crtc->head ? NV_PDIO0_SIZE : 0) + VGA_DAC_DATA, state->crtc_reg[nv_crtc->head].DAC[i]);
2737                 NV_WR08(pDACReg, VGA_DAC_DATA, state->crtc_reg[nv_crtc->head].DAC[i]);
2738         }
2739
2740         NVDisablePalette(crtc);
2741 }
2742
2743 /* on = unblank */
2744 void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
2745 {
2746         NVPtr pNv = NVPTR(crtc->scrn);
2747         unsigned char scrn;
2748
2749         if (pNv->twoHeads)
2750                 NVCrtcSetOwner(crtc);
2751
2752         scrn = NVReadVgaSeq(crtc, 0x01);
2753         if (on) {
2754                 scrn &= ~0x20;
2755         } else {
2756                 scrn |= 0x20;
2757         }
2758
2759         NVVgaSeqReset(crtc, TRUE);
2760         NVWriteVgaSeq(crtc, 0x01, scrn);
2761         NVVgaSeqReset(crtc, FALSE);
2762 }
2763
2764 /* Reset a mode after a drastic output resource change for example. */
2765 void NVCrtcModeFix(xf86CrtcPtr crtc)
2766 {
2767         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2768         Bool need_unlock;
2769
2770         if (!crtc->enabled)
2771                 return;
2772
2773         if (!xf86ModesEqual(&crtc->mode, &crtc->desiredMode)) /* not currently in X */
2774                 return;
2775
2776         DisplayModePtr adjusted_mode = xf86DuplicateMode(&crtc->mode);
2777         uint8_t dpms_mode = nv_crtc->last_dpms;
2778
2779         /* Set the crtc mode again. */
2780         crtc->funcs->dpms(crtc, DPMSModeOff);
2781         need_unlock = crtc->funcs->lock(crtc);
2782         crtc->funcs->mode_fixup(crtc, &crtc->mode, adjusted_mode);
2783         crtc->funcs->prepare(crtc);
2784         crtc->funcs->mode_set(crtc, &crtc->mode, adjusted_mode, crtc->x, crtc->y);
2785         crtc->funcs->commit(crtc);
2786         if (need_unlock)
2787                 crtc->funcs->unlock(crtc);
2788         crtc->funcs->dpms(crtc, dpms_mode);
2789
2790         /* Free mode. */
2791         xfree(adjusted_mode);
2792 }
2793
2794 /*************************************************************************** \
2795 |*                                                                           *|
2796 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
2797 |*                                                                           *|
2798 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
2799 |*     international laws.  Users and possessors of this source code are     *|
2800 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
2801 |*     use this code in individual and commercial software.                  *|
2802 |*                                                                           *|
2803 |*     Any use of this source code must include,  in the user documenta-     *|
2804 |*     tion and  internal comments to the code,  notices to the end user     *|
2805 |*     as follows:                                                           *|
2806 |*                                                                           *|
2807 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
2808 |*                                                                           *|
2809 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
2810 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
2811 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
2812 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
2813 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
2814 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
2815 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
2816 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
2817 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
2818 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
2819 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
2820 |*                                                                           *|
2821 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
2822 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
2823 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
2824 |*     computer  software  documentation,"  as such  terms  are  used in     *|
2825 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
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2827 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
2828 |*     all U.S. Government End Users  acquire the source code  with only     *|
2829 |*     those rights set forth herein.                                        *|
2830 |*                                                                           *|
2831  \***************************************************************************/