git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 2006 Dave Airlie
   3  * Copyright 2007 Maarten Maathuis
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
  26  * decleration is at the bottom of this file as it is rather ugly
  27  */
  28
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include <assert.h>
  34 #include "xf86.h"
  35 #include "os.h"
  36 #include "mibank.h"
  37 #include "globals.h"
  38 #include "xf86.h"
  39 #include "xf86Priv.h"
  40 #include "xf86DDC.h"
  41 #include "mipointer.h"
  42 #include "windowstr.h"
  43 #include <randrstr.h>
  44 #include <X11/extensions/render.h>
  45
  46 #include "xf86Crtc.h"
  47 #include "nv_include.h"
  48
  49 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  50 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override);
  51 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  52 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  53 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  54 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  55 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  56 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  57
  58 static uint32_t NVCrtcReadCRTC(xf86CrtcPtr crtc, uint32_t reg)
  59 {
  60         ScrnInfoPtr pScrn = crtc->scrn;
  61         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  62         NVPtr pNv = NVPTR(pScrn);
  63
  64         return NVReadCRTC(pNv, nv_crtc->head, reg);
  65 }
  66
  67 void NVCrtcWriteCRTC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
  68 {
  69         ScrnInfoPtr pScrn = crtc->scrn;
  70         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  71         NVPtr pNv = NVPTR(pScrn);
  72
  73         NVWriteCRTC(pNv, nv_crtc->head, reg, val);
  74 }
  75
  76 static uint32_t NVCrtcReadRAMDAC(xf86CrtcPtr crtc, uint32_t reg)
  77 {
  78         ScrnInfoPtr pScrn = crtc->scrn;
  79         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  80         NVPtr pNv = NVPTR(pScrn);
  81
  82         return NVReadRAMDAC(pNv, nv_crtc->head, reg);
  83 }
  84
  85 void NVCrtcWriteRAMDAC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
  86 {
  87         ScrnInfoPtr pScrn = crtc->scrn;
  88         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  89         NVPtr pNv = NVPTR(pScrn);
  90
  91         NVWriteRAMDAC(pNv, nv_crtc->head, reg, val);
  92 }
  93
  94 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool lock)
  95 {
  96         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  97         ScrnInfoPtr pScrn = crtc->scrn;
  98         NVPtr pNv = NVPTR(pScrn);
  99
 100         if (pNv->twoHeads)
 101                 NVSetOwner(pScrn, nv_crtc->head);
 102         NVLockVgaCrtc(pNv, nv_crtc->head, lock);
 103 }
 104
 105 static xf86OutputPtr
 106 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
 107 {
 108         ScrnInfoPtr pScrn = crtc->scrn;
 109         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 110         int i;
 111         for (i = 0; i < xf86_config->num_output; i++) {
 112                 xf86OutputPtr output = xf86_config->output[i];
 113
 114                 if (output->crtc == crtc) {
 115                         return output;
 116                 }
 117         }
 118
 119         return NULL;
 120 }
 121
 122 static xf86CrtcPtr
 123 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
 124 {
 125         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 126         int i;
 127
 128         for (i = 0; i < xf86_config->num_crtc; i++) {
 129                 xf86CrtcPtr crtc = xf86_config->crtc[i];
 130                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 131                 if (nv_crtc->head == index)
 132                         return crtc;
 133         }
 134
 135         return NULL;
 136 }
 137
 138 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
 139 /* They are only valid for NV4x, appearantly reordered for NV5x */
 140 /* gpu pll: 0x4000 + 0x4004
 141  * unknown pll: 0x4008 + 0x400c
 142  * vpll1: 0x4010 + 0x4014
 143  * vpll2: 0x4018 + 0x401c
 144  * unknown pll: 0x4020 + 0x4024
 145  * unknown pll: 0x4038 + 0x403c
 146  * Some of the unknown's are probably memory pll's.
 147  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
 148  * 1 and 2 refer to the registers of each pair. There is only one post divider.
 149  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
 150  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
 151  *     bit8: A switch that turns of the second divider and multiplier off.
 152  *     bit12: Also a switch, i haven't seen it yet.
 153  *     bit16-19: p-divider
 154  *     but 28-31: Something related to the mode that is used (see bit8).
 155  * 2) bit0-7: m-divider (a)
 156  *     bit8-15: n-multiplier (a)
 157  *     bit16-23: m-divider (b)
 158  *     bit24-31: n-multiplier (b)
 159  */
 160
 161 /* Modifying the gpu pll for example requires:
 162  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 163  * This is not needed for the vpll's which have their own bits.
 164  */
 165
 166 static void nv40_crtc_save_state_pll(ScrnInfoPtr pScrn, RIVA_HW_STATE *state)
 167 {
 168         NVPtr pNv = NVPTR(pScrn);
 169         state->vpll1_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL);
 170         state->vpll1_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B);
 171         state->vpll2_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2);
 172         state->vpll2_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B);
 173         state->pllsel = NVReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT);
 174         state->sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
 175         state->reg580 = NVReadRAMDAC(pNv, 0, NV_RAMDAC_580);
 176 }
 177
 178 static void nv40_crtc_load_state_pll(ScrnInfoPtr pScrn, RIVA_HW_STATE *state)
 179 {
 180         NVPtr pNv = NVPTR(pScrn);
 181         uint32_t fp_debug_0[2];
 182         uint32_t index[2];
 183         fp_debug_0[0] = NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
 184         fp_debug_0[1] = NVReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
 185
 186         /* The TMDS_PLL switch is on the actual ramdac */
 187         if (state->crosswired) {
 188                 index[0] = 1;
 189                 index[1] = 0;
 190         } else {
 191                 index[0] = 0;
 192                 index[1] = 1;
 193         }
 194
 195         if (state->vpll2_b && state->vpll_changed[1]) {
 196                 NVWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0,
 197                         fp_debug_0[index[1]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 198
 199                 /* Wait for the situation to stabilise */
 200                 usleep(5000);
 201
 202                 /* for vpll2 change bits 18 and 19 are disabled */
 203                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040 & ~(3 << 18));
 204
 205                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_VPLL2 %08X\n", state->vpll2_a);
 206                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_VPLL2_B %08X\n", state->vpll2_b);
 207
 208                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2, state->vpll2_a);
 209                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 210
 211                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_PLL_SELECT %08X\n", state->pllsel);
 212                 /* Don't turn vpll1 off. */
 213                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
 214
 215                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_580 %08X\n", state->reg580);
 216                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_580, state->reg580);
 217
 218                 /* We need to wait a while */
 219                 usleep(5000);
 220                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 221
 222                 NVWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[1]]);
 223
 224                 /* Wait for the situation to stabilise */
 225                 usleep(5000);
 226         }
 227
 228         if (state->vpll1_b && state->vpll_changed[0]) {
 229                 NVWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0,
 230                         fp_debug_0[index[0]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 231
 232                 /* Wait for the situation to stabilise */
 233                 usleep(5000);
 234
 235                 /* for vpll1 change bits 16 and 17 are disabled */
 236                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040 & ~(3 << 16));
 237
 238                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_VPLL %08X\n", state->vpll1_a);
 239                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_VPLL_B %08X\n", state->vpll1_b);
 240
 241                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL, state->vpll1_a);
 242                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B, state->vpll1_b);
 243
 244                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_PLL_SELECT %08X\n", state->pllsel);
 245                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
 246
 247                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_580 %08X\n", state->reg580);
 248                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_580, state->reg580);
 249
 250                 /* We need to wait a while */
 251                 usleep(5000);
 252                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 253
 254                 NVWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[0]]);
 255
 256                 /* Wait for the situation to stabilise */
 257                 usleep(5000);
 258         }
 259
 260         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_SEL_CLK %08X\n", state->sel_clk);
 261         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, state->sel_clk);
 262
 263         /* All clocks have been set at this point. */
 264         state->vpll_changed[0] = FALSE;
 265         state->vpll_changed[1] = FALSE;
 266 }
 267
 268 static void nv_crtc_save_state_pll(ScrnInfoPtr pScrn, RIVA_HW_STATE *state)
 269 {
 270         NVPtr pNv = NVPTR(pScrn);
 271         state->vpll1_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL);
 272         if (pNv->twoHeads) {
 273                 state->vpll2_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2);
 274                 state->sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
 275         }
 276         if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 277                 state->vpll1_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B);
 278                 state->vpll2_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B);
 279         }
 280         state->pllsel = NVReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT);
 281 }
 282
 283
 284 static void nv_crtc_load_state_pll(ScrnInfoPtr pScrn, RIVA_HW_STATE *state)
 285 {
 286         NVPtr pNv = NVPTR(pScrn);
 287         /* This sequence is important, the NV28 is very sensitive in this area. */
 288         /* Keep pllsel last and sel_clk first. */
 289         if (pNv->twoHeads) {
 290                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_SEL_CLK %08X\n", state->sel_clk);
 291                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, state->sel_clk);
 292         }
 293
 294         if (state->vpll2_a && state->vpll_changed[1]) {
 295                 if (pNv->twoHeads) {
 296                         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_VPLL2 %08X\n", state->vpll2_a);
 297                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2, state->vpll2_a);
 298                 }
 299                 if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 300                         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_VPLL2_B %08X\n", state->vpll2_b);
 301                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 302                 }
 303         }
 304
 305         if (state->vpll1_a && state->vpll_changed[0]) {
 306                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_VPLL %08X\n", state->vpll1_a);
 307                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL, state->vpll1_a);
 308                 if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 309                         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_VPLL_B %08X\n", state->vpll1_b);
 310                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B, state->vpll1_b);
 311                 }
 312         }
 313
 314         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_PLL_SELECT %08X\n", state->pllsel);
 315         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
 316
 317         /* All clocks have been set at this point. */
 318         state->vpll_changed[0] = FALSE;
 319         state->vpll_changed[1] = FALSE;
 320 }
 321
 322 static void nv_crtc_mode_set_sel_clk(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 323 {
 324         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 325         NVPtr pNv = NVPTR(crtc->scrn);
 326         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 327         NVOutputPrivatePtr nv_output;
 328         int i;
 329
 330         if (!output)
 331                 return;
 332         nv_output = output->driver_private;
 333
 334         /* init to existing value, less PLL binding */
 335         if (!state->sel_clk)
 336                 state->sel_clk = pNv->SavedReg.sel_clk & ~(0x5 << 16);
 337
 338         /* SEL_CLK is only used on the primary ramdac
 339          * It toggles spread spectrum PLL output and sets the bindings of PLLs
 340          * to heads on digital outputs
 341          */
 342         if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS) {
 343                 bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
 344
 345                 state->sel_clk &= ~(0xf << 16);
 346                 /* Even with two dvi, this should not conflict. */
 347                 if (crossed_clocks)
 348                         state->sel_clk |= (0x1 << 16);
 349                 else
 350                         state->sel_clk |= (0x4 << 16);
 351
 352                 /* nv30:
 353                  *      bit 0           NVClk spread spectrum on/off
 354                  *      bit 2           MemClk spread spectrum on/off
 355                  *      bit 4           PixClk1 spread spectrum on/off
 356                  *      bit 6           PixClk2 spread spectrum on/off
 357                  *
 358                  * nv40 (observations from bios behaviour and mmio traces):
 359                  *      bit 4           seems to get set when output is on head A - likely related to PixClk1
 360                  *      bit 6           seems to get set when output is on head B - likely related to PixClk2
 361                  *      bits 5&7        set as for bits 4&6, but do not appear on cards using 4&6
 362                  *
 363                  *      bits 8&10       seen on dual dvi outputs; possibly means "bits 4&6, dual dvi"
 364                  *
 365                  *      Note that the circumstances for setting the bits at all is unclear
 366                  */
 367                 for (i = 1; i <= 2; i++) {
 368                         uint32_t var = (state->sel_clk >> 4*i) & 0xf;
 369                         int shift = 0; /* assume (var & 0x5) by default */
 370
 371                         if (!var)
 372                                 continue;
 373                         if (var & 0xa)
 374                                 shift = 1;
 375
 376                         state->sel_clk &= ~(0xf << 4*i);
 377                         if (crossed_clocks)
 378                                 state->sel_clk |= (0x4 << (4*i + shift));
 379                         else
 380                                 state->sel_clk |= (0x1 << (4*i + shift));
 381                 }
 382         }
 383 }
 384
 385 /*
 386  * Calculate extended mode parameters (SVGA) and save in a
 387  * mode state structure.
 388  * State is not specific to a single crtc, but shared.
 389  */
 390 static void nv_crtc_calc_state_ext(
 391         xf86CrtcPtr             crtc,
 392         DisplayModePtr  mode,
 393         int                             bpp,
 394         int                             DisplayWidth, /* Does this change after setting the mode? */
 395         int                             CrtcHDisplay,
 396         int                             CrtcVDisplay,
 397         int                             dotClock,
 398         int                             flags
 399 )
 400 {
 401         ScrnInfoPtr pScrn = crtc->scrn;
 402         NVPtr pNv = NVPTR(pScrn);
 403         uint32_t pixelDepth, VClk = 0;
 404         uint32_t CursorStart;
 405         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 406         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 407         RIVA_HW_STATE *state = &pNv->ModeReg;
 408         uint32_t old_clock_a = 0, old_clock_b = 0;
 409         struct pll_lims pll_lim;
 410         int NM1 = 0xbeef, NM2 = 0xdead, log2P = 0;
 411         uint32_t g70_pll_special_bits = 0;
 412         Bool nv4x_single_stage_pll_mode = FALSE;
 413         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 414         NVOutputPrivatePtr nv_output = NULL;
 415         if (output)
 416                 nv_output = output->driver_private;
 417
 418         /* Store old clock. */
 419         if (nv_crtc->head == 1) {
 420                 old_clock_a = state->vpll2_a;
 421                 old_clock_b = state->vpll2_b;
 422         } else {
 423                 old_clock_a = state->vpll1_a;
 424                 old_clock_b = state->vpll1_b;
 425         }
 426
 427         /*
 428          * Extended RIVA registers.
 429          */
 430         /* This is pitch related, not mode related. */
 431         pixelDepth = (bpp + 1)/8;
 432
 433         if (nv_crtc->head == 0) {
 434                 if (!get_pll_limits(pScrn, VPLL1, &pll_lim))
 435                         return;
 436         } else
 437                 if (!get_pll_limits(pScrn, VPLL2, &pll_lim))
 438                         return;
 439
 440         if (pNv->twoStagePLL) {
 441                 if (dotClock < pll_lim.vco1.maxfreq && pNv->NVArch > 0x40) { /* use a single VCO */
 442                         nv4x_single_stage_pll_mode = TRUE;
 443                         /* Turn the second set of divider and multiplier off */
 444                         /* Bogus data, the same nvidia uses */
 445                         NM2 = 0x11f;
 446                         VClk = getMNP_single(pScrn, &pll_lim, dotClock, &NM1, &log2P);
 447                 } else
 448                         VClk = getMNP_double(pScrn, &pll_lim, dotClock, &NM1, &NM2, &log2P);
 449         } else
 450                 VClk = getMNP_single(pScrn, &pll_lim, dotClock, &NM1, &log2P);
 451
 452         /* Are these all the (relevant) G70 cards? */
 453         if (pNv->NVArch == 0x4B || pNv->NVArch == 0x46 || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
 454                 /* This is a big guess, but should be reasonable until we can narrow it down. */
 455                 /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
 456                 if (nv4x_single_stage_pll_mode)
 457                         g70_pll_special_bits = 0x1;
 458                 else
 459                         g70_pll_special_bits = 0x3;
 460         }
 461
 462         if (pNv->NVArch == 0x30)
 463                 /* See nvregisters.xml for details. */
 464                 state->pll = log2P << 16 | NM1 | (NM2 & 7) << 4 | ((NM2 >> 8) & 7) << 19 | ((NM2 >> 11) & 3) << 24 | NV30_RAMDAC_ENABLE_VCO2;
 465         else
 466                 state->pll = g70_pll_special_bits << 30 | log2P << 16 | NM1;
 467         state->pllB = NV31_RAMDAC_ENABLE_VCO2 | NM2;
 468
 469         /* Does register 0x580 already have a value? */
 470         if (!state->reg580)
 471                 state->reg580 = pNv->misc_info.ramdac_0_reg_580;
 472         if (nv4x_single_stage_pll_mode) {
 473                 if (nv_crtc->head == 0)
 474                         state->reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 475                 else
 476                         state->reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 477         } else {
 478                 if (nv_crtc->head == 0)
 479                         state->reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
 480                 else
 481                         state->reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
 482         }
 483
 484         if (!pNv->twoStagePLL || nv4x_single_stage_pll_mode)
 485                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vpll: n %d m %d log2p %d\n", NM1 >> 8, NM1 & 0xff, log2P);
 486         else
 487                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", NM1 >> 8, NM2 >> 8, NM1 & 0xff, NM2 & 0xff, log2P);
 488
 489         if (nv_crtc->head == 1) {
 490                 state->vpll2_a = state->pll;
 491                 state->vpll2_b = state->pllB;
 492         } else {
 493                 state->vpll1_a = state->pll;
 494                 state->vpll1_b = state->pllB;
 495         }
 496
 497         /* Changing clocks gives a delay, which is not always needed. */
 498         if (old_clock_a != state->pll || old_clock_b != state->pllB)
 499                 state->vpll_changed[nv_crtc->head] = TRUE;
 500         else
 501                 state->vpll_changed[nv_crtc->head] = FALSE;
 502
 503         switch (pNv->Architecture) {
 504         case NV_ARCH_04:
 505                 nv4UpdateArbitrationSettings(VClk,
 506                                                 pixelDepth * 8,
 507                                                 &(state->arbitration0),
 508                                                 &(state->arbitration1),
 509                                                 pNv);
 510                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
 511                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
 512                 if (flags & V_DBLSCAN)
 513                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 514                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
 515                 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
 516                 state->config = 0x00001114;
 517                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 518                 break;
 519         case NV_ARCH_10:
 520         case NV_ARCH_20:
 521         case NV_ARCH_30:
 522         default:
 523                 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
 524                         ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
 525                         state->arbitration0 = 128;
 526                         state->arbitration1 = 0x0480;
 527                 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
 528                         ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
 529                         nForceUpdateArbitrationSettings(VClk,
 530                                                 pixelDepth * 8,
 531                                                 &(state->arbitration0),
 532                                                 &(state->arbitration1),
 533                                                 pNv);
 534                 } else if (pNv->Architecture < NV_ARCH_30) {
 535                         nv10UpdateArbitrationSettings(VClk,
 536                                                 pixelDepth * 8,
 537                                                 &(state->arbitration0),
 538                                                 &(state->arbitration1),
 539                                                 pNv);
 540                 } else {
 541                         nv30UpdateArbitrationSettings(pNv,
 542                                                 &(state->arbitration0),
 543                                                 &(state->arbitration1));
 544                 }
 545
 546                 if (nv_crtc->head == 1) {
 547                         CursorStart = pNv->Cursor2->offset;
 548                 } else {
 549                         CursorStart = pNv->Cursor->offset;
 550                 }
 551
 552                 if (!NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 553                         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
 554                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
 555                         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
 556                 } else {
 557                         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x0;
 558                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0x0;
 559                         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x0;
 560                 }
 561
 562                 if (flags & V_DBLSCAN)
 563                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 564
 565                 state->config   = nvReadFB(pNv, NV_PFB_CFG0);
 566                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 567                 break;
 568         }
 569
 570         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 571                 /* This is a bit of a guess. */
 572                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] |= 0xB8;
 573         }
 574
 575         /* Are we crosswired? */
 576         if (output && nv_crtc->head != nv_output->preferred_output) {
 577                 state->crosswired = TRUE;
 578         } else
 579                 state->crosswired = FALSE;
 580
 581         /* The NV40 seems to have more similarities to NV3x than other cards. */
 582         if (pNv->NVArch < 0x41) {
 583                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL;
 584                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL;
 585         }
 586
 587         if (nv_crtc->head == 1) {
 588                 if (!nv4x_single_stage_pll_mode) {
 589                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 590                 } else {
 591                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 592                 }
 593                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
 594         } else {
 595                 if (!nv4x_single_stage_pll_mode) {
 596                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 597                 } else {
 598                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 599                 }
 600                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
 601         }
 602
 603         /* The blob uses this always, so let's do the same */
 604         if (pNv->Architecture == NV_ARCH_40) {
 605                 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
 606         }
 607
 608         regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
 609         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
 610         if (pNv->Architecture >= NV_ARCH_30) {
 611                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
 612         }
 613
 614         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 615                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = ((CrtcHDisplay/16) & 0x700) >> 3;
 616         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 617                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((CrtcHDisplay*bpp)/64) & 0x700) >> 3;
 618         } else { /* framebuffer can be larger than crtc scanout area. */
 619                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
 620         }
 621         regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
 622 }
 623
 624 static void
 625 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
 626 {
 627         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 628         ScrnInfoPtr pScrn = crtc->scrn;
 629         NVPtr pNv = NVPTR(pScrn);
 630         unsigned char seq1 = 0, crtc17 = 0;
 631         unsigned char crtc1A;
 632
 633         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_dpms is called for CRTC %d with mode %d.\n", nv_crtc->head, mode);
 634
 635         if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */
 636                 return;
 637
 638         nv_crtc->last_dpms = mode;
 639
 640         if (pNv->twoHeads)
 641                 NVSetOwner(pScrn, nv_crtc->head);
 642
 643         crtc1A = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
 644         switch(mode) {
 645                 case DPMSModeStandby:
 646                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
 647                 seq1 = 0x20;
 648                 crtc17 = 0x80;
 649                 crtc1A |= 0x80;
 650                 break;
 651         case DPMSModeSuspend:
 652                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
 653                 seq1 = 0x20;
 654                 crtc17 = 0x80;
 655                 crtc1A |= 0x40;
 656                 break;
 657         case DPMSModeOff:
 658                 /* Screen: Off; HSync: Off, VSync: Off */
 659                 seq1 = 0x20;
 660                 crtc17 = 0x00;
 661                 crtc1A |= 0xC0;
 662                 break;
 663         case DPMSModeOn:
 664         default:
 665                 /* Screen: On; HSync: On, VSync: On */
 666                 seq1 = 0x00;
 667                 crtc17 = 0x80;
 668                 break;
 669         }
 670
 671         NVVgaSeqReset(pNv, nv_crtc->head, true);
 672         /* Each head has it's own sequencer, so we can turn it off when we want */
 673         seq1 |= (NVReadVgaSeq(pNv, nv_crtc->head, 0x01) & ~0x20);
 674         NVWriteVgaSeq(pNv, nv_crtc->head, 0x1, seq1);
 675         crtc17 |= (NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_MODECTL) & ~0x80);
 676         usleep(10000);
 677         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_MODECTL, crtc17);
 678         NVVgaSeqReset(pNv, nv_crtc->head, false);
 679
 680         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT1, crtc1A);
 681 }
 682
 683 static Bool
 684 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
 685                      DisplayModePtr adjusted_mode)
 686 {
 687         return TRUE;
 688 }
 689
 690 static void
 691 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
 692 {
 693         ScrnInfoPtr pScrn = crtc->scrn;
 694         NVPtr pNv = NVPTR(pScrn);
 695         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 696         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 697         int depth = pScrn->depth;
 698
 699         /* Calculate our timings */
 700         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
 701         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
 702         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
 703         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
 704         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
 705         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
 706         int vertDisplay         = mode->CrtcVDisplay                    - 1;
 707         int vertStart           = mode->CrtcVSyncStart          - 1;
 708         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
 709         int vertTotal           = mode->CrtcVTotal                      - 2;
 710         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
 711         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
 712
 713         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 714         NVOutputPrivatePtr nv_output = NULL;
 715         if (output)
 716                 nv_output = output->driver_private;
 717
 718         /* This is pitch/memory size related. */
 719         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE))
 720                 depth = pNv->console_mode[nv_crtc->head].bpp;
 721
 722         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Mode clock: %d\n", mode->Clock);
 723         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Adjusted mode clock: %d\n", adjusted_mode->Clock);
 724
 725         /* Reverted to what nv did, because that works for all resolutions on flatpanels */
 726         if (output && (nv_output->type == OUTPUT_LVDS || nv_output->type == OUTPUT_TMDS)) {
 727                 vertStart = vertTotal - 3;
 728                 vertEnd = vertTotal - 2;
 729                 vertBlankStart = vertStart;
 730                 horizStart = horizTotal - 5;
 731                 horizEnd = horizTotal - 2;
 732                 horizBlankEnd = horizTotal + 4;
 733                 if (pNv->overlayAdaptor && pNv->Architecture >= NV_ARCH_10) {
 734                         /* This reportedly works around Xv some overlay bandwidth problems*/
 735                         horizTotal += 2;
 736                 }
 737         }
 738
 739         if (mode->Flags & V_INTERLACE)
 740                 vertTotal |= 1;
 741
 742 #if 0
 743         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
 744         ErrorF("horizStart: 0x%X \n", horizStart);
 745         ErrorF("horizEnd: 0x%X \n", horizEnd);
 746         ErrorF("horizTotal: 0x%X \n", horizTotal);
 747         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
 748         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
 749         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
 750         ErrorF("vertStart: 0x%X \n", vertStart);
 751         ErrorF("vertEnd: 0x%X \n", vertEnd);
 752         ErrorF("vertTotal: 0x%X \n", vertTotal);
 753         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
 754         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
 755 #endif
 756
 757         /*
 758         * compute correct Hsync & Vsync polarity
 759         */
 760         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
 761                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
 762
 763                 regp->MiscOutReg = 0x23;
 764                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
 765                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
 766         } else {
 767                 int VDisplay = mode->VDisplay;
 768                 if (mode->Flags & V_DBLSCAN)
 769                         VDisplay *= 2;
 770                 if (mode->VScan > 1)
 771                         VDisplay *= mode->VScan;
 772                 if (VDisplay < 400) {
 773                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
 774                 } else if (VDisplay < 480) {
 775                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
 776                 } else if (VDisplay < 768) {
 777                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
 778                 } else {
 779                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
 780                 }
 781         }
 782
 783         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
 784
 785         /*
 786         * Time Sequencer
 787         */
 788         regp->Sequencer[0] = 0x00;
 789         /* 0x20 disables the sequencer */
 790         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 791                 if (mode->HDisplay == 720) {
 792                         regp->Sequencer[1] = 0x21; /* enable 9/8 mode */
 793                 } else {
 794                         regp->Sequencer[1] = 0x20;
 795                 }
 796         } else {
 797                 if (mode->Flags & V_CLKDIV2) {
 798                         regp->Sequencer[1] = 0x29;
 799                 } else {
 800                         regp->Sequencer[1] = 0x21;
 801                 }
 802         }
 803         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 804                 regp->Sequencer[2] = 0x03; /* select 2 out of 4 planes */
 805         } else {
 806                 regp->Sequencer[2] = 0x0F;
 807         }
 808         regp->Sequencer[3] = 0x00;                     /* Font select */
 809         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 810                 regp->Sequencer[4] = 0x02;
 811         } else {
 812                 regp->Sequencer[4] = 0x0E;                             /* Misc */
 813         }
 814
 815         /*
 816         * CRTC Controller
 817         */
 818         regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
 819         regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
 820         regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
 821         regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0)
 822                                 | SetBit(7);
 823         regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
 824         regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
 825                                 | SetBitField(horizEnd,4:0,4:0);
 826         regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
 827         regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
 828                                 | SetBitField(vertDisplay,8:8,1:1)
 829                                 | SetBitField(vertStart,8:8,2:2)
 830                                 | SetBitField(vertBlankStart,8:8,3:3)
 831                                 | SetBit(4)
 832                                 | SetBitField(vertTotal,9:9,5:5)
 833                                 | SetBitField(vertDisplay,9:9,6:6)
 834                                 | SetBitField(vertStart,9:9,7:7);
 835         regp->CRTC[NV_VGA_CRTCX_PRROWSCN]  = 0x00;
 836         regp->CRTC[NV_VGA_CRTCX_MAXSCLIN]  = SetBitField(vertBlankStart,9:9,5:5)
 837                                 | SetBit(6)
 838                                 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00)
 839                                 | (NVMatchModePrivate(mode, NV_MODE_VGA) ? 0xF : 0x00); /* 8x15 chars */
 840         if (NVMatchModePrivate(mode, NV_MODE_VGA)) { /* Were do these cursor offsets come from? */
 841                 regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0xD; /* start scanline */
 842                 regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0xE; /* end scanline */
 843         } else {
 844                 regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0x00;
 845                 regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0x00;
 846         }
 847         regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00;
 848         regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
 849         regp->CRTC[0xe] = 0x00;
 850         regp->CRTC[0xf] = 0x00;
 851         regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
 852         /* What is the meaning of bit5, it is empty in the vga spec. */
 853         regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) |
 854                                                                         (NVMatchModePrivate(mode, NV_MODE_VGA) ? 0 : SetBit(5));
 855         regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
 856         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 857                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = (mode->CrtcHDisplay/16);
 858         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 859                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((mode->CrtcHDisplay*depth)/64);
 860         } else { /* framebuffer can be larger than crtc scanout area. */
 861                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pScrn->bitsPerPixel/8));
 862         }
 863         if (depth == 4) { /* How can these values be calculated? */
 864                 regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x1F;
 865         } else {
 866                 regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x00;
 867         }
 868         regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
 869         regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
 870         /* 0x80 enables the sequencer, we don't want that */
 871         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 872                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xA3 & ~0x80;
 873         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 874                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xE3 & ~0x80;
 875         } else {
 876                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80;
 877         }
 878         regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
 879
 880         /*
 881          * Some extended CRTC registers (they are not saved with the rest of the vga regs).
 882          */
 883
 884         regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
 885                                 | SetBitField(vertBlankStart,10:10,3:3)
 886                                 | SetBitField(vertStart,10:10,2:2)
 887                                 | SetBitField(vertDisplay,10:10,1:1)
 888                                 | SetBitField(vertTotal,10:10,0:0);
 889
 890         regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
 891                                 | SetBitField(horizDisplay,8:8,1:1)
 892                                 | SetBitField(horizBlankStart,8:8,2:2)
 893                                 | SetBitField(horizStart,8:8,3:3);
 894
 895         regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
 896                                 | SetBitField(vertDisplay,11:11,2:2)
 897                                 | SetBitField(vertStart,11:11,4:4)
 898                                 | SetBitField(vertBlankStart,11:11,6:6);
 899
 900         if(mode->Flags & V_INTERLACE) {
 901                 horizTotal = (horizTotal >> 1) & ~1;
 902                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
 903                 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
 904         } else {
 905                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff;  /* interlace off */
 906         }
 907
 908         /*
 909         * Graphics Display Controller
 910         */
 911         regp->Graphics[0] = 0x00;
 912         regp->Graphics[1] = 0x00;
 913         regp->Graphics[2] = 0x00;
 914         regp->Graphics[3] = 0x00;
 915         regp->Graphics[4] = 0x00;
 916         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 917                 regp->Graphics[5] = 0x10;
 918                 regp->Graphics[6] = 0x0E; /* map 32k mem */
 919                 regp->Graphics[7] = 0x00;
 920         } else {
 921                 regp->Graphics[5] = 0x40; /* 256 color mode */
 922                 regp->Graphics[6] = 0x05; /* map 64k mem + graphic mode */
 923                 regp->Graphics[7] = 0x0F;
 924         }
 925         regp->Graphics[8] = 0xFF;
 926
 927         regp->Attribute[0]  = 0x00; /* standard colormap translation */
 928         regp->Attribute[1]  = 0x01;
 929         regp->Attribute[2]  = 0x02;
 930         regp->Attribute[3]  = 0x03;
 931         regp->Attribute[4]  = 0x04;
 932         regp->Attribute[5]  = 0x05;
 933         regp->Attribute[6]  = 0x06;
 934         regp->Attribute[7]  = 0x07;
 935         regp->Attribute[8]  = 0x08;
 936         regp->Attribute[9]  = 0x09;
 937         regp->Attribute[10] = 0x0A;
 938         regp->Attribute[11] = 0x0B;
 939         regp->Attribute[12] = 0x0C;
 940         regp->Attribute[13] = 0x0D;
 941         regp->Attribute[14] = 0x0E;
 942         regp->Attribute[15] = 0x0F;
 943         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 944                 regp->Attribute[16] = 0x0C; /* Line Graphics Enable + Blink enable */
 945         } else {
 946                 regp->Attribute[16] = 0x01; /* Enable graphic mode */
 947         }
 948         /* Non-vga */
 949         regp->Attribute[17] = 0x00;
 950         regp->Attribute[18] = 0x0F; /* enable all color planes */
 951         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 952                 regp->Attribute[19] = 0x08; /* shift bits by 8 */
 953         } else {
 954                 regp->Attribute[19] = 0x00;
 955         }
 956         regp->Attribute[20] = 0x00;
 957 }
 958
 959 /**
 960  * Sets up registers for the given mode/adjusted_mode pair.
 961  *
 962  * The clocks, CRTCs and outputs attached to this CRTC must be off.
 963  *
 964  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
 965  * be easily turned on/off after this.
 966  */
 967 static void
 968 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
 969 {
 970         ScrnInfoPtr pScrn = crtc->scrn;
 971         NVPtr pNv = NVPTR(pScrn);
 972         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 973         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 974         NVCrtcRegPtr savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
 975         uint32_t depth;
 976         Bool is_fp = FALSE;
 977         Bool is_lvds = FALSE;
 978         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 979         NVOutputPrivatePtr nv_output = NULL;
 980         if (output) {
 981                 nv_output = output->driver_private;
 982
 983                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
 984                         is_fp = TRUE;
 985
 986                 if (nv_output->type == OUTPUT_LVDS)
 987                         is_lvds = TRUE;
 988         }
 989
 990         /* Registers not directly related to the (s)vga mode */
 991
 992         /* bit2 = 0 -> fine pitched crtc granularity */
 993         /* The rest disables double buffering on CRTC access */
 994         regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
 995
 996         if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
 997                 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
 998                 if (nv_crtc->head == 0) {
 999                         regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1000                 }
1001
1002                 if (is_fp) {
1003                         regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0);
1004                         if (!NVMatchModePrivate(mode, NV_MODE_VGA)) {
1005                                 regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 1);
1006                         }
1007                 }
1008         } else {
1009                 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
1010                 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
1011         }
1012
1013         /* Sometimes 0x10 is used, what is this? */
1014         regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1015         /* Some kind of tmds switch for older cards */
1016         if (pNv->Architecture < NV_ARCH_40) {
1017                 regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
1018         }
1019
1020         /*
1021         * Calculate the extended registers.
1022         */
1023
1024         if (pScrn->depth < 24)
1025                 depth = pScrn->depth;
1026         else
1027                 depth = 32;
1028
1029         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1030                 /* bpp is pitch related. */
1031                 depth = pNv->console_mode[nv_crtc->head].bpp;
1032         }
1033
1034         /* What is the meaning of this register? */
1035         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1036         regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
1037
1038         regp->head = 0;
1039
1040         /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1041         /* But what are those special conditions? */
1042         if (pNv->Architecture <= NV_ARCH_30) {
1043                 if (is_fp) {
1044                         if(nv_crtc->head == 1) {
1045                                 regp->head |= NV_CRTC_FSEL_FPP1;
1046                         } else if (pNv->twoHeads) {
1047                                 regp->head |= NV_CRTC_FSEL_FPP2;
1048                         }
1049                 }
1050         } else {
1051                 /* Most G70 cards have FPP2 set on the secondary CRTC. */
1052                 if (nv_crtc->head == 1 && pNv->NVArch > 0x44) {
1053                         regp->head |= NV_CRTC_FSEL_FPP2;
1054                 }
1055         }
1056
1057         /* Except for rare conditions I2C is enabled on the primary crtc */
1058         if (nv_crtc->head == 0) {
1059                 regp->head |= NV_CRTC_FSEL_I2C;
1060         }
1061
1062         /* Set overlay to desired crtc. */
1063         if (pNv->overlayAdaptor) {
1064                 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(pNv);
1065                 if (pPriv->overlayCRTC == nv_crtc->head)
1066                         regp->head |= NV_CRTC_FSEL_OVERLAY;
1067         }
1068
1069         /* This is not what nv does, but it is what the blob does (for nv4x at least) */
1070         /* This fixes my cursor corruption issue */
1071         regp->cursorConfig = 0x0;
1072         if(mode->Flags & V_DBLSCAN)
1073                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_DOUBLE_SCAN;
1074         if (pNv->alphaCursor && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1075                 regp->cursorConfig |=   (NV_CRTC_CURSOR_CONFIG_32BPP |
1076                                                         NV_CRTC_CURSOR_CONFIG_64PIXELS |
1077                                                         NV_CRTC_CURSOR_CONFIG_64LINES |
1078                                                         NV_CRTC_CURSOR_CONFIG_ALPHA_BLEND);
1079         } else {
1080                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_32LINES;
1081         }
1082
1083         /* Unblock some timings */
1084         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1085         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1086
1087         /* What is the purpose of this register? */
1088         /* 0x14 may be disabled? */
1089         regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1090
1091         /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
1092         if (is_lvds) {
1093                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x11;
1094         } else if (is_fp) {
1095                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1096         } else {
1097                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1098         }
1099
1100         /* These values seem to vary */
1101         /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
1102         regp->CRTC[NV_VGA_CRTCX_SCRATCH4] = savep->CRTC[NV_VGA_CRTCX_SCRATCH4];
1103
1104         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1105                 regp->CRTC[NV_VGA_CRTCX_45] = 0x0;
1106         } else {
1107                 regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1108         }
1109
1110         /* What does this do?:
1111          * bit0: crtc0
1112          * bit6: lvds
1113          * bit7: lvds + tmds (only in X)
1114          */
1115         if (nv_crtc->head == 0)
1116                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x1;
1117         else
1118                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x0;
1119
1120         if (is_lvds)
1121                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x40;
1122
1123         if (is_fp && !NVMatchModePrivate(mode, NV_MODE_VGA))
1124                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x80;
1125
1126         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) { /* we need consistent restore. */
1127                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[nv_crtc->head];
1128         } else {
1129                 /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1.*/
1130                 if (nv_crtc->head == 1) {
1131                         regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[0];
1132                 } else {
1133                         regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[0] + 4;
1134                 }
1135         }
1136
1137         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1138                 regp->unk830 = 0;
1139                 regp->unk834 = 0;
1140         } else {
1141                 regp->unk830 = mode->CrtcVDisplay - 3;
1142                 regp->unk834 = mode->CrtcVDisplay - 1;
1143         }
1144
1145         if (pNv->twoHeads)
1146                 /* This is what the blob does */
1147                 regp->unk850 = NVReadCRTC(pNv, 0, NV_CRTC_0850);
1148
1149         /* Never ever modify gpio, unless you know very well what you're doing */
1150         regp->gpio = NVReadCRTC(pNv, 0, NV_CRTC_GPIO);
1151
1152         if (pNv->twoHeads)
1153                 regp->gpio_ext = NVReadCRTC(pNv, 0, NV_CRTC_GPIO_EXT);
1154
1155         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1156                 regp->config = 0x0; /* VGA mode */
1157         } else {
1158                 regp->config = 0x2; /* HSYNC mode */
1159         }
1160
1161         /* Some misc regs */
1162         if (pNv->Architecture == NV_ARCH_40) {
1163                 regp->CRTC[NV_VGA_CRTCX_85] = 0xFF;
1164                 regp->CRTC[NV_VGA_CRTCX_86] = 0x1;
1165         }
1166
1167         /*
1168          * Calculate the state that is common to all crtc's (stored in the state struct).
1169          */
1170         nv_crtc_calc_state_ext(crtc,
1171                                 mode,
1172                                 depth,
1173                                 pScrn->displayWidth,
1174                                 mode->CrtcHDisplay,
1175                                 mode->CrtcVDisplay,
1176                                 adjusted_mode->Clock,
1177                                 mode->Flags);
1178
1179         /* Enable slaved mode */
1180         if (is_fp) {
1181                 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1182         }
1183 }
1184
1185 static void
1186 nv_crtc_mode_set_ramdac_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1187 {
1188         ScrnInfoPtr pScrn = crtc->scrn;
1189         NVPtr pNv = NVPTR(pScrn);
1190         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1191         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1192         NVCrtcRegPtr savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1193         Bool is_fp = FALSE;
1194         Bool is_lvds = FALSE;
1195         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1196         NVOutputPrivatePtr nv_output = NULL;
1197         if (output) {
1198                 nv_output = output->driver_private;
1199
1200                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1201                         is_fp = TRUE;
1202
1203                 if (nv_output->type == OUTPUT_LVDS)
1204                         is_lvds = TRUE;
1205         }
1206
1207         if (is_fp) {
1208                 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
1209                 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
1210                 /* This is what the blob does. */
1211                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HSyncStart - 75 - 1;
1212                 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
1213                 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
1214                 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
1215                 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
1216
1217                 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
1218                 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
1219                 /* This is what the blob does. */
1220                 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VTotal - 5 - 1;
1221                 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
1222                 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
1223                 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
1224                 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
1225
1226 #if 0
1227                 ErrorF("Horizontal:\n");
1228                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
1229                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
1230                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
1231                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
1232                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
1233                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
1234                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
1235
1236                 ErrorF("Vertical:\n");
1237                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
1238                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
1239                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
1240                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
1241                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
1242                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
1243                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
1244 #endif
1245         }
1246
1247         /*
1248         * bit0: positive vsync
1249         * bit4: positive hsync
1250         * bit8: enable center mode
1251         * bit9: enable native mode
1252         * bit24: 12/24 bit interface (12bit=on, 24bit=off)
1253         * bit26: a bit sometimes seen on some g70 cards
1254         * bit28: fp display enable bit
1255         * bit31: set for dual link LVDS
1256         * nv10reg contains a few more things, but i don't quite get what it all means.
1257         */
1258
1259         if (pNv->Architecture >= NV_ARCH_30)
1260                 regp->fp_control[nv_crtc->head] = 0x00100000;
1261         else
1262                 regp->fp_control[nv_crtc->head] = 0x00000000;
1263
1264         /* Deal with vsync/hsync polarity */
1265         /* LVDS screens do set this, but modes with +ve syncs are very rare */
1266         if (is_fp) {
1267                 if (adjusted_mode->Flags & V_PVSYNC)
1268                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
1269                 if (adjusted_mode->Flags & V_PHSYNC)
1270                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
1271         } else {
1272                 /* The blob doesn't always do this, but often */
1273                 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_VSYNC_DISABLE;
1274                 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_HSYNC_DISABLE;
1275         }
1276
1277         if (is_fp) {
1278                 if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) /* seems to be used almost always */
1279                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1280                 else if (nv_output->scaling_mode == SCALE_PANEL) /* panel needs to scale */
1281                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
1282                 /* This is also true for panel scaling, so we must put the panel scale check first */
1283                 else if (mode->Clock == adjusted_mode->Clock) /* native mode */
1284                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
1285                 else /* gpu needs to scale */
1286                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1287         }
1288
1289         if (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
1290                 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_WIDTH_12;
1291
1292         /* If the special bit exists, it exists on both ramdacs */
1293         regp->fp_control[nv_crtc->head] |= NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL) & (1 << 26);
1294
1295         if (is_fp)
1296                 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_DISPEN_POS;
1297         else
1298                 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_DISPEN_DISABLE;
1299
1300         if (is_lvds && pNv->VBIOS.fp.dual_link)
1301                 regp->fp_control[nv_crtc->head] |= (8 << 28);
1302
1303         if (is_fp) {
1304                 /* This can override HTOTAL and VTOTAL */
1305                 regp->debug_2 = 0;
1306                 /* We want automatic scaling */
1307                 regp->debug_1 = 0;
1308
1309                 regp->fp_hvalid_start = 0;
1310                 regp->fp_hvalid_end = (nv_output->fpWidth - 1);
1311                 regp->fp_vvalid_start = 0;
1312                 regp->fp_vvalid_end = (nv_output->fpHeight - 1);
1313
1314                 if (nv_output->scaling_mode == SCALE_ASPECT) {
1315                         /* Use 20.12 fixed point format to avoid floats */
1316                         uint32_t panel_ratio = (1 << 12) * nv_output->fpWidth / nv_output->fpHeight;
1317                         uint32_t aspect_ratio = (1 << 12) * mode->HDisplay / mode->VDisplay;
1318                         uint32_t h_scale = (1 << 12) * mode->HDisplay / nv_output->fpWidth;
1319                         uint32_t v_scale = (1 << 12) * mode->VDisplay / nv_output->fpHeight;
1320                         #define ONE_TENTH ((1 << 12) / 10)
1321
1322                         /* GPU scaling happens automatically at a ratio of 1.33 */
1323                         /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
1324                         if (h_scale != (1 << 12) && (panel_ratio > aspect_ratio + ONE_TENTH)) {
1325                                 uint32_t diff;
1326
1327                                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Maintaining aspect ratio requires vertical black bars.\n");
1328
1329                                 /* Scaling in both directions needs to the same */
1330                                 h_scale = v_scale;
1331
1332                                 /* Set a new horizontal scale factor and enable testmode (bit12) */
1333                                 regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
1334
1335                                 diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
1336                                 regp->fp_hvalid_start = diff/2;
1337                                 regp->fp_hvalid_end = nv_output->fpWidth - (diff/2) - 1;
1338                         }
1339
1340                         /* Same scaling, just for panels with aspect ratios smaller than 1 */
1341                         if (v_scale != (1 << 12) && (panel_ratio < aspect_ratio - ONE_TENTH)) {
1342                                 uint32_t diff;
1343
1344                                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Maintaining aspect ratio requires horizontal black bars.\n");
1345
1346                                 /* Scaling in both directions needs to the same */
1347                                 v_scale = h_scale;
1348
1349                                 /* Set a new vertical scale factor and enable testmode (bit28) */
1350                                 regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
1351
1352                                 diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
1353                                 regp->fp_vvalid_start = diff/2;
1354                                 regp->fp_vvalid_end = nv_output->fpHeight - (diff/2) - 1;
1355                         }
1356                 }
1357         }
1358
1359         if (!is_fp && NVMatchModePrivate(mode, NV_MODE_VGA)) {
1360                 regp->debug_1 = 0x08000800;
1361         }
1362
1363         if (pNv->Architecture >= NV_ARCH_10) {
1364                 /* Only bit that bios and blob set. */
1365                 regp->nv10_cursync = (1<<25);
1366         }
1367
1368         /* These are the common blob values, minus a few fp specific bit's */
1369         /* Let's keep the TMDS pll and fpclock running in all situations */
1370         regp->debug_0[nv_crtc->head] = 0x1101100;
1371
1372         if (is_fp && nv_output->scaling_mode != SCALE_NOSCALE) {
1373                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_XSCALE_ENABLED;
1374                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_YSCALE_ENABLED;
1375         } else if (is_fp) { /* no_scale mode, so we must center it */
1376                 uint32_t diff;
1377
1378                 diff = nv_output->fpWidth - mode->HDisplay;
1379                 regp->fp_hvalid_start = diff/2;
1380                 regp->fp_hvalid_end = (nv_output->fpWidth - diff/2 - 1);
1381
1382                 diff = nv_output->fpHeight - mode->VDisplay;
1383                 regp->fp_vvalid_start = diff/2;
1384                 regp->fp_vvalid_end = (nv_output->fpHeight - diff/2 - 1);
1385         }
1386
1387         /* Is this crtc bound or output bound? */
1388         /* Does the bios TMDS script try to change this sometimes? */
1389         if (is_fp) {
1390                 /* I am not completely certain, but seems to be set only for dfp's */
1391                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED;
1392         }
1393
1394         /* Flatpanel support needs at least a NV10 */
1395         if (pNv->twoHeads) {
1396                 if (pNv->FPDither || (is_lvds && !pNv->VBIOS.fp.if_is_24bit)) {
1397                         nv_crtc->ditherEnabled = TRUE;
1398                         if (pNv->NVArch == 0x11)
1399                                 regp->dither = savep->dither | 0x00010000;
1400                         else {
1401                                 int i;
1402                                 regp->dither = savep->dither | 0x00000001;
1403                                 for (i = 0; i < 3; i++) {
1404                                         regp->dither_regs[i] = 0xe4e4e4e4;
1405                                         regp->dither_regs[i + 3] = 0x44444444;
1406                                 }
1407                         }
1408                 } else {
1409                         nv_crtc->ditherEnabled = FALSE;
1410                         regp->dither = savep->dither;
1411                 }
1412         }
1413
1414         uint8_t depth;
1415         /* This is mode related, not pitch. */
1416         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE))
1417                 depth = pNv->console_mode[nv_crtc->head].depth;
1418         else
1419                 depth = pScrn->depth;
1420
1421         switch (depth) {
1422                 case 4:
1423                         regp->general = 0x00000100;
1424                         break;
1425                 case 24:
1426                 case 15:
1427                         regp->general = 0x00100100;
1428                         break;
1429                 case 32:
1430                 case 16:
1431                 case 8:
1432                 default:
1433                         regp->general = 0x00101100;
1434                         break;
1435         }
1436
1437         if (depth > 8 && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1438                 regp->general |= 0x30; /* enable palette mode */
1439         }
1440
1441         if (pNv->alphaCursor && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1442                 /* PIPE_LONG mode, something to do with the size of the cursor? */
1443                 regp->general |= (1<<29);
1444         }
1445
1446         /* Some values the blob sets */
1447         /* This may apply to the real ramdac that is being used (for crosswired situations) */
1448         /* Nevertheless, it's unlikely to cause many problems, since the values are equal for both */
1449         regp->unk_a20 = 0x0;
1450         regp->unk_a24 = 0xfffff;
1451         regp->unk_a34 = 0x1;
1452
1453         if (pNv->twoHeads) {
1454                 /* Do we also "own" the other register pair? */
1455                 /* If we own neither, they will just be ignored at load time. */
1456                 uint8_t other_head = (~nv_crtc->head) & 1;
1457                 if (pNv->fp_regs_owner[other_head] == nv_crtc->head) {
1458                         if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS) {
1459                                 regp->fp_control[other_head] = regp->fp_control[nv_crtc->head];
1460                                 regp->debug_0[other_head] = regp->debug_0[nv_crtc->head];
1461                                 /* Set TMDS_PLL and FPCLK, only seen for a NV31M so far. */
1462                                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK;
1463                                 regp->debug_0[other_head] |= NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL;
1464                         } else {
1465                                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "This is BAD, we own more than one flat panel register set, but are not a LVDS or TMDS output.\n");
1466                         }
1467                 }
1468         }
1469 }
1470
1471 /**
1472  * Sets up registers for the given mode/adjusted_mode pair.
1473  *
1474  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1475  *
1476  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1477  * be easily turned on/off after this.
1478  */
1479 static void
1480 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
1481                  DisplayModePtr adjusted_mode,
1482                  int x, int y)
1483 {
1484         ScrnInfoPtr pScrn = crtc->scrn;
1485         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1486         NVPtr pNv = NVPTR(pScrn);
1487
1488         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_mode_set is called for CRTC %d.\n", nv_crtc->head);
1489
1490         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->head);
1491         xf86PrintModeline(pScrn->scrnIndex, mode);
1492         if (pNv->twoHeads)
1493                 NVSetOwner(pScrn, nv_crtc->head);
1494
1495         nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
1496
1497         /* set sel_clk before calculating PLLs */
1498         nv_crtc_mode_set_sel_clk(crtc, &pNv->ModeReg);
1499         if (pNv->Architecture == NV_ARCH_40) {
1500                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_SEL_CLK %08X\n", pNv->ModeReg.sel_clk);
1501                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, pNv->ModeReg.sel_clk);
1502         }
1503         nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
1504         nv_crtc_mode_set_ramdac_regs(crtc, mode, adjusted_mode);
1505
1506         NVVgaProtect(pNv, nv_crtc->head, true);
1507         nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
1508         nv_crtc_load_state_ext(crtc, &pNv->ModeReg, FALSE);
1509         if (pScrn->depth > 8)
1510                 nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
1511         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
1512         if (pNv->Architecture == NV_ARCH_40) {
1513                 nv40_crtc_load_state_pll(pScrn, &pNv->ModeReg);
1514         } else {
1515                 nv_crtc_load_state_pll(pScrn, &pNv->ModeReg);
1516         }
1517
1518         NVVgaProtect(pNv, nv_crtc->head, false);
1519
1520         NVCrtcSetBase(crtc, x, y, NVMatchModePrivate(mode, NV_MODE_CONSOLE));
1521
1522 #if X_BYTE_ORDER == X_BIG_ENDIAN
1523         /* turn on LFB swapping */
1524         {
1525                 unsigned char tmp;
1526
1527                 tmp = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_SWAPPING);
1528                 tmp |= (1 << 7);
1529                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_SWAPPING, tmp);
1530         }
1531 #endif
1532 }
1533
1534 static void nv_crtc_save(xf86CrtcPtr crtc)
1535 {
1536         ScrnInfoPtr pScrn = crtc->scrn;
1537         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1538         NVPtr pNv = NVPTR(pScrn);
1539
1540         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_save is called for CRTC %d.\n", nv_crtc->head);
1541
1542         /* We just came back from terminal, so unlock */
1543         NVCrtcLockUnlock(crtc, FALSE);
1544
1545         nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
1546         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
1547         nv_crtc_save_state_palette(crtc, &pNv->SavedReg);
1548         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
1549         if (pNv->Architecture == NV_ARCH_40)
1550                 nv40_crtc_save_state_pll(pScrn, &pNv->SavedReg);
1551         else
1552                 nv_crtc_save_state_pll(pScrn, &pNv->SavedReg);
1553 }
1554
1555 static void nv_crtc_restore(xf86CrtcPtr crtc)
1556 {
1557         ScrnInfoPtr pScrn = crtc->scrn;
1558         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1559         NVPtr pNv = NVPTR(pScrn);
1560         RIVA_HW_STATE *state;
1561         NVCrtcRegPtr savep;
1562
1563         state = &pNv->SavedReg;
1564         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1565
1566         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_restore is called for CRTC %d.\n", nv_crtc->head);
1567
1568         /* Just to be safe */
1569         NVCrtcLockUnlock(crtc, FALSE);
1570
1571         NVVgaProtect(pNv, nv_crtc->head, true);
1572         nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
1573         nv_crtc_load_state_ext(crtc, &pNv->SavedReg, TRUE);
1574         nv_crtc_load_state_palette(crtc, &pNv->SavedReg);
1575         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
1576
1577         /* Force restoring vpll. */
1578         state->vpll_changed[nv_crtc->head] = TRUE;
1579
1580         if (pNv->Architecture == NV_ARCH_40) {
1581                 nv40_crtc_load_state_pll(pScrn, &pNv->SavedReg);
1582         } else {
1583                 nv_crtc_load_state_pll(pScrn, &pNv->SavedReg);
1584         }
1585         NVVgaProtect(pNv, nv_crtc->head, false);
1586
1587         nv_crtc->last_dpms = NV_DPMS_CLEARED;
1588 }
1589
1590 static void
1591 NVResetCrtcConfig(xf86CrtcPtr crtc, Bool set)
1592 {
1593         ScrnInfoPtr pScrn = crtc->scrn;
1594         NVPtr pNv = NVPTR(pScrn);
1595
1596         if (pNv->twoHeads) {
1597                 uint32_t val = 0;
1598
1599                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1600
1601                 if (set) {
1602                         NVCrtcRegPtr regp;
1603
1604                         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1605                         val = regp->head;
1606                 }
1607
1608                 NVCrtcWriteCRTC(crtc, NV_CRTC_FSEL, val);
1609         }
1610 }
1611
1612 static void nv_crtc_prepare(xf86CrtcPtr crtc)
1613 {
1614         ScrnInfoPtr pScrn = crtc->scrn;
1615         NVPtr pNv = NVPTR(pScrn);
1616         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1617
1618         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_prepare is called for CRTC %d.\n", nv_crtc->head);
1619
1620         /* Just in case */
1621         NVCrtcLockUnlock(crtc, 0);
1622
1623         NVResetCrtcConfig(crtc, FALSE);
1624
1625         crtc->funcs->dpms(crtc, DPMSModeOff);
1626
1627         /* Sync the engine before adjust mode */
1628         if (pNv->EXADriverPtr) {
1629                 exaMarkSync(pScrn->pScreen);
1630                 exaWaitSync(pScrn->pScreen);
1631         }
1632
1633         NVBlankScreen(pScrn, nv_crtc->head, true);
1634
1635         /* Some more preperation. */
1636         NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, 0x1); /* Go to non-vga mode/out of enhanced mode */
1637         if (pNv->Architecture == NV_ARCH_40) {
1638                 uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
1639                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
1640         }
1641 }
1642
1643 static void nv_crtc_commit(xf86CrtcPtr crtc)
1644 {
1645         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1646         ScrnInfoPtr pScrn = crtc->scrn;
1647         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_commit for CRTC %d.\n", nv_crtc->head);
1648
1649         crtc->funcs->dpms (crtc, DPMSModeOn);
1650
1651         if (crtc->scrn->pScreen != NULL) {
1652                 NVPtr pNv = NVPTR(crtc->scrn);
1653
1654                 xf86_reload_cursors (crtc->scrn->pScreen);
1655                 if (!pNv->alphaCursor) {
1656                         /* this works round the fact that xf86_reload_cursors
1657                          * will quite happily show the hw cursor when it knows
1658                          * the hardware can't do alpha, and the current cursor
1659                          * has an alpha channel
1660                          */
1661                         xf86ForceHWCursor(crtc->scrn->pScreen, 1);
1662                         xf86ForceHWCursor(crtc->scrn->pScreen, 0);
1663                 }
1664         }
1665
1666         NVResetCrtcConfig(crtc, TRUE);
1667 }
1668
1669 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
1670 {
1671         return FALSE;
1672 }
1673
1674 static void nv_crtc_unlock(xf86CrtcPtr crtc)
1675 {
1676 }
1677
1678 static void
1679 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
1680                                         int size)
1681 {
1682         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1683         ScrnInfoPtr pScrn = crtc->scrn;
1684         NVPtr pNv = NVPTR(pScrn);
1685         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1686         int i, j;
1687
1688         switch (pScrn->depth) {
1689         case 15:
1690                 /* R5G5B5 */
1691                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
1692                 for (i = 0; i < 32; i++) {
1693                         for (j = 0; j < 8; j++) {
1694                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1695                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
1696                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1697                         }
1698                 }
1699                 break;
1700         case 16:
1701                 /* R5G6B5 */
1702                 /* First deal with the 5 bit colors */
1703                 for (i = 0; i < 32; i++) {
1704                         for (j = 0; j < 8; j++) {
1705                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1706                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1707                         }
1708                 }
1709                 /* Now deal with the 6 bit color */
1710                 for (i = 0; i < 64; i++) {
1711                         for (j = 0; j < 4; j++) {
1712                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
1713                         }
1714                 }
1715                 break;
1716         default:
1717                 /* R8G8B8 */
1718                 for (i = 0; i < 256; i++) {
1719                         regp->DAC[i * 3] = red[i] >> 8;
1720                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
1721                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
1722                 }
1723                 break;
1724         }
1725
1726         nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
1727 }
1728
1729 /**
1730  * Allocates memory for a locked-in-framebuffer shadow of the given
1731  * width and height for this CRTC's rotated shadow framebuffer.
1732  */
1733
1734 static void *
1735 nv_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
1736 {
1737         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1738         ScrnInfoPtr pScrn = crtc->scrn;
1739 #if !NOUVEAU_EXA_PIXMAPS
1740         ScreenPtr pScreen = pScrn->pScreen;
1741 #endif /* !NOUVEAU_EXA_PIXMAPS */
1742         NVPtr pNv = NVPTR(pScrn);
1743         void *offset;
1744
1745         unsigned long rotate_pitch;
1746         int size, align = 64;
1747
1748         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_shadow_allocate is called.\n");
1749
1750         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
1751         size = rotate_pitch * height;
1752
1753         assert(nv_crtc->shadow == NULL);
1754 #if NOUVEAU_EXA_PIXMAPS
1755         if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN,
1756                         align, size, &nv_crtc->shadow)) {
1757                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to allocate memory for shadow buffer!\n");
1758                 return NULL;
1759         }
1760
1761         if (nv_crtc->shadow && nouveau_bo_map(nv_crtc->shadow, NOUVEAU_BO_RDWR)) {
1762                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1763                                 "Failed to map shadow buffer.\n");
1764                 return NULL;
1765         }
1766
1767         offset = nv_crtc->shadow->map;
1768 #else
1769         nv_crtc->shadow = exaOffscreenAlloc(pScreen, size, align, TRUE, NULL, NULL);
1770         if (nv_crtc->shadow == NULL) {
1771                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1772                         "Couldn't allocate shadow memory for rotated CRTC.\n");
1773                 return NULL;
1774         }
1775         offset = pNv->FB->map + nv_crtc->shadow->offset;
1776 #endif /* NOUVEAU_EXA_PIXMAPS */
1777
1778         return offset;
1779 }
1780
1781 /**
1782  * Creates a pixmap for this CRTC's rotated shadow framebuffer.
1783  */
1784 static PixmapPtr
1785 nv_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
1786 {
1787         ScrnInfoPtr pScrn = crtc->scrn;
1788 #if NOUVEAU_EXA_PIXMAPS
1789         ScreenPtr pScreen = pScrn->pScreen;
1790         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1791 #endif /* NOUVEAU_EXA_PIXMAPS */
1792         unsigned long rotate_pitch;
1793         PixmapPtr rotate_pixmap;
1794 #if NOUVEAU_EXA_PIXMAPS
1795         struct nouveau_pixmap *nvpix;
1796 #endif /* NOUVEAU_EXA_PIXMAPS */
1797
1798         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_shadow_create is called.\n");
1799
1800         if (!data)
1801                 data = crtc->funcs->shadow_allocate (crtc, width, height);
1802
1803         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
1804
1805 #if NOUVEAU_EXA_PIXMAPS
1806         /* Create a dummy pixmap, to get a private that will be accepted by the system.*/
1807         rotate_pixmap = pScreen->CreatePixmap(pScreen,
1808                                                                 0, /* width */
1809                                                                 0, /* height */
1810         #ifdef CREATE_PIXMAP_USAGE_SCRATCH /* there seems to have been no api bump */
1811                                                                 pScrn->depth,
1812                                                                 0);
1813         #else
1814                                                                 pScrn->depth);
1815         #endif /* CREATE_PIXMAP_USAGE_SCRATCH */
1816 #else
1817         rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen,
1818                                                                 width, height,
1819                                                                 pScrn->depth,
1820                                                                 pScrn->bitsPerPixel,
1821                                                                 rotate_pitch,
1822                                                                 data);
1823 #endif /* NOUVEAU_EXA_PIXMAPS */
1824
1825         if (rotate_pixmap == NULL) {
1826                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1827                         "Couldn't allocate shadow pixmap for rotated CRTC\n");
1828         }
1829
1830 #if NOUVEAU_EXA_PIXMAPS
1831         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
1832         if (!nvpix) {
1833                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No initial shadow private available for rotation.\n");
1834         } else {
1835                 nvpix->bo = nv_crtc->shadow;
1836                 nvpix->mapped = TRUE;
1837         }
1838
1839         /* Modify the pixmap to actually be the one we need. */
1840         pScreen->ModifyPixmapHeader(rotate_pixmap,
1841                                         width,
1842                                         height,
1843                                         pScrn->depth,
1844                                         pScrn->bitsPerPixel,
1845                                         rotate_pitch,
1846                                         data);
1847
1848         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
1849         if (!nvpix || !nvpix->bo)
1850                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No final shadow private available for rotation.\n");
1851 #endif /* NOUVEAU_EXA_PIXMAPS */
1852
1853         return rotate_pixmap;
1854 }
1855
1856 static void
1857 nv_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
1858 {
1859         ScrnInfoPtr pScrn = crtc->scrn;
1860         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1861         ScreenPtr pScreen = pScrn->pScreen;
1862
1863         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_shadow_destroy is called.\n");
1864
1865         if (rotate_pixmap) { /* This should also unmap the buffer object if relevant. */
1866                 pScreen->DestroyPixmap(rotate_pixmap);
1867         }
1868
1869 #if !NOUVEAU_EXA_PIXMAPS
1870         if (data && nv_crtc->shadow) {
1871                 exaOffscreenFree(pScreen, nv_crtc->shadow);
1872         }
1873 #endif /* !NOUVEAU_EXA_PIXMAPS */
1874
1875         nv_crtc->shadow = NULL;
1876 }
1877
1878 /* NV04-NV10 doesn't support alpha cursors */
1879 static const xf86CrtcFuncsRec nv_crtc_funcs = {
1880         .dpms = nv_crtc_dpms,
1881         .save = nv_crtc_save, /* XXX */
1882         .restore = nv_crtc_restore, /* XXX */
1883         .mode_fixup = nv_crtc_mode_fixup,
1884         .mode_set = nv_crtc_mode_set,
1885         .prepare = nv_crtc_prepare,
1886         .commit = nv_crtc_commit,
1887         .destroy = NULL, /* XXX */
1888         .lock = nv_crtc_lock,
1889         .unlock = nv_crtc_unlock,
1890         .set_cursor_colors = nv_crtc_set_cursor_colors,
1891         .set_cursor_position = nv_crtc_set_cursor_position,
1892         .show_cursor = nv_crtc_show_cursor,
1893         .hide_cursor = nv_crtc_hide_cursor,
1894         .load_cursor_image = nv_crtc_load_cursor_image,
1895         .gamma_set = nv_crtc_gamma_set,
1896         .shadow_create = nv_crtc_shadow_create,
1897         .shadow_allocate = nv_crtc_shadow_allocate,
1898         .shadow_destroy = nv_crtc_shadow_destroy,
1899 };
1900
1901 /* NV11 and up has support for alpha cursors. */
1902 /* Due to different maximum sizes we cannot allow it to use normal cursors */
1903 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
1904         .dpms = nv_crtc_dpms,
1905         .save = nv_crtc_save, /* XXX */
1906         .restore = nv_crtc_restore, /* XXX */
1907         .mode_fixup = nv_crtc_mode_fixup,
1908         .mode_set = nv_crtc_mode_set,
1909         .prepare = nv_crtc_prepare,
1910         .commit = nv_crtc_commit,
1911         .destroy = NULL, /* XXX */
1912         .lock = nv_crtc_lock,
1913         .unlock = nv_crtc_unlock,
1914         .set_cursor_colors = NULL, /* Alpha cursors do not need this */
1915         .set_cursor_position = nv_crtc_set_cursor_position,
1916         .show_cursor = nv_crtc_show_cursor,
1917         .hide_cursor = nv_crtc_hide_cursor,
1918         .load_cursor_argb = nv_crtc_load_cursor_argb,
1919         .gamma_set = nv_crtc_gamma_set,
1920         .shadow_create = nv_crtc_shadow_create,
1921         .shadow_allocate = nv_crtc_shadow_allocate,
1922         .shadow_destroy = nv_crtc_shadow_destroy,
1923 };
1924
1925
1926 void
1927 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
1928 {
1929         NVPtr pNv = NVPTR(pScrn);
1930         xf86CrtcPtr crtc;
1931         NVCrtcPrivatePtr nv_crtc;
1932         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[crtc_num];
1933         int i;
1934
1935         if (pNv->NVArch >= 0x11)
1936                 crtc = xf86CrtcCreate(pScrn, &nv11_crtc_funcs);
1937         else
1938                 crtc = xf86CrtcCreate(pScrn, &nv_crtc_funcs);
1939         if (crtc == NULL)
1940                 return;
1941
1942         nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
1943         nv_crtc->head = crtc_num;
1944         nv_crtc->last_dpms = NV_DPMS_CLEARED;
1945         nv_crtc->ditherEnabled = pNv->FPDither;
1946         pNv->fp_regs_owner[nv_crtc->head] = nv_crtc->head;
1947
1948         crtc->driver_private = nv_crtc;
1949
1950         /* Initialise the default LUT table. */
1951         for (i = 0; i < 256; i++) {
1952                 regp->DAC[i*3] = i;
1953                 regp->DAC[(i*3)+1] = i;
1954                 regp->DAC[(i*3)+2] = i;
1955         }
1956
1957         NVCrtcLockUnlock(crtc, FALSE);
1958 }
1959
1960 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1961 {
1962         ScrnInfoPtr pScrn = crtc->scrn;
1963         NVPtr pNv = NVPTR(pScrn);
1964         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1965         int i;
1966         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
1967
1968         NVWritePVIO(pNv, nv_crtc->head, VGA_MISC_OUT_W, regp->MiscOutReg);
1969
1970         for (i = 0; i < 5; i++)
1971                 NVWriteVgaSeq(pNv, nv_crtc->head, i, regp->Sequencer[i]);
1972
1973         /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
1974         NVWriteVgaCrtc(pNv, nv_crtc->head, 17, regp->CRTC[17] & ~0x80);
1975
1976         for (i = 0; i < 25; i++)
1977                 NVWriteVgaCrtc(pNv, nv_crtc->head, i, regp->CRTC[i]);
1978
1979         for (i = 0; i < 9; i++)
1980                 NVWriteVgaGr(pNv, nv_crtc->head, i, regp->Graphics[i]);
1981
1982         NVSetEnablePalette(pNv, nv_crtc->head, true);
1983         for (i = 0; i < 21; i++)
1984                 NVWriteVgaAttr(pNv, nv_crtc->head, i, regp->Attribute[i]);
1985
1986         NVSetEnablePalette(pNv, nv_crtc->head, false);
1987 }
1988
1989 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override)
1990 {
1991         ScrnInfoPtr pScrn = crtc->scrn;
1992         NVPtr pNv = NVPTR(pScrn);
1993         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1994         NVCrtcRegPtr regp;
1995         int i;
1996
1997         regp = &state->crtc_reg[nv_crtc->head];
1998
1999         if (pNv->Architecture >= NV_ARCH_10) {
2000                 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
2001                 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
2002                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
2003                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
2004                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2005                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2006                 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2007                 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2008                 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, 0);
2009
2010                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
2011                 NVCrtcWriteCRTC(crtc, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
2012                 NVCrtcWriteCRTC(crtc, NV_CRTC_0830, regp->unk830);
2013                 NVCrtcWriteCRTC(crtc, NV_CRTC_0834, regp->unk834);
2014                 if (pNv->Architecture == NV_ARCH_40) {
2015                         NVCrtcWriteCRTC(crtc, NV_CRTC_0850, regp->unk850);
2016                         NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO_EXT, regp->gpio_ext);
2017                 }
2018
2019                 if (pNv->Architecture == NV_ARCH_40) {
2020                         uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
2021                         if (regp->config == 0x2) { /* enhanced "horizontal only" non-vga mode */
2022                                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 | 0x10000);
2023                         } else {
2024                                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
2025                         }
2026                 }
2027         }
2028
2029         NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, regp->config);
2030         NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO, regp->gpio);
2031
2032         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
2033         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
2034         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
2035         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
2036         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
2037         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
2038         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
2039         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
2040         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
2041         if (pNv->Architecture >= NV_ARCH_30)
2042                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
2043
2044         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
2045         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
2046         if (pNv->Architecture == NV_ARCH_40) /* HW bug */
2047                 nv_crtc_fix_nv40_hw_cursor(pScrn, nv_crtc->head);
2048         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
2049         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
2050
2051         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
2052         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
2053         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_SCRATCH4, regp->CRTC[NV_VGA_CRTCX_SCRATCH4]);
2054         if (pNv->Architecture >= NV_ARCH_10) {
2055                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
2056                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
2057                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_4B, regp->CRTC[NV_VGA_CRTCX_4B]);
2058                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
2059         }
2060         /* NV11 and NV20 stop at 0x52. */
2061         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
2062                 if (override)
2063                         for (i = 0; i < 0x10; i++)
2064                                 NVWriteVgaCrtc5758(pNv, nv_crtc->head, i, regp->CR58[i]);
2065
2066                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
2067                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
2068
2069                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
2070
2071                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_85, regp->CRTC[NV_VGA_CRTCX_85]);
2072                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_86, regp->CRTC[NV_VGA_CRTCX_86]);
2073         }
2074
2075         /* Setting 1 on this value gives you interrupts for every vblank period. */
2076         NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_EN_0, 0);
2077         NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
2078 }
2079
2080 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2081 {
2082         ScrnInfoPtr pScrn = crtc->scrn;
2083         NVPtr pNv = NVPTR(pScrn);
2084         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2085         int i;
2086         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
2087
2088         regp->MiscOutReg = NVReadPVIO(pNv, nv_crtc->head, VGA_MISC_OUT_R);
2089
2090         for (i = 0; i < 25; i++)
2091                 regp->CRTC[i] = NVReadVgaCrtc(pNv, nv_crtc->head, i);
2092
2093         NVSetEnablePalette(pNv, nv_crtc->head, true);
2094         for (i = 0; i < 21; i++)
2095                 regp->Attribute[i] = NVReadVgaAttr(pNv, nv_crtc->head, i);
2096         NVSetEnablePalette(pNv, nv_crtc->head, false);
2097
2098         for (i = 0; i < 9; i++)
2099                 regp->Graphics[i] = NVReadVgaGr(pNv, nv_crtc->head, i);
2100
2101         for (i = 0; i < 5; i++)
2102                 regp->Sequencer[i] = NVReadVgaSeq(pNv, nv_crtc->head, i);
2103 }
2104
2105 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2106 {
2107         ScrnInfoPtr pScrn = crtc->scrn;
2108         NVPtr pNv = NVPTR(pScrn);
2109         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2110         NVCrtcRegPtr regp;
2111         int i;
2112
2113         regp = &state->crtc_reg[nv_crtc->head];
2114
2115         regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LCD);
2116         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT0);
2117         regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT1);
2118         regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LSR);
2119         regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_PIXEL);
2120         regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_HEB);
2121         regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO1);
2122
2123         regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO0);
2124         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO_LWM);
2125         regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_BUFFER);
2126         if (pNv->Architecture >= NV_ARCH_30)
2127                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO_LWM_NV30);
2128         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL0);
2129         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL1);
2130         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL2);
2131         regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_INTERLACE);
2132
2133         if (pNv->Architecture >= NV_ARCH_10) {
2134                 regp->unk830 = NVCrtcReadCRTC(crtc, NV_CRTC_0830);
2135                 regp->unk834 = NVCrtcReadCRTC(crtc, NV_CRTC_0834);
2136                 if (pNv->Architecture == NV_ARCH_40) {
2137                         regp->unk850 = NVCrtcReadCRTC(crtc, NV_CRTC_0850);
2138                         regp->gpio_ext = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO_EXT);
2139                 }
2140                 if (pNv->twoHeads) {
2141                         regp->head = NVCrtcReadCRTC(crtc, NV_CRTC_FSEL);
2142                         regp->crtcOwner = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_OWNER);
2143                 }
2144                 regp->cursorConfig = NVCrtcReadCRTC(crtc, NV_CRTC_CURSOR_CONFIG);
2145         }
2146
2147         regp->gpio = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO);
2148         regp->config = NVCrtcReadCRTC(crtc, NV_CRTC_CONFIG);
2149
2150         regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_26);
2151         regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_3B);
2152         regp->CRTC[NV_VGA_CRTCX_SCRATCH4] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_SCRATCH4);
2153         if (pNv->Architecture >= NV_ARCH_10) {
2154                 regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_EXTRA);
2155                 regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_45);
2156                 regp->CRTC[NV_VGA_CRTCX_4B] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_4B);
2157                 regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_52);
2158         }
2159         /* NV11 and NV20 don't have this, they stop at 0x52. */
2160         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
2161                 for (i = 0; i < 0x10; i++)
2162                         regp->CR58[i] = NVReadVgaCrtc5758(pNv, nv_crtc->head, i);
2163
2164                 regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_59);
2165                 regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FP_HTIMING);
2166                 regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FP_VTIMING);
2167
2168                 regp->CRTC[NV_VGA_CRTCX_85] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_85);
2169                 regp->CRTC[NV_VGA_CRTCX_86] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_86);
2170         }
2171 }
2172
2173 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2174 {
2175         ScrnInfoPtr pScrn = crtc->scrn;
2176         NVPtr pNv = NVPTR(pScrn);
2177         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2178         NVCrtcRegPtr regp;
2179         int i;
2180
2181         regp = &state->crtc_reg[nv_crtc->head];
2182
2183         regp->general = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL);
2184
2185         regp->fp_control[0]     = NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL);
2186         regp->debug_0[0]        = NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
2187
2188         if (pNv->twoHeads) {
2189                 regp->fp_control[1]     = NVReadRAMDAC(pNv, 1, NV_RAMDAC_FP_CONTROL);
2190                 regp->debug_0[1]        = NVReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
2191
2192                 regp->debug_1   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1);
2193                 regp->debug_2   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2);
2194
2195                 regp->unk_a20 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A20);
2196                 regp->unk_a24 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A24);
2197                 regp->unk_a34 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A34);
2198         }
2199
2200         if (pNv->NVArch == 0x11) {
2201                 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_DITHER_NV11);
2202         } else if (pNv->twoHeads) {
2203                 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DITHER);
2204                 for (i = 0; i < 3; i++) {
2205                         regp->dither_regs[i] = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_850 + i * 4);
2206                         regp->dither_regs[i + 3] = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_85C + i * 4);
2207                 }
2208         }
2209         if (pNv->Architecture >= NV_ARCH_10)
2210                 regp->nv10_cursync = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC);
2211
2212         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2213
2214         for (i = 0; i < 7; i++) {
2215                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2216                 regp->fp_horiz_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
2217         }
2218
2219         for (i = 0; i < 7; i++) {
2220                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2221                 regp->fp_vert_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
2222         }
2223
2224         regp->fp_hvalid_start = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_HVALID_START);
2225         regp->fp_hvalid_end = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_HVALID_END);
2226         regp->fp_vvalid_start = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_VVALID_START);
2227         regp->fp_vvalid_end = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_VVALID_END);
2228 }
2229
2230 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2231 {
2232         ScrnInfoPtr pScrn = crtc->scrn;
2233         NVPtr pNv = NVPTR(pScrn);
2234         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2235         NVCrtcRegPtr regp;
2236         int i;
2237
2238         regp = &state->crtc_reg[nv_crtc->head];
2239
2240         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL, regp->general);
2241
2242         if (pNv->fp_regs_owner[0] == nv_crtc->head) {
2243                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL, regp->fp_control[0]);
2244                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0, regp->debug_0[0]);
2245         }
2246         if (pNv->twoHeads) {
2247                 if (pNv->fp_regs_owner[1] == nv_crtc->head) {
2248                         NVWriteRAMDAC(pNv, 1, NV_RAMDAC_FP_CONTROL, regp->fp_control[1]);
2249                         NVWriteRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0, regp->debug_0[1]);
2250                 }
2251                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
2252                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
2253                 if (pNv->NVArch == 0x30) { /* For unknown purposes. */
2254                         uint32_t reg890 = NVCrtcReadRAMDAC(crtc, NV30_RAMDAC_890);
2255                         NVCrtcWriteRAMDAC(crtc, NV30_RAMDAC_89C, reg890);
2256                 }
2257
2258                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A20, regp->unk_a20);
2259                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A24, regp->unk_a24);
2260                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A34, regp->unk_a34);
2261         }
2262
2263         if (pNv->NVArch == 0x11) {
2264                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_DITHER_NV11, regp->dither);
2265         } else if (pNv->twoHeads) {
2266                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DITHER, regp->dither);
2267                 for (i = 0; i < 3; i++) {
2268                         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_850 + i * 4, regp->dither_regs[i]);
2269                         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_85C + i * 4, regp->dither_regs[i + 3]);
2270                 }
2271         }
2272         if (pNv->Architecture >= NV_ARCH_10)
2273                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
2274
2275         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2276
2277         for (i = 0; i < 7; i++) {
2278                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2279                 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_horiz_regs[i]);
2280         }
2281
2282         for (i = 0; i < 7; i++) {
2283                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2284                 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_vert_regs[i]);
2285         }
2286
2287         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_HVALID_START, regp->fp_hvalid_start);
2288         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_HVALID_END, regp->fp_hvalid_end);
2289         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_VVALID_START, regp->fp_vvalid_start);
2290         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_VVALID_END, regp->fp_vvalid_end);
2291 }
2292
2293 void
2294 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y, Bool bios_restore)
2295 {
2296         ScrnInfoPtr pScrn = crtc->scrn;
2297         NVPtr pNv = NVPTR(pScrn);
2298         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2299         uint32_t start = 0;
2300
2301         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NVCrtcSetBase is called with coordinates: x: %d y: %d\n", x, y);
2302
2303         if (bios_restore) {
2304                 start = pNv->console_mode[nv_crtc->head].fb_start;
2305         } else {
2306                 start += ((y * pScrn->displayWidth + x) * (pScrn->bitsPerPixel/8));
2307                 if (crtc->rotatedData != NULL) { /* we do not exist on the real framebuffer */
2308 #if NOUVEAU_EXA_PIXMAPS
2309                         start = nv_crtc->shadow->offset;
2310 #else
2311                         start = pNv->FB->offset + nv_crtc->shadow->offset; /* We do exist relative to the framebuffer */
2312 #endif
2313                 } else {
2314                         start += pNv->FB->offset;
2315                 }
2316         }
2317
2318         /* 30 bits addresses in 32 bits according to haiku */
2319         NVCrtcWriteCRTC(crtc, NV_CRTC_START, start & 0xfffffffc);
2320
2321         /* set NV4/NV10 byte adress: (bit0 - 1) */
2322         NVWriteVgaAttr(pNv, nv_crtc->head, 0x13, (start & 0x3) << 1);
2323
2324         crtc->x = x;
2325         crtc->y = y;
2326 }
2327
2328 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2329 {
2330         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2331         NVPtr pNv = NVPTR(crtc->scrn);
2332         uint32_t mmiobase = nv_crtc->head ? NV_PDIO1_OFFSET : NV_PDIO0_OFFSET;
2333         int i;
2334
2335         VGA_WR08(pNv->REGS, VGA_DAC_MASK + mmiobase, 0xff);
2336         VGA_WR08(pNv->REGS, VGA_DAC_READ_ADDR + mmiobase, 0x0);
2337
2338         for (i = 0; i < 768; i++) {
2339                 state->crtc_reg[nv_crtc->head].DAC[i] = NV_RD08(pNv->REGS, VGA_DAC_DATA + mmiobase);
2340                 DDXMMIOH("nv_crtc_save_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_DATA + mmiobase, state->crtc_reg[nv_crtc->head].DAC[i]);
2341         }
2342
2343         NVSetEnablePalette(pNv, nv_crtc->head, false);
2344 }
2345 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2346 {
2347         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2348         NVPtr pNv = NVPTR(crtc->scrn);
2349         uint32_t mmiobase = nv_crtc->head ? NV_PDIO1_OFFSET : NV_PDIO0_OFFSET;
2350         int i;
2351
2352         VGA_WR08(pNv->REGS, VGA_DAC_MASK + mmiobase, 0xff);
2353         VGA_WR08(pNv->REGS, VGA_DAC_WRITE_ADDR + mmiobase, 0x0);
2354
2355         for (i = 0; i < 768; i++) {
2356                 DDXMMIOH("nv_crtc_load_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_DATA + mmiobase, state->crtc_reg[nv_crtc->head].DAC[i]);
2357                 NV_WR08(pNv->REGS, VGA_DAC_DATA + mmiobase, state->crtc_reg[nv_crtc->head].DAC[i]);
2358         }
2359
2360         NVSetEnablePalette(pNv, nv_crtc->head, false);
2361 }
2362
2363 /*************************************************************************** \
2364 |*                                                                           *|
2365 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
2366 |*                                                                           *|
2367 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
2368 |*     international laws.  Users and possessors of this source code are     *|
2369 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
2370 |*     use this code in individual and commercial software.                  *|
2371 |*                                                                           *|
2372 |*     Any use of this source code must include,  in the user documenta-     *|
2373 |*     tion and  internal comments to the code,  notices to the end user     *|
2374 |*     as follows:                                                           *|
2375 |*                                                                           *|
2376 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
2377 |*                                                                           *|
2378 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
2379 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
2380 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
2381 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
2382 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
2383 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
2384 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
2385 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
2386 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
2387 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
2388 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
2389 |*                                                                           *|
2390 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
2391 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
2392 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
2393 |*     computer  software  documentation,"  as such  terms  are  used in     *|
2394 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
2395 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
2396 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
2397 |*     all U.S. Government End Users  acquire the source code  with only     *|
2398 |*     those rights set forth herein.                                        *|
2399 |*                                                                           *|
2400  \***************************************************************************/