git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 2006 Dave Airlie
   3  * Copyright 2007 Maarten Maathuis
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
  26  * decleration is at the bottom of this file as it is rather ugly
  27  */
  28
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include <assert.h>
  34 #include "xf86.h"
  35 #include "os.h"
  36 #include "mibank.h"
  37 #include "globals.h"
  38 #include "xf86.h"
  39 #include "xf86Priv.h"
  40 #include "xf86DDC.h"
  41 #include "mipointer.h"
  42 #include "windowstr.h"
  43 #include <randrstr.h>
  44 #include <X11/extensions/render.h>
  45
  46 #include "xf86Crtc.h"
  47 #include "nv_include.h"
  48
  49 #include "vgaHW.h"
  50
  51 #define CRTC_INDEX 0x3d4
  52 #define CRTC_DATA 0x3d5
  53 #define CRTC_IN_STAT_1 0x3da
  54
  55 #define WHITE_VALUE 0x3F
  56 #define BLACK_VALUE 0x00
  57 #define OVERSCAN_VALUE 0x01
  58
  59 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  60 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override);
  61 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  62 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  63 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  64 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  65 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  66 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  67
  68 uint32_t NVReadCRTC(NVPtr pNv, uint8_t head, uint32_t reg)
  69 {
  70         volatile const void *ptr = head ? pNv->PCRTC1 : pNv->PCRTC0;
  71         DDXMMIOH("NVReadCRTC: head %d reg %08x val %08x\n", head, reg + NV_PCRTC0_OFFSET + (head ? NV_PCRTC0_SIZE : 0), (uint32_t)MMIO_IN32(ptr, reg));
  72         return MMIO_IN32(ptr, reg);
  73 }
  74
  75 void NVWriteCRTC(NVPtr pNv, uint8_t head, uint32_t reg, uint32_t val)
  76 {
  77         volatile const void *ptr = head ? pNv->PCRTC1 : pNv->PCRTC0;
  78         DDXMMIOH("NVWriteCRTC: head %d reg %08x val %08x\n", head, reg + NV_PCRTC0_OFFSET + (head ? NV_PCRTC0_SIZE : 0), val);
  79         MMIO_OUT32(ptr, reg, val);
  80 }
  81
  82 uint32_t NVCrtcReadCRTC(xf86CrtcPtr crtc, uint32_t reg)
  83 {
  84         ScrnInfoPtr pScrn = crtc->scrn;
  85         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  86         NVPtr pNv = NVPTR(pScrn);
  87
  88         return NVReadCRTC(pNv, nv_crtc->head, reg);
  89 }
  90
  91 void NVCrtcWriteCRTC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
  92 {
  93         ScrnInfoPtr pScrn = crtc->scrn;
  94         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  95         NVPtr pNv = NVPTR(pScrn);
  96
  97         NVWriteCRTC(pNv, nv_crtc->head, reg, val);
  98 }
  99
 100 uint32_t NVReadRAMDAC(NVPtr pNv, uint8_t head, uint32_t reg)
 101 {
 102         volatile const void *ptr = head ? pNv->PRAMDAC1 : pNv->PRAMDAC0;
 103         DDXMMIOH("NVReadRamdac: head %d reg %08x val %08x\n", head, reg + NV_PRAMDAC0_OFFSET + (head ? NV_PRAMDAC0_SIZE : 0), (uint32_t)MMIO_IN32(ptr, reg));
 104         return MMIO_IN32(ptr, reg);
 105 }
 106
 107 void NVWriteRAMDAC(NVPtr pNv, uint8_t head, uint32_t reg, uint32_t val)
 108 {
 109         volatile const void *ptr = head ? pNv->PRAMDAC1 : pNv->PRAMDAC0;
 110         DDXMMIOH("NVWriteRamdac: head %d reg %08x val %08x\n", head, reg + NV_PRAMDAC0_OFFSET + (head ? NV_PRAMDAC0_SIZE : 0), val);
 111         MMIO_OUT32(ptr, reg, val);
 112 }
 113
 114 uint32_t NVCrtcReadRAMDAC(xf86CrtcPtr crtc, uint32_t reg)
 115 {
 116         ScrnInfoPtr pScrn = crtc->scrn;
 117         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 118         NVPtr pNv = NVPTR(pScrn);
 119
 120         return NVReadRAMDAC(pNv, nv_crtc->head, reg);
 121 }
 122
 123 void NVCrtcWriteRAMDAC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
 124 {
 125         ScrnInfoPtr pScrn = crtc->scrn;
 126         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 127         NVPtr pNv = NVPTR(pScrn);
 128
 129         NVWriteRAMDAC(pNv, nv_crtc->head, reg, val);
 130 }
 131
 132 static uint8_t NVReadPVIO(xf86CrtcPtr crtc, uint32_t address)
 133 {
 134         ScrnInfoPtr pScrn = crtc->scrn;
 135         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 136         NVPtr pNv = NVPTR(pScrn);
 137
 138         /* Only NV4x have two pvio ranges */
 139         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
 140                 DDXMMIOH("NVReadPVIO: head %d reg %08x val %02x\n", 1, address + NV_PVIO_OFFSET + NV_PVIO_SIZE, NV_RD08(pNv->PVIO1, address));
 141                 return NV_RD08(pNv->PVIO1, address);
 142         } else {
 143                 DDXMMIOH("NVReadPVIO: head %d reg %08x val %02x\n", 0, address + NV_PVIO_OFFSET, NV_RD08(pNv->PVIO0, address));
 144                 return NV_RD08(pNv->PVIO0, address);
 145         }
 146 }
 147
 148 static void NVWritePVIO(xf86CrtcPtr crtc, uint32_t address, uint8_t value)
 149 {
 150         ScrnInfoPtr pScrn = crtc->scrn;
 151         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 152         NVPtr pNv = NVPTR(pScrn);
 153
 154         DDXMMIOH("NVWritePVIO: head %d reg %08x val %02x\n", nv_crtc->head, address + NV_PVIO_OFFSET + (nv_crtc->head ? NV_PVIO_SIZE : 0), value);
 155         /* Only NV4x have two pvio ranges */
 156         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
 157                 NV_WR08(pNv->PVIO1, address, value);
 158         } else {
 159                 NV_WR08(pNv->PVIO0, address, value);
 160         }
 161 }
 162
 163 void NVWriteVGA(NVPtr pNv, int head, uint8_t index, uint8_t value)
 164 {
 165         volatile uint8_t *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 166
 167         DDXMMIOH("NVWriteVGA: head %d index 0x%02x data 0x%02x\n", head, index, value);
 168         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 169         NV_WR08(pCRTCReg, CRTC_DATA, value);
 170 }
 171
 172 uint8_t NVReadVGA(NVPtr pNv, int head, uint8_t index)
 173 {
 174         volatile uint8_t *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 175
 176         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 177         DDXMMIOH("NVReadVGA: head %d index 0x%02x data 0x%02x\n", head, index, NV_RD08(pCRTCReg, CRTC_DATA));
 178         return NV_RD08(pCRTCReg, CRTC_DATA);
 179 }
 180
 181 /* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
 182  * I suspect they in fact do nothing, but are merely a way to carry useful
 183  * per-head variables around
 184  *
 185  * Known uses:
 186  * CR57         CR58
 187  * 0x00         index to the appropriate dcb entry (or 7f for inactive)
 188  * 0x02         dcb entry's "or" value (or 00 for inactive)
 189  * 0x03         bit0 set for dual link (LVDS, possibly elsewhere too)
 190  * 0x08 or 0x09 pxclk in MHz
 191  * 0x0f         laptop panel info -     low nibble for PEXTDEV_BOOT strap
 192  *                                      high nibble for xlat strap value
 193  */
 194
 195 void NVWriteVGACR5758(NVPtr pNv, int head, uint8_t index, uint8_t value)
 196 {
 197         NVWriteVGA(pNv, head, 0x57, index);
 198         NVWriteVGA(pNv, head, 0x58, value);
 199 }
 200
 201 uint8_t NVReadVGACR5758(NVPtr pNv, int head, uint8_t index)
 202 {
 203         NVWriteVGA(pNv, head, 0x57, index);
 204         return NVReadVGA(pNv, head, 0x58);
 205 }
 206
 207 void NVWriteVgaCrtc(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 208 {
 209         ScrnInfoPtr pScrn = crtc->scrn;
 210         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 211         NVPtr pNv = NVPTR(pScrn);
 212
 213         NVWriteVGA(pNv, nv_crtc->head, index, value);
 214 }
 215
 216 uint8_t NVReadVgaCrtc(xf86CrtcPtr crtc, uint8_t index)
 217 {
 218         ScrnInfoPtr pScrn = crtc->scrn;
 219         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 220         NVPtr pNv = NVPTR(pScrn);
 221
 222         return NVReadVGA(pNv, nv_crtc->head, index);
 223 }
 224
 225 static void NVWriteVgaSeq(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 226 {
 227         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 228         NVWritePVIO(crtc, VGA_SEQ_DATA, value);
 229 }
 230
 231 static uint8_t NVReadVgaSeq(xf86CrtcPtr crtc, uint8_t index)
 232 {
 233         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 234         return NVReadPVIO(crtc, VGA_SEQ_DATA);
 235 }
 236
 237 static void NVWriteVgaGr(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 238 {
 239         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 240         NVWritePVIO(crtc, VGA_GRAPH_DATA, value);
 241 }
 242
 243 static uint8_t NVReadVgaGr(xf86CrtcPtr crtc, uint8_t index)
 244 {
 245         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 246         return NVReadPVIO(crtc, VGA_GRAPH_DATA);
 247 }
 248
 249
 250 static void NVWriteVgaAttr(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 251 {
 252         ScrnInfoPtr pScrn = crtc->scrn;
 253         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 254         NVPtr pNv = NVPTR(pScrn);
 255         volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 256
 257         DDXMMIOH("NVWriteVgaAttr: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, CRTC_IN_STAT_1, NV_RD08(pCRTCReg, CRTC_IN_STAT_1));
 258         NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 259         if (nv_crtc->paletteEnabled)
 260                 index &= ~0x20;
 261         else
 262                 index |= 0x20;
 263
 264         DDXMMIOH("NVWriteVgaAttr: head %d index 0x%02x data 0x%02x\n", nv_crtc->head, index, value);
 265         NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 266         NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
 267 }
 268
 269 static uint8_t NVReadVgaAttr(xf86CrtcPtr crtc, uint8_t index)
 270 {
 271         ScrnInfoPtr pScrn = crtc->scrn;
 272         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 273         NVPtr pNv = NVPTR(pScrn);
 274         volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 275
 276         DDXMMIOH("NVReadVgaAttr: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, CRTC_IN_STAT_1, NV_RD08(pCRTCReg, CRTC_IN_STAT_1));
 277         NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 278         if (nv_crtc->paletteEnabled)
 279                 index &= ~0x20;
 280         else
 281                 index |= 0x20;
 282
 283         NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 284         DDXMMIOH("NVReadVgaAttr: head %d index 0x%02x data 0x%02x\n", nv_crtc->head, index, NV_RD08(pCRTCReg, VGA_ATTR_DATA_R));
 285         return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
 286 }
 287
 288 static void NVCrtcSetOwner(xf86CrtcPtr crtc)
 289 {
 290         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 291         ScrnInfoPtr pScrn = crtc->scrn;
 292         NVPtr pNv = NVPTR(pScrn);
 293         /* Non standard beheaviour required by NV11 */
 294         if (pNv) {
 295                 uint8_t owner = NVReadVGA(pNv, 0, NV_VGA_CRTCX_OWNER);
 296                 ErrorF("pre-Owner: 0x%X\n", owner);
 297                 if (owner == 0x04) {
 298                         uint32_t pbus84 = nvReadMC(pNv, 0x1084);
 299                         ErrorF("pbus84: 0x%X\n", pbus84);
 300                         pbus84 &= ~(1<<28);
 301                         ErrorF("pbus84: 0x%X\n", pbus84);
 302                         nvWriteMC(pNv, 0x1084, pbus84);
 303                 }
 304                 /* The blob never writes owner to pcio1, so should we */
 305                 if (pNv->NVArch == 0x11) {
 306                         NVWriteVGA(pNv, 0, NV_VGA_CRTCX_OWNER, 0xff);
 307                 }
 308                 NVWriteVGA(pNv, 0, NV_VGA_CRTCX_OWNER, nv_crtc->head * 0x3);
 309                 owner = NVReadVGA(pNv, 0, NV_VGA_CRTCX_OWNER);
 310                 ErrorF("post-Owner: 0x%X\n", owner);
 311         } else {
 312                 ErrorF("pNv pointer is NULL\n");
 313         }
 314 }
 315
 316 static void
 317 NVEnablePalette(xf86CrtcPtr crtc)
 318 {
 319         ScrnInfoPtr pScrn = crtc->scrn;
 320         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 321         NVPtr pNv = NVPTR(pScrn);
 322         volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 323
 324         DDXMMIOH("NVEnablePalette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, CRTC_IN_STAT_1, NV_RD08(pCRTCReg, CRTC_IN_STAT_1));
 325         NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 326         DDXMMIOH("NVEnablePalette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_ATTR_INDEX, 0);
 327         NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
 328         nv_crtc->paletteEnabled = TRUE;
 329 }
 330
 331 static void
 332 NVDisablePalette(xf86CrtcPtr crtc)
 333 {
 334         ScrnInfoPtr pScrn = crtc->scrn;
 335         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 336         NVPtr pNv = NVPTR(pScrn);
 337         volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 338
 339         DDXMMIOH("NVDisablePalette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, NV_PCIO0_OFFSET + (nv_crtc->head ? NV_PCIO0_SIZE : 0) + CRTC_IN_STAT_1, NV_RD08(pCRTCReg, CRTC_IN_STAT_1));
 340         NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 341         DDXMMIOH("NVDisablePalette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, NV_PCIO0_OFFSET + (nv_crtc->head ? NV_PCIO0_SIZE : 0) + VGA_ATTR_INDEX, 0x20);
 342         NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
 343         nv_crtc->paletteEnabled = FALSE;
 344 }
 345
 346 /* perform a sequencer reset */
 347 static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
 348 {
 349   if (start)
 350     NVWriteVgaSeq(crtc, 0x00, 0x1);
 351   else
 352     NVWriteVgaSeq(crtc, 0x00, 0x3);
 353
 354 }
 355 static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
 356 {
 357         uint8_t tmp;
 358
 359         if (on) {
 360                 tmp = NVReadVgaSeq(crtc, 0x1);
 361                 NVVgaSeqReset(crtc, TRUE);
 362                 NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
 363
 364                 NVEnablePalette(crtc);
 365         } else {
 366                 /*
 367                  * Reenable sequencer, then turn on screen.
 368                  */
 369                 tmp = NVReadVgaSeq(crtc, 0x1);
 370                 NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20); /* reenable display */
 371                 NVVgaSeqReset(crtc, FALSE);
 372
 373                 NVDisablePalette(crtc);
 374         }
 375 }
 376
 377 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool Lock)
 378 {
 379         NVPtr pNv = NVPTR(crtc->scrn);
 380         uint8_t cr11;
 381
 382         if (pNv->twoHeads)
 383                 NVCrtcSetOwner(crtc);
 384
 385         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57);
 386         cr11 = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE);
 387         if (Lock) cr11 |= 0x80;
 388         else cr11 &= ~0x80;
 389         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE, cr11);
 390 }
 391
 392 xf86OutputPtr
 393 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
 394 {
 395         ScrnInfoPtr pScrn = crtc->scrn;
 396         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 397         int i;
 398         for (i = 0; i < xf86_config->num_output; i++) {
 399                 xf86OutputPtr output = xf86_config->output[i];
 400
 401                 if (output->crtc == crtc) {
 402                         return output;
 403                 }
 404         }
 405
 406         return NULL;
 407 }
 408
 409 xf86CrtcPtr
 410 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
 411 {
 412         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 413         int i;
 414
 415         for (i = 0; i < xf86_config->num_crtc; i++) {
 416                 xf86CrtcPtr crtc = xf86_config->crtc[i];
 417                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 418                 if (nv_crtc->head == index)
 419                         return crtc;
 420         }
 421
 422         return NULL;
 423 }
 424
 425 /*
 426  * Calculate the Video Clock parameters for the PLL.
 427  */
 428 /* Code taken from NVClock, with permission of the author (being a GPL->MIT code transfer). */
 429
 430 static void
 431 CalculateVClkNV4x_SingleVCO(NVPtr pNv, struct pll_lims *pll_lim, uint32_t clockIn, uint32_t *n1_best, uint32_t *m1_best, uint32_t *p_best)
 432 {
 433         uint32_t clock, M, N, P;
 434         uint32_t delta, bestDelta, minM, maxM, minN, maxN, maxP;
 435         uint32_t minVCOInputFreq, minVCOFreq, maxVCOFreq;
 436         uint32_t VCOFreq;
 437         uint32_t refClk = pNv->CrystalFreqKHz;
 438         bestDelta = clockIn;
 439
 440         minVCOInputFreq = pll_lim->vco1.min_inputfreq;
 441         minVCOFreq = pll_lim->vco1.minfreq;
 442         maxVCOFreq = pll_lim->vco1.maxfreq;
 443         minM = pll_lim->vco1.min_m;
 444         maxM = pll_lim->vco1.max_m;
 445         minN = pll_lim->vco1.min_n;
 446         maxN = pll_lim->vco1.max_n;
 447
 448         maxP = 6;
 449
 450         /* The optimal frequency for the PLL to work at is somewhere in the center of its range.
 451         /  Choose a post divider in such a way to achieve this.
 452         /  The G8x nv driver does something similar but they they derive a minP and maxP. That
 453         /  doesn't seem required as you get so many matching clocks that you don't enter a second
 454         /  iteration for P. (The minP / maxP values in the nv driver only differ at most 1, so it is for
 455         /  some rare corner cases.
 456         */
 457         for (P=0, VCOFreq=maxVCOFreq/2; clockIn<=VCOFreq && P <= maxP; P++)
 458         {
 459                 VCOFreq /= 2;
 460         }
 461
 462         /* Calculate the m and n values. There are a lot of values which give the same speed;
 463         /  We choose the speed for which the difference with the request speed is as small as possible.
 464         */
 465         for (M=minM; M<=maxM; M++)
 466         {
 467                 /* The VCO has a minimum input frequency */
 468                 if ((refClk/M) < minVCOInputFreq)
 469                         break;
 470
 471                 for (N=minN; N<=maxN; N++)
 472                 {
 473                         /* Calculate the frequency generated by VCO1 */
 474                         clock = (int)(refClk * N / (float)M);
 475
 476                         /* Verify if the clock lies within the output limits of VCO1 */
 477                         if (clock < minVCOFreq)
 478                                 continue;
 479                         else if (clock > maxVCOFreq) /* It is no use to continue as the clock will only become higher */
 480                                 break;
 481
 482                         clock >>= P;
 483                         delta = abs((int)(clockIn - clock));
 484                         /* When the difference is 0 or less than .5% accept the speed */
 485                         if (((delta == 0) || ((float)delta/(float)clockIn <= 0.005)))
 486                         {
 487                                 *m1_best = M;
 488                                 *n1_best = N;
 489                                 *p_best = P;
 490                                 return;
 491                         }
 492
 493                         /* When the new difference is smaller than the old one, use this one */
 494                         if (delta < bestDelta)
 495                         {
 496                                 bestDelta = delta;
 497                                 *m1_best = M;
 498                                 *n1_best = N;
 499                                 *p_best = P;
 500                         }
 501                 }
 502         }
 503 }
 504
 505 static void
 506 CalculateVClkNV4x_DoubleVCO(NVPtr pNv, struct pll_lims *pll_lim, uint32_t clockIn, uint32_t *n1_best, uint32_t *n2_best, uint32_t *m1_best, uint32_t *m2_best, uint32_t *p_best)
 507 {
 508         uint32_t clock1, clock2, M, M2, N, N2, P;
 509         uint32_t delta, bestDelta, minM, minM2, maxM, maxM2, minN, minN2, maxN, maxN2, maxP;
 510         uint32_t minVCOInputFreq, minVCO2InputFreq, maxVCO2InputFreq, minVCOFreq, minVCO2Freq, maxVCOFreq, maxVCO2Freq;
 511         uint32_t VCO2Freq, maxClock;
 512         uint32_t refClk = pNv->CrystalFreqKHz;
 513         bestDelta = clockIn;
 514
 515         minVCOInputFreq = pll_lim->vco1.min_inputfreq;
 516         minVCOFreq = pll_lim->vco1.minfreq;
 517         maxVCOFreq = pll_lim->vco1.maxfreq;
 518         minM = pll_lim->vco1.min_m;
 519         maxM = pll_lim->vco1.max_m;
 520         minN = pll_lim->vco1.min_n;
 521         maxN = pll_lim->vco1.max_n;
 522
 523         minVCO2InputFreq = pll_lim->vco2.min_inputfreq;
 524         maxVCO2InputFreq = pll_lim->vco2.max_inputfreq;
 525         minVCO2Freq = pll_lim->vco2.minfreq;
 526         maxVCO2Freq = pll_lim->vco2.maxfreq;
 527         minM2 = pll_lim->vco2.min_m;
 528         maxM2 = pll_lim->vco2.max_m;
 529         minN2 = pll_lim->vco2.min_n;
 530         maxN2 = pll_lim->vco2.max_n;
 531
 532         maxP = 6;
 533
 534         maxClock = maxVCO2Freq;
 535         /* If the requested clock is behind the bios limits, try it anyway */
 536         if (clockIn > maxVCO2Freq)
 537                 maxClock = clockIn + clockIn/200; /* Add a .5% margin */
 538
 539         /* The optimal frequency for the PLL to work at is somewhere in the center of its range.
 540         /  Choose a post divider in such a way to achieve this.
 541         /  The G8x nv driver does something similar but they they derive a minP and maxP. That
 542         /  doesn't seem required as you get so many matching clocks that you don't enter a second
 543         /  iteration for P. (The minP / maxP values in the nv driver only differ at most 1, so it is for
 544         /  some rare corner cases.
 545         */
 546         for (P=0, VCO2Freq=maxClock/2; clockIn<=VCO2Freq && P <= maxP; P++)
 547         {
 548                 VCO2Freq /= 2;
 549         }
 550
 551         /* The PLLs on Geforce6/7 hardware can operate in a single stage made with only 1 VCO
 552         /  and a cascade mode of two VCOs. This second mode is in general used for relatively high
 553         /  frequencies. The loop below calculates the divider and multiplier ratios for the cascade
 554         /  mode. The code takes into account limits defined in the video bios.
 555         */
 556         for (M=minM; M<=maxM; M++)
 557         {
 558                 /* The VCO has a minimum input frequency */
 559                 if ((refClk/M) < minVCOInputFreq)
 560                         break;
 561
 562                 for (N=minN; N<=maxN; N++)
 563                 {
 564                         /* Calculate the frequency generated by VCO1 */
 565                         clock1 = (int)(refClk * N / (float)M);
 566                         /* Verify if the clock lies within the output limits of VCO1 */
 567                         if ( (clock1 < minVCOFreq) )
 568                                 continue;
 569                         else if (clock1 > maxVCOFreq) /* For future N, the clock will only increase so stop; xorg nv continues but that is useless */
 570                                 break;
 571
 572                         for (M2=minM2; M2<=maxM2; M2++)
 573                         {
 574                                 /* The clock fed to the second VCO needs to lie within a certain input range */
 575                                 if (clock1 / M2 < minVCO2InputFreq)
 576                                         break;
 577                                 else if (clock1 / M2 > maxVCO2InputFreq)
 578                                         continue;
 579
 580                                 N2 = (int)((float)((clockIn << P) * M * M2) / (float)(refClk * N)+.5);
 581                                 if( (N2 < minN2) || (N2 > maxN2) )
 582                                         continue;
 583
 584                                 /* The clock before being fed to the post-divider needs to lie within a certain range.
 585                                 /  Further there are some limits on N2/M2.
 586                                 */
 587                                 clock2 = (int)((float)(N*N2)/(M*M2) * refClk);
 588                                 if( (clock2 < minVCO2Freq) || (clock2 > maxClock))// || ((N2 / M2) < 4) || ((N2 / M2) > 10) )
 589                                         continue;
 590
 591                                 /* The post-divider delays the 'high' clock to create a low clock if requested.
 592                                 /  This post-divider exists because the VCOs can only generate frequencies within
 593                                 /  a limited frequency range. This range has been tuned to lie around half of its max
 594                                 /  input frequency. It tries to calculate all clocks (including lower ones) around this
 595                                 /  'center' frequency.
 596                                 */
 597                                 clock2 >>= P;
 598                                 delta = abs((int)(clockIn - clock2));
 599
 600                                 /* When the difference is 0 or less than .5% accept the speed */
 601                                 if (((delta == 0) || ((float)delta/(float)clockIn <= 0.005)))
 602                                 {
 603                                         *m1_best = M;
 604                                         *m2_best = M2;
 605                                         *n1_best = N;
 606                                         *n2_best = N2;
 607                                         *p_best = P;
 608                                         return;
 609                                 }
 610
 611                                 /* When the new difference is smaller than the old one, use this one */
 612                                 if (delta < bestDelta)
 613                                 {
 614                                         bestDelta = delta;
 615                                         *m1_best = M;
 616                                         *m2_best = M2;
 617                                         *n1_best = N;
 618                                         *n2_best = N2;
 619                                         *p_best = P;
 620                                 }
 621                         }
 622                 }
 623         }
 624 }
 625
 626 /* BIG NOTE: modifying vpll1 and vpll2 does not work, what bit is the switch to allow it? */
 627
 628 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
 629 /* They are only valid for NV4x, appearantly reordered for NV5x */
 630 /* gpu pll: 0x4000 + 0x4004
 631  * unknown pll: 0x4008 + 0x400c
 632  * vpll1: 0x4010 + 0x4014
 633  * vpll2: 0x4018 + 0x401c
 634  * unknown pll: 0x4020 + 0x4024
 635  * unknown pll: 0x4038 + 0x403c
 636  * Some of the unknown's are probably memory pll's.
 637  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
 638  * 1 and 2 refer to the registers of each pair. There is only one post divider.
 639  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
 640  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
 641  *     bit8: A switch that turns of the second divider and multiplier off.
 642  *     bit12: Also a switch, i haven't seen it yet.
 643  *     bit16-19: p-divider
 644  *     but 28-31: Something related to the mode that is used (see bit8).
 645  * 2) bit0-7: m-divider (a)
 646  *     bit8-15: n-multiplier (a)
 647  *     bit16-23: m-divider (b)
 648  *     bit24-31: n-multiplier (b)
 649  */
 650
 651 /* Modifying the gpu pll for example requires:
 652  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 653  * This is not needed for the vpll's which have their own bits.
 654  */
 655
 656 static void
 657 CalculateVClkNV4x(
 658         ScrnInfoPtr pScrn,
 659         uint32_t requested_clock,
 660         uint32_t *given_clock,
 661         uint32_t *pll_a,
 662         uint32_t *pll_b,
 663         uint32_t *reg580,
 664         Bool    *db1_ratio,
 665         Bool primary
 666 )
 667 {
 668         NVPtr pNv = NVPTR(pScrn);
 669         uint32_t pll_lim_reg;
 670         struct pll_lims pll_lim;
 671         /* We have 2 mulitpliers, 2 dividers and one post divider */
 672         /* Note that p is only 3 bits */
 673         int NM1 = 0xbeef, NM2 = 0xdead, log2P = 0;
 674         uint32_t special_bits = 0;
 675
 676         if (primary) {
 677                 if (!get_pll_limits_reg(pScrn, VPLL1, &pll_lim_reg))
 678                         return;
 679         } else
 680                 if (!get_pll_limits_reg(pScrn, VPLL2, &pll_lim_reg))
 681                         return;
 682
 683         get_pll_limits(pScrn, pll_lim_reg, &pll_lim);
 684
 685         if (requested_clock < pll_lim.vco1.maxfreq && pNv->NVArch > 0x40) { /* single VCO */
 686                 *db1_ratio = TRUE;
 687                 /* Turn the second set of divider and multiplier off */
 688                 /* Bogus data, the same nvidia uses */
 689                 NM2 = 0x11f;
 690                 *given_clock = getMNP_single(pScrn, pll_lim_reg, requested_clock, &NM1, &log2P);
 691         } else { /* dual VCO */
 692                 *db1_ratio = FALSE;
 693                 *given_clock = getMNP_double(pScrn, pll_lim_reg, requested_clock, &NM1, &NM2, &log2P);
 694         }
 695
 696         /* Are this all (relevant) G70 cards? */
 697         if (pNv->NVArch == 0x4B || pNv->NVArch == 0x46 || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
 698                 /* This is a big guess, but should be reasonable until we can narrow it down. */
 699                 if (*db1_ratio) {
 700                         special_bits = 0x1;
 701                 } else {
 702                         special_bits = 0x3;
 703                 }
 704         }
 705
 706         /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
 707         *pll_a = (special_bits << 30) | (log2P << 16) | NM1;
 708         /* This VCO2 bit is an educated guess, but it needs to stay on for NV4x. */
 709         *pll_b = NV31_RAMDAC_ENABLE_VCO2 | NM2;
 710
 711         if (*db1_ratio) {
 712                 if (primary) {
 713                         *reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 714                 } else {
 715                         *reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 716                 }
 717         } else {
 718                 if (primary) {
 719                         *reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
 720                 } else {
 721                         *reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
 722                 }
 723         }
 724
 725         if (*db1_ratio) {
 726                 ErrorF("vpll: n1 %d m1 %d p %d db1_ratio %d\n", NM1 >> 8, NM1 & 0xff, log2P, *db1_ratio);
 727         } else {
 728                 ErrorF("vpll: n1 %d n2 %d m1 %d m2 %d p %d db1_ratio %d\n", NM1 >> 8, NM2 >> 8, NM1 & 0xff, NM2 & 0xff, log2P, *db1_ratio);
 729         }
 730 }
 731
 732 static void nv40_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 733 {
 734         state->vpll1_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL);
 735         state->vpll1_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B);
 736         state->vpll2_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2);
 737         state->vpll2_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B);
 738         state->pllsel = NVReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT);
 739         state->sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
 740         state->reg580 = NVReadRAMDAC(pNv, 0, NV_RAMDAC_580);
 741         state->reg594 = NVReadRAMDAC(pNv, 0, NV_RAMDAC_594);
 742 }
 743
 744 static void nv40_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 745 {
 746         ScrnInfoPtr pScrn = crtc->scrn;
 747         NVPtr pNv = NVPTR(pScrn);
 748         uint32_t fp_debug_0[2];
 749         uint32_t index[2];
 750         fp_debug_0[0] = NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
 751         fp_debug_0[1] = NVReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
 752
 753         /* The TMDS_PLL switch is on the actual ramdac */
 754         if (state->crosswired) {
 755                 index[0] = 1;
 756                 index[1] = 0;
 757                 ErrorF("Crosswired pll state load\n");
 758         } else {
 759                 index[0] = 0;
 760                 index[1] = 1;
 761         }
 762
 763         if (state->vpll2_b && state->vpll_changed[1]) {
 764                 NVWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0,
 765                         fp_debug_0[index[1]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 766
 767                 /* Wait for the situation to stabilise */
 768                 usleep(5000);
 769
 770                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 771                 /* for vpll2 change bits 18 and 19 are disabled */
 772                 reg_c040 &= ~(0x3 << 18);
 773                 nvWriteMC(pNv, 0xc040, reg_c040);
 774
 775                 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 776                 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 777
 778                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2, state->vpll2_a);
 779                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 780
 781                 ErrorF("writing pllsel %08X\n", state->pllsel);
 782                 /* Don't turn vpll1 off. */
 783                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
 784
 785                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_580, state->reg580);
 786                 ErrorF("writing reg580 %08X\n", state->reg580);
 787
 788                 /* We need to wait a while */
 789                 usleep(5000);
 790                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 791
 792                 NVWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[1]]);
 793
 794                 /* Wait for the situation to stabilise */
 795                 usleep(5000);
 796         }
 797
 798         if (state->vpll1_b && state->vpll_changed[0]) {
 799                 NVWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0,
 800                         fp_debug_0[index[0]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 801
 802                 /* Wait for the situation to stabilise */
 803                 usleep(5000);
 804
 805                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 806                 /* for vpll2 change bits 16 and 17 are disabled */
 807                 reg_c040 &= ~(0x3 << 16);
 808                 nvWriteMC(pNv, 0xc040, reg_c040);
 809
 810                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 811                 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 812
 813                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL, state->vpll1_a);
 814                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B, state->vpll1_b);
 815
 816                 ErrorF("writing pllsel %08X\n", state->pllsel);
 817                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
 818
 819                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_580, state->reg580);
 820                 ErrorF("writing reg580 %08X\n", state->reg580);
 821
 822                 /* We need to wait a while */
 823                 usleep(5000);
 824                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 825
 826                 NVWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[0]]);
 827
 828                 /* Wait for the situation to stabilise */
 829                 usleep(5000);
 830         }
 831
 832         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 833         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, state->sel_clk);
 834
 835         ErrorF("writing reg594 %08X\n", state->reg594);
 836         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_594, state->reg594);
 837
 838         /* All clocks have been set at this point. */
 839         state->vpll_changed[0] = FALSE;
 840         state->vpll_changed[1] = FALSE;
 841 }
 842
 843 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 844 {
 845         state->vpll1_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL);
 846         if (pNv->twoHeads) {
 847                 state->vpll2_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2);
 848         }
 849         if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 850                 state->vpll1_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B);
 851                 state->vpll2_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B);
 852         }
 853         state->pllsel = NVReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT);
 854         state->sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
 855 }
 856
 857
 858 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 859 {
 860         /* This sequence is important, the NV28 is very sensitive in this area. */
 861         /* Keep pllsel last and sel_clk first. */
 862         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 863         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, state->sel_clk);
 864
 865         if (state->vpll2_a && state->vpll_changed[1]) {
 866                 if (pNv->twoHeads) {
 867                         ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 868                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2, state->vpll2_a);
 869                 }
 870                 if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 871                         ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 872                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 873                 }
 874         }
 875
 876         if (state->vpll1_a && state->vpll_changed[0]) {
 877                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 878                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL, state->vpll1_a);
 879                 if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 880                         ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 881                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B, state->vpll1_b);
 882                 }
 883         }
 884
 885         ErrorF("writing pllsel %08X\n", state->pllsel);
 886         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
 887
 888         /* All clocks have been set at this point. */
 889         state->vpll_changed[0] = FALSE;
 890         state->vpll_changed[1] = FALSE;
 891 }
 892
 893 /*
 894  * Calculate extended mode parameters (SVGA) and save in a
 895  * mode state structure.
 896  * State is not specific to a single crtc, but shared.
 897  */
 898 void nv_crtc_calc_state_ext(
 899         xf86CrtcPtr             crtc,
 900         DisplayModePtr  mode,
 901         int                             bpp,
 902         int                             DisplayWidth, /* Does this change after setting the mode? */
 903         int                             CrtcHDisplay,
 904         int                             CrtcVDisplay,
 905         int                             dotClock,
 906         int                             flags
 907 )
 908 {
 909         ScrnInfoPtr pScrn = crtc->scrn;
 910         uint32_t pixelDepth, VClk = 0;
 911         uint32_t CursorStart;
 912         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 913         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 914         NVCrtcRegPtr regp;
 915         NVPtr pNv = NVPTR(pScrn);
 916         RIVA_HW_STATE *state;
 917         int num_crtc_enabled, i;
 918         uint32_t old_clock_a = 0, old_clock_b = 0;
 919
 920         state = &pNv->ModeReg;
 921
 922         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 923
 924         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 925         NVOutputPrivatePtr nv_output = NULL;
 926         Bool is_fp = FALSE;
 927         if (output) {
 928                 nv_output = output->driver_private;
 929                 if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)
 930                         is_fp = TRUE;
 931         }
 932
 933         /* Store old clock. */
 934         if (nv_crtc->head == 1) {
 935                 old_clock_a = state->vpll2_a;
 936                 old_clock_b = state->vpll2_b;
 937         } else {
 938                 old_clock_a = state->vpll1_a;
 939                 old_clock_b = state->vpll1_b;
 940         }
 941
 942         /*
 943          * Extended RIVA registers.
 944          */
 945         /* This is pitch related, not mode related. */
 946         pixelDepth = (bpp + 1)/8;
 947         if (pNv->Architecture == NV_ARCH_40) {
 948                 /* Does register 0x580 already have a value? */
 949                 if (!state->reg580) {
 950                         state->reg580 = pNv->misc_info.ramdac_0_reg_580;
 951                 }
 952                 if (nv_crtc->head == 1) {
 953                         CalculateVClkNV4x(pScrn, dotClock, &VClk, &state->vpll2_a, &state->vpll2_b, &state->reg580, &state->db1_ratio[1], FALSE);
 954                 } else {
 955                         CalculateVClkNV4x(pScrn, dotClock, &VClk, &state->vpll1_a, &state->vpll1_b, &state->reg580, &state->db1_ratio[0], TRUE);
 956                 }
 957         } else if (pNv->twoStagePLL) {
 958                 int NM1, NM2, log2P;
 959                 VClk = getMNP_double(pScrn, 0, dotClock, &NM1, &NM2, &log2P);
 960                 if (pNv->NVArch == 0x30) {
 961                         /* See nvregisters.xml for details. */
 962                         state->pll = log2P << 16 | NM1 | (NM2 & 7) << 4 | ((NM2 >> 8) & 7) << 19 | ((NM2 >> 11) & 3) << 24 | NV30_RAMDAC_ENABLE_VCO2;
 963                 } else {
 964                         state->pll = log2P << 16 | NM1;
 965                         state->pllB = NV31_RAMDAC_ENABLE_VCO2 | NM2;
 966                 }
 967         } else {
 968                 int NM, log2P;
 969                 VClk = getMNP_single(pScrn, 0, dotClock, &NM, &log2P);
 970                 state->pll = log2P << 16 | NM;
 971         }
 972
 973         if (pNv->Architecture < NV_ARCH_40) {
 974                 if (nv_crtc->head == 1) {
 975                         state->vpll2_a = state->pll;
 976                         state->vpll2_b = state->pllB;
 977                 } else {
 978                         state->vpll1_a = state->pll;
 979                         state->vpll1_b = state->pllB;
 980                 }
 981         }
 982
 983         /* always reset vpll, just to be sure. */
 984         state->vpll_changed[nv_crtc->head] = TRUE;
 985
 986         switch (pNv->Architecture) {
 987         case NV_ARCH_04:
 988                 nv4UpdateArbitrationSettings(VClk,
 989                                                 pixelDepth * 8,
 990                                                 &(state->arbitration0),
 991                                                 &(state->arbitration1),
 992                                                 pNv);
 993                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
 994                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
 995                 if (flags & V_DBLSCAN)
 996                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 997                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
 998                 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
 999                 state->config = 0x00001114;
1000                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
1001                 break;
1002         case NV_ARCH_10:
1003         case NV_ARCH_20:
1004         case NV_ARCH_30:
1005         default:
1006                 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
1007                         ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
1008                         state->arbitration0 = 128;
1009                         state->arbitration1 = 0x0480;
1010                 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
1011                         ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
1012                         nForceUpdateArbitrationSettings(VClk,
1013                                                 pixelDepth * 8,
1014                                                 &(state->arbitration0),
1015                                                 &(state->arbitration1),
1016                                                 pNv);
1017                 } else if (pNv->Architecture < NV_ARCH_30) {
1018                         nv10UpdateArbitrationSettings(VClk,
1019                                                 pixelDepth * 8,
1020                                                 &(state->arbitration0),
1021                                                 &(state->arbitration1),
1022                                                 pNv);
1023                 } else {
1024                         nv30UpdateArbitrationSettings(pNv,
1025                                                 &(state->arbitration0),
1026                                                 &(state->arbitration1));
1027                 }
1028
1029                 if (nv_crtc->head == 1) {
1030                         CursorStart = pNv->Cursor2->offset;
1031                 } else {
1032                         CursorStart = pNv->Cursor->offset;
1033                 }
1034
1035                 if (!NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1036                         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
1037                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
1038                         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
1039                 } else {
1040                         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x0;
1041                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0x0;
1042                         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x0;
1043                 }
1044
1045                 if (flags & V_DBLSCAN)
1046                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
1047
1048                 state->config   = nvReadFB(pNv, NV_PFB_CFG0);
1049                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
1050                 break;
1051         }
1052
1053         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1054                 /* This is a bit of a guess. */
1055                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] |= 0xB8;
1056         }
1057
1058         /* okay do we have 2 CRTCs running ? */
1059         num_crtc_enabled = 0;
1060         for (i = 0; i < xf86_config->num_crtc; i++) {
1061                 if (xf86_config->crtc[i]->enabled) {
1062                         num_crtc_enabled++;
1063                 }
1064         }
1065
1066         ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
1067
1068         /* The main stuff seems to be valid for NV3x also. */
1069         if (pNv->Architecture >= NV_ARCH_30) {
1070                 /* This register is only used on the primary ramdac */
1071                 /* This seems to be needed to select the proper clocks, otherwise bad things happen */
1072
1073                 if (!state->sel_clk)
1074                         state->sel_clk = pNv->misc_info.sel_clk & ~(0xf << 16);
1075
1076                 if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
1077                         /* Only wipe when are a relevant (digital) output. */
1078                         state->sel_clk &= ~(0xf << 16);
1079                         Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1080                         /* Even with two dvi, this should not conflict. */
1081                         if (crossed_clocks) {
1082                                 state->sel_clk |= (0x1 << 16);
1083                         } else {
1084                                 state->sel_clk |= (0x4 << 16);
1085                         }
1086                 }
1087
1088                 /* Some cards, specifically dual dvi/lvds cards set another bitrange.
1089                  * I suspect inverse beheaviour to the normal bitrange, but i am not a 100% certain about this.
1090                  * This is all based on default settings found in mmio-traces.
1091                  * The blob never changes these, as it doesn't run unusual output configurations.
1092                  * It seems to prefer situations that avoid changing these bits (for a good reason?).
1093                  * I still don't know the purpose of value 2, it's similar to 4, but what exactly does it do?
1094                  */
1095
1096                 /* Some extra info:
1097                  * nv30:
1098                  *      bit 0           NVClk spread spectrum on/off
1099                  *      bit 2           MemClk spread spectrum on/off
1100                  *      bit 4           PixClk1 spread spectrum on/off
1101                  *      bit 6           PixClk2 spread spectrum on/off
1102
1103                  *      nv40:
1104                  *      what causes setting of bits not obvious but:
1105                  *      bits 4&5                relate to headA
1106                 *       bits 6&7                relate to headB
1107                 */
1108                 /* Only let digital outputs mess with this, otherwise strange output routings may mess it up. */
1109                 if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
1110                         if (pNv->Architecture == NV_ARCH_40) {
1111                                 for (i = 0; i < 4; i++) {
1112                                         uint32_t var = (state->sel_clk & (0xf << 4*i)) >> 4*i;
1113                                         if (var == 0x1 || var == 0x4) {
1114                                                 state->sel_clk &= ~(0xf << 4*i);
1115                                                 Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1116                                                 if (crossed_clocks) {
1117                                                         state->sel_clk |= (0x4 << 4*i);
1118                                                 } else {
1119                                                         state->sel_clk |= (0x1 << 4*i);
1120                                                 }
1121                                                 break; /* This should only occur once. */
1122                                         }
1123                                 }
1124                         /* Based on NV31M. */
1125                         } else if (pNv->Architecture == NV_ARCH_30) {
1126                                 for (i = 0; i < 4; i++) {
1127                                         uint32_t var = (state->sel_clk & (0xf << 4*i)) >> 4*i;
1128                                         if (var == 0x4 || var == 0x5) {
1129                                                 state->sel_clk &= ~(0xf << 4*i);
1130                                                 Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1131                                                 if (crossed_clocks) {
1132                                                         state->sel_clk |= (0x4 << 4*i);
1133                                                 } else {
1134                                                         state->sel_clk |= (0x5 << 4*i);
1135                                                 }
1136                                                 break; /* This should only occur once. */
1137                                         }
1138                                 }
1139                         }
1140                 }
1141         } else {
1142                 /* Don't change SEL_CLK on NV0x/NV1x/NV2x cards */
1143                 state->sel_clk = pNv->misc_info.sel_clk;
1144                 state->crosswired = FALSE;
1145         }
1146
1147         /* Are we crosswired? */
1148         if (output && nv_crtc->head != nv_output->preferred_output) {
1149                 state->crosswired = TRUE;
1150         } else {
1151                 state->crosswired = FALSE;
1152         }
1153
1154         if (nv_crtc->head == 1) {
1155                 if (state->db1_ratio[1])
1156                         ErrorF("We are a lover of the DB1 VCLK ratio\n");
1157         } else if (nv_crtc->head == 0) {
1158                 if (state->db1_ratio[0])
1159                         ErrorF("We are a lover of the DB1 VCLK ratio\n");
1160         }
1161
1162         /* The NV40 seems to have more similarities to NV3x than other cards. */
1163         if (pNv->NVArch < 0x41) {
1164                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL;
1165                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL;
1166         }
1167
1168         if (nv_crtc->head == 1) {
1169                 if (!state->db1_ratio[1]) {
1170                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1171                 } else {
1172                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1173                 }
1174                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
1175         } else {
1176                 if (!state->db1_ratio[0]) {
1177                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1178                 } else {
1179                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1180                 }
1181                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
1182         }
1183
1184         /* The blob uses this always, so let's do the same */
1185         if (pNv->Architecture == NV_ARCH_40) {
1186                 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
1187         }
1188
1189         /* The primary output resource doesn't seem to care */
1190         if (output && pNv->Architecture == NV_ARCH_40 && nv_output->output_resource == 1) { /* This is the "output" */
1191                 /* non-zero values are for analog, don't know about tv-out and the likes */
1192                 if (output && nv_output->type != OUTPUT_ANALOG) {
1193                         state->reg594 = 0x0;
1194                 } else if (output) {
1195                         /* Are we a flexible output? */
1196                         if (ffs(pNv->dcb_table.entry[nv_output->dcb_entry].or) & OUTPUT_0) {
1197                                 state->reg594 = 0x1;
1198                                 pNv->restricted_mode = FALSE;
1199                         } else {
1200                                 state->reg594 = 0x0;
1201                                 pNv->restricted_mode = TRUE;
1202                         }
1203
1204                         /* More values exist, but they seem related to the 3rd dac (tv-out?) somehow */
1205                         /* bit 16-19 are bits that are set on some G70 cards */
1206                         /* Those bits are also set to the 3rd OUTPUT register */
1207                         if (nv_crtc->head == 1) {
1208                                 state->reg594 |= 0x100;
1209                         }
1210                 }
1211         }
1212
1213         regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
1214         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
1215         if (pNv->Architecture >= NV_ARCH_30) {
1216                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
1217         }
1218
1219         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1220                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = ((CrtcHDisplay/16) & 0x700) >> 3;
1221         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1222                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((CrtcHDisplay*bpp)/64) & 0x700) >> 3;
1223         } else { /* framebuffer can be larger than crtc scanout area. */
1224                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
1225         }
1226         regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
1227 }
1228
1229 static void
1230 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
1231 {
1232         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1233
1234         ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->head, mode);
1235
1236         if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */
1237                 return;
1238
1239         nv_crtc->last_dpms = mode;
1240
1241         ScrnInfoPtr pScrn = crtc->scrn;
1242         NVPtr pNv = NVPTR(pScrn);
1243         unsigned char seq1 = 0, crtc17 = 0;
1244         unsigned char crtc1A;
1245
1246         if (pNv->twoHeads)
1247                 NVCrtcSetOwner(crtc);
1248
1249         crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
1250         switch(mode) {
1251                 case DPMSModeStandby:
1252                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
1253                 seq1 = 0x20;
1254                 crtc17 = 0x80;
1255                 crtc1A |= 0x80;
1256                 break;
1257         case DPMSModeSuspend:
1258                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
1259                 seq1 = 0x20;
1260                 crtc17 = 0x80;
1261                 crtc1A |= 0x40;
1262                 break;
1263         case DPMSModeOff:
1264                 /* Screen: Off; HSync: Off, VSync: Off */
1265                 seq1 = 0x20;
1266                 crtc17 = 0x00;
1267                 crtc1A |= 0xC0;
1268                 break;
1269         case DPMSModeOn:
1270         default:
1271                 /* Screen: On; HSync: On, VSync: On */
1272                 seq1 = 0x00;
1273                 crtc17 = 0x80;
1274                 break;
1275         }
1276
1277         NVVgaSeqReset(crtc, TRUE);
1278         /* Each head has it's own sequencer, so we can turn it off when we want */
1279         seq1 |= (NVReadVgaSeq(crtc, 0x01) & ~0x20);
1280         NVWriteVgaSeq(crtc, 0x1, seq1);
1281         crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
1282         usleep(10000);
1283         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
1284         NVVgaSeqReset(crtc, FALSE);
1285
1286         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
1287
1288         /* I hope this is the right place */
1289         if (crtc->enabled && mode == DPMSModeOn) {
1290                 pNv->crtc_active[nv_crtc->head] = TRUE;
1291         } else {
1292                 pNv->crtc_active[nv_crtc->head] = FALSE;
1293         }
1294 }
1295
1296 static Bool
1297 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
1298                      DisplayModePtr adjusted_mode)
1299 {
1300         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1301         ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->head);
1302
1303         return TRUE;
1304 }
1305
1306 static void
1307 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1308 {
1309         ScrnInfoPtr pScrn = crtc->scrn;
1310         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1311         NVCrtcRegPtr regp;
1312         NVPtr pNv = NVPTR(pScrn);
1313         NVFBLayout *pLayout = &pNv->CurrentLayout;
1314         int depth = pScrn->depth;
1315
1316         /* This is pitch/memory size related. */
1317         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE))
1318                 depth = pNv->console_mode[nv_crtc->head].bpp;
1319
1320         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1321
1322         /* Calculate our timings */
1323         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
1324         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
1325         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
1326         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
1327         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
1328         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
1329         int vertDisplay         = mode->CrtcVDisplay                    - 1;
1330         int vertStart           = mode->CrtcVSyncStart          - 1;
1331         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
1332         int vertTotal           = mode->CrtcVTotal                      - 2;
1333         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
1334         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
1335
1336         Bool is_fp = FALSE;
1337
1338         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1339         NVOutputPrivatePtr nv_output = NULL;
1340         if (output) {
1341                 nv_output = output->driver_private;
1342
1343                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1344                         is_fp = TRUE;
1345         }
1346
1347         ErrorF("Mode clock: %d\n", mode->Clock);
1348         ErrorF("Adjusted mode clock: %d\n", adjusted_mode->Clock);
1349
1350         /* Reverted to what nv did, because that works for all resolutions on flatpanels */
1351         if (is_fp) {
1352                 vertStart = vertTotal - 3;
1353                 vertEnd = vertTotal - 2;
1354                 vertBlankStart = vertStart;
1355                 horizStart = horizTotal - 5;
1356                 horizEnd = horizTotal - 2;
1357                 horizBlankEnd = horizTotal + 4;
1358                 if (pNv->overlayAdaptor && pNv->Architecture >= NV_ARCH_10) {
1359                         /* This reportedly works around Xv some overlay bandwidth problems*/
1360                         horizTotal += 2;
1361                 }
1362         }
1363
1364         if (mode->Flags & V_INTERLACE)
1365                 vertTotal |= 1;
1366
1367         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
1368         ErrorF("horizStart: 0x%X \n", horizStart);
1369         ErrorF("horizEnd: 0x%X \n", horizEnd);
1370         ErrorF("horizTotal: 0x%X \n", horizTotal);
1371         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
1372         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
1373         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
1374         ErrorF("vertStart: 0x%X \n", vertStart);
1375         ErrorF("vertEnd: 0x%X \n", vertEnd);
1376         ErrorF("vertTotal: 0x%X \n", vertTotal);
1377         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
1378         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
1379
1380         /*
1381         * compute correct Hsync & Vsync polarity
1382         */
1383         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
1384                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
1385
1386                 regp->MiscOutReg = 0x23;
1387                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
1388                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
1389         } else {
1390                 int VDisplay = mode->VDisplay;
1391                 if (mode->Flags & V_DBLSCAN)
1392                         VDisplay *= 2;
1393                 if (mode->VScan > 1)
1394                         VDisplay *= mode->VScan;
1395                 if (VDisplay < 400) {
1396                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
1397                 } else if (VDisplay < 480) {
1398                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
1399                 } else if (VDisplay < 768) {
1400                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
1401                 } else {
1402                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
1403                 }
1404         }
1405
1406         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
1407
1408         /*
1409         * Time Sequencer
1410         */
1411         regp->Sequencer[0] = 0x00;
1412         /* 0x20 disables the sequencer */
1413         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1414                 if (mode->HDisplay == 720) {
1415                         regp->Sequencer[1] = 0x21; /* enable 9/8 mode */
1416                 } else {
1417                         regp->Sequencer[1] = 0x20;
1418                 }
1419         } else {
1420                 if (mode->Flags & V_CLKDIV2) {
1421                         regp->Sequencer[1] = 0x29;
1422                 } else {
1423                         regp->Sequencer[1] = 0x21;
1424                 }
1425         }
1426         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1427                 regp->Sequencer[2] = 0x03; /* select 2 out of 4 planes */
1428         } else {
1429                 regp->Sequencer[2] = 0x0F;
1430         }
1431         regp->Sequencer[3] = 0x00;                     /* Font select */
1432         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1433                 regp->Sequencer[4] = 0x02;
1434         } else {
1435                 regp->Sequencer[4] = 0x0E;                             /* Misc */
1436         }
1437
1438         /*
1439         * CRTC Controller
1440         */
1441         regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
1442         regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
1443         regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
1444         regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0)
1445                                 | SetBit(7);
1446         regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
1447         regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
1448                                 | SetBitField(horizEnd,4:0,4:0);
1449         regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
1450         regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
1451                                 | SetBitField(vertDisplay,8:8,1:1)
1452                                 | SetBitField(vertStart,8:8,2:2)
1453                                 | SetBitField(vertBlankStart,8:8,3:3)
1454                                 | SetBit(4)
1455                                 | SetBitField(vertTotal,9:9,5:5)
1456                                 | SetBitField(vertDisplay,9:9,6:6)
1457                                 | SetBitField(vertStart,9:9,7:7);
1458         regp->CRTC[NV_VGA_CRTCX_PRROWSCN]  = 0x00;
1459         regp->CRTC[NV_VGA_CRTCX_MAXSCLIN]  = SetBitField(vertBlankStart,9:9,5:5)
1460                                 | SetBit(6)
1461                                 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00)
1462                                 | (NVMatchModePrivate(mode, NV_MODE_VGA) ? 0xF : 0x00); /* 8x15 chars */
1463         if (NVMatchModePrivate(mode, NV_MODE_VGA)) { /* Were do these cursor offsets come from? */
1464                 regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0xD; /* start scanline */
1465                 regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0xE; /* end scanline */
1466         } else {
1467                 regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0x00;
1468                 regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0x00;
1469         }
1470         regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00;
1471         regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
1472         regp->CRTC[0xe] = 0x00;
1473         regp->CRTC[0xf] = 0x00;
1474         regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
1475         /* What is the meaning of bit5, it is empty in the vga spec. */
1476         regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) |
1477                                                                         (NVMatchModePrivate(mode, NV_MODE_VGA) ? 0 : SetBit(5));
1478         regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
1479         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1480                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = (mode->CrtcHDisplay/16);
1481         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1482                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((mode->CrtcHDisplay*depth)/64);
1483         } else { /* framebuffer can be larger than crtc scanout area. */
1484                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
1485         }
1486         if (depth == 4) { /* How can these values be calculated? */
1487                 regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x1F;
1488         } else {
1489                 regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x00;
1490         }
1491         regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
1492         regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
1493         /* 0x80 enables the sequencer, we don't want that */
1494         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1495                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xA3 & ~0x80;
1496         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1497                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xE3 & ~0x80;
1498         } else {
1499                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80;
1500         }
1501         regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
1502
1503         /*
1504          * Some extended CRTC registers (they are not saved with the rest of the vga regs).
1505          */
1506
1507         regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
1508                                 | SetBitField(vertBlankStart,10:10,3:3)
1509                                 | SetBitField(vertStart,10:10,2:2)
1510                                 | SetBitField(vertDisplay,10:10,1:1)
1511                                 | SetBitField(vertTotal,10:10,0:0);
1512
1513         regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
1514                                 | SetBitField(horizDisplay,8:8,1:1)
1515                                 | SetBitField(horizBlankStart,8:8,2:2)
1516                                 | SetBitField(horizStart,8:8,3:3);
1517
1518         regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
1519                                 | SetBitField(vertDisplay,11:11,2:2)
1520                                 | SetBitField(vertStart,11:11,4:4)
1521                                 | SetBitField(vertBlankStart,11:11,6:6);
1522
1523         if(mode->Flags & V_INTERLACE) {
1524                 horizTotal = (horizTotal >> 1) & ~1;
1525                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
1526                 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
1527         } else {
1528                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff;  /* interlace off */
1529         }
1530
1531         /*
1532         * Graphics Display Controller
1533         */
1534         regp->Graphics[0] = 0x00;
1535         regp->Graphics[1] = 0x00;
1536         regp->Graphics[2] = 0x00;
1537         regp->Graphics[3] = 0x00;
1538         regp->Graphics[4] = 0x00;
1539         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1540                 regp->Graphics[5] = 0x10;
1541                 regp->Graphics[6] = 0x0E; /* map 32k mem */
1542                 regp->Graphics[7] = 0x00;
1543         } else {
1544                 regp->Graphics[5] = 0x40; /* 256 color mode */
1545                 regp->Graphics[6] = 0x05; /* map 64k mem + graphic mode */
1546                 regp->Graphics[7] = 0x0F;
1547         }
1548         regp->Graphics[8] = 0xFF;
1549
1550         regp->Attribute[0]  = 0x00; /* standard colormap translation */
1551         regp->Attribute[1]  = 0x01;
1552         regp->Attribute[2]  = 0x02;
1553         regp->Attribute[3]  = 0x03;
1554         regp->Attribute[4]  = 0x04;
1555         regp->Attribute[5]  = 0x05;
1556         regp->Attribute[6]  = 0x06;
1557         regp->Attribute[7]  = 0x07;
1558         regp->Attribute[8]  = 0x08;
1559         regp->Attribute[9]  = 0x09;
1560         regp->Attribute[10] = 0x0A;
1561         regp->Attribute[11] = 0x0B;
1562         regp->Attribute[12] = 0x0C;
1563         regp->Attribute[13] = 0x0D;
1564         regp->Attribute[14] = 0x0E;
1565         regp->Attribute[15] = 0x0F;
1566         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1567                 regp->Attribute[16] = 0x0C; /* Line Graphics Enable + Blink enable */
1568         } else {
1569                 regp->Attribute[16] = 0x01; /* Enable graphic mode */
1570         }
1571         /* Non-vga */
1572         regp->Attribute[17] = 0x00;
1573         regp->Attribute[18] = 0x0F; /* enable all color planes */
1574         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1575                 regp->Attribute[19] = 0x08; /* shift bits by 8 */
1576         } else {
1577                 regp->Attribute[19] = 0x00;
1578         }
1579         regp->Attribute[20] = 0x00;
1580 }
1581
1582 /**
1583  * Sets up registers for the given mode/adjusted_mode pair.
1584  *
1585  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1586  *
1587  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1588  * be easily turned on/off after this.
1589  */
1590 static void
1591 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1592 {
1593         ScrnInfoPtr pScrn = crtc->scrn;
1594         NVPtr pNv = NVPTR(pScrn);
1595         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1596         NVFBLayout *pLayout = &pNv->CurrentLayout;
1597         NVCrtcRegPtr regp, savep;
1598         uint32_t i, depth;
1599         Bool is_fp = FALSE;
1600         Bool is_lvds = FALSE;
1601
1602         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1603         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1604
1605         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1606         NVOutputPrivatePtr nv_output = NULL;
1607         if (output) {
1608                 nv_output = output->driver_private;
1609
1610                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1611                         is_fp = TRUE;
1612
1613                 if (nv_output->type == OUTPUT_LVDS)
1614                         is_lvds = TRUE;
1615         }
1616
1617         /* Registers not directly related to the (s)vga mode */
1618
1619         /* bit2 = 0 -> fine pitched crtc granularity */
1620         /* The rest disables double buffering on CRTC access */
1621         regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
1622
1623         if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
1624                 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1625                 if (nv_crtc->head == 0) {
1626                         regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1627                 }
1628
1629                 if (is_fp) {
1630                         regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0);
1631                         if (!NVMatchModePrivate(mode, NV_MODE_VGA)) {
1632                                 regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 1);
1633                         }
1634                 }
1635         } else {
1636                 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
1637                 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
1638         }
1639
1640         /* Sometimes 0x10 is used, what is this? */
1641         regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1642         /* Some kind of tmds switch for older cards */
1643         if (pNv->Architecture < NV_ARCH_40) {
1644                 regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
1645         }
1646
1647         /*
1648         * Initialize DAC palette.
1649         * Will only be written when depth != 8.
1650         */
1651         for (i = 0; i < 256; i++) {
1652                 regp->DAC[i*3] = i;
1653                 regp->DAC[(i*3)+1] = i;
1654                 regp->DAC[(i*3)+2] = i;
1655         }
1656
1657         /*
1658         * Calculate the extended registers.
1659         */
1660
1661         if (pLayout->depth < 24) {
1662                 depth = pLayout->depth;
1663         } else {
1664                 depth = 32;
1665         }
1666
1667         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1668                 /* bpp is pitch related. */
1669                 depth = pNv->console_mode[nv_crtc->head].bpp;
1670         }
1671
1672         /* What is the meaning of this register? */
1673         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1674         regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
1675
1676         regp->head = 0;
1677
1678         /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1679         /* But what are those special conditions? */
1680         if (pNv->Architecture <= NV_ARCH_30) {
1681                 if (is_fp) {
1682                         if(nv_crtc->head == 1) {
1683                                 regp->head |= NV_CRTC_FSEL_FPP1;
1684                         } else if (pNv->twoHeads) {
1685                                 regp->head |= NV_CRTC_FSEL_FPP2;
1686                         }
1687                 }
1688         } else {
1689                 /* Most G70 cards have FPP2 set on the secondary CRTC. */
1690                 if (nv_crtc->head == 1 && pNv->NVArch > 0x44) {
1691                         regp->head |= NV_CRTC_FSEL_FPP2;
1692                 }
1693         }
1694
1695         /* Except for rare conditions I2C is enabled on the primary crtc */
1696         if (nv_crtc->head == 0) {
1697                 regp->head |= NV_CRTC_FSEL_I2C;
1698         }
1699
1700         /* Set overlay to desired crtc. */
1701         if (pNv->overlayAdaptor) {
1702                 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(pNv);
1703                 if (pPriv->overlayCRTC == nv_crtc->head)
1704                         regp->head |= NV_CRTC_FSEL_OVERLAY;
1705         }
1706
1707         /* This is not what nv does, but it is what the blob does (for nv4x at least) */
1708         /* This fixes my cursor corruption issue */
1709         regp->cursorConfig = 0x0;
1710         if(mode->Flags & V_DBLSCAN)
1711                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_DOUBLE_SCAN;
1712         if (pNv->alphaCursor && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1713                 regp->cursorConfig |=   (NV_CRTC_CURSOR_CONFIG_32BPP |
1714                                                         NV_CRTC_CURSOR_CONFIG_64PIXELS |
1715                                                         NV_CRTC_CURSOR_CONFIG_64LINES |
1716                                                         NV_CRTC_CURSOR_CONFIG_ALPHA_BLEND);
1717         } else {
1718                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_32LINES;
1719         }
1720
1721         /* Unblock some timings */
1722         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1723         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1724
1725         /* What is the purpose of this register? */
1726         /* 0x14 may be disabled? */
1727         regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1728
1729         /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
1730         if (is_lvds) {
1731                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x11;
1732         } else if (is_fp) {
1733                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1734         } else {
1735                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1736         }
1737
1738         /* These values seem to vary */
1739         /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
1740         regp->CRTC[NV_VGA_CRTCX_3C] = savep->CRTC[NV_VGA_CRTCX_3C];
1741
1742         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1743                 regp->CRTC[NV_VGA_CRTCX_45] = 0x0;
1744         } else {
1745                 regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1746         }
1747
1748         /* What does this do?:
1749          * bit0: crtc0
1750          * bit6: lvds
1751          * bit7: lvds + tmds (only in X)
1752          */
1753         if (nv_crtc->head == 0)
1754                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x1;
1755         else
1756                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x0;
1757
1758         if (is_lvds)
1759                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x40;
1760
1761         if (is_fp && !NVMatchModePrivate(mode, NV_MODE_VGA))
1762                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x80;
1763
1764         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) { /* we need consistent restore. */
1765                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[nv_crtc->head];
1766         } else {
1767                 /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1.*/
1768                 if (nv_crtc->head == 1) {
1769                         regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[0];
1770                 } else {
1771                         regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[0] + 4;
1772                 }
1773         }
1774
1775         if (pNv->twoHeads)
1776                 /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1777                 regp->unk81c = NVReadCRTC(pNv, 0, NV_CRTC_081C);
1778
1779         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1780                 regp->unk830 = 0;
1781                 regp->unk834 = 0;
1782         } else {
1783                 regp->unk830 = mode->CrtcVDisplay - 3;
1784                 regp->unk834 = mode->CrtcVDisplay - 1;
1785         }
1786
1787         if (pNv->twoHeads)
1788                 /* This is what the blob does */
1789                 regp->unk850 = NVReadCRTC(pNv, 0, NV_CRTC_0850);
1790
1791         /* Never ever modify gpio, unless you know very well what you're doing */
1792         regp->gpio = NVReadCRTC(pNv, 0, NV_CRTC_GPIO);
1793
1794         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1795                 regp->config = 0x0; /* VGA mode */
1796         } else {
1797                 regp->config = 0x2; /* HSYNC mode */
1798         }
1799
1800         /* Some misc regs */
1801         regp->CRTC[NV_VGA_CRTCX_43] = 0x1;
1802         if (pNv->Architecture == NV_ARCH_40) {
1803                 regp->CRTC[NV_VGA_CRTCX_85] = 0xFF;
1804                 regp->CRTC[NV_VGA_CRTCX_86] = 0x1;
1805         }
1806
1807         /*
1808          * Calculate the state that is common to all crtc's (stored in the state struct).
1809          */
1810         ErrorF("crtc %d %d %d\n", nv_crtc->head, mode->CrtcHDisplay, pScrn->displayWidth);
1811         nv_crtc_calc_state_ext(crtc,
1812                                 mode,
1813                                 depth,
1814                                 pScrn->displayWidth,
1815                                 mode->CrtcHDisplay,
1816                                 mode->CrtcVDisplay,
1817                                 adjusted_mode->Clock,
1818                                 mode->Flags);
1819
1820         /* Enable slaved mode */
1821         if (is_fp) {
1822                 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1823         }
1824 }
1825
1826 static void
1827 nv_crtc_mode_set_ramdac_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1828 {
1829         ScrnInfoPtr pScrn = crtc->scrn;
1830         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1831         NVCrtcRegPtr regp, savep;
1832         NVPtr pNv = NVPTR(pScrn);
1833         NVFBLayout *pLayout = &pNv->CurrentLayout;
1834         Bool is_fp = FALSE;
1835         Bool is_lvds = FALSE;
1836         float aspect_ratio, panel_ratio;
1837         uint32_t h_scale, v_scale;
1838
1839         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1840         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1841
1842         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1843         NVOutputPrivatePtr nv_output = NULL;
1844         if (output) {
1845                 nv_output = output->driver_private;
1846
1847                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1848                         is_fp = TRUE;
1849
1850                 if (nv_output->type == OUTPUT_LVDS)
1851                         is_lvds = TRUE;
1852         }
1853
1854         if (is_fp) {
1855                 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
1856                 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
1857                 /* This is what the blob does. */
1858                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HSyncStart - 75 - 1;
1859                 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
1860                 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
1861                 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
1862                 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
1863
1864                 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
1865                 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
1866                 /* This is what the blob does. */
1867                 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VTotal - 5 - 1;
1868                 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
1869                 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
1870                 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
1871                 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
1872
1873                 ErrorF("Horizontal:\n");
1874                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
1875                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
1876                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
1877                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
1878                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
1879                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
1880                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
1881
1882                 ErrorF("Vertical:\n");
1883                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
1884                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
1885                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
1886                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
1887                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
1888                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
1889                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
1890         }
1891
1892         /*
1893         * bit0: positive vsync
1894         * bit4: positive hsync
1895         * bit8: enable center mode
1896         * bit9: enable native mode
1897         * bit24: 12/24 bit interface (12bit=on, 24bit=off)
1898         * bit26: a bit sometimes seen on some g70 cards
1899         * bit28: fp display enable bit
1900         * bit31: set for dual link LVDS
1901         * nv10reg contains a few more things, but i don't quite get what it all means.
1902         */
1903
1904         if (pNv->Architecture >= NV_ARCH_30)
1905                 regp->fp_control[nv_crtc->head] = 0x00100000;
1906         else
1907                 regp->fp_control[nv_crtc->head] = 0x00000000;
1908
1909         /* Deal with vsync/hsync polarity */
1910         /* LVDS screens do set this, but modes with +ve syncs are very rare */
1911         if (is_fp) {
1912                 if (adjusted_mode->Flags & V_PVSYNC)
1913                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
1914                 if (adjusted_mode->Flags & V_PHSYNC)
1915                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
1916         } else {
1917                 /* The blob doesn't always do this, but often */
1918                 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_VSYNC_DISABLE;
1919                 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_HSYNC_DISABLE;
1920         }
1921
1922         if (is_fp) {
1923                 if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) /* seems to be used almost always */
1924                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1925                 else if (nv_output->scaling_mode == SCALE_PANEL) /* panel needs to scale */
1926                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
1927                 /* This is also true for panel scaling, so we must put the panel scale check first */
1928                 else if (mode->Clock == adjusted_mode->Clock) /* native mode */
1929                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
1930                 else /* gpu needs to scale */
1931                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1932         }
1933
1934         if (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
1935                 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
1936
1937         /* If the special bit exists, it exists on both ramdacs */
1938         regp->fp_control[nv_crtc->head] |= NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL) & (1 << 26);
1939
1940         if (is_fp)
1941                 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS;
1942         else
1943                 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE;
1944
1945         Bool lvds_use_straps = pNv->dcb_table.entry[nv_output->dcb_entry].lvdsconf.use_straps_for_mode;
1946         if (is_lvds && ((lvds_use_straps && pNv->VBIOS.fp.dual_link) || (!lvds_use_straps && adjusted_mode->Clock >= pNv->VBIOS.fp.duallink_transition_clk)))
1947                 regp->fp_control[nv_crtc->head] |= (8 << 28);
1948
1949         if (is_fp) {
1950                 ErrorF("Pre-panel scaling\n");
1951                 ErrorF("panel-size:%dx%d\n", nv_output->fpWidth, nv_output->fpHeight);
1952                 panel_ratio = (nv_output->fpWidth)/(float)(nv_output->fpHeight);
1953                 ErrorF("panel_ratio=%f\n", panel_ratio);
1954                 aspect_ratio = (mode->HDisplay)/(float)(mode->VDisplay);
1955                 ErrorF("aspect_ratio=%f\n", aspect_ratio);
1956                 /* Scale factors is the so called 20.12 format, taken from Haiku */
1957                 h_scale = ((1 << 12) * mode->HDisplay)/nv_output->fpWidth;
1958                 v_scale = ((1 << 12) * mode->VDisplay)/nv_output->fpHeight;
1959                 ErrorF("h_scale=%d\n", h_scale);
1960                 ErrorF("v_scale=%d\n", v_scale);
1961
1962                 /* This can override HTOTAL and VTOTAL */
1963                 regp->debug_2 = 0;
1964
1965                 /* We want automatic scaling */
1966                 regp->debug_1 = 0;
1967
1968                 regp->fp_hvalid_start = 0;
1969                 regp->fp_hvalid_end = (nv_output->fpWidth - 1);
1970
1971                 regp->fp_vvalid_start = 0;
1972                 regp->fp_vvalid_end = (nv_output->fpHeight - 1);
1973
1974                 /* 0 = panel scaling */
1975                 if (nv_output->scaling_mode == SCALE_PANEL) {
1976                         ErrorF("Flat panel is doing the scaling.\n");
1977                 } else {
1978                         ErrorF("GPU is doing the scaling.\n");
1979
1980                         if (nv_output->scaling_mode == SCALE_ASPECT) {
1981                                 /* GPU scaling happens automaticly at a ratio of 1.33 */
1982                                 /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
1983                                 if (h_scale != (1 << 12) && (panel_ratio > (aspect_ratio + 0.10))) {
1984                                         uint32_t diff;
1985
1986                                         ErrorF("Scaling resolution on a widescreen panel\n");
1987
1988                                         /* Scaling in both directions needs to the same */
1989                                         h_scale = v_scale;
1990
1991                                         /* Set a new horizontal scale factor and enable testmode (bit12) */
1992                                         regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
1993
1994                                         diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
1995                                         regp->fp_hvalid_start = diff/2;
1996                                         regp->fp_hvalid_end = nv_output->fpWidth - (diff/2) - 1;
1997                                 }
1998
1999                                 /* Same scaling, just for panels with aspect ratio's smaller than 1 */
2000                                 if (v_scale != (1 << 12) && (panel_ratio < (aspect_ratio - 0.10))) {
2001                                         uint32_t diff;
2002
2003                                         ErrorF("Scaling resolution on a portrait panel\n");
2004
2005                                         /* Scaling in both directions needs to the same */
2006                                         v_scale = h_scale;
2007
2008                                         /* Set a new vertical scale factor and enable testmode (bit28) */
2009                                         regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
2010
2011                                         diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
2012                                         regp->fp_vvalid_start = diff/2;
2013                                         regp->fp_vvalid_end = nv_output->fpHeight - (diff/2) - 1;
2014                                 }
2015                         }
2016                 }
2017
2018                 ErrorF("Post-panel scaling\n");
2019         }
2020
2021         if (!is_fp && NVMatchModePrivate(mode, NV_MODE_VGA)) {
2022                 regp->debug_1 = 0x08000800;
2023         }
2024
2025         if (pNv->Architecture >= NV_ARCH_10) {
2026                 /* Only bit that bios and blob set. */
2027                 regp->nv10_cursync = (1<<25);
2028         }
2029
2030         /* These are the common blob values, minus a few fp specific bit's */
2031         /* Let's keep the TMDS pll and fpclock running in all situations */
2032         regp->debug_0[nv_crtc->head] = 0x1101100;
2033
2034         if (is_fp && nv_output->scaling_mode != SCALE_NOSCALE) {
2035                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_XSCALE_ENABLED;
2036                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_YSCALE_ENABLED;
2037         } else if (is_fp) { /* no_scale mode, so we must center it */
2038                 uint32_t diff;
2039
2040                 diff = nv_output->fpWidth - mode->HDisplay;
2041                 regp->fp_hvalid_start = diff/2;
2042                 regp->fp_hvalid_end = (nv_output->fpWidth - diff/2 - 1);
2043
2044                 diff = nv_output->fpHeight - mode->VDisplay;
2045                 regp->fp_vvalid_start = diff/2;
2046                 regp->fp_vvalid_end = (nv_output->fpHeight - diff/2 - 1);
2047         }
2048
2049         /* Is this crtc bound or output bound? */
2050         /* Does the bios TMDS script try to change this sometimes? */
2051         if (is_fp) {
2052                 /* I am not completely certain, but seems to be set only for dfp's */
2053                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED;
2054         }
2055
2056         if (output)
2057                 ErrorF("output %d debug_0 %08X\n", nv_output->output_resource, regp->debug_0[nv_crtc->head]);
2058
2059         /* Flatpanel support needs at least a NV10 */
2060         if (pNv->twoHeads) {
2061                 /* The blob does this differently. */
2062                 /* TODO: Find out what precisely and why. */
2063                 /* Let's not destroy any bits that were already present. */
2064                 if (pNv->FPDither || (is_lvds && pNv->VBIOS.fp.if_is_18bit)) {
2065                         if (pNv->NVArch == 0x11) {
2066                                 regp->dither = savep->dither | 0x00010000;
2067                         } else {
2068                                 int i;
2069                                 regp->dither = savep->dither | 0x00000001;
2070                                 for (i = 0; i < 3; i++) {
2071                                         regp->dither_regs[i] = 0xe4e4e4e4;
2072                                         regp->dither_regs[i + 3] = 0x44444444;
2073                                 }
2074                         }
2075                 } else {
2076                         regp->dither = savep->dither;
2077                 }
2078         }
2079
2080         uint8_t depth;
2081         /* This is mode related, not pitch. */
2082         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
2083                 depth = pNv->console_mode[nv_crtc->head].depth;
2084         } else {
2085                 depth = pLayout->depth;
2086         }
2087
2088         switch (depth) {
2089                 case 4:
2090                         regp->general = 0x00000100;
2091                         break;
2092                 case 24:
2093                 case 15:
2094                         regp->general = 0x00100100;
2095                         break;
2096                 case 32:
2097                 case 16:
2098                 case 8:
2099                 default:
2100                         regp->general = 0x00101100;
2101                         break;
2102         }
2103
2104         if (depth > 8 && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
2105                 regp->general |= 0x30; /* enable palette mode */
2106         }
2107
2108         if (pNv->alphaCursor && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
2109                 /* PIPE_LONG mode, something to do with the size of the cursor? */
2110                 regp->general |= (1<<29);
2111         }
2112
2113         /* Some values the blob sets */
2114         /* This may apply to the real ramdac that is being used (for crosswired situations) */
2115         /* Nevertheless, it's unlikely to cause many problems, since the values are equal for both */
2116         regp->unk_a20 = 0x0;
2117         regp->unk_a24 = 0xfffff;
2118         regp->unk_a34 = 0x1;
2119
2120         if (pNv->twoHeads) {
2121                 /* Do we also "own" the other register pair? */
2122                 /* If we own neither, they will just be ignored at load time. */
2123                 uint8_t other_head = (~nv_crtc->head) & 1;
2124                 if (pNv->fp_regs_owner[other_head] == nv_crtc->head) {
2125                         if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS) {
2126                                 regp->fp_control[other_head] = regp->fp_control[nv_crtc->head];
2127                                 regp->debug_0[other_head] = regp->debug_0[nv_crtc->head];
2128                                 /* Set TMDS_PLL and FPCLK, only seen for a NV31M so far. */
2129                                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK;
2130                                 regp->debug_0[other_head] |= NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL;
2131                         } else {
2132                                 ErrorF("This is BAD, we own more than one fp reg set, but are not a LVDS or TMDS output.\n");
2133                         }
2134                 }
2135         }
2136 }
2137
2138 /**
2139  * Sets up registers for the given mode/adjusted_mode pair.
2140  *
2141  * The clocks, CRTCs and outputs attached to this CRTC must be off.
2142  *
2143  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
2144  * be easily turned on/off after this.
2145  */
2146 static void
2147 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
2148                  DisplayModePtr adjusted_mode,
2149                  int x, int y)
2150 {
2151         ScrnInfoPtr pScrn = crtc->scrn;
2152         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2153         NVPtr pNv = NVPTR(pScrn);
2154         NVFBLayout *pLayout = &pNv->CurrentLayout;
2155
2156         ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->head);
2157
2158         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->head);
2159         xf86PrintModeline(pScrn->scrnIndex, mode);
2160         if (pNv->twoHeads)
2161                 NVCrtcSetOwner(crtc);
2162
2163         nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
2164         nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
2165         nv_crtc_mode_set_ramdac_regs(crtc, mode, adjusted_mode);
2166
2167         NVVgaProtect(crtc, TRUE);
2168         nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
2169         nv_crtc_load_state_ext(crtc, &pNv->ModeReg, FALSE);
2170         if (pLayout->depth > 8)
2171                 nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
2172         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
2173         if (pNv->Architecture == NV_ARCH_40) {
2174                 nv40_crtc_load_state_pll(crtc, &pNv->ModeReg);
2175         } else {
2176                 nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
2177         }
2178
2179         NVVgaProtect(crtc, FALSE);
2180
2181         NVCrtcSetBase(crtc, x, y, NVMatchModePrivate(mode, NV_MODE_CONSOLE));
2182
2183 #if X_BYTE_ORDER == X_BIG_ENDIAN
2184         /* turn on LFB swapping */
2185         {
2186                 unsigned char tmp;
2187
2188                 tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
2189                 tmp |= (1 << 7);
2190                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
2191         }
2192 #endif
2193 }
2194
2195 void nv_crtc_save(xf86CrtcPtr crtc)
2196 {
2197         ScrnInfoPtr pScrn = crtc->scrn;
2198         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2199         NVPtr pNv = NVPTR(pScrn);
2200
2201         ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->head);
2202
2203         /* We just came back from terminal, so unlock */
2204         NVCrtcLockUnlock(crtc, FALSE);
2205
2206         nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
2207         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
2208         nv_crtc_save_state_palette(crtc, &pNv->SavedReg);
2209         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
2210         if (pNv->Architecture == NV_ARCH_40) {
2211                 nv40_crtc_save_state_pll(pNv, &pNv->SavedReg);
2212         } else {
2213                 nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
2214         }
2215 }
2216
2217 void nv_crtc_restore(xf86CrtcPtr crtc)
2218 {
2219         ScrnInfoPtr pScrn = crtc->scrn;
2220         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2221         NVPtr pNv = NVPTR(pScrn);
2222         RIVA_HW_STATE *state;
2223         NVCrtcRegPtr savep;
2224
2225         state = &pNv->SavedReg;
2226         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
2227
2228         ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->head);
2229
2230         /* Just to be safe */
2231         NVCrtcLockUnlock(crtc, FALSE);
2232
2233         NVVgaProtect(crtc, TRUE);
2234         nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
2235         nv_crtc_load_state_ext(crtc, &pNv->SavedReg, TRUE);
2236         nv_crtc_load_state_palette(crtc, &pNv->SavedReg);
2237         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
2238
2239         /* Force restoring vpll. */
2240         state->vpll_changed[nv_crtc->head] = TRUE;
2241
2242         if (pNv->Architecture == NV_ARCH_40) {
2243                 nv40_crtc_load_state_pll(crtc, &pNv->SavedReg);
2244         } else {
2245                 nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
2246         }
2247         if (pNv->twoHeads)
2248                 nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->vtOWNER);
2249         NVVgaProtect(crtc, FALSE);
2250
2251         nv_crtc->last_dpms = NV_DPMS_CLEARED;
2252 }
2253
2254 static void
2255 NVResetCrtcConfig(xf86CrtcPtr crtc, Bool set)
2256 {
2257         ScrnInfoPtr pScrn = crtc->scrn;
2258         NVPtr pNv = NVPTR(pScrn);
2259
2260         if (pNv->twoHeads) {
2261                 uint32_t val = 0;
2262
2263                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2264
2265                 if (set) {
2266                         NVCrtcRegPtr regp;
2267
2268                         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2269                         val = regp->head;
2270                 }
2271
2272                 NVCrtcWriteCRTC(crtc, NV_CRTC_FSEL, val);
2273         }
2274 }
2275
2276 void nv_crtc_prepare(xf86CrtcPtr crtc)
2277 {
2278         ScrnInfoPtr pScrn = crtc->scrn;
2279         NVPtr pNv = NVPTR(pScrn);
2280         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2281
2282         ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->head);
2283
2284         /* Just in case */
2285         NVCrtcLockUnlock(crtc, 0);
2286
2287         NVResetCrtcConfig(crtc, FALSE);
2288
2289         crtc->funcs->dpms(crtc, DPMSModeOff);
2290
2291         /* Sync the engine before adjust mode */
2292         if (pNv->EXADriverPtr) {
2293                 exaMarkSync(pScrn->pScreen);
2294                 exaWaitSync(pScrn->pScreen);
2295         }
2296
2297         NVCrtcBlankScreen(crtc, FALSE); /* Blank screen */
2298
2299         /* Some more preperation. */
2300         NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, 0x1); /* Go to non-vga mode/out of enhanced mode */
2301         if (pNv->Architecture == NV_ARCH_40) {
2302                 uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
2303                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
2304         }
2305 }
2306
2307 void nv_crtc_commit(xf86CrtcPtr crtc)
2308 {
2309         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2310         ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->head);
2311
2312         crtc->funcs->dpms (crtc, DPMSModeOn);
2313
2314         if (crtc->scrn->pScreen != NULL)
2315                 xf86_reload_cursors (crtc->scrn->pScreen);
2316
2317         NVResetCrtcConfig(crtc, TRUE);
2318 }
2319
2320 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
2321 {
2322         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2323         ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->head);
2324
2325         return FALSE;
2326 }
2327
2328 static void nv_crtc_unlock(xf86CrtcPtr crtc)
2329 {
2330         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2331         ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->head);
2332 }
2333
2334 static void
2335 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
2336                                         int size)
2337 {
2338         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2339         ScrnInfoPtr pScrn = crtc->scrn;
2340         NVPtr pNv = NVPTR(pScrn);
2341         int i, j;
2342
2343         NVCrtcRegPtr regp;
2344         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2345
2346         switch (pNv->CurrentLayout.depth) {
2347         case 15:
2348                 /* R5G5B5 */
2349                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
2350                 for (i = 0; i < 32; i++) {
2351                         for (j = 0; j < 8; j++) {
2352                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2353                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
2354                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2355                         }
2356                 }
2357                 break;
2358         case 16:
2359                 /* R5G6B5 */
2360                 /* First deal with the 5 bit colors */
2361                 for (i = 0; i < 32; i++) {
2362                         for (j = 0; j < 8; j++) {
2363                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2364                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2365                         }
2366                 }
2367                 /* Now deal with the 6 bit color */
2368                 for (i = 0; i < 64; i++) {
2369                         for (j = 0; j < 4; j++) {
2370                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
2371                         }
2372                 }
2373                 break;
2374         default:
2375                 /* R8G8B8 */
2376                 for (i = 0; i < 256; i++) {
2377                         regp->DAC[i * 3] = red[i] >> 8;
2378                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
2379                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
2380                 }
2381                 break;
2382         }
2383
2384         nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
2385 }
2386
2387 /**
2388  * Allocates memory for a locked-in-framebuffer shadow of the given
2389  * width and height for this CRTC's rotated shadow framebuffer.
2390  */
2391
2392 static void *
2393 nv_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
2394 {
2395         ErrorF("nv_crtc_shadow_allocate is called\n");
2396         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2397         ScrnInfoPtr pScrn = crtc->scrn;
2398 #if !NOUVEAU_EXA_PIXMAPS
2399         ScreenPtr pScreen = pScrn->pScreen;
2400 #endif /* !NOUVEAU_EXA_PIXMAPS */
2401         NVPtr pNv = NVPTR(pScrn);
2402         void *offset;
2403
2404         unsigned long rotate_pitch;
2405         int size, align = 64;
2406
2407         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2408         size = rotate_pitch * height;
2409
2410         assert(nv_crtc->shadow == NULL);
2411 #if NOUVEAU_EXA_PIXMAPS
2412         if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN,
2413                         align, size, &nv_crtc->shadow)) {
2414                 ErrorF("Failed to allocate memory for shadow buffer!\n");
2415                 return NULL;
2416         }
2417
2418         if (nv_crtc->shadow && nouveau_bo_map(nv_crtc->shadow, NOUVEAU_BO_RDWR)) {
2419                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2420                                 "Failed to map shadow buffer.\n");
2421                 return NULL;
2422         }
2423
2424         offset = nv_crtc->shadow->map;
2425 #else
2426         nv_crtc->shadow = exaOffscreenAlloc(pScreen, size, align, TRUE, NULL, NULL);
2427         if (nv_crtc->shadow == NULL) {
2428                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2429                         "Couldn't allocate shadow memory for rotated CRTC\n");
2430                 return NULL;
2431         }
2432         offset = pNv->FB->map + nv_crtc->shadow->offset;
2433 #endif /* NOUVEAU_EXA_PIXMAPS */
2434
2435         return offset;
2436 }
2437
2438 /**
2439  * Creates a pixmap for this CRTC's rotated shadow framebuffer.
2440  */
2441 static PixmapPtr
2442 nv_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
2443 {
2444         ErrorF("nv_crtc_shadow_create is called\n");
2445         ScrnInfoPtr pScrn = crtc->scrn;
2446 #if NOUVEAU_EXA_PIXMAPS
2447         ScreenPtr pScreen = pScrn->pScreen;
2448         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2449 #endif /* NOUVEAU_EXA_PIXMAPS */
2450         unsigned long rotate_pitch;
2451         PixmapPtr rotate_pixmap;
2452 #if NOUVEAU_EXA_PIXMAPS
2453         struct nouveau_pixmap *nvpix;
2454 #endif /* NOUVEAU_EXA_PIXMAPS */
2455
2456         if (!data)
2457                 data = crtc->funcs->shadow_allocate (crtc, width, height);
2458
2459         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2460
2461 #if NOUVEAU_EXA_PIXMAPS
2462         /* Create a dummy pixmap, to get a private that will be accepted by the system.*/
2463         rotate_pixmap = pScreen->CreatePixmap(pScreen,
2464                                                                 0, /* width */
2465                                                                 0, /* height */
2466         #ifdef CREATE_PIXMAP_USAGE_SCRATCH /* there seems to have been no api bump */
2467                                                                 pScrn->depth,
2468                                                                 0);
2469         #else
2470                                                                 pScrn->depth);
2471         #endif /* CREATE_PIXMAP_USAGE_SCRATCH */
2472 #else
2473         rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen,
2474                                                                 width, height,
2475                                                                 pScrn->depth,
2476                                                                 pScrn->bitsPerPixel,
2477                                                                 rotate_pitch,
2478                                                                 data);
2479 #endif /* NOUVEAU_EXA_PIXMAPS */
2480
2481         if (rotate_pixmap == NULL) {
2482                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2483                         "Couldn't allocate shadow pixmap for rotated CRTC\n");
2484         }
2485
2486 #if NOUVEAU_EXA_PIXMAPS
2487         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2488         if (!nvpix) {
2489                 ErrorF("No shadow private, stage 1\n");
2490         } else {
2491                 nvpix->bo = nv_crtc->shadow;
2492                 nvpix->mapped = TRUE;
2493         }
2494
2495         /* Modify the pixmap to actually be the one we need. */
2496         pScreen->ModifyPixmapHeader(rotate_pixmap,
2497                                         width,
2498                                         height,
2499                                         pScrn->depth,
2500                                         pScrn->bitsPerPixel,
2501                                         rotate_pitch,
2502                                         data);
2503
2504         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2505         if (!nvpix || !nvpix->bo)
2506                 ErrorF("No shadow private, stage 2\n");
2507 #endif /* NOUVEAU_EXA_PIXMAPS */
2508
2509         return rotate_pixmap;
2510 }
2511
2512 static void
2513 nv_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
2514 {
2515         ErrorF("nv_crtc_shadow_destroy is called\n");
2516         ScrnInfoPtr pScrn = crtc->scrn;
2517         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2518         ScreenPtr pScreen = pScrn->pScreen;
2519
2520         if (rotate_pixmap) { /* This should also unmap the buffer object if relevant. */
2521                 pScreen->DestroyPixmap(rotate_pixmap);
2522         }
2523
2524 #if !NOUVEAU_EXA_PIXMAPS
2525         if (data && nv_crtc->shadow) {
2526                 exaOffscreenFree(pScreen, nv_crtc->shadow);
2527         }
2528 #endif /* !NOUVEAU_EXA_PIXMAPS */
2529
2530         nv_crtc->shadow = NULL;
2531 }
2532
2533 /* NV04-NV10 doesn't support alpha cursors */
2534 static const xf86CrtcFuncsRec nv_crtc_funcs = {
2535         .dpms = nv_crtc_dpms,
2536         .save = nv_crtc_save, /* XXX */
2537         .restore = nv_crtc_restore, /* XXX */
2538         .mode_fixup = nv_crtc_mode_fixup,
2539         .mode_set = nv_crtc_mode_set,
2540         .prepare = nv_crtc_prepare,
2541         .commit = nv_crtc_commit,
2542         .destroy = NULL, /* XXX */
2543         .lock = nv_crtc_lock,
2544         .unlock = nv_crtc_unlock,
2545         .set_cursor_colors = nv_crtc_set_cursor_colors,
2546         .set_cursor_position = nv_crtc_set_cursor_position,
2547         .show_cursor = nv_crtc_show_cursor,
2548         .hide_cursor = nv_crtc_hide_cursor,
2549         .load_cursor_image = nv_crtc_load_cursor_image,
2550         .gamma_set = nv_crtc_gamma_set,
2551         .shadow_create = nv_crtc_shadow_create,
2552         .shadow_allocate = nv_crtc_shadow_allocate,
2553         .shadow_destroy = nv_crtc_shadow_destroy,
2554 };
2555
2556 /* NV11 and up has support for alpha cursors. */
2557 /* Due to different maximum sizes we cannot allow it to use normal cursors */
2558 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
2559         .dpms = nv_crtc_dpms,
2560         .save = nv_crtc_save, /* XXX */
2561         .restore = nv_crtc_restore, /* XXX */
2562         .mode_fixup = nv_crtc_mode_fixup,
2563         .mode_set = nv_crtc_mode_set,
2564         .prepare = nv_crtc_prepare,
2565         .commit = nv_crtc_commit,
2566         .destroy = NULL, /* XXX */
2567         .lock = nv_crtc_lock,
2568         .unlock = nv_crtc_unlock,
2569         .set_cursor_colors = NULL, /* Alpha cursors do not need this */
2570         .set_cursor_position = nv_crtc_set_cursor_position,
2571         .show_cursor = nv_crtc_show_cursor,
2572         .hide_cursor = nv_crtc_hide_cursor,
2573         .load_cursor_argb = nv_crtc_load_cursor_argb,
2574         .gamma_set = nv_crtc_gamma_set,
2575         .shadow_create = nv_crtc_shadow_create,
2576         .shadow_allocate = nv_crtc_shadow_allocate,
2577         .shadow_destroy = nv_crtc_shadow_destroy,
2578 };
2579
2580
2581 void
2582 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
2583 {
2584         NVPtr pNv = NVPTR(pScrn);
2585         xf86CrtcPtr crtc;
2586         NVCrtcPrivatePtr nv_crtc;
2587
2588         if (pNv->NVArch >= 0x11) {
2589                 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
2590         } else {
2591                 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
2592         }
2593         if (crtc == NULL)
2594                 return;
2595
2596         nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
2597         nv_crtc->head = crtc_num;
2598         nv_crtc->last_dpms = NV_DPMS_CLEARED;
2599         pNv->fp_regs_owner[nv_crtc->head] = nv_crtc->head;
2600
2601         crtc->driver_private = nv_crtc;
2602
2603         NVCrtcLockUnlock(crtc, FALSE);
2604 }
2605
2606 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2607 {
2608         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2609         int i;
2610         NVCrtcRegPtr regp;
2611
2612         regp = &state->crtc_reg[nv_crtc->head];
2613
2614         NVWritePVIO(crtc, VGA_MISC_OUT_W, regp->MiscOutReg);
2615
2616         for (i = 0; i < 5; i++)
2617                 NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
2618
2619         /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
2620         NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
2621
2622         for (i = 0; i < 25; i++)
2623                 NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
2624
2625         for (i = 0; i < 9; i++)
2626                 NVWriteVgaGr(crtc, i, regp->Graphics[i]);
2627
2628         NVEnablePalette(crtc);
2629         for (i = 0; i < 21; i++)
2630                 NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
2631
2632         NVDisablePalette(crtc);
2633 }
2634
2635 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override)
2636 {
2637         ScrnInfoPtr pScrn = crtc->scrn;
2638         NVPtr pNv = NVPTR(pScrn);
2639         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2640         NVCrtcRegPtr regp;
2641         int i;
2642
2643         regp = &state->crtc_reg[nv_crtc->head];
2644
2645         if (pNv->Architecture >= NV_ARCH_10) {
2646                 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
2647                 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
2648                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
2649                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
2650                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2651                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2652                 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2653                 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2654                 nvWriteMC(pNv, 0x1588, 0);
2655
2656                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
2657                 NVCrtcWriteCRTC(crtc, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
2658                 NVCrtcWriteCRTC(crtc, NV_CRTC_0830, regp->unk830);
2659                 NVCrtcWriteCRTC(crtc, NV_CRTC_0834, regp->unk834);
2660                 if (pNv->Architecture == NV_ARCH_40) {
2661                         NVCrtcWriteCRTC(crtc, NV_CRTC_0850, regp->unk850);
2662                         NVCrtcWriteCRTC(crtc, NV_CRTC_081C, regp->unk81c);
2663                 }
2664
2665                 if (pNv->Architecture == NV_ARCH_40) {
2666                         uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
2667                         if (regp->config == 0x2) { /* enhanced "horizontal only" non-vga mode */
2668                                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 | 0x10000);
2669                         } else {
2670                                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
2671                         }
2672                 }
2673         }
2674
2675         NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, regp->config);
2676         NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO, regp->gpio);
2677
2678         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
2679         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
2680         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
2681         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
2682         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
2683         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
2684         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
2685         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
2686         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
2687         if (pNv->Architecture >= NV_ARCH_30)
2688                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
2689
2690         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
2691         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
2692         if (pNv->Architecture == NV_ARCH_40) /* HW bug */
2693                 nv_crtc_fix_nv40_hw_cursor(crtc);
2694         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
2695         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
2696
2697         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
2698         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
2699         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3C, regp->CRTC[NV_VGA_CRTCX_3C]);
2700         if (pNv->Architecture >= NV_ARCH_10) {
2701                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
2702                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_43, regp->CRTC[NV_VGA_CRTCX_43]);
2703                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
2704                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_4B, regp->CRTC[NV_VGA_CRTCX_4B]);
2705                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
2706         }
2707         /* NV11 and NV20 stop at 0x52. */
2708         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
2709                 if (override)
2710                         for (i = 0; i < 0x10; i++)
2711                                 NVWriteVGACR5758(pNv, nv_crtc->head, i, regp->CR58[i]);
2712
2713                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
2714                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
2715
2716                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
2717
2718                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_85, regp->CRTC[NV_VGA_CRTCX_85]);
2719                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_86, regp->CRTC[NV_VGA_CRTCX_86]);
2720         }
2721
2722         /* Setting 1 on this value gives you interrupts for every vblank period. */
2723         NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_EN_0, 0);
2724         NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
2725
2726         pNv->CurrentState = state;
2727 }
2728
2729 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2730 {
2731         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2732         int i;
2733         NVCrtcRegPtr regp;
2734
2735         regp = &state->crtc_reg[nv_crtc->head];
2736
2737         regp->MiscOutReg = NVReadPVIO(crtc, VGA_MISC_OUT_R);
2738
2739         for (i = 0; i < 25; i++)
2740                 regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
2741
2742         NVEnablePalette(crtc);
2743         for (i = 0; i < 21; i++)
2744                 regp->Attribute[i] = NVReadVgaAttr(crtc, i);
2745         NVDisablePalette(crtc);
2746
2747         for (i = 0; i < 9; i++)
2748                 regp->Graphics[i] = NVReadVgaGr(crtc, i);
2749
2750         for (i = 0; i < 5; i++)
2751                 regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
2752 }
2753
2754 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2755 {
2756         ScrnInfoPtr pScrn = crtc->scrn;
2757         NVPtr pNv = NVPTR(pScrn);
2758         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2759         NVCrtcRegPtr regp;
2760         int i;
2761
2762         regp = &state->crtc_reg[nv_crtc->head];
2763
2764         regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
2765         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
2766         regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
2767         regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
2768         regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
2769         regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
2770         regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
2771
2772         regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
2773         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
2774         regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
2775         if (pNv->Architecture >= NV_ARCH_30)
2776                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
2777         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
2778         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
2779         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
2780         regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
2781
2782         if (pNv->Architecture >= NV_ARCH_10) {
2783                 regp->unk830 = NVCrtcReadCRTC(crtc, NV_CRTC_0830);
2784                 regp->unk834 = NVCrtcReadCRTC(crtc, NV_CRTC_0834);
2785                 if (pNv->Architecture == NV_ARCH_40) {
2786                         regp->unk850 = NVCrtcReadCRTC(crtc, NV_CRTC_0850);
2787                         regp->unk81c = NVCrtcReadCRTC(crtc, NV_CRTC_081C);
2788                 }
2789                 if (pNv->twoHeads) {
2790                         regp->head = NVCrtcReadCRTC(crtc, NV_CRTC_FSEL);
2791                         regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
2792                 }
2793                 regp->cursorConfig = NVCrtcReadCRTC(crtc, NV_CRTC_CURSOR_CONFIG);
2794         }
2795
2796         regp->gpio = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO);
2797         regp->config = NVCrtcReadCRTC(crtc, NV_CRTC_CONFIG);
2798
2799         regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
2800         regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
2801         regp->CRTC[NV_VGA_CRTCX_3C] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3C);
2802         if (pNv->Architecture >= NV_ARCH_10) {
2803                 regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
2804                 regp->CRTC[NV_VGA_CRTCX_43] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_43);
2805                 regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
2806                 regp->CRTC[NV_VGA_CRTCX_4B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_4B);
2807                 regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
2808         }
2809         /* NV11 and NV20 don't have this, they stop at 0x52. */
2810         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
2811                 for (i = 0; i < 0x10; i++)
2812                         regp->CR58[i] = NVReadVGACR5758(pNv, nv_crtc->head, i);
2813
2814                 regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
2815                 regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
2816                 regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
2817
2818                 regp->CRTC[NV_VGA_CRTCX_85] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_85);
2819                 regp->CRTC[NV_VGA_CRTCX_86] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_86);
2820         }
2821 }
2822
2823 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2824 {
2825         ScrnInfoPtr pScrn = crtc->scrn;
2826         NVPtr pNv = NVPTR(pScrn);
2827         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2828         NVCrtcRegPtr regp;
2829         int i;
2830
2831         regp = &state->crtc_reg[nv_crtc->head];
2832
2833         regp->general = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL);
2834
2835         regp->fp_control[0]     = NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL);
2836         regp->debug_0[0]        = NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
2837
2838         if (pNv->twoHeads) {
2839                 regp->fp_control[1]     = NVReadRAMDAC(pNv, 1, NV_RAMDAC_FP_CONTROL);
2840                 regp->debug_0[1]        = NVReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
2841
2842                 regp->debug_1   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1);
2843                 regp->debug_2   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2);
2844
2845                 regp->unk_a20 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A20);
2846                 regp->unk_a24 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A24);
2847                 regp->unk_a34 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A34);
2848         }
2849
2850         if (pNv->NVArch == 0x11) {
2851                 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_DITHER_NV11);
2852         } else if (pNv->twoHeads) {
2853                 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DITHER);
2854                 for (i = 0; i < 3; i++) {
2855                         regp->dither_regs[i] = NVCrtcReadRAMDAC(crtc, 0x850 + i * 4);
2856                         regp->dither_regs[i + 3] = NVCrtcReadRAMDAC(crtc, 0x85c + i * 4);
2857                 }
2858         }
2859         if (pNv->Architecture >= NV_ARCH_10)
2860                 regp->nv10_cursync = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC);
2861
2862         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2863
2864         for (i = 0; i < 7; i++) {
2865                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2866                 regp->fp_horiz_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
2867         }
2868
2869         for (i = 0; i < 7; i++) {
2870                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2871                 regp->fp_vert_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
2872         }
2873
2874         regp->fp_hvalid_start = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_HVALID_START);
2875         regp->fp_hvalid_end = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_HVALID_END);
2876         regp->fp_vvalid_start = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_VVALID_START);
2877         regp->fp_vvalid_end = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_VVALID_END);
2878 }
2879
2880 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2881 {
2882         ScrnInfoPtr pScrn = crtc->scrn;
2883         NVPtr pNv = NVPTR(pScrn);
2884         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2885         NVCrtcRegPtr regp;
2886         int i;
2887
2888         regp = &state->crtc_reg[nv_crtc->head];
2889
2890         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL, regp->general);
2891
2892         if (pNv->fp_regs_owner[0] == nv_crtc->head) {
2893                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL, regp->fp_control[0]);
2894                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0, regp->debug_0[0]);
2895         }
2896         if (pNv->twoHeads) {
2897                 if (pNv->fp_regs_owner[1] == nv_crtc->head) {
2898                         NVWriteRAMDAC(pNv, 1, NV_RAMDAC_FP_CONTROL, regp->fp_control[1]);
2899                         NVWriteRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0, regp->debug_0[1]);
2900                 }
2901                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
2902                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
2903                 if (pNv->NVArch == 0x30) { /* For unknown purposes. */
2904                         uint32_t reg890 = NVCrtcReadRAMDAC(crtc, NV30_RAMDAC_890);
2905                         NVCrtcWriteRAMDAC(crtc, NV30_RAMDAC_89C, reg890);
2906                 }
2907
2908                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A20, regp->unk_a20);
2909                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A24, regp->unk_a24);
2910                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A34, regp->unk_a34);
2911         }
2912
2913         if (pNv->NVArch == 0x11) {
2914                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_DITHER_NV11, regp->dither);
2915         } else if (pNv->twoHeads) {
2916                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DITHER, regp->dither);
2917                 for (i = 0; i < 3; i++) {
2918                         NVCrtcWriteRAMDAC(crtc, 0x850 + i * 4, regp->dither_regs[i]);
2919                         NVCrtcWriteRAMDAC(crtc, 0x85c + i * 4, regp->dither_regs[i + 3]);
2920                 }
2921         }
2922         if (pNv->Architecture >= NV_ARCH_10)
2923                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
2924
2925         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2926
2927         for (i = 0; i < 7; i++) {
2928                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2929                 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_horiz_regs[i]);
2930         }
2931
2932         for (i = 0; i < 7; i++) {
2933                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2934                 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_vert_regs[i]);
2935         }
2936
2937         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_HVALID_START, regp->fp_hvalid_start);
2938         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_HVALID_END, regp->fp_hvalid_end);
2939         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_VVALID_START, regp->fp_vvalid_start);
2940         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_VVALID_END, regp->fp_vvalid_end);
2941 }
2942
2943 void
2944 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y, Bool bios_restore)
2945 {
2946         ScrnInfoPtr pScrn = crtc->scrn;
2947         NVPtr pNv = NVPTR(pScrn);
2948         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2949         NVFBLayout *pLayout = &pNv->CurrentLayout;
2950         uint32_t start = 0;
2951
2952         ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
2953
2954         if (bios_restore) {
2955                 start = pNv->console_mode[nv_crtc->head].fb_start;
2956         } else {
2957                 start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
2958                 if (crtc->rotatedData != NULL) { /* we do not exist on the real framebuffer */
2959 #if NOUVEAU_EXA_PIXMAPS
2960                         start = nv_crtc->shadow->offset;
2961 #else
2962                         start = pNv->FB->offset + nv_crtc->shadow->offset; /* We do exist relative to the framebuffer */
2963 #endif
2964                 } else {
2965                         start += pNv->FB->offset;
2966                 }
2967         }
2968
2969         /* 30 bits addresses in 32 bits according to haiku */
2970         NVCrtcWriteCRTC(crtc, NV_CRTC_START, start & 0xfffffffc);
2971
2972         /* set NV4/NV10 byte adress: (bit0 - 1) */
2973         NVWriteVgaAttr(crtc, 0x13, (start & 0x3) << 1);
2974
2975         crtc->x = x;
2976         crtc->y = y;
2977 }
2978
2979 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2980 {
2981         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2982         NVPtr pNv = NVPTR(crtc->scrn);
2983         volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2984         int i;
2985
2986         VGA_WR08(pDACReg, VGA_DAC_MASK, 0xff);
2987         VGA_WR08(pDACReg, VGA_DAC_READ_ADDR, 0x0);
2988
2989         for (i = 0; i < 768; i++) {
2990                 state->crtc_reg[nv_crtc->head].DAC[i] = NV_RD08(pDACReg, VGA_DAC_DATA);
2991                 DDXMMIOH("nv_crtc_save_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, NV_PDIO0_OFFSET + (nv_crtc->head ? NV_PDIO0_SIZE : 0) + VGA_DAC_DATA, state->crtc_reg[nv_crtc->head].DAC[i]);
2992         }
2993
2994         NVDisablePalette(crtc);
2995 }
2996 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2997 {
2998         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2999         NVPtr pNv = NVPTR(crtc->scrn);
3000         volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3001         int i;
3002
3003         VGA_WR08(pDACReg, VGA_DAC_MASK, 0xff);
3004         VGA_WR08(pDACReg, VGA_DAC_WRITE_ADDR, 0x0);
3005
3006         for (i = 0; i < 768; i++) {
3007                 DDXMMIOH("nv_crtc_load_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, NV_PDIO0_OFFSET + (nv_crtc->head ? NV_PDIO0_SIZE : 0) + VGA_DAC_DATA, state->crtc_reg[nv_crtc->head].DAC[i]);
3008                 NV_WR08(pDACReg, VGA_DAC_DATA, state->crtc_reg[nv_crtc->head].DAC[i]);
3009         }
3010
3011         NVDisablePalette(crtc);
3012 }
3013
3014 /* on = unblank */
3015 void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
3016 {
3017         NVPtr pNv = NVPTR(crtc->scrn);
3018         unsigned char scrn;
3019
3020         if (pNv->twoHeads)
3021                 NVCrtcSetOwner(crtc);
3022
3023         scrn = NVReadVgaSeq(crtc, 0x01);
3024         if (on) {
3025                 scrn &= ~0x20;
3026         } else {
3027                 scrn |= 0x20;
3028         }
3029
3030         NVVgaSeqReset(crtc, TRUE);
3031         NVWriteVgaSeq(crtc, 0x01, scrn);
3032         NVVgaSeqReset(crtc, FALSE);
3033 }
3034
3035 /* Reset a mode after a drastic output resource change for example. */
3036 void NVCrtcModeFix(xf86CrtcPtr crtc)
3037 {
3038         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3039         Bool need_unlock;
3040
3041         if (!crtc->enabled)
3042                 return;
3043
3044         if (!xf86ModesEqual(&crtc->mode, &crtc->desiredMode)) /* not currently in X */
3045                 return;
3046
3047         DisplayModePtr adjusted_mode = xf86DuplicateMode(&crtc->mode);
3048         uint8_t dpms_mode = nv_crtc->last_dpms;
3049
3050         /* Set the crtc mode again. */
3051         crtc->funcs->dpms(crtc, DPMSModeOff);
3052         need_unlock = crtc->funcs->lock(crtc);
3053         crtc->funcs->mode_fixup(crtc, &crtc->mode, adjusted_mode);
3054         crtc->funcs->prepare(crtc);
3055         crtc->funcs->mode_set(crtc, &crtc->mode, adjusted_mode, crtc->x, crtc->y);
3056         crtc->funcs->commit(crtc);
3057         if (need_unlock)
3058                 crtc->funcs->unlock(crtc);
3059         crtc->funcs->dpms(crtc, dpms_mode);
3060
3061         /* Free mode. */
3062         xfree(adjusted_mode);
3063 }
3064
3065 /*************************************************************************** \
3066 |*                                                                           *|
3067 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
3068 |*                                                                           *|
3069 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
3070 |*     international laws.  Users and possessors of this source code are     *|
3071 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
3072 |*     use this code in individual and commercial software.                  *|
3073 |*                                                                           *|
3074 |*     Any use of this source code must include,  in the user documenta-     *|
3075 |*     tion and  internal comments to the code,  notices to the end user     *|
3076 |*     as follows:                                                           *|
3077 |*                                                                           *|
3078 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
3079 |*                                                                           *|
3080 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
3081 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
3082 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
3083 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
3084 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
3085 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
3086 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
3087 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
3088 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
3089 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
3090 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
3091 |*                                                                           *|
3092 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
3093 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
3094 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
3095 |*     computer  software  documentation,"  as such  terms  are  used in     *|
3096 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
3097 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
3098 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
3099 |*     all U.S. Government End Users  acquire the source code  with only     *|
3100 |*     those rights set forth herein.                                        *|
3101 |*                                                                           *|
3102  \***************************************************************************/