git.oblomov.eu Git - nouveau/blob - src/riva_setup.c

   1 /*
   2  * Copyright 1996-1997  David J. McKay
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 /* Hacked together from mga driver and 3.3.4 NVIDIA driver by Jarno Paananen
  24    <jpaana@s2.org> */
  25
  26 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_setup.c $ */
  27
  28 #include "riva_include.h"
  29
  30 /*
  31  * Override VGA I/O routines.
  32  */
  33 static void RivaWriteCrtc(vgaHWPtr pVga, CARD8 index, CARD8 value)
  34 {
  35     RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
  36     VGA_WR08(pRiva->riva.PCIO, pVga->IOBase + VGA_CRTC_INDEX_OFFSET, index);
  37     VGA_WR08(pRiva->riva.PCIO, pVga->IOBase + VGA_CRTC_DATA_OFFSET,  value);
  38 }
  39 static CARD8 RivaReadCrtc(vgaHWPtr pVga, CARD8 index)
  40 {
  41     RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
  42     VGA_WR08(pRiva->riva.PCIO, pVga->IOBase + VGA_CRTC_INDEX_OFFSET, index);
  43     return (VGA_RD08(pRiva->riva.PCIO, pVga->IOBase + VGA_CRTC_DATA_OFFSET));
  44 }
  45 static void RivaWriteGr(vgaHWPtr pVga, CARD8 index, CARD8 value)
  46 {
  47     RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
  48     VGA_WR08(pRiva->riva.PVIO, VGA_GRAPH_INDEX, index);
  49     VGA_WR08(pRiva->riva.PVIO, VGA_GRAPH_DATA,  value);
  50 }
  51 static CARD8 RivaReadGr(vgaHWPtr pVga, CARD8 index)
  52 {
  53     RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
  54     VGA_WR08(pRiva->riva.PVIO, VGA_GRAPH_INDEX, index);
  55     return (VGA_RD08(pRiva->riva.PVIO, VGA_GRAPH_DATA));
  56 }
  57 static void RivaWriteSeq(vgaHWPtr pVga, CARD8 index, CARD8 value)
  58 {
  59     RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
  60     VGA_WR08(pRiva->riva.PVIO, VGA_SEQ_INDEX, index);
  61     VGA_WR08(pRiva->riva.PVIO, VGA_SEQ_DATA,  value);
  62 }
  63 static CARD8 RivaReadSeq(vgaHWPtr pVga, CARD8 index)
  64 {
  65     RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
  66     VGA_WR08(pRiva->riva.PVIO, VGA_SEQ_INDEX, index);
  67     return (VGA_RD08(pRiva->riva.PVIO, VGA_SEQ_DATA));
  68 }
  69 static void RivaWriteAttr(vgaHWPtr pVga, CARD8 index, CARD8 value)
  70 {
  71     RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
  72     volatile CARD8 tmp;
  73
  74     tmp = VGA_RD08(pRiva->riva.PCIO, pVga->IOBase + VGA_IN_STAT_1_OFFSET);
  75     if (pVga->paletteEnabled)
  76         index &= ~0x20;
  77     else
  78         index |= 0x20;
  79     VGA_WR08(pRiva->riva.PCIO, VGA_ATTR_INDEX,  index);
  80     VGA_WR08(pRiva->riva.PCIO, VGA_ATTR_DATA_W, value);
  81 }
  82 static CARD8 RivaReadAttr(vgaHWPtr pVga, CARD8 index)
  83 {
  84     RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
  85     volatile CARD8 tmp;
  86
  87     tmp = VGA_RD08(pRiva->riva.PCIO, pVga->IOBase + VGA_IN_STAT_1_OFFSET);
  88     if (pVga->paletteEnabled)
  89         index &= ~0x20;
  90     else
  91         index |= 0x20;
  92     VGA_WR08(pRiva->riva.PCIO, VGA_ATTR_INDEX, index);
  93     return (VGA_RD08(pRiva->riva.PCIO, VGA_ATTR_DATA_R));
  94 }
  95 static void RivaWriteMiscOut(vgaHWPtr pVga, CARD8 value)
  96 {
  97     RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
  98     VGA_WR08(pRiva->riva.PVIO, VGA_MISC_OUT_W, value);
  99 }
 100 static CARD8 RivaReadMiscOut(vgaHWPtr pVga)
 101 {
 102     RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
 103     return (VGA_RD08(pRiva->riva.PVIO, VGA_MISC_OUT_R));
 104 }
 105 static void RivaEnablePalette(vgaHWPtr pVga)
 106 {
 107     RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
 108     volatile CARD8 tmp;
 109
 110     tmp = VGA_RD08(pRiva->riva.PCIO, pVga->IOBase + VGA_IN_STAT_1_OFFSET);
 111     VGA_WR08(pRiva->riva.PCIO, VGA_ATTR_INDEX, 0x00);
 112     pVga->paletteEnabled = TRUE;
 113 }
 114 static void RivaDisablePalette(vgaHWPtr pVga)
 115 {
 116     RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
 117     volatile CARD8 tmp;
 118
 119     tmp = VGA_RD08(pRiva->riva.PCIO, pVga->IOBase + VGA_IN_STAT_1_OFFSET);
 120     VGA_WR08(pRiva->riva.PCIO, VGA_ATTR_INDEX, 0x20);
 121     pVga->paletteEnabled = FALSE;
 122 }
 123 static void RivaWriteDacMask(vgaHWPtr pVga, CARD8 value)
 124 {
 125     RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
 126     VGA_WR08(pRiva->riva.PDIO, VGA_DAC_MASK, value);
 127 }
 128 static CARD8 RivaReadDacMask(vgaHWPtr pVga)
 129 {
 130     RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
 131     return (VGA_RD08(pRiva->riva.PDIO, VGA_DAC_MASK));
 132 }
 133 static void RivaWriteDacReadAddr(vgaHWPtr pVga, CARD8 value)
 134 {
 135     RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
 136     VGA_WR08(pRiva->riva.PDIO, VGA_DAC_READ_ADDR, value);
 137 }
 138 static void RivaWriteDacWriteAddr(vgaHWPtr pVga, CARD8 value)
 139 {
 140     RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
 141     VGA_WR08(pRiva->riva.PDIO, VGA_DAC_WRITE_ADDR, value);
 142 }
 143 static void RivaWriteDacData(vgaHWPtr pVga, CARD8 value)
 144 {
 145     RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
 146     VGA_WR08(pRiva->riva.PDIO, VGA_DAC_DATA, value);
 147 }
 148 static CARD8 RivaReadDacData(vgaHWPtr pVga)
 149 {
 150     RivaPtr pRiva = (RivaPtr)pVga->MMIOBase;
 151     return (VGA_RD08(pRiva->riva.PDIO, VGA_DAC_DATA));
 152 }
 153
 154
 155
 156 static xf86MonPtr
 157 RivaProbeDDC (ScrnInfoPtr pScrn)
 158 {
 159     RivaPtr pRiva = RivaPTR(pScrn);
 160     xf86MonPtr MonInfo = NULL;
 161
 162     if(!pRiva->I2C) return NULL;
 163
 164     pRiva->DDCBase = 0x3e;
 165
 166     xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Probing for EDID...\n");
 167
 168     if ((MonInfo = xf86DoEDID_DDC2(pScrn->scrnIndex, pRiva->I2C))) {
 169        xf86DrvMsg(pScrn->scrnIndex, X_INFO,
 170                   "  ... found one\n");
 171        xf86PrintEDID( MonInfo );
 172     } else {
 173        xf86DrvMsg(pScrn->scrnIndex, X_INFO,
 174                   "  ... none found\n");
 175     }
 176
 177     return MonInfo;
 178 }
 179
 180 void
 181 Riva3Setup(ScrnInfoPtr pScrn)
 182 {
 183     RivaPtr pRiva = RivaPTR(pScrn);
 184     vgaHWPtr pVga = VGAHWPTR(pScrn);
 185     CARD32 regBase = pRiva->IOAddress;
 186     CARD32 frameBase = pRiva->FbAddress;
 187     xf86MonPtr monitor;
 188     int mmioFlags;
 189
 190     pRiva->Save = RivaDACSave;
 191     pRiva->Restore = RivaDACRestore;
 192     pRiva->ModeInit = RivaDACInit;
 193
 194     pRiva->Dac.LoadPalette = RivaDACLoadPalette;
 195
 196     /*
 197      * Override VGA I/O routines.
 198      */
 199     pVga->writeCrtc         = RivaWriteCrtc;
 200     pVga->readCrtc          = RivaReadCrtc;
 201     pVga->writeGr           = RivaWriteGr;
 202     pVga->readGr            = RivaReadGr;
 203     pVga->writeAttr         = RivaWriteAttr;
 204     pVga->readAttr          = RivaReadAttr;
 205     pVga->writeSeq          = RivaWriteSeq;
 206     pVga->readSeq           = RivaReadSeq;
 207     pVga->writeMiscOut      = RivaWriteMiscOut;
 208     pVga->readMiscOut       = RivaReadMiscOut;
 209     pVga->enablePalette     = RivaEnablePalette;
 210     pVga->disablePalette    = RivaDisablePalette;
 211     pVga->writeDacMask      = RivaWriteDacMask;
 212     pVga->readDacMask       = RivaReadDacMask;
 213     pVga->writeDacWriteAddr = RivaWriteDacWriteAddr;
 214     pVga->writeDacReadAddr  = RivaWriteDacReadAddr;
 215     pVga->writeDacData      = RivaWriteDacData;
 216     pVga->readDacData       = RivaReadDacData;
 217     /*
 218      * Note: There are different pointers to the CRTC/AR and GR/SEQ registers.
 219      * Bastardize the intended uses of these to make it work.
 220      */
 221     pVga->MMIOBase   = (CARD8 *)pRiva;
 222     pVga->MMIOOffset = 0;
 223
 224     /*
 225      * No IRQ in use.
 226      */
 227     pRiva->riva.EnableIRQ = 0;
 228     pRiva->riva.IO      = VGA_IOBASE_COLOR;
 229
 230     mmioFlags = VIDMEM_MMIO | VIDMEM_READSIDEEFFECT;
 231
 232     pRiva->riva.PRAMDAC = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pRiva->PciTag,
 233                                       regBase+0x00680000, 0x00003000);
 234     pRiva->riva.PFB     = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pRiva->PciTag,
 235                                       regBase+0x00100000, 0x00001000);
 236     pRiva->riva.PFIFO   = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pRiva->PciTag,
 237                                       regBase+0x00002000, 0x00002000);
 238     pRiva->riva.PGRAPH  = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pRiva->PciTag,
 239                                       regBase+0x00400000, 0x00002000);
 240     pRiva->riva.PEXTDEV = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pRiva->PciTag,
 241                                       regBase+0x00101000, 0x00001000);
 242     pRiva->riva.PTIMER  = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pRiva->PciTag,
 243                                       regBase+0x00009000, 0x00001000);
 244     pRiva->riva.PMC     = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pRiva->PciTag,
 245                                       regBase+0x00000000, 0x00009000);
 246     pRiva->riva.FIFO    = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pRiva->PciTag,
 247                                       regBase+0x00800000, 0x00010000);
 248     pRiva->riva.PRAMIN = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pRiva->PciTag,
 249                                      frameBase+0x00C00000, 0x00008000);
 250
 251     /*
 252      * These registers are read/write as 8 bit values.  Probably have to map
 253      * sparse on alpha.
 254      */
 255     pRiva->riva.PCIO = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
 256                                            pRiva->PciTag, regBase+0x00601000,
 257                                            0x00003000);
 258     pRiva->riva.PDIO = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
 259                                            pRiva->PciTag, regBase+0x00681000,
 260                                            0x00003000);
 261     pRiva->riva.PVIO = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
 262                                            pRiva->PciTag, regBase+0x000C0000,
 263                                            0x00001000);
 264
 265     pRiva->riva.PCRTC = pRiva->riva.PGRAPH;
 266
 267     RivaGetConfig(pRiva);
 268
 269     pRiva->riva.LockUnlock(&pRiva->riva, 0);
 270
 271     RivaI2CInit(pScrn);
 272
 273     monitor = RivaProbeDDC(pScrn);
 274
 275     if(monitor)
 276       xf86SetDDCproperties(pScrn, monitor);
 277
 278     pRiva->Dac.maxPixelClock = pRiva->riva.MaxVClockFreqKHz;
 279 }