git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 2006 Dave Airlie
   3  * Copyright 2007 Maarten Maathuis
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
  26  * decleration is at the bottom of this file as it is rather ugly
  27  */
  28
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include <assert.h>
  34 #include "xf86.h"
  35 #include "os.h"
  36 #include "mibank.h"
  37 #include "globals.h"
  38 #include "xf86.h"
  39 #include "xf86Priv.h"
  40 #include "xf86DDC.h"
  41 #include "mipointer.h"
  42 #include "windowstr.h"
  43 #include <randrstr.h>
  44 #include <X11/extensions/render.h>
  45
  46 #include "xf86Crtc.h"
  47 #include "nv_include.h"
  48
  49 #include "vgaHW.h"
  50
  51 #define CRTC_INDEX 0x3d4
  52 #define CRTC_DATA 0x3d5
  53 #define CRTC_IN_STAT_1 0x3da
  54
  55 #define WHITE_VALUE 0x3F
  56 #define BLACK_VALUE 0x00
  57 #define OVERSCAN_VALUE 0x01
  58
  59 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  60 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  61 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  62 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  63
  64 static CARD8 NVReadPVIO(xf86CrtcPtr crtc, CARD32 address)
  65 {
  66         ScrnInfoPtr pScrn = crtc->scrn;
  67         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  68         NVPtr pNv = NVPTR(pScrn);
  69
  70         /* Only NV4x have two pvio ranges */
  71         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  72                 return NV_RD08(pNv->PVIO1, address);
  73         } else {
  74                 return NV_RD08(pNv->PVIO0, address);
  75         }
  76 }
  77
  78 static void NVWritePVIO(xf86CrtcPtr crtc, CARD32 address, CARD8 value)
  79 {
  80         ScrnInfoPtr pScrn = crtc->scrn;
  81         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  82         NVPtr pNv = NVPTR(pScrn);
  83
  84         /* Only NV4x have two pvio ranges */
  85         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  86                 NV_WR08(pNv->PVIO1, address, value);
  87         } else {
  88                 NV_WR08(pNv->PVIO0, address, value);
  89         }
  90 }
  91
  92 static void NVWriteMiscOut(xf86CrtcPtr crtc, CARD8 value)
  93 {
  94         NVWritePVIO(crtc, VGA_MISC_OUT_W, value);
  95 }
  96
  97 static CARD8 NVReadMiscOut(xf86CrtcPtr crtc)
  98 {
  99         return NVReadPVIO(crtc, VGA_MISC_OUT_R);
 100 }
 101
 102 void NVWriteVGA(NVPtr pNv, int head, CARD8 index, CARD8 value)
 103 {
 104         volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 105
 106         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 107         NV_WR08(pCRTCReg, CRTC_DATA, value);
 108 }
 109
 110 CARD8 NVReadVGA(NVPtr pNv, int head, CARD8 index)
 111 {
 112         volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 113
 114         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 115         return NV_RD08(pCRTCReg, CRTC_DATA);
 116 }
 117
 118 void NVWriteVgaCrtc(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 119 {
 120         ScrnInfoPtr pScrn = crtc->scrn;
 121         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 122         NVPtr pNv = NVPTR(pScrn);
 123
 124         NVWriteVGA(pNv, nv_crtc->head, index, value);
 125 }
 126
 127 CARD8 NVReadVgaCrtc(xf86CrtcPtr crtc, CARD8 index)
 128 {
 129         ScrnInfoPtr pScrn = crtc->scrn;
 130         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 131         NVPtr pNv = NVPTR(pScrn);
 132
 133         return NVReadVGA(pNv, nv_crtc->head, index);
 134 }
 135
 136 static void NVWriteVgaSeq(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 137 {
 138         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 139         NVWritePVIO(crtc, VGA_SEQ_DATA, value);
 140 }
 141
 142 static CARD8 NVReadVgaSeq(xf86CrtcPtr crtc, CARD8 index)
 143 {
 144         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 145         return NVReadPVIO(crtc, VGA_SEQ_DATA);
 146 }
 147
 148 static void NVWriteVgaGr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 149 {
 150         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 151         NVWritePVIO(crtc, VGA_GRAPH_DATA, value);
 152 }
 153
 154 static CARD8 NVReadVgaGr(xf86CrtcPtr crtc, CARD8 index)
 155 {
 156         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 157         return NVReadPVIO(crtc, VGA_GRAPH_DATA);
 158 }
 159
 160
 161 static void NVWriteVgaAttr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 162 {
 163   ScrnInfoPtr pScrn = crtc->scrn;
 164   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 165   NVPtr pNv = NVPTR(pScrn);
 166   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 167
 168   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 169   if (nv_crtc->paletteEnabled)
 170     index &= ~0x20;
 171   else
 172     index |= 0x20;
 173   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 174   NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
 175 }
 176
 177 static CARD8 NVReadVgaAttr(xf86CrtcPtr crtc, CARD8 index)
 178 {
 179   ScrnInfoPtr pScrn = crtc->scrn;
 180   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 181   NVPtr pNv = NVPTR(pScrn);
 182   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 183
 184   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 185   if (nv_crtc->paletteEnabled)
 186     index &= ~0x20;
 187   else
 188     index |= 0x20;
 189   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 190   return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
 191 }
 192
 193 void NVCrtcSetOwner(xf86CrtcPtr crtc)
 194 {
 195         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 196         ScrnInfoPtr pScrn = crtc->scrn;
 197         NVPtr pNv = NVPTR(pScrn);
 198         /* Non standard beheaviour required by NV11 */
 199         if (pNv) {
 200                 uint8_t owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 201                 ErrorF("pre-Owner: 0x%X\n", owner);
 202                 if (owner == 0x04) {
 203                         uint32_t pbus84 = nvReadMC(pNv, 0x1084);
 204                         ErrorF("pbus84: 0x%X\n", pbus84);
 205                         pbus84 &= ~(1<<28);
 206                         ErrorF("pbus84: 0x%X\n", pbus84);
 207                         nvWriteMC(pNv, 0x1084, pbus84);
 208                 }
 209                 /* The blob never writes owner to pcio1, so should we */
 210                 if (pNv->NVArch == 0x11) {
 211                         NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, 0xff);
 212                 }
 213                 NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, nv_crtc->crtc * 0x3);
 214                 owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 215                 ErrorF("post-Owner: 0x%X\n", owner);
 216         } else {
 217                 ErrorF("pNv pointer is NULL\n");
 218         }
 219 }
 220
 221 static void
 222 NVEnablePalette(xf86CrtcPtr crtc)
 223 {
 224   ScrnInfoPtr pScrn = crtc->scrn;
 225   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 226   NVPtr pNv = NVPTR(pScrn);
 227   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 228
 229   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 230   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
 231   nv_crtc->paletteEnabled = TRUE;
 232 }
 233
 234 static void
 235 NVDisablePalette(xf86CrtcPtr crtc)
 236 {
 237   ScrnInfoPtr pScrn = crtc->scrn;
 238   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 239   NVPtr pNv = NVPTR(pScrn);
 240   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 241
 242   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 243   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
 244   nv_crtc->paletteEnabled = FALSE;
 245 }
 246
 247 static void NVWriteVgaReg(xf86CrtcPtr crtc, CARD32 reg, CARD8 value)
 248 {
 249  ScrnInfoPtr pScrn = crtc->scrn;
 250   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 251   NVPtr pNv = NVPTR(pScrn);
 252   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 253
 254   NV_WR08(pCRTCReg, reg, value);
 255 }
 256
 257 /* perform a sequencer reset */
 258 static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
 259 {
 260   if (start)
 261     NVWriteVgaSeq(crtc, 0x00, 0x1);
 262   else
 263     NVWriteVgaSeq(crtc, 0x00, 0x3);
 264
 265 }
 266 static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
 267 {
 268         CARD8 tmp;
 269
 270         if (on) {
 271                 tmp = NVReadVgaSeq(crtc, 0x1);
 272                 NVVgaSeqReset(crtc, TRUE);
 273                 NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
 274
 275                 NVEnablePalette(crtc);
 276         } else {
 277                 /*
 278                  * Reenable sequencer, then turn on screen.
 279                  */
 280                 tmp = NVReadVgaSeq(crtc, 0x1);
 281                 NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20); /* reenable display */
 282                 NVVgaSeqReset(crtc, FALSE);
 283
 284                 NVDisablePalette(crtc);
 285         }
 286 }
 287
 288 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool Lock)
 289 {
 290         CARD8 cr11;
 291
 292         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57);
 293         cr11 = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE);
 294         if (Lock) cr11 |= 0x80;
 295         else cr11 &= ~0x80;
 296         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE, cr11);
 297 }
 298
 299 xf86OutputPtr
 300 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
 301 {
 302         ScrnInfoPtr pScrn = crtc->scrn;
 303         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 304         int i;
 305         for (i = 0; i < xf86_config->num_output; i++) {
 306                 xf86OutputPtr output = xf86_config->output[i];
 307
 308                 if (output->crtc == crtc) {
 309                         return output;
 310                 }
 311         }
 312
 313         return NULL;
 314 }
 315
 316 xf86CrtcPtr
 317 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
 318 {
 319         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 320         int i;
 321
 322         for (i = 0; i < xf86_config->num_crtc; i++) {
 323                 xf86CrtcPtr crtc = xf86_config->crtc[i];
 324                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 325                 if (nv_crtc->crtc == index)
 326                         return crtc;
 327         }
 328
 329         return NULL;
 330 }
 331
 332 /*
 333  * Calculate the Video Clock parameters for the PLL.
 334  */
 335 static void CalcVClock (
 336         uint32_t                clockIn,
 337         uint32_t                *clockOut,
 338         CARD32          *pllOut,
 339         NVPtr           pNv
 340 )
 341 {
 342         unsigned lowM, highM, highP;
 343         unsigned DeltaNew, DeltaOld;
 344         unsigned VClk, Freq;
 345         unsigned M, N, P;
 346
 347         /* M: PLL reference frequency postscaler divider */
 348         /* P: PLL VCO output postscaler divider */
 349         /* N: PLL VCO postscaler setting */
 350
 351         DeltaOld = 0xFFFFFFFF;
 352
 353         VClk = (unsigned)clockIn;
 354
 355         /* Taken from Haiku, after someone with an NV28 had an issue */
 356         switch(pNv->NVArch) {
 357                 case 0x28:
 358                         lowM = 1;
 359                         highP = 32;
 360                         if (VClk > 340000) {
 361                                 highM = 2;
 362                         } else if (VClk > 200000) {
 363                                 highM = 4;
 364                         } else if (VClk > 150000) {
 365                                 highM = 6;
 366                         } else {
 367                                 highM = 14;
 368                         }
 369                         break;
 370                 default:
 371                         lowM = 1;
 372                         highP = 16;
 373                         if (VClk > 340000) {
 374                                 highM = 2;
 375                         } else if (VClk > 250000) {
 376                                 highM = 6;
 377                         } else {
 378                                 highM = 14;
 379                         }
 380                         break;
 381         }
 382
 383         for (P = 1; P <= highP; P++) {
 384                 Freq = VClk << P;
 385                 if ((Freq >= 128000) && (Freq <= 350000)) {
 386                         for (M = lowM; M <= highM; M++) {
 387                                 N = ((VClk << P) * M) / pNv->CrystalFreqKHz;
 388                                 if (N <= 255) {
 389                                         Freq = ((pNv->CrystalFreqKHz * N) / M) >> P;
 390                                         if (Freq > VClk) {
 391                                                 DeltaNew = Freq - VClk;
 392                                         } else {
 393                                                 DeltaNew = VClk - Freq;
 394                                         }
 395                                         if (DeltaNew < DeltaOld) {
 396                                                 *pllOut   = (P << 16) | (N << 8) | M;
 397                                                 *clockOut = Freq;
 398                                                 DeltaOld  = DeltaNew;
 399                                         }
 400                                 }
 401                         }
 402                 }
 403         }
 404 }
 405
 406 static void CalcVClock2Stage (
 407         uint32_t                clockIn,
 408         uint32_t                *clockOut,
 409         CARD32          *pllOut,
 410         CARD32          *pllBOut,
 411         NVPtr           pNv
 412 )
 413 {
 414         unsigned DeltaNew, DeltaOld;
 415         unsigned VClk, Freq;
 416         unsigned M, N, P;
 417         unsigned lowM, highM, highP;
 418
 419         DeltaOld = 0xFFFFFFFF;
 420
 421         *pllBOut = 0x80000401;  /* fixed at x4 for now */
 422
 423         VClk = (unsigned)clockIn;
 424
 425         /* Taken from Haiku, after someone with an NV28 had an issue */
 426         switch(pNv->NVArch) {
 427                 case 0x28:
 428                         lowM = 1;
 429                         highP = 32;
 430                         if (VClk > 340000) {
 431                                 highM = 2;
 432                         } else if (VClk > 200000) {
 433                                 highM = 4;
 434                         } else if (VClk > 150000) {
 435                                 highM = 6;
 436                         } else {
 437                                 highM = 14;
 438                         }
 439                         break;
 440                 default:
 441                         lowM = 1;
 442                         highP = 15;
 443                         if (VClk > 340000) {
 444                                 highM = 2;
 445                         } else if (VClk > 250000) {
 446                                 highM = 6;
 447                         } else {
 448                                 highM = 14;
 449                         }
 450                         break;
 451         }
 452
 453         for (P = 0; P <= highP; P++) {
 454                 Freq = VClk << P;
 455                 if ((Freq >= 400000) && (Freq <= 1000000)) {
 456                         for (M = lowM; M <= highM; M++) {
 457                                 N = ((VClk << P) * M) / (pNv->CrystalFreqKHz << 2);
 458                                 if ((N >= 5) && (N <= 255)) {
 459                                         Freq = (((pNv->CrystalFreqKHz << 2) * N) / M) >> P;
 460                                         if (Freq > VClk) {
 461                                                 DeltaNew = Freq - VClk;
 462                                         } else {
 463                                                 DeltaNew = VClk - Freq;
 464                                         }
 465                                         if (DeltaNew < DeltaOld) {
 466                                                 *pllOut   = (P << 16) | (N << 8) | M;
 467                                                 *clockOut = Freq;
 468                                                 DeltaOld  = DeltaNew;
 469                                         }
 470                                 }
 471                         }
 472                 }
 473         }
 474 }
 475
 476 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
 477 /* They are only valid for NV4x, appearantly reordered for NV5x */
 478 /* gpu pll: 0x4000 + 0x4004
 479  * unknown pll: 0x4008 + 0x400c
 480  * vpll1: 0x4010 + 0x4014
 481  * vpll2: 0x4018 + 0x401c
 482  * unknown pll: 0x4020 + 0x4024
 483  * unknown pll: 0x4038 + 0x403c
 484  * Some of the unknown's are probably memory pll's.
 485  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
 486  * 1 and 2 refer to the registers of each pair. There is only one post divider.
 487  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
 488  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
 489  *     bit8: A switch that turns of the second divider and multiplier off.
 490  *     bit12: Also a switch, i haven't seen it yet.
 491  *     bit16-19: p-divider
 492  *     but 28-31: Something related to the mode that is used (see bit8).
 493  * 2) bit0-7: m-divider (a)
 494  *     bit8-15: n-multiplier (a)
 495  *     bit16-23: m-divider (b)
 496  *     bit24-31: n-multiplier (b)
 497  */
 498
 499 /* Modifying the gpu pll for example requires:
 500  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 501  * This is not needed for the vpll's which have their own bits.
 502  */
 503
 504 static void
 505 CalculateVClkNV4x(
 506         NVPtr pNv,
 507         uint32_t requested_clock,
 508         uint32_t *given_clock,
 509         uint32_t *pll_a,
 510         uint32_t *pll_b,
 511         Bool    *db1_ratio
 512 )
 513 {
 514         uint32_t DeltaOld, DeltaNew;
 515         uint32_t freq;
 516         /* We have 2 mulitpliers, 2 dividers and one post divider */
 517         /* Note that p is only 4 bits */
 518         uint8_t m1, m2, n1, n2, p;
 519         uint8_t m1_best = 0, m2_best = 0, n1_best = 0, n2_best = 0, p_best = 0;
 520
 521         DeltaOld = 0xFFFFFFFF;
 522
 523         /* Only unset the needed stuff */
 524         *pll_a &= ~((0xf << 28) | (0xf << 16) | (1 << 8) | (1 << 12));
 525         /* This only contains the m multipliers and n dividers */
 526         *pll_b = 0;
 527
 528         if (pNv->misc_info.prefer_db1) {
 529                 *db1_ratio = TRUE;
 530                 /* Turn the second set of divider and multiplier off */
 531                 *pll_a |= (1 << 8);
 532                 *pll_a |= (0x8 << 28);
 533                 /* Neutral settings */
 534                 n2 = 1;
 535                 m2 = 1;
 536         } else {
 537                 *db1_ratio = FALSE;
 538                 *pll_a |= (0xc << 28);
 539                 /* Fixed at x4 for the moment */
 540                 n2 = 4;
 541                 m2 = 1;
 542         }
 543
 544         n2_best = n2;
 545         m2_best = m2;
 546
 547         /* Sticking to the limits of nv, maybe convert the other functions back as well? */
 548         for (p = 0; p < 6; p++) {
 549                 freq = requested_clock << p;
 550                 /* We must restrict the frequency before the post divider somewhat */
 551                 if (freq > 400000 && freq < 1000000) {
 552                         /* We have 8 bits for each multiplier */
 553                         for (m1 = 1; m1 < 14; m1++) {
 554                                 n1 = ((requested_clock << p) * m1 * m2)/(pNv->CrystalFreqKHz * n2);
 555                                 if (n1 > 5 && n1 < 255) {
 556                                         freq = ((pNv->CrystalFreqKHz * n1 * n2)/(m1 * m2)) >> p;
 557                                         if (freq > requested_clock) {
 558                                                 DeltaNew = freq - requested_clock;
 559                                         } else {
 560                                                 DeltaNew = requested_clock - freq;
 561                                         }
 562                                         if (DeltaNew < DeltaOld) {
 563                                                 m1_best = m1;
 564                                                 n1_best = n1;
 565                                                 p_best = p;
 566                                                 DeltaOld = DeltaNew;
 567                                         }
 568                                 }
 569                         }
 570                 }
 571         }
 572
 573         if (pNv->misc_info.prefer_db1) {
 574                 /* Bogus data, the same nvidia uses */
 575                 n2_best = 1;
 576                 m2_best = 31;
 577         }
 578
 579         *pll_a |= (p_best << 16);
 580         *pll_b |= ((n2_best << 24) | (m2_best << 16) | (n1_best << 8) | (m1_best << 0));
 581
 582         ErrorF("vpll: n1 %d n2 %d m1 %d m2 %d p %d db1_ratio %d\n", n1_best, n2_best, m1_best, m2_best, p_best, *db1_ratio);
 583 }
 584
 585 static void nv40_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 586 {
 587         state->vpll1_a = nvReadMC(pNv, NV40_VCLK1_A);
 588         state->vpll1_b = nvReadMC(pNv, NV40_VCLK1_B);
 589         state->vpll2_a = nvReadMC(pNv, NV40_VCLK2_A);
 590         state->vpll2_b = nvReadMC(pNv, NV40_VCLK2_B);
 591         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 592         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 593 }
 594
 595 static void nv40_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 596 {
 597         CARD32 fp_debug_0[2];
 598         uint32_t index[2];
 599         fp_debug_0[0] = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
 600         fp_debug_0[1] = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
 601
 602         /* The TMDS_PLL switch is on the actual ramdac */
 603         if (state->crosswired) {
 604                 index[0] = 1;
 605                 index[1] = 0;
 606                 ErrorF("Crosswired pll state load\n");
 607         } else {
 608                 index[0] = 0;
 609                 index[1] = 1;
 610         }
 611
 612         if (state->vpll2_b) {
 613                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0,
 614                         fp_debug_0[index[1]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 615
 616                 /* Wait for the situation to stabilise */
 617                 usleep(5000);
 618
 619                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 620                 /* for vpll2 change bits 18 and 19 are disabled */
 621                 reg_c040 &= ~(0x3 << 18);
 622                 nvWriteMC(pNv, 0xc040, reg_c040);
 623
 624                 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 625                 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 626
 627                 nvWriteMC(pNv, NV40_VCLK2_A, state->vpll2_a);
 628                 nvWriteMC(pNv, NV40_VCLK2_B, state->vpll2_b);
 629
 630                 /* We need to wait a while */
 631                 usleep(5000);
 632                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 633
 634                 ErrorF("writing pllsel %08X\n", state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 635                 /* Let's keep the primary vpll off */
 636                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 637
 638                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[1]]);
 639
 640                 /* Wait for the situation to stabilise */
 641                 usleep(5000);
 642         }
 643
 644         if (state->vpll1_b) {
 645                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0,
 646                         fp_debug_0[index[0]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 647
 648                 /* Wait for the situation to stabilise */
 649                 usleep(5000);
 650
 651                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 652                 /* for vpll2 change bits 16 and 17 are disabled */
 653                 reg_c040 &= ~(0x3 << 16);
 654                 nvWriteMC(pNv, 0xc040, reg_c040);
 655
 656                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 657                 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 658
 659                 nvWriteMC(pNv, NV40_VCLK1_A, state->vpll1_a);
 660                 nvWriteMC(pNv, NV40_VCLK1_B, state->vpll1_b);
 661
 662                 /* We need to wait a while */
 663                 usleep(5000);
 664                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 665
 666                 ErrorF("writing pllsel %08X\n", state->pllsel);
 667                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 668
 669                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[0]]);
 670
 671                 /* Wait for the situation to stabilise */
 672                 usleep(5000);
 673         }
 674
 675         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 676         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 677 }
 678
 679 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 680 {
 681         state->vpll = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 682         if(pNv->twoHeads) {
 683                 state->vpll2 = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 684         }
 685         if(pNv->twoStagePLL) {
 686                 state->vpllB = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 687                 state->vpll2B = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 688         }
 689         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 690         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 691 }
 692
 693
 694 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 695 {
 696         if (state->vpll2) {
 697                 if(pNv->twoHeads) {
 698                         ErrorF("writing vpll2 %08X\n", state->vpll2);
 699                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2);
 700                 }
 701                 if(pNv->twoStagePLL) {
 702                         ErrorF("writing vpll2B %08X\n", state->vpll2B);
 703                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2B);
 704                 }
 705
 706                 ErrorF("writing pllsel %08X\n", state->pllsel);
 707                 /* Let's keep the primary vpll off */
 708                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 709         }
 710
 711         if (state->vpll) {
 712                 ErrorF("writing vpll %08X\n", state->vpll);
 713                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll);
 714                 if(pNv->twoStagePLL) {
 715                         ErrorF("writing vpllB %08X\n", state->vpllB);
 716                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpllB);
 717                 }
 718
 719                 ErrorF("writing pllsel %08X\n", state->pllsel);
 720                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 721         }
 722
 723         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 724         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 725 }
 726
 727 /*
 728  * Calculate extended mode parameters (SVGA) and save in a
 729  * mode state structure.
 730  */
 731 void nv_crtc_calc_state_ext(
 732         xf86CrtcPtr     crtc,
 733         int                     bpp,
 734         int                     DisplayWidth, /* Does this change after setting the mode? */
 735         int                     CrtcHDisplay,
 736         int                     CrtcVDisplay,
 737         int                     dotClock,
 738         int                     flags
 739 )
 740 {
 741         ScrnInfoPtr pScrn = crtc->scrn;
 742         uint32_t pixelDepth, VClk = 0;
 743         CARD32 CursorStart;
 744         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 745         xf86CrtcConfigPtr   xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 746         NVCrtcRegPtr regp;
 747         NVPtr pNv = NVPTR(pScrn);
 748         RIVA_HW_STATE *state;
 749         int num_crtc_enabled, i;
 750
 751         state = &pNv->ModeReg;
 752
 753         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 754
 755         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 756         NVOutputPrivatePtr nv_output = output->driver_private;
 757
 758         /*
 759          * Extended RIVA registers.
 760          */
 761         pixelDepth = (bpp + 1)/8;
 762         if (pNv->Architecture == NV_ARCH_40) {
 763                 if (nv_crtc->head == 1) {
 764                         /* Read our clocks if haven't got any yet */
 765                         if (!state->vpll2_b) {
 766                                 state->vpll2_a = nvReadMC(pNv, NV40_VCLK2_A);
 767                                 state->vpll2_b = nvReadMC(pNv, NV40_VCLK2_B);
 768                         }
 769                         CalculateVClkNV4x(pNv, dotClock, &VClk, &state->vpll2_a, &state->vpll2_b, &state->db1_ratio[1]);
 770                 } else {
 771                         /* Read our clocks if haven't got any yet */
 772                         if (!state->vpll1_b) {
 773                                 state->vpll1_a = nvReadMC(pNv, NV40_VCLK1_A);
 774                                 state->vpll1_b = nvReadMC(pNv, NV40_VCLK1_B);
 775                         }
 776                         CalculateVClkNV4x(pNv, dotClock, &VClk, &state->vpll1_a, &state->vpll1_b, &state->db1_ratio[0]);
 777                 }
 778         } else if (pNv->twoStagePLL) {
 779                 CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB, pNv);
 780         } else {
 781                 CalcVClock(dotClock, &VClk, &state->pll, pNv);
 782         }
 783
 784         switch (pNv->Architecture) {
 785         case NV_ARCH_04:
 786                 nv4UpdateArbitrationSettings(VClk,
 787                                                 pixelDepth * 8,
 788                                                 &(state->arbitration0),
 789                                                 &(state->arbitration1),
 790                                                 pNv);
 791                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
 792                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
 793                 if (flags & V_DBLSCAN)
 794                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 795                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
 796                 state->pllsel   |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
 797                 state->config   = 0x00001114;
 798                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 799                 break;
 800         case NV_ARCH_10:
 801         case NV_ARCH_20:
 802         case NV_ARCH_30:
 803         default:
 804                 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
 805                         ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
 806                         state->arbitration0 = 128;
 807                         state->arbitration1 = 0x0480;
 808                 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
 809                         ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
 810                         nForceUpdateArbitrationSettings(VClk,
 811                                                 pixelDepth * 8,
 812                                                 &(state->arbitration0),
 813                                                 &(state->arbitration1),
 814                                                 pNv);
 815                 } else if (pNv->Architecture < NV_ARCH_30) {
 816                         nv10UpdateArbitrationSettings(VClk,
 817                                                 pixelDepth * 8,
 818                                                 &(state->arbitration0),
 819                                                 &(state->arbitration1),
 820                                                 pNv);
 821                 } else {
 822                         nv30UpdateArbitrationSettings(pNv,
 823                                                 &(state->arbitration0),
 824                                                 &(state->arbitration1));
 825                 }
 826
 827                 CursorStart = pNv->Cursor->offset;
 828
 829                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
 830                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
 831                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
 832
 833                 if (flags & V_DBLSCAN)
 834                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 835
 836                 state->config   = nvReadFB(pNv, NV_PFB_CFG0);
 837                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 838                 break;
 839         }
 840
 841         /* okay do we have 2 CRTCs running ? */
 842         num_crtc_enabled = 0;
 843         for (i = 0; i < xf86_config->num_crtc; i++) {
 844                 if (xf86_config->crtc[i]->enabled) {
 845                         num_crtc_enabled++;
 846                 }
 847         }
 848
 849         ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
 850
 851         if (pNv->Architecture < NV_ARCH_40) {
 852                 /* We need this before the next code */
 853                 if (nv_crtc->crtc == 1) {
 854                         state->vpll2 = state->pll;
 855                         state->vpll2B = state->pllB;
 856                 } else {
 857                         state->vpll = state->pll;
 858                         state->vpllB = state->pllB;
 859                 }
 860         }
 861
 862         if (pNv->Architecture == NV_ARCH_40) {
 863                 /* This register is only used on the primary ramdac */
 864                 /* This seems to be needed to select the proper clocks, otherwise bad things happen */
 865                 /* Assumption CRTC1 will overwrite the CRTC0 value */
 866                 /* Also make sure we don't set both bits */
 867                 state->sel_clk = (pNv->misc_info.sel_clk & ~(0xf << 16)) | (1 << 18);
 868                 /* Are we a TMDS running on head 0(=ramdac 0), but native to ramdac 1? */
 869                 if (nv_crtc->head == 0 && nv_output->type == OUTPUT_TMDS && nv_output->valid_ramdac & RAMDAC_1) {
 870                         state->sel_clk = (pNv->misc_info.sel_clk & ~(0xf << 16)) | (1 << 16);
 871                         state->crosswired = TRUE;
 872                 } else if (nv_crtc->head == 0) {
 873                         state->crosswired = FALSE;
 874                 }
 875
 876                 /* Some cards want this register zero, so let's hope we can catch them all */
 877                 if (pNv->sel_clk_override) {
 878                         state->sel_clk = pNv->misc_info.sel_clk;
 879                 }
 880
 881                 if (nv_crtc->head == 1) {
 882                         if (state->db1_ratio[1])
 883                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
 884                 } else if (nv_crtc->head == 0) {
 885                         if (state->db1_ratio[0])
 886                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
 887                 }
 888         } else {
 889                 /* This seems true for nv34 */
 890                 state->sel_clk = 0x0;
 891                 state->crosswired = FALSE;
 892         }
 893
 894         /* We've bound crtc's and ramdac's together */
 895         if (nv_crtc->head == 1) {
 896                 if (!state->db1_ratio[1]) {
 897                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 898                 } else {
 899                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 900                 }
 901                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
 902         } else {
 903                 if (pNv->Architecture < NV_ARCH_40)
 904                         state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
 905                 else
 906                         state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
 907                 if (!state->db1_ratio[0]) {
 908                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 909                 } else {
 910                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 911                 }
 912         }
 913
 914         /* The purpose is unknown */
 915         if (pNv->Architecture == NV_ARCH_40)
 916                 state->pllsel |= (1 << 2);
 917
 918         regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
 919         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
 920         if (pNv->Architecture >= NV_ARCH_30) {
 921                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
 922         }
 923
 924         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
 925         regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
 926 }
 927
 928 static void
 929 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
 930 {
 931         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 932         ScrnInfoPtr pScrn = crtc->scrn;
 933         NVPtr pNv = NVPTR(pScrn);
 934         unsigned char seq1 = 0, crtc17 = 0;
 935         unsigned char crtc1A;
 936
 937         ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->crtc, mode);
 938
 939         NVCrtcSetOwner(crtc);
 940
 941         crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
 942         switch(mode) {
 943                 case DPMSModeStandby:
 944                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
 945                 seq1 = 0x20;
 946                 crtc17 = 0x80;
 947                 crtc1A |= 0x80;
 948                 break;
 949         case DPMSModeSuspend:
 950                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
 951                 seq1 = 0x20;
 952                 crtc17 = 0x80;
 953                 crtc1A |= 0x40;
 954                 break;
 955         case DPMSModeOff:
 956                 /* Screen: Off; HSync: Off, VSync: Off */
 957                 seq1 = 0x20;
 958                 crtc17 = 0x00;
 959                 crtc1A |= 0xC0;
 960                 break;
 961         case DPMSModeOn:
 962         default:
 963                 /* Screen: On; HSync: On, VSync: On */
 964                 seq1 = 0x00;
 965                 crtc17 = 0x80;
 966                 break;
 967         }
 968
 969         NVVgaSeqReset(crtc, TRUE);
 970         /* Each head has it's own sequencer, so we can turn it off when we want */
 971         seq1 |= (NVReadVgaSeq(crtc, 0x01) & ~0x20);
 972         NVWriteVgaSeq(crtc, 0x1, seq1);
 973         crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
 974         usleep(10000);
 975         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
 976         NVVgaSeqReset(crtc, FALSE);
 977
 978         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
 979
 980         /* I hope this is the right place */
 981         if (crtc->enabled && mode == DPMSModeOn) {
 982                 pNv->crtc_active[nv_crtc->head] = TRUE;
 983         } else {
 984                 pNv->crtc_active[nv_crtc->head] = FALSE;
 985         }
 986 }
 987
 988 static Bool
 989 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
 990                      DisplayModePtr adjusted_mode)
 991 {
 992         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 993         ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->crtc);
 994
 995         return TRUE;
 996 }
 997
 998 static void
 999 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode)
1000 {
1001         ScrnInfoPtr pScrn = crtc->scrn;
1002         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1003         NVCrtcRegPtr regp;
1004         NVPtr pNv = NVPTR(pScrn);
1005         int depth = pScrn->depth;
1006         unsigned int i;
1007
1008         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1009
1010         /*
1011         * compute correct Hsync & Vsync polarity
1012         */
1013         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
1014                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
1015
1016                 regp->MiscOutReg = 0x23;
1017                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
1018                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
1019         } else {
1020                 int VDisplay = mode->VDisplay;
1021                 if (mode->Flags & V_DBLSCAN)
1022                         VDisplay *= 2;
1023                 if (mode->VScan > 1)
1024                         VDisplay *= mode->VScan;
1025                 if (VDisplay < 400) {
1026                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
1027                 } else if (VDisplay < 480) {
1028                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
1029                 } else if (VDisplay < 768) {
1030                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
1031                 } else {
1032                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
1033                 }
1034         }
1035
1036         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
1037
1038         /*
1039         * Time Sequencer
1040         */
1041         if (depth == 4) {
1042                 regp->Sequencer[0] = 0x02;
1043         } else {
1044                 regp->Sequencer[0] = 0x00;
1045         }
1046         /* 0x20 disables the sequencer */
1047         if (mode->Flags & V_CLKDIV2) {
1048                 regp->Sequencer[1] = 0x29;
1049         } else {
1050                 regp->Sequencer[1] = 0x21;
1051         }
1052         if (depth == 1) {
1053                 regp->Sequencer[2] = 1 << BIT_PLANE;
1054         } else {
1055                 regp->Sequencer[2] = 0x0F;
1056                 regp->Sequencer[3] = 0x00;                     /* Font select */
1057         }
1058         if (depth < 8) {
1059                 regp->Sequencer[4] = 0x06;                             /* Misc */
1060         } else {
1061                 regp->Sequencer[4] = 0x0E;                             /* Misc */
1062         }
1063
1064         /*
1065         * CRTC Controller
1066         */
1067         regp->CRTC[0]  = (mode->CrtcHTotal >> 3) - 5;
1068         regp->CRTC[1]  = (mode->CrtcHDisplay >> 3) - 1;
1069         regp->CRTC[2]  = (mode->CrtcHBlankStart >> 3) - 1;
1070         regp->CRTC[3]  = (((mode->CrtcHBlankEnd >> 3) - 1) & 0x1F) | 0x80;
1071         i = (((mode->CrtcHSkew << 2) + 0x10) & ~0x1F);
1072         if (i < 0x80) {
1073                 regp->CRTC[3] |= i;
1074         }
1075         regp->CRTC[4]  = (mode->CrtcHSyncStart >> 3);
1076         regp->CRTC[5]  = ((((mode->CrtcHBlankEnd >> 3) - 1) & 0x20) << 2)
1077         | (((mode->CrtcHSyncEnd >> 3)) & 0x1F);
1078         regp->CRTC[6]  = (mode->CrtcVTotal - 2) & 0xFF;
1079         regp->CRTC[7]  = (((mode->CrtcVTotal - 2) & 0x100) >> 8)
1080                         | (((mode->CrtcVDisplay - 1) & 0x100) >> 7)
1081                         | ((mode->CrtcVSyncStart & 0x100) >> 6)
1082                         | (((mode->CrtcVBlankStart - 1) & 0x100) >> 5)
1083                         | 0x10
1084                         | (((mode->CrtcVTotal - 2) & 0x200)   >> 4)
1085                         | (((mode->CrtcVDisplay - 1) & 0x200) >> 3)
1086                         | ((mode->CrtcVSyncStart & 0x200) >> 2);
1087         regp->CRTC[8]  = 0x00;
1088         regp->CRTC[9]  = (((mode->CrtcVBlankStart - 1) & 0x200) >> 4) | 0x40;
1089         if (mode->Flags & V_DBLSCAN) {
1090                 regp->CRTC[9] |= 0x80;
1091         }
1092         if (mode->VScan >= 32) {
1093                 regp->CRTC[9] |= 0x1F;
1094         } else if (mode->VScan > 1) {
1095                 regp->CRTC[9] |= mode->VScan - 1;
1096         }
1097         regp->CRTC[10] = 0x00;
1098         regp->CRTC[11] = 0x00;
1099         regp->CRTC[12] = 0x00;
1100         regp->CRTC[13] = 0x00;
1101         regp->CRTC[14] = 0x00;
1102         regp->CRTC[15] = 0x00;
1103         regp->CRTC[16] = mode->CrtcVSyncStart & 0xFF;
1104         regp->CRTC[17] = (mode->CrtcVSyncEnd & 0x0F) | 0x20;
1105         regp->CRTC[18] = (mode->CrtcVDisplay - 1) & 0xFF;
1106         regp->CRTC[19] = mode->CrtcHDisplay >> 4;  /* just a guess */
1107         regp->CRTC[20] = 0x00;
1108         regp->CRTC[21] = (mode->CrtcVBlankStart - 1) & 0xFF;
1109         regp->CRTC[22] = (mode->CrtcVBlankEnd - 1) & 0xFF;
1110         /* 0x80 enables the sequencer, we don't want that */
1111         if (depth < 8) {
1112                 regp->CRTC[23] = 0xE3 & ~0x80;
1113         } else {
1114                 regp->CRTC[23] = 0xC3 & ~0x80;
1115         }
1116         regp->CRTC[24] = 0xFF;
1117
1118         /*
1119         * Theory resumes here....
1120         */
1121
1122         /*
1123         * Graphics Display Controller
1124         */
1125         regp->Graphics[0] = 0x00;
1126         regp->Graphics[1] = 0x00;
1127         regp->Graphics[2] = 0x00;
1128         regp->Graphics[3] = 0x00;
1129         if (depth == 1) {
1130                 regp->Graphics[4] = BIT_PLANE;
1131                 regp->Graphics[5] = 0x00;
1132         } else {
1133                 regp->Graphics[4] = 0x00;
1134                 if (depth == 4) {
1135                         regp->Graphics[5] = 0x02;
1136                 } else {
1137                         regp->Graphics[5] = 0x40;
1138                 }
1139         }
1140         regp->Graphics[6] = 0x05;   /* only map 64k VGA memory !!!! */
1141         regp->Graphics[7] = 0x0F;
1142         regp->Graphics[8] = 0xFF;
1143
1144         if (depth == 1) {
1145                 /* Initialise the Mono map according to which bit-plane gets used */
1146
1147                 Bool flipPixels = xf86GetFlipPixels();
1148
1149                 for (i=0; i<16; i++) {
1150                         if (((i & (1 << BIT_PLANE)) != 0) != flipPixels) {
1151                                 regp->Attribute[i] = WHITE_VALUE;
1152                         } else {
1153                                 regp->Attribute[i] = BLACK_VALUE;
1154                         }
1155                 }
1156
1157         } else {
1158                 regp->Attribute[0]  = 0x00; /* standard colormap translation */
1159                 regp->Attribute[1]  = 0x01;
1160                 regp->Attribute[2]  = 0x02;
1161                 regp->Attribute[3]  = 0x03;
1162                 regp->Attribute[4]  = 0x04;
1163                 regp->Attribute[5]  = 0x05;
1164                 regp->Attribute[6]  = 0x06;
1165                 regp->Attribute[7]  = 0x07;
1166                 regp->Attribute[8]  = 0x08;
1167                 regp->Attribute[9]  = 0x09;
1168                 regp->Attribute[10] = 0x0A;
1169                 regp->Attribute[11] = 0x0B;
1170                 regp->Attribute[12] = 0x0C;
1171                 regp->Attribute[13] = 0x0D;
1172                 regp->Attribute[14] = 0x0E;
1173                 regp->Attribute[15] = 0x0F;
1174                 if (depth == 4) {
1175                         regp->Attribute[16] = 0x81; /* wrong for the ET4000 */
1176                 } else {
1177                         regp->Attribute[16] = 0x41; /* wrong for the ET4000 */
1178                 }
1179                 if (depth > 4) {
1180                         regp->Attribute[17] = 0xff;
1181                 }
1182                 /* Attribute[17] (overscan) initialised in vgaHWGetHWRec() */
1183         }
1184         regp->Attribute[18] = 0x0F;
1185         regp->Attribute[19] = 0x00;
1186         regp->Attribute[20] = 0x00;
1187 }
1188
1189 #define MAX_H_VALUE(i) ((0x1ff + i) << 3)
1190 #define MAX_V_VALUE(i) ((0xfff + i) << 0)
1191
1192 /**
1193  * Sets up registers for the given mode/adjusted_mode pair.
1194  *
1195  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1196  *
1197  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1198  * be easily turned on/off after this.
1199  */
1200 static void
1201 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1202 {
1203         ScrnInfoPtr pScrn = crtc->scrn;
1204         NVPtr pNv = NVPTR(pScrn);
1205         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
1206         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1207         NVFBLayout *pLayout = &pNv->CurrentLayout;
1208         NVCrtcRegPtr regp, savep;
1209         unsigned int i;
1210
1211 #if 0
1212         /* Happily borrowed from haiku driver, as an extra safety */
1213
1214         /* Make it multiples of 8 */
1215         mode->CrtcHDisplay &= ~7;
1216         mode->CrtcHSyncStart &= ~7;
1217         mode->CrtcHSyncEnd &= ~7;
1218         mode->CrtcHTotal &= ~7;
1219
1220         /* Horizontal stuff */
1221
1222         /* Time for some mode mangling */
1223         /* We only have 9 bits to store most of this information (mask 0x3f) */
1224         if (mode->CrtcHDisplay > MAX_H_VALUE(-2))
1225                 mode->CrtcHDisplay = MAX_H_VALUE(-2);
1226
1227         if (mode->CrtcHSyncStart > MAX_H_VALUE(-1))
1228                 mode->CrtcHSyncStart = MAX_H_VALUE(-1);
1229
1230         if  (mode->CrtcHSyncEnd > MAX_H_VALUE(0))
1231                 mode->CrtcHSyncEnd = MAX_H_VALUE(0);
1232
1233         if (mode->CrtcHTotal > MAX_H_VALUE(5))
1234                 mode->CrtcHTotal = MAX_H_VALUE(5);
1235
1236         /* Make room for a sync pulse if there is not enough room */
1237         if (mode->CrtcHTotal < mode->CrtcHSyncEnd + 0x50)
1238                 mode->CrtcHTotal = mode->CrtcHSyncEnd + 0x50;
1239
1240         /* Too large sync pulse? */
1241         if (mode->CrtcHTotal > mode->CrtcHSyncEnd + 0x3f8)
1242                 mode->CrtcHTotal = mode->CrtcHSyncEnd + 0x3f8;
1243
1244         /* Is the sync pulse outside the screen? */
1245         if (mode->CrtcHSyncEnd > mode->CrtcHTotal - 8)
1246                 mode->CrtcHSyncEnd = mode->CrtcHTotal - 8;
1247
1248         if (mode->CrtcHSyncStart < mode->CrtcHDisplay + 8)
1249                 mode->CrtcHSyncStart = mode->CrtcHDisplay + 8;
1250
1251         /* We've only got 5 bits to store the sync stuff */
1252         if (mode->CrtcHSyncEnd > mode->CrtcHSyncStart + (0x1f << 3))
1253                 mode->CrtcHSyncEnd = mode->CrtcHSyncStart + (0x1f << 3);
1254
1255         /* Vertical stuff */
1256
1257         /* We've only got 12 bits for this stuff */
1258         if (mode->CrtcVDisplay > MAX_V_VALUE(-2))
1259                 mode->CrtcVDisplay = MAX_V_VALUE(-2);
1260
1261         if (mode->CrtcVSyncStart > MAX_V_VALUE(-1))
1262                 mode->CrtcVSyncStart = MAX_V_VALUE(-1);
1263
1264         if  (mode->CrtcVSyncEnd > MAX_V_VALUE(0))
1265                 mode->CrtcVSyncEnd = MAX_V_VALUE(0);
1266
1267         if (mode->CrtcVTotal > MAX_V_VALUE(5))
1268                 mode->CrtcVTotal = MAX_V_VALUE(5);
1269
1270         /* Make room for a sync pulse if there is not enough room */
1271         if (mode->CrtcVTotal < mode->CrtcVSyncEnd + 0x3)
1272                 mode->CrtcVTotal = mode->CrtcVSyncEnd + 0x3;
1273
1274         /* Too large sync pulse? */
1275         if (mode->CrtcVTotal > mode->CrtcVSyncEnd + 0xff)
1276                 mode->CrtcVTotal = mode->CrtcVSyncEnd + 0xff;
1277
1278         /* Is the sync pulse outside the screen? */
1279         if (mode->CrtcVSyncEnd > mode->CrtcVTotal - 1)
1280                 mode->CrtcVSyncEnd = mode->CrtcVTotal - 1;
1281
1282         if (mode->CrtcVSyncStart < mode->CrtcVDisplay + 1)
1283                 mode->CrtcVSyncStart = mode->CrtcVDisplay + 1;
1284
1285         /* We've only got 4 bits to store the sync stuff */
1286         if (mode->CrtcVSyncEnd > mode->CrtcVSyncStart + (0x0f << 0))
1287                 mode->CrtcVSyncEnd = mode->CrtcVSyncStart + (0x0f << 0);
1288 #endif
1289
1290         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
1291         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
1292         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
1293         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
1294         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
1295         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
1296         int vertDisplay         = mode->CrtcVDisplay                    - 1;
1297         int vertStart           = mode->CrtcVSyncStart          - 1;
1298         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
1299         int vertTotal           = mode->CrtcVTotal                      - 2;
1300         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
1301         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
1302
1303         Bool is_fp = FALSE;
1304
1305         xf86OutputPtr  output;
1306         NVOutputPrivatePtr nv_output;
1307         for (i = 0; i < xf86_config->num_output; i++) {
1308                 output = xf86_config->output[i];
1309                 nv_output = output->driver_private;
1310
1311                 if (output->crtc == crtc) {
1312                         if ((nv_output->type == OUTPUT_LVDS) ||
1313                                 (nv_output->type == OUTPUT_TMDS)) {
1314
1315                                 is_fp = TRUE;
1316                                 break;
1317                         }
1318                 }
1319         }
1320
1321         ErrorF("Mode clock: %d\n", mode->Clock);
1322         ErrorF("Adjusted mode clock: %d\n", adjusted_mode->Clock);
1323
1324         ErrorF("crtc: Pre-sync workaround\n");
1325         /* Reverted to what nv did, because that works for all resolutions on flatpanels */
1326         if (is_fp) {
1327                 vertStart = vertTotal - 3;
1328                 vertEnd = vertTotal - 2;
1329                 vertBlankStart = vertStart;
1330                 horizStart = horizTotal - 5;
1331                 horizEnd = horizTotal - 2;
1332                 horizBlankEnd = horizTotal + 4;
1333                 if (pNv->overlayAdaptor) {
1334                         /* This reportedly works around Xv some overlay bandwidth problems*/
1335                         horizTotal += 2;
1336                 }
1337         }
1338         ErrorF("crtc: Post-sync workaround\n");
1339
1340         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
1341         ErrorF("horizStart: 0x%X \n", horizStart);
1342         ErrorF("horizEnd: 0x%X \n", horizEnd);
1343         ErrorF("horizTotal: 0x%X \n", horizTotal);
1344         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
1345         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
1346         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
1347         ErrorF("vertStart: 0x%X \n", vertStart);
1348         ErrorF("vertEnd: 0x%X \n", vertEnd);
1349         ErrorF("vertTotal: 0x%X \n", vertTotal);
1350         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
1351         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
1352
1353         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1354         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1355
1356         if(mode->Flags & V_INTERLACE)
1357                 vertTotal |= 1;
1358
1359         regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
1360         regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
1361         regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
1362         regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0)
1363                                 | SetBit(7);
1364         regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
1365         regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
1366                                 | SetBitField(horizEnd,4:0,4:0);
1367         regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
1368         regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
1369                                 | SetBitField(vertDisplay,8:8,1:1)
1370                                 | SetBitField(vertStart,8:8,2:2)
1371                                 | SetBitField(vertBlankStart,8:8,3:3)
1372                                 | SetBit(4)
1373                                 | SetBitField(vertTotal,9:9,5:5)
1374                                 | SetBitField(vertDisplay,9:9,6:6)
1375                                 | SetBitField(vertStart,9:9,7:7);
1376         regp->CRTC[NV_VGA_CRTCX_MAXSCLIN]  = SetBitField(vertBlankStart,9:9,5:5)
1377                                 | SetBit(6)
1378                                 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00);
1379         regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
1380         regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
1381         regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
1382         regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
1383         regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
1384         regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
1385         /* Not an extended register */
1386         regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
1387
1388         regp->Attribute[0x10] = 0x01;
1389         /* Blob sets this for normal monitors as well */
1390         regp->Attribute[0x11] = 0x00;
1391
1392         regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
1393                                 | SetBitField(vertBlankStart,10:10,3:3)
1394                                 | SetBitField(vertStart,10:10,2:2)
1395                                 | SetBitField(vertDisplay,10:10,1:1)
1396                                 | SetBitField(vertTotal,10:10,0:0);
1397
1398         regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
1399                                 | SetBitField(horizDisplay,8:8,1:1)
1400                                 | SetBitField(horizBlankStart,8:8,2:2)
1401                                 | SetBitField(horizStart,8:8,3:3);
1402
1403         regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
1404                                 | SetBitField(vertDisplay,11:11,2:2)
1405                                 | SetBitField(vertStart,11:11,4:4)
1406                                 | SetBitField(vertBlankStart,11:11,6:6);
1407
1408         if(mode->Flags & V_INTERLACE) {
1409                 horizTotal = (horizTotal >> 1) & ~1;
1410                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
1411                 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
1412         } else {
1413                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff;  /* interlace off */
1414         }
1415
1416         /* bit2 = 0 -> fine pitched crtc granularity */
1417         /* The rest disables double buffering on CRTC access */
1418         regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
1419
1420         if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
1421                 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1422                 if (nv_crtc->head == 0) {
1423                         regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1424                 }
1425
1426                 if (is_fp) {
1427                         regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0) | (1 << 1);
1428                 }
1429         } else {
1430                 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
1431                 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
1432         }
1433
1434         /* I'm trusting haiku driver on this one, they say it enables an external TDMS clock */
1435         if (is_fp) {
1436                 regp->CRTC[NV_VGA_CRTCX_59] = 0x1;
1437         } else {
1438                 regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1439         }
1440
1441         /*
1442         * Initialize DAC palette.
1443         */
1444         if(pLayout->bitsPerPixel != 8 ) {
1445                 for (i = 0; i < 256; i++) {
1446                         regp->DAC[i*3]     = i;
1447                         regp->DAC[(i*3)+1] = i;
1448                         regp->DAC[(i*3)+2] = i;
1449                 }
1450         }
1451
1452         /*
1453         * Calculate the extended registers.
1454         */
1455
1456         if(pLayout->depth < 24) {
1457                 i = pLayout->depth;
1458         } else {
1459                 i = 32;
1460         }
1461
1462         if(pNv->Architecture >= NV_ARCH_10) {
1463                 pNv->CURSOR = (CARD32 *)pNv->Cursor->map;
1464         }
1465
1466         ErrorF("crtc %d %d %d\n", nv_crtc->crtc, mode->CrtcHDisplay, pScrn->displayWidth);
1467         nv_crtc_calc_state_ext(crtc,
1468                                 i,
1469                                 pScrn->displayWidth,
1470                                 mode->CrtcHDisplay,
1471                                 mode->CrtcVDisplay,
1472                                 adjusted_mode->Clock,
1473                                 mode->Flags);
1474
1475         /* Enable slaved mode */
1476         if (is_fp) {
1477                 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1478         }
1479
1480         /* What is the meaning of this register? */
1481         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1482         regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
1483
1484         /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1485         /* But what are those special conditions? */
1486         if (pNv->Architecture <= NV_ARCH_30) {
1487                 if (is_fp) {
1488                         if(nv_crtc->head == 1) {
1489                                 regp->head |= NV_CRTC_FSEL_FPP1;
1490                         } else if (pNv->twoHeads) {
1491                                 regp->head |= NV_CRTC_FSEL_FPP2;
1492                         }
1493                 }
1494         } else {
1495                 /* This is observed on some g70 cards, non-flatpanel's too */
1496                 if (nv_crtc->head == 1) {
1497                         regp->head |= NV_CRTC_FSEL_FPP2;
1498                 }
1499         }
1500
1501         /* Except for rare conditions I2C is enabled on the primary crtc */
1502         if (nv_crtc->head == 0) {
1503                 if (pNv->overlayAdaptor) {
1504                         regp->head |= NV_CRTC_FSEL_OVERLAY;
1505                 }
1506                 regp->head |= NV_CRTC_FSEL_I2C;
1507         }
1508
1509         regp->cursorConfig = 0x00000100;
1510         if(mode->Flags & V_DBLSCAN)
1511                 regp->cursorConfig |= (1 << 4);
1512         if(pNv->alphaCursor) {
1513                 if((pNv->Chipset & 0x0ff0) != CHIPSET_NV11) {
1514                         regp->cursorConfig |= 0x04011000;
1515                 } else {
1516                         regp->cursorConfig |= 0x14011000;
1517                 }
1518         } else {
1519                 regp->cursorConfig |= 0x02000000;
1520         }
1521
1522         /* Unblock some timings */
1523         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1524         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1525
1526         /* 0x20 seems to be enabled and 0x14 disabled */
1527         regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1528
1529         /* 0x00 is disabled, 0x22 crt and 0x88 dfp */
1530         /* 0x11 is LVDS? */
1531         if (is_fp) {
1532                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1533         } else {
1534                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1535         }
1536
1537         /* These values seem to vary */
1538         regp->CRTC[NV_VGA_CRTCX_3C] = savep->CRTC[NV_VGA_CRTCX_3C];
1539
1540         /* 0x80 seems to be used very often, if not always */
1541         regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1542
1543         /* Are these(0x55 and 0x56) also timing related registers, since disabling them does nothing? */
1544         regp->CRTC[NV_VGA_CRTCX_55] = 0x0;
1545
1546         /* Common values like 0x14 and 0x04 are converted to 0x10 and 0x00 */
1547         //regp->CRTC[NV_VGA_CRTCX_56] = savep->CRTC[NV_VGA_CRTCX_56] & ~(1<<4);
1548         regp->CRTC[NV_VGA_CRTCX_56] = 0x0;
1549
1550         regp->CRTC[NV_VGA_CRTCX_57] = 0x0;
1551
1552         /* bit0: Seems to be mostly used on crtc1 */
1553         /* bit1: 1=crtc1, 0=crtc, but i'm unsure about this */
1554         /* 0x7E (crtc0, only seen in one dump) and 0x7F (crtc1) seem to be some kind of disable setting */
1555         /* This is likely to be incomplete */
1556         /* This is a very strange register, changed very often by the blob */
1557         regp->CRTC[NV_VGA_CRTCX_58] = 0x0;
1558
1559         /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1*/
1560         if (nv_crtc->head == 1) {
1561                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52;
1562         } else {
1563                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52 + 4;
1564         }
1565
1566         /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1567         regp->unk81c = nvReadCRTC0(pNv, NV_CRTC_081C);
1568
1569         regp->unk830 = mode->CrtcVDisplay - 3;
1570         regp->unk834 = mode->CrtcVDisplay - 1;
1571
1572         /* This is what the blob does */
1573         regp->unk850 = nvReadCRTC(pNv, 0, NV_CRTC_0850);
1574
1575         /* Never ever modify gpio, unless you know very well what you're doing */
1576         regp->gpio = nvReadCRTC(pNv, 0, NV_CRTC_GPIO);
1577 }
1578
1579 /**
1580  * Sets up registers for the given mode/adjusted_mode pair.
1581  *
1582  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1583  *
1584  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1585  * be easily turned on/off after this.
1586  */
1587 static void
1588 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
1589                  DisplayModePtr adjusted_mode,
1590                  int x, int y)
1591 {
1592         ScrnInfoPtr pScrn = crtc->scrn;
1593         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1594         NVPtr pNv = NVPTR(pScrn);
1595
1596         ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->crtc);
1597
1598         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->crtc);
1599         xf86PrintModeline(pScrn->scrnIndex, mode);
1600         NVCrtcSetOwner(crtc);
1601
1602         nv_crtc_mode_set_vga(crtc, mode);
1603         nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
1604
1605         /* Just in case */
1606         NVCrtcLockUnlock(crtc, FALSE);
1607
1608         NVVgaProtect(crtc, TRUE);
1609         if (pNv->Architecture == NV_ARCH_40) {
1610                 nv40_crtc_load_state_pll(pNv, &pNv->ModeReg);
1611         } else {
1612                 nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
1613         }
1614         nv_crtc_load_state_ext(crtc, &pNv->ModeReg);
1615         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
1616
1617         NVVgaProtect(crtc, FALSE);
1618
1619         NVCrtcSetBase(crtc, x, y);
1620
1621 #if X_BYTE_ORDER == X_BIG_ENDIAN
1622         /* turn on LFB swapping */
1623         {
1624                 unsigned char tmp;
1625
1626                 tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
1627                 tmp |= (1 << 7);
1628                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
1629         }
1630 #endif
1631 }
1632
1633 void nv_crtc_save(xf86CrtcPtr crtc)
1634 {
1635         ScrnInfoPtr pScrn = crtc->scrn;
1636         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1637         NVPtr pNv = NVPTR(pScrn);
1638
1639         ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->crtc);
1640
1641         /* We just came back from terminal, so unlock */
1642         NVCrtcLockUnlock(crtc, FALSE);
1643
1644         NVCrtcSetOwner(crtc);
1645         if (pNv->Architecture == NV_ARCH_40) {
1646                 nv40_crtc_save_state_pll(pNv, &pNv->SavedReg);
1647         } else {
1648                 nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
1649         }
1650         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
1651         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
1652 }
1653
1654 void nv_crtc_restore(xf86CrtcPtr crtc)
1655 {
1656         ScrnInfoPtr pScrn = crtc->scrn;
1657         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1658         NVPtr pNv = NVPTR(pScrn);
1659
1660         ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->crtc);
1661
1662         NVCrtcSetOwner(crtc);
1663
1664         /* Just to be safe */
1665         NVCrtcLockUnlock(crtc, FALSE);
1666
1667         NVVgaProtect(crtc, TRUE);
1668         nv_crtc_load_state_ext(crtc, &pNv->SavedReg);
1669         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
1670         if (pNv->Architecture == NV_ARCH_40) {
1671                 nv40_crtc_load_state_pll(pNv, &pNv->SavedReg);
1672         } else {
1673                 nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
1674         }
1675         nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->vtOWNER);
1676         NVVgaProtect(crtc, FALSE);
1677
1678         /* We must lock the door if we leave ;-) */
1679         NVCrtcLockUnlock(crtc, TRUE);
1680 }
1681
1682 void nv_crtc_prepare(xf86CrtcPtr crtc)
1683 {
1684         ScrnInfoPtr pScrn = crtc->scrn;
1685         NVPtr pNv = NVPTR(pScrn);
1686         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1687
1688         ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->crtc);
1689
1690         crtc->funcs->dpms(crtc, DPMSModeOff);
1691
1692         /* Sync the engine before adjust mode */
1693         if (pNv->EXADriverPtr) {
1694                 exaMarkSync(pScrn->pScreen);
1695                 exaWaitSync(pScrn->pScreen);
1696         }
1697 }
1698
1699 void nv_crtc_commit(xf86CrtcPtr crtc)
1700 {
1701         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1702         ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->crtc);
1703
1704         crtc->funcs->dpms (crtc, DPMSModeOn);
1705         if (crtc->scrn->pScreen != NULL)
1706                 xf86_reload_cursors (crtc->scrn->pScreen);
1707 }
1708
1709 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
1710 {
1711         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1712         ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->crtc);
1713
1714         return FALSE;
1715 }
1716
1717 static void nv_crtc_unlock(xf86CrtcPtr crtc)
1718 {
1719         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1720         ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->crtc);
1721 }
1722
1723 static void
1724 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
1725                                         int size)
1726 {
1727         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1728         ScrnInfoPtr pScrn = crtc->scrn;
1729         NVPtr pNv = NVPTR(pScrn);
1730         int i, j;
1731
1732         NVCrtcRegPtr regp;
1733         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1734
1735         switch (pNv->CurrentLayout.depth) {
1736         case 15:
1737                 /* R5G5B5 */
1738                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
1739                 for (i = 0; i < 32; i++) {
1740                         for (j = 0; j < 8; j++) {
1741                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1742                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
1743                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1744                         }
1745                 }
1746                 break;
1747         case 16:
1748                 /* R5G6B5 */
1749                 /* First deal with the 5 bit colors */
1750                 for (i = 0; i < 32; i++) {
1751                         for (j = 0; j < 8; j++) {
1752                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1753                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1754                         }
1755                 }
1756                 /* Now deal with the 6 bit color */
1757                 for (i = 0; i < 64; i++) {
1758                         for (j = 0; j < 4; j++) {
1759                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
1760                         }
1761                 }
1762                 break;
1763         default:
1764                 /* R8G8B8 */
1765                 for (i = 0; i < 256; i++) {
1766                         regp->DAC[i * 3] = red[i] >> 8;
1767                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
1768                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
1769                 }
1770                 break;
1771         }
1772
1773         NVCrtcLoadPalette(crtc);
1774 }
1775
1776 /* NV04-NV10 doesn't support alpha cursors */
1777 static const xf86CrtcFuncsRec nv_crtc_funcs = {
1778         .dpms = nv_crtc_dpms,
1779         .save = nv_crtc_save, /* XXX */
1780         .restore = nv_crtc_restore, /* XXX */
1781         .mode_fixup = nv_crtc_mode_fixup,
1782         .mode_set = nv_crtc_mode_set,
1783         .prepare = nv_crtc_prepare,
1784         .commit = nv_crtc_commit,
1785         .destroy = NULL, /* XXX */
1786         .lock = nv_crtc_lock,
1787         .unlock = nv_crtc_unlock,
1788         .set_cursor_colors = nv_crtc_set_cursor_colors,
1789         .set_cursor_position = nv_crtc_set_cursor_position,
1790         .show_cursor = nv_crtc_show_cursor,
1791         .hide_cursor = nv_crtc_hide_cursor,
1792         .load_cursor_image = nv_crtc_load_cursor_image,
1793         .gamma_set = nv_crtc_gamma_set,
1794 };
1795
1796 /* NV11 and up has support for alpha cursors. */
1797 /* Due to different maximum sizes we cannot allow it to use normal cursors */
1798 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
1799         .dpms = nv_crtc_dpms,
1800         .save = nv_crtc_save, /* XXX */
1801         .restore = nv_crtc_restore, /* XXX */
1802         .mode_fixup = nv_crtc_mode_fixup,
1803         .mode_set = nv_crtc_mode_set,
1804         .prepare = nv_crtc_prepare,
1805         .commit = nv_crtc_commit,
1806         .destroy = NULL, /* XXX */
1807         .lock = nv_crtc_lock,
1808         .unlock = nv_crtc_unlock,
1809         .set_cursor_colors = nv_crtc_set_cursor_colors,
1810         .set_cursor_position = nv_crtc_set_cursor_position,
1811         .show_cursor = nv_crtc_show_cursor,
1812         .hide_cursor = nv_crtc_hide_cursor,
1813         .load_cursor_argb = nv_crtc_load_cursor_argb,
1814         .gamma_set = nv_crtc_gamma_set,
1815 };
1816
1817
1818 void
1819 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
1820 {
1821         NVPtr pNv = NVPTR(pScrn);
1822         xf86CrtcPtr crtc;
1823         NVCrtcPrivatePtr nv_crtc;
1824
1825         if (pNv->NVArch >= 0x11) {
1826                 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
1827         } else {
1828                 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
1829         }
1830         if (crtc == NULL)
1831                 return;
1832
1833         nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
1834         nv_crtc->crtc = crtc_num;
1835         nv_crtc->head = crtc_num;
1836
1837         crtc->driver_private = nv_crtc;
1838
1839         NVCrtcLockUnlock(crtc, FALSE);
1840 }
1841
1842 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1843 {
1844     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1845     int i;
1846     NVCrtcRegPtr regp;
1847
1848     regp = &state->crtc_reg[nv_crtc->head];
1849
1850     NVWriteMiscOut(crtc, regp->MiscOutReg);
1851
1852     for (i = 1; i < 5; i++)
1853       NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
1854
1855     /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
1856     NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
1857
1858     for (i = 0; i < 25; i++)
1859       NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
1860
1861     for (i = 0; i < 9; i++)
1862       NVWriteVgaGr(crtc, i, regp->Graphics[i]);
1863
1864     NVEnablePalette(crtc);
1865     for (i = 0; i < 21; i++)
1866       NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
1867     NVDisablePalette(crtc);
1868
1869 }
1870
1871 static void nv_crtc_fix_nv40_hw_cursor(xf86CrtcPtr crtc)
1872 {
1873   /* TODO - implement this properly */
1874   ScrnInfoPtr pScrn = crtc->scrn;
1875   NVPtr pNv = NVPTR(pScrn);
1876
1877   if(pNv->Architecture == NV_ARCH_40) {  /* HW bug */
1878     volatile CARD32 curpos = nvReadCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS);
1879     nvWriteCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS, curpos);
1880   }
1881
1882 }
1883 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1884 {
1885     ScrnInfoPtr pScrn = crtc->scrn;
1886     NVPtr pNv = NVPTR(pScrn);
1887     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1888     NVCrtcRegPtr regp;
1889
1890     regp = &state->crtc_reg[nv_crtc->head];
1891
1892     if(pNv->Architecture >= NV_ARCH_10) {
1893         if(pNv->twoHeads) {
1894            nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL, regp->head);
1895         }
1896         nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
1897         nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
1898         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
1899         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
1900         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1901         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1902         nvWriteMC(pNv, 0x1588, 0);
1903
1904         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
1905         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
1906         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO, regp->gpio);
1907         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0830, regp->unk830);
1908         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0834, regp->unk834);
1909         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0850, regp->unk850);
1910         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_081C, regp->unk81c);
1911
1912         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
1913         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
1914
1915         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
1916         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
1917         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3C, regp->CRTC[NV_VGA_CRTCX_3C]);
1918         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
1919         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
1920         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_56, regp->CRTC[NV_VGA_CRTCX_56]);
1921         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_57, regp->CRTC[NV_VGA_CRTCX_57]);
1922         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_58, regp->CRTC[NV_VGA_CRTCX_58]);
1923         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
1924         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
1925     }
1926
1927     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
1928     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
1929     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
1930     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
1931     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
1932     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
1933     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
1934     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
1935     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
1936     if(pNv->Architecture >= NV_ARCH_30) {
1937       NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
1938     }
1939
1940     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
1941     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
1942     nv_crtc_fix_nv40_hw_cursor(crtc);
1943     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
1944     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
1945
1946     nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_EN_0, 0);
1947     nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
1948
1949     pNv->CurrentState = state;
1950 }
1951
1952 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1953 {
1954     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1955     int i;
1956     NVCrtcRegPtr regp;
1957
1958     regp = &state->crtc_reg[nv_crtc->head];
1959
1960     regp->MiscOutReg = NVReadMiscOut(crtc);
1961
1962     for (i = 0; i < 25; i++)
1963         regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
1964
1965     NVEnablePalette(crtc);
1966     for (i = 0; i < 21; i++)
1967         regp->Attribute[i] = NVReadVgaAttr(crtc, i);
1968     NVDisablePalette(crtc);
1969
1970     for (i = 0; i < 9; i++)
1971         regp->Graphics[i] = NVReadVgaGr(crtc, i);
1972
1973     for (i = 1; i < 5; i++)
1974         regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
1975
1976 }
1977
1978 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1979 {
1980     ScrnInfoPtr pScrn = crtc->scrn;
1981     NVPtr pNv = NVPTR(pScrn);
1982     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1983     NVCrtcRegPtr regp;
1984
1985     regp = &state->crtc_reg[nv_crtc->head];
1986
1987     regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
1988     regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
1989     regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
1990     regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
1991     regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
1992     regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
1993     regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
1994
1995     regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
1996     regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
1997     if(pNv->Architecture >= NV_ARCH_30) {
1998          regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
1999     }
2000     regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
2001     regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
2002     regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
2003     regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
2004
2005     regp->gpio = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO);
2006     regp->unk830 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0830);
2007     regp->unk834 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0834);
2008     regp->unk850 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0850);
2009     regp->unk81c = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_081C);
2010
2011     if(pNv->Architecture >= NV_ARCH_10) {
2012         if(pNv->twoHeads) {
2013            regp->head     = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL);
2014            regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
2015         }
2016         regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
2017
2018         regp->cursorConfig = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG);
2019
2020         regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
2021         regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
2022         regp->CRTC[NV_VGA_CRTCX_3C] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3C);
2023         regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
2024         regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
2025         regp->CRTC[NV_VGA_CRTCX_56] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_56);
2026         regp->CRTC[NV_VGA_CRTCX_57] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_57);
2027         regp->CRTC[NV_VGA_CRTCX_58] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_58);
2028         regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
2029         regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
2030         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
2031         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
2032     }
2033 }
2034
2035 void
2036 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y)
2037 {
2038         ScrnInfoPtr pScrn = crtc->scrn;
2039         NVPtr pNv = NVPTR(pScrn);
2040         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2041         NVFBLayout *pLayout = &pNv->CurrentLayout;
2042         CARD32 start = 0;
2043
2044         ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
2045
2046         start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
2047         start += pNv->FB->offset;
2048
2049         /* 30 bits addresses in 32 bits according to haiku */
2050         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_START, start & 0xfffffffc);
2051
2052         /* set NV4/NV10 byte adress: (bit0 - 1) */
2053         NVWriteVgaAttr(crtc, 0x13, (start & 0x3) << 1);
2054
2055         crtc->x = x;
2056         crtc->y = y;
2057 }
2058
2059 static void NVCrtcWriteDacMask(xf86CrtcPtr crtc, CARD8 value)
2060 {
2061   ScrnInfoPtr pScrn = crtc->scrn;
2062   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2063   NVPtr pNv = NVPTR(pScrn);
2064   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2065
2066   NV_WR08(pDACReg, VGA_DAC_MASK, value);
2067 }
2068
2069 static CARD8 NVCrtcReadDacMask(xf86CrtcPtr crtc)
2070 {
2071   ScrnInfoPtr pScrn = crtc->scrn;
2072   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2073   NVPtr pNv = NVPTR(pScrn);
2074   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2075
2076   return NV_RD08(pDACReg, VGA_DAC_MASK);
2077 }
2078
2079 static void NVCrtcWriteDacReadAddr(xf86CrtcPtr crtc, CARD8 value)
2080 {
2081   ScrnInfoPtr pScrn = crtc->scrn;
2082   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2083   NVPtr pNv = NVPTR(pScrn);
2084   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2085
2086   NV_WR08(pDACReg, VGA_DAC_READ_ADDR, value);
2087 }
2088
2089 static void NVCrtcWriteDacWriteAddr(xf86CrtcPtr crtc, CARD8 value)
2090 {
2091   ScrnInfoPtr pScrn = crtc->scrn;
2092   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2093   NVPtr pNv = NVPTR(pScrn);
2094   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2095
2096   NV_WR08(pDACReg, VGA_DAC_WRITE_ADDR, value);
2097 }
2098
2099 static void NVCrtcWriteDacData(xf86CrtcPtr crtc, CARD8 value)
2100 {
2101   ScrnInfoPtr pScrn = crtc->scrn;
2102   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2103   NVPtr pNv = NVPTR(pScrn);
2104   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2105
2106   NV_WR08(pDACReg, VGA_DAC_DATA, value);
2107 }
2108
2109 static CARD8 NVCrtcReadDacData(xf86CrtcPtr crtc, CARD8 value)
2110 {
2111   ScrnInfoPtr pScrn = crtc->scrn;
2112   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2113   NVPtr pNv = NVPTR(pScrn);
2114   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2115
2116   return NV_RD08(pDACReg, VGA_DAC_DATA);
2117 }
2118
2119 void NVCrtcLoadPalette(xf86CrtcPtr crtc)
2120 {
2121         int i;
2122         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2123         NVCrtcRegPtr regp;
2124         ScrnInfoPtr pScrn = crtc->scrn;
2125         NVPtr pNv = NVPTR(pScrn);
2126
2127         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2128
2129         NVCrtcSetOwner(crtc);
2130         NVCrtcWriteDacMask(crtc, 0xff);
2131         NVCrtcWriteDacWriteAddr(crtc, 0x00);
2132
2133         for (i = 0; i<768; i++) {
2134                 NVCrtcWriteDacData(crtc, regp->DAC[i]);
2135         }
2136         NVDisablePalette(crtc);
2137 }
2138
2139 void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
2140 {
2141         unsigned char scrn;
2142
2143         NVCrtcSetOwner(crtc);
2144
2145         scrn = NVReadVgaSeq(crtc, 0x01);
2146         if (on) {
2147                 scrn &= ~0x20;
2148         } else {
2149                 scrn |= 0x20;
2150         }
2151
2152         NVVgaSeqReset(crtc, TRUE);
2153         NVWriteVgaSeq(crtc, 0x01, scrn);
2154         NVVgaSeqReset(crtc, FALSE);
2155 }
2156
2157 /*************************************************************************** \
2158 |*                                                                           *|
2159 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
2160 |*                                                                           *|
2161 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
2162 |*     international laws.  Users and possessors of this source code are     *|
2163 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
2164 |*     use this code in individual and commercial software.                  *|
2165 |*                                                                           *|
2166 |*     Any use of this source code must include,  in the user documenta-     *|
2167 |*     tion and  internal comments to the code,  notices to the end user     *|
2168 |*     as follows:                                                           *|
2169 |*                                                                           *|
2170 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
2171 |*                                                                           *|
2172 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
2173 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
2174 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
2175 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
2176 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
2177 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
2178 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
2179 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
2180 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
2181 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
2182 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
2183 |*                                                                           *|
2184 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
2185 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
2186 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
2187 |*     computer  software  documentation,"  as such  terms  are  used in     *|
2188 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
2189 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
2190 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
2191 |*     all U.S. Government End Users  acquire the source code  with only     *|
2192 |*     those rights set forth herein.                                        *|
2193 |*                                                                           *|
2194  \***************************************************************************/