git.oblomov.eu Git - nouveau/blob - src/riva_hw.c

   1  /***************************************************************************\
   2 |*                                                                           *|
   3 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
   4 |*                                                                           *|
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   9 |*                                                                           *|
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  12 |*     as follows:                                                           *|
  13 |*                                                                           *|
  14 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
  15 |*                                                                           *|
  16 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
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  36 |*     those rights set forth herein.                                        *|
  37 |*                                                                           *|
  38  \***************************************************************************/
  39 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.c,v 1.51tsi Exp $ */
  40
  41 #include "riva_local.h"
  42 #include "compiler.h"
  43 #include "riva_include.h"
  44 #include "riva_hw.h"
  45 #include "riva_tbl.h"
  46
  47 /*
  48  * This file is an OS-agnostic file used to make RIVA 128 and RIVA TNT
  49  * operate identically (except TNT has more memory and better 3D quality.
  50  */
  51 static int nv3Busy
  52 (
  53     RIVA_HW_INST *chip
  54 )
  55 {
  56     return ((chip->Rop->FifoFree < chip->FifoEmptyCount) || (chip->PGRAPH[0x000006B0/4] & 0x01));
  57 }
  58 static void vgaLockUnlock
  59 (
  60     RIVA_HW_INST *chip,
  61     Bool           Lock
  62 )
  63 {
  64     CARD8 cr11;
  65     VGA_WR08(chip->PCIO, 0x3D4, 0x11);
  66     cr11 = VGA_RD08(chip->PCIO, 0x3D5);
  67     if(Lock) cr11 |= 0x80;
  68     else cr11 &= ~0x80;
  69     VGA_WR08(chip->PCIO, 0x3D5, cr11);
  70 }
  71
  72 static void nv3LockUnlock
  73 (
  74     RIVA_HW_INST *chip,
  75     Bool           Lock
  76 )
  77 {
  78     VGA_WR08(chip->PVIO, 0x3C4, 0x06);
  79     VGA_WR08(chip->PVIO, 0x3C5, Lock ? 0x99 : 0x57);
  80     vgaLockUnlock(chip, Lock);
  81 }
  82 static int ShowHideCursor
  83 (
  84     RIVA_HW_INST *chip,
  85     int           ShowHide
  86 )
  87 {
  88     int current;
  89     current                     =  chip->CurrentState->cursor1;
  90     chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) |
  91                                   (ShowHide & 0x01);
  92     VGA_WR08(chip->PCIO, 0x3D4, 0x31);
  93     VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1);
  94     return (current & 0x01);
  95 }
  96
  97 /****************************************************************************\
  98 *                                                                            *
  99 * The video arbitration routines calculate some "magic" numbers.  Fixes      *
 100 * the snow seen when accessing the framebuffer without it.                   *
 101 * It just works (I hope).                                                    *
 102 *                                                                            *
 103 \****************************************************************************/
 104
 105 #define DEFAULT_GR_LWM 100
 106 #define DEFAULT_VID_LWM 100
 107 #define DEFAULT_GR_BURST_SIZE 256
 108 #define DEFAULT_VID_BURST_SIZE 128
 109 #define VIDEO           0
 110 #define GRAPHICS        1
 111 #define MPORT           2
 112 #define ENGINE          3
 113 #define GFIFO_SIZE      320
 114 #define GFIFO_SIZE_128  256
 115 #define MFIFO_SIZE      120
 116 #define VFIFO_SIZE      256
 117 #define ABS(a)  (a>0?a:-a)
 118 typedef struct {
 119   int gdrain_rate;
 120   int vdrain_rate;
 121   int mdrain_rate;
 122   int gburst_size;
 123   int vburst_size;
 124   char vid_en;
 125   char gr_en;
 126   int wcmocc, wcgocc, wcvocc, wcvlwm, wcglwm;
 127   int by_gfacc;
 128   char vid_only_once;
 129   char gr_only_once;
 130   char first_vacc;
 131   char first_gacc;
 132   char first_macc;
 133   int vocc;
 134   int gocc;
 135   int mocc;
 136   char cur;
 137   char engine_en;
 138   char converged;
 139   int priority;
 140 } nv3_arb_info;
 141 typedef struct {
 142   int graphics_lwm;
 143   int video_lwm;
 144   int graphics_burst_size;
 145   int video_burst_size;
 146   int graphics_hi_priority;
 147   int media_hi_priority;
 148   int rtl_values;
 149   int valid;
 150 } nv3_fifo_info;
 151 typedef struct {
 152   char pix_bpp;
 153   char enable_video;
 154   char gr_during_vid;
 155   char enable_mp;
 156   int memory_width;
 157   int video_scale;
 158   int pclk_khz;
 159   int mclk_khz;
 160   int mem_page_miss;
 161   int mem_latency;
 162   char mem_aligned;
 163 } nv3_sim_state;
 164 static int nv3_iterate(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
 165 {
 166     int iter = 0;
 167     int tmp;
 168     int vfsize, mfsize, gfsize;
 169     int mburst_size = 32;
 170     int mmisses, gmisses, vmisses;
 171     int misses;
 172     int vlwm, glwm;
 173     int last, next, cur;
 174     int max_gfsize ;
 175     long ns;
 176
 177     vlwm = 0;
 178     glwm = 0;
 179     vfsize = 0;
 180     gfsize = 0;
 181     cur = ainfo->cur;
 182     mmisses = 2;
 183     gmisses = 2;
 184     vmisses = 2;
 185     if (ainfo->gburst_size == 128) max_gfsize = GFIFO_SIZE_128;
 186     else  max_gfsize = GFIFO_SIZE;
 187     max_gfsize = GFIFO_SIZE;
 188     while (1)
 189     {
 190         if (ainfo->vid_en)
 191         {
 192             if (ainfo->wcvocc > ainfo->vocc) ainfo->wcvocc = ainfo->vocc;
 193             if (ainfo->wcvlwm > vlwm) ainfo->wcvlwm = vlwm ;
 194             ns = 1000000 * ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz;
 195             vfsize = ns * ainfo->vdrain_rate / 1000000;
 196             vfsize =  ainfo->wcvlwm - ainfo->vburst_size + vfsize;
 197         }
 198         if (state->enable_mp)
 199         {
 200             if (ainfo->wcmocc > ainfo->mocc) ainfo->wcmocc = ainfo->mocc;
 201         }
 202         if (ainfo->gr_en)
 203         {
 204             if (ainfo->wcglwm > glwm) ainfo->wcglwm = glwm ;
 205             if (ainfo->wcgocc > ainfo->gocc) ainfo->wcgocc = ainfo->gocc;
 206             ns = 1000000 * (ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz;
 207             gfsize = (ns * (long) ainfo->gdrain_rate)/1000000;
 208             gfsize = ainfo->wcglwm - ainfo->gburst_size + gfsize;
 209         }
 210         mfsize = 0;
 211         if (!state->gr_during_vid && ainfo->vid_en)
 212             if (ainfo->vid_en && (ainfo->vocc < 0) && !ainfo->vid_only_once)
 213                 next = VIDEO;
 214             else if (ainfo->mocc < 0)
 215                 next = MPORT;
 216             else if (ainfo->gocc< ainfo->by_gfacc)
 217                 next = GRAPHICS;
 218             else return (0);
 219         else switch (ainfo->priority)
 220             {
 221                 case VIDEO:
 222                     if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)
 223                         next = VIDEO;
 224                     else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)
 225                         next = GRAPHICS;
 226                     else if (ainfo->mocc<0)
 227                         next = MPORT;
 228                     else    return (0);
 229                     break;
 230                 case GRAPHICS:
 231                     if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)
 232                         next = GRAPHICS;
 233                     else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)
 234                         next = VIDEO;
 235                     else if (ainfo->mocc<0)
 236                         next = MPORT;
 237                     else    return (0);
 238                     break;
 239                 default:
 240                     if (ainfo->mocc<0)
 241                         next = MPORT;
 242                     else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)
 243                         next = GRAPHICS;
 244                     else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)
 245                         next = VIDEO;
 246                     else    return (0);
 247                     break;
 248             }
 249         last = cur;
 250         cur = next;
 251         iter++;
 252         switch (cur)
 253         {
 254             case VIDEO:
 255                 if (last==cur)    misses = 0;
 256                 else if (ainfo->first_vacc)   misses = vmisses;
 257                 else    misses = 1;
 258                 ainfo->first_vacc = 0;
 259                 if (last!=cur)
 260                 {
 261                     ns =  1000000 * (vmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz;
 262                     vlwm = ns * ainfo->vdrain_rate/ 1000000;
 263                     vlwm = ainfo->vocc - vlwm;
 264                 }
 265                 ns = 1000000*(misses*state->mem_page_miss + ainfo->vburst_size)/(state->memory_width/8)/state->mclk_khz;
 266                 ainfo->vocc = ainfo->vocc + ainfo->vburst_size - ns*ainfo->vdrain_rate/1000000;
 267                 ainfo->gocc = ainfo->gocc - ns*ainfo->gdrain_rate/1000000;
 268                 ainfo->mocc = ainfo->mocc - ns*ainfo->mdrain_rate/1000000;
 269                 break;
 270             case GRAPHICS:
 271                 if (last==cur)    misses = 0;
 272                 else if (ainfo->first_gacc)   misses = gmisses;
 273                 else    misses = 1;
 274                 ainfo->first_gacc = 0;
 275                 if (last!=cur)
 276                 {
 277                     ns = 1000000*(gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz ;
 278                     glwm = ns * ainfo->gdrain_rate/1000000;
 279                     glwm = ainfo->gocc - glwm;
 280                 }
 281                 ns = 1000000*(misses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz;
 282                 ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000;
 283                 ainfo->gocc = ainfo->gocc + ainfo->gburst_size - ns*ainfo->gdrain_rate/1000000;
 284                 ainfo->mocc = ainfo->mocc + 0 - ns*ainfo->mdrain_rate/1000000;
 285                 break;
 286             default:
 287                 if (last==cur)    misses = 0;
 288                 else if (ainfo->first_macc)   misses = mmisses;
 289                 else    misses = 1;
 290                 ainfo->first_macc = 0;
 291                 ns = 1000000*(misses*state->mem_page_miss + mburst_size/(state->memory_width/8))/state->mclk_khz;
 292                 ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000;
 293                 ainfo->gocc = ainfo->gocc + 0 - ns*ainfo->gdrain_rate/1000000;
 294                 ainfo->mocc = ainfo->mocc + mburst_size - ns*ainfo->mdrain_rate/1000000;
 295                 break;
 296         }
 297         if (iter>100)
 298         {
 299             ainfo->converged = 0;
 300             return (1);
 301         }
 302         ns = 1000000*ainfo->gburst_size/(state->memory_width/8)/state->mclk_khz;
 303         tmp = ns * ainfo->gdrain_rate/1000000;
 304         if (ABS(ainfo->gburst_size) + ((ABS(ainfo->wcglwm) + 16 ) & ~0x7) - tmp > max_gfsize)
 305         {
 306             ainfo->converged = 0;
 307             return (1);
 308         }
 309         ns = 1000000*ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz;
 310         tmp = ns * ainfo->vdrain_rate/1000000;
 311         if (ABS(ainfo->vburst_size) + (ABS(ainfo->wcvlwm + 32) & ~0xf)  - tmp> VFIFO_SIZE)
 312         {
 313             ainfo->converged = 0;
 314             return (1);
 315         }
 316         if (ABS(ainfo->gocc) > max_gfsize)
 317         {
 318             ainfo->converged = 0;
 319             return (1);
 320         }
 321         if (ABS(ainfo->vocc) > VFIFO_SIZE)
 322         {
 323             ainfo->converged = 0;
 324             return (1);
 325         }
 326         if (ABS(ainfo->mocc) > MFIFO_SIZE)
 327         {
 328             ainfo->converged = 0;
 329             return (1);
 330         }
 331         if (ABS(vfsize) > VFIFO_SIZE)
 332         {
 333             ainfo->converged = 0;
 334             return (1);
 335         }
 336         if (ABS(gfsize) > max_gfsize)
 337         {
 338             ainfo->converged = 0;
 339             return (1);
 340         }
 341         if (ABS(mfsize) > MFIFO_SIZE)
 342         {
 343             ainfo->converged = 0;
 344             return (1);
 345         }
 346     }
 347 }
 348 static char nv3_arb(nv3_fifo_info * res_info, nv3_sim_state * state,  nv3_arb_info *ainfo)
 349 {
 350     long ens, vns, mns, gns;
 351     int mmisses, gmisses, vmisses, eburst_size, mburst_size;
 352     int refresh_cycle;
 353
 354     refresh_cycle = 0;
 355     refresh_cycle = 2*(state->mclk_khz/state->pclk_khz) + 5;
 356     mmisses = 2;
 357     if (state->mem_aligned) gmisses = 2;
 358     else    gmisses = 3;
 359     vmisses = 2;
 360     eburst_size = state->memory_width * 1;
 361     mburst_size = 32;
 362     gns = 1000000 * (gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz;
 363     ainfo->by_gfacc = gns*ainfo->gdrain_rate/1000000;
 364     ainfo->wcmocc = 0;
 365     ainfo->wcgocc = 0;
 366     ainfo->wcvocc = 0;
 367     ainfo->wcvlwm = 0;
 368     ainfo->wcglwm = 0;
 369     ainfo->engine_en = 1;
 370     ainfo->converged = 1;
 371     if (ainfo->engine_en)
 372     {
 373         ens =  1000000*(state->mem_page_miss + eburst_size/(state->memory_width/8) +refresh_cycle)/state->mclk_khz;
 374         ainfo->mocc = state->enable_mp ? 0-ens*ainfo->mdrain_rate/1000000 : 0;
 375         ainfo->vocc = ainfo->vid_en ? 0-ens*ainfo->vdrain_rate/1000000 : 0;
 376         ainfo->gocc = ainfo->gr_en ? 0-ens*ainfo->gdrain_rate/1000000 : 0;
 377         ainfo->cur = ENGINE;
 378         ainfo->first_vacc = 1;
 379         ainfo->first_gacc = 1;
 380         ainfo->first_macc = 1;
 381         nv3_iterate(res_info, state,ainfo);
 382     }
 383     if (state->enable_mp)
 384     {
 385         mns = 1000000 * (mmisses*state->mem_page_miss + mburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
 386         ainfo->mocc = state->enable_mp ? 0 : mburst_size - mns*ainfo->mdrain_rate/1000000;
 387         ainfo->vocc = ainfo->vid_en ? 0 : 0- mns*ainfo->vdrain_rate/1000000;
 388         ainfo->gocc = ainfo->gr_en ? 0: 0- mns*ainfo->gdrain_rate/1000000;
 389         ainfo->cur = MPORT;
 390         ainfo->first_vacc = 1;
 391         ainfo->first_gacc = 1;
 392         ainfo->first_macc = 0;
 393         nv3_iterate(res_info, state,ainfo);
 394     }
 395     if (ainfo->gr_en)
 396     {
 397         ainfo->first_vacc = 1;
 398         ainfo->first_gacc = 0;
 399         ainfo->first_macc = 1;
 400         gns = 1000000*(gmisses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
 401         ainfo->gocc = ainfo->gburst_size - gns*ainfo->gdrain_rate/1000000;
 402         ainfo->vocc = ainfo->vid_en? 0-gns*ainfo->vdrain_rate/1000000 : 0;
 403         ainfo->mocc = state->enable_mp ?  0-gns*ainfo->mdrain_rate/1000000: 0;
 404         ainfo->cur = GRAPHICS;
 405         nv3_iterate(res_info, state,ainfo);
 406     }
 407     if (ainfo->vid_en)
 408     {
 409         ainfo->first_vacc = 0;
 410         ainfo->first_gacc = 1;
 411         ainfo->first_macc = 1;
 412         vns = 1000000*(vmisses*state->mem_page_miss + ainfo->vburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
 413         ainfo->vocc = ainfo->vburst_size - vns*ainfo->vdrain_rate/1000000;
 414         ainfo->gocc = ainfo->gr_en? (0-vns*ainfo->gdrain_rate/1000000) : 0;
 415         ainfo->mocc = state->enable_mp? 0-vns*ainfo->mdrain_rate/1000000 :0 ;
 416         ainfo->cur = VIDEO;
 417         nv3_iterate(res_info, state, ainfo);
 418     }
 419     if (ainfo->converged)
 420     {
 421         res_info->graphics_lwm = (int)ABS(ainfo->wcglwm) + 16;
 422         res_info->video_lwm = (int)ABS(ainfo->wcvlwm) + 32;
 423         res_info->graphics_burst_size = ainfo->gburst_size;
 424         res_info->video_burst_size = ainfo->vburst_size;
 425         res_info->graphics_hi_priority = (ainfo->priority == GRAPHICS);
 426         res_info->media_hi_priority = (ainfo->priority == MPORT);
 427         if (res_info->video_lwm > 160)
 428         {
 429             res_info->graphics_lwm = 256;
 430             res_info->video_lwm = 128;
 431             res_info->graphics_burst_size = 64;
 432             res_info->video_burst_size = 64;
 433             res_info->graphics_hi_priority = 0;
 434             res_info->media_hi_priority = 0;
 435             ainfo->converged = 0;
 436             return (0);
 437         }
 438         if (res_info->video_lwm > 128)
 439         {
 440             res_info->video_lwm = 128;
 441         }
 442         return (1);
 443     }
 444     else
 445     {
 446         res_info->graphics_lwm = 256;
 447         res_info->video_lwm = 128;
 448         res_info->graphics_burst_size = 64;
 449         res_info->video_burst_size = 64;
 450         res_info->graphics_hi_priority = 0;
 451         res_info->media_hi_priority = 0;
 452         return (0);
 453     }
 454 }
 455 static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
 456 {
 457     int done, g,v, p;
 458
 459     done = 0;
 460     for (p=0; p < 2; p++)
 461     {
 462         for (g=128 ; g > 32; g= g>> 1)
 463         {
 464             for (v=128; v >=32; v = v>> 1)
 465             {
 466                 ainfo->priority = p;
 467                 ainfo->gburst_size = g;
 468                 ainfo->vburst_size = v;
 469                 done = nv3_arb(res_info, state,ainfo);
 470                 if (done && (g==128))
 471                     if ((res_info->graphics_lwm + g) > 256)
 472                         done = 0;
 473                 if (done)
 474                     goto Done;
 475             }
 476         }
 477     }
 478
 479  Done:
 480     return done;
 481 }
 482 static void nv3CalcArbitration
 483 (
 484     nv3_fifo_info * res_info,
 485     nv3_sim_state * state
 486 )
 487 {
 488     nv3_fifo_info save_info;
 489     nv3_arb_info ainfo;
 490     char   res_gr, res_vid;
 491
 492     ainfo.gr_en = 1;
 493     ainfo.vid_en = state->enable_video;
 494     ainfo.vid_only_once = 0;
 495     ainfo.gr_only_once = 0;
 496     ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8);
 497     ainfo.vdrain_rate = (int) state->pclk_khz * 2;
 498     if (state->video_scale != 0)
 499         ainfo.vdrain_rate = ainfo.vdrain_rate/state->video_scale;
 500     ainfo.mdrain_rate = 33000;
 501     res_info->rtl_values = 0;
 502     if (!state->gr_during_vid && state->enable_video)
 503     {
 504         ainfo.gr_only_once = 1;
 505         ainfo.gr_en = 1;
 506         ainfo.gdrain_rate = 0;
 507         res_vid = nv3_get_param(res_info, state,  &ainfo);
 508         res_vid = ainfo.converged;
 509         save_info.video_lwm = res_info->video_lwm;
 510         save_info.video_burst_size = res_info->video_burst_size;
 511         ainfo.vid_en = 1;
 512         ainfo.vid_only_once = 1;
 513         ainfo.gr_en = 1;
 514         ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8);
 515         ainfo.vdrain_rate = 0;
 516         res_gr = nv3_get_param(res_info, state,  &ainfo);
 517         res_gr = ainfo.converged;
 518         res_info->video_lwm = save_info.video_lwm;
 519         res_info->video_burst_size = save_info.video_burst_size;
 520         res_info->valid = res_gr & res_vid;
 521     }
 522     else
 523     {
 524         if (!ainfo.gr_en) ainfo.gdrain_rate = 0;
 525         if (!ainfo.vid_en) ainfo.vdrain_rate = 0;
 526         res_gr = nv3_get_param(res_info, state,  &ainfo);
 527         res_info->valid = ainfo.converged;
 528     }
 529 }
 530 static void nv3UpdateArbitrationSettings
 531 (
 532     unsigned      VClk,
 533     unsigned      pixelDepth,
 534     unsigned     *burst,
 535     unsigned     *lwm,
 536     RIVA_HW_INST *chip
 537 )
 538 {
 539     nv3_fifo_info fifo_data;
 540     nv3_sim_state sim_data;
 541     unsigned int M, N, P, pll, MClk;
 542
 543     pll = chip->PRAMDAC[0x00000504/4];
 544     M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
 545     MClk = (N * chip->CrystalFreqKHz / M) >> P;
 546     sim_data.pix_bpp        = (char)pixelDepth;
 547     sim_data.enable_video   = 0;
 548     sim_data.enable_mp      = 0;
 549     sim_data.video_scale    = 1;
 550     sim_data.memory_width   = (chip->PEXTDEV[0x00000000/4] & 0x10) ? 128 : 64;
 551     sim_data.memory_width   = 128;
 552
 553     sim_data.mem_latency    = 9;
 554     sim_data.mem_aligned    = 1;
 555     sim_data.mem_page_miss  = 11;
 556     sim_data.gr_during_vid  = 0;
 557     sim_data.pclk_khz       = VClk;
 558     sim_data.mclk_khz       = MClk;
 559     nv3CalcArbitration(&fifo_data, &sim_data);
 560     if (fifo_data.valid)
 561     {
 562         int  b = fifo_data.graphics_burst_size >> 4;
 563         *burst = 0;
 564         while (b >>= 1) (*burst)++;
 565         *lwm   = fifo_data.graphics_lwm >> 3;
 566     }
 567     else
 568     {
 569         *lwm   = 0x24;
 570         *burst = 0x2;
 571     }
 572 }
 573
 574 /****************************************************************************\
 575 *                                                                            *
 576 *                          RIVA Mode State Routines                          *
 577 *                                                                            *
 578 \****************************************************************************/
 579
 580 /*
 581  * Calculate the Video Clock parameters for the PLL.
 582  */
 583 static int CalcVClock
 584 (
 585     int           clockIn,
 586     int          *clockOut,
 587     int          *mOut,
 588     int          *nOut,
 589     int          *pOut,
 590     RIVA_HW_INST *chip
 591 )
 592 {
 593     unsigned lowM, highM, highP;
 594     unsigned DeltaNew, DeltaOld;
 595     unsigned VClk, Freq;
 596     unsigned M, N, P;
 597
 598     DeltaOld = 0xFFFFFFFF;
 599
 600     VClk     = (unsigned)clockIn;
 601
 602     if (chip->CrystalFreqKHz == 13500)
 603     {
 604         lowM  = 7;
 605         highM = 12;
 606     }
 607     else
 608     {
 609         lowM  = 8;
 610         highM = 13;
 611     }
 612
 613     highP = 3;
 614     for (P = 0; P <= highP; P ++)
 615     {
 616         Freq = VClk << P;
 617         if ((Freq >= 128000) && (Freq <= chip->MaxVClockFreqKHz))
 618         {
 619             for (M = lowM; M <= highM; M++)
 620             {
 621                 N    = (VClk << P) * M / chip->CrystalFreqKHz;
 622                 if(N <= 255) {
 623                     Freq = (chip->CrystalFreqKHz * N / M) >> P;
 624                     if (Freq > VClk)
 625                         DeltaNew = Freq - VClk;
 626                     else
 627                         DeltaNew = VClk - Freq;
 628                     if (DeltaNew < DeltaOld)
 629                     {
 630                         *mOut     = M;
 631                         *nOut     = N;
 632                         *pOut     = P;
 633                         *clockOut = Freq;
 634                         DeltaOld  = DeltaNew;
 635                     }
 636                 }
 637             }
 638         }
 639     }
 640     return (DeltaOld != 0xFFFFFFFF);
 641 }
 642 /*
 643  * Calculate extended mode parameters (SVGA) and save in a
 644  * mode state structure.
 645  */
 646 static void CalcStateExt
 647 (
 648     RIVA_HW_INST  *chip,
 649     RIVA_HW_STATE *state,
 650     int            bpp,
 651     int            width,
 652     int            hDisplaySize,
 653     int            height,
 654     int            dotClock,
 655     int            flags
 656 )
 657 {
 658     int pixelDepth, VClk, m, n, p;
 659     /*
 660      * Save mode parameters.
 661      */
 662     state->bpp    = bpp;    /* this is not bitsPerPixel, it's 8,15,16,32 */
 663     state->width  = width;
 664     state->height = height;
 665     /*
 666      * Extended RIVA registers.
 667      */
 668     pixelDepth = (bpp + 1)/8;
 669     CalcVClock(dotClock, &VClk, &m, &n, &p, chip);
 670
 671     nv3UpdateArbitrationSettings(VClk,
 672                                  pixelDepth * 8,
 673                                  &(state->arbitration0),
 674                                  &(state->arbitration1),
 675                                  chip);
 676     state->cursor0  = 0x00;
 677     state->cursor1  = 0x78;
 678     if (flags & V_DBLSCAN)
 679        state->cursor1 |= 2;
 680     state->cursor2  = 0x00000000;
 681     state->pllsel   = 0x10010100;
 682     state->config   = ((width + 31)/32)
 683                       | (((pixelDepth > 2) ? 3 : pixelDepth) << 8)
 684                       | 0x1000;
 685     state->general  = 0x00100100;
 686     state->repaint1 = hDisplaySize < 1280 ? 0x06 : 0x02;
 687
 688
 689     state->vpll     = (p << 16) | (n << 8) | m;
 690     state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3;
 691     state->pixel    = pixelDepth > 2   ? 3    : pixelDepth;
 692     state->offset   = 0;
 693     state->pitch    = pixelDepth * width;
 694 }
 695 /*
 696  * Load fixed function state and pre-calculated/stored state.
 697  */
 698 #define LOAD_FIXED_STATE(tbl,dev)                                       \
 699     for (i = 0; i < sizeof(tbl##Table##dev)/8; i++)                 \
 700         chip->dev[tbl##Table##dev[i][0]] = tbl##Table##dev[i][1]
 701 #define LOAD_FIXED_STATE_8BPP(tbl,dev)                                  \
 702     for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++)            \
 703         chip->dev[tbl##Table##dev##_8BPP[i][0]] = tbl##Table##dev##_8BPP[i][1]
 704 #define LOAD_FIXED_STATE_15BPP(tbl,dev)                                 \
 705     for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++)           \
 706         chip->dev[tbl##Table##dev##_15BPP[i][0]] = tbl##Table##dev##_15BPP[i][1]
 707 #define LOAD_FIXED_STATE_16BPP(tbl,dev)                                 \
 708     for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++)           \
 709         chip->dev[tbl##Table##dev##_16BPP[i][0]] = tbl##Table##dev##_16BPP[i][1]
 710 #define LOAD_FIXED_STATE_32BPP(tbl,dev)                                 \
 711     for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++)           \
 712         chip->dev[tbl##Table##dev##_32BPP[i][0]] = tbl##Table##dev##_32BPP[i][1]
 713 static void UpdateFifoState
 714 (
 715     RIVA_HW_INST  *chip
 716 )
 717 {
 718 }
 719 static void LoadStateExt
 720 (
 721     RIVA_HW_INST  *chip,
 722     RIVA_HW_STATE *state
 723 )
 724 {
 725     int i;
 726
 727     /*
 728      * Load HW fixed function state.
 729      */
 730     LOAD_FIXED_STATE(Riva,PMC);
 731     LOAD_FIXED_STATE(Riva,PTIMER);
 732      /*
 733       * Make sure frame buffer config gets set before loading PRAMIN.
 734       */
 735     chip->PFB[0x00000200/4] = state->config;
 736     LOAD_FIXED_STATE(nv3,PFIFO);
 737     LOAD_FIXED_STATE(nv3,PRAMIN);
 738     LOAD_FIXED_STATE(nv3,PGRAPH);
 739     switch (state->bpp)
 740     {
 741      case 15:
 742      case 16:
 743          LOAD_FIXED_STATE_15BPP(nv3,PRAMIN);
 744          LOAD_FIXED_STATE_15BPP(nv3,PGRAPH);
 745          break;
 746      case 24:
 747      case 32:
 748          LOAD_FIXED_STATE_32BPP(nv3,PRAMIN);
 749          LOAD_FIXED_STATE_32BPP(nv3,PGRAPH);
 750          break;
 751      case 8:
 752      default:
 753          LOAD_FIXED_STATE_8BPP(nv3,PRAMIN);
 754         LOAD_FIXED_STATE_8BPP(nv3,PGRAPH);
 755         break;
 756     }
 757     for (i = 0x00000; i < 0x00800; i++)
 758         chip->PRAMIN[0x00000502 + i] = (i << 12) | 0x03;
 759     chip->PGRAPH[0x00000630/4] = state->offset;
 760     chip->PGRAPH[0x00000634/4] = state->offset;
 761     chip->PGRAPH[0x00000638/4] = state->offset;
 762     chip->PGRAPH[0x0000063C/4] = state->offset;
 763     chip->PGRAPH[0x00000650/4] = state->pitch;
 764     chip->PGRAPH[0x00000654/4] = state->pitch;
 765     chip->PGRAPH[0x00000658/4] = state->pitch;
 766     chip->PGRAPH[0x0000065C/4] = state->pitch;
 767
 768     LOAD_FIXED_STATE(Riva,FIFO);
 769     UpdateFifoState(chip);
 770
 771     /*
 772      * Load HW mode state.
 773      */
 774     VGA_WR08(chip->PCIO, 0x03D4, 0x19);
 775     VGA_WR08(chip->PCIO, 0x03D5, state->repaint0);
 776     VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
 777     VGA_WR08(chip->PCIO, 0x03D5, state->repaint1);
 778     VGA_WR08(chip->PCIO, 0x03D4, 0x25);
 779     VGA_WR08(chip->PCIO, 0x03D5, state->screen);
 780     VGA_WR08(chip->PCIO, 0x03D4, 0x28);
 781     VGA_WR08(chip->PCIO, 0x03D5, state->pixel);
 782     VGA_WR08(chip->PCIO, 0x03D4, 0x2D);
 783     VGA_WR08(chip->PCIO, 0x03D5, state->horiz);
 784     VGA_WR08(chip->PCIO, 0x03D4, 0x1B);
 785     VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0);
 786     VGA_WR08(chip->PCIO, 0x03D4, 0x20);
 787     VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1);
 788     VGA_WR08(chip->PCIO, 0x03D4, 0x30);
 789     VGA_WR08(chip->PCIO, 0x03D5, state->cursor0);
 790     VGA_WR08(chip->PCIO, 0x03D4, 0x31);
 791     VGA_WR08(chip->PCIO, 0x03D5, state->cursor1);
 792     VGA_WR08(chip->PCIO, 0x03D4, 0x2F);
 793     VGA_WR08(chip->PCIO, 0x03D5, state->cursor2);
 794     VGA_WR08(chip->PCIO, 0x03D4, 0x39);
 795     VGA_WR08(chip->PCIO, 0x03D5, state->interlace);
 796
 797     chip->PRAMDAC[0x00000508/4] = state->vpll;
 798     chip->PRAMDAC[0x0000050C/4] = state->pllsel;
 799     chip->PRAMDAC[0x00000600/4]  = state->general;
 800
 801     /*
 802      * Turn off VBlank enable and reset.
 803      */
 804     chip->PCRTC[0x00000140/4] = 0;
 805     chip->PCRTC[0x00000100/4] = chip->VBlankBit;
 806     /*
 807      * Set interrupt enable.
 808      */
 809     chip->PMC[0x00000140/4]  = chip->EnableIRQ & 0x01;
 810     /*
 811      * Set current state pointer.
 812      */
 813     chip->CurrentState = state;
 814     /*
 815      * Reset FIFO free and empty counts.
 816      */
 817     chip->FifoFreeCount  = 0;
 818     /* Free count from first subchannel */
 819     chip->FifoEmptyCount = chip->Rop->FifoFree;
 820 }
 821
 822 static void UnloadStateExt
 823 (
 824     RIVA_HW_INST  *chip,
 825     RIVA_HW_STATE *state
 826 )
 827 {
 828     /*
 829      * Save current HW state.
 830      */
 831     VGA_WR08(chip->PCIO, 0x03D4, 0x19);
 832     state->repaint0     = VGA_RD08(chip->PCIO, 0x03D5);
 833     VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
 834     state->repaint1     = VGA_RD08(chip->PCIO, 0x03D5);
 835     VGA_WR08(chip->PCIO, 0x03D4, 0x25);
 836     state->screen       = VGA_RD08(chip->PCIO, 0x03D5);
 837     VGA_WR08(chip->PCIO, 0x03D4, 0x28);
 838     state->pixel        = VGA_RD08(chip->PCIO, 0x03D5);
 839     VGA_WR08(chip->PCIO, 0x03D4, 0x2D);
 840     state->horiz        = VGA_RD08(chip->PCIO, 0x03D5);
 841     VGA_WR08(chip->PCIO, 0x03D4, 0x1B);
 842     state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5);
 843     VGA_WR08(chip->PCIO, 0x03D4, 0x20);
 844     state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5);
 845     VGA_WR08(chip->PCIO, 0x03D4, 0x30);
 846     state->cursor0      = VGA_RD08(chip->PCIO, 0x03D5);
 847     VGA_WR08(chip->PCIO, 0x03D4, 0x31);
 848     state->cursor1      = VGA_RD08(chip->PCIO, 0x03D5);
 849     VGA_WR08(chip->PCIO, 0x03D4, 0x2F);
 850     state->cursor2      = VGA_RD08(chip->PCIO, 0x03D5);
 851     VGA_WR08(chip->PCIO, 0x03D4, 0x39);
 852     state->interlace    = VGA_RD08(chip->PCIO, 0x03D5);
 853     state->vpll         = chip->PRAMDAC[0x00000508/4];
 854     state->pllsel       = chip->PRAMDAC[0x0000050C/4];
 855     state->general      = chip->PRAMDAC[0x00000600/4];
 856     state->config       = chip->PFB[0x00000200/4];
 857     state->offset       = chip->PGRAPH[0x00000630/4];
 858     state->pitch        = chip->PGRAPH[0x00000650/4];
 859 }
 860
 861 static void SetStartAddress
 862 (
 863     RIVA_HW_INST *chip,
 864     unsigned      start
 865 )
 866 {
 867     int offset = start >> 2;
 868     int pan    = (start & 3) << 1;
 869     unsigned char tmp;
 870
 871     /*
 872      * Unlock extended registers.
 873      */
 874     chip->LockUnlock(chip, 0);
 875     /*
 876      * Set start address.
 877      */
 878     VGA_WR08(chip->PCIO, 0x3D4, 0x0D); VGA_WR08(chip->PCIO, 0x3D5, offset);
 879     offset >>= 8;
 880     VGA_WR08(chip->PCIO, 0x3D4, 0x0C); VGA_WR08(chip->PCIO, 0x3D5, offset);
 881     offset >>= 8;
 882     VGA_WR08(chip->PCIO, 0x3D4, 0x19); tmp = VGA_RD08(chip->PCIO, 0x3D5);
 883     VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x01F) | (tmp & ~0x1F));
 884     VGA_WR08(chip->PCIO, 0x3D4, 0x2D); tmp = VGA_RD08(chip->PCIO, 0x3D5);
 885     VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x60) | (tmp & ~0x60));
 886     /*
 887      * 4 pixel pan register.
 888      */
 889     offset = VGA_RD08(chip->PCIO, chip->IO + 0x0A);
 890     VGA_WR08(chip->PCIO, 0x3C0, 0x13);
 891     VGA_WR08(chip->PCIO, 0x3C0, pan);
 892 }
 893 /****************************************************************************\
 894 *                                                                            *
 895 *                      Probe RIVA Chip Configuration                         *
 896 *                                                                            *
 897 \****************************************************************************/
 898
 899 static void nv3GetConfig
 900 (
 901     RIVA_HW_INST *chip
 902 )
 903 {
 904     /*
 905      * Fill in chip configuration.
 906      */
 907     if (chip->PFB[0x00000000/4] & 0x00000020)
 908     {
 909         if (((chip->PMC[0x00000000/4] & 0xF0) == 0x20)
 910          && ((chip->PMC[0x00000000/4] & 0x0F) >= 0x02))
 911         {
 912             /*
 913              * SDRAM 128 ZX.
 914              */
 915             chip->RamBandwidthKBytesPerSec = 800000;
 916             switch (chip->PFB[0x00000000/4] & 0x03)
 917             {
 918                 case 2:
 919                     chip->RamAmountKBytes = 1024 * 4;
 920                     break;
 921                 case 1:
 922                     chip->RamAmountKBytes = 1024 * 2;
 923                     break;
 924                 default:
 925                     chip->RamAmountKBytes = 1024 * 8;
 926                     break;
 927             }
 928         }
 929         else
 930         {
 931             chip->RamBandwidthKBytesPerSec = 1000000;
 932             chip->RamAmountKBytes          = 1024 * 8;
 933         }
 934     }
 935     else
 936     {
 937         /*
 938          * SGRAM 128.
 939          */
 940         chip->RamBandwidthKBytesPerSec = 1000000;
 941         switch (chip->PFB[0x00000000/4] & 0x00000003)
 942         {
 943             case 0:
 944                 chip->RamAmountKBytes = 1024 * 8;
 945                 break;
 946             case 2:
 947                 chip->RamAmountKBytes = 1024 * 4;
 948                 break;
 949             default:
 950                 chip->RamAmountKBytes = 1024 * 2;
 951                 break;
 952         }
 953     }
 954     chip->CrystalFreqKHz   = (chip->PEXTDEV[0x00000000/4] & 0x00000040) ? 14318 : 13500;
 955     chip->CURSOR           = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]);
 956     chip->VBlankBit        = 0x00000100;
 957     chip->MaxVClockFreqKHz = 256000;
 958     /*
 959      * Set chip functions.
 960      */
 961     chip->Busy            = nv3Busy;
 962     chip->ShowHideCursor  = ShowHideCursor;
 963     chip->CalcStateExt    = CalcStateExt;
 964     chip->LoadStateExt    = LoadStateExt;
 965     chip->UnloadStateExt  = UnloadStateExt;
 966     chip->SetStartAddress = SetStartAddress;
 967     chip->LockUnlock      = nv3LockUnlock;
 968 }
 969 int RivaGetConfig
 970 (
 971     RivaPtr pRiva
 972 )
 973 {
 974     RIVA_HW_INST *chip = &pRiva->riva;
 975
 976     nv3GetConfig(chip);
 977     /*
 978      * Fill in FIFO pointers.
 979      */
 980     chip->Rop    = (RivaRop                 *)&(chip->FIFO[0x00000000/4]);
 981     chip->Clip   = (RivaClip                *)&(chip->FIFO[0x00002000/4]);
 982     chip->Patt   = (RivaPattern             *)&(chip->FIFO[0x00004000/4]);
 983     chip->Pixmap = (RivaPixmap              *)&(chip->FIFO[0x00006000/4]);
 984     chip->Blt    = (RivaScreenBlt           *)&(chip->FIFO[0x00008000/4]);
 985     chip->Bitmap = (RivaBitmap              *)&(chip->FIFO[0x0000A000/4]);
 986     chip->Line   = (RivaLine                *)&(chip->FIFO[0x0000C000/4]);
 987     return (0);
 988 }
 989