2 * Copyright 2003 NVIDIA, Corporation
3 * Copyright 2006 Dave Airlie
4 * Copyright 2007 Maarten Maathuis
5 * Copyright 2007-2008 Stuart Bennett
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
27 #include <X11/Xatom.h>
28 #include "nv_include.h"
30 #define MULTIPLE_ENCODERS(e) (e & (e - 1))
31 #define FOR_EACH_ENCODER_IN_CONNECTOR(i, c, e) for (i = 0; i < pNv->dcb_table.entries; i++) \
32 if (c->possible_encoders & (1 << i) && \
33 (e = &pNv->encoders[i]))
35 static int nv_output_ramdac_offset(struct nouveau_encoder *nv_encoder)
39 if (nv_encoder->dcb->or & (8 | OUTPUT_C))
41 if (nv_encoder->dcb->or & (8 | OUTPUT_B))
48 nv_load_detect(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder)
50 NVPtr pNv = NVPTR(pScrn);
51 uint32_t testval, regoffset = nv_output_ramdac_offset(nv_encoder);
52 uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput, saved_rtest_ctrl, temp;
53 int head, present = 0;
54 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
56 #define RGB_TEST_DATA(r,g,b) (r << 0 | g << 10 | b << 20)
57 testval = RGB_TEST_DATA(0x140, 0x140, 0x140); /* 0x94050140 */
58 if (pNv->VBIOS.dactestval)
59 testval = pNv->VBIOS.dactestval;
61 saved_rtest_ctrl = NVReadRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset);
62 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset,
63 saved_rtest_ctrl & ~NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF);
65 if (pNv->NVArch >= 0x17) {
66 saved_powerctrl_2 = nvReadMC(pNv, NV_PBUS_POWERCTRL_2);
68 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, saved_powerctrl_2 & 0xd7ffffff);
69 if (regoffset == 0x68) {
70 saved_powerctrl_4 = nvReadMC(pNv, NV_PBUS_POWERCTRL_4);
71 nvWriteMC(pNv, NV_PBUS_POWERCTRL_4, saved_powerctrl_4 & 0xffffffcf);
77 saved_routput = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset);
78 head = (saved_routput & 0x100) >> 8;
79 /* if there's a spare crtc, using it will minimise flicker for the case
80 * where the in-use crtc is in use by an off-chip tmds encoder */
81 if (xf86_config->crtc[head]->enabled && !xf86_config->crtc[head ^ 1]->enabled)
83 /* nv driver and nv31 use 0xfffffeee, nv34 and 6600 use 0xfffffece */
84 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset,
85 (saved_routput & 0xfffffece) | head << 8);
88 temp = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset);
89 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset, temp | 1);
91 NVWriteRAMDAC(pNv, head, NV_RAMDAC_TEST_DATA,
92 NV_PRAMDAC_TESTPOINT_DATA_NOTBLANK | testval);
93 temp = NVReadRAMDAC(pNv, head, NV_RAMDAC_TEST_CONTROL);
94 NVWriteRAMDAC(pNv, head, NV_RAMDAC_TEST_CONTROL,
95 temp | NV_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED);
98 present = NVReadRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset) &
99 NV_PRAMDAC_TEST_CONTROL_SENSEB_ALLHI;
101 temp = NVReadRAMDAC(pNv, head, NV_RAMDAC_TEST_CONTROL);
102 NVWriteRAMDAC(pNv, head, NV_RAMDAC_TEST_CONTROL,
103 temp & ~NV_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED);
104 NVWriteRAMDAC(pNv, head, NV_RAMDAC_TEST_DATA, 0);
106 /* bios does something more complex for restoring, but I think this is good enough */
107 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset, saved_routput);
108 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset, saved_rtest_ctrl);
109 if (pNv->NVArch >= 0x17) {
110 if (regoffset == 0x68)
111 nvWriteMC(pNv, NV_PBUS_POWERCTRL_4, saved_powerctrl_4);
112 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, saved_powerctrl_2);
116 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Load detected on output %c\n", '@' + ffs(nv_encoder->dcb->or));
124 update_output_fields(xf86OutputPtr output, struct nouveau_encoder *det_encoder)
126 struct nouveau_connector *nv_connector = to_nouveau_connector(output);
127 NVPtr pNv = NVPTR(output->scrn);
129 if (nv_connector->detected_encoder == det_encoder)
132 nv_connector->detected_encoder = det_encoder;
133 output->possible_crtcs = det_encoder->dcb->heads;
134 if (det_encoder->dcb->type == OUTPUT_LVDS || det_encoder->dcb->type == OUTPUT_TMDS) {
135 output->doubleScanAllowed = false;
136 output->interlaceAllowed = false;
138 output->doubleScanAllowed = true;
139 if (pNv->Architecture == NV_ARCH_20 ||
140 (pNv->Architecture == NV_ARCH_10 &&
141 (pNv->Chipset & 0x0ff0) != CHIPSET_NV10 &&
142 (pNv->Chipset & 0x0ff0) != CHIPSET_NV15))
144 output->interlaceAllowed = false;
146 output->interlaceAllowed = true;
150 static xf86OutputStatus
151 nv_output_detect(xf86OutputPtr output)
153 struct nouveau_connector *nv_connector = to_nouveau_connector(output);
154 ScrnInfoPtr pScrn = output->scrn;
155 NVPtr pNv = NVPTR(pScrn);
156 struct nouveau_encoder *det_encoder;
157 xf86OutputStatus ret = XF86OutputStatusDisconnected;
159 struct nouveau_encoder *find_encoder_by_type(NVOutputType type)
162 for (i = 0; i < pNv->dcb_table.entries; i++)
163 if (nv_connector->possible_encoders & (1 << i) &&
164 (type == OUTPUT_ANY || pNv->encoders[i].dcb->type == type))
165 return &pNv->encoders[i];
169 if (nv_connector->pDDCBus &&
170 (nv_connector->edid = xf86OutputGetEDID(output, nv_connector->pDDCBus),
171 xf86OutputSetEDID(output, nv_connector->edid), nv_connector->edid)) {
172 if (MULTIPLE_ENCODERS(nv_connector->possible_encoders)) {
173 if (nv_connector->edid->features.input_type)
174 det_encoder = find_encoder_by_type(OUTPUT_TMDS);
176 det_encoder = find_encoder_by_type(OUTPUT_ANALOG);
178 det_encoder = find_encoder_by_type(OUTPUT_ANY);
179 ret = XF86OutputStatusConnected;
180 } else if ((det_encoder = find_encoder_by_type(OUTPUT_ANALOG))) {
181 /* we don't have a load det function for early cards */
182 if (!pNv->twoHeads || pNv->NVArch == 0x11)
183 ret = XF86OutputStatusUnknown;
184 else if (pNv->twoHeads && nv_load_detect(pScrn, det_encoder))
185 ret = XF86OutputStatusConnected;
186 } else if ((det_encoder = find_encoder_by_type(OUTPUT_LVDS))) {
187 if (det_encoder->dcb->lvdsconf.use_straps_for_mode &&
188 pNv->VBIOS.fp.native_mode)
189 ret = XF86OutputStatusConnected;
190 if (pNv->VBIOS.fp.edid) {
191 nv_connector->edid = xf86InterpretEDID(pScrn->scrnIndex, pNv->VBIOS.fp.edid);
192 xf86OutputSetEDID(output, nv_connector->edid);
193 ret = XF86OutputStatusConnected;
197 if (ret != XF86OutputStatusDisconnected)
198 update_output_fields(output, det_encoder);
203 static DisplayModePtr
204 get_native_mode_from_edid(xf86OutputPtr output, DisplayModePtr edid_modes)
206 struct nouveau_connector *nv_connector = to_nouveau_connector(output);
207 struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder;
208 ScrnInfoPtr pScrn = output->scrn;
209 int max_h_active = 0, max_v_active = 0;
213 for (i = 0; i < DET_TIMINGS; i++) {
214 /* We only look at detailed timings atm */
215 if (nv_connector->edid->det_mon[i].type != DT)
217 /* Selecting only based on width ok? */
218 if (nv_connector->edid->det_mon[i].section.d_timings.h_active > max_h_active) {
219 max_h_active = nv_connector->edid->det_mon[i].section.d_timings.h_active;
220 max_v_active = nv_connector->edid->det_mon[i].section.d_timings.v_active;
223 if (!(max_h_active && max_v_active)) {
224 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
225 "No EDID detailed timings available for finding native mode\n");
229 if (nv_encoder->native_mode) {
230 xfree(nv_encoder->native_mode);
231 nv_encoder->native_mode = NULL;
234 for (mode = edid_modes; mode != NULL; mode = mode->next) {
235 if (mode->HDisplay == max_h_active &&
236 mode->VDisplay == max_v_active) {
237 /* Take the preferred mode when it exists. */
238 if (mode->type & M_T_PREFERRED) {
239 nv_encoder->native_mode = xf86DuplicateMode(mode);
242 /* Find the highest refresh mode otherwise. */
243 if (!nv_encoder->native_mode || (mode->VRefresh > nv_encoder->native_mode->VRefresh)) {
244 if (nv_encoder->native_mode)
245 xfree(nv_encoder->native_mode);
246 mode->type |= M_T_PREFERRED;
247 nv_encoder->native_mode = xf86DuplicateMode(mode);
252 return nv_encoder->native_mode;
255 static DisplayModePtr
256 nv_output_get_edid_modes(xf86OutputPtr output)
258 struct nouveau_connector *nv_connector = to_nouveau_connector(output);
259 struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder;
260 ScrnInfoPtr pScrn = output->scrn;
261 DisplayModePtr edid_modes;
263 if (!(edid_modes = xf86OutputGetEDIDModes(output)))
266 if (nv_encoder->dcb->type == OUTPUT_TMDS || nv_encoder->dcb->type == OUTPUT_LVDS)
267 if (!get_native_mode_from_edid(output, edid_modes))
270 if (nv_encoder->dcb->type == OUTPUT_LVDS)
271 parse_lvds_manufacturer_table(pScrn, &NVPTR(pScrn)->VBIOS, nv_encoder->native_mode->Clock);
276 static DisplayModePtr
277 nv_lvds_output_get_modes(xf86OutputPtr output)
279 struct nouveau_connector *nv_connector = to_nouveau_connector(output);
280 struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder;
281 ScrnInfoPtr pScrn = output->scrn;
282 NVPtr pNv = NVPTR(pScrn);
283 DisplayModePtr modes;
285 /* panels only have one mode, and it doesn't change */
286 if (nv_encoder->native_mode)
287 return xf86DuplicateMode(nv_encoder->native_mode);
289 if ((modes = nv_output_get_edid_modes(output)))
292 if (!nv_encoder->dcb->lvdsconf.use_straps_for_mode || pNv->VBIOS.fp.native_mode == NULL)
295 nv_encoder->native_mode = xf86DuplicateMode(pNv->VBIOS.fp.native_mode);
297 return xf86DuplicateMode(pNv->VBIOS.fp.native_mode);
300 static int nv_output_mode_valid(xf86OutputPtr output, DisplayModePtr mode)
302 struct nouveau_encoder *nv_encoder = to_nouveau_connector(output)->detected_encoder;
303 NVPtr pNv = NVPTR(output->scrn);
305 if (!output->doubleScanAllowed && mode->Flags & V_DBLSCAN)
306 return MODE_NO_DBLESCAN;
307 if (!output->interlaceAllowed && mode->Flags & V_INTERLACE)
308 return MODE_NO_INTERLACE;
310 if (nv_encoder->dcb->type == OUTPUT_ANALOG) {
311 if (mode->Clock > (pNv->twoStagePLL ? 400000 : 350000))
312 return MODE_CLOCK_HIGH;
313 if (mode->Clock < 12000)
314 return MODE_CLOCK_LOW;
316 if (nv_encoder->dcb->type == OUTPUT_LVDS || nv_encoder->dcb->type == OUTPUT_TMDS)
317 /* No modes > panel's native res */
318 if (mode->HDisplay > nv_encoder->native_mode->HDisplay ||
319 mode->VDisplay > nv_encoder->native_mode->VDisplay)
321 if (nv_encoder->dcb->type == OUTPUT_TMDS) {
322 if (nv_encoder->dcb->duallink_possible) {
323 if (mode->Clock > 330000) /* 2x165 MHz */
324 return MODE_CLOCK_HIGH;
326 if (mode->Clock > 165000) /* 165 MHz */
327 return MODE_CLOCK_HIGH;
334 nv_output_destroy(xf86OutputPtr output)
336 struct nouveau_connector *nv_connector = to_nouveau_connector(output);
337 struct nouveau_encoder *nv_encoder;
338 ScrnInfoPtr pScrn = output->scrn;
339 NVPtr pNv = NVPTR(output->scrn);
342 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s called\n", __func__);
347 if (nv_connector->edid)
348 xfree(nv_connector->edid);
349 FOR_EACH_ENCODER_IN_CONNECTOR(i, nv_connector, nv_encoder)
350 if (nv_encoder->native_mode)
351 xfree(nv_encoder->native_mode);
355 static Atom scaling_mode_atom;
356 #define SCALING_MODE_NAME "SCALING_MODE"
357 static const struct {
359 enum scaling_modes mode;
361 { "panel", SCALE_PANEL },
362 { "fullscreen", SCALE_FULLSCREEN },
363 { "aspect", SCALE_ASPECT },
364 { "noscale", SCALE_NOSCALE },
365 { NULL, SCALE_INVALID}
368 static Atom dithering_atom;
369 #define DITHERING_MODE_NAME "DITHERING"
372 nv_output_create_resources(xf86OutputPtr output)
374 struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
375 ScrnInfoPtr pScrn = output->scrn;
376 INT32 dithering_range[2] = { 0, 1 };
379 /* may be called before encoder is picked, resources will be created
380 * by update_output_fields()
385 /* no properties for vga */
386 if (nv_encoder->dcb->type == OUTPUT_ANALOG)
390 * Setup scaling mode property.
392 scaling_mode_atom = MakeAtom(SCALING_MODE_NAME, sizeof(SCALING_MODE_NAME) - 1, TRUE);
394 error = RRConfigureOutputProperty(output->randr_output,
395 scaling_mode_atom, TRUE, FALSE, FALSE,
399 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
400 "RRConfigureOutputProperty error, %d\n", error);
403 char *existing_scale_name = NULL;
404 for (i = 0; scaling_mode[i].name; i++)
405 if (scaling_mode[i].mode == nv_encoder->scaling_mode)
406 existing_scale_name = scaling_mode[i].name;
408 error = RRChangeOutputProperty(output->randr_output, scaling_mode_atom,
409 XA_STRING, 8, PropModeReplace,
410 strlen(existing_scale_name),
411 existing_scale_name, FALSE, TRUE);
414 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
415 "Failed to set scaling mode, %d\n", error);
419 * Setup dithering property.
421 dithering_atom = MakeAtom(DITHERING_MODE_NAME, sizeof(DITHERING_MODE_NAME) - 1, TRUE);
423 error = RRConfigureOutputProperty(output->randr_output,
424 dithering_atom, TRUE, TRUE, FALSE,
428 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
429 "RRConfigureOutputProperty error, %d\n", error);
432 /* promote bool into int32 to make RandR DIX and big endian happy */
433 int32_t existing_dither = nv_encoder->dithering;
434 error = RRChangeOutputProperty(output->randr_output, dithering_atom,
435 XA_INTEGER, 32, PropModeReplace, 1,
436 &existing_dither, FALSE, TRUE);
439 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
440 "Failed to set dithering mode, %d\n", error);
443 RRPostPendingProperties(output->randr_output);
447 nv_output_set_property(xf86OutputPtr output, Atom property,
448 RRPropertyValuePtr value)
450 struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
452 if (property == scaling_mode_atom) {
456 if (value->type != XA_STRING || value->format != 8)
459 name = (char *) value->data;
461 /* Match a string to a scaling mode */
462 ret = nv_scaling_mode_lookup(name, value->size);
463 if (ret == SCALE_INVALID)
466 /* LVDS must always use gpu scaling. */
467 if (ret == SCALE_PANEL && nv_encoder->dcb->type == OUTPUT_LVDS)
470 nv_encoder->scaling_mode = ret;
471 } else if (property == dithering_atom) {
472 if (value->type != XA_INTEGER || value->format != 32)
475 int32_t val = *(int32_t *) value->data;
477 if (val < 0 || val > 1)
480 nv_encoder->dithering = val;
487 nv_output_mode_fixup(xf86OutputPtr output, DisplayModePtr mode,
488 DisplayModePtr adjusted_mode)
490 struct nouveau_connector *nv_connector = to_nouveau_connector(output);
492 if (nv_connector->nv_encoder != nv_connector->detected_encoder) {
493 nv_connector->nv_encoder = nv_connector->detected_encoder;
494 if (output->randr_output) {
495 RRDeleteOutputProperty(output->randr_output, dithering_atom);
496 RRDeleteOutputProperty(output->randr_output, scaling_mode_atom);
497 output->funcs->create_resources(output);
501 struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
503 /* For internal panels and gpu scaling on DVI we need the native mode */
504 if (nv_encoder->dcb->type == OUTPUT_LVDS ||
505 (nv_encoder->dcb->type == OUTPUT_TMDS && nv_encoder->scaling_mode != SCALE_PANEL)) {
506 adjusted_mode->HDisplay = nv_encoder->native_mode->HDisplay;
507 adjusted_mode->HSkew = nv_encoder->native_mode->HSkew;
508 adjusted_mode->HSyncStart = nv_encoder->native_mode->HSyncStart;
509 adjusted_mode->HSyncEnd = nv_encoder->native_mode->HSyncEnd;
510 adjusted_mode->HTotal = nv_encoder->native_mode->HTotal;
511 adjusted_mode->VDisplay = nv_encoder->native_mode->VDisplay;
512 adjusted_mode->VScan = nv_encoder->native_mode->VScan;
513 adjusted_mode->VSyncStart = nv_encoder->native_mode->VSyncStart;
514 adjusted_mode->VSyncEnd = nv_encoder->native_mode->VSyncEnd;
515 adjusted_mode->VTotal = nv_encoder->native_mode->VTotal;
516 adjusted_mode->Clock = nv_encoder->native_mode->Clock;
517 adjusted_mode->Flags = nv_encoder->native_mode->Flags;
519 xf86SetModeCrtc(adjusted_mode, INTERLACE_HALVE_V);
525 static void nv_digital_output_prepare_sel_clk(NVPtr pNv, struct nouveau_encoder *nv_encoder, int head)
527 NVRegPtr state = &pNv->ModeReg;
528 uint32_t bits1618 = nv_encoder->dcb->or & OUTPUT_A ? 0x10000 : 0x40000;
530 if (nv_encoder->dcb->location != LOC_ON_CHIP)
533 /* SEL_CLK is only used on the primary ramdac
534 * It toggles spread spectrum PLL output and sets the bindings of PLLs
535 * to heads on digital outputs
538 state->sel_clk |= bits1618;
540 state->sel_clk &= ~bits1618;
543 * bit 0 NVClk spread spectrum on/off
544 * bit 2 MemClk spread spectrum on/off
545 * bit 4 PixClk1 spread spectrum on/off toggle
546 * bit 6 PixClk2 spread spectrum on/off toggle
548 * nv40 (observations from bios behaviour and mmio traces):
549 * bits 4&6 as for nv30
550 * bits 5&7 head dependent as for bits 4&6, but do not appear with 4&6;
551 * maybe a different spread mode
552 * bits 8&10 seen on dual-link dvi outputs, purpose unknown (set by POST scripts)
553 * The logic behind turning spread spectrum on/off in the first place,
554 * and which bit-pair to use, is unclear on nv40 (for earlier cards, the fp table
555 * entry has the necessary info)
557 if (nv_encoder->dcb->type == OUTPUT_LVDS && pNv->SavedReg.sel_clk & 0xf0) {
558 int shift = (pNv->SavedReg.sel_clk & 0x50) ? 0 : 1;
560 state->sel_clk &= ~0xf0;
561 state->sel_clk |= (head ? 0x40 : 0x10) << shift;
566 nv_output_prepare(xf86OutputPtr output)
568 struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
569 NVPtr pNv = NVPTR(output->scrn);
570 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(output->crtc);
571 NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
573 output->funcs->dpms(output, DPMSModeOff);
575 /* calculate some output specific CRTC regs now, so that they can be written in nv_crtc_set_mode */
576 if (nv_encoder->dcb->type == OUTPUT_LVDS || nv_encoder->dcb->type == OUTPUT_TMDS)
577 nv_digital_output_prepare_sel_clk(pNv, nv_encoder, nv_crtc->head);
579 /* Some NV4x have unknown values (0x3f, 0x50, 0x54, 0x6b, 0x79, 0x7f etc.) which we don't alter */
580 if (!(regp->CRTC[NV_CIO_CRE_LCD__INDEX] & 0x44)) {
581 if (nv_encoder->dcb->type == OUTPUT_LVDS || nv_encoder->dcb->type == OUTPUT_TMDS) {
582 regp->CRTC[NV_CIO_CRE_LCD__INDEX] &= ~0x30;
583 regp->CRTC[NV_CIO_CRE_LCD__INDEX] |= 0x3;
584 if (nv_crtc->head == 0)
585 regp->CRTC[NV_CIO_CRE_LCD__INDEX] |= 0x8;
587 regp->CRTC[NV_CIO_CRE_LCD__INDEX] &= ~0x8;
588 if (nv_encoder->dcb->location != LOC_ON_CHIP)
589 regp->CRTC[NV_CIO_CRE_LCD__INDEX] |= (nv_encoder->dcb->or << 4) & 0x30;
591 regp->CRTC[NV_CIO_CRE_LCD__INDEX] = 0;
596 nv_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, DisplayModePtr adjusted_mode)
598 struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
599 ScrnInfoPtr pScrn = output->scrn;
600 NVPtr pNv = NVPTR(pScrn);
601 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(output->crtc);
603 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
604 "%s called for encoder %d\n", __func__, nv_encoder->dcb->index);
606 if (pNv->twoHeads && nv_encoder->dcb->type == OUTPUT_ANALOG) {
607 uint32_t dac_offset = nv_output_ramdac_offset(nv_encoder);
611 /* bit 16-19 are bits that are set on some G70 cards,
612 * but don't seem to have much effect */
613 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + dac_offset,
614 nv_crtc->head << 8 | NV_RAMDAC_OUTPUT_DAC_ENABLE);
615 /* force any other vga encoders to bind to the other crtc */
616 for (i = 0; i < pNv->dcb_table.entries; i++)
617 if (i != nv_encoder->dcb->index && pNv->encoders[i].dcb &&
618 pNv->encoders[i].dcb->type == OUTPUT_ANALOG) {
619 dac_offset = nv_output_ramdac_offset(&pNv->encoders[i]);
620 otherdac = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + dac_offset);
621 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + dac_offset,
622 (otherdac & ~0x100) | (nv_crtc->head ^ 1) << 8);
625 if (nv_encoder->dcb->type == OUTPUT_TMDS)
626 run_tmds_table(pScrn, nv_encoder->dcb, nv_crtc->head, adjusted_mode->Clock);
627 else if (nv_encoder->dcb->type == OUTPUT_LVDS)
628 call_lvds_script(pScrn, nv_encoder->dcb, nv_crtc->head, LVDS_RESET, adjusted_mode->Clock);
630 /* This could use refinement for flatpanels, but it should work this way */
631 if (pNv->NVArch < 0x44)
632 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + nv_output_ramdac_offset(nv_encoder), 0xf0000000);
634 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + nv_output_ramdac_offset(nv_encoder), 0x00100000);
638 nv_output_commit(xf86OutputPtr output)
640 struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
641 ScrnInfoPtr pScrn = output->scrn;
642 struct nouveau_crtc *nv_crtc = to_nouveau_crtc(output->crtc);
644 output->funcs->dpms(output, DPMSModeOn);
646 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Output %s is running on CRTC %d using output %c\n", output->name, nv_crtc->head, '@' + ffs(nv_encoder->dcb->or));
649 static void dpms_update_fp_control(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
651 NVPtr pNv = NVPTR(pScrn);
652 struct nouveau_crtc *nv_crtc;
654 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
657 if (mode == DPMSModeOn) {
658 nv_crtc = to_nouveau_crtc(crtc);
659 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
661 nv_crtc->fp_users |= 1 << nv_encoder->dcb->index;
662 NVWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL,
663 regp->fp_control & ~NV_PRAMDAC_FP_TG_CONTROL_OFF);
665 for (i = 0; i < xf86_config->num_crtc; i++) {
666 nv_crtc = to_nouveau_crtc(xf86_config->crtc[i]);
667 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
669 nv_crtc->fp_users &= ~(1 << nv_encoder->dcb->index);
670 if (!nv_crtc->fp_users) {
671 /* cut the FP output */
672 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_OFF;
673 NVWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control);
679 lvds_encoder_dpms(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
681 NVPtr pNv = NVPTR(pScrn);
683 if (nv_encoder->last_dpms == mode)
685 nv_encoder->last_dpms = mode;
687 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
688 "Setting dpms mode %d on lvds encoder (output %d)\n", mode, nv_encoder->dcb->index);
690 if (nv_encoder->dcb->lvdsconf.use_power_scripts) {
691 /* when removing an output, crtc may not be set, but PANEL_OFF must still be run */
692 int head = nv_get_digital_bound_head(pNv, nv_encoder->dcb->or);
693 int pclk = nv_encoder->native_mode->Clock;
696 head = to_nouveau_crtc(crtc)->head;
698 if (mode == DPMSModeOn)
699 call_lvds_script(pScrn, nv_encoder->dcb, head, LVDS_PANEL_ON, pclk);
701 call_lvds_script(pScrn, nv_encoder->dcb, head, LVDS_PANEL_OFF, pclk);
704 dpms_update_fp_control(pScrn, nv_encoder, crtc, mode);
706 if (mode == DPMSModeOn)
707 nv_digital_output_prepare_sel_clk(pNv, nv_encoder, to_nouveau_crtc(crtc)->head);
709 pNv->ModeReg.sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
710 pNv->ModeReg.sel_clk &= ~0xf0;
712 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, pNv->ModeReg.sel_clk);
716 vga_encoder_dpms(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
718 NVPtr pNv = NVPTR(pScrn);
720 if (nv_encoder->last_dpms == mode)
722 nv_encoder->last_dpms = mode;
724 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
725 "Setting dpms mode %d on vga encoder (output %d)\n", mode, nv_encoder->dcb->index);
728 uint32_t outputval = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder));
730 if (mode == DPMSModeOff)
731 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder),
732 outputval & ~NV_RAMDAC_OUTPUT_DAC_ENABLE);
733 else if (mode == DPMSModeOn)
734 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder),
735 outputval | NV_RAMDAC_OUTPUT_DAC_ENABLE);
740 tmds_encoder_dpms(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
742 NVPtr pNv = NVPTR(pScrn);
744 if (nv_encoder->last_dpms == mode)
746 nv_encoder->last_dpms = mode;
748 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
749 "Setting dpms mode %d on tmds encoder (output %d)\n", mode, nv_encoder->dcb->index);
751 dpms_update_fp_control(pScrn, nv_encoder, crtc, mode);
753 if (nv_encoder->dcb->location != LOC_ON_CHIP) {
754 struct nouveau_crtc *nv_crtc;
757 if (mode == DPMSModeOn) {
758 nv_crtc = to_nouveau_crtc(crtc);
759 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_LCD__INDEX,
760 pNv->ModeReg.crtc_reg[nv_crtc->head].CRTC[NV_CIO_CRE_LCD__INDEX]);
762 for (i = 0; i <= pNv->twoHeads; i++)
763 NVWriteVgaCrtc(pNv, i, NV_CIO_CRE_LCD__INDEX,
764 NVReadVgaCrtc(pNv, i, NV_CIO_CRE_LCD__INDEX) & ~((nv_encoder->dcb->or << 4) & 0x30));
768 static void nv_output_dpms(xf86OutputPtr output, int mode)
770 struct nouveau_connector *nv_connector = to_nouveau_connector(output);
771 struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
772 ScrnInfoPtr pScrn = output->scrn;
773 xf86CrtcPtr crtc = output->crtc;
774 NVPtr pNv = NVPTR(pScrn);
776 void (* const encoder_dpms[4])(ScrnInfoPtr, struct nouveau_encoder *, xf86CrtcPtr, int) =
777 /* index matches DCB type */
778 { vga_encoder_dpms, NULL, tmds_encoder_dpms, lvds_encoder_dpms };
780 struct nouveau_encoder *nv_encoder_i;
781 FOR_EACH_ENCODER_IN_CONNECTOR(i, nv_connector, nv_encoder_i)
782 if (nv_encoder_i != nv_encoder)
783 encoder_dpms[nv_encoder_i->dcb->type](pScrn, nv_encoder_i, crtc, DPMSModeOff);
785 if (nv_encoder) /* may be called before encoder is picked, but iteration above solves it */
786 encoder_dpms[nv_encoder->dcb->type](pScrn, nv_encoder, crtc, mode);
789 static uint32_t nv_get_clock_from_crtc(ScrnInfoPtr pScrn, RIVA_HW_STATE *state, uint8_t crtc)
791 NVPtr pNv = NVPTR(pScrn);
792 struct pll_lims pll_lim;
793 uint32_t vplla = state->crtc_reg[crtc].vpll_a;
794 uint32_t vpllb = state->crtc_reg[crtc].vpll_b;
795 bool nv40_single = pNv->Architecture == 0x40 &&
796 ((!crtc && state->reg580 & NV_RAMDAC_580_VPLL1_ACTIVE) ||
797 (crtc && state->reg580 & NV_RAMDAC_580_VPLL2_ACTIVE));
799 if (get_pll_limits(pScrn, crtc ? VPLL2 : VPLL1, &pll_lim))
802 return nv_decode_pll_highregs(pNv, vplla, vpllb, nv40_single, pll_lim.refclk);
805 void nv_encoder_save(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder)
807 NVPtr pNv = NVPTR(pScrn);
809 if (!nv_encoder->dcb) /* uninitialised encoder */
812 if (pNv->twoHeads && nv_encoder->dcb->type == OUTPUT_ANALOG)
813 nv_encoder->restore.output = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder));
814 if (nv_encoder->dcb->type == OUTPUT_TMDS || nv_encoder->dcb->type == OUTPUT_LVDS)
815 nv_encoder->restore.head = nv_get_digital_bound_head(pNv, nv_encoder->dcb->or);
818 void nv_encoder_restore(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder)
820 NVPtr pNv = NVPTR(pScrn);
821 int head = nv_encoder->restore.head;
823 if (!nv_encoder->dcb) /* uninitialised encoder */
826 if (pNv->twoHeads && nv_encoder->dcb->type == OUTPUT_ANALOG)
827 NVWriteRAMDAC(pNv, 0,
828 NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder),
829 nv_encoder->restore.output);
830 if (nv_encoder->dcb->type == OUTPUT_LVDS)
831 call_lvds_script(pScrn, nv_encoder->dcb, head, LVDS_PANEL_ON,
832 nv_encoder->native_mode->Clock);
833 if (nv_encoder->dcb->type == OUTPUT_TMDS) {
834 int clock = nv_get_clock_from_crtc(pScrn, &pNv->SavedReg, head);
836 run_tmds_table(pScrn, nv_encoder->dcb, head, clock);
839 nv_encoder->last_dpms = NV_DPMS_CLEARED;
842 static const xf86OutputFuncsRec nv_output_funcs = {
843 .dpms = nv_output_dpms,
844 .mode_valid = nv_output_mode_valid,
845 .mode_fixup = nv_output_mode_fixup,
846 .mode_set = nv_output_mode_set,
847 .detect = nv_output_detect,
848 .get_modes = nv_output_get_edid_modes,
849 .destroy = nv_output_destroy,
850 .prepare = nv_output_prepare,
851 .commit = nv_output_commit,
852 .create_resources = nv_output_create_resources,
853 .set_property = nv_output_set_property,
856 static const xf86OutputFuncsRec nv_lvds_output_funcs = {
857 .dpms = nv_output_dpms,
858 .mode_valid = nv_output_mode_valid,
859 .mode_fixup = nv_output_mode_fixup,
860 .mode_set = nv_output_mode_set,
861 .detect = nv_output_detect,
862 .get_modes = nv_lvds_output_get_modes,
863 .destroy = nv_output_destroy,
864 .prepare = nv_output_prepare,
865 .commit = nv_output_commit,
866 .create_resources = nv_output_create_resources,
867 .set_property = nv_output_set_property,
871 nv_add_encoder(ScrnInfoPtr pScrn, struct dcb_entry *dcbent)
873 NVPtr pNv = NVPTR(pScrn);
874 struct nouveau_encoder *nv_encoder = &pNv->encoders[dcbent->index];
876 nv_encoder->dcb = dcbent;
877 nv_encoder->last_dpms = NV_DPMS_CLEARED;
878 nv_encoder->dithering = (pNv->FPDither || (nv_encoder->dcb->type == OUTPUT_LVDS && !pNv->VBIOS.fp.if_is_24bit));
879 if (pNv->fpScaler) /* GPU Scaling */
880 nv_encoder->scaling_mode = SCALE_ASPECT;
881 else if (nv_encoder->dcb->type == OUTPUT_LVDS)
882 nv_encoder->scaling_mode = SCALE_NOSCALE;
884 nv_encoder->scaling_mode = SCALE_PANEL;
885 if (xf86GetOptValString(pNv->Options, OPTION_SCALING_MODE)) {
886 nv_encoder->scaling_mode = nv_scaling_mode_lookup(xf86GetOptValString(pNv->Options, OPTION_SCALING_MODE), -1);
887 if (nv_encoder->scaling_mode == SCALE_INVALID)
888 nv_encoder->scaling_mode = SCALE_ASPECT; /* default */
893 nv_add_connector(ScrnInfoPtr pScrn, int i2c_index, int encoders, const xf86OutputFuncsRec *output_funcs, char *outputname)
895 NVPtr pNv = NVPTR(pScrn);
896 xf86OutputPtr output;
897 struct nouveau_connector *nv_connector;
899 if (!(output = xf86OutputCreate(pScrn, output_funcs, outputname)))
901 if (!(nv_connector = xcalloc(1, sizeof (struct nouveau_connector)))) {
902 xf86OutputDestroy(output);
906 output->driver_private = nv_connector;
909 NV_I2CInit(pScrn, &nv_connector->pDDCBus, pNv->dcb_table.i2c_read[i2c_index], xstrdup(outputname));
910 nv_connector->possible_encoders = encoders;
913 void NvSetupOutputs(ScrnInfoPtr pScrn)
915 NVPtr pNv = NVPTR(pScrn);
916 uint16_t connectors[0x10] = { 0 };
917 struct dcb_entry *dcbent;
918 int i, vga_count = 0, dvid_count = 0, dvii_count = 0, lvds_count = 0;
920 if (!(pNv->encoders = xcalloc(pNv->dcb_table.entries, sizeof (struct nouveau_encoder))))
923 for (i = 0; i < pNv->dcb_table.entries; i++) {
924 dcbent = &pNv->dcb_table.entry[i];
926 if (dcbent->type == OUTPUT_TV)
928 if (dcbent->type > 3) {
929 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DCB type %d not known\n", dcbent->type);
933 connectors[dcbent->i2c_index] |= 1 << i;
935 nv_add_encoder(pScrn, dcbent);
938 for (i = 0; i < pNv->dcb_table.entries; i++) {
939 int i2c_index = pNv->dcb_table.entry[i].i2c_index;
940 uint16_t encoders = connectors[i2c_index];
942 xf86OutputFuncsRec const *funcs = &nv_output_funcs;
947 switch (pNv->dcb_table.entry[i].type) {
949 if (!MULTIPLE_ENCODERS(encoders))
950 sprintf(outputname, "VGA-%d", vga_count++);
952 sprintf(outputname, "DVI-I-%d", dvii_count++);
955 if (!MULTIPLE_ENCODERS(encoders))
956 sprintf(outputname, "DVI-D-%d", dvid_count++);
958 sprintf(outputname, "DVI-I-%d", dvii_count++);
961 sprintf(outputname, "LVDS-%d", lvds_count++);
962 funcs = &nv_lvds_output_funcs;
968 nv_add_connector(pScrn, i2c_index, encoders, funcs, outputname);
969 connectors[i2c_index] = 0; /* avoid connectors being added multiply */