2 * Copyright 2007 Maarten Maathuis
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27 /* These are probably redrirected from 0x4000 range (very similar regs to nv40, maybe different order) */
28 #define NV50_CRTC_VPLL1_A 0x00614104
29 #define NV50_CRTC_VPLL1_B 0x00614108
30 #define NV50_CRTC_VPLL2_A 0x00614904
31 #define NV50_CRTC_VPLL2_B 0x00614908
33 /* Clamped to 256 MiB */
34 #define NV50_CRTC0_RAM_AMOUNT 0x00610384
35 #define NV50_CRTC1_RAM_AMOUNT 0x00610784
37 /* These things below are so called "commands" */
38 #define NV50_UPDATE_DISPLAY 0x80
40 #define NV50_CRTC0_CLOCK 0x804
41 #define NV50_CRTC0_INTERLACE 0x808
43 /* Anyone know what part of the chip is triggered here precisely? */
44 #define NV84_CRTC0_BLANK_UNK1 0x85C
45 #define NV84_CRTC0_BLANK_UNK1_BLANK 0x0
46 #define NV84_CRTC0_BLANK_UNK1_UNBLANK 0x1
48 #define NV50_CRTC0_FB_SIZE 0x868
49 #define NV50_CRTC0_PITCH 0x86C
51 /* I'm openminded to better interpretations. */
52 /* This is an educated guess. */
53 /* NV50 has RAMDAC and TMDS offchip, so it's unlikely to be that. */
54 #define NV50_CRTC0_BLANK_CTRL 0x874
55 #define NV50_CRTC0_BLANK_CTRL_BLANK 0x0
56 #define NV50_CRTC0_BLANK_CTRL_UNBLANK 0x1
58 /* Anyone know what part of the chip is triggered here precisely? */
59 #define NV84_CRTC0_BLANK_UNK2 0x89C
60 #define NV84_CRTC0_BLANK_UNK2_BLANK 0x0
61 #define NV84_CRTC0_BLANK_UNK2_UNBLANK 0x1
63 #define NV50_CRTC0_FB_POS 0x8C0
64 #define NV50_CRTC0_SCRN_SIZE 0x8C8
66 #define NV50_CRTC0_HBLANK_START 0x814
67 #define NV50_CRTC0_HSYNC_END 0x818
68 #define NV50_CRTC0_HBLANK_END 0x81C
69 #define NV50_CRTC0_HTOTAL 0x820
71 #define NV50_CRTC1_CLOCK 0xC04
72 #define NV50_CRTC1_INTERLACE 0xC08
74 /* Anyone know what part of the chip is triggered here precisely? */
75 #define NV84_CRTC1_BLANK_UNK1 0xC5C
76 #define NV84_CRTC1_BLANK_UNK1_BLANK 0x0
77 #define NV84_CRTC1_BLANK_UNK1_UNBLANK 0x1
79 /* I'm openminded to better interpretations. */
80 #define NV50_CRTC1_BLANK_CTRL 0xC74
81 #define NV50_CRTC1_BLANK_CTRL_BLANK 0x0
82 #define NV50_CRTC1_BLANK_CTRL_UNBLANK 0x1
84 /* Anyone know what part of the chip is triggered here precisely? */
85 #define NV84_CRTC1_BLANK_UNK2 0xC9C
86 #define NV84_CRTC1_BLANK_UNK2_BLANK 0x0
87 #define NV84_CRTC1_BLANK_UNK2_UNBLANK 0x1
89 #define NV50_CRTC1_HBLANK_START 0xC14
90 #define NV50_CRTC1_HSYNC_END 0xC18
91 #define NV50_CRTC1_HBLANK_END 0xC1C
92 #define NV50_CRTC1_HTOTAL 0xC20
94 #define NV50_CRTC1_FB_SIZE 0xC68
95 #define NV50_CRTC1_PITCH 0xC6C
97 #define NV50_CRTC1_FB_POS 0xCC0
98 #define NV50_CRTC1_SCRN_SIZE 0xCC8
100 #define NV50_CRTC0_DEPTH 0x870
101 #define NV50_CRTC0_DEPTH_8BPP 0x1E00
102 #define NV50_CRTC0_DEPTH_15BPP 0xE900
103 #define NV50_CRTC0_DEPTH_16BPP 0xE800
104 #define NV50_CRTC0_DEPTH_24BPP 0xCF00
106 #define NV50_CRTC1_DEPTH 0xC70
107 #define NV50_CRTC1_DEPTH_8BPP 0x1E00
108 #define NV50_CRTC1_DEPTH_15BPP 0xE900
109 #define NV50_CRTC1_DEPTH_16BPP 0xE800
110 #define NV50_CRTC1_DEPTH_24BPP 0xCF00
112 #define NV50_CRTC0_FB_OFFSET 0x860
113 #define NV50_CRTC1_FB_OFFSET 0xC60
115 #define NV50_CRTC0_CURSOR_OFFSET 0x884
116 #define NV50_CRTC1_CURSOR_OFFSET 0xC84
118 /* You can't have a palette in 8 bit mode (=OFF) */
119 #define NV50_CRTC0_CLUT_MODE 0x840
120 #define NV50_CRTC0_CLUT_MODE_BLANK 0x00000000
121 #define NV50_CRTC0_CLUT_MODE_OFF 0x80000000
122 #define NV50_CRTC0_CLUT_MODE_ON 0xC0000000
123 #define NV50_CRTC0_CLUT_OFFSET 0x844
125 #define NV50_CRTC1_CLUT_MODE 0xC40
126 #define NV50_CRTC1_CLUT_MODE_BLANK 0x00000000
127 #define NV50_CRTC1_CLUT_MODE_OFF 0x80000000
128 #define NV50_CRTC1_CLUT_MODE_ON 0xC0000000
129 #define NV50_CRTC1_CLUT_OFFSET 0xC44
131 #define NV50_CRTC0_CURSOR0 0x880
132 #define NV50_CRTC0_CURSOR0_SHOW 0x85000000
133 #define NV50_CRTC0_CURSOR0_HIDE 0x05000000
135 #define NV50_CRTC1_CURSOR0 0xC80
136 #define NV50_CRTC1_CURSOR0_SHOW 0x85000000
137 #define NV50_CRTC1_CURSOR0_HIDE 0x05000000
139 #endif /* __NV50REG_H_ */