git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 2006 Dave Airlie
   3  * Copyright 2007 Maarten Maathuis
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
  26  * decleration is at the bottom of this file as it is rather ugly
  27  */
  28
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include <assert.h>
  34 #include "xf86.h"
  35 #include "os.h"
  36 #include "mibank.h"
  37 #include "globals.h"
  38 #include "xf86.h"
  39 #include "xf86Priv.h"
  40 #include "xf86DDC.h"
  41 #include "mipointer.h"
  42 #include "windowstr.h"
  43 #include <randrstr.h>
  44 #include <X11/extensions/render.h>
  45
  46 #include "xf86Crtc.h"
  47 #include "nv_include.h"
  48
  49 #include "vgaHW.h"
  50
  51 #define CRTC_INDEX 0x3d4
  52 #define CRTC_DATA 0x3d5
  53 #define CRTC_IN_STAT_1 0x3da
  54
  55 #define WHITE_VALUE 0x3F
  56 #define BLACK_VALUE 0x00
  57 #define OVERSCAN_VALUE 0x01
  58
  59 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  60 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override);
  61 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  62 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  63 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  64 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  65
  66 static CARD8 NVReadPVIO(xf86CrtcPtr crtc, CARD32 address)
  67 {
  68         ScrnInfoPtr pScrn = crtc->scrn;
  69         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  70         NVPtr pNv = NVPTR(pScrn);
  71
  72         /* Only NV4x have two pvio ranges */
  73         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  74                 return NV_RD08(pNv->PVIO1, address);
  75         } else {
  76                 return NV_RD08(pNv->PVIO0, address);
  77         }
  78 }
  79
  80 static void NVWritePVIO(xf86CrtcPtr crtc, CARD32 address, CARD8 value)
  81 {
  82         ScrnInfoPtr pScrn = crtc->scrn;
  83         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  84         NVPtr pNv = NVPTR(pScrn);
  85
  86         /* Only NV4x have two pvio ranges */
  87         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  88                 NV_WR08(pNv->PVIO1, address, value);
  89         } else {
  90                 NV_WR08(pNv->PVIO0, address, value);
  91         }
  92 }
  93
  94 static void NVWriteMiscOut(xf86CrtcPtr crtc, CARD8 value)
  95 {
  96         NVWritePVIO(crtc, VGA_MISC_OUT_W, value);
  97 }
  98
  99 static CARD8 NVReadMiscOut(xf86CrtcPtr crtc)
 100 {
 101         return NVReadPVIO(crtc, VGA_MISC_OUT_R);
 102 }
 103
 104 void NVWriteVGA(NVPtr pNv, int head, CARD8 index, CARD8 value)
 105 {
 106         volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 107
 108         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 109         NV_WR08(pCRTCReg, CRTC_DATA, value);
 110 }
 111
 112 CARD8 NVReadVGA(NVPtr pNv, int head, CARD8 index)
 113 {
 114         volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 115
 116         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 117         return NV_RD08(pCRTCReg, CRTC_DATA);
 118 }
 119
 120 /* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
 121  * I suspect they in fact do nothing, but are merely a way to carry useful
 122  * per-head variables around
 123  *
 124  * Known uses:
 125  * CR57         CR58
 126  * 0x00         index to the appropriate dcb entry (or 7f for inactive)
 127  * 0x02         dcb entry's "or" value (or 00 for inactive)
 128  * 0x03         bit0 set for dual link (LVDS, possibly elsewhere too)
 129  * 0x0f         laptop panel info -     high nibble for PEXTDEV_BOOT strap
 130  *                                      low nibble for xlat strap value
 131  */
 132
 133 void NVWriteVGACR5758(NVPtr pNv, int head, uint8_t index, uint8_t value)
 134 {
 135         NVWriteVGA(pNv, head, 0x57, index);
 136         NVWriteVGA(pNv, head, 0x58, value);
 137 }
 138
 139 uint8_t NVReadVGACR5758(NVPtr pNv, int head, uint8_t index)
 140 {
 141         NVWriteVGA(pNv, head, 0x57, index);
 142         return NVReadVGA(pNv, head, 0x58);
 143 }
 144
 145 void NVWriteVgaCrtc(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 146 {
 147         ScrnInfoPtr pScrn = crtc->scrn;
 148         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 149         NVPtr pNv = NVPTR(pScrn);
 150
 151         NVWriteVGA(pNv, nv_crtc->head, index, value);
 152 }
 153
 154 CARD8 NVReadVgaCrtc(xf86CrtcPtr crtc, CARD8 index)
 155 {
 156         ScrnInfoPtr pScrn = crtc->scrn;
 157         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 158         NVPtr pNv = NVPTR(pScrn);
 159
 160         return NVReadVGA(pNv, nv_crtc->head, index);
 161 }
 162
 163 static void NVWriteVgaSeq(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 164 {
 165         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 166         NVWritePVIO(crtc, VGA_SEQ_DATA, value);
 167 }
 168
 169 static CARD8 NVReadVgaSeq(xf86CrtcPtr crtc, CARD8 index)
 170 {
 171         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 172         return NVReadPVIO(crtc, VGA_SEQ_DATA);
 173 }
 174
 175 static void NVWriteVgaGr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 176 {
 177         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 178         NVWritePVIO(crtc, VGA_GRAPH_DATA, value);
 179 }
 180
 181 static CARD8 NVReadVgaGr(xf86CrtcPtr crtc, CARD8 index)
 182 {
 183         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 184         return NVReadPVIO(crtc, VGA_GRAPH_DATA);
 185 }
 186
 187
 188 static void NVWriteVgaAttr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 189 {
 190   ScrnInfoPtr pScrn = crtc->scrn;
 191   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 192   NVPtr pNv = NVPTR(pScrn);
 193   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 194
 195   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 196   if (nv_crtc->paletteEnabled)
 197     index &= ~0x20;
 198   else
 199     index |= 0x20;
 200   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 201   NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
 202 }
 203
 204 static CARD8 NVReadVgaAttr(xf86CrtcPtr crtc, CARD8 index)
 205 {
 206   ScrnInfoPtr pScrn = crtc->scrn;
 207   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 208   NVPtr pNv = NVPTR(pScrn);
 209   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 210
 211   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 212   if (nv_crtc->paletteEnabled)
 213     index &= ~0x20;
 214   else
 215     index |= 0x20;
 216   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 217   return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
 218 }
 219
 220 void NVCrtcSetOwner(xf86CrtcPtr crtc)
 221 {
 222         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 223         ScrnInfoPtr pScrn = crtc->scrn;
 224         NVPtr pNv = NVPTR(pScrn);
 225         /* Non standard beheaviour required by NV11 */
 226         if (pNv) {
 227                 uint8_t owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 228                 ErrorF("pre-Owner: 0x%X\n", owner);
 229                 if (owner == 0x04) {
 230                         uint32_t pbus84 = nvReadMC(pNv, 0x1084);
 231                         ErrorF("pbus84: 0x%X\n", pbus84);
 232                         pbus84 &= ~(1<<28);
 233                         ErrorF("pbus84: 0x%X\n", pbus84);
 234                         nvWriteMC(pNv, 0x1084, pbus84);
 235                 }
 236                 /* The blob never writes owner to pcio1, so should we */
 237                 if (pNv->NVArch == 0x11) {
 238                         NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, 0xff);
 239                 }
 240                 NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, nv_crtc->crtc * 0x3);
 241                 owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 242                 ErrorF("post-Owner: 0x%X\n", owner);
 243         } else {
 244                 ErrorF("pNv pointer is NULL\n");
 245         }
 246 }
 247
 248 static void
 249 NVEnablePalette(xf86CrtcPtr crtc)
 250 {
 251   ScrnInfoPtr pScrn = crtc->scrn;
 252   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 253   NVPtr pNv = NVPTR(pScrn);
 254   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 255
 256   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 257   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
 258   nv_crtc->paletteEnabled = TRUE;
 259 }
 260
 261 static void
 262 NVDisablePalette(xf86CrtcPtr crtc)
 263 {
 264   ScrnInfoPtr pScrn = crtc->scrn;
 265   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 266   NVPtr pNv = NVPTR(pScrn);
 267   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 268
 269   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 270   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
 271   nv_crtc->paletteEnabled = FALSE;
 272 }
 273
 274 static void NVWriteVgaReg(xf86CrtcPtr crtc, CARD32 reg, CARD8 value)
 275 {
 276  ScrnInfoPtr pScrn = crtc->scrn;
 277   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 278   NVPtr pNv = NVPTR(pScrn);
 279   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 280
 281   NV_WR08(pCRTCReg, reg, value);
 282 }
 283
 284 /* perform a sequencer reset */
 285 static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
 286 {
 287   if (start)
 288     NVWriteVgaSeq(crtc, 0x00, 0x1);
 289   else
 290     NVWriteVgaSeq(crtc, 0x00, 0x3);
 291
 292 }
 293 static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
 294 {
 295         CARD8 tmp;
 296
 297         if (on) {
 298                 tmp = NVReadVgaSeq(crtc, 0x1);
 299                 NVVgaSeqReset(crtc, TRUE);
 300                 NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
 301
 302                 NVEnablePalette(crtc);
 303         } else {
 304                 /*
 305                  * Reenable sequencer, then turn on screen.
 306                  */
 307                 tmp = NVReadVgaSeq(crtc, 0x1);
 308                 NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20); /* reenable display */
 309                 NVVgaSeqReset(crtc, FALSE);
 310
 311                 NVDisablePalette(crtc);
 312         }
 313 }
 314
 315 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool Lock)
 316 {
 317         CARD8 cr11;
 318
 319         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57);
 320         cr11 = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE);
 321         if (Lock) cr11 |= 0x80;
 322         else cr11 &= ~0x80;
 323         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE, cr11);
 324 }
 325
 326 xf86OutputPtr
 327 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
 328 {
 329         ScrnInfoPtr pScrn = crtc->scrn;
 330         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 331         int i;
 332         for (i = 0; i < xf86_config->num_output; i++) {
 333                 xf86OutputPtr output = xf86_config->output[i];
 334
 335                 if (output->crtc == crtc) {
 336                         return output;
 337                 }
 338         }
 339
 340         return NULL;
 341 }
 342
 343 xf86CrtcPtr
 344 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
 345 {
 346         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 347         int i;
 348
 349         for (i = 0; i < xf86_config->num_crtc; i++) {
 350                 xf86CrtcPtr crtc = xf86_config->crtc[i];
 351                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 352                 if (nv_crtc->crtc == index)
 353                         return crtc;
 354         }
 355
 356         return NULL;
 357 }
 358
 359 /*
 360  * Calculate the Video Clock parameters for the PLL.
 361  */
 362 static void CalcVClock (
 363         uint32_t                clockIn,
 364         uint32_t                *clockOut,
 365         CARD32          *pllOut,
 366         NVPtr           pNv
 367 )
 368 {
 369         unsigned lowM, highM, highP;
 370         unsigned DeltaNew, DeltaOld;
 371         unsigned VClk, Freq;
 372         unsigned M, N, P;
 373
 374         /* M: PLL reference frequency postscaler divider */
 375         /* P: PLL VCO output postscaler divider */
 376         /* N: PLL VCO postscaler setting */
 377
 378         DeltaOld = 0xFFFFFFFF;
 379
 380         VClk = (unsigned)clockIn;
 381
 382         /* Taken from Haiku, after someone with an NV28 had an issue */
 383         switch(pNv->NVArch) {
 384                 case 0x28:
 385                         lowM = 1;
 386                         highP = 32;
 387                         if (VClk > 340000) {
 388                                 highM = 2;
 389                         } else if (VClk > 200000) {
 390                                 highM = 4;
 391                         } else if (VClk > 150000) {
 392                                 highM = 6;
 393                         } else {
 394                                 highM = 14;
 395                         }
 396                         break;
 397                 default:
 398                         lowM = 1;
 399                         highP = 16;
 400                         if (VClk > 340000) {
 401                                 highM = 2;
 402                         } else if (VClk > 250000) {
 403                                 highM = 6;
 404                         } else {
 405                                 highM = 14;
 406                         }
 407                         break;
 408         }
 409
 410         for (P = 1; P <= highP; P++) {
 411                 Freq = VClk << P;
 412                 if ((Freq >= 128000) && (Freq <= 350000)) {
 413                         for (M = lowM; M <= highM; M++) {
 414                                 N = ((VClk << P) * M) / pNv->CrystalFreqKHz;
 415                                 if (N <= 255) {
 416                                         Freq = ((pNv->CrystalFreqKHz * N) / M) >> P;
 417                                         if (Freq > VClk) {
 418                                                 DeltaNew = Freq - VClk;
 419                                         } else {
 420                                                 DeltaNew = VClk - Freq;
 421                                         }
 422                                         if (DeltaNew < DeltaOld) {
 423                                                 *pllOut   = (P << 16) | (N << 8) | M;
 424                                                 *clockOut = Freq;
 425                                                 DeltaOld  = DeltaNew;
 426                                         }
 427                                 }
 428                         }
 429                 }
 430         }
 431 }
 432
 433 static void CalcVClock2Stage (
 434         uint32_t                clockIn,
 435         uint32_t                *clockOut,
 436         CARD32          *pllOut,
 437         CARD32          *pllBOut,
 438         NVPtr           pNv
 439 )
 440 {
 441         unsigned DeltaNew, DeltaOld;
 442         unsigned VClk, Freq;
 443         unsigned M, N, P;
 444         unsigned lowM, highM, highP;
 445
 446         DeltaOld = 0xFFFFFFFF;
 447
 448         *pllBOut = 0x80000401;  /* fixed at x4 for now */
 449
 450         VClk = (unsigned)clockIn;
 451
 452         /* Taken from Haiku, after someone with an NV28 had an issue */
 453         switch(pNv->NVArch) {
 454                 case 0x28:
 455                         lowM = 1;
 456                         highP = 32;
 457                         if (VClk > 340000) {
 458                                 highM = 2;
 459                         } else if (VClk > 200000) {
 460                                 highM = 4;
 461                         } else if (VClk > 150000) {
 462                                 highM = 6;
 463                         } else {
 464                                 highM = 14;
 465                         }
 466                         break;
 467                 default:
 468                         lowM = 1;
 469                         highP = 15;
 470                         if (VClk > 340000) {
 471                                 highM = 2;
 472                         } else if (VClk > 250000) {
 473                                 highM = 6;
 474                         } else {
 475                                 highM = 14;
 476                         }
 477                         break;
 478         }
 479
 480         for (P = 0; P <= highP; P++) {
 481                 Freq = VClk << P;
 482                 if ((Freq >= 400000) && (Freq <= 1000000)) {
 483                         for (M = lowM; M <= highM; M++) {
 484                                 N = ((VClk << P) * M) / (pNv->CrystalFreqKHz << 2);
 485                                 if ((N >= 5) && (N <= 255)) {
 486                                         Freq = (((pNv->CrystalFreqKHz << 2) * N) / M) >> P;
 487                                         if (Freq > VClk) {
 488                                                 DeltaNew = Freq - VClk;
 489                                         } else {
 490                                                 DeltaNew = VClk - Freq;
 491                                         }
 492                                         if (DeltaNew < DeltaOld) {
 493                                                 *pllOut   = (P << 16) | (N << 8) | M;
 494                                                 *clockOut = Freq;
 495                                                 DeltaOld  = DeltaNew;
 496                                         }
 497                                 }
 498                         }
 499                 }
 500         }
 501 }
 502
 503 /* BIG NOTE: modifying vpll1 and vpll2vpll2 does not work, what bit is the switch to allow it? */
 504
 505 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
 506 /* They are only valid for NV4x, appearantly reordered for NV5x */
 507 /* gpu pll: 0x4000 + 0x4004
 508  * unknown pll: 0x4008 + 0x400c
 509  * vpll1: 0x4010 + 0x4014
 510  * vpll2: 0x4018 + 0x401c
 511  * unknown pll: 0x4020 + 0x4024
 512  * unknown pll: 0x4038 + 0x403c
 513  * Some of the unknown's are probably memory pll's.
 514  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
 515  * 1 and 2 refer to the registers of each pair. There is only one post divider.
 516  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
 517  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
 518  *     bit8: A switch that turns of the second divider and multiplier off.
 519  *     bit12: Also a switch, i haven't seen it yet.
 520  *     bit16-19: p-divider
 521  *     but 28-31: Something related to the mode that is used (see bit8).
 522  * 2) bit0-7: m-divider (a)
 523  *     bit8-15: n-multiplier (a)
 524  *     bit16-23: m-divider (b)
 525  *     bit24-31: n-multiplier (b)
 526  */
 527
 528 /* Modifying the gpu pll for example requires:
 529  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 530  * This is not needed for the vpll's which have their own bits.
 531  */
 532
 533 static void
 534 CalculateVClkNV4x(
 535         NVPtr pNv,
 536         uint32_t requested_clock,
 537         uint32_t *given_clock,
 538         uint32_t *pll_a,
 539         uint32_t *pll_b,
 540         uint32_t *reg580,
 541         Bool    *db1_ratio,
 542         Bool primary,
 543         uint8_t special_bits
 544 )
 545 {
 546         uint32_t DeltaOld, DeltaNew;
 547         uint32_t freq, temp;
 548         /* We have 2 mulitpliers, 2 dividers and one post divider */
 549         /* Note that p is only 4 bits */
 550         uint32_t m1, m2, n1, n2, p;
 551         uint32_t m1_best = 0, m2_best = 0, n1_best = 0, n2_best = 0, p_best = 0;
 552
 553         DeltaOld = 0xFFFFFFFF;
 554
 555         /* This is no solid limit, but a reasonable boundary */
 556         if (requested_clock < 120000) {
 557                 *db1_ratio = TRUE;
 558                 /* Turn the second set of divider and multiplier off */
 559                 /* Neutral settings */
 560                 n2 = 1;
 561                 m2 = 1;
 562         } else {
 563                 *db1_ratio = FALSE;
 564                 /* Fixed at x4 for the moment */
 565                 n2 = 4;
 566                 m2 = 1;
 567         }
 568
 569         n2_best = n2;
 570         m2_best = m2;
 571
 572         /* Single pll */
 573         if (*db1_ratio) {
 574                 temp = 0.4975 * 250000;
 575                 p = 0;
 576
 577                 while (requested_clock <= temp) {
 578                         temp /= 2;
 579                         p++;
 580                 }
 581
 582                 /* The minimum clock after m1 is 3 Mhz, and the clock is 27 Mhz, so m_max = 9 */
 583                 /* The maximum clock is 25 Mhz */
 584                 for (m1 = 2; m1 <= 9; m1++) {
 585                         n1 = ((requested_clock << p) * m1)/(pNv->CrystalFreqKHz);
 586                         if (n1 > 0 && n1 <= 255) {
 587                                 freq = ((pNv->CrystalFreqKHz * n1)/m1) >> p;
 588                                 if (freq > requested_clock) {
 589                                         DeltaNew = freq - requested_clock;
 590                                 } else {
 591                                         DeltaNew = requested_clock - freq;
 592                                 }
 593                                 if (DeltaNew < DeltaOld) {
 594                                         m1_best = m1;
 595                                         n1_best = n1;
 596                                         p_best = p;
 597                                         DeltaOld = DeltaNew;
 598                                 }
 599                         }
 600                 }
 601         /* Dual pll */
 602         } else {
 603                 for (p = 0; p <= 6; p++) {
 604                         /* Assuming a fixed 2nd stage */
 605                         freq = requested_clock << p;
 606                         /* The maximum output frequency of stage 2 is allowed to be between 400 Mhz and 1 GHz */
 607                         if (freq > 400000 && freq < 1000000) {
 608                                 /* The minimum clock after m1 is 3 Mhz, and the clock is 27 Mhz, so m_max = 9 */
 609                                 /* The maximum clock is 25 Mhz */
 610                                 for (m1 = 2; m1 <= 9; m1++) {
 611                                         n1 = ((requested_clock << p) * m1 * m2)/(pNv->CrystalFreqKHz * n2);
 612                                         if (n1 >= 5 && n1 <= 255) {
 613                                                 freq = ((pNv->CrystalFreqKHz * n1 * n2)/(m1 * m2)) >> p;
 614                                                 if (freq > requested_clock) {
 615                                                         DeltaNew = freq - requested_clock;
 616                                                 } else {
 617                                                         DeltaNew = requested_clock - freq;
 618                                                 }
 619                                                 if (DeltaNew < DeltaOld) {
 620                                                         m1_best = m1;
 621                                                         n1_best = n1;
 622                                                         p_best = p;
 623                                                         DeltaOld = DeltaNew;
 624                                                 }
 625                                         }
 626                                 }
 627                         }
 628                 }
 629         }
 630
 631         if (*db1_ratio) {
 632                 /* Bogus data, the same nvidia uses */
 633                 n2_best = 1;
 634                 m2_best = 31;
 635         }
 636
 637         /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
 638         /* Let's keep the special bits, if the bios already set them */
 639         *pll_a = (special_bits << 30) | (p_best << 16) | (n1_best << 8) | (m1_best << 0);
 640         *pll_b = (1 << 31) | (n2_best << 8) | (m2_best << 0);
 641
 642         if (*db1_ratio) {
 643                 if (primary) {
 644                         *reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 645                 } else {
 646                         *reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 647                 }
 648         } else {
 649                 if (primary) {
 650                         *reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
 651                 } else {
 652                         *reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
 653                 }
 654         }
 655
 656         if (*db1_ratio) {
 657                 ErrorF("vpll: n1 %d m1 %d p %d db1_ratio %d\n", n1_best, m1_best, p_best, *db1_ratio);
 658         } else {
 659                 ErrorF("vpll: n1 %d n2 %d m1 %d m2 %d p %d db1_ratio %d\n", n1_best, n2_best, m1_best, m2_best, p_best, *db1_ratio);
 660         }
 661 }
 662
 663 static void nv40_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 664 {
 665         state->vpll1_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 666         state->vpll1_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 667         state->vpll2_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 668         state->vpll2_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 669         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 670         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 671         state->reg580 = nvReadRAMDAC0(pNv, NV_RAMDAC_580);
 672         state->reg594 = nvReadRAMDAC0(pNv, NV_RAMDAC_594);
 673 }
 674
 675 static void nv40_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 676 {
 677         CARD32 fp_debug_0[2];
 678         uint32_t index[2];
 679         fp_debug_0[0] = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
 680         fp_debug_0[1] = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
 681
 682         /* The TMDS_PLL switch is on the actual ramdac */
 683         if (state->crosswired) {
 684                 index[0] = 1;
 685                 index[1] = 0;
 686                 ErrorF("Crosswired pll state load\n");
 687         } else {
 688                 index[0] = 0;
 689                 index[1] = 1;
 690         }
 691
 692         if (state->vpll2_b) {
 693                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0,
 694                         fp_debug_0[index[1]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 695
 696                 /* Wait for the situation to stabilise */
 697                 usleep(5000);
 698
 699                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 700                 /* for vpll2 change bits 18 and 19 are disabled */
 701                 reg_c040 &= ~(0x3 << 18);
 702                 nvWriteMC(pNv, 0xc040, reg_c040);
 703
 704                 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 705                 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 706
 707                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2_a);
 708                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 709
 710                 ErrorF("writing pllsel %08X\n", state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 711                 /* Let's keep the primary vpll off */
 712                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 713
 714                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 715                 ErrorF("writing reg580 %08X\n", state->reg580);
 716
 717                 /* We need to wait a while */
 718                 usleep(5000);
 719                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 720
 721                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[1]]);
 722
 723                 /* Wait for the situation to stabilise */
 724                 usleep(5000);
 725         }
 726
 727         if (state->vpll1_b) {
 728                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0,
 729                         fp_debug_0[index[0]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 730
 731                 /* Wait for the situation to stabilise */
 732                 usleep(5000);
 733
 734                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 735                 /* for vpll2 change bits 16 and 17 are disabled */
 736                 reg_c040 &= ~(0x3 << 16);
 737                 nvWriteMC(pNv, 0xc040, reg_c040);
 738
 739                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 740                 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 741
 742                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll1_a);
 743                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpll1_b);
 744
 745                 ErrorF("writing pllsel %08X\n", state->pllsel);
 746                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 747
 748                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 749                 ErrorF("writing reg580 %08X\n", state->reg580);
 750
 751                 /* We need to wait a while */
 752                 usleep(5000);
 753                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 754
 755                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[0]]);
 756
 757                 /* Wait for the situation to stabilise */
 758                 usleep(5000);
 759         }
 760
 761         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 762         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 763
 764         ErrorF("writing reg594 %08X\n", state->reg594);
 765         nvWriteRAMDAC0(pNv, NV_RAMDAC_594, state->reg594);
 766 }
 767
 768 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 769 {
 770         state->vpll = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 771         if(pNv->twoHeads) {
 772                 state->vpll2 = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 773         }
 774         if(pNv->twoStagePLL) {
 775                 state->vpllB = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 776                 state->vpll2B = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 777         }
 778         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 779         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 780 }
 781
 782
 783 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 784 {
 785         if (state->vpll2) {
 786                 if(pNv->twoHeads) {
 787                         ErrorF("writing vpll2 %08X\n", state->vpll2);
 788                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2);
 789                 }
 790                 if(pNv->twoStagePLL) {
 791                         ErrorF("writing vpll2B %08X\n", state->vpll2B);
 792                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2B);
 793                 }
 794
 795                 ErrorF("writing pllsel %08X\n", state->pllsel);
 796                 /* Let's keep the primary vpll off */
 797                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 798         }
 799
 800         if (state->vpll) {
 801                 ErrorF("writing vpll %08X\n", state->vpll);
 802                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll);
 803                 if(pNv->twoStagePLL) {
 804                         ErrorF("writing vpllB %08X\n", state->vpllB);
 805                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpllB);
 806                 }
 807
 808                 ErrorF("writing pllsel %08X\n", state->pllsel);
 809                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 810         }
 811
 812         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 813         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 814 }
 815
 816 #define IS_NV44P (pNv->NVArch >= 0x44 ? 1 : 0)
 817 #define SEL_CLK_OFFSET (16 - 4 * !nv_output->preferred_output * (1 + IS_NV44P))
 818 #define SEL_CLK_OFFSET_INV (16 - 4 * nv_output->preferred_output * (1 + IS_NV44P))
 819
 820 /*
 821  * Calculate extended mode parameters (SVGA) and save in a
 822  * mode state structure.
 823  * State is not specific to a single crtc, but shared.
 824  */
 825 void nv_crtc_calc_state_ext(
 826         xf86CrtcPtr     crtc,
 827         int                     bpp,
 828         int                     DisplayWidth, /* Does this change after setting the mode? */
 829         int                     CrtcHDisplay,
 830         int                     CrtcVDisplay,
 831         int                     dotClock,
 832         int                     flags
 833 )
 834 {
 835         ScrnInfoPtr pScrn = crtc->scrn;
 836         uint32_t pixelDepth, VClk = 0;
 837         CARD32 CursorStart;
 838         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 839         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 840         NVCrtcRegPtr regp;
 841         NVPtr pNv = NVPTR(pScrn);
 842         RIVA_HW_STATE *state, *sv_state;
 843         int num_crtc_enabled, i;
 844
 845         state = &pNv->ModeReg;
 846         sv_state = &pNv->SavedReg;
 847
 848         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 849
 850         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 851         NVOutputPrivatePtr nv_output = NULL;
 852         if (output) {
 853                 nv_output = output->driver_private;
 854         }
 855
 856         /*
 857          * Extended RIVA registers.
 858          */
 859         pixelDepth = (bpp + 1)/8;
 860         if (pNv->Architecture == NV_ARCH_40) {
 861                 /* Does register 0x580 already have a value? */
 862                 if (!state->reg580) {
 863                         state->reg580 = pNv->misc_info.ramdac_0_reg_580;
 864                 }
 865                 if (nv_crtc->head == 1) {
 866                         CalculateVClkNV4x(pNv, dotClock, &VClk, &state->vpll2_a, &state->vpll2_b, &state->reg580, &state->db1_ratio[1], FALSE, (sv_state->vpll2_a >> 30));
 867                 } else {
 868                         CalculateVClkNV4x(pNv, dotClock, &VClk, &state->vpll1_a, &state->vpll1_b, &state->reg580, &state->db1_ratio[0], TRUE, (sv_state->vpll1_a >> 30));
 869                 }
 870         } else if (pNv->twoStagePLL) {
 871                 CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB, pNv);
 872         } else {
 873                 CalcVClock(dotClock, &VClk, &state->pll, pNv);
 874         }
 875
 876         switch (pNv->Architecture) {
 877         case NV_ARCH_04:
 878                 nv4UpdateArbitrationSettings(VClk,
 879                                                 pixelDepth * 8,
 880                                                 &(state->arbitration0),
 881                                                 &(state->arbitration1),
 882                                                 pNv);
 883                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
 884                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
 885                 if (flags & V_DBLSCAN)
 886                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 887                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
 888                 state->pllsel   |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
 889                 state->config   = 0x00001114;
 890                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 891                 break;
 892         case NV_ARCH_10:
 893         case NV_ARCH_20:
 894         case NV_ARCH_30:
 895         default:
 896                 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
 897                         ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
 898                         state->arbitration0 = 128;
 899                         state->arbitration1 = 0x0480;
 900                 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
 901                         ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
 902                         nForceUpdateArbitrationSettings(VClk,
 903                                                 pixelDepth * 8,
 904                                                 &(state->arbitration0),
 905                                                 &(state->arbitration1),
 906                                                 pNv);
 907                 } else if (pNv->Architecture < NV_ARCH_30) {
 908                         nv10UpdateArbitrationSettings(VClk,
 909                                                 pixelDepth * 8,
 910                                                 &(state->arbitration0),
 911                                                 &(state->arbitration1),
 912                                                 pNv);
 913                 } else {
 914                         nv30UpdateArbitrationSettings(pNv,
 915                                                 &(state->arbitration0),
 916                                                 &(state->arbitration1));
 917                 }
 918
 919                 CursorStart = pNv->Cursor->offset;
 920
 921                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
 922                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
 923                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
 924
 925                 if (flags & V_DBLSCAN)
 926                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 927
 928                 state->config   = nvReadFB(pNv, NV_PFB_CFG0);
 929                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 930                 break;
 931         }
 932
 933         /* okay do we have 2 CRTCs running ? */
 934         num_crtc_enabled = 0;
 935         for (i = 0; i < xf86_config->num_crtc; i++) {
 936                 if (xf86_config->crtc[i]->enabled) {
 937                         num_crtc_enabled++;
 938                 }
 939         }
 940
 941         ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
 942
 943         if (pNv->Architecture < NV_ARCH_40) {
 944                 /* We need this before the next code */
 945                 if (nv_crtc->head == 1) {
 946                         state->vpll2 = state->pll;
 947                         state->vpll2B = state->pllB;
 948                 } else {
 949                         state->vpll = state->pll;
 950                         state->vpllB = state->pllB;
 951                 }
 952         }
 953
 954         if (pNv->Architecture == NV_ARCH_40) {
 955                 /* This register is only used on the primary ramdac */
 956                 /* This seems to be needed to select the proper clocks, otherwise bad things happen */
 957
 958                 if (!state->sel_clk)
 959                         state->sel_clk = pNv->misc_info.sel_clk & ~(0xfff << 8);
 960
 961                 /* There are a few possibilities:
 962                  * Early NV4x cards: 0x41000 for example
 963                  * Later NV4x cards: 0x40100 for example
 964                  * The lower entry is the first bus, the higher entry is the second bus
 965                  * 0: No dvi present
 966                  * 1: Primary clock
 967                  * 2: Unknown, similar to 4?
 968                  * 4: Secondary clock
 969                  */
 970
 971                 /* This won't work when tv-out's come into play */
 972                 state->sel_clk &= ~(0xf << SEL_CLK_OFFSET);
 973                 if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
 974                         if (nv_crtc->head == 1) { /* secondary clock */
 975                                 state->sel_clk |= (0x4 << SEL_CLK_OFFSET);
 976                                 /* Does the other output occupy the same clock? -> Switch it to primary clock */
 977                                 if ((state->sel_clk & (0xf << SEL_CLK_OFFSET_INV)) == (0x4 << SEL_CLK_OFFSET_INV)) {
 978                                         state->sel_clk &= ~(0xf << SEL_CLK_OFFSET_INV);
 979                                         state->sel_clk |= (0x1 << SEL_CLK_OFFSET_INV);
 980                                 }
 981                         } else { /* primary clock */
 982                                 state->sel_clk |= (0x1 << SEL_CLK_OFFSET);
 983                                 /* Does the other output occupy the same clock? -> Switch it to secondary clock */
 984                                 if ((state->sel_clk & (0xf << SEL_CLK_OFFSET_INV)) == (0x1 << SEL_CLK_OFFSET_INV)) {
 985                                         state->sel_clk &= ~(0xf << SEL_CLK_OFFSET_INV);
 986                                         state->sel_clk |= (0x4 << SEL_CLK_OFFSET_INV);
 987                                 }
 988                         }
 989                 }
 990
 991                 /* The hardware gets upset if for example 0x00100 is set instead of 0x40100 */
 992                 if ((state->sel_clk & (0xff << 8)) && !(state->sel_clk & (0xf << 16))) {
 993                         if ((state->sel_clk & (0xf << (12 -  4*IS_NV44P))) == (0x1 << (12 -  4*IS_NV44P))) {
 994                                 state->sel_clk |= (0x4 << 16);
 995                         } else {
 996                                 state->sel_clk |= (0x1 << 16);
 997                         }
 998                 }
 999
1000                 /* Are we crosswired? */
1001                 if (output && nv_crtc->head != nv_output->preferred_output &&
1002                         (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
1003                         state->crosswired = TRUE;
1004                 } else if (output && nv_crtc->head != nv_output->preferred_output) {
1005                         state->crosswired = FALSE;
1006                 } else {
1007                         state->crosswired = FALSE;
1008                 }
1009
1010                 if (nv_crtc->head == 1) {
1011                         if (state->db1_ratio[1])
1012                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1013                 } else if (nv_crtc->head == 0) {
1014                         if (state->db1_ratio[0])
1015                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1016                 }
1017         } else {
1018                 /* This seems true for nv34 */
1019                 state->sel_clk = 0x0;
1020                 state->crosswired = FALSE;
1021         }
1022
1023         if (nv_crtc->head == 1) {
1024                 if (!state->db1_ratio[1]) {
1025                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1026                 } else {
1027                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1028                 }
1029                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
1030         } else {
1031                 if (pNv->Architecture < NV_ARCH_40)
1032                         state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
1033                 else
1034                         state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
1035                 if (!state->db1_ratio[0]) {
1036                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1037                 } else {
1038                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1039                 }
1040         }
1041
1042         /* The blob uses this always, so let's do the same */
1043         if (pNv->Architecture == NV_ARCH_40) {
1044                 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
1045         }
1046
1047         /* The primary output doesn't seem to care */
1048         if (nv_output->preferred_output == 1) { /* This is the "output" */
1049                 /* non-zero values are for analog, don't know about tv-out and the likes */
1050                 if (output && nv_output->type != OUTPUT_ANALOG) {
1051                         state->reg594 = 0x0;
1052                 } else {
1053                         /* More values exist, but they seem related to the 3rd dac (tv-out?) somehow */
1054                         /* bit 16-19 are bits that are set on some G70 cards */
1055                         /* Those bits are also set to the 3rd OUTPUT register */
1056                         if (nv_crtc->head == 1) {
1057                                 state->reg594 = 0x101;
1058                         } else {
1059                                 state->reg594 = 0x1;
1060                         }
1061                 }
1062         }
1063
1064         regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
1065         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
1066         if (pNv->Architecture >= NV_ARCH_30) {
1067                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
1068         }
1069
1070         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
1071         regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
1072 }
1073
1074 static void
1075 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
1076 {
1077         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1078         ScrnInfoPtr pScrn = crtc->scrn;
1079         NVPtr pNv = NVPTR(pScrn);
1080         unsigned char seq1 = 0, crtc17 = 0;
1081         unsigned char crtc1A;
1082
1083         ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->crtc, mode);
1084
1085         NVCrtcSetOwner(crtc);
1086
1087         crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
1088         switch(mode) {
1089                 case DPMSModeStandby:
1090                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
1091                 seq1 = 0x20;
1092                 crtc17 = 0x80;
1093                 crtc1A |= 0x80;
1094                 break;
1095         case DPMSModeSuspend:
1096                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
1097                 seq1 = 0x20;
1098                 crtc17 = 0x80;
1099                 crtc1A |= 0x40;
1100                 break;
1101         case DPMSModeOff:
1102                 /* Screen: Off; HSync: Off, VSync: Off */
1103                 seq1 = 0x20;
1104                 crtc17 = 0x00;
1105                 crtc1A |= 0xC0;
1106                 break;
1107         case DPMSModeOn:
1108         default:
1109                 /* Screen: On; HSync: On, VSync: On */
1110                 seq1 = 0x00;
1111                 crtc17 = 0x80;
1112                 break;
1113         }
1114
1115         NVVgaSeqReset(crtc, TRUE);
1116         /* Each head has it's own sequencer, so we can turn it off when we want */
1117         seq1 |= (NVReadVgaSeq(crtc, 0x01) & ~0x20);
1118         NVWriteVgaSeq(crtc, 0x1, seq1);
1119         crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
1120         usleep(10000);
1121         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
1122         NVVgaSeqReset(crtc, FALSE);
1123
1124         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
1125
1126         /* I hope this is the right place */
1127         if (crtc->enabled && mode == DPMSModeOn) {
1128                 pNv->crtc_active[nv_crtc->head] = TRUE;
1129         } else {
1130                 pNv->crtc_active[nv_crtc->head] = FALSE;
1131         }
1132 }
1133
1134 static Bool
1135 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
1136                      DisplayModePtr adjusted_mode)
1137 {
1138         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1139         ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->crtc);
1140
1141         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1142         NVOutputPrivatePtr nv_output = NULL;
1143         if (output) {
1144                 nv_output = output->driver_private;
1145         }
1146
1147         /* For internal panels and gpu scaling on DVI we need the native mode */
1148         if (output && ((nv_output->type == OUTPUT_LVDS) || (nv_output->scaling_mode > 0 && (nv_output->type == OUTPUT_TMDS)))) {
1149                 adjusted_mode->HDisplay = nv_output->native_mode->HDisplay;
1150                 adjusted_mode->HSkew = nv_output->native_mode->HSkew;
1151                 adjusted_mode->HSyncStart = nv_output->native_mode->HSyncStart;
1152                 adjusted_mode->HSyncEnd = nv_output->native_mode->HSyncEnd;
1153                 adjusted_mode->HTotal = nv_output->native_mode->HTotal;
1154                 adjusted_mode->VDisplay = nv_output->native_mode->VDisplay;
1155                 adjusted_mode->VScan = nv_output->native_mode->VScan;
1156                 adjusted_mode->VSyncStart = nv_output->native_mode->VSyncStart;
1157                 adjusted_mode->VSyncEnd = nv_output->native_mode->VSyncEnd;
1158                 adjusted_mode->VTotal = nv_output->native_mode->VTotal;
1159                 adjusted_mode->Clock = nv_output->native_mode->Clock;
1160
1161                 xf86SetModeCrtc(adjusted_mode, INTERLACE_HALVE_V);
1162         }
1163
1164         return TRUE;
1165 }
1166
1167 static void
1168 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1169 {
1170         ScrnInfoPtr pScrn = crtc->scrn;
1171         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1172         NVCrtcRegPtr regp;
1173         NVPtr pNv = NVPTR(pScrn);
1174         NVFBLayout *pLayout = &pNv->CurrentLayout;
1175         int depth = pScrn->depth;
1176
1177         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1178
1179         /* Calculate our timings */
1180         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
1181         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
1182         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
1183         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
1184         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
1185         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
1186         int vertDisplay         = mode->CrtcVDisplay                    - 1;
1187         int vertStart           = mode->CrtcVSyncStart          - 1;
1188         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
1189         int vertTotal           = mode->CrtcVTotal                      - 2;
1190         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
1191         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
1192
1193         Bool is_fp = FALSE;
1194
1195         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1196         NVOutputPrivatePtr nv_output = NULL;
1197         if (output) {
1198                 nv_output = output->driver_private;
1199
1200                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1201                         is_fp = TRUE;
1202         }
1203
1204         ErrorF("Mode clock: %d\n", mode->Clock);
1205         ErrorF("Adjusted mode clock: %d\n", adjusted_mode->Clock);
1206
1207         /* Reverted to what nv did, because that works for all resolutions on flatpanels */
1208         if (is_fp) {
1209                 vertStart = vertTotal - 3;
1210                 vertEnd = vertTotal - 2;
1211                 vertBlankStart = vertStart;
1212                 horizStart = horizTotal - 5;
1213                 horizEnd = horizTotal - 2;
1214                 horizBlankEnd = horizTotal + 4;
1215                 if (pNv->overlayAdaptor) {
1216                         /* This reportedly works around Xv some overlay bandwidth problems*/
1217                         horizTotal += 2;
1218                 }
1219         }
1220
1221         if(mode->Flags & V_INTERLACE)
1222                 vertTotal |= 1;
1223
1224         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
1225         ErrorF("horizStart: 0x%X \n", horizStart);
1226         ErrorF("horizEnd: 0x%X \n", horizEnd);
1227         ErrorF("horizTotal: 0x%X \n", horizTotal);
1228         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
1229         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
1230         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
1231         ErrorF("vertStart: 0x%X \n", vertStart);
1232         ErrorF("vertEnd: 0x%X \n", vertEnd);
1233         ErrorF("vertTotal: 0x%X \n", vertTotal);
1234         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
1235         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
1236
1237         /*
1238         * compute correct Hsync & Vsync polarity
1239         */
1240         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
1241                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
1242
1243                 regp->MiscOutReg = 0x23;
1244                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
1245                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
1246         } else {
1247                 int VDisplay = mode->VDisplay;
1248                 if (mode->Flags & V_DBLSCAN)
1249                         VDisplay *= 2;
1250                 if (mode->VScan > 1)
1251                         VDisplay *= mode->VScan;
1252                 if (VDisplay < 400) {
1253                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
1254                 } else if (VDisplay < 480) {
1255                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
1256                 } else if (VDisplay < 768) {
1257                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
1258                 } else {
1259                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
1260                 }
1261         }
1262
1263         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
1264
1265         /*
1266         * Time Sequencer
1267         */
1268         if (depth == 4) {
1269                 regp->Sequencer[0] = 0x02;
1270         } else {
1271                 regp->Sequencer[0] = 0x00;
1272         }
1273         /* 0x20 disables the sequencer */
1274         if (mode->Flags & V_CLKDIV2) {
1275                 regp->Sequencer[1] = 0x29;
1276         } else {
1277                 regp->Sequencer[1] = 0x21;
1278         }
1279         if (depth == 1) {
1280                 regp->Sequencer[2] = 1 << BIT_PLANE;
1281         } else {
1282                 regp->Sequencer[2] = 0x0F;
1283                 regp->Sequencer[3] = 0x00;                     /* Font select */
1284         }
1285         if (depth < 8) {
1286                 regp->Sequencer[4] = 0x06;                             /* Misc */
1287         } else {
1288                 regp->Sequencer[4] = 0x0E;                             /* Misc */
1289         }
1290
1291         /*
1292         * CRTC Controller
1293         */
1294         regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
1295         regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
1296         regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
1297         regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0)
1298                                 | SetBit(7);
1299         regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
1300         regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
1301                                 | SetBitField(horizEnd,4:0,4:0);
1302         regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
1303         regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
1304                                 | SetBitField(vertDisplay,8:8,1:1)
1305                                 | SetBitField(vertStart,8:8,2:2)
1306                                 | SetBitField(vertBlankStart,8:8,3:3)
1307                                 | SetBit(4)
1308                                 | SetBitField(vertTotal,9:9,5:5)
1309                                 | SetBitField(vertDisplay,9:9,6:6)
1310                                 | SetBitField(vertStart,9:9,7:7);
1311         regp->CRTC[NV_VGA_CRTCX_PRROWSCN]  = 0x00;
1312         regp->CRTC[NV_VGA_CRTCX_MAXSCLIN]  = SetBitField(vertBlankStart,9:9,5:5)
1313                                 | SetBit(6)
1314                                 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00);
1315         regp->CRTC[NV_VGA_CRTCX_VGACURCTRL] = 0x00;
1316         regp->CRTC[0xb] = 0x00;
1317         regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00;
1318         regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
1319         regp->CRTC[0xe] = 0x00;
1320         regp->CRTC[0xf] = 0x00;
1321         regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
1322         regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
1323         regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
1324         regp->CRTC[0x14] = 0x00;
1325         regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
1326         regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
1327         regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
1328         /* 0x80 enables the sequencer, we don't want that */
1329         if (depth < 8) {
1330                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xE3 & ~0x80;
1331         } else {
1332                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80;
1333         }
1334         regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
1335
1336         /*
1337          * Some extended CRTC registers (they are not saved with the rest of the vga regs).
1338          */
1339
1340         regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
1341                                 | SetBitField(vertBlankStart,10:10,3:3)
1342                                 | SetBitField(vertStart,10:10,2:2)
1343                                 | SetBitField(vertDisplay,10:10,1:1)
1344                                 | SetBitField(vertTotal,10:10,0:0);
1345
1346         regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
1347                                 | SetBitField(horizDisplay,8:8,1:1)
1348                                 | SetBitField(horizBlankStart,8:8,2:2)
1349                                 | SetBitField(horizStart,8:8,3:3);
1350
1351         regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
1352                                 | SetBitField(vertDisplay,11:11,2:2)
1353                                 | SetBitField(vertStart,11:11,4:4)
1354                                 | SetBitField(vertBlankStart,11:11,6:6);
1355
1356         if(mode->Flags & V_INTERLACE) {
1357                 horizTotal = (horizTotal >> 1) & ~1;
1358                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
1359                 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
1360         } else {
1361                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff;  /* interlace off */
1362         }
1363
1364         /*
1365         * Theory resumes here....
1366         */
1367
1368         /*
1369         * Graphics Display Controller
1370         */
1371         regp->Graphics[0] = 0x00;
1372         regp->Graphics[1] = 0x00;
1373         regp->Graphics[2] = 0x00;
1374         regp->Graphics[3] = 0x00;
1375         if (depth == 1) {
1376                 regp->Graphics[4] = BIT_PLANE;
1377                 regp->Graphics[5] = 0x00;
1378         } else {
1379                 regp->Graphics[4] = 0x00;
1380                 if (depth == 4) {
1381                         regp->Graphics[5] = 0x02;
1382                 } else {
1383                         regp->Graphics[5] = 0x40;
1384                 }
1385         }
1386         regp->Graphics[6] = 0x05;   /* only map 64k VGA memory !!!! */
1387         regp->Graphics[7] = 0x0F;
1388         regp->Graphics[8] = 0xFF;
1389
1390         /* I ditched the mono stuff */
1391         regp->Attribute[0]  = 0x00; /* standard colormap translation */
1392         regp->Attribute[1]  = 0x01;
1393         regp->Attribute[2]  = 0x02;
1394         regp->Attribute[3]  = 0x03;
1395         regp->Attribute[4]  = 0x04;
1396         regp->Attribute[5]  = 0x05;
1397         regp->Attribute[6]  = 0x06;
1398         regp->Attribute[7]  = 0x07;
1399         regp->Attribute[8]  = 0x08;
1400         regp->Attribute[9]  = 0x09;
1401         regp->Attribute[10] = 0x0A;
1402         regp->Attribute[11] = 0x0B;
1403         regp->Attribute[12] = 0x0C;
1404         regp->Attribute[13] = 0x0D;
1405         regp->Attribute[14] = 0x0E;
1406         regp->Attribute[15] = 0x0F;
1407         /* These two below are non-vga */
1408         regp->Attribute[16] = 0x01;
1409         regp->Attribute[17] = 0x00;
1410         regp->Attribute[18] = 0x0F;
1411         regp->Attribute[19] = 0x00;
1412         regp->Attribute[20] = 0x00;
1413 }
1414
1415 #define MAX_H_VALUE(i) ((0x1ff + i) << 3)
1416 #define MAX_V_VALUE(i) ((0xfff + i) << 0)
1417
1418 /**
1419  * Sets up registers for the given mode/adjusted_mode pair.
1420  *
1421  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1422  *
1423  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1424  * be easily turned on/off after this.
1425  */
1426 static void
1427 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1428 {
1429         ScrnInfoPtr pScrn = crtc->scrn;
1430         NVPtr pNv = NVPTR(pScrn);
1431         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1432         NVFBLayout *pLayout = &pNv->CurrentLayout;
1433         NVCrtcRegPtr regp, savep;
1434         unsigned int i;
1435         Bool is_fp = FALSE;
1436
1437         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1438         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1439
1440         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1441         NVOutputPrivatePtr nv_output = NULL;
1442         if (output) {
1443                 nv_output = output->driver_private;
1444
1445                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1446                         is_fp = TRUE;
1447         }
1448
1449         /* Registers not directly related to the (s)vga mode */
1450
1451         /* bit2 = 0 -> fine pitched crtc granularity */
1452         /* The rest disables double buffering on CRTC access */
1453         regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
1454
1455         if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
1456                 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1457                 if (nv_crtc->head == 0) {
1458                         regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1459                 }
1460
1461                 if (is_fp) {
1462                         regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0) | (1 << 1);
1463                 }
1464         } else {
1465                 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
1466                 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
1467         }
1468
1469         /* Sometimes 0x10 is used, what is this? */
1470         regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1471         /* Some kind of tmds switch for older cards */
1472         if (pNv->Architecture < NV_ARCH_40) {
1473                 regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
1474         }
1475
1476         /*
1477         * Initialize DAC palette.
1478         */
1479         if(pLayout->bitsPerPixel != 8 ) {
1480                 for (i = 0; i < 256; i++) {
1481                         regp->DAC[i*3]     = i;
1482                         regp->DAC[(i*3)+1] = i;
1483                         regp->DAC[(i*3)+2] = i;
1484                 }
1485         }
1486
1487         /*
1488         * Calculate the extended registers.
1489         */
1490
1491         if(pLayout->depth < 24) {
1492                 i = pLayout->depth;
1493         } else {
1494                 i = 32;
1495         }
1496
1497         if(pNv->Architecture >= NV_ARCH_10) {
1498                 pNv->CURSOR = (CARD32 *)pNv->Cursor->map;
1499         }
1500
1501         /* What is the meaning of this register? */
1502         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1503         regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
1504
1505         /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1506         /* But what are those special conditions? */
1507         if (pNv->Architecture <= NV_ARCH_30) {
1508                 if (is_fp) {
1509                         if(nv_crtc->head == 1) {
1510                                 regp->head |= NV_CRTC_FSEL_FPP1;
1511                         } else if (pNv->twoHeads) {
1512                                 regp->head |= NV_CRTC_FSEL_FPP2;
1513                         }
1514                 }
1515         } else {
1516                 /* Some G70 cards have either FPP1 or FPP2 set, copy this if it's already present */
1517                 if (nv_crtc->head == 1 && pNv->NVArch > 0x44) {
1518                         regp->head |= savep->head & (NV_CRTC_FSEL_FPP1 | NV_CRTC_FSEL_FPP2);
1519                 }
1520         }
1521
1522         /* Except for rare conditions I2C is enabled on the primary crtc */
1523         if (nv_crtc->head == 0) {
1524                 if (pNv->overlayAdaptor) {
1525                         regp->head |= NV_CRTC_FSEL_OVERLAY;
1526                 }
1527                 regp->head |= NV_CRTC_FSEL_I2C;
1528         }
1529
1530         /* This is not what nv does, but it is what the blob does (for nv4x at least) */
1531         /* This fixes my cursor corruption issue */
1532         regp->cursorConfig = 0x0;
1533         if(mode->Flags & V_DBLSCAN)
1534                 regp->cursorConfig |= (1 << 4);
1535         if (pNv->alphaCursor) {
1536                 /* bit28 means we go into alpha blend mode and not rely on the current ROP */
1537                 regp->cursorConfig |= 0x14011000;
1538         } else {
1539                 regp->cursorConfig |= 0x02000000;
1540         }
1541
1542         /* Unblock some timings */
1543         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1544         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1545
1546         /* What is the purpose of this register? */
1547         if (nv_crtc->head == 1) {
1548                 regp->CRTC[NV_VGA_CRTCX_26] = 0x14;
1549         } else {
1550                 regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1551         }
1552
1553         /* 0x00 is disabled, 0x22 crt and 0x88 dfp */
1554         /* 0x11 is LVDS? */
1555         if (is_fp) {
1556                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1557         } else {
1558                 /* 0x20 is also seen sometimes, why? */
1559                 if (nv_crtc->head == 1) {
1560                         regp->CRTC[NV_VGA_CRTCX_3B] = 0x24;
1561                 } else {
1562                         regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1563                 }
1564         }
1565
1566         /* These values seem to vary */
1567         if (nv_crtc->head == 1) {
1568                 regp->CRTC[NV_VGA_CRTCX_3C] = 0x0;
1569         } else {
1570                 regp->CRTC[NV_VGA_CRTCX_3C] = 0x70;
1571         }
1572
1573         /* 0x80 seems to be used very often, if not always */
1574         regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1575
1576         if (nv_crtc->head == 1) {
1577                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x0;
1578         } else {
1579                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x1;
1580         }
1581
1582         if (is_fp)
1583                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x80;
1584
1585         /* Are these(0x55 and 0x56) also timing related registers, since disabling them does nothing? */
1586         regp->CRTC[NV_VGA_CRTCX_55] = 0x0;
1587
1588         /* Common values like 0x14 and 0x04 are converted to 0x10 and 0x00 */
1589         regp->CRTC[NV_VGA_CRTCX_56] = 0x0;
1590
1591         /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1*/
1592         if (nv_crtc->head == 1) {
1593                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52;
1594         } else {
1595                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52 + 4;
1596         }
1597
1598         /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1599         regp->unk81c = nvReadCRTC0(pNv, NV_CRTC_081C);
1600
1601         regp->unk830 = mode->CrtcVDisplay - 3;
1602         regp->unk834 = mode->CrtcVDisplay - 1;
1603
1604         /* This is what the blob does */
1605         regp->unk850 = nvReadCRTC(pNv, 0, NV_CRTC_0850);
1606
1607         /* Never ever modify gpio, unless you know very well what you're doing */
1608         regp->gpio = nvReadCRTC(pNv, 0, NV_CRTC_GPIO);
1609
1610         /* Switch to non-vga mode (the so called HSYNC mode) */
1611         regp->config = 0x2;
1612
1613         /*
1614          * Calculate the state that is common to all crtc's (stored in the state struct).
1615          */
1616         ErrorF("crtc %d %d %d\n", nv_crtc->crtc, mode->CrtcHDisplay, pScrn->displayWidth);
1617         nv_crtc_calc_state_ext(crtc,
1618                                 i,
1619                                 pScrn->displayWidth,
1620                                 mode->CrtcHDisplay,
1621                                 mode->CrtcVDisplay,
1622                                 adjusted_mode->Clock,
1623                                 mode->Flags);
1624
1625         /* Enable slaved mode */
1626         if (is_fp) {
1627                 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1628         }
1629 }
1630
1631 static void
1632 nv_crtc_mode_set_ramdac_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1633 {
1634         ScrnInfoPtr pScrn = crtc->scrn;
1635         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1636         NVCrtcRegPtr regp;
1637         NVPtr pNv = NVPTR(pScrn);
1638         NVFBLayout *pLayout = &pNv->CurrentLayout;
1639         Bool is_fp = FALSE;
1640         Bool is_lvds = FALSE;
1641         float aspect_ratio, panel_ratio;
1642         uint32_t h_scale, v_scale;
1643
1644         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1645
1646         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1647         NVOutputPrivatePtr nv_output = NULL;
1648         if (output) {
1649                 nv_output = output->driver_private;
1650
1651                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1652                         is_fp = TRUE;
1653
1654                 if (nv_output->type == OUTPUT_LVDS)
1655                         is_lvds = TRUE;
1656         }
1657
1658         if (is_fp) {
1659                 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
1660                 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
1661                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HDisplay;
1662                 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
1663                 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
1664                 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
1665                 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
1666
1667                 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
1668                 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
1669                 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VDisplay;
1670                 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
1671                 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
1672                 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
1673                 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
1674
1675                 ErrorF("Horizontal:\n");
1676                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
1677                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
1678                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
1679                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
1680                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
1681                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
1682                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
1683
1684                 ErrorF("Vertical:\n");
1685                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
1686                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
1687                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
1688                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
1689                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
1690                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
1691                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
1692         }
1693
1694         /*
1695         * bit0: positive vsync
1696         * bit4: positive hsync
1697         * bit8: enable panel scaling
1698         * bit9: something related to dual link dvi?
1699         * bit26: a bit sometimes seen on some g70 cards
1700         * bit31: set for dual link LVDS
1701         * This must also be set for non-flatpanels
1702         * Some bits seem shifted for vga monitors
1703         */
1704
1705         if (is_fp) {
1706                 regp->fp_control = 0x11100000;
1707         } else {
1708                 regp->fp_control = 0x21100000;
1709         }
1710
1711         if (is_lvds && pNv->VBIOS.fp.dual_link)
1712                 regp->fp_control |= 0x80000000;
1713         else {
1714                 /* If the special bit exists, it exists on both ramdac's */
1715                 regp->fp_control |= nvReadRAMDAC0(pNv, NV_RAMDAC_FP_CONTROL) & (1 << 26);
1716         }
1717
1718         /* Does this turn something off, since it's similar to what is used in dpms (being a "2" bit)? */
1719         if (is_fp && !is_lvds && pNv->dcb_table.entry[nv_output->dcb_entry].duallink_possible)
1720                 regp->fp_control |= (1 << 9);
1721
1722         /* Deal with vsync/hsync polarity */
1723         /* These analog monitor offsets are guesswork */
1724         if (adjusted_mode->Flags & V_PVSYNC) {
1725                 regp->fp_control |= (1 << (0 + !is_fp));
1726         }
1727
1728         if (adjusted_mode->Flags & V_PHSYNC) {
1729                 regp->fp_control |= (1 << (4 + !is_fp));
1730         }
1731
1732         if (is_fp) {
1733                 ErrorF("Pre-panel scaling\n");
1734                 ErrorF("panel-size:%dx%d\n", nv_output->fpWidth, nv_output->fpHeight);
1735                 panel_ratio = (nv_output->fpWidth)/(float)(nv_output->fpHeight);
1736                 ErrorF("panel_ratio=%f\n", panel_ratio);
1737                 aspect_ratio = (mode->HDisplay)/(float)(mode->VDisplay);
1738                 ErrorF("aspect_ratio=%f\n", aspect_ratio);
1739                 /* Scale factors is the so called 20.12 format, taken from Haiku */
1740                 h_scale = ((1 << 12) * mode->HDisplay)/nv_output->fpWidth;
1741                 v_scale = ((1 << 12) * mode->VDisplay)/nv_output->fpHeight;
1742                 ErrorF("h_scale=%d\n", h_scale);
1743                 ErrorF("v_scale=%d\n", v_scale);
1744
1745                 /* Don't limit last fetched line */
1746                 regp->debug_2 = 0;
1747
1748                 /* We want automatic scaling */
1749                 regp->debug_1 = 0;
1750
1751                 regp->fp_hvalid_start = 0;
1752                 regp->fp_hvalid_end = (nv_output->fpWidth - 1);
1753
1754                 regp->fp_vvalid_start = 0;
1755                 regp->fp_vvalid_end = (nv_output->fpHeight - 1);
1756
1757                 /* 0 = panel scaling */
1758                 if (nv_output->scaling_mode == 0) {
1759                         ErrorF("Flat panel is doing the scaling.\n");
1760                         regp->fp_control |= (1 << 8);
1761                 } else {
1762                         ErrorF("GPU is doing the scaling.\n");
1763
1764                         /* 1 = fullscale gpu */
1765                         /* 2 = aspect ratio scaling */
1766                         if (nv_output->scaling_mode == 2) {
1767                                 /* GPU scaling happens automaticly at a ratio of 1.33 */
1768                                 /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
1769                                 if (h_scale != (1 << 12) && (panel_ratio > (aspect_ratio + 0.10))) {
1770                                         uint32_t diff;
1771
1772                                         ErrorF("Scaling resolution on a widescreen panel\n");
1773
1774                                         /* Scaling in both directions needs to the same */
1775                                         h_scale = v_scale;
1776
1777                                         /* Set a new horizontal scale factor and enable testmode (bit12) */
1778                                         regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
1779
1780                                         diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
1781                                         regp->fp_hvalid_start = diff/2;
1782                                         regp->fp_hvalid_end = nv_output->fpWidth - (diff/2) - 1;
1783                                 }
1784
1785                                 /* Same scaling, just for panels with aspect ratio's smaller than 1 */
1786                                 if (v_scale != (1 << 12) && (panel_ratio < (aspect_ratio - 0.10))) {
1787                                         uint32_t diff;
1788
1789                                         ErrorF("Scaling resolution on a portrait panel\n");
1790
1791                                         /* Scaling in both directions needs to the same */
1792                                         v_scale = h_scale;
1793
1794                                         /* Set a new vertical scale factor and enable testmode (bit28) */
1795                                         regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
1796
1797                                         diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
1798                                         regp->fp_vvalid_start = diff/2;
1799                                         regp->fp_vvalid_end = nv_output->fpHeight - (diff/2) - 1;
1800                                 }
1801                         }
1802                 }
1803
1804                 ErrorF("Post-panel scaling\n");
1805         }
1806
1807         if (pNv->Architecture >= NV_ARCH_10) {
1808                 /* Bios and blob don't seem to do anything (else) */
1809                 regp->nv10_cursync = (1<<25);
1810         }
1811
1812         /* These are the common blob values, minus a few fp specific bit's */
1813         /* Let's keep the TMDS pll and fpclock running in all situations */
1814         regp->debug_0 = 0x1101111;
1815
1816         if(is_fp) {
1817                 /* I am not completely certain, but seems to be set only for dfp's */
1818                 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED;
1819         }
1820
1821         if (output)
1822                 ErrorF("output %d debug_0 %08X\n", nv_output->preferred_output, regp->debug_0);
1823
1824         /* Flatpanel support needs at least a NV10 */
1825         if(pNv->twoHeads) {
1826                 /* Instead of 1, several other values are also used: 2, 7, 9 */
1827                 /* The purpose is unknown */
1828                 if(pNv->FPDither) {
1829                         regp->dither = 0x00010000;
1830                 }
1831         }
1832
1833         /* Kindly borrowed from haiku driver */
1834         /* bit4 and bit5 activate indirect mode trough color palette */
1835         switch (pLayout->depth) {
1836                 case 32:
1837                 case 16:
1838                         regp->general = 0x00101130;
1839                         break;
1840                 case 24:
1841                 case 15:
1842                         regp->general = 0x00100130;
1843                         break;
1844                 case 8:
1845                 default:
1846                         regp->general = 0x00101100;
1847                         break;
1848         }
1849
1850         if (pNv->alphaCursor) {
1851                 regp->general |= (1<<29);
1852         }
1853
1854         /* Some values the blob sets */
1855         /* This may apply to the real ramdac that is being used (for crosswired situations) */
1856         /* Nevertheless, it's unlikely to cause many problems, since the values are equal for both */
1857         regp->unk_a20 = 0x0;
1858         regp->unk_a24 = 0xfffff;
1859         regp->unk_a34 = 0x1;
1860 }
1861
1862 /**
1863  * Sets up registers for the given mode/adjusted_mode pair.
1864  *
1865  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1866  *
1867  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1868  * be easily turned on/off after this.
1869  */
1870 static void
1871 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
1872                  DisplayModePtr adjusted_mode,
1873                  int x, int y)
1874 {
1875         ScrnInfoPtr pScrn = crtc->scrn;
1876         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1877         NVPtr pNv = NVPTR(pScrn);
1878
1879         ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->crtc);
1880
1881         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->crtc);
1882         xf86PrintModeline(pScrn->scrnIndex, mode);
1883         NVCrtcSetOwner(crtc);
1884
1885         nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
1886         nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
1887         nv_crtc_mode_set_ramdac_regs(crtc, mode, adjusted_mode);
1888
1889         /* Just in case */
1890         NVCrtcLockUnlock(crtc, FALSE);
1891
1892         NVVgaProtect(crtc, TRUE);
1893         nv_crtc_load_state_ext(crtc, &pNv->ModeReg, FALSE);
1894         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
1895         if (pNv->Architecture == NV_ARCH_40) {
1896                 nv40_crtc_load_state_pll(pNv, &pNv->ModeReg);
1897         } else {
1898                 nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
1899         }
1900         nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
1901
1902         NVVgaProtect(crtc, FALSE);
1903
1904         NVCrtcSetBase(crtc, x, y);
1905
1906 #if X_BYTE_ORDER == X_BIG_ENDIAN
1907         /* turn on LFB swapping */
1908         {
1909                 unsigned char tmp;
1910
1911                 tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
1912                 tmp |= (1 << 7);
1913                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
1914         }
1915 #endif
1916 }
1917
1918 void nv_crtc_save(xf86CrtcPtr crtc)
1919 {
1920         ScrnInfoPtr pScrn = crtc->scrn;
1921         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1922         NVPtr pNv = NVPTR(pScrn);
1923
1924         ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->crtc);
1925
1926         /* We just came back from terminal, so unlock */
1927         NVCrtcLockUnlock(crtc, FALSE);
1928
1929         NVCrtcSetOwner(crtc);
1930         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
1931         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
1932         if (pNv->Architecture == NV_ARCH_40) {
1933                 nv40_crtc_save_state_pll(pNv, &pNv->SavedReg);
1934         } else {
1935                 nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
1936         }
1937         nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
1938 }
1939
1940 void nv_crtc_restore(xf86CrtcPtr crtc)
1941 {
1942         ScrnInfoPtr pScrn = crtc->scrn;
1943         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1944         NVPtr pNv = NVPTR(pScrn);
1945         RIVA_HW_STATE *state;
1946         NVOutputRegPtr regp;
1947
1948         state = &pNv->SavedReg;
1949
1950         /* Some aspects of an output needs to be restore before the crtc. */
1951         /* In my case this has to do with the mode that i get at very low resolutions. */
1952         /* If i do this at the end, it will not be restored properly */
1953         /* Assumption: crtc0 is restored first. */
1954         if (nv_crtc->head == 0) {
1955                 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
1956                 int i;
1957                 ErrorF("Restore all TMDS timings, before restoring anything else\n");
1958                 for (i = 0; i < config->num_output; i++) {
1959                         NVOutputPrivatePtr nv_output2 = config->output[i]->driver_private;
1960                         regp = &state->dac_reg[nv_output2->preferred_output];
1961                         Bool crosswired = regp->TMDS[0x4] & (1 << 3);
1962                         /* Let's guess the bios state ;-) */
1963                         if (nv_output2->type == OUTPUT_TMDS) {
1964                                 uint32_t clock = nv_calc_tmds_clock_from_pll(config->output[i]);
1965                                 nv_set_tmds_registers(config->output[i], clock, TRUE, crosswired);
1966                         }
1967                         if (nv_output2->type == OUTPUT_TMDS || nv_output2->type == OUTPUT_LVDS)
1968                                 link_head_and_output(pScrn, -1, nv_output2->dcb_entry, crosswired);
1969                 }
1970         }
1971
1972         ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->crtc);
1973
1974         NVCrtcSetOwner(crtc);
1975
1976         /* Just to be safe */
1977         NVCrtcLockUnlock(crtc, FALSE);
1978
1979         NVVgaProtect(crtc, TRUE);
1980         nv_crtc_load_state_ext(crtc, &pNv->SavedReg, TRUE);
1981         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
1982         if (pNv->Architecture == NV_ARCH_40) {
1983                 nv40_crtc_load_state_pll(pNv, &pNv->SavedReg);
1984         } else {
1985                 nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
1986         }
1987         nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
1988         nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->vtOWNER);
1989         NVVgaProtect(crtc, FALSE);
1990
1991         /* We must lock the door if we leave ;-) */
1992         NVCrtcLockUnlock(crtc, TRUE);
1993 }
1994
1995 void nv_crtc_prepare(xf86CrtcPtr crtc)
1996 {
1997         ScrnInfoPtr pScrn = crtc->scrn;
1998         NVPtr pNv = NVPTR(pScrn);
1999         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2000
2001         ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->crtc);
2002
2003         crtc->funcs->dpms(crtc, DPMSModeOff);
2004
2005         /* Sync the engine before adjust mode */
2006         if (pNv->EXADriverPtr) {
2007                 exaMarkSync(pScrn->pScreen);
2008                 exaWaitSync(pScrn->pScreen);
2009         }
2010 }
2011
2012 void nv_crtc_commit(xf86CrtcPtr crtc)
2013 {
2014         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2015         ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->crtc);
2016
2017         crtc->funcs->dpms (crtc, DPMSModeOn);
2018
2019         if (crtc->scrn->pScreen != NULL)
2020                 xf86_reload_cursors (crtc->scrn->pScreen);
2021 }
2022
2023 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
2024 {
2025         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2026         ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->crtc);
2027
2028         return FALSE;
2029 }
2030
2031 static void nv_crtc_unlock(xf86CrtcPtr crtc)
2032 {
2033         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2034         ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->crtc);
2035 }
2036
2037 static void
2038 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
2039                                         int size)
2040 {
2041         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2042         ScrnInfoPtr pScrn = crtc->scrn;
2043         NVPtr pNv = NVPTR(pScrn);
2044         int i, j;
2045
2046         NVCrtcRegPtr regp;
2047         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2048
2049         switch (pNv->CurrentLayout.depth) {
2050         case 15:
2051                 /* R5G5B5 */
2052                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
2053                 for (i = 0; i < 32; i++) {
2054                         for (j = 0; j < 8; j++) {
2055                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2056                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
2057                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2058                         }
2059                 }
2060                 break;
2061         case 16:
2062                 /* R5G6B5 */
2063                 /* First deal with the 5 bit colors */
2064                 for (i = 0; i < 32; i++) {
2065                         for (j = 0; j < 8; j++) {
2066                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2067                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2068                         }
2069                 }
2070                 /* Now deal with the 6 bit color */
2071                 for (i = 0; i < 64; i++) {
2072                         for (j = 0; j < 4; j++) {
2073                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
2074                         }
2075                 }
2076                 break;
2077         default:
2078                 /* R8G8B8 */
2079                 for (i = 0; i < 256; i++) {
2080                         regp->DAC[i * 3] = red[i] >> 8;
2081                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
2082                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
2083                 }
2084                 break;
2085         }
2086
2087         NVCrtcLoadPalette(crtc);
2088 }
2089
2090 /* NV04-NV10 doesn't support alpha cursors */
2091 static const xf86CrtcFuncsRec nv_crtc_funcs = {
2092         .dpms = nv_crtc_dpms,
2093         .save = nv_crtc_save, /* XXX */
2094         .restore = nv_crtc_restore, /* XXX */
2095         .mode_fixup = nv_crtc_mode_fixup,
2096         .mode_set = nv_crtc_mode_set,
2097         .prepare = nv_crtc_prepare,
2098         .commit = nv_crtc_commit,
2099         .destroy = NULL, /* XXX */
2100         .lock = nv_crtc_lock,
2101         .unlock = nv_crtc_unlock,
2102         .set_cursor_colors = nv_crtc_set_cursor_colors,
2103         .set_cursor_position = nv_crtc_set_cursor_position,
2104         .show_cursor = nv_crtc_show_cursor,
2105         .hide_cursor = nv_crtc_hide_cursor,
2106         .load_cursor_image = nv_crtc_load_cursor_image,
2107         .gamma_set = nv_crtc_gamma_set,
2108 };
2109
2110 /* NV11 and up has support for alpha cursors. */
2111 /* Due to different maximum sizes we cannot allow it to use normal cursors */
2112 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
2113         .dpms = nv_crtc_dpms,
2114         .save = nv_crtc_save, /* XXX */
2115         .restore = nv_crtc_restore, /* XXX */
2116         .mode_fixup = nv_crtc_mode_fixup,
2117         .mode_set = nv_crtc_mode_set,
2118         .prepare = nv_crtc_prepare,
2119         .commit = nv_crtc_commit,
2120         .destroy = NULL, /* XXX */
2121         .lock = nv_crtc_lock,
2122         .unlock = nv_crtc_unlock,
2123         .set_cursor_colors = NULL, /* Alpha cursors do not need this */
2124         .set_cursor_position = nv_crtc_set_cursor_position,
2125         .show_cursor = nv_crtc_show_cursor,
2126         .hide_cursor = nv_crtc_hide_cursor,
2127         .load_cursor_argb = nv_crtc_load_cursor_argb,
2128         .gamma_set = nv_crtc_gamma_set,
2129 };
2130
2131
2132 void
2133 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
2134 {
2135         NVPtr pNv = NVPTR(pScrn);
2136         xf86CrtcPtr crtc;
2137         NVCrtcPrivatePtr nv_crtc;
2138
2139         if (pNv->NVArch >= 0x11) {
2140                 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
2141         } else {
2142                 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
2143         }
2144         if (crtc == NULL)
2145                 return;
2146
2147         nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
2148         nv_crtc->crtc = crtc_num;
2149         nv_crtc->head = crtc_num;
2150
2151         crtc->driver_private = nv_crtc;
2152
2153         NVCrtcLockUnlock(crtc, FALSE);
2154 }
2155
2156 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2157 {
2158     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2159     int i;
2160     NVCrtcRegPtr regp;
2161
2162     regp = &state->crtc_reg[nv_crtc->head];
2163
2164     NVWriteMiscOut(crtc, regp->MiscOutReg);
2165
2166     for (i = 1; i < 5; i++)
2167       NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
2168
2169     /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
2170     NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
2171
2172     for (i = 0; i < 25; i++)
2173       NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
2174
2175     for (i = 0; i < 9; i++)
2176       NVWriteVgaGr(crtc, i, regp->Graphics[i]);
2177
2178     NVEnablePalette(crtc);
2179     for (i = 0; i < 21; i++)
2180       NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
2181     NVDisablePalette(crtc);
2182
2183 }
2184
2185 static void nv_crtc_fix_nv40_hw_cursor(xf86CrtcPtr crtc)
2186 {
2187         /* TODO - implement this properly */
2188         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2189         ScrnInfoPtr pScrn = crtc->scrn;
2190         NVPtr pNv = NVPTR(pScrn);
2191
2192         if (pNv->Architecture == NV_ARCH_40) {  /* HW bug */
2193                 volatile CARD32 curpos = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS);
2194                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS, curpos);
2195         }
2196 }
2197 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override)
2198 {
2199     ScrnInfoPtr pScrn = crtc->scrn;
2200     NVPtr pNv = NVPTR(pScrn);
2201     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2202     NVCrtcRegPtr regp;
2203     int i;
2204
2205     regp = &state->crtc_reg[nv_crtc->head];
2206
2207     if(pNv->Architecture >= NV_ARCH_10) {
2208         if(pNv->twoHeads) {
2209            nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL, regp->head);
2210         }
2211         nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
2212         nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
2213         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
2214         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
2215         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2216         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2217         nvWriteMC(pNv, 0x1588, 0);
2218
2219         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
2220         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
2221         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO, regp->gpio);
2222         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0830, regp->unk830);
2223         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0834, regp->unk834);
2224         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0850, regp->unk850);
2225         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_081C, regp->unk81c);
2226
2227         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG, regp->config);
2228
2229         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
2230         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
2231
2232         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
2233         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
2234         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3C, regp->CRTC[NV_VGA_CRTCX_3C]);
2235         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
2236         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_4B, regp->CRTC[NV_VGA_CRTCX_4B]);
2237         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
2238         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_56, regp->CRTC[NV_VGA_CRTCX_56]);
2239         if (override) {
2240                 for (i = 0; i < 0x10; i++)
2241                         NVWriteVGACR5758(pNv, nv_crtc->head, i, regp->CR58[i]);
2242         }
2243         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
2244         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
2245     }
2246
2247     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
2248     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
2249     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
2250     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
2251     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
2252     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
2253     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
2254     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
2255     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
2256     if(pNv->Architecture >= NV_ARCH_30) {
2257       NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
2258     }
2259
2260     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
2261     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
2262     nv_crtc_fix_nv40_hw_cursor(crtc);
2263     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
2264     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
2265
2266     nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_EN_0, 0);
2267     nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
2268
2269     pNv->CurrentState = state;
2270 }
2271
2272 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2273 {
2274     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2275     int i;
2276     NVCrtcRegPtr regp;
2277
2278     regp = &state->crtc_reg[nv_crtc->head];
2279
2280     regp->MiscOutReg = NVReadMiscOut(crtc);
2281
2282     for (i = 0; i < 25; i++)
2283         regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
2284
2285     NVEnablePalette(crtc);
2286     for (i = 0; i < 21; i++)
2287         regp->Attribute[i] = NVReadVgaAttr(crtc, i);
2288     NVDisablePalette(crtc);
2289
2290     for (i = 0; i < 9; i++)
2291         regp->Graphics[i] = NVReadVgaGr(crtc, i);
2292
2293     for (i = 1; i < 5; i++)
2294         regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
2295
2296 }
2297
2298 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2299 {
2300     ScrnInfoPtr pScrn = crtc->scrn;
2301     NVPtr pNv = NVPTR(pScrn);
2302     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2303     NVCrtcRegPtr regp;
2304     int i;
2305
2306     regp = &state->crtc_reg[nv_crtc->head];
2307
2308     regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
2309     regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
2310     regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
2311     regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
2312     regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
2313     regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
2314     regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
2315
2316     regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
2317     regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
2318     if(pNv->Architecture >= NV_ARCH_30) {
2319          regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
2320     }
2321     regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
2322     regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
2323     regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
2324     regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
2325
2326     regp->gpio = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO);
2327     regp->unk830 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0830);
2328     regp->unk834 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0834);
2329     regp->unk850 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0850);
2330     regp->unk81c = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_081C);
2331
2332         regp->config = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG);
2333
2334     if(pNv->Architecture >= NV_ARCH_10) {
2335         if(pNv->twoHeads) {
2336            regp->head     = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL);
2337            regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
2338         }
2339         regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
2340
2341         regp->cursorConfig = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG);
2342
2343         regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
2344         regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
2345         regp->CRTC[NV_VGA_CRTCX_3C] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3C);
2346         regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
2347         regp->CRTC[NV_VGA_CRTCX_4B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_4B);
2348         regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
2349         regp->CRTC[NV_VGA_CRTCX_56] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_56);
2350         for (i = 0; i < 0x10; i++)
2351                 regp->CR58[i] = NVReadVGACR5758(pNv, nv_crtc->head, i);
2352         regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
2353         regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
2354         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
2355         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
2356     }
2357 }
2358
2359 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2360 {
2361         ScrnInfoPtr pScrn = crtc->scrn;
2362         NVPtr pNv = NVPTR(pScrn);
2363         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2364         NVCrtcRegPtr regp;
2365         int i;
2366
2367         regp = &state->crtc_reg[nv_crtc->head];
2368
2369         regp->general = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL);
2370
2371         regp->fp_control        = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL);
2372         regp->debug_0   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0);
2373         regp->debug_1   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1);
2374         regp->debug_2   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2);
2375
2376         regp->unk_a20 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20);
2377         regp->unk_a24 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24);
2378         regp->unk_a34 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34);
2379
2380         if (pNv->NVArch == 0x11) {
2381                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11);
2382         } else if (pNv->twoHeads) {
2383                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER);
2384         }
2385         regp->nv10_cursync = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC);
2386
2387         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2388
2389         for (i = 0; i < 7; i++) {
2390                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2391                 regp->fp_horiz_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2392         }
2393
2394         for (i = 0; i < 7; i++) {
2395                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2396                 regp->fp_vert_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2397         }
2398
2399         regp->fp_hvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START);
2400         regp->fp_hvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END);
2401         regp->fp_vvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START);
2402         regp->fp_vvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END);
2403 }
2404
2405 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2406 {
2407         ScrnInfoPtr pScrn = crtc->scrn;
2408         NVPtr pNv = NVPTR(pScrn);
2409         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2410         NVCrtcRegPtr regp;
2411         int i;
2412
2413         regp = &state->crtc_reg[nv_crtc->head];
2414
2415         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL, regp->general);
2416
2417         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control);
2418         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0, regp->debug_0);
2419         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
2420         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
2421
2422         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20, regp->unk_a20);
2423         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24, regp->unk_a24);
2424         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34, regp->unk_a34);
2425
2426         if (pNv->NVArch == 0x11) {
2427                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11, regp->dither);
2428         } else if (pNv->twoHeads) {
2429                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER, regp->dither);
2430         }
2431         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
2432
2433         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2434
2435         for (i = 0; i < 7; i++) {
2436                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2437                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_horiz_regs[i]);
2438         }
2439
2440         for (i = 0; i < 7; i++) {
2441                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2442                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_vert_regs[i]);
2443         }
2444
2445         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START, regp->fp_hvalid_start);
2446         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END, regp->fp_hvalid_end);
2447         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START, regp->fp_vvalid_start);
2448         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END, regp->fp_vvalid_end);
2449 }
2450
2451 void
2452 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y)
2453 {
2454         ScrnInfoPtr pScrn = crtc->scrn;
2455         NVPtr pNv = NVPTR(pScrn);
2456         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2457         NVFBLayout *pLayout = &pNv->CurrentLayout;
2458         CARD32 start = 0;
2459
2460         ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
2461
2462         start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
2463         start += pNv->FB->offset;
2464
2465         /* 30 bits addresses in 32 bits according to haiku */
2466         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_START, start & 0xfffffffc);
2467
2468         /* set NV4/NV10 byte adress: (bit0 - 1) */
2469         NVWriteVgaAttr(crtc, 0x13, (start & 0x3) << 1);
2470
2471         crtc->x = x;
2472         crtc->y = y;
2473 }
2474
2475 static void NVCrtcWriteDacMask(xf86CrtcPtr crtc, CARD8 value)
2476 {
2477   ScrnInfoPtr pScrn = crtc->scrn;
2478   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2479   NVPtr pNv = NVPTR(pScrn);
2480   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2481
2482   NV_WR08(pDACReg, VGA_DAC_MASK, value);
2483 }
2484
2485 static CARD8 NVCrtcReadDacMask(xf86CrtcPtr crtc)
2486 {
2487   ScrnInfoPtr pScrn = crtc->scrn;
2488   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2489   NVPtr pNv = NVPTR(pScrn);
2490   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2491
2492   return NV_RD08(pDACReg, VGA_DAC_MASK);
2493 }
2494
2495 static void NVCrtcWriteDacReadAddr(xf86CrtcPtr crtc, CARD8 value)
2496 {
2497   ScrnInfoPtr pScrn = crtc->scrn;
2498   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2499   NVPtr pNv = NVPTR(pScrn);
2500   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2501
2502   NV_WR08(pDACReg, VGA_DAC_READ_ADDR, value);
2503 }
2504
2505 static void NVCrtcWriteDacWriteAddr(xf86CrtcPtr crtc, CARD8 value)
2506 {
2507   ScrnInfoPtr pScrn = crtc->scrn;
2508   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2509   NVPtr pNv = NVPTR(pScrn);
2510   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2511
2512   NV_WR08(pDACReg, VGA_DAC_WRITE_ADDR, value);
2513 }
2514
2515 static void NVCrtcWriteDacData(xf86CrtcPtr crtc, CARD8 value)
2516 {
2517   ScrnInfoPtr pScrn = crtc->scrn;
2518   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2519   NVPtr pNv = NVPTR(pScrn);
2520   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2521
2522   NV_WR08(pDACReg, VGA_DAC_DATA, value);
2523 }
2524
2525 static CARD8 NVCrtcReadDacData(xf86CrtcPtr crtc, CARD8 value)
2526 {
2527   ScrnInfoPtr pScrn = crtc->scrn;
2528   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2529   NVPtr pNv = NVPTR(pScrn);
2530   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2531
2532   return NV_RD08(pDACReg, VGA_DAC_DATA);
2533 }
2534
2535 void NVCrtcLoadPalette(xf86CrtcPtr crtc)
2536 {
2537         int i;
2538         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2539         NVCrtcRegPtr regp;
2540         ScrnInfoPtr pScrn = crtc->scrn;
2541         NVPtr pNv = NVPTR(pScrn);
2542
2543         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2544
2545         NVCrtcSetOwner(crtc);
2546         NVCrtcWriteDacMask(crtc, 0xff);
2547         NVCrtcWriteDacWriteAddr(crtc, 0x00);
2548
2549         for (i = 0; i<768; i++) {
2550                 NVCrtcWriteDacData(crtc, regp->DAC[i]);
2551         }
2552         NVDisablePalette(crtc);
2553 }
2554
2555 void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
2556 {
2557         unsigned char scrn;
2558
2559         NVCrtcSetOwner(crtc);
2560
2561         scrn = NVReadVgaSeq(crtc, 0x01);
2562         if (on) {
2563                 scrn &= ~0x20;
2564         } else {
2565                 scrn |= 0x20;
2566         }
2567
2568         NVVgaSeqReset(crtc, TRUE);
2569         NVWriteVgaSeq(crtc, 0x01, scrn);
2570         NVVgaSeqReset(crtc, FALSE);
2571 }
2572
2573 /*************************************************************************** \
2574 |*                                                                           *|
2575 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
2576 |*                                                                           *|
2577 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
2578 |*     international laws.  Users and possessors of this source code are     *|
2579 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
2580 |*     use this code in individual and commercial software.                  *|
2581 |*                                                                           *|
2582 |*     Any use of this source code must include,  in the user documenta-     *|
2583 |*     tion and  internal comments to the code,  notices to the end user     *|
2584 |*     as follows:                                                           *|
2585 |*                                                                           *|
2586 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
2587 |*                                                                           *|
2588 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
2589 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
2590 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
2591 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
2592 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
2593 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
2594 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
2595 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
2596 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
2597 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
2598 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
2599 |*                                                                           *|
2600 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
2601 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
2602 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
2603 |*     computer  software  documentation,"  as such  terms  are  used in     *|
2604 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
2605 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
2606 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
2607 |*     all U.S. Government End Users  acquire the source code  with only     *|
2608 |*     those rights set forth herein.                                        *|
2609 |*                                                                           *|
2610  \***************************************************************************/