git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 2006 Dave Airlie
   3  * Copyright 2007 Maarten Maathuis
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
  26  * decleration is at the bottom of this file as it is rather ugly
  27  */
  28
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include <assert.h>
  34 #include "xf86.h"
  35 #include "os.h"
  36 #include "mibank.h"
  37 #include "globals.h"
  38 #include "xf86.h"
  39 #include "xf86Priv.h"
  40 #include "xf86DDC.h"
  41 #include "mipointer.h"
  42 #include "windowstr.h"
  43 #include <randrstr.h>
  44 #include <X11/extensions/render.h>
  45
  46 #include "xf86Crtc.h"
  47 #include "nv_include.h"
  48
  49 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  50 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override);
  51 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  52 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  53 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  54 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  55 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  56 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  57
  58 uint32_t NVCrtcReadCRTC(xf86CrtcPtr crtc, uint32_t reg)
  59 {
  60         ScrnInfoPtr pScrn = crtc->scrn;
  61         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  62         NVPtr pNv = NVPTR(pScrn);
  63
  64         return NVReadCRTC(pNv, nv_crtc->head, reg);
  65 }
  66
  67 void NVCrtcWriteCRTC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
  68 {
  69         ScrnInfoPtr pScrn = crtc->scrn;
  70         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  71         NVPtr pNv = NVPTR(pScrn);
  72
  73         NVWriteCRTC(pNv, nv_crtc->head, reg, val);
  74 }
  75
  76 uint32_t NVCrtcReadRAMDAC(xf86CrtcPtr crtc, uint32_t reg)
  77 {
  78         ScrnInfoPtr pScrn = crtc->scrn;
  79         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  80         NVPtr pNv = NVPTR(pScrn);
  81
  82         return NVReadRAMDAC(pNv, nv_crtc->head, reg);
  83 }
  84
  85 void NVCrtcWriteRAMDAC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
  86 {
  87         ScrnInfoPtr pScrn = crtc->scrn;
  88         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  89         NVPtr pNv = NVPTR(pScrn);
  90
  91         NVWriteRAMDAC(pNv, nv_crtc->head, reg, val);
  92 }
  93
  94 void NVWriteVgaCrtc(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
  95 {
  96         ScrnInfoPtr pScrn = crtc->scrn;
  97         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  98         NVPtr pNv = NVPTR(pScrn);
  99
 100         NVWriteVGA(pNv, nv_crtc->head, index, value);
 101 }
 102
 103 uint8_t NVReadVgaCrtc(xf86CrtcPtr crtc, uint8_t index)
 104 {
 105         ScrnInfoPtr pScrn = crtc->scrn;
 106         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 107         NVPtr pNv = NVPTR(pScrn);
 108
 109         return NVReadVGA(pNv, nv_crtc->head, index);
 110 }
 111
 112 static void NVCrtcSetOwner(xf86CrtcPtr crtc)
 113 {
 114         ScrnInfoPtr pScrn = crtc->scrn;
 115         NVPtr pNv = NVPTR(pScrn);
 116         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 117
 118         NVSetOwner(pNv, nv_crtc->head);
 119 }
 120
 121 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool lock)
 122 {
 123         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 124         ScrnInfoPtr pScrn = crtc->scrn;
 125         NVPtr pNv = NVPTR(pScrn);
 126
 127         NVLockUnlockHead(pNv, nv_crtc->head, lock);
 128 }
 129
 130 xf86OutputPtr
 131 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
 132 {
 133         ScrnInfoPtr pScrn = crtc->scrn;
 134         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 135         int i;
 136         for (i = 0; i < xf86_config->num_output; i++) {
 137                 xf86OutputPtr output = xf86_config->output[i];
 138
 139                 if (output->crtc == crtc) {
 140                         return output;
 141                 }
 142         }
 143
 144         return NULL;
 145 }
 146
 147 xf86CrtcPtr
 148 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
 149 {
 150         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 151         int i;
 152
 153         for (i = 0; i < xf86_config->num_crtc; i++) {
 154                 xf86CrtcPtr crtc = xf86_config->crtc[i];
 155                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 156                 if (nv_crtc->head == index)
 157                         return crtc;
 158         }
 159
 160         return NULL;
 161 }
 162
 163 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
 164 /* They are only valid for NV4x, appearantly reordered for NV5x */
 165 /* gpu pll: 0x4000 + 0x4004
 166  * unknown pll: 0x4008 + 0x400c
 167  * vpll1: 0x4010 + 0x4014
 168  * vpll2: 0x4018 + 0x401c
 169  * unknown pll: 0x4020 + 0x4024
 170  * unknown pll: 0x4038 + 0x403c
 171  * Some of the unknown's are probably memory pll's.
 172  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
 173  * 1 and 2 refer to the registers of each pair. There is only one post divider.
 174  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
 175  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
 176  *     bit8: A switch that turns of the second divider and multiplier off.
 177  *     bit12: Also a switch, i haven't seen it yet.
 178  *     bit16-19: p-divider
 179  *     but 28-31: Something related to the mode that is used (see bit8).
 180  * 2) bit0-7: m-divider (a)
 181  *     bit8-15: n-multiplier (a)
 182  *     bit16-23: m-divider (b)
 183  *     bit24-31: n-multiplier (b)
 184  */
 185
 186 /* Modifying the gpu pll for example requires:
 187  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 188  * This is not needed for the vpll's which have their own bits.
 189  */
 190
 191 static void nv40_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 192 {
 193         state->vpll1_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL);
 194         state->vpll1_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B);
 195         state->vpll2_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2);
 196         state->vpll2_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B);
 197         state->pllsel = NVReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT);
 198         state->sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
 199         state->reg580 = NVReadRAMDAC(pNv, 0, NV_RAMDAC_580);
 200         state->reg594 = NVReadRAMDAC(pNv, 0, NV_RAMDAC_594);
 201 }
 202
 203 static void nv40_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 204 {
 205         ScrnInfoPtr pScrn = crtc->scrn;
 206         NVPtr pNv = NVPTR(pScrn);
 207         uint32_t fp_debug_0[2];
 208         uint32_t index[2];
 209         fp_debug_0[0] = NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
 210         fp_debug_0[1] = NVReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
 211
 212         /* The TMDS_PLL switch is on the actual ramdac */
 213         if (state->crosswired) {
 214                 index[0] = 1;
 215                 index[1] = 0;
 216                 ErrorF("Crosswired pll state load\n");
 217         } else {
 218                 index[0] = 0;
 219                 index[1] = 1;
 220         }
 221
 222         if (state->vpll2_b && state->vpll_changed[1]) {
 223                 NVWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0,
 224                         fp_debug_0[index[1]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 225
 226                 /* Wait for the situation to stabilise */
 227                 usleep(5000);
 228
 229                 /* for vpll2 change bits 18 and 19 are disabled */
 230                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040 & ~(3 << 18));
 231
 232                 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 233                 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 234
 235                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2, state->vpll2_a);
 236                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 237
 238                 ErrorF("writing pllsel %08X\n", state->pllsel);
 239                 /* Don't turn vpll1 off. */
 240                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
 241
 242                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_580, state->reg580);
 243                 ErrorF("writing reg580 %08X\n", state->reg580);
 244
 245                 /* We need to wait a while */
 246                 usleep(5000);
 247                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 248
 249                 NVWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[1]]);
 250
 251                 /* Wait for the situation to stabilise */
 252                 usleep(5000);
 253         }
 254
 255         if (state->vpll1_b && state->vpll_changed[0]) {
 256                 NVWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0,
 257                         fp_debug_0[index[0]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 258
 259                 /* Wait for the situation to stabilise */
 260                 usleep(5000);
 261
 262                 /* for vpll1 change bits 16 and 17 are disabled */
 263                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040 & ~(3 << 16));
 264
 265                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 266                 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 267
 268                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL, state->vpll1_a);
 269                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B, state->vpll1_b);
 270
 271                 ErrorF("writing pllsel %08X\n", state->pllsel);
 272                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
 273
 274                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_580, state->reg580);
 275                 ErrorF("writing reg580 %08X\n", state->reg580);
 276
 277                 /* We need to wait a while */
 278                 usleep(5000);
 279                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 280
 281                 NVWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[0]]);
 282
 283                 /* Wait for the situation to stabilise */
 284                 usleep(5000);
 285         }
 286
 287         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 288         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, state->sel_clk);
 289
 290         ErrorF("writing reg594 %08X\n", state->reg594);
 291         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_594, state->reg594);
 292
 293         /* All clocks have been set at this point. */
 294         state->vpll_changed[0] = FALSE;
 295         state->vpll_changed[1] = FALSE;
 296 }
 297
 298 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 299 {
 300         state->vpll1_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL);
 301         if (pNv->twoHeads) {
 302                 state->vpll2_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2);
 303         }
 304         if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 305                 state->vpll1_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B);
 306                 state->vpll2_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B);
 307         }
 308         state->pllsel = NVReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT);
 309         state->sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
 310 }
 311
 312
 313 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 314 {
 315         /* This sequence is important, the NV28 is very sensitive in this area. */
 316         /* Keep pllsel last and sel_clk first. */
 317         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 318         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, state->sel_clk);
 319
 320         if (state->vpll2_a && state->vpll_changed[1]) {
 321                 if (pNv->twoHeads) {
 322                         ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 323                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2, state->vpll2_a);
 324                 }
 325                 if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 326                         ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 327                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 328                 }
 329         }
 330
 331         if (state->vpll1_a && state->vpll_changed[0]) {
 332                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 333                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL, state->vpll1_a);
 334                 if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 335                         ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 336                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B, state->vpll1_b);
 337                 }
 338         }
 339
 340         ErrorF("writing pllsel %08X\n", state->pllsel);
 341         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
 342
 343         /* All clocks have been set at this point. */
 344         state->vpll_changed[0] = FALSE;
 345         state->vpll_changed[1] = FALSE;
 346 }
 347
 348 static void nv_crtc_mode_set_sel_clk(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 349 {
 350         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 351         NVPtr pNv = NVPTR(crtc->scrn);
 352         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 353         NVOutputPrivatePtr nv_output;
 354         int i;
 355
 356         /* Don't change SEL_CLK on NV0x/NV1x/NV2x cards */
 357         if (pNv->Architecture < NV_ARCH_30) {
 358                 state->sel_clk = pNv->misc_info.sel_clk;
 359                 return;
 360         }
 361
 362         /* SEL_CLK is only used on the primary ramdac */
 363         /* This seems to be needed to select the proper clocks, otherwise bad things happen */
 364         if (!state->sel_clk)
 365                 state->sel_clk = pNv->misc_info.sel_clk & ~(0xf << 16);
 366
 367         if (!output)
 368                 return;
 369         nv_output = output->driver_private;
 370
 371         /* Only let digital outputs mess further with SEL_CLK, otherwise strange output routings may mess it up. */
 372         if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS) {
 373                 Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
 374
 375                 state->sel_clk &= ~(0xf << 16);
 376                 /* Even with two dvi, this should not conflict. */
 377                 if (crossed_clocks)
 378                         state->sel_clk |= (0x1 << 16);
 379                 else
 380                         state->sel_clk |= (0x4 << 16);
 381
 382                 /* nv30:
 383                  *      bit 0           NVClk spread spectrum on/off
 384                  *      bit 2           MemClk spread spectrum on/off
 385                  *      bit 4           PixClk1 spread spectrum on/off
 386                  *      bit 6           PixClk2 spread spectrum on/off
 387                  *
 388                  * nv40 (observations from bios behaviour and mmio traces):
 389                  *      bit 4           seems to get set when output is on head A - likely related to PixClk1
 390                  *      bit 6           seems to get set when output is on head B - likely related to PixClk2
 391                  *      bits 5&7        set as for bits 4&6, but do not appear on cards using 4&6
 392                  *
 393                  *      bits 8&10       seen on dual dvi outputs; possibly means "bits 4&6, dual dvi"
 394                  *
 395                  *      Note that the circumstances for setting the bits at all is unclear
 396                  */
 397                 if (pNv->Architecture == NV_ARCH_40) {
 398                         for (i = 1; i <= 2; i++) {
 399                                 uint32_t var = (state->sel_clk >> 4*i) & 0xf;
 400                                 int shift = 0; /* assume (var & 0x5) by default */
 401
 402                                 if (!var)
 403                                         continue;
 404                                 if (var & 0xa)
 405                                         shift = 1;
 406
 407                                 state->sel_clk &= ~(0xf << 4*i);
 408                                 if (crossed_clocks)
 409                                         state->sel_clk |= (0x4 << (4*i + shift));
 410                                 else
 411                                         state->sel_clk |= (0x1 << (4*i + shift));
 412                         }
 413                 }
 414         }
 415 }
 416
 417 /*
 418  * Calculate extended mode parameters (SVGA) and save in a
 419  * mode state structure.
 420  * State is not specific to a single crtc, but shared.
 421  */
 422 void nv_crtc_calc_state_ext(
 423         xf86CrtcPtr             crtc,
 424         DisplayModePtr  mode,
 425         int                             bpp,
 426         int                             DisplayWidth, /* Does this change after setting the mode? */
 427         int                             CrtcHDisplay,
 428         int                             CrtcVDisplay,
 429         int                             dotClock,
 430         int                             flags
 431 )
 432 {
 433         ScrnInfoPtr pScrn = crtc->scrn;
 434         NVPtr pNv = NVPTR(pScrn);
 435         uint32_t pixelDepth, VClk = 0;
 436         uint32_t CursorStart;
 437         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 438         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 439         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 440         RIVA_HW_STATE *state = &pNv->ModeReg;
 441         int num_crtc_enabled, i;
 442         uint32_t old_clock_a = 0, old_clock_b = 0;
 443         struct pll_lims pll_lim;
 444         int NM1 = 0xbeef, NM2 = 0xdead, log2P = 0;
 445         uint32_t g70_pll_special_bits = 0;
 446         Bool nv4x_single_stage_pll_mode = FALSE;
 447         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 448         NVOutputPrivatePtr nv_output = NULL;
 449         if (output)
 450                 nv_output = output->driver_private;
 451
 452         /* Store old clock. */
 453         if (nv_crtc->head == 1) {
 454                 old_clock_a = state->vpll2_a;
 455                 old_clock_b = state->vpll2_b;
 456         } else {
 457                 old_clock_a = state->vpll1_a;
 458                 old_clock_b = state->vpll1_b;
 459         }
 460
 461         /*
 462          * Extended RIVA registers.
 463          */
 464         /* This is pitch related, not mode related. */
 465         pixelDepth = (bpp + 1)/8;
 466
 467         if (nv_crtc->head == 0) {
 468                 if (!get_pll_limits(pScrn, VPLL1, &pll_lim))
 469                         return;
 470         } else
 471                 if (!get_pll_limits(pScrn, VPLL2, &pll_lim))
 472                         return;
 473
 474         if (pNv->twoStagePLL) {
 475                 if (dotClock < pll_lim.vco1.maxfreq && pNv->NVArch > 0x40) { /* use a single VCO */
 476                         nv4x_single_stage_pll_mode = TRUE;
 477                         /* Turn the second set of divider and multiplier off */
 478                         /* Bogus data, the same nvidia uses */
 479                         NM2 = 0x11f;
 480                         VClk = getMNP_single(pScrn, &pll_lim, dotClock, &NM1, &log2P);
 481                 } else
 482                         VClk = getMNP_double(pScrn, &pll_lim, dotClock, &NM1, &NM2, &log2P);
 483         } else
 484                 VClk = getMNP_single(pScrn, &pll_lim, dotClock, &NM1, &log2P);
 485
 486         /* Are these all the (relevant) G70 cards? */
 487         if (pNv->NVArch == 0x4B || pNv->NVArch == 0x46 || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
 488                 /* This is a big guess, but should be reasonable until we can narrow it down. */
 489                 /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
 490                 if (nv4x_single_stage_pll_mode)
 491                         g70_pll_special_bits = 0x1;
 492                 else
 493                         g70_pll_special_bits = 0x3;
 494         }
 495
 496         if (pNv->NVArch == 0x30)
 497                 /* See nvregisters.xml for details. */
 498                 state->pll = log2P << 16 | NM1 | (NM2 & 7) << 4 | ((NM2 >> 8) & 7) << 19 | ((NM2 >> 11) & 3) << 24 | NV30_RAMDAC_ENABLE_VCO2;
 499         else
 500                 state->pll = g70_pll_special_bits << 30 | log2P << 16 | NM1;
 501         state->pllB = NV31_RAMDAC_ENABLE_VCO2 | NM2;
 502
 503         /* Does register 0x580 already have a value? */
 504         if (!state->reg580)
 505                 state->reg580 = pNv->misc_info.ramdac_0_reg_580;
 506         if (nv4x_single_stage_pll_mode) {
 507                 if (nv_crtc->head == 0)
 508                         state->reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 509                 else
 510                         state->reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 511         } else {
 512                 if (nv_crtc->head == 0)
 513                         state->reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
 514                 else
 515                         state->reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
 516         }
 517
 518         if (!pNv->twoStagePLL || nv4x_single_stage_pll_mode)
 519                 ErrorF("vpll: n %d m %d log2p %d\n", NM1 >> 8, NM1 & 0xff, log2P);
 520         else
 521                 ErrorF("vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", NM1 >> 8, NM2 >> 8, NM1 & 0xff, NM2 & 0xff, log2P);
 522
 523         if (nv_crtc->head == 1) {
 524                 state->vpll2_a = state->pll;
 525                 state->vpll2_b = state->pllB;
 526         } else {
 527                 state->vpll1_a = state->pll;
 528                 state->vpll1_b = state->pllB;
 529         }
 530
 531         /* always reset vpll, just to be sure. */
 532         state->vpll_changed[nv_crtc->head] = TRUE;
 533
 534         switch (pNv->Architecture) {
 535         case NV_ARCH_04:
 536                 nv4UpdateArbitrationSettings(VClk,
 537                                                 pixelDepth * 8,
 538                                                 &(state->arbitration0),
 539                                                 &(state->arbitration1),
 540                                                 pNv);
 541                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
 542                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
 543                 if (flags & V_DBLSCAN)
 544                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 545                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
 546                 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
 547                 state->config = 0x00001114;
 548                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 549                 break;
 550         case NV_ARCH_10:
 551         case NV_ARCH_20:
 552         case NV_ARCH_30:
 553         default:
 554                 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
 555                         ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
 556                         state->arbitration0 = 128;
 557                         state->arbitration1 = 0x0480;
 558                 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
 559                         ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
 560                         nForceUpdateArbitrationSettings(VClk,
 561                                                 pixelDepth * 8,
 562                                                 &(state->arbitration0),
 563                                                 &(state->arbitration1),
 564                                                 pNv);
 565                 } else if (pNv->Architecture < NV_ARCH_30) {
 566                         nv10UpdateArbitrationSettings(VClk,
 567                                                 pixelDepth * 8,
 568                                                 &(state->arbitration0),
 569                                                 &(state->arbitration1),
 570                                                 pNv);
 571                 } else {
 572                         nv30UpdateArbitrationSettings(pNv,
 573                                                 &(state->arbitration0),
 574                                                 &(state->arbitration1));
 575                 }
 576
 577                 if (nv_crtc->head == 1) {
 578                         CursorStart = pNv->Cursor2->offset;
 579                 } else {
 580                         CursorStart = pNv->Cursor->offset;
 581                 }
 582
 583                 if (!NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 584                         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
 585                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
 586                         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
 587                 } else {
 588                         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x0;
 589                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0x0;
 590                         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x0;
 591                 }
 592
 593                 if (flags & V_DBLSCAN)
 594                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 595
 596                 state->config   = nvReadFB(pNv, NV_PFB_CFG0);
 597                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 598                 break;
 599         }
 600
 601         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 602                 /* This is a bit of a guess. */
 603                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] |= 0xB8;
 604         }
 605
 606         /* okay do we have 2 CRTCs running ? */
 607         num_crtc_enabled = 0;
 608         for (i = 0; i < xf86_config->num_crtc; i++) {
 609                 if (xf86_config->crtc[i]->enabled) {
 610                         num_crtc_enabled++;
 611                 }
 612         }
 613
 614         ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
 615
 616         /* Are we crosswired? */
 617         if (output && nv_crtc->head != nv_output->preferred_output) {
 618                 state->crosswired = TRUE;
 619         } else
 620                 state->crosswired = FALSE;
 621
 622         /* The NV40 seems to have more similarities to NV3x than other cards. */
 623         if (pNv->NVArch < 0x41) {
 624                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL;
 625                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL;
 626         }
 627
 628         if (nv_crtc->head == 1) {
 629                 if (!nv4x_single_stage_pll_mode) {
 630                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 631                 } else {
 632                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 633                 }
 634                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
 635         } else {
 636                 if (!nv4x_single_stage_pll_mode) {
 637                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 638                 } else {
 639                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 640                 }
 641                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
 642         }
 643
 644         /* The blob uses this always, so let's do the same */
 645         if (pNv->Architecture == NV_ARCH_40) {
 646                 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
 647         }
 648
 649         /* The primary output resource doesn't seem to care */
 650         if (output && pNv->Architecture == NV_ARCH_40 && nv_output->output_resource == 1) { /* This is the "output" */
 651                 /* non-zero values are for analog, don't know about tv-out and the likes */
 652                 if (output && nv_output->type != OUTPUT_ANALOG) {
 653                         state->reg594 = 0x0;
 654                 } else if (output) {
 655                         /* Are we a flexible output? */
 656                         if (ffs(pNv->dcb_table.entry[nv_output->dcb_entry].or) & OUTPUT_0)
 657                                 state->reg594 = 0x1;
 658                         else
 659                                 state->reg594 = 0x0;
 660
 661                         /* More values exist, but they seem related to the 3rd dac (tv-out?) somehow */
 662                         /* bit 16-19 are bits that are set on some G70 cards */
 663                         /* Those bits are also set to the 3rd OUTPUT register */
 664                         if (nv_crtc->head == 1) {
 665                                 state->reg594 |= 0x100;
 666                         }
 667                 }
 668         }
 669
 670         regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
 671         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
 672         if (pNv->Architecture >= NV_ARCH_30) {
 673                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
 674         }
 675
 676         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 677                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = ((CrtcHDisplay/16) & 0x700) >> 3;
 678         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 679                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((CrtcHDisplay*bpp)/64) & 0x700) >> 3;
 680         } else { /* framebuffer can be larger than crtc scanout area. */
 681                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
 682         }
 683         regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
 684 }
 685
 686 static void
 687 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
 688 {
 689         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 690         ScrnInfoPtr pScrn = crtc->scrn;
 691         NVPtr pNv = NVPTR(pScrn);
 692         unsigned char seq1 = 0, crtc17 = 0;
 693         unsigned char crtc1A;
 694
 695         ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->head, mode);
 696
 697         if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */
 698                 return;
 699
 700         nv_crtc->last_dpms = mode;
 701
 702         if (pNv->twoHeads)
 703                 NVCrtcSetOwner(crtc);
 704
 705         crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
 706         switch(mode) {
 707                 case DPMSModeStandby:
 708                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
 709                 seq1 = 0x20;
 710                 crtc17 = 0x80;
 711                 crtc1A |= 0x80;
 712                 break;
 713         case DPMSModeSuspend:
 714                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
 715                 seq1 = 0x20;
 716                 crtc17 = 0x80;
 717                 crtc1A |= 0x40;
 718                 break;
 719         case DPMSModeOff:
 720                 /* Screen: Off; HSync: Off, VSync: Off */
 721                 seq1 = 0x20;
 722                 crtc17 = 0x00;
 723                 crtc1A |= 0xC0;
 724                 break;
 725         case DPMSModeOn:
 726         default:
 727                 /* Screen: On; HSync: On, VSync: On */
 728                 seq1 = 0x00;
 729                 crtc17 = 0x80;
 730                 break;
 731         }
 732
 733         NVVgaSeqReset(pNv, nv_crtc->head, true);
 734         /* Each head has it's own sequencer, so we can turn it off when we want */
 735         seq1 |= (NVReadVgaSeq(pNv, nv_crtc->head, 0x01) & ~0x20);
 736         NVWriteVgaSeq(pNv, nv_crtc->head, 0x1, seq1);
 737         crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
 738         usleep(10000);
 739         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
 740         NVVgaSeqReset(pNv, nv_crtc->head, false);
 741
 742         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
 743 }
 744
 745 static Bool
 746 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
 747                      DisplayModePtr adjusted_mode)
 748 {
 749         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 750         ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->head);
 751
 752         return TRUE;
 753 }
 754
 755 static void
 756 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
 757 {
 758         ScrnInfoPtr pScrn = crtc->scrn;
 759         NVPtr pNv = NVPTR(pScrn);
 760         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 761         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 762         NVFBLayout *pLayout = &pNv->CurrentLayout;
 763         int depth = pScrn->depth;
 764
 765         /* Calculate our timings */
 766         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
 767         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
 768         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
 769         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
 770         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
 771         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
 772         int vertDisplay         = mode->CrtcVDisplay                    - 1;
 773         int vertStart           = mode->CrtcVSyncStart          - 1;
 774         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
 775         int vertTotal           = mode->CrtcVTotal                      - 2;
 776         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
 777         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
 778
 779         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 780         NVOutputPrivatePtr nv_output = NULL;
 781         if (output)
 782                 nv_output = output->driver_private;
 783
 784         /* This is pitch/memory size related. */
 785         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE))
 786                 depth = pNv->console_mode[nv_crtc->head].bpp;
 787
 788         ErrorF("Mode clock: %d\n", mode->Clock);
 789         ErrorF("Adjusted mode clock: %d\n", adjusted_mode->Clock);
 790
 791         /* Reverted to what nv did, because that works for all resolutions on flatpanels */
 792         if (output && (nv_output->type == OUTPUT_LVDS || nv_output->type == OUTPUT_TMDS)) {
 793                 vertStart = vertTotal - 3;
 794                 vertEnd = vertTotal - 2;
 795                 vertBlankStart = vertStart;
 796                 horizStart = horizTotal - 5;
 797                 horizEnd = horizTotal - 2;
 798                 horizBlankEnd = horizTotal + 4;
 799                 if (pNv->overlayAdaptor && pNv->Architecture >= NV_ARCH_10) {
 800                         /* This reportedly works around Xv some overlay bandwidth problems*/
 801                         horizTotal += 2;
 802                 }
 803         }
 804
 805         if (mode->Flags & V_INTERLACE)
 806                 vertTotal |= 1;
 807
 808         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
 809         ErrorF("horizStart: 0x%X \n", horizStart);
 810         ErrorF("horizEnd: 0x%X \n", horizEnd);
 811         ErrorF("horizTotal: 0x%X \n", horizTotal);
 812         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
 813         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
 814         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
 815         ErrorF("vertStart: 0x%X \n", vertStart);
 816         ErrorF("vertEnd: 0x%X \n", vertEnd);
 817         ErrorF("vertTotal: 0x%X \n", vertTotal);
 818         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
 819         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
 820
 821         /*
 822         * compute correct Hsync & Vsync polarity
 823         */
 824         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
 825                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
 826
 827                 regp->MiscOutReg = 0x23;
 828                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
 829                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
 830         } else {
 831                 int VDisplay = mode->VDisplay;
 832                 if (mode->Flags & V_DBLSCAN)
 833                         VDisplay *= 2;
 834                 if (mode->VScan > 1)
 835                         VDisplay *= mode->VScan;
 836                 if (VDisplay < 400) {
 837                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
 838                 } else if (VDisplay < 480) {
 839                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
 840                 } else if (VDisplay < 768) {
 841                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
 842                 } else {
 843                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
 844                 }
 845         }
 846
 847         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
 848
 849         /*
 850         * Time Sequencer
 851         */
 852         regp->Sequencer[0] = 0x00;
 853         /* 0x20 disables the sequencer */
 854         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 855                 if (mode->HDisplay == 720) {
 856                         regp->Sequencer[1] = 0x21; /* enable 9/8 mode */
 857                 } else {
 858                         regp->Sequencer[1] = 0x20;
 859                 }
 860         } else {
 861                 if (mode->Flags & V_CLKDIV2) {
 862                         regp->Sequencer[1] = 0x29;
 863                 } else {
 864                         regp->Sequencer[1] = 0x21;
 865                 }
 866         }
 867         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 868                 regp->Sequencer[2] = 0x03; /* select 2 out of 4 planes */
 869         } else {
 870                 regp->Sequencer[2] = 0x0F;
 871         }
 872         regp->Sequencer[3] = 0x00;                     /* Font select */
 873         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 874                 regp->Sequencer[4] = 0x02;
 875         } else {
 876                 regp->Sequencer[4] = 0x0E;                             /* Misc */
 877         }
 878
 879         /*
 880         * CRTC Controller
 881         */
 882         regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
 883         regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
 884         regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
 885         regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0)
 886                                 | SetBit(7);
 887         regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
 888         regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
 889                                 | SetBitField(horizEnd,4:0,4:0);
 890         regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
 891         regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
 892                                 | SetBitField(vertDisplay,8:8,1:1)
 893                                 | SetBitField(vertStart,8:8,2:2)
 894                                 | SetBitField(vertBlankStart,8:8,3:3)
 895                                 | SetBit(4)
 896                                 | SetBitField(vertTotal,9:9,5:5)
 897                                 | SetBitField(vertDisplay,9:9,6:6)
 898                                 | SetBitField(vertStart,9:9,7:7);
 899         regp->CRTC[NV_VGA_CRTCX_PRROWSCN]  = 0x00;
 900         regp->CRTC[NV_VGA_CRTCX_MAXSCLIN]  = SetBitField(vertBlankStart,9:9,5:5)
 901                                 | SetBit(6)
 902                                 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00)
 903                                 | (NVMatchModePrivate(mode, NV_MODE_VGA) ? 0xF : 0x00); /* 8x15 chars */
 904         if (NVMatchModePrivate(mode, NV_MODE_VGA)) { /* Were do these cursor offsets come from? */
 905                 regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0xD; /* start scanline */
 906                 regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0xE; /* end scanline */
 907         } else {
 908                 regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0x00;
 909                 regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0x00;
 910         }
 911         regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00;
 912         regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
 913         regp->CRTC[0xe] = 0x00;
 914         regp->CRTC[0xf] = 0x00;
 915         regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
 916         /* What is the meaning of bit5, it is empty in the vga spec. */
 917         regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) |
 918                                                                         (NVMatchModePrivate(mode, NV_MODE_VGA) ? 0 : SetBit(5));
 919         regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
 920         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 921                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = (mode->CrtcHDisplay/16);
 922         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 923                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((mode->CrtcHDisplay*depth)/64);
 924         } else { /* framebuffer can be larger than crtc scanout area. */
 925                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
 926         }
 927         if (depth == 4) { /* How can these values be calculated? */
 928                 regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x1F;
 929         } else {
 930                 regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x00;
 931         }
 932         regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
 933         regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
 934         /* 0x80 enables the sequencer, we don't want that */
 935         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 936                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xA3 & ~0x80;
 937         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 938                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xE3 & ~0x80;
 939         } else {
 940                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80;
 941         }
 942         regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
 943
 944         /*
 945          * Some extended CRTC registers (they are not saved with the rest of the vga regs).
 946          */
 947
 948         regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
 949                                 | SetBitField(vertBlankStart,10:10,3:3)
 950                                 | SetBitField(vertStart,10:10,2:2)
 951                                 | SetBitField(vertDisplay,10:10,1:1)
 952                                 | SetBitField(vertTotal,10:10,0:0);
 953
 954         regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
 955                                 | SetBitField(horizDisplay,8:8,1:1)
 956                                 | SetBitField(horizBlankStart,8:8,2:2)
 957                                 | SetBitField(horizStart,8:8,3:3);
 958
 959         regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
 960                                 | SetBitField(vertDisplay,11:11,2:2)
 961                                 | SetBitField(vertStart,11:11,4:4)
 962                                 | SetBitField(vertBlankStart,11:11,6:6);
 963
 964         if(mode->Flags & V_INTERLACE) {
 965                 horizTotal = (horizTotal >> 1) & ~1;
 966                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
 967                 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
 968         } else {
 969                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff;  /* interlace off */
 970         }
 971
 972         /*
 973         * Graphics Display Controller
 974         */
 975         regp->Graphics[0] = 0x00;
 976         regp->Graphics[1] = 0x00;
 977         regp->Graphics[2] = 0x00;
 978         regp->Graphics[3] = 0x00;
 979         regp->Graphics[4] = 0x00;
 980         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
 981                 regp->Graphics[5] = 0x10;
 982                 regp->Graphics[6] = 0x0E; /* map 32k mem */
 983                 regp->Graphics[7] = 0x00;
 984         } else {
 985                 regp->Graphics[5] = 0x40; /* 256 color mode */
 986                 regp->Graphics[6] = 0x05; /* map 64k mem + graphic mode */
 987                 regp->Graphics[7] = 0x0F;
 988         }
 989         regp->Graphics[8] = 0xFF;
 990
 991         regp->Attribute[0]  = 0x00; /* standard colormap translation */
 992         regp->Attribute[1]  = 0x01;
 993         regp->Attribute[2]  = 0x02;
 994         regp->Attribute[3]  = 0x03;
 995         regp->Attribute[4]  = 0x04;
 996         regp->Attribute[5]  = 0x05;
 997         regp->Attribute[6]  = 0x06;
 998         regp->Attribute[7]  = 0x07;
 999         regp->Attribute[8]  = 0x08;
1000         regp->Attribute[9]  = 0x09;
1001         regp->Attribute[10] = 0x0A;
1002         regp->Attribute[11] = 0x0B;
1003         regp->Attribute[12] = 0x0C;
1004         regp->Attribute[13] = 0x0D;
1005         regp->Attribute[14] = 0x0E;
1006         regp->Attribute[15] = 0x0F;
1007         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1008                 regp->Attribute[16] = 0x0C; /* Line Graphics Enable + Blink enable */
1009         } else {
1010                 regp->Attribute[16] = 0x01; /* Enable graphic mode */
1011         }
1012         /* Non-vga */
1013         regp->Attribute[17] = 0x00;
1014         regp->Attribute[18] = 0x0F; /* enable all color planes */
1015         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1016                 regp->Attribute[19] = 0x08; /* shift bits by 8 */
1017         } else {
1018                 regp->Attribute[19] = 0x00;
1019         }
1020         regp->Attribute[20] = 0x00;
1021 }
1022
1023 /**
1024  * Sets up registers for the given mode/adjusted_mode pair.
1025  *
1026  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1027  *
1028  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1029  * be easily turned on/off after this.
1030  */
1031 static void
1032 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1033 {
1034         ScrnInfoPtr pScrn = crtc->scrn;
1035         NVPtr pNv = NVPTR(pScrn);
1036         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1037         NVFBLayout *pLayout = &pNv->CurrentLayout;
1038         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1039         NVCrtcRegPtr savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1040         uint32_t i, depth;
1041         Bool is_fp = FALSE;
1042         Bool is_lvds = FALSE;
1043         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1044         NVOutputPrivatePtr nv_output = NULL;
1045         if (output) {
1046                 nv_output = output->driver_private;
1047
1048                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1049                         is_fp = TRUE;
1050
1051                 if (nv_output->type == OUTPUT_LVDS)
1052                         is_lvds = TRUE;
1053         }
1054
1055         /* Registers not directly related to the (s)vga mode */
1056
1057         /* bit2 = 0 -> fine pitched crtc granularity */
1058         /* The rest disables double buffering on CRTC access */
1059         regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
1060
1061         if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
1062                 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1063                 if (nv_crtc->head == 0) {
1064                         regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1065                 }
1066
1067                 if (is_fp) {
1068                         regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0);
1069                         if (!NVMatchModePrivate(mode, NV_MODE_VGA)) {
1070                                 regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 1);
1071                         }
1072                 }
1073         } else {
1074                 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
1075                 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
1076         }
1077
1078         /* Sometimes 0x10 is used, what is this? */
1079         regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1080         /* Some kind of tmds switch for older cards */
1081         if (pNv->Architecture < NV_ARCH_40) {
1082                 regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
1083         }
1084
1085         /*
1086         * Initialize DAC palette.
1087         * Will only be written when depth != 8.
1088         */
1089         for (i = 0; i < 256; i++) {
1090                 regp->DAC[i*3] = i;
1091                 regp->DAC[(i*3)+1] = i;
1092                 regp->DAC[(i*3)+2] = i;
1093         }
1094
1095         /*
1096         * Calculate the extended registers.
1097         */
1098
1099         if (pLayout->depth < 24) {
1100                 depth = pLayout->depth;
1101         } else {
1102                 depth = 32;
1103         }
1104
1105         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1106                 /* bpp is pitch related. */
1107                 depth = pNv->console_mode[nv_crtc->head].bpp;
1108         }
1109
1110         /* What is the meaning of this register? */
1111         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1112         regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
1113
1114         regp->head = 0;
1115
1116         /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1117         /* But what are those special conditions? */
1118         if (pNv->Architecture <= NV_ARCH_30) {
1119                 if (is_fp) {
1120                         if(nv_crtc->head == 1) {
1121                                 regp->head |= NV_CRTC_FSEL_FPP1;
1122                         } else if (pNv->twoHeads) {
1123                                 regp->head |= NV_CRTC_FSEL_FPP2;
1124                         }
1125                 }
1126         } else {
1127                 /* Most G70 cards have FPP2 set on the secondary CRTC. */
1128                 if (nv_crtc->head == 1 && pNv->NVArch > 0x44) {
1129                         regp->head |= NV_CRTC_FSEL_FPP2;
1130                 }
1131         }
1132
1133         /* Except for rare conditions I2C is enabled on the primary crtc */
1134         if (nv_crtc->head == 0) {
1135                 regp->head |= NV_CRTC_FSEL_I2C;
1136         }
1137
1138         /* Set overlay to desired crtc. */
1139         if (pNv->overlayAdaptor) {
1140                 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(pNv);
1141                 if (pPriv->overlayCRTC == nv_crtc->head)
1142                         regp->head |= NV_CRTC_FSEL_OVERLAY;
1143         }
1144
1145         /* This is not what nv does, but it is what the blob does (for nv4x at least) */
1146         /* This fixes my cursor corruption issue */
1147         regp->cursorConfig = 0x0;
1148         if(mode->Flags & V_DBLSCAN)
1149                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_DOUBLE_SCAN;
1150         if (pNv->alphaCursor && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1151                 regp->cursorConfig |=   (NV_CRTC_CURSOR_CONFIG_32BPP |
1152                                                         NV_CRTC_CURSOR_CONFIG_64PIXELS |
1153                                                         NV_CRTC_CURSOR_CONFIG_64LINES |
1154                                                         NV_CRTC_CURSOR_CONFIG_ALPHA_BLEND);
1155         } else {
1156                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_32LINES;
1157         }
1158
1159         /* Unblock some timings */
1160         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1161         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1162
1163         /* What is the purpose of this register? */
1164         /* 0x14 may be disabled? */
1165         regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1166
1167         /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
1168         if (is_lvds) {
1169                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x11;
1170         } else if (is_fp) {
1171                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1172         } else {
1173                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1174         }
1175
1176         /* These values seem to vary */
1177         /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
1178         regp->CRTC[NV_VGA_CRTCX_SCRATCH4] = savep->CRTC[NV_VGA_CRTCX_SCRATCH4];
1179
1180         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1181                 regp->CRTC[NV_VGA_CRTCX_45] = 0x0;
1182         } else {
1183                 regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1184         }
1185
1186         /* What does this do?:
1187          * bit0: crtc0
1188          * bit6: lvds
1189          * bit7: lvds + tmds (only in X)
1190          */
1191         if (nv_crtc->head == 0)
1192                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x1;
1193         else
1194                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x0;
1195
1196         if (is_lvds)
1197                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x40;
1198
1199         if (is_fp && !NVMatchModePrivate(mode, NV_MODE_VGA))
1200                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x80;
1201
1202         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) { /* we need consistent restore. */
1203                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[nv_crtc->head];
1204         } else {
1205                 /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1.*/
1206                 if (nv_crtc->head == 1) {
1207                         regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[0];
1208                 } else {
1209                         regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[0] + 4;
1210                 }
1211         }
1212
1213         if (pNv->twoHeads)
1214                 /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1215                 regp->gpio_ext = NVReadCRTC(pNv, 0, NV_PCRTC_GPIO_EXT);
1216
1217         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1218                 regp->unk830 = 0;
1219                 regp->unk834 = 0;
1220         } else {
1221                 regp->unk830 = mode->CrtcVDisplay - 3;
1222                 regp->unk834 = mode->CrtcVDisplay - 1;
1223         }
1224
1225         if (pNv->twoHeads)
1226                 /* This is what the blob does */
1227                 regp->unk850 = NVReadCRTC(pNv, 0, NV_CRTC_0850);
1228
1229         /* Never ever modify gpio, unless you know very well what you're doing */
1230         regp->gpio = NVReadCRTC(pNv, 0, NV_CRTC_GPIO);
1231
1232         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1233                 regp->config = 0x0; /* VGA mode */
1234         } else {
1235                 regp->config = 0x2; /* HSYNC mode */
1236         }
1237
1238         /* Some misc regs */
1239         regp->CRTC[NV_VGA_CRTCX_43] = 0x1;
1240         if (pNv->Architecture == NV_ARCH_40) {
1241                 regp->CRTC[NV_VGA_CRTCX_85] = 0xFF;
1242                 regp->CRTC[NV_VGA_CRTCX_86] = 0x1;
1243         }
1244
1245         /*
1246          * Calculate the state that is common to all crtc's (stored in the state struct).
1247          */
1248         ErrorF("crtc %d %d %d\n", nv_crtc->head, mode->CrtcHDisplay, pScrn->displayWidth);
1249         nv_crtc_calc_state_ext(crtc,
1250                                 mode,
1251                                 depth,
1252                                 pScrn->displayWidth,
1253                                 mode->CrtcHDisplay,
1254                                 mode->CrtcVDisplay,
1255                                 adjusted_mode->Clock,
1256                                 mode->Flags);
1257
1258         /* Enable slaved mode */
1259         if (is_fp) {
1260                 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1261         }
1262 }
1263
1264 static void
1265 nv_crtc_mode_set_ramdac_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1266 {
1267         ScrnInfoPtr pScrn = crtc->scrn;
1268         NVPtr pNv = NVPTR(pScrn);
1269         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1270         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1271         NVCrtcRegPtr savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1272         NVFBLayout *pLayout = &pNv->CurrentLayout;
1273         Bool is_fp = FALSE;
1274         Bool is_lvds = FALSE;
1275         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1276         NVOutputPrivatePtr nv_output = NULL;
1277         if (output) {
1278                 nv_output = output->driver_private;
1279
1280                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1281                         is_fp = TRUE;
1282
1283                 if (nv_output->type == OUTPUT_LVDS)
1284                         is_lvds = TRUE;
1285         }
1286
1287         if (is_fp) {
1288                 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
1289                 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
1290                 /* This is what the blob does. */
1291                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HSyncStart - 75 - 1;
1292                 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
1293                 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
1294                 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
1295                 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
1296
1297                 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
1298                 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
1299                 /* This is what the blob does. */
1300                 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VTotal - 5 - 1;
1301                 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
1302                 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
1303                 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
1304                 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
1305
1306                 ErrorF("Horizontal:\n");
1307                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
1308                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
1309                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
1310                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
1311                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
1312                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
1313                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
1314
1315                 ErrorF("Vertical:\n");
1316                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
1317                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
1318                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
1319                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
1320                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
1321                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
1322                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
1323         }
1324
1325         /*
1326         * bit0: positive vsync
1327         * bit4: positive hsync
1328         * bit8: enable center mode
1329         * bit9: enable native mode
1330         * bit24: 12/24 bit interface (12bit=on, 24bit=off)
1331         * bit26: a bit sometimes seen on some g70 cards
1332         * bit28: fp display enable bit
1333         * bit31: set for dual link LVDS
1334         * nv10reg contains a few more things, but i don't quite get what it all means.
1335         */
1336
1337         if (pNv->Architecture >= NV_ARCH_30)
1338                 regp->fp_control[nv_crtc->head] = 0x00100000;
1339         else
1340                 regp->fp_control[nv_crtc->head] = 0x00000000;
1341
1342         /* Deal with vsync/hsync polarity */
1343         /* LVDS screens do set this, but modes with +ve syncs are very rare */
1344         if (is_fp) {
1345                 if (adjusted_mode->Flags & V_PVSYNC)
1346                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
1347                 if (adjusted_mode->Flags & V_PHSYNC)
1348                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
1349         } else {
1350                 /* The blob doesn't always do this, but often */
1351                 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_VSYNC_DISABLE;
1352                 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_HSYNC_DISABLE;
1353         }
1354
1355         if (is_fp) {
1356                 if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) /* seems to be used almost always */
1357                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1358                 else if (nv_output->scaling_mode == SCALE_PANEL) /* panel needs to scale */
1359                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
1360                 /* This is also true for panel scaling, so we must put the panel scale check first */
1361                 else if (mode->Clock == adjusted_mode->Clock) /* native mode */
1362                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
1363                 else /* gpu needs to scale */
1364                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1365         }
1366
1367         if (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
1368                 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
1369
1370         /* If the special bit exists, it exists on both ramdacs */
1371         regp->fp_control[nv_crtc->head] |= NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL) & (1 << 26);
1372
1373         if (is_fp)
1374                 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS;
1375         else
1376                 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE;
1377
1378         Bool lvds_use_straps = pNv->dcb_table.entry[nv_output->dcb_entry].lvdsconf.use_straps_for_mode;
1379         if (is_lvds && ((lvds_use_straps && pNv->VBIOS.fp.dual_link) || (!lvds_use_straps && adjusted_mode->Clock >= pNv->VBIOS.fp.duallink_transition_clk)))
1380                 regp->fp_control[nv_crtc->head] |= (8 << 28);
1381
1382         if (is_fp) {
1383                 /* This can override HTOTAL and VTOTAL */
1384                 regp->debug_2 = 0;
1385                 /* We want automatic scaling */
1386                 regp->debug_1 = 0;
1387
1388                 regp->fp_hvalid_start = 0;
1389                 regp->fp_hvalid_end = (nv_output->fpWidth - 1);
1390                 regp->fp_vvalid_start = 0;
1391                 regp->fp_vvalid_end = (nv_output->fpHeight - 1);
1392
1393                 if (nv_output->scaling_mode == SCALE_ASPECT) {
1394                         /* Use 20.12 fixed point format to avoid floats */
1395                         uint32_t panel_ratio = (1 << 12) * nv_output->fpWidth / nv_output->fpHeight;
1396                         uint32_t aspect_ratio = (1 << 12) * mode->HDisplay / mode->VDisplay;
1397                         uint32_t h_scale = (1 << 12) * mode->HDisplay / nv_output->fpWidth;
1398                         uint32_t v_scale = (1 << 12) * mode->VDisplay / nv_output->fpHeight;
1399                         #define ONE_TENTH ((1 << 12) / 10)
1400
1401                         /* GPU scaling happens automatically at a ratio of 1.33 */
1402                         /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
1403                         if (h_scale != (1 << 12) && (panel_ratio > aspect_ratio + ONE_TENTH)) {
1404                                 uint32_t diff;
1405
1406                                 ErrorF("Scaling resolution on a widescreen panel\n");
1407
1408                                 /* Scaling in both directions needs to the same */
1409                                 h_scale = v_scale;
1410
1411                                 /* Set a new horizontal scale factor and enable testmode (bit12) */
1412                                 regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
1413
1414                                 diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
1415                                 regp->fp_hvalid_start = diff/2;
1416                                 regp->fp_hvalid_end = nv_output->fpWidth - (diff/2) - 1;
1417                         }
1418
1419                         /* Same scaling, just for panels with aspect ratios smaller than 1 */
1420                         if (v_scale != (1 << 12) && (panel_ratio < aspect_ratio - ONE_TENTH)) {
1421                                 uint32_t diff;
1422
1423                                 ErrorF("Scaling resolution on a portrait panel\n");
1424
1425                                 /* Scaling in both directions needs to the same */
1426                                 v_scale = h_scale;
1427
1428                                 /* Set a new vertical scale factor and enable testmode (bit28) */
1429                                 regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
1430
1431                                 diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
1432                                 regp->fp_vvalid_start = diff/2;
1433                                 regp->fp_vvalid_end = nv_output->fpHeight - (diff/2) - 1;
1434                         }
1435                 }
1436         }
1437
1438         if (!is_fp && NVMatchModePrivate(mode, NV_MODE_VGA)) {
1439                 regp->debug_1 = 0x08000800;
1440         }
1441
1442         if (pNv->Architecture >= NV_ARCH_10) {
1443                 /* Only bit that bios and blob set. */
1444                 regp->nv10_cursync = (1<<25);
1445         }
1446
1447         /* These are the common blob values, minus a few fp specific bit's */
1448         /* Let's keep the TMDS pll and fpclock running in all situations */
1449         regp->debug_0[nv_crtc->head] = 0x1101100;
1450
1451         if (is_fp && nv_output->scaling_mode != SCALE_NOSCALE) {
1452                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_XSCALE_ENABLED;
1453                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_YSCALE_ENABLED;
1454         } else if (is_fp) { /* no_scale mode, so we must center it */
1455                 uint32_t diff;
1456
1457                 diff = nv_output->fpWidth - mode->HDisplay;
1458                 regp->fp_hvalid_start = diff/2;
1459                 regp->fp_hvalid_end = (nv_output->fpWidth - diff/2 - 1);
1460
1461                 diff = nv_output->fpHeight - mode->VDisplay;
1462                 regp->fp_vvalid_start = diff/2;
1463                 regp->fp_vvalid_end = (nv_output->fpHeight - diff/2 - 1);
1464         }
1465
1466         /* Is this crtc bound or output bound? */
1467         /* Does the bios TMDS script try to change this sometimes? */
1468         if (is_fp) {
1469                 /* I am not completely certain, but seems to be set only for dfp's */
1470                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED;
1471         }
1472
1473         if (output)
1474                 ErrorF("output %d debug_0 %08X\n", nv_output->output_resource, regp->debug_0[nv_crtc->head]);
1475
1476         /* Flatpanel support needs at least a NV10 */
1477         if (pNv->twoHeads) {
1478                 if (pNv->FPDither || (is_lvds && !pNv->VBIOS.fp.if_is_24bit)) {
1479                         if (pNv->NVArch == 0x11)
1480                                 regp->dither = savep->dither | 0x00010000;
1481                         else {
1482                                 int i;
1483                                 regp->dither = savep->dither | 0x00000001;
1484                                 for (i = 0; i < 3; i++) {
1485                                         regp->dither_regs[i] = 0xe4e4e4e4;
1486                                         regp->dither_regs[i + 3] = 0x44444444;
1487                                 }
1488                         }
1489                 } else
1490                         regp->dither = savep->dither;
1491         }
1492
1493         uint8_t depth;
1494         /* This is mode related, not pitch. */
1495         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1496                 depth = pNv->console_mode[nv_crtc->head].depth;
1497         } else {
1498                 depth = pLayout->depth;
1499         }
1500
1501         switch (depth) {
1502                 case 4:
1503                         regp->general = 0x00000100;
1504                         break;
1505                 case 24:
1506                 case 15:
1507                         regp->general = 0x00100100;
1508                         break;
1509                 case 32:
1510                 case 16:
1511                 case 8:
1512                 default:
1513                         regp->general = 0x00101100;
1514                         break;
1515         }
1516
1517         if (depth > 8 && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1518                 regp->general |= 0x30; /* enable palette mode */
1519         }
1520
1521         if (pNv->alphaCursor && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1522                 /* PIPE_LONG mode, something to do with the size of the cursor? */
1523                 regp->general |= (1<<29);
1524         }
1525
1526         /* Some values the blob sets */
1527         /* This may apply to the real ramdac that is being used (for crosswired situations) */
1528         /* Nevertheless, it's unlikely to cause many problems, since the values are equal for both */
1529         regp->unk_a20 = 0x0;
1530         regp->unk_a24 = 0xfffff;
1531         regp->unk_a34 = 0x1;
1532
1533         if (pNv->twoHeads) {
1534                 /* Do we also "own" the other register pair? */
1535                 /* If we own neither, they will just be ignored at load time. */
1536                 uint8_t other_head = (~nv_crtc->head) & 1;
1537                 if (pNv->fp_regs_owner[other_head] == nv_crtc->head) {
1538                         if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS) {
1539                                 regp->fp_control[other_head] = regp->fp_control[nv_crtc->head];
1540                                 regp->debug_0[other_head] = regp->debug_0[nv_crtc->head];
1541                                 /* Set TMDS_PLL and FPCLK, only seen for a NV31M so far. */
1542                                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK;
1543                                 regp->debug_0[other_head] |= NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL;
1544                         } else {
1545                                 ErrorF("This is BAD, we own more than one fp reg set, but are not a LVDS or TMDS output.\n");
1546                         }
1547                 }
1548         }
1549 }
1550
1551 /**
1552  * Sets up registers for the given mode/adjusted_mode pair.
1553  *
1554  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1555  *
1556  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1557  * be easily turned on/off after this.
1558  */
1559 static void
1560 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
1561                  DisplayModePtr adjusted_mode,
1562                  int x, int y)
1563 {
1564         ScrnInfoPtr pScrn = crtc->scrn;
1565         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1566         NVPtr pNv = NVPTR(pScrn);
1567         NVFBLayout *pLayout = &pNv->CurrentLayout;
1568
1569         ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->head);
1570
1571         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->head);
1572         xf86PrintModeline(pScrn->scrnIndex, mode);
1573         if (pNv->twoHeads)
1574                 NVCrtcSetOwner(crtc);
1575
1576         nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
1577
1578         /* set sel_clk before calculating PLLs */
1579         nv_crtc_mode_set_sel_clk(crtc, &pNv->ModeReg);
1580         if (pNv->Architecture == NV_ARCH_40) {
1581                 ErrorF("writing sel_clk %08X\n", pNv->ModeReg.sel_clk);
1582                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, pNv->ModeReg.sel_clk);
1583         }
1584         nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
1585         nv_crtc_mode_set_ramdac_regs(crtc, mode, adjusted_mode);
1586
1587         NVVgaProtect(pNv, nv_crtc->head, true);
1588         nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
1589         nv_crtc_load_state_ext(crtc, &pNv->ModeReg, FALSE);
1590         if (pLayout->depth > 8)
1591                 nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
1592         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
1593         if (pNv->Architecture == NV_ARCH_40) {
1594                 nv40_crtc_load_state_pll(crtc, &pNv->ModeReg);
1595         } else {
1596                 nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
1597         }
1598
1599         NVVgaProtect(pNv, nv_crtc->head, false);
1600
1601         NVCrtcSetBase(crtc, x, y, NVMatchModePrivate(mode, NV_MODE_CONSOLE));
1602
1603 #if X_BYTE_ORDER == X_BIG_ENDIAN
1604         /* turn on LFB swapping */
1605         {
1606                 unsigned char tmp;
1607
1608                 tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
1609                 tmp |= (1 << 7);
1610                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
1611         }
1612 #endif
1613 }
1614
1615 void nv_crtc_save(xf86CrtcPtr crtc)
1616 {
1617         ScrnInfoPtr pScrn = crtc->scrn;
1618         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1619         NVPtr pNv = NVPTR(pScrn);
1620
1621         ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->head);
1622
1623         /* We just came back from terminal, so unlock */
1624         NVCrtcLockUnlock(crtc, FALSE);
1625
1626         nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
1627         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
1628         nv_crtc_save_state_palette(crtc, &pNv->SavedReg);
1629         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
1630         if (pNv->Architecture == NV_ARCH_40) {
1631                 nv40_crtc_save_state_pll(pNv, &pNv->SavedReg);
1632         } else {
1633                 nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
1634         }
1635 }
1636
1637 void nv_crtc_restore(xf86CrtcPtr crtc)
1638 {
1639         ScrnInfoPtr pScrn = crtc->scrn;
1640         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1641         NVPtr pNv = NVPTR(pScrn);
1642         RIVA_HW_STATE *state;
1643         NVCrtcRegPtr savep;
1644
1645         state = &pNv->SavedReg;
1646         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1647
1648         ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->head);
1649
1650         /* Just to be safe */
1651         NVCrtcLockUnlock(crtc, FALSE);
1652
1653         NVVgaProtect(pNv, nv_crtc->head, true);
1654         nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
1655         nv_crtc_load_state_ext(crtc, &pNv->SavedReg, TRUE);
1656         nv_crtc_load_state_palette(crtc, &pNv->SavedReg);
1657         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
1658
1659         /* Force restoring vpll. */
1660         state->vpll_changed[nv_crtc->head] = TRUE;
1661
1662         if (pNv->Architecture == NV_ARCH_40) {
1663                 nv40_crtc_load_state_pll(crtc, &pNv->SavedReg);
1664         } else {
1665                 nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
1666         }
1667         NVVgaProtect(pNv, nv_crtc->head, false);
1668
1669         nv_crtc->last_dpms = NV_DPMS_CLEARED;
1670 }
1671
1672 static void
1673 NVResetCrtcConfig(xf86CrtcPtr crtc, Bool set)
1674 {
1675         ScrnInfoPtr pScrn = crtc->scrn;
1676         NVPtr pNv = NVPTR(pScrn);
1677
1678         if (pNv->twoHeads) {
1679                 uint32_t val = 0;
1680
1681                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1682
1683                 if (set) {
1684                         NVCrtcRegPtr regp;
1685
1686                         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1687                         val = regp->head;
1688                 }
1689
1690                 NVCrtcWriteCRTC(crtc, NV_CRTC_FSEL, val);
1691         }
1692 }
1693
1694 void nv_crtc_prepare(xf86CrtcPtr crtc)
1695 {
1696         ScrnInfoPtr pScrn = crtc->scrn;
1697         NVPtr pNv = NVPTR(pScrn);
1698         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1699
1700         ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->head);
1701
1702         /* Just in case */
1703         NVCrtcLockUnlock(crtc, 0);
1704
1705         NVResetCrtcConfig(crtc, FALSE);
1706
1707         crtc->funcs->dpms(crtc, DPMSModeOff);
1708
1709         /* Sync the engine before adjust mode */
1710         if (pNv->EXADriverPtr) {
1711                 exaMarkSync(pScrn->pScreen);
1712                 exaWaitSync(pScrn->pScreen);
1713         }
1714
1715         NVBlankScreen(pNv, nv_crtc->head, true);
1716
1717         /* Some more preperation. */
1718         NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, 0x1); /* Go to non-vga mode/out of enhanced mode */
1719         if (pNv->Architecture == NV_ARCH_40) {
1720                 uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
1721                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
1722         }
1723 }
1724
1725 void nv_crtc_commit(xf86CrtcPtr crtc)
1726 {
1727         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1728         ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->head);
1729
1730         crtc->funcs->dpms (crtc, DPMSModeOn);
1731
1732         if (crtc->scrn->pScreen != NULL)
1733                 xf86_reload_cursors (crtc->scrn->pScreen);
1734
1735         NVResetCrtcConfig(crtc, TRUE);
1736 }
1737
1738 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
1739 {
1740         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1741         ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->head);
1742
1743         return FALSE;
1744 }
1745
1746 static void nv_crtc_unlock(xf86CrtcPtr crtc)
1747 {
1748         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1749         ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->head);
1750 }
1751
1752 static void
1753 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
1754                                         int size)
1755 {
1756         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1757         ScrnInfoPtr pScrn = crtc->scrn;
1758         NVPtr pNv = NVPTR(pScrn);
1759         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1760         int i, j;
1761
1762         switch (pNv->CurrentLayout.depth) {
1763         case 15:
1764                 /* R5G5B5 */
1765                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
1766                 for (i = 0; i < 32; i++) {
1767                         for (j = 0; j < 8; j++) {
1768                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1769                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
1770                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1771                         }
1772                 }
1773                 break;
1774         case 16:
1775                 /* R5G6B5 */
1776                 /* First deal with the 5 bit colors */
1777                 for (i = 0; i < 32; i++) {
1778                         for (j = 0; j < 8; j++) {
1779                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1780                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1781                         }
1782                 }
1783                 /* Now deal with the 6 bit color */
1784                 for (i = 0; i < 64; i++) {
1785                         for (j = 0; j < 4; j++) {
1786                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
1787                         }
1788                 }
1789                 break;
1790         default:
1791                 /* R8G8B8 */
1792                 for (i = 0; i < 256; i++) {
1793                         regp->DAC[i * 3] = red[i] >> 8;
1794                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
1795                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
1796                 }
1797                 break;
1798         }
1799
1800         nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
1801 }
1802
1803 /**
1804  * Allocates memory for a locked-in-framebuffer shadow of the given
1805  * width and height for this CRTC's rotated shadow framebuffer.
1806  */
1807
1808 static void *
1809 nv_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
1810 {
1811         ErrorF("nv_crtc_shadow_allocate is called\n");
1812         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1813         ScrnInfoPtr pScrn = crtc->scrn;
1814 #if !NOUVEAU_EXA_PIXMAPS
1815         ScreenPtr pScreen = pScrn->pScreen;
1816 #endif /* !NOUVEAU_EXA_PIXMAPS */
1817         NVPtr pNv = NVPTR(pScrn);
1818         void *offset;
1819
1820         unsigned long rotate_pitch;
1821         int size, align = 64;
1822
1823         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
1824         size = rotate_pitch * height;
1825
1826         assert(nv_crtc->shadow == NULL);
1827 #if NOUVEAU_EXA_PIXMAPS
1828         if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN,
1829                         align, size, &nv_crtc->shadow)) {
1830                 ErrorF("Failed to allocate memory for shadow buffer!\n");
1831                 return NULL;
1832         }
1833
1834         if (nv_crtc->shadow && nouveau_bo_map(nv_crtc->shadow, NOUVEAU_BO_RDWR)) {
1835                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1836                                 "Failed to map shadow buffer.\n");
1837                 return NULL;
1838         }
1839
1840         offset = nv_crtc->shadow->map;
1841 #else
1842         nv_crtc->shadow = exaOffscreenAlloc(pScreen, size, align, TRUE, NULL, NULL);
1843         if (nv_crtc->shadow == NULL) {
1844                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1845                         "Couldn't allocate shadow memory for rotated CRTC\n");
1846                 return NULL;
1847         }
1848         offset = pNv->FB->map + nv_crtc->shadow->offset;
1849 #endif /* NOUVEAU_EXA_PIXMAPS */
1850
1851         return offset;
1852 }
1853
1854 /**
1855  * Creates a pixmap for this CRTC's rotated shadow framebuffer.
1856  */
1857 static PixmapPtr
1858 nv_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
1859 {
1860         ErrorF("nv_crtc_shadow_create is called\n");
1861         ScrnInfoPtr pScrn = crtc->scrn;
1862 #if NOUVEAU_EXA_PIXMAPS
1863         ScreenPtr pScreen = pScrn->pScreen;
1864         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1865 #endif /* NOUVEAU_EXA_PIXMAPS */
1866         unsigned long rotate_pitch;
1867         PixmapPtr rotate_pixmap;
1868 #if NOUVEAU_EXA_PIXMAPS
1869         struct nouveau_pixmap *nvpix;
1870 #endif /* NOUVEAU_EXA_PIXMAPS */
1871
1872         if (!data)
1873                 data = crtc->funcs->shadow_allocate (crtc, width, height);
1874
1875         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
1876
1877 #if NOUVEAU_EXA_PIXMAPS
1878         /* Create a dummy pixmap, to get a private that will be accepted by the system.*/
1879         rotate_pixmap = pScreen->CreatePixmap(pScreen,
1880                                                                 0, /* width */
1881                                                                 0, /* height */
1882         #ifdef CREATE_PIXMAP_USAGE_SCRATCH /* there seems to have been no api bump */
1883                                                                 pScrn->depth,
1884                                                                 0);
1885         #else
1886                                                                 pScrn->depth);
1887         #endif /* CREATE_PIXMAP_USAGE_SCRATCH */
1888 #else
1889         rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen,
1890                                                                 width, height,
1891                                                                 pScrn->depth,
1892                                                                 pScrn->bitsPerPixel,
1893                                                                 rotate_pitch,
1894                                                                 data);
1895 #endif /* NOUVEAU_EXA_PIXMAPS */
1896
1897         if (rotate_pixmap == NULL) {
1898                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1899                         "Couldn't allocate shadow pixmap for rotated CRTC\n");
1900         }
1901
1902 #if NOUVEAU_EXA_PIXMAPS
1903         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
1904         if (!nvpix) {
1905                 ErrorF("No shadow private, stage 1\n");
1906         } else {
1907                 nvpix->bo = nv_crtc->shadow;
1908                 nvpix->mapped = TRUE;
1909         }
1910
1911         /* Modify the pixmap to actually be the one we need. */
1912         pScreen->ModifyPixmapHeader(rotate_pixmap,
1913                                         width,
1914                                         height,
1915                                         pScrn->depth,
1916                                         pScrn->bitsPerPixel,
1917                                         rotate_pitch,
1918                                         data);
1919
1920         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
1921         if (!nvpix || !nvpix->bo)
1922                 ErrorF("No shadow private, stage 2\n");
1923 #endif /* NOUVEAU_EXA_PIXMAPS */
1924
1925         return rotate_pixmap;
1926 }
1927
1928 static void
1929 nv_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
1930 {
1931         ErrorF("nv_crtc_shadow_destroy is called\n");
1932         ScrnInfoPtr pScrn = crtc->scrn;
1933         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1934         ScreenPtr pScreen = pScrn->pScreen;
1935
1936         if (rotate_pixmap) { /* This should also unmap the buffer object if relevant. */
1937                 pScreen->DestroyPixmap(rotate_pixmap);
1938         }
1939
1940 #if !NOUVEAU_EXA_PIXMAPS
1941         if (data && nv_crtc->shadow) {
1942                 exaOffscreenFree(pScreen, nv_crtc->shadow);
1943         }
1944 #endif /* !NOUVEAU_EXA_PIXMAPS */
1945
1946         nv_crtc->shadow = NULL;
1947 }
1948
1949 /* NV04-NV10 doesn't support alpha cursors */
1950 static const xf86CrtcFuncsRec nv_crtc_funcs = {
1951         .dpms = nv_crtc_dpms,
1952         .save = nv_crtc_save, /* XXX */
1953         .restore = nv_crtc_restore, /* XXX */
1954         .mode_fixup = nv_crtc_mode_fixup,
1955         .mode_set = nv_crtc_mode_set,
1956         .prepare = nv_crtc_prepare,
1957         .commit = nv_crtc_commit,
1958         .destroy = NULL, /* XXX */
1959         .lock = nv_crtc_lock,
1960         .unlock = nv_crtc_unlock,
1961         .set_cursor_colors = nv_crtc_set_cursor_colors,
1962         .set_cursor_position = nv_crtc_set_cursor_position,
1963         .show_cursor = nv_crtc_show_cursor,
1964         .hide_cursor = nv_crtc_hide_cursor,
1965         .load_cursor_image = nv_crtc_load_cursor_image,
1966         .gamma_set = nv_crtc_gamma_set,
1967         .shadow_create = nv_crtc_shadow_create,
1968         .shadow_allocate = nv_crtc_shadow_allocate,
1969         .shadow_destroy = nv_crtc_shadow_destroy,
1970 };
1971
1972 /* NV11 and up has support for alpha cursors. */
1973 /* Due to different maximum sizes we cannot allow it to use normal cursors */
1974 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
1975         .dpms = nv_crtc_dpms,
1976         .save = nv_crtc_save, /* XXX */
1977         .restore = nv_crtc_restore, /* XXX */
1978         .mode_fixup = nv_crtc_mode_fixup,
1979         .mode_set = nv_crtc_mode_set,
1980         .prepare = nv_crtc_prepare,
1981         .commit = nv_crtc_commit,
1982         .destroy = NULL, /* XXX */
1983         .lock = nv_crtc_lock,
1984         .unlock = nv_crtc_unlock,
1985         .set_cursor_colors = NULL, /* Alpha cursors do not need this */
1986         .set_cursor_position = nv_crtc_set_cursor_position,
1987         .show_cursor = nv_crtc_show_cursor,
1988         .hide_cursor = nv_crtc_hide_cursor,
1989         .load_cursor_argb = nv_crtc_load_cursor_argb,
1990         .gamma_set = nv_crtc_gamma_set,
1991         .shadow_create = nv_crtc_shadow_create,
1992         .shadow_allocate = nv_crtc_shadow_allocate,
1993         .shadow_destroy = nv_crtc_shadow_destroy,
1994 };
1995
1996
1997 void
1998 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
1999 {
2000         NVPtr pNv = NVPTR(pScrn);
2001         xf86CrtcPtr crtc;
2002         NVCrtcPrivatePtr nv_crtc;
2003
2004         if (pNv->NVArch >= 0x11) {
2005                 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
2006         } else {
2007                 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
2008         }
2009         if (crtc == NULL)
2010                 return;
2011
2012         nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
2013         nv_crtc->head = crtc_num;
2014         nv_crtc->last_dpms = NV_DPMS_CLEARED;
2015         pNv->fp_regs_owner[nv_crtc->head] = nv_crtc->head;
2016
2017         crtc->driver_private = nv_crtc;
2018
2019         NVCrtcLockUnlock(crtc, FALSE);
2020 }
2021
2022 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2023 {
2024         ScrnInfoPtr pScrn = crtc->scrn;
2025         NVPtr pNv = NVPTR(pScrn);
2026         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2027         int i;
2028         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
2029
2030         NVWritePVIO(pNv, nv_crtc->head, VGA_MISC_OUT_W, regp->MiscOutReg);
2031
2032         for (i = 0; i < 5; i++)
2033                 NVWriteVgaSeq(pNv, nv_crtc->head, i, regp->Sequencer[i]);
2034
2035         /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
2036         NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
2037
2038         for (i = 0; i < 25; i++)
2039                 NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
2040
2041         for (i = 0; i < 9; i++)
2042                 NVWriteVgaGr(pNv, nv_crtc->head, i, regp->Graphics[i]);
2043
2044         NVSetEnablePalette(pNv, nv_crtc->head, true);
2045         for (i = 0; i < 21; i++)
2046                 NVWriteVgaAttr(pNv, nv_crtc->head, i, regp->Attribute[i]);
2047
2048         NVSetEnablePalette(pNv, nv_crtc->head, false);
2049 }
2050
2051 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override)
2052 {
2053         ScrnInfoPtr pScrn = crtc->scrn;
2054         NVPtr pNv = NVPTR(pScrn);
2055         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2056         NVCrtcRegPtr regp;
2057         int i;
2058
2059         regp = &state->crtc_reg[nv_crtc->head];
2060
2061         if (pNv->Architecture >= NV_ARCH_10) {
2062                 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
2063                 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
2064                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
2065                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
2066                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2067                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2068                 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2069                 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2070                 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, 0);
2071
2072                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
2073                 NVCrtcWriteCRTC(crtc, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
2074                 NVCrtcWriteCRTC(crtc, NV_CRTC_0830, regp->unk830);
2075                 NVCrtcWriteCRTC(crtc, NV_CRTC_0834, regp->unk834);
2076                 if (pNv->Architecture == NV_ARCH_40) {
2077                         NVCrtcWriteCRTC(crtc, NV_CRTC_0850, regp->unk850);
2078                         NVCrtcWriteCRTC(crtc, NV_PCRTC_GPIO_EXT, regp->gpio_ext);
2079                 }
2080
2081                 if (pNv->Architecture == NV_ARCH_40) {
2082                         uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
2083                         if (regp->config == 0x2) { /* enhanced "horizontal only" non-vga mode */
2084                                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 | 0x10000);
2085                         } else {
2086                                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
2087                         }
2088                 }
2089         }
2090
2091         NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, regp->config);
2092         NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO, regp->gpio);
2093
2094         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
2095         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
2096         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
2097         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
2098         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
2099         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
2100         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
2101         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
2102         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
2103         if (pNv->Architecture >= NV_ARCH_30)
2104                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
2105
2106         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
2107         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
2108         if (pNv->Architecture == NV_ARCH_40) /* HW bug */
2109                 nv_crtc_fix_nv40_hw_cursor(pScrn, nv_crtc->head);
2110         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
2111         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
2112
2113         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
2114         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
2115         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SCRATCH4, regp->CRTC[NV_VGA_CRTCX_SCRATCH4]);
2116         if (pNv->Architecture >= NV_ARCH_10) {
2117                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
2118                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_43, regp->CRTC[NV_VGA_CRTCX_43]);
2119                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
2120                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_4B, regp->CRTC[NV_VGA_CRTCX_4B]);
2121                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
2122         }
2123         /* NV11 and NV20 stop at 0x52. */
2124         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
2125                 if (override)
2126                         for (i = 0; i < 0x10; i++)
2127                                 NVWriteVGACR5758(pNv, nv_crtc->head, i, regp->CR58[i]);
2128
2129                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
2130                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
2131
2132                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
2133
2134                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_85, regp->CRTC[NV_VGA_CRTCX_85]);
2135                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_86, regp->CRTC[NV_VGA_CRTCX_86]);
2136         }
2137
2138         /* Setting 1 on this value gives you interrupts for every vblank period. */
2139         NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_EN_0, 0);
2140         NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
2141 }
2142
2143 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2144 {
2145         ScrnInfoPtr pScrn = crtc->scrn;
2146         NVPtr pNv = NVPTR(pScrn);
2147         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2148         int i;
2149         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
2150
2151         regp->MiscOutReg = NVReadPVIO(pNv, nv_crtc->head, VGA_MISC_OUT_R);
2152
2153         for (i = 0; i < 25; i++)
2154                 regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
2155
2156         NVSetEnablePalette(pNv, nv_crtc->head, true);
2157         for (i = 0; i < 21; i++)
2158                 regp->Attribute[i] = NVReadVgaAttr(pNv, nv_crtc->head, i);
2159         NVSetEnablePalette(pNv, nv_crtc->head, false);
2160
2161         for (i = 0; i < 9; i++)
2162                 regp->Graphics[i] = NVReadVgaGr(pNv, nv_crtc->head, i);
2163
2164         for (i = 0; i < 5; i++)
2165                 regp->Sequencer[i] = NVReadVgaSeq(pNv, nv_crtc->head, i);
2166 }
2167
2168 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2169 {
2170         ScrnInfoPtr pScrn = crtc->scrn;
2171         NVPtr pNv = NVPTR(pScrn);
2172         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2173         NVCrtcRegPtr regp;
2174         int i;
2175
2176         regp = &state->crtc_reg[nv_crtc->head];
2177
2178         regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
2179         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
2180         regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
2181         regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
2182         regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
2183         regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
2184         regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
2185
2186         regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
2187         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
2188         regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
2189         if (pNv->Architecture >= NV_ARCH_30)
2190                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
2191         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
2192         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
2193         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
2194         regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
2195
2196         if (pNv->Architecture >= NV_ARCH_10) {
2197                 regp->unk830 = NVCrtcReadCRTC(crtc, NV_CRTC_0830);
2198                 regp->unk834 = NVCrtcReadCRTC(crtc, NV_CRTC_0834);
2199                 if (pNv->Architecture == NV_ARCH_40) {
2200                         regp->unk850 = NVCrtcReadCRTC(crtc, NV_CRTC_0850);
2201                         regp->gpio_ext = NVCrtcReadCRTC(crtc, NV_PCRTC_GPIO_EXT);
2202                 }
2203                 if (pNv->twoHeads) {
2204                         regp->head = NVCrtcReadCRTC(crtc, NV_CRTC_FSEL);
2205                         regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
2206                 }
2207                 regp->cursorConfig = NVCrtcReadCRTC(crtc, NV_CRTC_CURSOR_CONFIG);
2208         }
2209
2210         regp->gpio = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO);
2211         regp->config = NVCrtcReadCRTC(crtc, NV_CRTC_CONFIG);
2212
2213         regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
2214         regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
2215         regp->CRTC[NV_VGA_CRTCX_SCRATCH4] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SCRATCH4);
2216         if (pNv->Architecture >= NV_ARCH_10) {
2217                 regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
2218                 regp->CRTC[NV_VGA_CRTCX_43] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_43);
2219                 regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
2220                 regp->CRTC[NV_VGA_CRTCX_4B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_4B);
2221                 regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
2222         }
2223         /* NV11 and NV20 don't have this, they stop at 0x52. */
2224         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
2225                 for (i = 0; i < 0x10; i++)
2226                         regp->CR58[i] = NVReadVGACR5758(pNv, nv_crtc->head, i);
2227
2228                 regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
2229                 regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
2230                 regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
2231
2232                 regp->CRTC[NV_VGA_CRTCX_85] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_85);
2233                 regp->CRTC[NV_VGA_CRTCX_86] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_86);
2234         }
2235 }
2236
2237 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2238 {
2239         ScrnInfoPtr pScrn = crtc->scrn;
2240         NVPtr pNv = NVPTR(pScrn);
2241         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2242         NVCrtcRegPtr regp;
2243         int i;
2244
2245         regp = &state->crtc_reg[nv_crtc->head];
2246
2247         regp->general = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL);
2248
2249         regp->fp_control[0]     = NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL);
2250         regp->debug_0[0]        = NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
2251
2252         if (pNv->twoHeads) {
2253                 regp->fp_control[1]     = NVReadRAMDAC(pNv, 1, NV_RAMDAC_FP_CONTROL);
2254                 regp->debug_0[1]        = NVReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
2255
2256                 regp->debug_1   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1);
2257                 regp->debug_2   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2);
2258
2259                 regp->unk_a20 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A20);
2260                 regp->unk_a24 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A24);
2261                 regp->unk_a34 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A34);
2262         }
2263
2264         if (pNv->NVArch == 0x11) {
2265                 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_DITHER_NV11);
2266         } else if (pNv->twoHeads) {
2267                 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DITHER);
2268                 for (i = 0; i < 3; i++) {
2269                         regp->dither_regs[i] = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_850 + i * 4);
2270                         regp->dither_regs[i + 3] = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_85C + i * 4);
2271                 }
2272         }
2273         if (pNv->Architecture >= NV_ARCH_10)
2274                 regp->nv10_cursync = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC);
2275
2276         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2277
2278         for (i = 0; i < 7; i++) {
2279                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2280                 regp->fp_horiz_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
2281         }
2282
2283         for (i = 0; i < 7; i++) {
2284                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2285                 regp->fp_vert_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
2286         }
2287
2288         regp->fp_hvalid_start = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_HVALID_START);
2289         regp->fp_hvalid_end = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_HVALID_END);
2290         regp->fp_vvalid_start = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_VVALID_START);
2291         regp->fp_vvalid_end = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_VVALID_END);
2292 }
2293
2294 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2295 {
2296         ScrnInfoPtr pScrn = crtc->scrn;
2297         NVPtr pNv = NVPTR(pScrn);
2298         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2299         NVCrtcRegPtr regp;
2300         int i;
2301
2302         regp = &state->crtc_reg[nv_crtc->head];
2303
2304         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL, regp->general);
2305
2306         if (pNv->fp_regs_owner[0] == nv_crtc->head) {
2307                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL, regp->fp_control[0]);
2308                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0, regp->debug_0[0]);
2309         }
2310         if (pNv->twoHeads) {
2311                 if (pNv->fp_regs_owner[1] == nv_crtc->head) {
2312                         NVWriteRAMDAC(pNv, 1, NV_RAMDAC_FP_CONTROL, regp->fp_control[1]);
2313                         NVWriteRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0, regp->debug_0[1]);
2314                 }
2315                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
2316                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
2317                 if (pNv->NVArch == 0x30) { /* For unknown purposes. */
2318                         uint32_t reg890 = NVCrtcReadRAMDAC(crtc, NV30_RAMDAC_890);
2319                         NVCrtcWriteRAMDAC(crtc, NV30_RAMDAC_89C, reg890);
2320                 }
2321
2322                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A20, regp->unk_a20);
2323                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A24, regp->unk_a24);
2324                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A34, regp->unk_a34);
2325         }
2326
2327         if (pNv->NVArch == 0x11) {
2328                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_DITHER_NV11, regp->dither);
2329         } else if (pNv->twoHeads) {
2330                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DITHER, regp->dither);
2331                 for (i = 0; i < 3; i++) {
2332                         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_850 + i * 4, regp->dither_regs[i]);
2333                         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_85C + i * 4, regp->dither_regs[i + 3]);
2334                 }
2335         }
2336         if (pNv->Architecture >= NV_ARCH_10)
2337                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
2338
2339         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2340
2341         for (i = 0; i < 7; i++) {
2342                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2343                 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_horiz_regs[i]);
2344         }
2345
2346         for (i = 0; i < 7; i++) {
2347                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2348                 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_vert_regs[i]);
2349         }
2350
2351         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_HVALID_START, regp->fp_hvalid_start);
2352         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_HVALID_END, regp->fp_hvalid_end);
2353         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_VVALID_START, regp->fp_vvalid_start);
2354         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_VVALID_END, regp->fp_vvalid_end);
2355 }
2356
2357 void
2358 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y, Bool bios_restore)
2359 {
2360         ScrnInfoPtr pScrn = crtc->scrn;
2361         NVPtr pNv = NVPTR(pScrn);
2362         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2363         NVFBLayout *pLayout = &pNv->CurrentLayout;
2364         uint32_t start = 0;
2365
2366         ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
2367
2368         if (bios_restore) {
2369                 start = pNv->console_mode[nv_crtc->head].fb_start;
2370         } else {
2371                 start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
2372                 if (crtc->rotatedData != NULL) { /* we do not exist on the real framebuffer */
2373 #if NOUVEAU_EXA_PIXMAPS
2374                         start = nv_crtc->shadow->offset;
2375 #else
2376                         start = pNv->FB->offset + nv_crtc->shadow->offset; /* We do exist relative to the framebuffer */
2377 #endif
2378                 } else {
2379                         start += pNv->FB->offset;
2380                 }
2381         }
2382
2383         /* 30 bits addresses in 32 bits according to haiku */
2384         NVCrtcWriteCRTC(crtc, NV_CRTC_START, start & 0xfffffffc);
2385
2386         /* set NV4/NV10 byte adress: (bit0 - 1) */
2387         NVWriteVgaAttr(pNv, nv_crtc->head, 0x13, (start & 0x3) << 1);
2388
2389         crtc->x = x;
2390         crtc->y = y;
2391 }
2392
2393 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2394 {
2395         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2396         NVPtr pNv = NVPTR(crtc->scrn);
2397         uint32_t mmiobase = nv_crtc->head ? NV_PDIO1_OFFSET : NV_PDIO0_OFFSET;
2398         int i;
2399
2400         VGA_WR08(pNv->REGS, VGA_DAC_MASK + mmiobase, 0xff);
2401         VGA_WR08(pNv->REGS, VGA_DAC_READ_ADDR + mmiobase, 0x0);
2402
2403         for (i = 0; i < 768; i++) {
2404                 state->crtc_reg[nv_crtc->head].DAC[i] = NV_RD08(pNv->REGS, VGA_DAC_DATA + mmiobase);
2405                 DDXMMIOH("nv_crtc_save_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_DATA + mmiobase, state->crtc_reg[nv_crtc->head].DAC[i]);
2406         }
2407
2408         NVSetEnablePalette(pNv, nv_crtc->head, false);
2409 }
2410 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2411 {
2412         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2413         NVPtr pNv = NVPTR(crtc->scrn);
2414         uint32_t mmiobase = nv_crtc->head ? NV_PDIO1_OFFSET : NV_PDIO0_OFFSET;
2415         int i;
2416
2417         VGA_WR08(pNv->REGS, VGA_DAC_MASK + mmiobase, 0xff);
2418         VGA_WR08(pNv->REGS, VGA_DAC_WRITE_ADDR + mmiobase, 0x0);
2419
2420         for (i = 0; i < 768; i++) {
2421                 DDXMMIOH("nv_crtc_load_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_DATA + mmiobase, state->crtc_reg[nv_crtc->head].DAC[i]);
2422                 NV_WR08(pNv->REGS, VGA_DAC_DATA + mmiobase, state->crtc_reg[nv_crtc->head].DAC[i]);
2423         }
2424
2425         NVSetEnablePalette(pNv, nv_crtc->head, false);
2426 }
2427
2428 /* Reset a mode after a drastic output resource change for example. */
2429 void NVCrtcModeFix(xf86CrtcPtr crtc)
2430 {
2431         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2432         Bool need_unlock;
2433
2434         if (!crtc->enabled)
2435                 return;
2436
2437         if (!xf86ModesEqual(&crtc->mode, &crtc->desiredMode)) /* not currently in X */
2438                 return;
2439
2440         DisplayModePtr adjusted_mode = xf86DuplicateMode(&crtc->mode);
2441         uint8_t dpms_mode = nv_crtc->last_dpms;
2442
2443         /* Set the crtc mode again. */
2444         crtc->funcs->dpms(crtc, DPMSModeOff);
2445         need_unlock = crtc->funcs->lock(crtc);
2446         crtc->funcs->mode_fixup(crtc, &crtc->mode, adjusted_mode);
2447         crtc->funcs->prepare(crtc);
2448         crtc->funcs->mode_set(crtc, &crtc->mode, adjusted_mode, crtc->x, crtc->y);
2449         crtc->funcs->commit(crtc);
2450         if (need_unlock)
2451                 crtc->funcs->unlock(crtc);
2452         crtc->funcs->dpms(crtc, dpms_mode);
2453
2454         /* Free mode. */
2455         xfree(adjusted_mode);
2456 }
2457
2458 /*************************************************************************** \
2459 |*                                                                           *|
2460 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
2461 |*                                                                           *|
2462 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
2463 |*     international laws.  Users and possessors of this source code are     *|
2464 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
2465 |*     use this code in individual and commercial software.                  *|
2466 |*                                                                           *|
2467 |*     Any use of this source code must include,  in the user documenta-     *|
2468 |*     tion and  internal comments to the code,  notices to the end user     *|
2469 |*     as follows:                                                           *|
2470 |*                                                                           *|
2471 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
2472 |*                                                                           *|
2473 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
2474 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
2475 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
2476 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
2477 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
2478 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
2479 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
2480 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
2481 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
2482 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
2483 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
2484 |*                                                                           *|
2485 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
2486 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
2487 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
2488 |*     computer  software  documentation,"  as such  terms  are  used in     *|
2489 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
2490 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
2491 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
2492 |*     all U.S. Government End Users  acquire the source code  with only     *|
2493 |*     those rights set forth herein.                                        *|
2494 |*                                                                           *|
2495  \***************************************************************************/