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38 \***************************************************************************/
40 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_dac.c,v 1.45 2005/07/09 00:53:00 mvojkovi Exp $ */
42 #include "nv_include.h"
45 NVDACPanelTweaks(NVPtr pNv, NVRegPtr state)
49 if(pNv->usePanelTweak) {
50 tweak = pNv->PanelTweak;
52 /* begin flat panel hacks */
53 /* This is unfortunate, but some chips need this register
54 tweaked or else you get artifacts where adjacent pixels are
55 swapped. There are no hard rules for what to set here so all
56 we can do is experiment and apply hacks. */
58 if(((pNv->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) {
59 /* At least one NV34 laptop needs this workaround. */
63 if((pNv->Chipset & 0xfff0) == CHIPSET_NV31) {
66 /* end flat panel hacks */
73 NVDACInit(ScrnInfoPtr pScrn, DisplayModePtr mode)
76 int horizDisplay = (mode->CrtcHDisplay/8) - 1;
77 int horizStart = (mode->CrtcHSyncStart/8) - 1;
78 int horizEnd = (mode->CrtcHSyncEnd/8) - 1;
79 int horizTotal = (mode->CrtcHTotal/8) - 5;
80 int horizBlankStart = (mode->CrtcHDisplay/8) - 1;
81 int horizBlankEnd = (mode->CrtcHTotal/8) - 1;
82 int vertDisplay = mode->CrtcVDisplay - 1;
83 int vertStart = mode->CrtcVSyncStart - 1;
84 int vertEnd = mode->CrtcVSyncEnd - 1;
85 int vertTotal = mode->CrtcVTotal - 2;
86 int vertBlankStart = mode->CrtcVDisplay - 1;
87 int vertBlankEnd = mode->CrtcVTotal - 1;
89 NVPtr pNv = NVPTR(pScrn);
90 NVRegPtr nvReg = &pNv->ModeReg;
91 NVFBLayout *pLayout = &pNv->CurrentLayout;
95 * Initialize all of the generic VGA registers. Don't bother with
96 * VGA_FIX_SYNC_PULSES, given the relevant CRTC settings are overridden
97 * below. Ditto for the KGA workaround.
99 if (!vgaHWInit(pScrn, mode))
102 pVga = &VGAHWPTR(pScrn)->ModeReg;
105 * Set all CRTC values.
108 if(mode->Flags & V_INTERLACE)
111 if(pNv->FlatPanel == 1) {
112 vertStart = vertTotal - 3;
113 vertEnd = vertTotal - 2;
114 vertBlankStart = vertStart;
115 horizStart = horizTotal - 5;
116 horizEnd = horizTotal - 2;
117 horizBlankEnd = horizTotal + 4;
118 if ( pNv->Architecture == NV_ARCH_30 )
122 pVga->CRTC[0x0] = Set8Bits(horizTotal);
123 pVga->CRTC[0x1] = Set8Bits(horizDisplay);
124 pVga->CRTC[0x2] = Set8Bits(horizBlankStart);
125 pVga->CRTC[0x3] = SetBitField(horizBlankEnd,4:0,4:0)
127 pVga->CRTC[0x4] = Set8Bits(horizStart);
128 pVga->CRTC[0x5] = SetBitField(horizBlankEnd,5:5,7:7)
129 | SetBitField(horizEnd,4:0,4:0);
130 pVga->CRTC[0x6] = SetBitField(vertTotal,7:0,7:0);
131 pVga->CRTC[0x7] = SetBitField(vertTotal,8:8,0:0)
132 | SetBitField(vertDisplay,8:8,1:1)
133 | SetBitField(vertStart,8:8,2:2)
134 | SetBitField(vertBlankStart,8:8,3:3)
136 | SetBitField(vertTotal,9:9,5:5)
137 | SetBitField(vertDisplay,9:9,6:6)
138 | SetBitField(vertStart,9:9,7:7);
139 pVga->CRTC[0x9] = SetBitField(vertBlankStart,9:9,5:5)
141 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00);
142 pVga->CRTC[0x10] = Set8Bits(vertStart);
143 pVga->CRTC[0x11] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
144 pVga->CRTC[0x12] = Set8Bits(vertDisplay);
145 pVga->CRTC[0x13] = ((pLayout->displayWidth/8)*(pLayout->bitsPerPixel/8));
146 pVga->CRTC[0x15] = Set8Bits(vertBlankStart);
147 pVga->CRTC[0x16] = Set8Bits(vertBlankEnd);
149 pVga->Attribute[0x10] = 0x01;
152 pVga->Attribute[0x11] = 0x00;
154 nvReg->screen = SetBitField(horizBlankEnd,6:6,4:4)
155 | SetBitField(vertBlankStart,10:10,3:3)
156 | SetBitField(vertStart,10:10,2:2)
157 | SetBitField(vertDisplay,10:10,1:1)
158 | SetBitField(vertTotal,10:10,0:0);
160 nvReg->horiz = SetBitField(horizTotal,8:8,0:0)
161 | SetBitField(horizDisplay,8:8,1:1)
162 | SetBitField(horizBlankStart,8:8,2:2)
163 | SetBitField(horizStart,8:8,3:3);
165 nvReg->extra = SetBitField(vertTotal,11:11,0:0)
166 | SetBitField(vertDisplay,11:11,2:2)
167 | SetBitField(vertStart,11:11,4:4)
168 | SetBitField(vertBlankStart,11:11,6:6);
170 if(mode->Flags & V_INTERLACE) {
171 horizTotal = (horizTotal >> 1) & ~1;
172 nvReg->interlace = Set8Bits(horizTotal);
173 nvReg->horiz |= SetBitField(horizTotal,8:8,4:4);
175 nvReg->interlace = 0xff; /* interlace off */
180 * Initialize DAC palette.
182 if(pLayout->bitsPerPixel != 8 )
184 for (i = 0; i < 256; i++)
187 pVga->DAC[(i*3)+1] = i;
188 pVga->DAC[(i*3)+2] = i;
193 * Calculate the extended registers.
196 if(pLayout->depth < 24)
200 if(pNv->Architecture >= NV_ARCH_10)
201 pNv->CURSOR = (CARD32 *)pNv->Cursor->map;
206 pLayout->displayWidth,
212 nvReg->scale = nvReadCurRAMDAC(pNv, NV_RAMDAC_FP_CONTROL) & 0xfff000ff;
213 if(pNv->FlatPanel == 1) {
214 nvReg->pixel |= (1 << 7);
215 if(!pNv->fpScaler || (pNv->fpWidth <= mode->HDisplay)
216 || (pNv->fpHeight <= mode->VDisplay))
218 nvReg->scale |= (1 << 8) ;
220 nvReg->crtcSync = nvReadCurRAMDAC(pNv, NV_RAMDAC_FP_HCRTC);
221 nvReg->crtcSync += NVDACPanelTweaks(pNv, nvReg);
224 nvReg->vpll = nvReg->pll;
225 nvReg->vpll2 = nvReg->pll;
226 nvReg->vpllB = nvReg->pllB;
227 nvReg->vpll2B = nvReg->pllB;
229 nvReg->fifo = nvReadVGA(pNv, 0x1c) & ~(1<<5);
231 if(pNv->CRTCnumber) {
232 nvReg->head = nvReadCRTC(pNv, 0, NV_CRTC_FSEL) & ~0x00001000;
233 nvReg->head2 = nvReadCRTC(pNv, 1, NV_CRTC_FSEL) | 0x00001000;
234 nvReg->crtcOwner = 3;
235 nvReg->pllsel |= 0x20000800;
236 nvReg->vpll = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
238 nvReg->vpllB = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
241 nvReg->head = nvReadCRTC(pNv, 0, NV_CRTC_FSEL) | 0x00001000;
242 nvReg->head2 = nvReadCRTC(pNv, 1, NV_CRTC_FSEL) & ~0x00001000;
243 nvReg->crtcOwner = 0;
244 nvReg->vpll2 = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
246 nvReg->vpll2B = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
249 nvReg->cursorConfig = 0x00000100;
250 if(mode->Flags & V_DBLSCAN)
251 nvReg->cursorConfig |= (1 << 4);
252 if(pNv->alphaCursor) {
253 if((pNv->Chipset & 0x0ff0) != CHIPSET_NV11)
254 nvReg->cursorConfig |= 0x04011000;
256 nvReg->cursorConfig |= 0x14011000;
257 nvReg->general |= (1 << 29);
259 nvReg->cursorConfig |= 0x02000000;
262 if((pNv->Chipset & 0x0ff0) == CHIPSET_NV11) {
263 nvReg->dither = nvReadCurRAMDAC(pNv, NV_RAMDAC_DITHER_NV11) & ~0x00010000;
265 nvReg->dither |= 0x00010000;
267 nvReg->dither = nvReadCurRAMDAC(pNv, NV_RAMDAC_FP_DITHER) & ~1;
275 nvReg->displayV = mode->CrtcVDisplay;
281 NVDACRestore(ScrnInfoPtr pScrn, vgaRegPtr vgaReg, NVRegPtr nvReg,
284 int restore = VGA_SR_MODE;
286 if(primary) restore |= VGA_SR_CMAP | VGA_SR_FONTS;
287 NVLoadStateExt(pScrn, nvReg);
288 #if defined(__powerpc__)
289 restore &= ~VGA_SR_FONTS;
291 vgaHWRestore(pScrn, vgaReg, restore);
297 * This function saves the video state.
300 NVDACSave(ScrnInfoPtr pScrn, vgaRegPtr vgaReg, NVRegPtr nvReg,
303 NVPtr pNv = NVPTR(pScrn);
305 #if defined(__powerpc__)
309 vgaHWSave(pScrn, vgaReg, VGA_SR_CMAP | VGA_SR_MODE |
310 (saveFonts? VGA_SR_FONTS : 0));
311 NVUnloadStateExt(pNv, nvReg);
313 /* can't read this reliably on NV11 */
314 if((pNv->Chipset & 0x0ff0) == CHIPSET_NV11)
315 nvReg->crtcOwner = pNv->CRTCnumber;
318 #define DEPTH_SHIFT(val, w) ((val << (8 - w)) | (val >> ((w << 1) - 8)))
319 #define MAKE_INDEX(in, w) (DEPTH_SHIFT(in, w) * 3)
322 NVDACLoadPalette(ScrnInfoPtr pScrn, int numColors, int *indices, LOCO *colors,
326 NVPtr pNv = NVPTR(pScrn);
329 pVga = &VGAHWPTR(pScrn)->ModeReg;
331 switch(pNv->CurrentLayout.depth) {
333 for(i = 0; i < numColors; i++) {
335 pVga->DAC[MAKE_INDEX(index, 5) + 0] = colors[index].red;
336 pVga->DAC[MAKE_INDEX(index, 5) + 1] = colors[index].green;
337 pVga->DAC[MAKE_INDEX(index, 5) + 2] = colors[index].blue;
341 for(i = 0; i < numColors; i++) {
343 pVga->DAC[MAKE_INDEX(index, 6) + 1] = colors[index].green;
345 pVga->DAC[MAKE_INDEX(index, 5) + 0] = colors[index].red;
346 pVga->DAC[MAKE_INDEX(index, 5) + 2] = colors[index].blue;
351 for(i = 0; i < numColors; i++) {
353 pVga->DAC[index*3] = colors[index].red;
354 pVga->DAC[(index*3)+1] = colors[index].green;
355 pVga->DAC[(index*3)+2] = colors[index].blue;
359 vgaHWRestore(pScrn, pVga, VGA_SR_CMAP);
363 * DDC1 support only requires DDC_SDA_MASK,
364 * DDC2 support requires DDC_SDA_MASK and DDC_SCL_MASK
366 #define DDC_SDA_READ_MASK (1 << 3)
367 #define DDC_SCL_READ_MASK (1 << 2)
368 #define DDC_SDA_WRITE_MASK (1 << 4)
369 #define DDC_SCL_WRITE_MASK (1 << 5)
372 NV_I2CGetBits(I2CBusPtr b, int *clock, int *data)
374 NVPtr pNv = NVPTR(xf86Screens[b->scrnIndex]);
377 /* Get the result. */
378 val = nvReadVGA(pNv, pNv->DDCBase);
380 *clock = (val & DDC_SCL_READ_MASK) != 0;
381 *data = (val & DDC_SDA_READ_MASK) != 0;
385 NV_I2CPutBits(I2CBusPtr b, int clock, int data)
387 NVPtr pNv = NVPTR(xf86Screens[b->scrnIndex]);
390 val = nvReadVGA(pNv, pNv->DDCBase + 1) & 0xf0;
392 val |= DDC_SCL_WRITE_MASK;
394 val &= ~DDC_SCL_WRITE_MASK;
397 val |= DDC_SDA_WRITE_MASK;
399 val &= ~DDC_SDA_WRITE_MASK;
401 nvWriteVGA(pNv, pNv->DDCBase + 1, val | 0x1);
405 NVDACi2cInit(ScrnInfoPtr pScrn)
407 NVPtr pNv = NVPTR(pScrn);
410 I2CPtr = xf86CreateI2CBusRec();
411 if(!I2CPtr) return FALSE;
415 I2CPtr->BusName = "DDC";
416 I2CPtr->scrnIndex = pScrn->scrnIndex;
417 I2CPtr->I2CPutBits = NV_I2CPutBits;
418 I2CPtr->I2CGetBits = NV_I2CGetBits;
419 I2CPtr->AcknTimeout = 5;
421 if (!xf86I2CBusInit(I2CPtr)) {