git.oblomov.eu Git - nouveau/blob - src/nv_output.c

   1 /*
   2  * Copyright 2003 NVIDIA, Corporation
   3  * Copyright 2006 Dave Airlie
   4  * Copyright 2007 Maarten Maathuis
   5  * Copyright 2007-2008 Stuart Bennett
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  23  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  */
  26
  27 #include <X11/Xatom.h>
  28 #include "nv_include.h"
  29
  30 #define MULTIPLE_ENCODERS(e) (e & (e - 1))
  31 #define FOR_EACH_ENCODER_IN_CONNECTOR(i, c, e)  for (i = 0; i < pNv->dcb_table.entries; i++)    \
  32                                                         if (c->possible_encoders & (1 << i) &&  \
  33                                                             (e = &pNv->encoders[i]))
  34
  35 static int nv_output_ramdac_offset(struct nouveau_encoder *nv_encoder)
  36 {
  37         int offset = 0;
  38
  39         if (nv_encoder->dcb->or & (8 | OUTPUT_C))
  40                 offset += 0x68;
  41         if (nv_encoder->dcb->or & (8 | OUTPUT_B))
  42                 offset += 0x2000;
  43
  44         return offset;
  45 }
  46
  47 static Bool
  48 nv_load_detect(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder)
  49 {
  50         NVPtr pNv = NVPTR(pScrn);
  51         uint32_t testval, regoffset = nv_output_ramdac_offset(nv_encoder);
  52         uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput, saved_rtest_ctrl, temp;
  53         int head, present = 0;
  54         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
  55
  56 #define RGB_TEST_DATA(r,g,b) (r << 0 | g << 10 | b << 20)
  57         testval = RGB_TEST_DATA(0x140, 0x140, 0x140); /* 0x94050140 */
  58         if (pNv->VBIOS.dactestval)
  59                 testval = pNv->VBIOS.dactestval;
  60
  61         saved_rtest_ctrl = NVReadRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset);
  62         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset, saved_rtest_ctrl & ~0x00010000);
  63
  64         if (pNv->NVArch >= 0x17) {
  65                 saved_powerctrl_2 = nvReadMC(pNv, NV_PBUS_POWERCTRL_2);
  66
  67                 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, saved_powerctrl_2 & 0xd7ffffff);
  68                 if (regoffset == 0x68) {
  69                         saved_powerctrl_4 = nvReadMC(pNv, NV_PBUS_POWERCTRL_4);
  70                         nvWriteMC(pNv, NV_PBUS_POWERCTRL_4, saved_powerctrl_4 & 0xffffffcf);
  71                 }
  72         }
  73
  74         usleep(4000);
  75
  76         saved_routput = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset);
  77         head = (saved_routput & 0x100) >> 8;
  78         /* if there's a spare crtc, using it will minimise flicker for the case
  79          * where the in-use crtc is in use by an off-chip tmds encoder */
  80         if (xf86_config->crtc[head]->enabled && !xf86_config->crtc[head ^ 1]->enabled)
  81                 head ^= 1;
  82         /* nv driver and nv31 use 0xfffffeee, nv34 and 6600 use 0xfffffece */
  83         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset,
  84                       (saved_routput & 0xfffffece) | head << 8);
  85         usleep(1000);
  86
  87         temp = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset);
  88         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset, temp | 1);
  89
  90         NVWriteRAMDAC(pNv, head, NV_RAMDAC_TEST_DATA, 1 << 31 | testval);
  91         temp = NVReadRAMDAC(pNv, head, NV_RAMDAC_TEST_CONTROL);
  92         NVWriteRAMDAC(pNv, head, NV_RAMDAC_TEST_CONTROL, temp | 0x1000);
  93         usleep(1000);
  94
  95         present = NVReadRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset) & (1 << 28);
  96
  97         temp = NVReadRAMDAC(pNv, head, NV_RAMDAC_TEST_CONTROL);
  98         NVWriteRAMDAC(pNv, head, NV_RAMDAC_TEST_CONTROL, temp & 0xffffefff);
  99         NVWriteRAMDAC(pNv, head, NV_RAMDAC_TEST_DATA, 0);
 100
 101         /* bios does something more complex for restoring, but I think this is good enough */
 102         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset, saved_routput);
 103         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset, saved_rtest_ctrl);
 104         if (pNv->NVArch >= 0x17) {
 105                 if (regoffset == 0x68)
 106                         nvWriteMC(pNv, NV_PBUS_POWERCTRL_4, saved_powerctrl_4);
 107                 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, saved_powerctrl_2);
 108         }
 109
 110         if (present) {
 111                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Load detected on output %c\n", '@' + ffs(nv_encoder->dcb->or));
 112                 return TRUE;
 113         }
 114
 115         return FALSE;
 116 }
 117
 118 static void
 119 update_output_fields(xf86OutputPtr output, struct nouveau_encoder *det_encoder)
 120 {
 121         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 122         NVPtr pNv = NVPTR(output->scrn);
 123
 124         if (nv_connector->detected_encoder == det_encoder)
 125                 return;
 126
 127         nv_connector->detected_encoder = det_encoder;
 128         output->possible_crtcs = det_encoder->dcb->heads;
 129         if (det_encoder->dcb->type == OUTPUT_LVDS || det_encoder->dcb->type == OUTPUT_TMDS) {
 130                 output->doubleScanAllowed = false;
 131                 output->interlaceAllowed = false;
 132         } else {
 133                 output->doubleScanAllowed = true;
 134                 if (pNv->Architecture == NV_ARCH_20 ||
 135                    (pNv->Architecture == NV_ARCH_10 &&
 136                     (pNv->Chipset & 0x0ff0) != CHIPSET_NV10 &&
 137                     (pNv->Chipset & 0x0ff0) != CHIPSET_NV15))
 138                         /* HW is broken */
 139                         output->interlaceAllowed = false;
 140                 else
 141                         output->interlaceAllowed = true;
 142         }
 143 }
 144
 145 static xf86OutputStatus
 146 nv_output_detect(xf86OutputPtr output)
 147 {
 148         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 149         ScrnInfoPtr pScrn = output->scrn;
 150         NVPtr pNv = NVPTR(pScrn);
 151         struct nouveau_encoder *det_encoder;
 152         xf86OutputStatus ret = XF86OutputStatusDisconnected;
 153
 154         struct nouveau_encoder *find_encoder_by_type(NVOutputType type)
 155         {
 156                 int i;
 157                 for (i = 0; i < pNv->dcb_table.entries; i++)
 158                         if (nv_connector->possible_encoders & (1 << i) &&
 159                             (type == OUTPUT_ANY || pNv->encoders[i].dcb->type == type))
 160                                 return &pNv->encoders[i];
 161                 return NULL;
 162         }
 163
 164         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_detect is called.\n");
 165
 166         if (nv_connector->pDDCBus &&
 167             (nv_connector->edid = xf86OutputGetEDID(output, nv_connector->pDDCBus),
 168              xf86OutputSetEDID(output, nv_connector->edid), nv_connector->edid)) {
 169                 if (MULTIPLE_ENCODERS(nv_connector->possible_encoders)) {
 170                         if (nv_connector->edid->features.input_type)
 171                                 det_encoder = find_encoder_by_type(OUTPUT_TMDS);
 172                         else
 173                                 det_encoder = find_encoder_by_type(OUTPUT_ANALOG);
 174                 } else
 175                         det_encoder = find_encoder_by_type(OUTPUT_ANY);
 176                 ret = XF86OutputStatusConnected;
 177         } else if ((det_encoder = find_encoder_by_type(OUTPUT_ANALOG))) {
 178                 /* we don't have a load det function for early cards */
 179                 if (!pNv->twoHeads || pNv->NVArch == 0x11)
 180                         ret = XF86OutputStatusUnknown;
 181                 else if (pNv->twoHeads && nv_load_detect(pScrn, det_encoder))
 182                         ret = XF86OutputStatusConnected;
 183         } else if ((det_encoder = find_encoder_by_type(OUTPUT_LVDS))) {
 184                 if (det_encoder->dcb->lvdsconf.use_straps_for_mode &&
 185                     pNv->VBIOS.fp.native_mode)
 186                         ret = XF86OutputStatusConnected;
 187                 if (pNv->VBIOS.fp.edid) {
 188                         xf86DrvMsg(pScrn->scrnIndex, X_INFO,
 189                                    "Will use hardcoded BIOS FP EDID\n");
 190                         nv_connector->edid = xf86InterpretEDID(pScrn->scrnIndex, pNv->VBIOS.fp.edid);
 191                         xf86OutputSetEDID(output, nv_connector->edid);
 192                         ret = XF86OutputStatusConnected;
 193                 }
 194         }
 195
 196         if (ret != XF86OutputStatusDisconnected)
 197                 update_output_fields(output, det_encoder);
 198
 199         return ret;
 200 }
 201
 202 static DisplayModePtr
 203 get_native_mode_from_edid(xf86OutputPtr output, DisplayModePtr edid_modes)
 204 {
 205         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 206         struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder;
 207         ScrnInfoPtr pScrn = output->scrn;
 208         int max_h_active = 0, max_v_active = 0;
 209         int i;
 210         DisplayModePtr mode;
 211
 212         for (i = 0; i < DET_TIMINGS; i++) {
 213                 /* We only look at detailed timings atm */
 214                 if (nv_connector->edid->det_mon[i].type != DT)
 215                         continue;
 216                 /* Selecting only based on width ok? */
 217                 if (nv_connector->edid->det_mon[i].section.d_timings.h_active > max_h_active) {
 218                         max_h_active = nv_connector->edid->det_mon[i].section.d_timings.h_active;
 219                         max_v_active = nv_connector->edid->det_mon[i].section.d_timings.v_active;
 220                 }
 221         }
 222         if (!(max_h_active && max_v_active)) {
 223                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No EDID detailed timings available, bailing out.\n");
 224                 return NULL;
 225         }
 226
 227         if (nv_encoder->native_mode) {
 228                 xfree(nv_encoder->native_mode);
 229                 nv_encoder->native_mode = NULL;
 230         }
 231
 232         for (mode = edid_modes; mode != NULL; mode = mode->next) {
 233                 if (mode->HDisplay == max_h_active &&
 234                         mode->VDisplay == max_v_active) {
 235                         /* Take the preferred mode when it exists. */
 236                         if (mode->type & M_T_PREFERRED) {
 237                                 nv_encoder->native_mode = xf86DuplicateMode(mode);
 238                                 break;
 239                         }
 240                         /* Find the highest refresh mode otherwise. */
 241                         if (!nv_encoder->native_mode || (mode->VRefresh > nv_encoder->native_mode->VRefresh)) {
 242                                 if (nv_encoder->native_mode)
 243                                         xfree(nv_encoder->native_mode);
 244                                 mode->type |= M_T_PREFERRED;
 245                                 nv_encoder->native_mode = xf86DuplicateMode(mode);
 246                         }
 247                 }
 248         }
 249
 250         return nv_encoder->native_mode;
 251 }
 252
 253 static DisplayModePtr
 254 nv_output_get_edid_modes(xf86OutputPtr output)
 255 {
 256         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 257         struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder;
 258         ScrnInfoPtr pScrn = output->scrn;
 259         DisplayModePtr edid_modes;
 260
 261         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_get_edid_modes is called.\n");
 262
 263         if (!(edid_modes = xf86OutputGetEDIDModes(output)))
 264                 return edid_modes;
 265
 266         if (nv_encoder->dcb->type == OUTPUT_TMDS || nv_encoder->dcb->type == OUTPUT_LVDS)
 267                 if (!get_native_mode_from_edid(output, edid_modes))
 268                         return NULL;
 269
 270         if (nv_encoder->dcb->type == OUTPUT_LVDS) {
 271                 static bool dual_link_correction_done = false;
 272
 273                 if (!dual_link_correction_done) {
 274                         parse_lvds_manufacturer_table(pScrn, &NVPTR(pScrn)->VBIOS, nv_encoder->native_mode->Clock);
 275                         dual_link_correction_done = true;
 276                 }
 277         }
 278
 279         return edid_modes;
 280 }
 281
 282 static DisplayModePtr
 283 nv_lvds_output_get_modes(xf86OutputPtr output)
 284 {
 285         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 286         struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder;
 287         ScrnInfoPtr pScrn = output->scrn;
 288         NVPtr pNv = NVPTR(pScrn);
 289         DisplayModePtr modes;
 290
 291         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_lvds_output_get_modes is called.\n");
 292
 293         if ((modes = nv_output_get_edid_modes(output)))
 294                 return modes;
 295
 296         if (!nv_encoder->dcb->lvdsconf.use_straps_for_mode || pNv->VBIOS.fp.native_mode == NULL)
 297                 return NULL;
 298
 299         if (nv_encoder->native_mode)
 300                 xfree(nv_encoder->native_mode);
 301         nv_encoder->native_mode = xf86DuplicateMode(pNv->VBIOS.fp.native_mode);
 302
 303         return xf86DuplicateMode(pNv->VBIOS.fp.native_mode);
 304 }
 305
 306 static int nv_output_mode_valid(xf86OutputPtr output, DisplayModePtr mode)
 307 {
 308         struct nouveau_encoder *nv_encoder = to_nouveau_connector(output)->detected_encoder;
 309         NVPtr pNv = NVPTR(output->scrn);
 310
 311         if (!output->doubleScanAllowed && mode->Flags & V_DBLSCAN)
 312                 return MODE_NO_DBLESCAN;
 313         if (!output->interlaceAllowed && mode->Flags & V_INTERLACE)
 314                 return MODE_NO_INTERLACE;
 315
 316         if (nv_encoder->dcb->type == OUTPUT_ANALOG) {
 317                 if (mode->Clock > (pNv->twoStagePLL ? 400000 : 350000))
 318                         return MODE_CLOCK_HIGH;
 319                 if (mode->Clock < 12000)
 320                         return MODE_CLOCK_LOW;
 321         }
 322         if (nv_encoder->dcb->type == OUTPUT_LVDS || nv_encoder->dcb->type == OUTPUT_TMDS)
 323                 /* No modes > panel's native res */
 324                 if (mode->HDisplay > nv_encoder->native_mode->HDisplay ||
 325                     mode->VDisplay > nv_encoder->native_mode->VDisplay)
 326                         return MODE_PANEL;
 327         if (nv_encoder->dcb->type == OUTPUT_TMDS) {
 328                 if (nv_encoder->dcb->duallink_possible) {
 329                         if (mode->Clock > 330000) /* 2x165 MHz */
 330                                 return MODE_CLOCK_HIGH;
 331                 } else
 332                         if (mode->Clock > 165000) /* 165 MHz */
 333                                 return MODE_CLOCK_HIGH;
 334         }
 335
 336         return MODE_OK;
 337 }
 338
 339 static void
 340 nv_output_destroy (xf86OutputPtr output)
 341 {
 342         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 343         struct nouveau_encoder *nv_encoder;
 344         ScrnInfoPtr pScrn = output->scrn;
 345         NVPtr pNv = NVPTR(output->scrn);
 346         int i;
 347
 348         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_destroy is called.\n");
 349
 350         if (!nv_connector)
 351                 return;
 352
 353         if (nv_connector->edid)
 354                 xfree(nv_connector->edid);
 355         FOR_EACH_ENCODER_IN_CONNECTOR(i, nv_connector, nv_encoder)
 356                 if (nv_encoder->native_mode)
 357                         xfree(nv_encoder->native_mode);
 358         xfree(nv_connector);
 359 }
 360
 361 static Atom scaling_mode_atom;
 362 #define SCALING_MODE_NAME "SCALING_MODE"
 363 static const struct {
 364         char *name;
 365         enum scaling_modes mode;
 366 } scaling_mode[] = {
 367         { "panel", SCALE_PANEL },
 368         { "fullscreen", SCALE_FULLSCREEN },
 369         { "aspect", SCALE_ASPECT },
 370         { "noscale", SCALE_NOSCALE },
 371         { NULL, SCALE_INVALID}
 372 };
 373
 374 static Atom dithering_atom;
 375 #define DITHERING_MODE_NAME "DITHERING"
 376
 377 static void
 378 nv_output_create_resources(xf86OutputPtr output)
 379 {
 380         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 381         ScrnInfoPtr pScrn = output->scrn;
 382         INT32 dithering_range[2] = { 0, 1 };
 383         int error, i;
 384
 385         /* may be called before encoder is picked, resources will be created
 386          * by update_output_fields()
 387          */
 388         if (!nv_encoder)
 389                 return;
 390
 391         /* no properties for vga */
 392         if (nv_encoder->dcb->type == OUTPUT_ANALOG)
 393                 return;
 394
 395         /*
 396          * Setup scaling mode property.
 397          */
 398         scaling_mode_atom = MakeAtom(SCALING_MODE_NAME, sizeof(SCALING_MODE_NAME) - 1, TRUE);
 399
 400         error = RRConfigureOutputProperty(output->randr_output,
 401                                         scaling_mode_atom, TRUE, FALSE, FALSE,
 402                                         0, NULL);
 403
 404         if (error != 0) {
 405                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 406                         "RRConfigureOutputProperty error, %d\n", error);
 407         }
 408
 409         char *existing_scale_name = NULL;
 410         for (i = 0; scaling_mode[i].name; i++)
 411                 if (scaling_mode[i].mode == nv_encoder->scaling_mode)
 412                         existing_scale_name = scaling_mode[i].name;
 413
 414         error = RRChangeOutputProperty(output->randr_output, scaling_mode_atom,
 415                                         XA_STRING, 8, PropModeReplace,
 416                                         strlen(existing_scale_name),
 417                                         existing_scale_name, FALSE, TRUE);
 418
 419         if (error != 0) {
 420                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 421                         "Failed to set scaling mode, %d\n", error);
 422         }
 423
 424         /*
 425          * Setup dithering property.
 426          */
 427         dithering_atom = MakeAtom(DITHERING_MODE_NAME, sizeof(DITHERING_MODE_NAME) - 1, TRUE);
 428
 429         error = RRConfigureOutputProperty(output->randr_output,
 430                                         dithering_atom, TRUE, TRUE, FALSE,
 431                                         2, dithering_range);
 432
 433         if (error != 0) {
 434                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 435                         "RRConfigureOutputProperty error, %d\n", error);
 436         }
 437
 438         /* promote bool into int32 to make RandR DIX and big endian happy */
 439         int32_t existing_dither = nv_encoder->dithering;
 440         error = RRChangeOutputProperty(output->randr_output, dithering_atom,
 441                                         XA_INTEGER, 32, PropModeReplace, 1,
 442                                         &existing_dither, FALSE, TRUE);
 443
 444         if (error != 0) {
 445                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 446                         "Failed to set dithering mode, %d\n", error);
 447         }
 448
 449         RRPostPendingProperties(output->randr_output);
 450 }
 451
 452 static Bool
 453 nv_output_set_property(xf86OutputPtr output, Atom property,
 454                                 RRPropertyValuePtr value)
 455 {
 456         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 457
 458         if (property == scaling_mode_atom) {
 459                 int32_t ret;
 460                 char *name = NULL;
 461
 462                 if (value->type != XA_STRING || value->format != 8)
 463                         return FALSE;
 464
 465                 name = (char *) value->data;
 466
 467                 /* Match a string to a scaling mode */
 468                 ret = nv_scaling_mode_lookup(name, value->size);
 469                 if (ret == SCALE_INVALID)
 470                         return FALSE;
 471
 472                 /* LVDS must always use gpu scaling. */
 473                 if (ret == SCALE_PANEL && nv_encoder->dcb->type == OUTPUT_LVDS)
 474                         return FALSE;
 475
 476                 nv_encoder->scaling_mode = ret;
 477         } else if (property == dithering_atom) {
 478                 if (value->type != XA_INTEGER || value->format != 32)
 479                         return FALSE;
 480
 481                 int32_t val = *(int32_t *) value->data;
 482
 483                 if (val < 0 || val > 1)
 484                         return FALSE;
 485
 486                 nv_encoder->dithering = val;
 487         }
 488
 489         return TRUE;
 490 }
 491
 492 static Bool
 493 nv_output_mode_fixup(xf86OutputPtr output, DisplayModePtr mode,
 494                      DisplayModePtr adjusted_mode)
 495 {
 496         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 497
 498         if (nv_connector->nv_encoder != nv_connector->detected_encoder) {
 499                 nv_connector->nv_encoder = nv_connector->detected_encoder;
 500                 if (output->randr_output) {
 501                         RRDeleteOutputProperty(output->randr_output, dithering_atom);
 502                         RRDeleteOutputProperty(output->randr_output, scaling_mode_atom);
 503                         output->funcs->create_resources(output);
 504                 }
 505         }
 506
 507         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 508         ScrnInfoPtr pScrn = output->scrn;
 509
 510         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_mode_fixup is called.\n");
 511
 512         /* For internal panels and gpu scaling on DVI we need the native mode */
 513         if (nv_encoder->dcb->type == OUTPUT_LVDS ||
 514             (nv_encoder->dcb->type == OUTPUT_TMDS && nv_encoder->scaling_mode != SCALE_PANEL)) {
 515                 adjusted_mode->HDisplay = nv_encoder->native_mode->HDisplay;
 516                 adjusted_mode->HSkew = nv_encoder->native_mode->HSkew;
 517                 adjusted_mode->HSyncStart = nv_encoder->native_mode->HSyncStart;
 518                 adjusted_mode->HSyncEnd = nv_encoder->native_mode->HSyncEnd;
 519                 adjusted_mode->HTotal = nv_encoder->native_mode->HTotal;
 520                 adjusted_mode->VDisplay = nv_encoder->native_mode->VDisplay;
 521                 adjusted_mode->VScan = nv_encoder->native_mode->VScan;
 522                 adjusted_mode->VSyncStart = nv_encoder->native_mode->VSyncStart;
 523                 adjusted_mode->VSyncEnd = nv_encoder->native_mode->VSyncEnd;
 524                 adjusted_mode->VTotal = nv_encoder->native_mode->VTotal;
 525                 adjusted_mode->Clock = nv_encoder->native_mode->Clock;
 526                 adjusted_mode->Flags = nv_encoder->native_mode->Flags;
 527
 528                 xf86SetModeCrtc(adjusted_mode, INTERLACE_HALVE_V);
 529         }
 530
 531         return TRUE;
 532 }
 533
 534 static void nv_digital_output_prepare_sel_clk(NVPtr pNv, struct nouveau_encoder *nv_encoder, int head)
 535 {
 536         NVRegPtr state = &pNv->ModeReg;
 537         uint32_t bits1618 = nv_encoder->dcb->or & OUTPUT_A ? 0x10000 : 0x40000;
 538
 539         if (nv_encoder->dcb->location != LOC_ON_CHIP)
 540                 return;
 541
 542         /* SEL_CLK is only used on the primary ramdac
 543          * It toggles spread spectrum PLL output and sets the bindings of PLLs
 544          * to heads on digital outputs
 545          */
 546         if (head)
 547                 state->sel_clk |= bits1618;
 548         else
 549                 state->sel_clk &= ~bits1618;
 550
 551         /* nv30:
 552          *      bit 0           NVClk spread spectrum on/off
 553          *      bit 2           MemClk spread spectrum on/off
 554          *      bit 4           PixClk1 spread spectrum on/off toggle
 555          *      bit 6           PixClk2 spread spectrum on/off toggle
 556          *
 557          * nv40 (observations from bios behaviour and mmio traces):
 558          *      bits 4&6        as for nv30
 559          *      bits 5&7        head dependent as for bits 4&6, but do not appear with 4&6;
 560          *                      maybe a different spread mode
 561          *      bits 8&10       seen on dual-link dvi outputs, purpose unknown (set by POST scripts)
 562          *      The logic behind turning spread spectrum on/off in the first place,
 563          *      and which bit-pair to use, is unclear on nv40 (for earlier cards, the fp table
 564          *      entry has the necessary info)
 565          */
 566         if (nv_encoder->dcb->type == OUTPUT_LVDS && pNv->SavedReg.sel_clk & 0xf0) {
 567                 int shift = (pNv->SavedReg.sel_clk & 0x50) ? 0 : 1;
 568
 569                 state->sel_clk &= ~0xf0;
 570                 state->sel_clk |= (head ? 0x40 : 0x10) << shift;
 571         }
 572 }
 573
 574 static void
 575 nv_output_prepare(xf86OutputPtr output)
 576 {
 577         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 578         ScrnInfoPtr pScrn = output->scrn;
 579         NVPtr pNv = NVPTR(output->scrn);
 580         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(output->crtc);
 581         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 582
 583         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_prepare is called.\n");
 584
 585         output->funcs->dpms(output, DPMSModeOff);
 586
 587         /* calculate some output specific CRTC regs now, so that they can be written in nv_crtc_set_mode */
 588         if (nv_encoder->dcb->type == OUTPUT_LVDS || nv_encoder->dcb->type == OUTPUT_TMDS)
 589                 nv_digital_output_prepare_sel_clk(pNv, nv_encoder, nv_crtc->head);
 590
 591         /* Some NV4x have unknown values (0x3f, 0x50, 0x54, 0x6b, 0x79, 0x7f etc.) which we don't alter */
 592         if (!(regp->CRTC[NV_VGA_CRTCX_LCD] & 0x44)) {
 593                 if (nv_encoder->dcb->type == OUTPUT_LVDS || nv_encoder->dcb->type == OUTPUT_TMDS) {
 594                         regp->CRTC[NV_VGA_CRTCX_LCD] &= ~0x30;
 595                         regp->CRTC[NV_VGA_CRTCX_LCD] |= 0x3;
 596                         if (nv_crtc->head == 0)
 597                                 regp->CRTC[NV_VGA_CRTCX_LCD] |= 0x8;
 598                         else
 599                                 regp->CRTC[NV_VGA_CRTCX_LCD] &= ~0x8;
 600                         if (nv_encoder->dcb->location != LOC_ON_CHIP)
 601                                 regp->CRTC[NV_VGA_CRTCX_LCD] |= (nv_encoder->dcb->or << 4) & 0x30;
 602                 } else
 603                         regp->CRTC[NV_VGA_CRTCX_LCD] = 0;
 604         }
 605 }
 606
 607 static void
 608 nv_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, DisplayModePtr adjusted_mode)
 609 {
 610         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 611         ScrnInfoPtr pScrn = output->scrn;
 612         NVPtr pNv = NVPTR(pScrn);
 613         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(output->crtc);
 614
 615         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_mode_set is called.\n");
 616
 617         if (pNv->twoHeads && nv_encoder->dcb->type == OUTPUT_ANALOG) {
 618                 uint32_t dac_offset = nv_output_ramdac_offset(nv_encoder);
 619                 uint32_t otherdac;
 620                 int i;
 621
 622                 /* bit 16-19 are bits that are set on some G70 cards,
 623                  * but don't seem to have much effect */
 624                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + dac_offset,
 625                               nv_crtc->head << 8 | NV_RAMDAC_OUTPUT_DAC_ENABLE);
 626                 /* force any other vga encoders to bind to the other crtc */
 627                 for (i = 0; i < pNv->dcb_table.entries; i++)
 628                         if (i != nv_encoder->dcb->index && pNv->encoders[i].dcb &&
 629                             pNv->encoders[i].dcb->type == OUTPUT_ANALOG) {
 630                                 dac_offset = nv_output_ramdac_offset(&pNv->encoders[i]);
 631                                 otherdac = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + dac_offset);
 632                                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + dac_offset,
 633                                               (otherdac & ~0x100) | (nv_crtc->head ^ 1) << 8);
 634                         }
 635         }
 636         if (nv_encoder->dcb->type == OUTPUT_TMDS)
 637                 run_tmds_table(pScrn, nv_encoder->dcb, nv_crtc->head, adjusted_mode->Clock);
 638         else if (nv_encoder->dcb->type == OUTPUT_LVDS)
 639                 call_lvds_script(pScrn, nv_encoder->dcb, nv_crtc->head, LVDS_RESET, adjusted_mode->Clock);
 640
 641         /* This could use refinement for flatpanels, but it should work this way */
 642         if (pNv->NVArch < 0x44)
 643                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + nv_output_ramdac_offset(nv_encoder), 0xf0000000);
 644         else
 645                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + nv_output_ramdac_offset(nv_encoder), 0x00100000);
 646 }
 647
 648 static void
 649 nv_output_commit(xf86OutputPtr output)
 650 {
 651         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 652         ScrnInfoPtr pScrn = output->scrn;
 653         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(output->crtc);
 654
 655         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_output_commit is called.\n");
 656
 657         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Output %s is running on CRTC %d using output %c\n", output->name, nv_crtc->head, '@' + ffs(nv_encoder->dcb->or));
 658
 659         output->funcs->dpms(output, DPMSModeOn);
 660 }
 661
 662 static void dpms_update_fp_control(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
 663 {
 664         NVPtr pNv = NVPTR(pScrn);
 665         struct nouveau_crtc *nv_crtc;
 666         NVCrtcRegPtr regp;
 667         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 668         int i;
 669
 670         if (mode == DPMSModeOn) {
 671                 nv_crtc = to_nouveau_crtc(crtc);
 672                 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 673
 674                 nv_crtc->fp_users |= 1 << nv_encoder->dcb->index;
 675                 NVWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control & ~0x20000022);
 676         } else
 677                 for (i = 0; i < xf86_config->num_crtc; i++) {
 678                         nv_crtc = to_nouveau_crtc(xf86_config->crtc[i]);
 679                         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 680
 681                         nv_crtc->fp_users &= ~(1 << nv_encoder->dcb->index);
 682                         if (!nv_crtc->fp_users) {
 683                                 /* cut the FP output */
 684                                 regp->fp_control |= 0x20000022;
 685                                 NVWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control);
 686                         }
 687                 }
 688 }
 689
 690 static void
 691 lvds_encoder_dpms(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
 692 {
 693         NVPtr pNv = NVPTR(pScrn);
 694
 695         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "lvds_encoder_dpms is called with mode %d\n", mode);
 696
 697         if (nv_encoder->last_dpms == mode)
 698                 return;
 699         nv_encoder->last_dpms = mode;
 700
 701         if (nv_encoder->dcb->lvdsconf.use_power_scripts) {
 702                 /* when removing an output, crtc may not be set, but PANEL_OFF must still be run */
 703                 int head = nv_get_digital_bound_head(pNv, nv_encoder->dcb->or);
 704                 int pclk = nv_encoder->native_mode->Clock;
 705
 706                 if (crtc)
 707                         head = to_nouveau_crtc(crtc)->head;
 708
 709                 if (mode == DPMSModeOn)
 710                         call_lvds_script(pScrn, nv_encoder->dcb, head, LVDS_PANEL_ON, pclk);
 711                 else
 712                         call_lvds_script(pScrn, nv_encoder->dcb, head, LVDS_PANEL_OFF, pclk);
 713         }
 714
 715         dpms_update_fp_control(pScrn, nv_encoder, crtc, mode);
 716
 717         if (mode == DPMSModeOn)
 718                 nv_digital_output_prepare_sel_clk(pNv, nv_encoder, to_nouveau_crtc(crtc)->head);
 719         else {
 720                 pNv->ModeReg.sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
 721                 pNv->ModeReg.sel_clk &= ~0xf0;
 722         }
 723         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, pNv->ModeReg.sel_clk);
 724 }
 725
 726 static void
 727 vga_encoder_dpms(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
 728 {
 729         NVPtr pNv = NVPTR(pScrn);
 730
 731         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vga_encoder_dpms is called with mode %d\n", mode);
 732
 733         if (nv_encoder->last_dpms == mode)
 734                 return;
 735         nv_encoder->last_dpms = mode;
 736
 737         if (pNv->twoHeads) {
 738                 uint32_t outputval = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder));
 739
 740                 if (mode == DPMSModeOff)
 741                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder),
 742                                       outputval & ~NV_RAMDAC_OUTPUT_DAC_ENABLE);
 743                 else if (mode == DPMSModeOn)
 744                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder),
 745                                       outputval | NV_RAMDAC_OUTPUT_DAC_ENABLE);
 746         }
 747 }
 748
 749 static void
 750 tmds_encoder_dpms(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder, xf86CrtcPtr crtc, int mode)
 751 {
 752         NVPtr pNv = NVPTR(pScrn);
 753
 754         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "tmds_encoder_dpms is called with mode %d\n", mode);
 755
 756         if (nv_encoder->last_dpms == mode)
 757                 return;
 758         nv_encoder->last_dpms = mode;
 759
 760         dpms_update_fp_control(pScrn, nv_encoder, crtc, mode);
 761
 762         if (nv_encoder->dcb->location != LOC_ON_CHIP) {
 763                 struct nouveau_crtc *nv_crtc;
 764                 int i;
 765
 766                 if (mode == DPMSModeOn) {
 767                         nv_crtc = to_nouveau_crtc(crtc);
 768                         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LCD,
 769                                        pNv->ModeReg.crtc_reg[nv_crtc->head].CRTC[NV_VGA_CRTCX_LCD]);
 770                 } else
 771                         for (i = 0; i <= pNv->twoHeads; i++)
 772                                 NVWriteVgaCrtc(pNv, i, NV_VGA_CRTCX_LCD,
 773                                                NVReadVgaCrtc(pNv, i, NV_VGA_CRTCX_LCD) & ~((nv_encoder->dcb->or << 4) & 0x30));
 774         }
 775 }
 776
 777 static void nv_output_dpms(xf86OutputPtr output, int mode)
 778 {
 779         struct nouveau_connector *nv_connector = to_nouveau_connector(output);
 780         struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 781         ScrnInfoPtr pScrn = output->scrn;
 782         xf86CrtcPtr crtc = output->crtc;
 783         NVPtr pNv = NVPTR(pScrn);
 784         int i;
 785         void (* const encoder_dpms[4])(ScrnInfoPtr, struct nouveau_encoder *, xf86CrtcPtr, int) =
 786                 /* index matches DCB type */
 787                 { vga_encoder_dpms, NULL, tmds_encoder_dpms, lvds_encoder_dpms };
 788
 789         struct nouveau_encoder *nv_encoder_i;
 790         FOR_EACH_ENCODER_IN_CONNECTOR(i, nv_connector, nv_encoder_i)
 791                 if (nv_encoder_i != nv_encoder)
 792                         encoder_dpms[nv_encoder_i->dcb->type](pScrn, nv_encoder_i, crtc, DPMSModeOff);
 793
 794         if (nv_encoder) /* may be called before encoder is picked, but iteration above solves it */
 795                 encoder_dpms[nv_encoder->dcb->type](pScrn, nv_encoder, crtc, mode);
 796 }
 797
 798 static uint32_t nv_get_clock_from_crtc(ScrnInfoPtr pScrn, RIVA_HW_STATE *state, uint8_t crtc)
 799 {
 800         NVPtr pNv = NVPTR(pScrn);
 801         struct pll_lims pll_lim;
 802         uint32_t vplla = state->crtc_reg[crtc].vpll_a;
 803         uint32_t vpllb = state->crtc_reg[crtc].vpll_b;
 804         bool nv40_single = pNv->Architecture == 0x40 &&
 805                            ((!crtc && state->reg580 & NV_RAMDAC_580_VPLL1_ACTIVE) ||
 806                             (crtc && state->reg580 & NV_RAMDAC_580_VPLL2_ACTIVE));
 807
 808         if (!get_pll_limits(pScrn, crtc ? VPLL2 : VPLL1, &pll_lim))
 809                 return 0;
 810
 811         return nv_decode_pll_highregs(pNv, vplla, vpllb, nv40_single, pll_lim.refclk);
 812 }
 813
 814 void nv_encoder_save(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder)
 815 {
 816         NVPtr pNv = NVPTR(pScrn);
 817
 818         if (!nv_encoder->dcb)   /* uninitialised encoder */
 819                 return;
 820
 821         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_encoder_save is called.\n");
 822
 823         if (pNv->twoHeads && nv_encoder->dcb->type == OUTPUT_ANALOG)
 824                 nv_encoder->restore.output = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder));
 825         if (nv_encoder->dcb->type == OUTPUT_TMDS || nv_encoder->dcb->type == OUTPUT_LVDS)
 826                 nv_encoder->restore.head = nv_get_digital_bound_head(pNv, nv_encoder->dcb->or);
 827 }
 828
 829 void nv_encoder_restore(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder)
 830 {
 831         NVPtr pNv = NVPTR(pScrn);
 832         int head = nv_encoder->restore.head;
 833
 834         if (!nv_encoder->dcb)   /* uninitialised encoder */
 835                 return;
 836
 837         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_encoder_restore is called.\n");
 838
 839         if (pNv->twoHeads && nv_encoder->dcb->type == OUTPUT_ANALOG)
 840                 NVWriteRAMDAC(pNv, 0,
 841                               NV_RAMDAC_OUTPUT + nv_output_ramdac_offset(nv_encoder),
 842                               nv_encoder->restore.output);
 843         if (nv_encoder->dcb->type == OUTPUT_LVDS)
 844                 call_lvds_script(pScrn, nv_encoder->dcb, head, LVDS_PANEL_ON,
 845                                  nv_encoder->native_mode->Clock);
 846         if (nv_encoder->dcb->type == OUTPUT_TMDS) {
 847                 int clock = nv_get_clock_from_crtc(pScrn, &pNv->SavedReg, head);
 848
 849                 run_tmds_table(pScrn, nv_encoder->dcb, head, clock);
 850         }
 851
 852         nv_encoder->last_dpms = NV_DPMS_CLEARED;
 853 }
 854
 855 static const xf86OutputFuncsRec nv_output_funcs = {
 856         .dpms = nv_output_dpms,
 857         .mode_valid = nv_output_mode_valid,
 858         .mode_fixup = nv_output_mode_fixup,
 859         .mode_set = nv_output_mode_set,
 860         .detect = nv_output_detect,
 861         .get_modes = nv_output_get_edid_modes,
 862         .destroy = nv_output_destroy,
 863         .prepare = nv_output_prepare,
 864         .commit = nv_output_commit,
 865         .create_resources = nv_output_create_resources,
 866         .set_property = nv_output_set_property,
 867 };
 868
 869 static const xf86OutputFuncsRec nv_lvds_output_funcs = {
 870         .dpms = nv_output_dpms,
 871         .mode_valid = nv_output_mode_valid,
 872         .mode_fixup = nv_output_mode_fixup,
 873         .mode_set = nv_output_mode_set,
 874         .detect = nv_output_detect,
 875         .get_modes = nv_lvds_output_get_modes,
 876         .destroy = nv_output_destroy,
 877         .prepare = nv_output_prepare,
 878         .commit = nv_output_commit,
 879         .create_resources = nv_output_create_resources,
 880         .set_property = nv_output_set_property,
 881 };
 882
 883 static void
 884 nv_add_encoder(ScrnInfoPtr pScrn, struct dcb_entry *dcbent)
 885 {
 886         NVPtr pNv = NVPTR(pScrn);
 887         struct nouveau_encoder *nv_encoder = &pNv->encoders[dcbent->index];
 888
 889         nv_encoder->dcb = dcbent;
 890         nv_encoder->last_dpms = NV_DPMS_CLEARED;
 891         nv_encoder->dithering = (pNv->FPDither || (nv_encoder->dcb->type == OUTPUT_LVDS && !pNv->VBIOS.fp.if_is_24bit));
 892         if (pNv->fpScaler) /* GPU Scaling */
 893                 nv_encoder->scaling_mode = SCALE_ASPECT;
 894         else if (nv_encoder->dcb->type == OUTPUT_LVDS)
 895                 nv_encoder->scaling_mode = SCALE_NOSCALE;
 896         else
 897                 nv_encoder->scaling_mode = SCALE_PANEL;
 898         if (xf86GetOptValString(pNv->Options, OPTION_SCALING_MODE)) {
 899                 nv_encoder->scaling_mode = nv_scaling_mode_lookup(xf86GetOptValString(pNv->Options, OPTION_SCALING_MODE), -1);
 900                 if (nv_encoder->scaling_mode == SCALE_INVALID)
 901                         nv_encoder->scaling_mode = SCALE_ASPECT; /* default */
 902         }
 903 }
 904
 905 static void
 906 nv_add_connector(ScrnInfoPtr pScrn, int i2c_index, int encoders, const xf86OutputFuncsRec *output_funcs, char *outputname)
 907 {
 908         NVPtr pNv = NVPTR(pScrn);
 909         xf86OutputPtr output;
 910         struct nouveau_connector *nv_connector;
 911
 912         if (!(output = xf86OutputCreate(pScrn, output_funcs, outputname)))
 913                 return;
 914         if (!(nv_connector = xcalloc(1, sizeof (struct nouveau_connector)))) {
 915                 xf86OutputDestroy(output);
 916                 return;
 917         }
 918
 919         output->driver_private = nv_connector;
 920
 921         if (i2c_index < 0xf)
 922                 NV_I2CInit(pScrn, &nv_connector->pDDCBus, pNv->dcb_table.i2c_read[i2c_index], xstrdup(outputname));
 923         nv_connector->possible_encoders = encoders;
 924 }
 925
 926 void NvSetupOutputs(ScrnInfoPtr pScrn)
 927 {
 928         NVPtr pNv = NVPTR(pScrn);
 929         uint16_t connectors[0x10];
 930         struct dcb_entry *dcbent;
 931         int i, vga_count = 0, dvid_count = 0, dvii_count = 0, lvds_count = 0;
 932
 933         if (!(pNv->encoders = xcalloc(pNv->dcb_table.entries, sizeof (struct nouveau_encoder))))
 934                 return;
 935
 936         memset(connectors, 0, sizeof (connectors));
 937
 938         for (i = 0; i < pNv->dcb_table.entries; i++) {
 939                 dcbent = &pNv->dcb_table.entry[i];
 940
 941                 if (dcbent->type == OUTPUT_TV)
 942                         continue;
 943                 if (dcbent->type > 3) {
 944                         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DCB type %d not known\n", dcbent->type);
 945                         continue;
 946                 }
 947
 948                 connectors[dcbent->i2c_index] |= 1 << i;
 949
 950                 nv_add_encoder(pScrn, dcbent);
 951         }
 952
 953         for (i = 0; i < pNv->dcb_table.entries; i++) {
 954                 int i2c_index = pNv->dcb_table.entry[i].i2c_index;
 955                 uint16_t encoders = connectors[i2c_index];
 956                 char outputname[20];
 957                 xf86OutputFuncsRec const *funcs = &nv_output_funcs;
 958
 959                 if (!encoders)
 960                         continue;
 961
 962                 switch (pNv->dcb_table.entry[i].type) {
 963                 case OUTPUT_ANALOG:
 964                         if (!MULTIPLE_ENCODERS(encoders))
 965                                 sprintf(outputname, "VGA-%d", vga_count++);
 966                         else
 967                                 sprintf(outputname, "DVI-I-%d", dvii_count++);
 968                         break;
 969                 case OUTPUT_TMDS:
 970                         if (!MULTIPLE_ENCODERS(encoders))
 971                                 sprintf(outputname, "DVI-D-%d", dvid_count++);
 972                         else
 973                                 sprintf(outputname, "DVI-I-%d", dvii_count++);
 974                         break;
 975                 case OUTPUT_LVDS:
 976                         sprintf(outputname, "LVDS-%d", lvds_count++);
 977                         funcs = &nv_lvds_output_funcs;
 978                         break;
 979                 default:
 980                         continue;
 981                 }
 982
 983                 nv_add_connector(pScrn, i2c_index, encoders, funcs, outputname);
 984                 connectors[i2c_index] = 0; /* avoid connectors being added multiply */
 985         }
 986 }