git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 2006 Dave Airlie
   3  * Copyright 2007 Maarten Maathuis
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
  26  * decleration is at the bottom of this file as it is rather ugly
  27  */
  28
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include <assert.h>
  34 #include "xf86.h"
  35 #include "os.h"
  36 #include "mibank.h"
  37 #include "globals.h"
  38 #include "xf86.h"
  39 #include "xf86Priv.h"
  40 #include "xf86DDC.h"
  41 #include "mipointer.h"
  42 #include "windowstr.h"
  43 #include <randrstr.h>
  44 #include <X11/extensions/render.h>
  45
  46 #include "xf86Crtc.h"
  47 #include "nv_include.h"
  48
  49 #include "vgaHW.h"
  50
  51 #define CRTC_INDEX 0x3d4
  52 #define CRTC_DATA 0x3d5
  53 #define CRTC_IN_STAT_1 0x3da
  54
  55 #define WHITE_VALUE 0x3F
  56 #define BLACK_VALUE 0x00
  57 #define OVERSCAN_VALUE 0x01
  58
  59 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  60 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override);
  61 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  62 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  63 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  64 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  65
  66 static uint8_t NVReadPVIO(xf86CrtcPtr crtc, uint32_t address)
  67 {
  68         ScrnInfoPtr pScrn = crtc->scrn;
  69         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  70         NVPtr pNv = NVPTR(pScrn);
  71
  72         /* Only NV4x have two pvio ranges */
  73         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  74                 return NV_RD08(pNv->PVIO1, address);
  75         } else {
  76                 return NV_RD08(pNv->PVIO0, address);
  77         }
  78 }
  79
  80 static void NVWritePVIO(xf86CrtcPtr crtc, uint32_t address, uint8_t value)
  81 {
  82         ScrnInfoPtr pScrn = crtc->scrn;
  83         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  84         NVPtr pNv = NVPTR(pScrn);
  85
  86         /* Only NV4x have two pvio ranges */
  87         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  88                 NV_WR08(pNv->PVIO1, address, value);
  89         } else {
  90                 NV_WR08(pNv->PVIO0, address, value);
  91         }
  92 }
  93
  94 static void NVWriteMiscOut(xf86CrtcPtr crtc, uint8_t value)
  95 {
  96         NVWritePVIO(crtc, VGA_MISC_OUT_W, value);
  97 }
  98
  99 static uint8_t NVReadMiscOut(xf86CrtcPtr crtc)
 100 {
 101         return NVReadPVIO(crtc, VGA_MISC_OUT_R);
 102 }
 103
 104 void NVWriteVGA(NVPtr pNv, int head, uint8_t index, uint8_t value)
 105 {
 106         volatile uint8_t *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 107
 108         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 109         NV_WR08(pCRTCReg, CRTC_DATA, value);
 110 }
 111
 112 uint8_t NVReadVGA(NVPtr pNv, int head, uint8_t index)
 113 {
 114         volatile uint8_t *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 115
 116         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 117         return NV_RD08(pCRTCReg, CRTC_DATA);
 118 }
 119
 120 /* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
 121  * I suspect they in fact do nothing, but are merely a way to carry useful
 122  * per-head variables around
 123  *
 124  * Known uses:
 125  * CR57         CR58
 126  * 0x00         index to the appropriate dcb entry (or 7f for inactive)
 127  * 0x02         dcb entry's "or" value (or 00 for inactive)
 128  * 0x03         bit0 set for dual link (LVDS, possibly elsewhere too)
 129  * 0x08 or 0x09 pxclk in MHz
 130  * 0x0f         laptop panel info -     low nibble for PEXTDEV_BOOT strap
 131  *                                      high nibble for xlat strap value
 132  */
 133
 134 void NVWriteVGACR5758(NVPtr pNv, int head, uint8_t index, uint8_t value)
 135 {
 136         NVWriteVGA(pNv, head, 0x57, index);
 137         NVWriteVGA(pNv, head, 0x58, value);
 138 }
 139
 140 uint8_t NVReadVGACR5758(NVPtr pNv, int head, uint8_t index)
 141 {
 142         NVWriteVGA(pNv, head, 0x57, index);
 143         return NVReadVGA(pNv, head, 0x58);
 144 }
 145
 146 void NVWriteVgaCrtc(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 147 {
 148         ScrnInfoPtr pScrn = crtc->scrn;
 149         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 150         NVPtr pNv = NVPTR(pScrn);
 151
 152         NVWriteVGA(pNv, nv_crtc->head, index, value);
 153 }
 154
 155 uint8_t NVReadVgaCrtc(xf86CrtcPtr crtc, uint8_t index)
 156 {
 157         ScrnInfoPtr pScrn = crtc->scrn;
 158         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 159         NVPtr pNv = NVPTR(pScrn);
 160
 161         return NVReadVGA(pNv, nv_crtc->head, index);
 162 }
 163
 164 static void NVWriteVgaSeq(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 165 {
 166         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 167         NVWritePVIO(crtc, VGA_SEQ_DATA, value);
 168 }
 169
 170 static uint8_t NVReadVgaSeq(xf86CrtcPtr crtc, uint8_t index)
 171 {
 172         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 173         return NVReadPVIO(crtc, VGA_SEQ_DATA);
 174 }
 175
 176 static void NVWriteVgaGr(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 177 {
 178         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 179         NVWritePVIO(crtc, VGA_GRAPH_DATA, value);
 180 }
 181
 182 static uint8_t NVReadVgaGr(xf86CrtcPtr crtc, uint8_t index)
 183 {
 184         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 185         return NVReadPVIO(crtc, VGA_GRAPH_DATA);
 186 }
 187
 188
 189 static void NVWriteVgaAttr(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 190 {
 191   ScrnInfoPtr pScrn = crtc->scrn;
 192   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 193   NVPtr pNv = NVPTR(pScrn);
 194   volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 195
 196   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 197   if (nv_crtc->paletteEnabled)
 198     index &= ~0x20;
 199   else
 200     index |= 0x20;
 201   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 202   NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
 203 }
 204
 205 static uint8_t NVReadVgaAttr(xf86CrtcPtr crtc, uint8_t index)
 206 {
 207   ScrnInfoPtr pScrn = crtc->scrn;
 208   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 209   NVPtr pNv = NVPTR(pScrn);
 210   volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 211
 212   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 213   if (nv_crtc->paletteEnabled)
 214     index &= ~0x20;
 215   else
 216     index |= 0x20;
 217   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 218   return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
 219 }
 220
 221 void NVCrtcSetOwner(xf86CrtcPtr crtc)
 222 {
 223         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 224         ScrnInfoPtr pScrn = crtc->scrn;
 225         NVPtr pNv = NVPTR(pScrn);
 226         /* Non standard beheaviour required by NV11 */
 227         if (pNv) {
 228                 uint8_t owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 229                 ErrorF("pre-Owner: 0x%X\n", owner);
 230                 if (owner == 0x04) {
 231                         uint32_t pbus84 = nvReadMC(pNv, 0x1084);
 232                         ErrorF("pbus84: 0x%X\n", pbus84);
 233                         pbus84 &= ~(1<<28);
 234                         ErrorF("pbus84: 0x%X\n", pbus84);
 235                         nvWriteMC(pNv, 0x1084, pbus84);
 236                 }
 237                 /* The blob never writes owner to pcio1, so should we */
 238                 if (pNv->NVArch == 0x11) {
 239                         NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, 0xff);
 240                 }
 241                 NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, nv_crtc->head * 0x3);
 242                 owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 243                 ErrorF("post-Owner: 0x%X\n", owner);
 244         } else {
 245                 ErrorF("pNv pointer is NULL\n");
 246         }
 247 }
 248
 249 static void
 250 NVEnablePalette(xf86CrtcPtr crtc)
 251 {
 252   ScrnInfoPtr pScrn = crtc->scrn;
 253   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 254   NVPtr pNv = NVPTR(pScrn);
 255   volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 256
 257   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 258   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
 259   nv_crtc->paletteEnabled = TRUE;
 260 }
 261
 262 static void
 263 NVDisablePalette(xf86CrtcPtr crtc)
 264 {
 265   ScrnInfoPtr pScrn = crtc->scrn;
 266   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 267   NVPtr pNv = NVPTR(pScrn);
 268   volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 269
 270   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 271   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
 272   nv_crtc->paletteEnabled = FALSE;
 273 }
 274
 275 static void NVWriteVgaReg(xf86CrtcPtr crtc, uint32_t reg, uint8_t value)
 276 {
 277  ScrnInfoPtr pScrn = crtc->scrn;
 278   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 279   NVPtr pNv = NVPTR(pScrn);
 280   volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 281
 282   NV_WR08(pCRTCReg, reg, value);
 283 }
 284
 285 /* perform a sequencer reset */
 286 static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
 287 {
 288   if (start)
 289     NVWriteVgaSeq(crtc, 0x00, 0x1);
 290   else
 291     NVWriteVgaSeq(crtc, 0x00, 0x3);
 292
 293 }
 294 static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
 295 {
 296         uint8_t tmp;
 297
 298         if (on) {
 299                 tmp = NVReadVgaSeq(crtc, 0x1);
 300                 NVVgaSeqReset(crtc, TRUE);
 301                 NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
 302
 303                 NVEnablePalette(crtc);
 304         } else {
 305                 /*
 306                  * Reenable sequencer, then turn on screen.
 307                  */
 308                 tmp = NVReadVgaSeq(crtc, 0x1);
 309                 NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20); /* reenable display */
 310                 NVVgaSeqReset(crtc, FALSE);
 311
 312                 NVDisablePalette(crtc);
 313         }
 314 }
 315
 316 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool Lock)
 317 {
 318         uint8_t cr11;
 319
 320         NVCrtcSetOwner(crtc);
 321
 322         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57);
 323         cr11 = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE);
 324         if (Lock) cr11 |= 0x80;
 325         else cr11 &= ~0x80;
 326         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE, cr11);
 327 }
 328
 329 xf86OutputPtr
 330 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
 331 {
 332         ScrnInfoPtr pScrn = crtc->scrn;
 333         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 334         int i;
 335         for (i = 0; i < xf86_config->num_output; i++) {
 336                 xf86OutputPtr output = xf86_config->output[i];
 337
 338                 if (output->crtc == crtc) {
 339                         return output;
 340                 }
 341         }
 342
 343         return NULL;
 344 }
 345
 346 xf86CrtcPtr
 347 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
 348 {
 349         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 350         int i;
 351
 352         for (i = 0; i < xf86_config->num_crtc; i++) {
 353                 xf86CrtcPtr crtc = xf86_config->crtc[i];
 354                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 355                 if (nv_crtc->head == index)
 356                         return crtc;
 357         }
 358
 359         return NULL;
 360 }
 361
 362 /*
 363  * Calculate the Video Clock parameters for the PLL.
 364  */
 365 /* Code taken from NVClock, with permission of the author (being a GPL->MIT code transfer). */
 366
 367 static void
 368 CalculateVClkNV4x_SingleVCO(NVPtr pNv, struct pll_lims *pll_lim, uint32_t clockIn, uint32_t *n1_best, uint32_t *m1_best, uint32_t *p_best)
 369 {
 370         uint32_t clock, M, N, P;
 371         uint32_t delta, bestDelta, minM, maxM, minN, maxN, maxP;
 372         uint32_t minVCOInputFreq, minVCOFreq, maxVCOFreq;
 373         uint32_t VCOFreq;
 374         uint32_t refClk = pNv->CrystalFreqKHz;
 375         bestDelta = clockIn;
 376
 377         /* bios clocks are in MHz, we use KHz */
 378         minVCOInputFreq = pll_lim->vco1.min_inputfreq*1000;
 379         minVCOFreq = pll_lim->vco1.minfreq*1000;
 380         maxVCOFreq = pll_lim->vco1.maxfreq*1000;
 381         minM = pll_lim->vco1.min_m;
 382         maxM = pll_lim->vco1.max_m;
 383         minN = pll_lim->vco1.min_n;
 384         maxN = pll_lim->vco1.max_n;
 385
 386         maxP = 6;
 387
 388         /* The optimal frequency for the PLL to work at is somewhere in the center of its range.
 389         /  Choose a post divider in such a way to achieve this.
 390         /  The G8x nv driver does something similar but they they derive a minP and maxP. That
 391         /  doesn't seem required as you get so many matching clocks that you don't enter a second
 392         /  iteration for P. (The minP / maxP values in the nv driver only differ at most 1, so it is for
 393         /  some rare corner cases.
 394         */
 395         for (P=0, VCOFreq=maxVCOFreq/2; clockIn<=VCOFreq && P <= maxP; P++)
 396         {
 397                 VCOFreq /= 2;
 398         }
 399
 400         /* Calculate the m and n values. There are a lot of values which give the same speed;
 401         /  We choose the speed for which the difference with the request speed is as small as possible.
 402         */
 403         for (M=minM; M<=maxM; M++)
 404         {
 405                 /* The VCO has a minimum input frequency */
 406                 if ((refClk/M) < minVCOInputFreq)
 407                         break;
 408
 409                 for (N=minN; N<=maxN; N++)
 410                 {
 411                         /* Calculate the frequency generated by VCO1 */
 412                         clock = (int)(refClk * N / (float)M);
 413
 414                         /* Verify if the clock lies within the output limits of VCO1 */
 415                         if (clock < minVCOFreq)
 416                                 continue;
 417                         else if (clock > maxVCOFreq) /* It is no use to continue as the clock will only become higher */
 418                                 break;
 419
 420                         clock >>= P;
 421                         delta = abs((int)(clockIn - clock));
 422                         /* When the difference is 0 or less than .5% accept the speed */
 423                         if (((delta == 0) || ((float)delta/(float)clockIn <= 0.005)))
 424                         {
 425                                 *m1_best = M;
 426                                 *n1_best = N;
 427                                 *p_best = P;
 428                                 return;
 429                         }
 430
 431                         /* When the new difference is smaller than the old one, use this one */
 432                         if (delta < bestDelta)
 433                         {
 434                                 bestDelta = delta;
 435                                 *m1_best = M;
 436                                 *n1_best = N;
 437                                 *p_best = P;
 438                         }
 439                 }
 440         }
 441 }
 442
 443 static void
 444 CalculateVClkNV4x_DoubleVCO(NVPtr pNv, struct pll_lims *pll_lim, uint32_t clockIn, uint32_t *n1_best, uint32_t *n2_best, uint32_t *m1_best, uint32_t *m2_best, uint32_t *p_best)
 445 {
 446         uint32_t clock1, clock2, M, M2, N, N2, P;
 447         uint32_t delta, bestDelta, minM, minM2, maxM, maxM2, minN, minN2, maxN, maxN2, maxP;
 448         uint32_t minVCOInputFreq, minVCO2InputFreq, maxVCO2InputFreq, minVCOFreq, minVCO2Freq, maxVCOFreq, maxVCO2Freq;
 449         uint32_t VCO2Freq, maxClock;
 450         uint32_t refClk = pNv->CrystalFreqKHz;
 451         bestDelta = clockIn;
 452
 453         /* bios clocks are in MHz, we use KHz */
 454         minVCOInputFreq = pll_lim->vco1.min_inputfreq*1000;
 455         minVCOFreq = pll_lim->vco1.minfreq*1000;
 456         maxVCOFreq = pll_lim->vco1.maxfreq*1000;
 457         minM = pll_lim->vco1.min_m;
 458         maxM = pll_lim->vco1.max_m;
 459         minN = pll_lim->vco1.min_n;
 460         maxN = pll_lim->vco1.max_n;
 461
 462         minVCO2InputFreq = pll_lim->vco2.min_inputfreq*1000;
 463         maxVCO2InputFreq = pll_lim->vco2.max_inputfreq*1000;
 464         minVCO2Freq = pll_lim->vco2.minfreq*1000;
 465         maxVCO2Freq = pll_lim->vco2.maxfreq*1000;
 466         minM2 = pll_lim->vco2.min_m;
 467         maxM2 = pll_lim->vco2.max_m;
 468         minN2 = pll_lim->vco2.min_n;
 469         maxN2 = pll_lim->vco2.max_n;
 470
 471         maxP = 6;
 472
 473         maxClock = maxVCO2Freq;
 474         /* If the requested clock is behind the bios limits, try it anyway */
 475         if (clockIn > maxVCO2Freq)
 476                 maxClock = clockIn + clockIn/200; /* Add a .5% margin */
 477
 478         /* The optimal frequency for the PLL to work at is somewhere in the center of its range.
 479         /  Choose a post divider in such a way to achieve this.
 480         /  The G8x nv driver does something similar but they they derive a minP and maxP. That
 481         /  doesn't seem required as you get so many matching clocks that you don't enter a second
 482         /  iteration for P. (The minP / maxP values in the nv driver only differ at most 1, so it is for
 483         /  some rare corner cases.
 484         */
 485         for (P=0, VCO2Freq=maxClock/2; clockIn<=VCO2Freq && P <= maxP; P++)
 486         {
 487                 VCO2Freq /= 2;
 488         }
 489
 490         /* The PLLs on Geforce6/7 hardware can operate in a single stage made with only 1 VCO
 491         /  and a cascade mode of two VCOs. This second mode is in general used for relatively high
 492         /  frequencies. The loop below calculates the divider and multiplier ratios for the cascade
 493         /  mode. The code takes into account limits defined in the video bios.
 494         */
 495         for (M=minM; M<=maxM; M++)
 496         {
 497                 /* The VCO has a minimum input frequency */
 498                 if ((refClk/M) < minVCOInputFreq)
 499                         break;
 500
 501                 for (N=minN; N<=maxN; N++)
 502                 {
 503                         /* Calculate the frequency generated by VCO1 */
 504                         clock1 = (int)(refClk * N / (float)M);
 505                         /* Verify if the clock lies within the output limits of VCO1 */
 506                         if ( (clock1 < minVCOFreq) )
 507                                 continue;
 508                         else if (clock1 > maxVCOFreq) /* For future N, the clock will only increase so stop; xorg nv continues but that is useless */
 509                                 break;
 510
 511                         for (M2=minM2; M2<=maxM2; M2++)
 512                         {
 513                                 /* The clock fed to the second VCO needs to lie within a certain input range */
 514                                 if (clock1 / M2 < minVCO2InputFreq)
 515                                         break;
 516                                 else if (clock1 / M2 > maxVCO2InputFreq)
 517                                         continue;
 518
 519                                 N2 = (int)((float)((clockIn << P) * M * M2) / (float)(refClk * N)+.5);
 520                                 if( (N2 < minN2) || (N2 > maxN2) )
 521                                         continue;
 522
 523                                 /* The clock before being fed to the post-divider needs to lie within a certain range.
 524                                 /  Further there are some limits on N2/M2.
 525                                 */
 526                                 clock2 = (int)((float)(N*N2)/(M*M2) * refClk);
 527                                 if( (clock2 < minVCO2Freq) || (clock2 > maxClock))// || ((N2 / M2) < 4) || ((N2 / M2) > 10) )
 528                                         continue;
 529
 530                                 /* The post-divider delays the 'high' clock to create a low clock if requested.
 531                                 /  This post-divider exists because the VCOs can only generate frequencies within
 532                                 /  a limited frequency range. This range has been tuned to lie around half of its max
 533                                 /  input frequency. It tries to calculate all clocks (including lower ones) around this
 534                                 /  'center' frequency.
 535                                 */
 536                                 clock2 >>= P;
 537                                 delta = abs((int)(clockIn - clock2));
 538
 539                                 /* When the difference is 0 or less than .5% accept the speed */
 540                                 if (((delta == 0) || ((float)delta/(float)clockIn <= 0.005)))
 541                                 {
 542                                         *m1_best = M;
 543                                         *m2_best = M2;
 544                                         *n1_best = N;
 545                                         *n2_best = N2;
 546                                         *p_best = P;
 547                                         return;
 548                                 }
 549
 550                                 /* When the new difference is smaller than the old one, use this one */
 551                                 if (delta < bestDelta)
 552                                 {
 553                                         bestDelta = delta;
 554                                         *m1_best = M;
 555                                         *m2_best = M2;
 556                                         *n1_best = N;
 557                                         *n2_best = N2;
 558                                         *p_best = P;
 559                                 }
 560                         }
 561                 }
 562         }
 563 }
 564
 565 /* BIG NOTE: modifying vpll1 and vpll2 does not work, what bit is the switch to allow it? */
 566
 567 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
 568 /* They are only valid for NV4x, appearantly reordered for NV5x */
 569 /* gpu pll: 0x4000 + 0x4004
 570  * unknown pll: 0x4008 + 0x400c
 571  * vpll1: 0x4010 + 0x4014
 572  * vpll2: 0x4018 + 0x401c
 573  * unknown pll: 0x4020 + 0x4024
 574  * unknown pll: 0x4038 + 0x403c
 575  * Some of the unknown's are probably memory pll's.
 576  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
 577  * 1 and 2 refer to the registers of each pair. There is only one post divider.
 578  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
 579  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
 580  *     bit8: A switch that turns of the second divider and multiplier off.
 581  *     bit12: Also a switch, i haven't seen it yet.
 582  *     bit16-19: p-divider
 583  *     but 28-31: Something related to the mode that is used (see bit8).
 584  * 2) bit0-7: m-divider (a)
 585  *     bit8-15: n-multiplier (a)
 586  *     bit16-23: m-divider (b)
 587  *     bit24-31: n-multiplier (b)
 588  */
 589
 590 /* Modifying the gpu pll for example requires:
 591  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 592  * This is not needed for the vpll's which have their own bits.
 593  */
 594
 595 static void
 596 CalculateVClkNV4x(
 597         ScrnInfoPtr pScrn,
 598         uint32_t requested_clock,
 599         uint32_t *given_clock,
 600         uint32_t *pll_a,
 601         uint32_t *pll_b,
 602         uint32_t *reg580,
 603         Bool    *db1_ratio,
 604         Bool primary
 605 )
 606 {
 607         NVPtr pNv = NVPTR(pScrn);
 608         struct pll_lims pll_lim;
 609         /* We have 2 mulitpliers, 2 dividers and one post divider */
 610         /* Note that p is only 3 bits */
 611         uint32_t m1_best = 0, m2_best = 0, n1_best = 0, n2_best = 0, p_best = 0;
 612         uint32_t special_bits = 0;
 613
 614         if (primary) {
 615                 if (!get_pll_limits(pScrn, VPLL1, &pll_lim))
 616                         return;
 617         } else
 618                 if (!get_pll_limits(pScrn, VPLL2, &pll_lim))
 619                         return;
 620
 621         if (requested_clock < pll_lim.vco1.maxfreq*1000) { /* single VCO */
 622                 *db1_ratio = TRUE;
 623                 /* Turn the second set of divider and multiplier off */
 624                 /* Bogus data, the same nvidia uses */
 625                 n2_best = 1;
 626                 m2_best = 31;
 627                 CalculateVClkNV4x_SingleVCO(pNv, &pll_lim, requested_clock, &n1_best, &m1_best, &p_best);
 628         } else { /* dual VCO */
 629                 *db1_ratio = FALSE;
 630                 CalculateVClkNV4x_DoubleVCO(pNv, &pll_lim, requested_clock, &n1_best, &n2_best, &m1_best, &m2_best, &p_best);
 631         }
 632
 633         /* Are this all (relevant) G70 cards? */
 634         if (pNv->NVArch == 0x4B || pNv->NVArch == 0x46 || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
 635                 /* This is a big guess, but should be reasonable until we can narrow it down. */
 636                 if (*db1_ratio) {
 637                         special_bits = 0x1;
 638                 } else {
 639                         special_bits = 0x3;
 640                 }
 641         }
 642
 643         /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
 644         /* Let's keep the special bits, if the bios already set them */
 645         *pll_a = (special_bits << 30) | (p_best << 16) | (n1_best << 8) | (m1_best << 0);
 646         *pll_b = (1 << 31) | (n2_best << 8) | (m2_best << 0);
 647
 648         if (*db1_ratio) {
 649                 if (primary) {
 650                         *reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 651                 } else {
 652                         *reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 653                 }
 654         } else {
 655                 if (primary) {
 656                         *reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
 657                 } else {
 658                         *reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
 659                 }
 660         }
 661
 662         if (*db1_ratio) {
 663                 ErrorF("vpll: n1 %d m1 %d p %d db1_ratio %d\n", n1_best, m1_best, p_best, *db1_ratio);
 664         } else {
 665                 ErrorF("vpll: n1 %d n2 %d m1 %d m2 %d p %d db1_ratio %d\n", n1_best, n2_best, m1_best, m2_best, p_best, *db1_ratio);
 666         }
 667 }
 668
 669 static void nv40_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 670 {
 671         state->vpll1_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 672         state->vpll1_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 673         state->vpll2_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 674         state->vpll2_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 675         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 676         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 677         state->reg580 = nvReadRAMDAC0(pNv, NV_RAMDAC_580);
 678         state->reg594 = nvReadRAMDAC0(pNv, NV_RAMDAC_594);
 679 }
 680
 681 static void nv40_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 682 {
 683         ScrnInfoPtr pScrn = crtc->scrn;
 684         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 685         NVPtr pNv = NVPTR(pScrn);
 686         uint32_t fp_debug_0[2];
 687         uint32_t index[2];
 688         fp_debug_0[0] = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
 689         fp_debug_0[1] = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
 690
 691         uint32_t reg_c040_old = nvReadMC(pNv, 0xc040);
 692
 693         /* The TMDS_PLL switch is on the actual ramdac */
 694         if (state->crosswired) {
 695                 index[0] = 1;
 696                 index[1] = 0;
 697                 ErrorF("Crosswired pll state load\n");
 698         } else {
 699                 index[0] = 0;
 700                 index[1] = 1;
 701         }
 702
 703         if (state->vpll2_b && state->vpll_changed[1]) {
 704                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0,
 705                         fp_debug_0[index[1]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 706
 707                 /* Wait for the situation to stabilise */
 708                 usleep(5000);
 709
 710                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 711                 /* for vpll2 change bits 18 and 19 are disabled */
 712                 reg_c040 &= ~(0x3 << 18);
 713                 nvWriteMC(pNv, 0xc040, reg_c040);
 714
 715                 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 716                 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 717
 718                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2_a);
 719                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 720
 721                 ErrorF("writing pllsel %08X\n", state->pllsel);
 722                 /* Don't turn vpll1 off. */
 723                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 724
 725                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 726                 ErrorF("writing reg580 %08X\n", state->reg580);
 727
 728                 /* We need to wait a while */
 729                 usleep(5000);
 730                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 731
 732                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[1]]);
 733
 734                 /* Wait for the situation to stabilise */
 735                 usleep(5000);
 736         }
 737
 738         if (state->vpll1_b && state->vpll_changed[0]) {
 739                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0,
 740                         fp_debug_0[index[0]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 741
 742                 /* Wait for the situation to stabilise */
 743                 usleep(5000);
 744
 745                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 746                 /* for vpll2 change bits 16 and 17 are disabled */
 747                 reg_c040 &= ~(0x3 << 16);
 748                 nvWriteMC(pNv, 0xc040, reg_c040);
 749
 750                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 751                 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 752
 753                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll1_a);
 754                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpll1_b);
 755
 756                 ErrorF("writing pllsel %08X\n", state->pllsel);
 757                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 758
 759                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 760                 ErrorF("writing reg580 %08X\n", state->reg580);
 761
 762                 /* We need to wait a while */
 763                 usleep(5000);
 764                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 765
 766                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[0]]);
 767
 768                 /* Wait for the situation to stabilise */
 769                 usleep(5000);
 770         }
 771
 772         /* Let's be sure not to wake up any crtc's from dpms. */
 773         /* But we do want to keep our newly set crtc awake. */
 774         if (nv_crtc->head == 1) {
 775                 nvWriteMC(pNv, 0xc040, reg_c040_old | (pNv->misc_info.reg_c040 & (0x3 << 18)));
 776         } else {
 777                 nvWriteMC(pNv, 0xc040, reg_c040_old | (pNv->misc_info.reg_c040 & (0x3 << 16)));
 778         }
 779
 780         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 781         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 782
 783         ErrorF("writing reg594 %08X\n", state->reg594);
 784         nvWriteRAMDAC0(pNv, NV_RAMDAC_594, state->reg594);
 785
 786         /* All clocks have been set at this point. */
 787         state->vpll_changed[0] = FALSE;
 788         state->vpll_changed[1] = FALSE;
 789 }
 790
 791 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 792 {
 793         state->vpll1_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 794         if(pNv->twoHeads) {
 795                 state->vpll2_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 796         }
 797         if(pNv->twoStagePLL) {
 798                 state->vpll1_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 799                 state->vpll2_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 800         }
 801         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 802         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 803 }
 804
 805
 806 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 807 {
 808         /* This sequence is important, the NV28 is very sensitive in this area. */
 809         /* Keep pllsel last and sel_clk first. */
 810         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 811         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 812
 813         if (state->vpll2_a && state->vpll_changed[1]) {
 814                 if(pNv->twoHeads) {
 815                         ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 816                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2_a);
 817                 }
 818                 if(pNv->twoStagePLL) {
 819                         ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 820                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 821                 }
 822         }
 823
 824         if (state->vpll1_a && state->vpll_changed[0]) {
 825                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 826                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll1_a);
 827                 if(pNv->twoStagePLL) {
 828                         ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 829                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpll2_b);
 830                 }
 831         }
 832
 833         ErrorF("writing pllsel %08X\n", state->pllsel);
 834         nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 835
 836         /* All clocks have been set at this point. */
 837         state->vpll_changed[0] = FALSE;
 838         state->vpll_changed[1] = FALSE;
 839 }
 840
 841 #define IS_NV44P (pNv->NVArch >= 0x44 ? 1 : 0)
 842 #define SEL_CLK_OFFSET (nv_get_sel_clk_offset(pNv->NVArch, nv_output->bus))
 843
 844 #define WIPE_OTHER_CLOCKS(_sel_clk, _head, _bus) (nv_wipe_other_clocks(_sel_clk, pNv->NVArch, _head, _bus))
 845
 846 /*
 847  * Calculate extended mode parameters (SVGA) and save in a
 848  * mode state structure.
 849  * State is not specific to a single crtc, but shared.
 850  */
 851 void nv_crtc_calc_state_ext(
 852         xf86CrtcPtr     crtc,
 853         int                     bpp,
 854         int                     DisplayWidth, /* Does this change after setting the mode? */
 855         int                     CrtcHDisplay,
 856         int                     CrtcVDisplay,
 857         int                     dotClock,
 858         int                     flags
 859 )
 860 {
 861         ScrnInfoPtr pScrn = crtc->scrn;
 862         uint32_t pixelDepth, VClk = 0;
 863         uint32_t CursorStart;
 864         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 865         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 866         NVCrtcRegPtr regp;
 867         NVPtr pNv = NVPTR(pScrn);
 868         RIVA_HW_STATE *state;
 869         int num_crtc_enabled, i;
 870         uint32_t old_clock_a = 0, old_clock_b = 0;
 871
 872         state = &pNv->ModeReg;
 873
 874         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 875
 876         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 877         NVOutputPrivatePtr nv_output = NULL;
 878         if (output) {
 879                 nv_output = output->driver_private;
 880         }
 881
 882         /* Store old clock. */
 883         if (nv_crtc->head == 1) {
 884                 old_clock_a = state->vpll2_a;
 885                 old_clock_b = state->vpll2_b;
 886         } else {
 887                 old_clock_a = state->vpll1_a;
 888                 old_clock_b = state->vpll1_b;
 889         }
 890
 891         /*
 892          * Extended RIVA registers.
 893          */
 894         pixelDepth = (bpp + 1)/8;
 895         if (pNv->Architecture == NV_ARCH_40) {
 896                 /* Does register 0x580 already have a value? */
 897                 if (!state->reg580) {
 898                         state->reg580 = pNv->misc_info.ramdac_0_reg_580;
 899                 }
 900                 if (nv_crtc->head == 1) {
 901                         CalculateVClkNV4x(pScrn, dotClock, &VClk, &state->vpll2_a, &state->vpll2_b, &state->reg580, &state->db1_ratio[1], FALSE);
 902                 } else {
 903                         CalculateVClkNV4x(pScrn, dotClock, &VClk, &state->vpll1_a, &state->vpll1_b, &state->reg580, &state->db1_ratio[0], TRUE);
 904                 }
 905         } else if (pNv->twoStagePLL) {
 906                 struct pll_lims pll_lim;
 907                 int NM1, NM2, log2P;
 908                 get_pll_limits(pScrn, 0, &pll_lim);
 909                 VClk = getMNP_double(pScrn, &pll_lim, dotClock, &NM1, &NM2, &log2P);
 910                 state->pll = log2P << 16 | NM1;
 911                 state->pllB = 1 << 31 | NM2;
 912         } else {
 913                 int NM, log2P;
 914                 VClk = getMNP_single(pScrn, dotClock, &NM, &log2P);
 915                 state->pll = log2P << 16 | NM;
 916         }
 917
 918         if (pNv->Architecture < NV_ARCH_40) {
 919                 if (nv_crtc->head == 1) {
 920                         state->vpll2_a = state->pll;
 921                         state->vpll2_b = state->pllB;
 922                 } else {
 923                         state->vpll1_a = state->pll;
 924                         state->vpll1_b = state->pllB;
 925                 }
 926         }
 927
 928         if (nv_crtc->head == 1) {
 929                 state->vpll_changed[1] = ((state->vpll2_a == old_clock_a) && (state->vpll2_b == old_clock_b)) ? FALSE : TRUE;
 930         } else {
 931                 state->vpll_changed[0] = ((state->vpll1_a == old_clock_a) && (state->vpll1_b == old_clock_b)) ? FALSE : TRUE;
 932         }
 933
 934         switch (pNv->Architecture) {
 935         case NV_ARCH_04:
 936                 nv4UpdateArbitrationSettings(VClk,
 937                                                 pixelDepth * 8,
 938                                                 &(state->arbitration0),
 939                                                 &(state->arbitration1),
 940                                                 pNv);
 941                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
 942                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
 943                 if (flags & V_DBLSCAN)
 944                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 945                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
 946                 state->pllsel   |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
 947                 state->config   = 0x00001114;
 948                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 949                 break;
 950         case NV_ARCH_10:
 951         case NV_ARCH_20:
 952         case NV_ARCH_30:
 953         default:
 954                 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
 955                         ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
 956                         state->arbitration0 = 128;
 957                         state->arbitration1 = 0x0480;
 958                 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
 959                         ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
 960                         nForceUpdateArbitrationSettings(VClk,
 961                                                 pixelDepth * 8,
 962                                                 &(state->arbitration0),
 963                                                 &(state->arbitration1),
 964                                                 pNv);
 965                 } else if (pNv->Architecture < NV_ARCH_30) {
 966                         nv10UpdateArbitrationSettings(VClk,
 967                                                 pixelDepth * 8,
 968                                                 &(state->arbitration0),
 969                                                 &(state->arbitration1),
 970                                                 pNv);
 971                 } else {
 972                         nv30UpdateArbitrationSettings(pNv,
 973                                                 &(state->arbitration0),
 974                                                 &(state->arbitration1));
 975                 }
 976
 977                 if (nv_crtc->head == 1) {
 978                         CursorStart = pNv->Cursor2->offset;
 979                 } else {
 980                         CursorStart = pNv->Cursor->offset;
 981                 }
 982
 983                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
 984                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
 985                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
 986
 987                 if (flags & V_DBLSCAN)
 988                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 989
 990                 state->config   = nvReadFB(pNv, NV_PFB_CFG0);
 991                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 992                 break;
 993         }
 994
 995         /* okay do we have 2 CRTCs running ? */
 996         num_crtc_enabled = 0;
 997         for (i = 0; i < xf86_config->num_crtc; i++) {
 998                 if (xf86_config->crtc[i]->enabled) {
 999                         num_crtc_enabled++;
1000                 }
1001         }
1002
1003         ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
1004
1005         /* The main stuff seems to be valid for NV3x also. */
1006         if (pNv->Architecture >= NV_ARCH_30) {
1007                 /* This register is only used on the primary ramdac */
1008                 /* This seems to be needed to select the proper clocks, otherwise bad things happen */
1009
1010                 if (!state->sel_clk)
1011                         state->sel_clk = pNv->misc_info.sel_clk & ~(0xf << 16);
1012
1013                 if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
1014                         /* Only wipe when are a relevant (digital) output. */
1015                         state->sel_clk &= ~(0xf << 16);
1016                         Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1017                         /* Even with two dvi, this should not conflict. */
1018                         if (crossed_clocks) {
1019                                 state->sel_clk |= (0x1 << 16);
1020                         } else {
1021                                 state->sel_clk |= (0x4 << 16);
1022                         }
1023                 }
1024
1025                 /* Some cards, specifically dual dvi/lvds cards set another bitrange.
1026                  * I suspect inverse beheaviour to the normal bitrange, but i am not a 100% certain about this.
1027                  * This is all based on default settings found in mmio-traces.
1028                  * The blob never changes these, as it doesn't run unusual output configurations.
1029                  * It seems to prefer situations that avoid changing these bits (for a good reason?).
1030                  * I still don't know the purpose of value 2, it's similar to 4, but what exactly does it do?
1031                  */
1032
1033                 /* Some extra info:
1034                  * nv30:
1035                  *      bit 0           NVClk spread spectrum on/off
1036                  *      bit 2           MemClk spread spectrum on/off
1037                  *      bit 4           PixClk1 spread spectrum on/off
1038                  *      bit 6           PixClk2 spread spectrum on/off
1039
1040                  *      nv40:
1041                  *      what causes setting of bits not obvious but:
1042                  *      bits 4&5                relate to headA
1043                  *      bits 6&7                relate to headB
1044                 */
1045                 /* Only let digital outputs mess with this, otherwise strange output routings may mess it up. */
1046                 if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
1047                         if (pNv->Architecture == NV_ARCH_40) {
1048                                 for (i = 0; i < 4; i++) {
1049                                         uint32_t var = (state->sel_clk & (0xf << 4*i)) >> 4*i;
1050                                         if (var == 0x1 || var == 0x4) {
1051                                                 state->sel_clk &= ~(0xf << 4*i);
1052                                                 Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1053                                                 if (crossed_clocks) {
1054                                                         state->sel_clk |= (0x4 << 4*i);
1055                                                 } else {
1056                                                         state->sel_clk |= (0x1 << 4*i);
1057                                                 }
1058                                                 break; /* This should only occur once. */
1059                                         }
1060                                 }
1061                         }
1062                 }
1063
1064                 /* Are we crosswired? */
1065                 if (output && nv_crtc->head != nv_output->preferred_output) {
1066                         state->crosswired = TRUE;
1067                 } else {
1068                         state->crosswired = FALSE;
1069                 }
1070
1071                 if (nv_crtc->head == 1) {
1072                         if (state->db1_ratio[1])
1073                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1074                 } else if (nv_crtc->head == 0) {
1075                         if (state->db1_ratio[0])
1076                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1077                 }
1078         } else {
1079                 /* Do NV1x/NV2x cards need anything in sel_clk? */
1080                 state->sel_clk = 0x0;
1081                 state->crosswired = FALSE;
1082         }
1083
1084         /* The NV40 seems to have more similarities to NV3x than other cards. */
1085         if (pNv->NVArch < 0x41) {
1086                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL;
1087                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL;
1088         }
1089
1090         if (nv_crtc->head == 1) {
1091                 if (!state->db1_ratio[1]) {
1092                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1093                 } else {
1094                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1095                 }
1096                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
1097         } else {
1098                 if (!state->db1_ratio[0]) {
1099                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1100                 } else {
1101                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1102                 }
1103                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
1104         }
1105
1106         /* The blob uses this always, so let's do the same */
1107         if (pNv->Architecture == NV_ARCH_40) {
1108                 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
1109         }
1110
1111         /* The primary output resource doesn't seem to care */
1112         if (output && pNv->Architecture == NV_ARCH_40 && nv_output->output_resource == 1) { /* This is the "output" */
1113                 /* non-zero values are for analog, don't know about tv-out and the likes */
1114                 if (output && nv_output->type != OUTPUT_ANALOG) {
1115                         state->reg594 = 0x0;
1116                 } else if (output) {
1117                         /* Are we a flexible output? */
1118                         if (ffs(pNv->dcb_table.entry[nv_output->dcb_entry].or) & OUTPUT_0) {
1119                                 state->reg594 = 0x1;
1120                                 pNv->restricted_mode = FALSE;
1121                         } else {
1122                                 state->reg594 = 0x0;
1123                                 pNv->restricted_mode = TRUE;
1124                         }
1125
1126                         /* More values exist, but they seem related to the 3rd dac (tv-out?) somehow */
1127                         /* bit 16-19 are bits that are set on some G70 cards */
1128                         /* Those bits are also set to the 3rd OUTPUT register */
1129                         if (nv_crtc->head == 1) {
1130                                 state->reg594 |= 0x100;
1131                         }
1132                 }
1133         }
1134
1135         regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
1136         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
1137         if (pNv->Architecture >= NV_ARCH_30) {
1138                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
1139         }
1140
1141         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
1142         regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
1143 }
1144
1145 static void
1146 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
1147 {
1148         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1149         ScrnInfoPtr pScrn = crtc->scrn;
1150         NVPtr pNv = NVPTR(pScrn);
1151         unsigned char seq1 = 0, crtc17 = 0;
1152         unsigned char crtc1A;
1153
1154         ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->head, mode);
1155
1156         NVCrtcSetOwner(crtc);
1157
1158         crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
1159         switch(mode) {
1160                 case DPMSModeStandby:
1161                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
1162                 seq1 = 0x20;
1163                 crtc17 = 0x80;
1164                 crtc1A |= 0x80;
1165                 break;
1166         case DPMSModeSuspend:
1167                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
1168                 seq1 = 0x20;
1169                 crtc17 = 0x80;
1170                 crtc1A |= 0x40;
1171                 break;
1172         case DPMSModeOff:
1173                 /* Screen: Off; HSync: Off, VSync: Off */
1174                 seq1 = 0x20;
1175                 crtc17 = 0x00;
1176                 crtc1A |= 0xC0;
1177                 break;
1178         case DPMSModeOn:
1179         default:
1180                 /* Screen: On; HSync: On, VSync: On */
1181                 seq1 = 0x00;
1182                 crtc17 = 0x80;
1183                 break;
1184         }
1185
1186         NVVgaSeqReset(crtc, TRUE);
1187         /* Each head has it's own sequencer, so we can turn it off when we want */
1188         seq1 |= (NVReadVgaSeq(crtc, 0x01) & ~0x20);
1189         NVWriteVgaSeq(crtc, 0x1, seq1);
1190         crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
1191         usleep(10000);
1192         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
1193         NVVgaSeqReset(crtc, FALSE);
1194
1195         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
1196
1197         /* We can completely disable a vpll if the crtc is off. */
1198         if (pNv->Architecture == NV_ARCH_40) {
1199                 uint32_t reg_c040_old = nvReadMC(pNv, 0xc040);
1200                 if (mode == DPMSModeOn) {
1201                         nvWriteMC(pNv, 0xc040, reg_c040_old | (pNv->misc_info.reg_c040 & (0x3 << (16 + 2*nv_crtc->head))));
1202                 } else {
1203                         nvWriteMC(pNv, 0xc040, reg_c040_old & ~(pNv->misc_info.reg_c040 & (0x3 << (16 + 2*nv_crtc->head))));
1204                 }
1205         }
1206
1207         /* I hope this is the right place */
1208         if (crtc->enabled && mode == DPMSModeOn) {
1209                 pNv->crtc_active[nv_crtc->head] = TRUE;
1210         } else {
1211                 pNv->crtc_active[nv_crtc->head] = FALSE;
1212         }
1213 }
1214
1215 static Bool
1216 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
1217                      DisplayModePtr adjusted_mode)
1218 {
1219         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1220         ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->head);
1221
1222         return TRUE;
1223 }
1224
1225 static void
1226 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1227 {
1228         ScrnInfoPtr pScrn = crtc->scrn;
1229         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1230         NVCrtcRegPtr regp;
1231         NVPtr pNv = NVPTR(pScrn);
1232         NVFBLayout *pLayout = &pNv->CurrentLayout;
1233         int depth = pScrn->depth;
1234
1235         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1236
1237         /* Calculate our timings */
1238         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
1239         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
1240         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
1241         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
1242         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
1243         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
1244         int vertDisplay         = mode->CrtcVDisplay                    - 1;
1245         int vertStart           = mode->CrtcVSyncStart          - 1;
1246         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
1247         int vertTotal           = mode->CrtcVTotal                      - 2;
1248         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
1249         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
1250
1251         Bool is_fp = FALSE;
1252
1253         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1254         NVOutputPrivatePtr nv_output = NULL;
1255         if (output) {
1256                 nv_output = output->driver_private;
1257
1258                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1259                         is_fp = TRUE;
1260         }
1261
1262         ErrorF("Mode clock: %d\n", mode->Clock);
1263         ErrorF("Adjusted mode clock: %d\n", adjusted_mode->Clock);
1264
1265         /* Reverted to what nv did, because that works for all resolutions on flatpanels */
1266         if (is_fp) {
1267                 vertStart = vertTotal - 3;
1268                 vertEnd = vertTotal - 2;
1269                 vertBlankStart = vertStart;
1270                 horizStart = horizTotal - 5;
1271                 horizEnd = horizTotal - 2;
1272                 horizBlankEnd = horizTotal + 4;
1273                 if (pNv->overlayAdaptor) {
1274                         /* This reportedly works around Xv some overlay bandwidth problems*/
1275                         horizTotal += 2;
1276                 }
1277         }
1278
1279         if(mode->Flags & V_INTERLACE)
1280                 vertTotal |= 1;
1281
1282         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
1283         ErrorF("horizStart: 0x%X \n", horizStart);
1284         ErrorF("horizEnd: 0x%X \n", horizEnd);
1285         ErrorF("horizTotal: 0x%X \n", horizTotal);
1286         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
1287         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
1288         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
1289         ErrorF("vertStart: 0x%X \n", vertStart);
1290         ErrorF("vertEnd: 0x%X \n", vertEnd);
1291         ErrorF("vertTotal: 0x%X \n", vertTotal);
1292         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
1293         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
1294
1295         /*
1296         * compute correct Hsync & Vsync polarity
1297         */
1298         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
1299                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
1300
1301                 regp->MiscOutReg = 0x23;
1302                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
1303                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
1304         } else {
1305                 int VDisplay = mode->VDisplay;
1306                 if (mode->Flags & V_DBLSCAN)
1307                         VDisplay *= 2;
1308                 if (mode->VScan > 1)
1309                         VDisplay *= mode->VScan;
1310                 if (VDisplay < 400) {
1311                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
1312                 } else if (VDisplay < 480) {
1313                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
1314                 } else if (VDisplay < 768) {
1315                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
1316                 } else {
1317                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
1318                 }
1319         }
1320
1321         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
1322
1323         /*
1324         * Time Sequencer
1325         */
1326         if (depth == 4) {
1327                 regp->Sequencer[0] = 0x02;
1328         } else {
1329                 regp->Sequencer[0] = 0x00;
1330         }
1331         /* 0x20 disables the sequencer */
1332         if (mode->Flags & V_CLKDIV2) {
1333                 regp->Sequencer[1] = 0x29;
1334         } else {
1335                 regp->Sequencer[1] = 0x21;
1336         }
1337         if (depth == 1) {
1338                 regp->Sequencer[2] = 1 << BIT_PLANE;
1339         } else {
1340                 regp->Sequencer[2] = 0x0F;
1341                 regp->Sequencer[3] = 0x00;                     /* Font select */
1342         }
1343         if (depth < 8) {
1344                 regp->Sequencer[4] = 0x06;                             /* Misc */
1345         } else {
1346                 regp->Sequencer[4] = 0x0E;                             /* Misc */
1347         }
1348
1349         /*
1350         * CRTC Controller
1351         */
1352         regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
1353         regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
1354         regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
1355         regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0)
1356                                 | SetBit(7);
1357         regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
1358         regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
1359                                 | SetBitField(horizEnd,4:0,4:0);
1360         regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
1361         regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
1362                                 | SetBitField(vertDisplay,8:8,1:1)
1363                                 | SetBitField(vertStart,8:8,2:2)
1364                                 | SetBitField(vertBlankStart,8:8,3:3)
1365                                 | SetBit(4)
1366                                 | SetBitField(vertTotal,9:9,5:5)
1367                                 | SetBitField(vertDisplay,9:9,6:6)
1368                                 | SetBitField(vertStart,9:9,7:7);
1369         regp->CRTC[NV_VGA_CRTCX_PRROWSCN]  = 0x00;
1370         regp->CRTC[NV_VGA_CRTCX_MAXSCLIN]  = SetBitField(vertBlankStart,9:9,5:5)
1371                                 | SetBit(6)
1372                                 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00);
1373         regp->CRTC[NV_VGA_CRTCX_VGACURCTRL] = 0x00;
1374         regp->CRTC[0xb] = 0x00;
1375         regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00;
1376         regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
1377         regp->CRTC[0xe] = 0x00;
1378         regp->CRTC[0xf] = 0x00;
1379         regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
1380         regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
1381         regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
1382         regp->CRTC[0x14] = 0x00;
1383         regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
1384         regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
1385         regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
1386         /* 0x80 enables the sequencer, we don't want that */
1387         if (depth < 8) {
1388                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xE3 & ~0x80;
1389         } else {
1390                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80;
1391         }
1392         regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
1393
1394         /*
1395          * Some extended CRTC registers (they are not saved with the rest of the vga regs).
1396          */
1397
1398         regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
1399                                 | SetBitField(vertBlankStart,10:10,3:3)
1400                                 | SetBitField(vertStart,10:10,2:2)
1401                                 | SetBitField(vertDisplay,10:10,1:1)
1402                                 | SetBitField(vertTotal,10:10,0:0);
1403
1404         regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
1405                                 | SetBitField(horizDisplay,8:8,1:1)
1406                                 | SetBitField(horizBlankStart,8:8,2:2)
1407                                 | SetBitField(horizStart,8:8,3:3);
1408
1409         regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
1410                                 | SetBitField(vertDisplay,11:11,2:2)
1411                                 | SetBitField(vertStart,11:11,4:4)
1412                                 | SetBitField(vertBlankStart,11:11,6:6);
1413
1414         if(mode->Flags & V_INTERLACE) {
1415                 horizTotal = (horizTotal >> 1) & ~1;
1416                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
1417                 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
1418         } else {
1419                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff;  /* interlace off */
1420         }
1421
1422         /*
1423         * Theory resumes here....
1424         */
1425
1426         /*
1427         * Graphics Display Controller
1428         */
1429         regp->Graphics[0] = 0x00;
1430         regp->Graphics[1] = 0x00;
1431         regp->Graphics[2] = 0x00;
1432         regp->Graphics[3] = 0x00;
1433         if (depth == 1) {
1434                 regp->Graphics[4] = BIT_PLANE;
1435                 regp->Graphics[5] = 0x00;
1436         } else {
1437                 regp->Graphics[4] = 0x00;
1438                 if (depth == 4) {
1439                         regp->Graphics[5] = 0x02;
1440                 } else {
1441                         regp->Graphics[5] = 0x40;
1442                 }
1443         }
1444         regp->Graphics[6] = 0x05;   /* only map 64k VGA memory !!!! */
1445         regp->Graphics[7] = 0x0F;
1446         regp->Graphics[8] = 0xFF;
1447
1448         /* I ditched the mono stuff */
1449         regp->Attribute[0]  = 0x00; /* standard colormap translation */
1450         regp->Attribute[1]  = 0x01;
1451         regp->Attribute[2]  = 0x02;
1452         regp->Attribute[3]  = 0x03;
1453         regp->Attribute[4]  = 0x04;
1454         regp->Attribute[5]  = 0x05;
1455         regp->Attribute[6]  = 0x06;
1456         regp->Attribute[7]  = 0x07;
1457         regp->Attribute[8]  = 0x08;
1458         regp->Attribute[9]  = 0x09;
1459         regp->Attribute[10] = 0x0A;
1460         regp->Attribute[11] = 0x0B;
1461         regp->Attribute[12] = 0x0C;
1462         regp->Attribute[13] = 0x0D;
1463         regp->Attribute[14] = 0x0E;
1464         regp->Attribute[15] = 0x0F;
1465         /* These two below are non-vga */
1466         regp->Attribute[16] = 0x01;
1467         regp->Attribute[17] = 0x00;
1468         regp->Attribute[18] = 0x0F;
1469         regp->Attribute[19] = 0x00;
1470         regp->Attribute[20] = 0x00;
1471 }
1472
1473 #define MAX_H_VALUE(i) ((0x1ff + i) << 3)
1474 #define MAX_V_VALUE(i) ((0xfff + i) << 0)
1475
1476 /**
1477  * Sets up registers for the given mode/adjusted_mode pair.
1478  *
1479  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1480  *
1481  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1482  * be easily turned on/off after this.
1483  */
1484 static void
1485 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1486 {
1487         ScrnInfoPtr pScrn = crtc->scrn;
1488         NVPtr pNv = NVPTR(pScrn);
1489         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1490         NVFBLayout *pLayout = &pNv->CurrentLayout;
1491         NVCrtcRegPtr regp, savep;
1492         unsigned int i;
1493         Bool is_fp = FALSE;
1494         Bool is_lvds = FALSE;
1495
1496         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1497         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1498
1499         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1500         NVOutputPrivatePtr nv_output = NULL;
1501         if (output) {
1502                 nv_output = output->driver_private;
1503
1504                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1505                         is_fp = TRUE;
1506
1507                 if (nv_output->type == OUTPUT_LVDS)
1508                         is_lvds = TRUE;
1509         }
1510
1511         /* Registers not directly related to the (s)vga mode */
1512
1513         /* bit2 = 0 -> fine pitched crtc granularity */
1514         /* The rest disables double buffering on CRTC access */
1515         regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
1516
1517         if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
1518                 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1519                 if (nv_crtc->head == 0) {
1520                         regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1521                 }
1522
1523                 if (is_fp) {
1524                         regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0) | (1 << 1);
1525                 }
1526         } else {
1527                 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
1528                 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
1529         }
1530
1531         /* Sometimes 0x10 is used, what is this? */
1532         regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1533         /* Some kind of tmds switch for older cards */
1534         if (pNv->Architecture < NV_ARCH_40) {
1535                 regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
1536         }
1537
1538         /*
1539         * Initialize DAC palette.
1540         * Will only be written when depth != 8.
1541         */
1542         for (i = 0; i < 256; i++) {
1543                 regp->DAC[i*3] = i;
1544                 regp->DAC[(i*3)+1] = i;
1545                 regp->DAC[(i*3)+2] = i;
1546         }
1547
1548         /*
1549         * Calculate the extended registers.
1550         */
1551
1552         if(pLayout->depth < 24) {
1553                 i = pLayout->depth;
1554         } else {
1555                 i = 32;
1556         }
1557
1558         /* What is the meaning of this register? */
1559         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1560         regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
1561
1562         /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1563         /* But what are those special conditions? */
1564         if (pNv->Architecture <= NV_ARCH_30) {
1565                 if (is_fp) {
1566                         if(nv_crtc->head == 1) {
1567                                 regp->head |= NV_CRTC_FSEL_FPP1;
1568                         } else if (pNv->twoHeads) {
1569                                 regp->head |= NV_CRTC_FSEL_FPP2;
1570                         }
1571                 }
1572         } else {
1573                 /* Most G70 cards have FPP2 set on the secondary CRTC. */
1574                 if (nv_crtc->head == 1 && pNv->NVArch > 0x44) {
1575                         regp->head |= NV_CRTC_FSEL_FPP2;
1576                 }
1577         }
1578
1579         /* Except for rare conditions I2C is enabled on the primary crtc */
1580         if (nv_crtc->head == 0) {
1581                 if (pNv->overlayAdaptor) {
1582                         regp->head |= NV_CRTC_FSEL_OVERLAY;
1583                 }
1584                 regp->head |= NV_CRTC_FSEL_I2C;
1585         }
1586
1587         /* This is not what nv does, but it is what the blob does (for nv4x at least) */
1588         /* This fixes my cursor corruption issue */
1589         regp->cursorConfig = 0x0;
1590         if(mode->Flags & V_DBLSCAN)
1591                 regp->cursorConfig |= (1 << 4);
1592         if (pNv->alphaCursor) {
1593                 /* bit28 means we go into alpha blend mode and not rely on the current ROP */
1594                 regp->cursorConfig |= 0x14011000;
1595         } else {
1596                 regp->cursorConfig |= 0x02000000;
1597         }
1598
1599         /* Unblock some timings */
1600         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1601         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1602
1603         /* What is the purpose of this register? */
1604         /* 0x14 may be disabled? */
1605         regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1606
1607         /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
1608         if (is_lvds) {
1609                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x11;
1610         } else if (is_fp) {
1611                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1612         } else {
1613                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1614         }
1615
1616         /* These values seem to vary */
1617         /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
1618         regp->CRTC[NV_VGA_CRTCX_3C] = savep->CRTC[NV_VGA_CRTCX_3C];
1619
1620         /* 0x80 seems to be used very often, if not always */
1621         regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1622
1623         /* Some cards have 0x41 instead of 0x1 (for crtc 0), it doesn't hurt to just use the old value. */
1624         regp->CRTC[NV_VGA_CRTCX_4B] = savep->CRTC[NV_VGA_CRTCX_4B];
1625
1626         if (is_fp)
1627                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x80;
1628
1629         /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1*/
1630         if (nv_crtc->head == 1) {
1631                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52;
1632         } else {
1633                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52 + 4;
1634         }
1635
1636         /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1637         regp->unk81c = nvReadCRTC0(pNv, NV_CRTC_081C);
1638
1639         regp->unk830 = mode->CrtcVDisplay - 3;
1640         regp->unk834 = mode->CrtcVDisplay - 1;
1641
1642         /* This is what the blob does */
1643         regp->unk850 = nvReadCRTC(pNv, 0, NV_CRTC_0850);
1644
1645         /* Never ever modify gpio, unless you know very well what you're doing */
1646         regp->gpio = nvReadCRTC(pNv, 0, NV_CRTC_GPIO);
1647
1648         /* Switch to non-vga mode (the so called HSYNC mode) */
1649         regp->config = 0x2;
1650
1651         /* Some misc regs */
1652         regp->CRTC[NV_VGA_CRTCX_43] = 0x1;
1653         if (pNv->Architecture == NV_ARCH_40) {
1654                 regp->CRTC[NV_VGA_CRTCX_85] = 0xFF;
1655                 regp->CRTC[NV_VGA_CRTCX_86] = 0x1;
1656         }
1657
1658         /*
1659          * Calculate the state that is common to all crtc's (stored in the state struct).
1660          */
1661         ErrorF("crtc %d %d %d\n", nv_crtc->head, mode->CrtcHDisplay, pScrn->displayWidth);
1662         nv_crtc_calc_state_ext(crtc,
1663                                 i,
1664                                 pScrn->displayWidth,
1665                                 mode->CrtcHDisplay,
1666                                 mode->CrtcVDisplay,
1667                                 adjusted_mode->Clock,
1668                                 mode->Flags);
1669
1670         /* Enable slaved mode */
1671         if (is_fp) {
1672                 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1673         }
1674 }
1675
1676 static void
1677 nv_crtc_mode_set_ramdac_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1678 {
1679         ScrnInfoPtr pScrn = crtc->scrn;
1680         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1681         NVCrtcRegPtr regp, savep;
1682         NVPtr pNv = NVPTR(pScrn);
1683         NVFBLayout *pLayout = &pNv->CurrentLayout;
1684         Bool is_fp = FALSE;
1685         Bool is_lvds = FALSE;
1686         float aspect_ratio, panel_ratio;
1687         uint32_t h_scale, v_scale;
1688
1689         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1690         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1691
1692         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1693         NVOutputPrivatePtr nv_output = NULL;
1694         if (output) {
1695                 nv_output = output->driver_private;
1696
1697                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1698                         is_fp = TRUE;
1699
1700                 if (nv_output->type == OUTPUT_LVDS)
1701                         is_lvds = TRUE;
1702         }
1703
1704         if (is_fp) {
1705                 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
1706                 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
1707                 /* This is what the blob does. */
1708                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HSyncStart - 75 - 1;
1709                 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
1710                 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
1711                 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
1712                 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
1713
1714                 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
1715                 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
1716                 /* This is what the blob does. */
1717                 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VTotal - 5 - 1;
1718                 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
1719                 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
1720                 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
1721                 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
1722
1723                 /* Quirks, maybe move them somewere else? */
1724                 if (is_lvds) {
1725                         switch(pNv->NVArch) {
1726                                 case 0x46: /* 7300GO */
1727                                         /* Only native mode needed, is there some logic to this? */
1728                                         if (mode->HDisplay == 1280 && mode->VDisplay == 800) {
1729                                                 regp->fp_horiz_regs[REG_DISP_CRTC] = 0x4c6;
1730                                         }
1731                                         break;
1732                                 default:
1733                                         break;
1734                         }
1735                 }
1736
1737                 ErrorF("Horizontal:\n");
1738                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
1739                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
1740                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
1741                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
1742                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
1743                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
1744                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
1745
1746                 ErrorF("Vertical:\n");
1747                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
1748                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
1749                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
1750                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
1751                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
1752                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
1753                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
1754         }
1755
1756         /*
1757         * bit0: positive vsync
1758         * bit4: positive hsync
1759         * bit8: enable center mode
1760         * bit9: enable native mode
1761         * bit26: a bit sometimes seen on some g70 cards
1762         * bit31: set for dual link LVDS
1763         * nv10reg contains a few more things, but i don't quite get what it all means.
1764         */
1765
1766         if (pNv->Architecture >= NV_ARCH_30) {
1767                 regp->fp_control = 0x01100000;
1768         } else {
1769                 regp->fp_control = 0x00000000;
1770         }
1771
1772         if (is_fp) {
1773                 regp->fp_control |= (1 << 28);
1774         } else {
1775                 regp->fp_control |= (2 << 28);
1776                 if (pNv->Architecture < NV_ARCH_30)
1777                         regp->fp_control |= (1 << 24);
1778         }
1779
1780         /* Some 7300GO cards get a quad view if this bit is set, even though they are duallink. */
1781         /* This was seen on 2 cards. */
1782         if (is_lvds && pNv->VBIOS.fp.dual_link && pNv->NVArch != 0x46) {
1783                 regp->fp_control |= (8 << 28);
1784         }
1785
1786         /* If the special bit exists, it exists on both ramdac's */
1787         regp->fp_control |= nvReadRAMDAC0(pNv, NV_RAMDAC_FP_CONTROL) & (1 << 26);
1788
1789         if (is_fp) {
1790                 if (nv_output->scaling_mode == SCALE_PANEL) { /* panel needs to scale */
1791                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
1792                 /* This is also true for panel scaling, so we must put the panel scale check first */
1793                 } else if (mode->Clock == adjusted_mode->Clock) { /* native mode */
1794                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
1795                 } else { /* gpu needs to scale */
1796                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1797                 }
1798         }
1799
1800         /* Deal with vsync/hsync polarity */
1801         /* LVDS screens don't set this. */
1802         if (is_fp && !is_lvds) {
1803                 if (adjusted_mode->Flags & V_PVSYNC) {
1804                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
1805                 }
1806
1807                 if (adjusted_mode->Flags & V_PHSYNC) {
1808                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
1809                 }
1810         } else if (!is_lvds) {
1811                 /* The blob doesn't always do this, but often */
1812                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_VSYNC_DISABLE;
1813                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_HSYNC_DISABLE;
1814         }
1815
1816         if (is_fp) {
1817                 ErrorF("Pre-panel scaling\n");
1818                 ErrorF("panel-size:%dx%d\n", nv_output->fpWidth, nv_output->fpHeight);
1819                 panel_ratio = (nv_output->fpWidth)/(float)(nv_output->fpHeight);
1820                 ErrorF("panel_ratio=%f\n", panel_ratio);
1821                 aspect_ratio = (mode->HDisplay)/(float)(mode->VDisplay);
1822                 ErrorF("aspect_ratio=%f\n", aspect_ratio);
1823                 /* Scale factors is the so called 20.12 format, taken from Haiku */
1824                 h_scale = ((1 << 12) * mode->HDisplay)/nv_output->fpWidth;
1825                 v_scale = ((1 << 12) * mode->VDisplay)/nv_output->fpHeight;
1826                 ErrorF("h_scale=%d\n", h_scale);
1827                 ErrorF("v_scale=%d\n", v_scale);
1828
1829                 /* This can override HTOTAL and VTOTAL */
1830                 regp->debug_2 = 0;
1831
1832                 /* We want automatic scaling */
1833                 regp->debug_1 = 0;
1834
1835                 regp->fp_hvalid_start = 0;
1836                 regp->fp_hvalid_end = (nv_output->fpWidth - 1);
1837
1838                 regp->fp_vvalid_start = 0;
1839                 regp->fp_vvalid_end = (nv_output->fpHeight - 1);
1840
1841                 /* 0 = panel scaling */
1842                 if (nv_output->scaling_mode == SCALE_PANEL) {
1843                         ErrorF("Flat panel is doing the scaling.\n");
1844                 } else {
1845                         ErrorF("GPU is doing the scaling.\n");
1846
1847                         if (nv_output->scaling_mode == SCALE_ASPECT) {
1848                                 /* GPU scaling happens automaticly at a ratio of 1.33 */
1849                                 /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
1850                                 if (h_scale != (1 << 12) && (panel_ratio > (aspect_ratio + 0.10))) {
1851                                         uint32_t diff;
1852
1853                                         ErrorF("Scaling resolution on a widescreen panel\n");
1854
1855                                         /* Scaling in both directions needs to the same */
1856                                         h_scale = v_scale;
1857
1858                                         /* Set a new horizontal scale factor and enable testmode (bit12) */
1859                                         regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
1860
1861                                         diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
1862                                         regp->fp_hvalid_start = diff/2;
1863                                         regp->fp_hvalid_end = nv_output->fpWidth - (diff/2) - 1;
1864                                 }
1865
1866                                 /* Same scaling, just for panels with aspect ratio's smaller than 1 */
1867                                 if (v_scale != (1 << 12) && (panel_ratio < (aspect_ratio - 0.10))) {
1868                                         uint32_t diff;
1869
1870                                         ErrorF("Scaling resolution on a portrait panel\n");
1871
1872                                         /* Scaling in both directions needs to the same */
1873                                         v_scale = h_scale;
1874
1875                                         /* Set a new vertical scale factor and enable testmode (bit28) */
1876                                         regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
1877
1878                                         diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
1879                                         regp->fp_vvalid_start = diff/2;
1880                                         regp->fp_vvalid_end = nv_output->fpHeight - (diff/2) - 1;
1881                                 }
1882                         }
1883                 }
1884
1885                 ErrorF("Post-panel scaling\n");
1886         }
1887
1888         if (pNv->Architecture >= NV_ARCH_10) {
1889                 /* Bios and blob don't seem to do anything (else) */
1890                 regp->nv10_cursync = (1<<25);
1891         }
1892
1893         /* These are the common blob values, minus a few fp specific bit's */
1894         /* Let's keep the TMDS pll and fpclock running in all situations */
1895         regp->debug_0 = 0x1101100;
1896
1897         if (is_fp && nv_output->scaling_mode != SCALE_NOSCALE) {
1898                 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_XSCALE_ENABLED;
1899                 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_YSCALE_ENABLED;
1900         } else if (is_fp) { /* no_scale mode, so we must center it */
1901                 uint32_t diff;
1902
1903                 diff = nv_output->fpWidth - mode->HDisplay;
1904                 regp->fp_hvalid_start = diff/2;
1905                 regp->fp_hvalid_end = (nv_output->fpWidth - diff/2 - 1);
1906
1907                 diff = nv_output->fpHeight - mode->VDisplay;
1908                 regp->fp_vvalid_start = diff/2;
1909                 regp->fp_vvalid_end = (nv_output->fpHeight - diff/2 - 1);
1910         }
1911
1912         /* Is this crtc bound or output bound? */
1913         /* Does the bios TMDS script try to change this sometimes? */
1914         if (is_fp) {
1915                 /* I am not completely certain, but seems to be set only for dfp's */
1916                 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED;
1917         }
1918
1919         if (output)
1920                 ErrorF("output %d debug_0 %08X\n", nv_output->output_resource, regp->debug_0);
1921
1922         /* Flatpanel support needs at least a NV10 */
1923         if (pNv->twoHeads) {
1924                 /* The blob does this differently. */
1925                 /* TODO: Find out what precisely and why. */
1926                 /* Let's not destroy any bits that were already present. */
1927                 if (pNv->FPDither || (is_lvds && pNv->VBIOS.fp.if_is_18bit)) {
1928                         if (pNv->NVArch == 0x11) {
1929                                 regp->dither = savep->dither | 0x00010000;
1930                         } else {
1931                                 regp->dither = savep->dither | 0x00000001;
1932                         }
1933                 } else {
1934                         regp->dither = savep->dither;
1935                 }
1936         }
1937
1938         /* Kindly borrowed from haiku driver */
1939         /* bit4 and bit5 activate indirect mode trough color palette */
1940         switch (pLayout->depth) {
1941                 case 32:
1942                 case 16:
1943                         regp->general = 0x00101130;
1944                         break;
1945                 case 24:
1946                 case 15:
1947                         regp->general = 0x00100130;
1948                         break;
1949                 case 8:
1950                 default:
1951                         regp->general = 0x00101100;
1952                         break;
1953         }
1954
1955         if (pNv->alphaCursor) {
1956                 /* PIPE_LONG mode, something to do with the size of the cursor? */
1957                 regp->general |= (1<<29);
1958         }
1959
1960         /* Some values the blob sets */
1961         /* This may apply to the real ramdac that is being used (for crosswired situations) */
1962         /* Nevertheless, it's unlikely to cause many problems, since the values are equal for both */
1963         regp->unk_a20 = 0x0;
1964         regp->unk_a24 = 0xfffff;
1965         regp->unk_a34 = 0x1;
1966 }
1967
1968 /**
1969  * Sets up registers for the given mode/adjusted_mode pair.
1970  *
1971  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1972  *
1973  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1974  * be easily turned on/off after this.
1975  */
1976 static void
1977 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
1978                  DisplayModePtr adjusted_mode,
1979                  int x, int y)
1980 {
1981         ScrnInfoPtr pScrn = crtc->scrn;
1982         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1983         NVPtr pNv = NVPTR(pScrn);
1984         NVFBLayout *pLayout = &pNv->CurrentLayout;
1985
1986         ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->head);
1987
1988         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->head);
1989         xf86PrintModeline(pScrn->scrnIndex, mode);
1990         NVCrtcSetOwner(crtc);
1991
1992         nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
1993         nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
1994         nv_crtc_mode_set_ramdac_regs(crtc, mode, adjusted_mode);
1995
1996         NVVgaProtect(crtc, TRUE);
1997         nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
1998         nv_crtc_load_state_ext(crtc, &pNv->ModeReg, FALSE);
1999         if (pLayout->depth != 8)
2000                 NVCrtcLoadPalette(crtc);
2001         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
2002         if (pNv->Architecture == NV_ARCH_40) {
2003                 nv40_crtc_load_state_pll(crtc, &pNv->ModeReg);
2004         } else {
2005                 nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
2006         }
2007
2008         NVVgaProtect(crtc, FALSE);
2009
2010         NVCrtcSetBase(crtc, x, y);
2011
2012 #if X_BYTE_ORDER == X_BIG_ENDIAN
2013         /* turn on LFB swapping */
2014         {
2015                 unsigned char tmp;
2016
2017                 tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
2018                 tmp |= (1 << 7);
2019                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
2020         }
2021 #endif
2022 }
2023
2024 /* This functions generates data that is not saved, but still is needed. */
2025 void nv_crtc_restore_generate(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2026 {
2027         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2028         int i;
2029         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
2030
2031         /* It's a good idea to also save a default palette on shutdown. */
2032         for (i = 0; i < 256; i++) {
2033                 regp->DAC[i*3] = i;
2034                 regp->DAC[(i*3)+1] = i;
2035                 regp->DAC[(i*3)+2] = i;
2036         }
2037 }
2038
2039 void nv_crtc_save(xf86CrtcPtr crtc)
2040 {
2041         ScrnInfoPtr pScrn = crtc->scrn;
2042         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2043         NVPtr pNv = NVPTR(pScrn);
2044
2045         ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->head);
2046
2047         /* We just came back from terminal, so unlock */
2048         NVCrtcLockUnlock(crtc, FALSE);
2049
2050         NVCrtcSetOwner(crtc);
2051         nv_crtc_restore_generate(crtc, &pNv->SavedReg);
2052         nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
2053         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
2054         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
2055         if (pNv->Architecture == NV_ARCH_40) {
2056                 nv40_crtc_save_state_pll(pNv, &pNv->SavedReg);
2057         } else {
2058                 nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
2059         }
2060 }
2061
2062 void nv_crtc_restore(xf86CrtcPtr crtc)
2063 {
2064         ScrnInfoPtr pScrn = crtc->scrn;
2065         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2066         NVPtr pNv = NVPTR(pScrn);
2067         RIVA_HW_STATE *state;
2068         NVCrtcRegPtr savep;
2069
2070         state = &pNv->SavedReg;
2071         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
2072
2073         ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->head);
2074
2075         NVCrtcSetOwner(crtc);
2076
2077         /* Just to be safe */
2078         NVCrtcLockUnlock(crtc, FALSE);
2079
2080         NVVgaProtect(crtc, TRUE);
2081         nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
2082         nv_crtc_load_state_ext(crtc, &pNv->SavedReg, TRUE);
2083         if (savep->general & 0x30) /* Palette mode */
2084                 NVCrtcLoadPalette(crtc);
2085         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
2086
2087         /* Force restoring pll's. */
2088         state->vpll_changed[0] = TRUE;
2089         state->vpll_changed[1] = TRUE;
2090
2091         if (pNv->Architecture == NV_ARCH_40) {
2092                 nv40_crtc_load_state_pll(crtc, &pNv->SavedReg);
2093         } else {
2094                 nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
2095         }
2096         nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->vtOWNER);
2097         NVVgaProtect(crtc, FALSE);
2098 }
2099
2100 void
2101 NVResetCrtcConfig(xf86CrtcPtr crtc, Bool set)
2102 {
2103         ScrnInfoPtr pScrn = crtc->scrn;
2104         NVPtr pNv = NVPTR(pScrn);
2105         uint32_t val = 0;
2106
2107         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2108
2109         if (set) {
2110                 NVCrtcRegPtr regp;
2111
2112                 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2113                 val = regp->head;
2114         }
2115
2116         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL, val);
2117 }
2118
2119 void nv_crtc_prepare(xf86CrtcPtr crtc)
2120 {
2121         ScrnInfoPtr pScrn = crtc->scrn;
2122         NVPtr pNv = NVPTR(pScrn);
2123         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2124
2125         ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->head);
2126
2127         /* Just in case */
2128         NVCrtcLockUnlock(crtc, 0);
2129
2130         NVResetCrtcConfig(crtc, FALSE);
2131
2132         crtc->funcs->dpms(crtc, DPMSModeOff);
2133
2134         /* Sync the engine before adjust mode */
2135         if (pNv->EXADriverPtr) {
2136                 exaMarkSync(pScrn->pScreen);
2137                 exaWaitSync(pScrn->pScreen);
2138         }
2139
2140         NVCrtcBlankScreen(crtc, FALSE); /* Blank screen */
2141
2142         /* Some more preperation. */
2143         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG, 0x1); /* Go to non-vga mode/out of enhanced mode */
2144         uint32_t reg900 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900);
2145         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 & ~0x10000);
2146         /* Set FP_CONTROL to a neutral mode, (almost) off i believe. */
2147         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, 0x21100222);
2148
2149         usleep(5000); /* Give it some time to settle */
2150 }
2151
2152 void nv_crtc_commit(xf86CrtcPtr crtc)
2153 {
2154         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2155         ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->head);
2156
2157         crtc->funcs->dpms (crtc, DPMSModeOn);
2158
2159         if (crtc->scrn->pScreen != NULL)
2160                 xf86_reload_cursors (crtc->scrn->pScreen);
2161
2162         NVResetCrtcConfig(crtc, TRUE);
2163 }
2164
2165 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
2166 {
2167         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2168         ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->head);
2169
2170         return FALSE;
2171 }
2172
2173 static void nv_crtc_unlock(xf86CrtcPtr crtc)
2174 {
2175         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2176         ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->head);
2177 }
2178
2179 static void
2180 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
2181                                         int size)
2182 {
2183         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2184         ScrnInfoPtr pScrn = crtc->scrn;
2185         NVPtr pNv = NVPTR(pScrn);
2186         int i, j;
2187
2188         NVCrtcRegPtr regp;
2189         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2190
2191         switch (pNv->CurrentLayout.depth) {
2192         case 15:
2193                 /* R5G5B5 */
2194                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
2195                 for (i = 0; i < 32; i++) {
2196                         for (j = 0; j < 8; j++) {
2197                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2198                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
2199                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2200                         }
2201                 }
2202                 break;
2203         case 16:
2204                 /* R5G6B5 */
2205                 /* First deal with the 5 bit colors */
2206                 for (i = 0; i < 32; i++) {
2207                         for (j = 0; j < 8; j++) {
2208                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2209                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2210                         }
2211                 }
2212                 /* Now deal with the 6 bit color */
2213                 for (i = 0; i < 64; i++) {
2214                         for (j = 0; j < 4; j++) {
2215                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
2216                         }
2217                 }
2218                 break;
2219         default:
2220                 /* R8G8B8 */
2221                 for (i = 0; i < 256; i++) {
2222                         regp->DAC[i * 3] = red[i] >> 8;
2223                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
2224                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
2225                 }
2226                 break;
2227         }
2228
2229         NVCrtcLoadPalette(crtc);
2230 }
2231
2232 /**
2233  * Allocates memory for a locked-in-framebuffer shadow of the given
2234  * width and height for this CRTC's rotated shadow framebuffer.
2235  */
2236
2237 static void *
2238 nv_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
2239 {
2240         ErrorF("nv_crtc_shadow_allocate is called\n");
2241         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2242         ScrnInfoPtr pScrn = crtc->scrn;
2243 #if !NOUVEAU_EXA_PIXMAPS
2244         ScreenPtr pScreen = pScrn->pScreen;
2245 #endif /* !NOUVEAU_EXA_PIXMAPS */
2246         NVPtr pNv = NVPTR(pScrn);
2247         void *offset;
2248
2249         unsigned long rotate_pitch;
2250         int size, align = 64;
2251
2252         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2253         size = rotate_pitch * height;
2254
2255         assert(nv_crtc->shadow == NULL);
2256 #if NOUVEAU_EXA_PIXMAPS
2257         if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN,
2258                         align, size, &nv_crtc->shadow)) {
2259                 ErrorF("Failed to allocate memory for shadow buffer!\n");
2260                 return NULL;
2261         }
2262
2263         if (nv_crtc->shadow && nouveau_bo_map(nv_crtc->shadow, NOUVEAU_BO_RDWR)) {
2264                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2265                                 "Failed to map shadow buffer.\n");
2266                 return NULL;
2267         }
2268
2269         offset = nv_crtc->shadow->map;
2270 #else
2271         nv_crtc->shadow = exaOffscreenAlloc(pScreen, size, align, TRUE, NULL, NULL);
2272         if (nv_crtc->shadow == NULL) {
2273                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2274                         "Couldn't allocate shadow memory for rotated CRTC\n");
2275                 return NULL;
2276         }
2277         offset = pNv->FB->map + nv_crtc->shadow->offset;
2278 #endif /* NOUVEAU_EXA_PIXMAPS */
2279
2280         return offset;
2281 }
2282
2283 /**
2284  * Creates a pixmap for this CRTC's rotated shadow framebuffer.
2285  */
2286 static PixmapPtr
2287 nv_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
2288 {
2289         ErrorF("nv_crtc_shadow_create is called\n");
2290         ScrnInfoPtr pScrn = crtc->scrn;
2291 #if NOUVEAU_EXA_PIXMAPS
2292         ScreenPtr pScreen = pScrn->pScreen;
2293         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2294 #endif /* NOUVEAU_EXA_PIXMAPS */
2295         unsigned long rotate_pitch;
2296         PixmapPtr rotate_pixmap;
2297 #if NOUVEAU_EXA_PIXMAPS
2298         struct nouveau_pixmap *nvpix;
2299 #endif /* NOUVEAU_EXA_PIXMAPS */
2300
2301         if (!data)
2302                 data = crtc->funcs->shadow_allocate (crtc, width, height);
2303
2304         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2305
2306 #if NOUVEAU_EXA_PIXMAPS
2307         /* Create a dummy pixmap, to get a private that will be accepted by the system.*/
2308         rotate_pixmap = pScreen->CreatePixmap(pScreen,
2309                                                                 0, /* width */
2310                                                                 0, /* height */
2311         #ifdef CREATE_PIXMAP_USAGE_SCRATCH /* there seems to have been no api bump */
2312                                                                 pScrn->depth,
2313                                                                 0);
2314         #else
2315                                                                 pScrn->depth);
2316         #endif /* CREATE_PIXMAP_USAGE_SCRATCH */
2317 #else
2318         rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen,
2319                                                                 width, height,
2320                                                                 pScrn->depth,
2321                                                                 pScrn->bitsPerPixel,
2322                                                                 rotate_pitch,
2323                                                                 data);
2324 #endif /* NOUVEAU_EXA_PIXMAPS */
2325
2326         if (rotate_pixmap == NULL) {
2327                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2328                         "Couldn't allocate shadow pixmap for rotated CRTC\n");
2329         }
2330
2331 #if NOUVEAU_EXA_PIXMAPS
2332         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2333         if (!nvpix) {
2334                 ErrorF("No shadow private, stage 1\n");
2335         } else {
2336                 nvpix->bo = nv_crtc->shadow;
2337                 nvpix->mapped = TRUE;
2338         }
2339
2340         /* Modify the pixmap to actually be the one we need. */
2341         pScreen->ModifyPixmapHeader(rotate_pixmap,
2342                                         width,
2343                                         height,
2344                                         pScrn->depth,
2345                                         pScrn->bitsPerPixel,
2346                                         rotate_pitch,
2347                                         data);
2348
2349         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2350         if (!nvpix || !nvpix->bo)
2351                 ErrorF("No shadow private, stage 2\n");
2352 #endif /* NOUVEAU_EXA_PIXMAPS */
2353
2354         return rotate_pixmap;
2355 }
2356
2357 static void
2358 nv_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
2359 {
2360         ErrorF("nv_crtc_shadow_destroy is called\n");
2361         ScrnInfoPtr pScrn = crtc->scrn;
2362         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2363         ScreenPtr pScreen = pScrn->pScreen;
2364
2365         if (rotate_pixmap) { /* This should also unmap the buffer object if relevant. */
2366                 pScreen->DestroyPixmap(rotate_pixmap);
2367         }
2368
2369 #if !NOUVEAU_EXA_PIXMAPS
2370         if (data && nv_crtc->shadow) {
2371                 exaOffscreenFree(pScreen, nv_crtc->shadow);
2372         }
2373 #endif /* !NOUVEAU_EXA_PIXMAPS */
2374
2375         nv_crtc->shadow = NULL;
2376 }
2377
2378 /* NV04-NV10 doesn't support alpha cursors */
2379 static const xf86CrtcFuncsRec nv_crtc_funcs = {
2380         .dpms = nv_crtc_dpms,
2381         .save = nv_crtc_save, /* XXX */
2382         .restore = nv_crtc_restore, /* XXX */
2383         .mode_fixup = nv_crtc_mode_fixup,
2384         .mode_set = nv_crtc_mode_set,
2385         .prepare = nv_crtc_prepare,
2386         .commit = nv_crtc_commit,
2387         .destroy = NULL, /* XXX */
2388         .lock = nv_crtc_lock,
2389         .unlock = nv_crtc_unlock,
2390         .set_cursor_colors = nv_crtc_set_cursor_colors,
2391         .set_cursor_position = nv_crtc_set_cursor_position,
2392         .show_cursor = nv_crtc_show_cursor,
2393         .hide_cursor = nv_crtc_hide_cursor,
2394         .load_cursor_image = nv_crtc_load_cursor_image,
2395         .gamma_set = nv_crtc_gamma_set,
2396         .shadow_create = nv_crtc_shadow_create,
2397         .shadow_allocate = nv_crtc_shadow_allocate,
2398         .shadow_destroy = nv_crtc_shadow_destroy,
2399 };
2400
2401 /* NV11 and up has support for alpha cursors. */
2402 /* Due to different maximum sizes we cannot allow it to use normal cursors */
2403 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
2404         .dpms = nv_crtc_dpms,
2405         .save = nv_crtc_save, /* XXX */
2406         .restore = nv_crtc_restore, /* XXX */
2407         .mode_fixup = nv_crtc_mode_fixup,
2408         .mode_set = nv_crtc_mode_set,
2409         .prepare = nv_crtc_prepare,
2410         .commit = nv_crtc_commit,
2411         .destroy = NULL, /* XXX */
2412         .lock = nv_crtc_lock,
2413         .unlock = nv_crtc_unlock,
2414         .set_cursor_colors = NULL, /* Alpha cursors do not need this */
2415         .set_cursor_position = nv_crtc_set_cursor_position,
2416         .show_cursor = nv_crtc_show_cursor,
2417         .hide_cursor = nv_crtc_hide_cursor,
2418         .load_cursor_argb = nv_crtc_load_cursor_argb,
2419         .gamma_set = nv_crtc_gamma_set,
2420         .shadow_create = nv_crtc_shadow_create,
2421         .shadow_allocate = nv_crtc_shadow_allocate,
2422         .shadow_destroy = nv_crtc_shadow_destroy,
2423 };
2424
2425
2426 void
2427 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
2428 {
2429         NVPtr pNv = NVPTR(pScrn);
2430         xf86CrtcPtr crtc;
2431         NVCrtcPrivatePtr nv_crtc;
2432
2433         if (pNv->NVArch >= 0x11) {
2434                 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
2435         } else {
2436                 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
2437         }
2438         if (crtc == NULL)
2439                 return;
2440
2441         nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
2442         nv_crtc->head = crtc_num;
2443
2444         crtc->driver_private = nv_crtc;
2445
2446         NVCrtcLockUnlock(crtc, FALSE);
2447 }
2448
2449 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2450 {
2451         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2452         int i;
2453         NVCrtcRegPtr regp;
2454
2455         regp = &state->crtc_reg[nv_crtc->head];
2456
2457         NVWriteMiscOut(crtc, regp->MiscOutReg);
2458
2459         for (i = 1; i < 5; i++)
2460                 NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
2461
2462         /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
2463         NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
2464
2465         for (i = 0; i < 25; i++)
2466                 NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
2467
2468         for (i = 0; i < 9; i++)
2469                 NVWriteVgaGr(crtc, i, regp->Graphics[i]);
2470
2471         NVEnablePalette(crtc);
2472         for (i = 0; i < 21; i++)
2473                 NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
2474
2475         NVDisablePalette(crtc);
2476 }
2477
2478 static void nv_crtc_fix_nv40_hw_cursor(xf86CrtcPtr crtc)
2479 {
2480         /* TODO - implement this properly */
2481         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2482         ScrnInfoPtr pScrn = crtc->scrn;
2483         NVPtr pNv = NVPTR(pScrn);
2484
2485         if (pNv->Architecture == NV_ARCH_40) {  /* HW bug */
2486                 volatile uint32_t curpos = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS);
2487                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS, curpos);
2488         }
2489 }
2490 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override)
2491 {
2492         ScrnInfoPtr pScrn = crtc->scrn;
2493         NVPtr pNv = NVPTR(pScrn);
2494         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2495         NVCrtcRegPtr regp;
2496         int i;
2497
2498         regp = &state->crtc_reg[nv_crtc->head];
2499
2500         /* If we ever get down to pre-nv10 cards, then we must reinstate some limits. */
2501         nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
2502         nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
2503         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
2504         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
2505         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2506         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2507         nvWriteMC(pNv, 0x1588, 0);
2508
2509         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
2510         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
2511         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO, regp->gpio);
2512         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0830, regp->unk830);
2513         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0834, regp->unk834);
2514         if (pNv->Architecture == NV_ARCH_40) {
2515                 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0850, regp->unk850);
2516                 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_081C, regp->unk81c);
2517         }
2518
2519         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG, regp->config);
2520         uint32_t reg900 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900);
2521         if (pNv->Architecture == NV_ARCH_40) {
2522                 if (regp->config == 0x2) { /* enhanced "horizontal only" non-vga mode */
2523                         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 | 0x10000);
2524                 } else {
2525                         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 & ~0x10000);
2526                 }
2527         }
2528
2529         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
2530         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
2531
2532         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
2533         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
2534         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3C, regp->CRTC[NV_VGA_CRTCX_3C]);
2535         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
2536         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_4B, regp->CRTC[NV_VGA_CRTCX_4B]);
2537         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
2538         if (override) {
2539                 for (i = 0; i < 0x10; i++)
2540                         NVWriteVGACR5758(pNv, nv_crtc->head, i, regp->CR58[i]);
2541         }
2542         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
2543         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
2544
2545         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
2546         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
2547         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
2548         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
2549         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
2550         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
2551         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
2552         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
2553         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
2554         if (pNv->Architecture >= NV_ARCH_30) {
2555                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
2556         }
2557
2558         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_43, regp->CRTC[NV_VGA_CRTCX_43]);
2559         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_85, regp->CRTC[NV_VGA_CRTCX_85]);
2560         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_86, regp->CRTC[NV_VGA_CRTCX_86]);
2561
2562         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
2563         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
2564         nv_crtc_fix_nv40_hw_cursor(crtc);
2565         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
2566         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
2567
2568         /* Setting 1 on this value gives you interrupts for every vblank period. */
2569         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_EN_0, 0);
2570         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
2571
2572         pNv->CurrentState = state;
2573 }
2574
2575 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2576 {
2577         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2578         int i;
2579         NVCrtcRegPtr regp;
2580
2581         regp = &state->crtc_reg[nv_crtc->head];
2582
2583         regp->MiscOutReg = NVReadMiscOut(crtc);
2584
2585         for (i = 0; i < 25; i++)
2586                 regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
2587
2588         NVEnablePalette(crtc);
2589         for (i = 0; i < 21; i++)
2590                 regp->Attribute[i] = NVReadVgaAttr(crtc, i);
2591         NVDisablePalette(crtc);
2592
2593         for (i = 0; i < 9; i++)
2594                 regp->Graphics[i] = NVReadVgaGr(crtc, i);
2595
2596         for (i = 1; i < 5; i++)
2597                 regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
2598
2599 }
2600
2601 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2602 {
2603         ScrnInfoPtr pScrn = crtc->scrn;
2604         NVPtr pNv = NVPTR(pScrn);
2605         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2606         NVCrtcRegPtr regp;
2607         int i;
2608
2609         regp = &state->crtc_reg[nv_crtc->head];
2610
2611         /* If we ever get down to pre-nv10 cards, then we must reinstate some limits. */
2612         regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
2613         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
2614         regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
2615         regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
2616         regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
2617         regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
2618         regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
2619
2620         regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
2621         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
2622         if (pNv->Architecture >= NV_ARCH_30) {
2623                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
2624         }
2625         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
2626         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
2627         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
2628         regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
2629
2630         regp->gpio = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO);
2631         regp->unk830 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0830);
2632         regp->unk834 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0834);
2633         if (pNv->Architecture == NV_ARCH_40) {
2634                 regp->unk850 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0850);
2635                 regp->unk81c = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_081C);
2636         }
2637
2638         regp->config = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG);
2639
2640         regp->head = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL);
2641         regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
2642         regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
2643
2644         regp->cursorConfig = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG);
2645
2646         regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
2647         regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
2648         regp->CRTC[NV_VGA_CRTCX_3C] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3C);
2649         regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
2650         regp->CRTC[NV_VGA_CRTCX_4B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_4B);
2651         regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
2652         for (i = 0; i < 0x10; i++)
2653                 regp->CR58[i] = NVReadVGACR5758(pNv, nv_crtc->head, i);
2654
2655         regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
2656         regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
2657         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
2658         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
2659
2660         regp->CRTC[NV_VGA_CRTCX_43] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_43);
2661         regp->CRTC[NV_VGA_CRTCX_85] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_85);
2662         regp->CRTC[NV_VGA_CRTCX_86] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_86);
2663 }
2664
2665 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2666 {
2667         ScrnInfoPtr pScrn = crtc->scrn;
2668         NVPtr pNv = NVPTR(pScrn);
2669         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2670         NVCrtcRegPtr regp;
2671         int i;
2672
2673         regp = &state->crtc_reg[nv_crtc->head];
2674
2675         regp->general = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL);
2676
2677         regp->fp_control        = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL);
2678         regp->debug_0   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0);
2679         regp->debug_1   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1);
2680         regp->debug_2   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2);
2681
2682         regp->unk_a20 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20);
2683         regp->unk_a24 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24);
2684         regp->unk_a34 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34);
2685
2686         if (pNv->NVArch == 0x11) {
2687                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11);
2688         } else if (pNv->twoHeads) {
2689                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER);
2690         }
2691         regp->nv10_cursync = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC);
2692
2693         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2694
2695         for (i = 0; i < 7; i++) {
2696                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2697                 regp->fp_horiz_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2698         }
2699
2700         for (i = 0; i < 7; i++) {
2701                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2702                 regp->fp_vert_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2703         }
2704
2705         regp->fp_hvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START);
2706         regp->fp_hvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END);
2707         regp->fp_vvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START);
2708         regp->fp_vvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END);
2709 }
2710
2711 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2712 {
2713         ScrnInfoPtr pScrn = crtc->scrn;
2714         NVPtr pNv = NVPTR(pScrn);
2715         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2716         NVCrtcRegPtr regp;
2717         int i;
2718
2719         regp = &state->crtc_reg[nv_crtc->head];
2720
2721         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL, regp->general);
2722
2723         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control);
2724         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0, regp->debug_0);
2725         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
2726         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
2727
2728         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20, regp->unk_a20);
2729         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24, regp->unk_a24);
2730         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34, regp->unk_a34);
2731
2732         if (pNv->NVArch == 0x11) {
2733                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11, regp->dither);
2734         } else if (pNv->twoHeads) {
2735                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER, regp->dither);
2736         }
2737         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
2738
2739         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2740
2741         for (i = 0; i < 7; i++) {
2742                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2743                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_horiz_regs[i]);
2744         }
2745
2746         for (i = 0; i < 7; i++) {
2747                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2748                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_vert_regs[i]);
2749         }
2750
2751         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START, regp->fp_hvalid_start);
2752         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END, regp->fp_hvalid_end);
2753         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START, regp->fp_vvalid_start);
2754         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END, regp->fp_vvalid_end);
2755 }
2756
2757 void
2758 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y)
2759 {
2760         ScrnInfoPtr pScrn = crtc->scrn;
2761         NVPtr pNv = NVPTR(pScrn);
2762         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2763         NVFBLayout *pLayout = &pNv->CurrentLayout;
2764         uint32_t start = 0;
2765
2766         ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
2767
2768         start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
2769         if (crtc->rotatedData != NULL) { /* we do not exist on the real framebuffer */
2770 #if NOUVEAU_EXA_PIXMAPS
2771                 start = nv_crtc->shadow->offset;
2772 #else
2773                 start = pNv->FB->offset + nv_crtc->shadow->offset; /* We do exist relative to the framebuffer */
2774 #endif
2775         } else {
2776                 start += pNv->FB->offset;
2777         }
2778
2779         /* 30 bits addresses in 32 bits according to haiku */
2780         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_START, start & 0xfffffffc);
2781
2782         /* set NV4/NV10 byte adress: (bit0 - 1) */
2783         NVWriteVgaAttr(crtc, 0x13, (start & 0x3) << 1);
2784
2785         crtc->x = x;
2786         crtc->y = y;
2787 }
2788
2789 static void NVCrtcWriteDacMask(xf86CrtcPtr crtc, uint8_t value)
2790 {
2791   ScrnInfoPtr pScrn = crtc->scrn;
2792   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2793   NVPtr pNv = NVPTR(pScrn);
2794   volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2795
2796   NV_WR08(pDACReg, VGA_DAC_MASK, value);
2797 }
2798
2799 static uint8_t NVCrtcReadDacMask(xf86CrtcPtr crtc)
2800 {
2801   ScrnInfoPtr pScrn = crtc->scrn;
2802   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2803   NVPtr pNv = NVPTR(pScrn);
2804   volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2805
2806   return NV_RD08(pDACReg, VGA_DAC_MASK);
2807 }
2808
2809 static void NVCrtcWriteDacReadAddr(xf86CrtcPtr crtc, uint8_t value)
2810 {
2811   ScrnInfoPtr pScrn = crtc->scrn;
2812   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2813   NVPtr pNv = NVPTR(pScrn);
2814   volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2815
2816   NV_WR08(pDACReg, VGA_DAC_READ_ADDR, value);
2817 }
2818
2819 static void NVCrtcWriteDacWriteAddr(xf86CrtcPtr crtc, uint8_t value)
2820 {
2821   ScrnInfoPtr pScrn = crtc->scrn;
2822   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2823   NVPtr pNv = NVPTR(pScrn);
2824   volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2825
2826   NV_WR08(pDACReg, VGA_DAC_WRITE_ADDR, value);
2827 }
2828
2829 static void NVCrtcWriteDacData(xf86CrtcPtr crtc, uint8_t value)
2830 {
2831   ScrnInfoPtr pScrn = crtc->scrn;
2832   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2833   NVPtr pNv = NVPTR(pScrn);
2834   volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2835
2836   NV_WR08(pDACReg, VGA_DAC_DATA, value);
2837 }
2838
2839 static uint8_t NVCrtcReadDacData(xf86CrtcPtr crtc, uint8_t value)
2840 {
2841   ScrnInfoPtr pScrn = crtc->scrn;
2842   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2843   NVPtr pNv = NVPTR(pScrn);
2844   volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2845
2846   return NV_RD08(pDACReg, VGA_DAC_DATA);
2847 }
2848
2849 void NVCrtcLoadPalette(xf86CrtcPtr crtc)
2850 {
2851         int i;
2852         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2853         NVCrtcRegPtr regp;
2854         ScrnInfoPtr pScrn = crtc->scrn;
2855         NVPtr pNv = NVPTR(pScrn);
2856
2857         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2858
2859         NVCrtcSetOwner(crtc);
2860         NVCrtcWriteDacMask(crtc, 0xff);
2861         NVCrtcWriteDacWriteAddr(crtc, 0x00);
2862
2863         for (i = 0; i<768; i++) {
2864                 NVCrtcWriteDacData(crtc, regp->DAC[i]);
2865         }
2866         NVDisablePalette(crtc);
2867 }
2868
2869 /* on = unblank */
2870 void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
2871 {
2872         unsigned char scrn;
2873
2874         NVCrtcSetOwner(crtc);
2875
2876         scrn = NVReadVgaSeq(crtc, 0x01);
2877         if (on) {
2878                 scrn &= ~0x20;
2879         } else {
2880                 scrn |= 0x20;
2881         }
2882
2883         NVVgaSeqReset(crtc, TRUE);
2884         NVWriteVgaSeq(crtc, 0x01, scrn);
2885         NVVgaSeqReset(crtc, FALSE);
2886 }
2887
2888 /*************************************************************************** \
2889 |*                                                                           *|
2890 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
2891 |*                                                                           *|
2892 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
2893 |*     international laws.  Users and possessors of this source code are     *|
2894 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
2895 |*     use this code in individual and commercial software.                  *|
2896 |*                                                                           *|
2897 |*     Any use of this source code must include,  in the user documenta-     *|
2898 |*     tion and  internal comments to the code,  notices to the end user     *|
2899 |*     as follows:                                                           *|
2900 |*                                                                           *|
2901 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
2902 |*                                                                           *|
2903 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
2904 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
2905 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
2906 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
2907 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
2908 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
2909 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
2910 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
2911 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
2912 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
2913 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
2914 |*                                                                           *|
2915 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
2916 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
2917 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
2918 |*     computer  software  documentation,"  as such  terms  are  used in     *|
2919 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
2920 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
2921 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
2922 |*     all U.S. Government End Users  acquire the source code  with only     *|
2923 |*     those rights set forth herein.                                        *|
2924 |*                                                                           *|
2925  \***************************************************************************/