2 * Copyright 2007 Maarten Maathuis
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
27 /* Bit 28 also does something, although i don't know what. */
28 #define NV50_CONNECTOR_HOTPLUG_INTR 0x0000E050
29 #define NV50_CONNECTOR_HOTPLUG_INTR_PLUG_I2C0 (1 << 0)
30 #define NV50_CONNECTOR_HOTPLUG_INTR_PLUG_I2C1 (2 << 0)
31 #define NV50_CONNECTOR_HOTPLUG_INTR_UNPLUG_I2C0 (1 << 16)
32 #define NV50_CONNECTOR_HOTPLUG_INTR_UNPLUG_I2C1 (2 << 16)
34 /* Writing 0x7FFF7FFF seems to be the way to acknowledge an interrupt. */
35 /* There is also bit 7 and bit 23, but i also don't know what they do. */
36 #define NV50_CONNECTOR_HOTPLUG_CTRL 0x0000E054
37 #define NV50_CONNECTOR_HOTPLUG_CTRL_PLUG_I2C0 (1 << 0)
38 #define NV50_CONNECTOR_HOTPLUG_CTRL_PLUG_I2C1 (2 << 0)
39 #define NV50_CONNECTOR_HOTPLUG_CTRL_UNPLUG_I2C0 (1 << 16)
40 #define NV50_CONNECTOR_HOTPLUG_CTRL_UNPLUG_I2C1 (2 << 16)
42 /* This works for DVI->VGA adapters as well, providing the adapter supports it. */
43 /* It's unknown if bits exist for i2c port > 1. */
44 /* Renamed to avoid confusion with other instances of CONNECTED. */
45 #define NV50_CONNECTOR_HOTPLUG_STATE 0x0000E104
46 #define NV50_CONNECTOR_HOTPLUG_STATE_I2C0_DETECT_PIN (1 << 2)
47 #define NV50_CONNECTOR_HOTPLUG_STATE_I2C1_DETECT_PIN (1 << 6)
49 #define NV50_PCONNECTOR_I2C_PORT_0 0x0000e138
50 #define NV50_PCONNECTOR_I2C_PORT_1 0x0000e150
51 #define NV50_PCONNECTOR_I2C_PORT_2 0x0000e168
52 #define NV50_PCONNECTOR_I2C_PORT_3 0x0000e180
53 #define NV50_PCONNECTOR_I2C_PORT_4 0x0000e240
54 #define NV50_PCONNECTOR_I2C_PORT_5 0x0000e258
56 /* 0x00610024 is the state register to read, all it's bits also exist in 0x0061002C in the form of interrupt switches. */
57 #define NV50_DISPLAY_SUPERVISOR 0x00610024
58 #define NV50_DISPLAY_SUPERVISOR_CRTC0 (1 << 2)
59 #define NV50_DISPLAY_SUPERVISOR_CRTC1 (2 << 2)
60 #define NV50_DISPLAY_SUPERVISOR_CRTCn (3 << 2)
61 #define NV50_DISPLAY_SUPERVISOR_CLK_MASK (7 << 4)
62 #define NV50_DISPLAY_SUPERVISOR_CLK_UPDATE (2 << 4)
64 /* Two vblank interrupts arrive per blanking period, it could be rise and fall, i do not know. */
65 /* If a vblank interrupt arrives, check NV50_DISPLAY_SUPERVISOR, it will show for which crtc (or both) it is. */
66 /* Note that one crtc bit will always show, maybe it's updated when a vblank occurs? */
67 /* Once modesetting goes into the kernel, we can ditch NV50CheckWriteVClk() and do it with interrupts. */
68 /* Up until then, realise that most interrupts are not handled properly yet (and will stall your machine). */
69 /* Bit 8 and 9 also exist for sure, but their purpose is unknown. */
70 #define NV50_DISPLAY_SUPERVISOR_INTR 0x0061002C
71 #define NV50_DISPLAY_INTR_VBLANK_CRTC0 (1 << 2)
72 #define NV50_DISPLAY_INTR_VBLANK_CRTC1 (1 << 3)
73 #define NV50_DISPLAY_INTR_UNK1 (1 << 4)
74 #define NV50_DISPLAY_INTR_CLK_UPDATE (2 << 4)
75 #define NV50_DISPLAY_INTR_UNK4 (4 << 4)
77 #define NV50_DISPLAY_UNK30_CTRL 0x00610030
78 #define NV50_DISPLAY_UNK30_CTRL_UPDATE_VCLK0 (1 << 9)
79 #define NV50_DISPLAY_UNK30_CTRL_UPDATE_VCLK1 (1 << 10)
80 #define NV50_DISPLAY_UNK30_CTRL_PENDING (1 << 31)
82 #define NV50_DISPLAY_UNK50_CTRL 0x00610050
83 #define NV50_DISPLAY_UNK50_CTRL_CRTC0_ACTIVE (2 << 0)
84 #define NV50_DISPLAY_UNK50_CTRL_CRTC0_MASK (3 << 0)
85 #define NV50_DISPLAY_UNK50_CTRL_CRTC1_ACTIVE (2 << 8)
86 #define NV50_DISPLAY_UNK50_CTRL_CRTC1_MASK (3 << 8)
88 /* I really don't know what this does, except that it's only revelant at start. */
89 #define NV50_DISPLAY_UNK200_CTRL 0x00610200
91 /* bit3 always activates itself, and bit 4 is some kind of switch. */
92 #define NV50_CRTC0_CURSOR_CTRL2 0x00610270
93 #define NV50_CRTC_CURSOR_CTRL2_ON (1 << 0)
94 #define NV50_CRTC_CURSOR_CTRL2_OFF (0 << 0)
95 #define NV50_CRTC_CURSOR_CTRL2_STATUS_MASK (3 << 16)
96 #define NV50_CRTC_CURSOR_CTRL2_STATUS_ACTIVE (1 << 16)
97 #define NV50_CRTC1_CURSOR_CTRL2 0x00610280
99 #define NV50_DISPLAY_CTRL_STATE 0x00610300
100 #define NV50_DISPLAY_CTRL_STATE_DISABLE (0 << 0)
101 #define NV50_DISPLAY_CTRL_STATE_ENABLE (1 << 0)
102 #define NV50_DISPLAY_CTRL_STATE_PENDING (1 << 31)
103 #define NV50_DISPLAY_CTRL_VAL 0x00610304
105 #define NV50_DISPLAY_UNK_380 0x00610380
106 /* Clamped to 256 MiB */
107 #define NV50_DISPLAY_RAM_AMOUNT 0x00610384
108 #define NV50_DISPLAY_UNK_388 0x00610388
109 #define NV50_DISPLAY_UNK_38C 0x0061038C
111 /* The registers in this range are normally accessed through display commands, with an offset of 0x540 for crtc1. */
112 /* They also seem duplicated into the next register as well. */
113 #define NV50_CRTC0_CLUT_MODE_VAL 0x00610A24
114 #define NV50_CRTC0_SCALE_CTRL_VAL 0x00610A50
115 #define NV50_CRTC0_CURSOR_CTRL_VAL 0x00610A58
116 #define NV50_CRTC0_DEPTH_VAL 0x00610AC8
117 #define NV50_CRTC0_CLOCK_VAL 0x00610AD0
118 #define NV50_CRTC0_COLOR_CTRL_VAL 0x00610AE0
119 #define NV50_CRTC0_SYNC_START_TO_BLANK_END_VAL 0x00610AE8
120 #define NV50_CRTC0_MODE_UNK1_VAL 0x00610AF0
121 #define NV50_CRTC0_DISPLAY_TOTAL_VAL 0x00610AF8
122 #define NV50_CRTC0_SYNC_DURATION_VAL 0x00610B00
123 /* For some reason this displayed the maximum framebuffer size for crtc0/dfp. */
124 /* It was correct for crtc1/afp. */
125 #define NV50_CRTC0_FB_SIZE_VAL 0x00610B18
126 #define NV50_CRTC0_FB_PITCH_VAL 0x00610B20
127 #define NV50_CRTC0_FB_POS_VAL 0x00610B28
128 #define NV50_CRTC0_SCALE_CENTER_OFFSET_VAL 0x00610B38
129 #define NV50_CRTC0_REAL_RES_VAL 0x00610B40
130 /* I can't be 100% about the order of these two, as setting them differently locks up the card. */
131 #define NV50_CRTC0_SCALE_RES1_VAL 0x00610B48
132 #define NV50_CRTC0_SCALE_RES2_VAL 0x00610B50
134 /* Some registers are based on extrapolation. */
135 #define NV50_DAC0_MODE_CTRL_VAL 0x00610B58
136 #define NV50_DAC1_MODE_CTRL_VAL 0x00610B60
137 #define NV50_DAC2_MODE_CTRL_VAL 0x00610B68
138 #define NV50_SOR0_MODE_CTRL_VAL 0x00610B70
139 #define NV50_SOR1_MODE_CTRL_VAL 0x00610B78
141 #define NV50_DAC0_MODE_CTRL2_VAL 0x00610BDC
142 #define NV50_DAC1_MODE_CTRL2_VAL 0x00610BE4
143 #define NV50_DAC2_MODE_CTRL2_VAL 0x00610BEC
145 #define NV50_CRTC1_CLUT_MODE_VAL 0x00610F64
146 #define NV50_CRTC1_SCALE_CTRL_VAL 0x00610F90
147 #define NV50_CRTC1_CURSOR_CTRL_VAL 0x00610F98
148 #define NV50_CRTC1_DEPTH_VAL 0x00611008
149 #define NV50_CRTC1_CLOCK_VAL 0x00611010
150 #define NV50_CRTC1_COLOR_CTRL_VAL 0x00611020
151 #define NV50_CRTC1_SYNC_START_TO_BLANK_END_VAL 0x00611028
152 #define NV50_CRTC1_MODE_UNK1_VAL 0x00611030
153 #define NV50_CRTC1_DISPLAY_TOTAL_VAL 0x00611038
154 #define NV50_CRTC1_SYNC_DURATION_VAL 0x00611040
155 #define NV50_CRTC1_FB_SIZE_VAL 0x00611058
156 #define NV50_CRTC1_FB_PITCH_VAL 0x00611060
157 #define NV50_CRTC1_FB_POS_VAL 0x00611068
158 #define NV50_CRTC1_SCALE_CENTER_OFFSET_VAL 0x00611078
159 #define NV50_CRTC1_REAL_RES_VAL 0x00611080
160 /* I can't be 100% about the order of these two, as setting them differently locks up the card. */
161 #define NV50_CRTC1_SCALE_RES1_VAL 0x00611088
162 #define NV50_CRTC1_SCALE_RES2_VAL 0x00611090
164 /* These CLK_CTRL names are a bit of a guess, i do have my reasons though. */
165 /* These connected indicators exist for crtc, dac and sor. */
166 #define NV50_CRTC0_CLK_CTRL1 0x00614100
167 #define NV50_CRTC_CLK_CTRL1_CONNECTED (3 << 9)
168 /* These are probably redrirected from 0x4000 range (very similar regs to nv40, maybe different order) */
169 #define NV50_CRTC0_VPLL_A 0x00614104
170 #define NV50_CRTC0_VPLL_B 0x00614108
171 #define NV50_CRTC0_CLK_CTRL2 0x00614200
173 /* These control some special modes, like dual link dvi, maybe they need another name? */
174 #define NV50_DAC0_CLK_CTRL2 0x00614280
175 #define NV50_SOR0_CLK_CTRL2 0x00614300
177 #define NV50_CRTC1_CLK_CTRL1 0x00614900
178 #define NV50_CRTC1_VPLL_A 0x00614904
179 #define NV50_CRTC1_VPLL_B 0x00614908
180 #define NV50_CRTC1_CLK_CTRL2 0x00614A00
182 #define NV50_DAC1_CLK_CTRL2 0x00614A80
183 #define NV50_SOR1_CLK_CTRL2 0x00614B00
185 #define NV50_DAC2_CLK_CTRL2 0x00615280
187 #define NV50_DAC0_DPMS_CTRL 0x0061A004
188 #define NV50_DAC_DPMS_CTRL_HSYNC_OFF (1 << 0)
189 #define NV50_DAC_DPMS_CTRL_VSYNC_OFF (1 << 2)
190 #define NV50_DAC_DPMS_CTRL_BLANKED (1 << 4)
191 #define NV50_DAC_DPMS_CTRL_OFF (1 << 6)
192 /* Some cards also use bit 22, why exactly is unknown. */
193 /* It seems that 1, 4 and 5 are present at bit0. bit4. bit16, bit20. */
194 /* No idea what the symmetry means precisely. */
195 #define NV50_DAC_DPMS_CTRL_DEFAULT_STATE (21 << 16)
196 #define NV50_DAC_DPMS_CTRL_PENDING (1 << 31)
197 #define NV50_DAC0_LOAD_CTRL 0x0061A00C
198 #define NV50_DAC_LOAD_CTRL_ACTIVE (1 << 20)
199 #define NV50_DAC_LOAD_CTRL_PRESENT (7 << 27)
200 /* this a bit of a guess, as load detect is very fast */
201 #define NV50_DAC_LOAD_CTRL_DONE (1 << 31)
202 /* These connected indicators exist for crtc, dac and sor. */
203 /* The upper 4 bits seem to be some kind indicator. */
204 /* The purpose of bit 1 is unknown, maybe some kind of reset? */
205 #define NV50_DAC0_CLK_CTRL1 0x0061A010
206 #define NV50_DAC_CLK_CTRL1_CONNECTED (3 << 9)
207 #define NV50_DAC1_DPMS_CTRL 0x0061A804
208 #define NV50_DAC1_LOAD_CTRL 0x0061A80C
209 #define NV50_DAC1_CLK_CTRL1 0x0061A810
210 #define NV50_DAC2_DPMS_CTRL 0x0061B004
211 #define NV50_DAC2_LOAD_CTRL 0x0061B00C
212 #define NV50_DAC2_CLK_CTRL1 0x0061B010
214 /* both SOR_DPMS and DAC_DPMS have a bit28, whose purpose is unknown atm. */
215 #define NV50_SOR0_DPMS_CTRL 0x0061C004
216 #define NV50_SOR_DPMS_CTRL_MODE_ON (1 << 0)
217 #define NV50_SOR_DPMS_CTRL_PENDING (1 << 31)
218 /* These connected indicators exist for crtc, dac and sor. */
219 /* I don't know what bit27 does, it doesn't seem extremely important. */
220 #define NV50_SOR0_CLK_CTRL1 0x0061C008
221 #define NV50_SOR_CLK_CTRL1_CONNECTED (3 << 9)
222 /* Seems to be a default state, nothing that can RE'd in great detail. */
223 #define NV50_SOR0_UNK00C 0x0061C00C
224 #define NV50_SOR0_UNK010 0x0061C010
225 #define NV50_SOR0_UNK014 0x0061C014
226 #define NV50_SOR0_UNK018 0x0061C018
228 #define NV50_SOR0_DPMS_STATE 0x0061C030
229 #define NV50_SOR_DPMS_STATE_ACTIVE (3 << 16) /* this does not show if DAC is active */
230 #define NV50_SOR_DPMS_STATE_BLANKED (8 << 16)
231 #define NV50_SOR_DPMS_STATE_WAIT (1 << 28)
233 #define NV50_SOR1_DPMS_CTRL 0x0061C804
234 #define NV50_SOR1_CLK_CTRL1 0x0061C808
235 /* Seems to be a default state, nothing that can RE'd in any great detail. */
236 #define NV50_SOR1_UNK00C 0x0061C80C
237 #define NV50_SOR1_UNK010 0x0061C810
238 #define NV50_SOR1_UNK014 0x0061C814
239 #define NV50_SOR1_UNK018 0x0061C818
241 #define NV50_SOR1_DPMS_STATE 0x0061C830
243 /* A few things seem to exist in the 0x0064XXXX range, but not much. */
244 /* Each of these corresponds to a range in 0x006102XX. */
245 /* The blob writes zero to these regs. */
246 /* 0x00610200-0x0061020C, 0x00610200 seems special from all the rest. */
247 #define NV50_UNK_640000 0x00640000
248 /* 0x00610210-0x0061021C */
249 #define NV50_UNK_641000 0x00641000
250 /* 0x00610220-0x0061022C */
251 /* Seems tv-out related somehow, the other two show up always. */
252 #define NV50_UNK_642000 0x00642000
253 /* 0x00610230-0x0061023C and 0x00610240-0x0061024C seem to be similar. */
254 /* I think the correlation goes for all 0x0064X000, up to and including 6. */
256 /* Write 0 to process the new position, seem to be write only registers. */
257 #define NV50_CRTC0_CURSOR_POS_CTRL 0x00647080
258 #define NV50_CRTC0_CURSOR_POS 0x00647084
259 #define NV50_CRTC1_CURSOR_POS_CTRL 0x00648080
260 #define NV50_CRTC1_CURSOR_POS 0x00648084
262 /* These things below are so called "commands" */
263 #define NV50_UPDATE_DISPLAY 0x80
264 #define NV50_UNK84 0x84
265 #define NV50_UNK88 0x88
267 #define NV50_DAC0_MODE_CTRL 0x400
268 #define NV50_DAC_MODE_CTRL_OFF (0 << 0)
269 #define NV50_DAC_MODE_CTRL_CRTC0 (1 << 0)
270 #define NV50_DAC_MODE_CTRL_CRTC1 (1 << 1)
271 #define NV50_DAC1_MODE_CTRL 0x480
272 #define NV50_DAC2_MODE_CTRL 0x500
274 #define NV50_DAC0_MODE_CTRL2 0x404
275 #define NV50_DAC_MODE_CTRL2_NHSYNC (1 << 0)
276 #define NV50_DAC_MODE_CTRL2_NVSYNC (2 << 0)
277 #define NV50_DAC1_MODE_CTRL2 0x484
278 #define NV50_DAC2_MODE_CTRL2 0x504
280 #define NV50_SOR0_MODE_CTRL 0x600
281 #define NV50_SOR_MODE_CTRL_OFF (0 << 0)
282 #define NV50_SOR_MODE_CTRL_CRTC0 (1 << 0)
283 #define NV50_SOR_MODE_CTRL_CRTC1 (1 << 1)
284 #define NV50_SOR_MODE_CTRL_LVDS (0 << 8)
285 #define NV50_SOR_MODE_CTRL_TMDS (1 << 8)
286 #define NV50_SOR_MODE_CTRL_TMDS_DUAL_LINK (4 << 8)
287 #define NV50_SOR_MODE_CTRL_NHSYNC (1 << 12)
288 #define NV50_SOR_MODE_CTRL_NVSYNC (2 << 12)
289 #define NV50_SOR1_MODE_CTRL 0x640
291 #define NV50_CRTC0_UNK800 0x800
292 #define NV50_CRTC0_CLOCK 0x804
293 #define NV50_CRTC0_INTERLACE 0x808
295 /* 0x810 is a reasonable guess, nothing more. */
296 #define NV50_CRTC0_DISPLAY_START 0x810
297 #define NV50_CRTC0_DISPLAY_TOTAL 0x814
298 #define NV50_CRTC0_SYNC_DURATION 0x818
299 #define NV50_CRTC0_SYNC_START_TO_BLANK_END 0x81C
300 #define NV50_CRTC0_MODE_UNK1 0x820
301 #define NV50_CRTC0_MODE_UNK2 0x824
303 #define NV50_CRTC0_UNK82C 0x82C
305 /* You can't have a palette in 8 bit mode (=OFF) */
306 #define NV50_CRTC0_CLUT_MODE 0x840
307 #define NV50_CRTC0_CLUT_MODE_BLANK 0x00000000
308 #define NV50_CRTC0_CLUT_MODE_OFF 0x80000000
309 #define NV50_CRTC0_CLUT_MODE_ON 0xC0000000
310 #define NV50_CRTC0_CLUT_OFFSET 0x844
312 /* Anyone know what part of the chip is triggered here precisely? */
313 #define NV84_CRTC0_BLANK_UNK1 0x85C
314 #define NV84_CRTC0_BLANK_UNK1_BLANK 0x0
315 #define NV84_CRTC0_BLANK_UNK1_UNBLANK 0x1
317 #define NV50_CRTC0_FB_OFFSET 0x860
319 #define NV50_CRTC0_FB_SIZE 0x868
320 #define NV50_CRTC0_FB_PITCH 0x86C
322 #define NV50_CRTC0_DEPTH 0x870
323 #define NV50_CRTC0_DEPTH_8BPP 0x1E00
324 #define NV50_CRTC0_DEPTH_15BPP 0xE900
325 #define NV50_CRTC0_DEPTH_16BPP 0xE800
326 #define NV50_CRTC0_DEPTH_24BPP 0xCF00
328 /* I'm openminded to better interpretations. */
329 /* This is an educated guess. */
330 /* NV50 has RAMDAC and TMDS offchip, so it's unlikely to be that. */
331 #define NV50_CRTC0_BLANK_CTRL 0x874
332 #define NV50_CRTC0_BLANK_CTRL_BLANK 0x0
333 #define NV50_CRTC0_BLANK_CTRL_UNBLANK 0x1
335 #define NV50_CRTC0_CURSOR_CTRL 0x880
336 #define NV50_CRTC0_CURSOR_CTRL_SHOW 0x85000000
337 #define NV50_CRTC0_CURSOR_CTRL_HIDE 0x05000000
339 #define NV50_CRTC0_CURSOR_OFFSET 0x884
341 /* Anyone know what part of the chip is triggered here precisely? */
342 #define NV84_CRTC0_BLANK_UNK2 0x89C
343 #define NV84_CRTC0_BLANK_UNK2_BLANK 0x0
344 #define NV84_CRTC0_BLANK_UNK2_UNBLANK 0x1
346 #define NV50_CRTC0_DITHERING_CTRL 0x8A0
347 #define NV50_CRTC0_DITHERING_CTRL_ON 0x11
348 #define NV50_CRTC0_DITHERING_CTRL_OFF 0x0
350 #define NV50_CRTC0_SCALE_CTRL 0x8A4
351 #define NV50_CRTC0_SCALE_CTRL_SCALER_INACTIVE (0 << 0)
352 /* It doesn't seem to be needed, hence i wonder what it does precisely. */
353 #define NV50_CRTC0_SCALE_CTRL_SCALER_ACTIVE (9 << 0)
354 #define NV50_CRTC0_COLOR_CTRL 0x8A8
355 #define NV50_CRTC_COLOR_CTRL_MODE_COLOR (4 << 16)
357 #define NV50_CRTC0_FB_POS 0x8C0
358 #define NV50_CRTC0_REAL_RES 0x8C8
360 /* Added a macro, because the signed stuff can cause you problems very quickly. */
361 #define NV50_CRTC0_SCALE_CENTER_OFFSET 0x8D4
362 #define NV50_CRTC_SCALE_CENTER_OFFSET_VAL(x, y) ((((unsigned)y << 16) & 0xFFFF0000) | (((unsigned)x) & 0x0000FFFF))
363 /* Both of these are needed, otherwise nothing happens. */
364 #define NV50_CRTC0_SCALE_RES1 0x8D8
365 #define NV50_CRTC0_SCALE_RES2 0x8DC
367 #define NV50_CRTC1_UNK800 0xC00
368 #define NV50_CRTC1_CLOCK 0xC04
369 #define NV50_CRTC1_INTERLACE 0xC08
371 /* 0xC10 is a reasonable guess, nothing more. */
372 #define NV50_CRTC1_DISPLAY_START 0xC10
373 #define NV50_CRTC1_DISPLAY_TOTAL 0xC14
374 #define NV50_CRTC1_SYNC_DURATION 0xC18
375 #define NV50_CRTC1_SYNC_START_TO_BLANK_END 0xC1C
376 #define NV50_CRTC1_MODE_UNK1 0xC20
377 #define NV50_CRTC1_MODE_UNK2 0xC24
379 #define NV50_CRTC1_CLUT_MODE 0xC40
380 #define NV50_CRTC1_CLUT_MODE_BLANK 0x00000000
381 #define NV50_CRTC1_CLUT_MODE_OFF 0x80000000
382 #define NV50_CRTC1_CLUT_MODE_ON 0xC0000000
383 #define NV50_CRTC1_CLUT_OFFSET 0xC44
385 /* Anyone know what part of the chip is triggered here precisely? */
386 #define NV84_CRTC1_BLANK_UNK1 0xC5C
387 #define NV84_CRTC1_BLANK_UNK1_BLANK 0x0
388 #define NV84_CRTC1_BLANK_UNK1_UNBLANK 0x1
390 #define NV50_CRTC1_FB_OFFSET 0xC60
392 #define NV50_CRTC1_FB_SIZE 0xC68
393 #define NV50_CRTC1_FB_PITCH 0xC6C
395 #define NV50_CRTC1_DEPTH 0xC70
396 #define NV50_CRTC1_DEPTH_8BPP 0x1E00
397 #define NV50_CRTC1_DEPTH_15BPP 0xE900
398 #define NV50_CRTC1_DEPTH_16BPP 0xE800
399 #define NV50_CRTC1_DEPTH_24BPP 0xCF00
401 /* I'm openminded to better interpretations. */
402 #define NV50_CRTC1_BLANK_CTRL 0xC74
403 #define NV50_CRTC1_BLANK_CTRL_BLANK 0x0
404 #define NV50_CRTC1_BLANK_CTRL_UNBLANK 0x1
406 #define NV50_CRTC1_CURSOR_CTRL 0xC80
407 #define NV50_CRTC1_CURSOR_CTRL_SHOW 0x85000000
408 #define NV50_CRTC1_CURSOR_CTRL_HIDE 0x05000000
410 #define NV50_CRTC1_CURSOR_OFFSET 0xC84
412 /* Anyone know what part of the chip is triggered here precisely? */
413 #define NV84_CRTC1_BLANK_UNK2 0xC9C
414 #define NV84_CRTC1_BLANK_UNK2_BLANK 0x0
415 #define NV84_CRTC1_BLANK_UNK2_UNBLANK 0x1
417 #define NV50_CRTC1_DITHERING_CTRL 0xCA0
418 #define NV50_CRTC1_DITHERING_CTRL_ON 0x11
419 #define NV50_CRTC1_DITHERING_CTRL_OFF 0x0
421 #define NV50_CRTC1_SCALE_CTRL 0xCA4
422 #define NV50_CRTC1_COLOR_CTRL 0xCA8
424 #define NV50_CRTC1_FB_POS 0xCC0
425 #define NV50_CRTC1_REAL_RES 0xCC8
427 #define NV50_CRTC1_SCALE_CENTER_OFFSET 0xCD4
428 /* Both of these are needed, otherwise nothing happens. */
429 #define NV50_CRTC1_SCALE_RES1 0xCD8
430 #define NV50_CRTC1_SCALE_RES2 0xCDC
433 #define NV50_I2C_START 0x7
434 #define NV50_I2C_STOP 0x3
436 #endif /* __NV50REG_H_ */
projects / nouveau / blob