git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 2006 Dave Airlie
   3  * Copyright 2007 Maarten Maathuis
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
  26  * decleration is at the bottom of this file as it is rather ugly
  27  */
  28
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include <assert.h>
  34 #include "xf86.h"
  35 #include "os.h"
  36 #include "mibank.h"
  37 #include "globals.h"
  38 #include "xf86.h"
  39 #include "xf86Priv.h"
  40 #include "xf86DDC.h"
  41 #include "mipointer.h"
  42 #include "windowstr.h"
  43 #include <randrstr.h>
  44 #include <X11/extensions/render.h>
  45
  46 #include "xf86Crtc.h"
  47 #include "nv_include.h"
  48
  49 #include "vgaHW.h"
  50
  51 #define CRTC_INDEX 0x3d4
  52 #define CRTC_DATA 0x3d5
  53 #define CRTC_IN_STAT_1 0x3da
  54
  55 #define WHITE_VALUE 0x3F
  56 #define BLACK_VALUE 0x00
  57 #define OVERSCAN_VALUE 0x01
  58
  59 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  60 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override);
  61 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  62 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  63 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  64 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  65
  66 static CARD8 NVReadPVIO(xf86CrtcPtr crtc, CARD32 address)
  67 {
  68         ScrnInfoPtr pScrn = crtc->scrn;
  69         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  70         NVPtr pNv = NVPTR(pScrn);
  71
  72         /* Only NV4x have two pvio ranges */
  73         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  74                 return NV_RD08(pNv->PVIO1, address);
  75         } else {
  76                 return NV_RD08(pNv->PVIO0, address);
  77         }
  78 }
  79
  80 static void NVWritePVIO(xf86CrtcPtr crtc, CARD32 address, CARD8 value)
  81 {
  82         ScrnInfoPtr pScrn = crtc->scrn;
  83         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  84         NVPtr pNv = NVPTR(pScrn);
  85
  86         /* Only NV4x have two pvio ranges */
  87         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  88                 NV_WR08(pNv->PVIO1, address, value);
  89         } else {
  90                 NV_WR08(pNv->PVIO0, address, value);
  91         }
  92 }
  93
  94 static void NVWriteMiscOut(xf86CrtcPtr crtc, CARD8 value)
  95 {
  96         NVWritePVIO(crtc, VGA_MISC_OUT_W, value);
  97 }
  98
  99 static CARD8 NVReadMiscOut(xf86CrtcPtr crtc)
 100 {
 101         return NVReadPVIO(crtc, VGA_MISC_OUT_R);
 102 }
 103
 104 void NVWriteVGA(NVPtr pNv, int head, CARD8 index, CARD8 value)
 105 {
 106         volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 107
 108         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 109         NV_WR08(pCRTCReg, CRTC_DATA, value);
 110 }
 111
 112 CARD8 NVReadVGA(NVPtr pNv, int head, CARD8 index)
 113 {
 114         volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 115
 116         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 117         return NV_RD08(pCRTCReg, CRTC_DATA);
 118 }
 119
 120 /* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
 121  * I suspect they in fact do nothing, but are merely a way to carry useful
 122  * per-head variables around
 123  *
 124  * Known uses:
 125  * CR57         CR58
 126  * 0x00         index to the appropriate dcb entry (or 7f for inactive)
 127  * 0x02         dcb entry's "or" value (or 00 for inactive)
 128  * 0x03         bit0 set for dual link (LVDS, possibly elsewhere too)
 129  * 0x08 or 0x09 pxclk in MHz
 130  * 0x0f         laptop panel info -     low nibble for PEXTDEV_BOOT strap
 131  *                                      high nibble for xlat strap value
 132  */
 133
 134 void NVWriteVGACR5758(NVPtr pNv, int head, uint8_t index, uint8_t value)
 135 {
 136         NVWriteVGA(pNv, head, 0x57, index);
 137         NVWriteVGA(pNv, head, 0x58, value);
 138 }
 139
 140 uint8_t NVReadVGACR5758(NVPtr pNv, int head, uint8_t index)
 141 {
 142         NVWriteVGA(pNv, head, 0x57, index);
 143         return NVReadVGA(pNv, head, 0x58);
 144 }
 145
 146 void NVWriteVgaCrtc(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 147 {
 148         ScrnInfoPtr pScrn = crtc->scrn;
 149         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 150         NVPtr pNv = NVPTR(pScrn);
 151
 152         NVWriteVGA(pNv, nv_crtc->head, index, value);
 153 }
 154
 155 CARD8 NVReadVgaCrtc(xf86CrtcPtr crtc, CARD8 index)
 156 {
 157         ScrnInfoPtr pScrn = crtc->scrn;
 158         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 159         NVPtr pNv = NVPTR(pScrn);
 160
 161         return NVReadVGA(pNv, nv_crtc->head, index);
 162 }
 163
 164 static void NVWriteVgaSeq(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 165 {
 166         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 167         NVWritePVIO(crtc, VGA_SEQ_DATA, value);
 168 }
 169
 170 static CARD8 NVReadVgaSeq(xf86CrtcPtr crtc, CARD8 index)
 171 {
 172         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 173         return NVReadPVIO(crtc, VGA_SEQ_DATA);
 174 }
 175
 176 static void NVWriteVgaGr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 177 {
 178         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 179         NVWritePVIO(crtc, VGA_GRAPH_DATA, value);
 180 }
 181
 182 static CARD8 NVReadVgaGr(xf86CrtcPtr crtc, CARD8 index)
 183 {
 184         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 185         return NVReadPVIO(crtc, VGA_GRAPH_DATA);
 186 }
 187
 188
 189 static void NVWriteVgaAttr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 190 {
 191   ScrnInfoPtr pScrn = crtc->scrn;
 192   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 193   NVPtr pNv = NVPTR(pScrn);
 194   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 195
 196   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 197   if (nv_crtc->paletteEnabled)
 198     index &= ~0x20;
 199   else
 200     index |= 0x20;
 201   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 202   NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
 203 }
 204
 205 static CARD8 NVReadVgaAttr(xf86CrtcPtr crtc, CARD8 index)
 206 {
 207   ScrnInfoPtr pScrn = crtc->scrn;
 208   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 209   NVPtr pNv = NVPTR(pScrn);
 210   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 211
 212   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 213   if (nv_crtc->paletteEnabled)
 214     index &= ~0x20;
 215   else
 216     index |= 0x20;
 217   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 218   return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
 219 }
 220
 221 void NVCrtcSetOwner(xf86CrtcPtr crtc)
 222 {
 223         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 224         ScrnInfoPtr pScrn = crtc->scrn;
 225         NVPtr pNv = NVPTR(pScrn);
 226         /* Non standard beheaviour required by NV11 */
 227         if (pNv) {
 228                 uint8_t owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 229                 ErrorF("pre-Owner: 0x%X\n", owner);
 230                 if (owner == 0x04) {
 231                         uint32_t pbus84 = nvReadMC(pNv, 0x1084);
 232                         ErrorF("pbus84: 0x%X\n", pbus84);
 233                         pbus84 &= ~(1<<28);
 234                         ErrorF("pbus84: 0x%X\n", pbus84);
 235                         nvWriteMC(pNv, 0x1084, pbus84);
 236                 }
 237                 /* The blob never writes owner to pcio1, so should we */
 238                 if (pNv->NVArch == 0x11) {
 239                         NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, 0xff);
 240                 }
 241                 NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, nv_crtc->head * 0x3);
 242                 owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 243                 ErrorF("post-Owner: 0x%X\n", owner);
 244         } else {
 245                 ErrorF("pNv pointer is NULL\n");
 246         }
 247 }
 248
 249 static void
 250 NVEnablePalette(xf86CrtcPtr crtc)
 251 {
 252   ScrnInfoPtr pScrn = crtc->scrn;
 253   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 254   NVPtr pNv = NVPTR(pScrn);
 255   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 256
 257   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 258   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
 259   nv_crtc->paletteEnabled = TRUE;
 260 }
 261
 262 static void
 263 NVDisablePalette(xf86CrtcPtr crtc)
 264 {
 265   ScrnInfoPtr pScrn = crtc->scrn;
 266   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 267   NVPtr pNv = NVPTR(pScrn);
 268   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 269
 270   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 271   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
 272   nv_crtc->paletteEnabled = FALSE;
 273 }
 274
 275 static void NVWriteVgaReg(xf86CrtcPtr crtc, CARD32 reg, CARD8 value)
 276 {
 277  ScrnInfoPtr pScrn = crtc->scrn;
 278   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 279   NVPtr pNv = NVPTR(pScrn);
 280   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 281
 282   NV_WR08(pCRTCReg, reg, value);
 283 }
 284
 285 /* perform a sequencer reset */
 286 static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
 287 {
 288   if (start)
 289     NVWriteVgaSeq(crtc, 0x00, 0x1);
 290   else
 291     NVWriteVgaSeq(crtc, 0x00, 0x3);
 292
 293 }
 294 static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
 295 {
 296         CARD8 tmp;
 297
 298         if (on) {
 299                 tmp = NVReadVgaSeq(crtc, 0x1);
 300                 NVVgaSeqReset(crtc, TRUE);
 301                 NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
 302
 303                 NVEnablePalette(crtc);
 304         } else {
 305                 /*
 306                  * Reenable sequencer, then turn on screen.
 307                  */
 308                 tmp = NVReadVgaSeq(crtc, 0x1);
 309                 NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20); /* reenable display */
 310                 NVVgaSeqReset(crtc, FALSE);
 311
 312                 NVDisablePalette(crtc);
 313         }
 314 }
 315
 316 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool Lock)
 317 {
 318         CARD8 cr11;
 319
 320         NVCrtcSetOwner(crtc);
 321
 322         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57);
 323         cr11 = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE);
 324         if (Lock) cr11 |= 0x80;
 325         else cr11 &= ~0x80;
 326         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE, cr11);
 327 }
 328
 329 xf86OutputPtr
 330 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
 331 {
 332         ScrnInfoPtr pScrn = crtc->scrn;
 333         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 334         int i;
 335         for (i = 0; i < xf86_config->num_output; i++) {
 336                 xf86OutputPtr output = xf86_config->output[i];
 337
 338                 if (output->crtc == crtc) {
 339                         return output;
 340                 }
 341         }
 342
 343         return NULL;
 344 }
 345
 346 xf86CrtcPtr
 347 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
 348 {
 349         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 350         int i;
 351
 352         for (i = 0; i < xf86_config->num_crtc; i++) {
 353                 xf86CrtcPtr crtc = xf86_config->crtc[i];
 354                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 355                 if (nv_crtc->head == index)
 356                         return crtc;
 357         }
 358
 359         return NULL;
 360 }
 361
 362 /*
 363  * Calculate the Video Clock parameters for the PLL.
 364  */
 365 static void CalcVClock (
 366         uint32_t                clockIn,
 367         uint32_t                *clockOut,
 368         CARD32          *pllOut,
 369         NVPtr           pNv
 370 )
 371 {
 372         unsigned lowM, highM, highP;
 373         unsigned DeltaNew, DeltaOld;
 374         unsigned VClk, Freq;
 375         unsigned M, N, P;
 376
 377         /* M: PLL reference frequency postscaler divider */
 378         /* P: PLL VCO output postscaler divider */
 379         /* N: PLL VCO postscaler setting */
 380
 381         DeltaOld = 0xFFFFFFFF;
 382
 383         VClk = (unsigned)clockIn;
 384
 385         /* Taken from Haiku, after someone with an NV28 had an issue */
 386         switch(pNv->NVArch) {
 387                 case 0x28:
 388                         lowM = 1;
 389                         highP = 32;
 390                         if (VClk > 340000) {
 391                                 highM = 2;
 392                         } else if (VClk > 200000) {
 393                                 highM = 4;
 394                         } else if (VClk > 150000) {
 395                                 highM = 6;
 396                         } else {
 397                                 highM = 14;
 398                         }
 399                         break;
 400                 default:
 401                         lowM = 1;
 402                         highP = 16;
 403                         if (VClk > 340000) {
 404                                 highM = 2;
 405                         } else if (VClk > 250000) {
 406                                 highM = 6;
 407                         } else {
 408                                 highM = 14;
 409                         }
 410                         break;
 411         }
 412
 413         for (P = 1; P <= highP; P++) {
 414                 Freq = VClk << P;
 415                 if ((Freq >= 128000) && (Freq <= 350000)) {
 416                         for (M = lowM; M <= highM; M++) {
 417                                 N = ((VClk << P) * M) / pNv->CrystalFreqKHz;
 418                                 if (N <= 255) {
 419                                         Freq = ((pNv->CrystalFreqKHz * N) / M) >> P;
 420                                         if (Freq > VClk) {
 421                                                 DeltaNew = Freq - VClk;
 422                                         } else {
 423                                                 DeltaNew = VClk - Freq;
 424                                         }
 425                                         if (DeltaNew < DeltaOld) {
 426                                                 *pllOut   = (P << 16) | (N << 8) | M;
 427                                                 *clockOut = Freq;
 428                                                 DeltaOld  = DeltaNew;
 429                                         }
 430                                 }
 431                         }
 432                 }
 433         }
 434 }
 435
 436 static void CalcVClock2Stage (
 437         uint32_t                clockIn,
 438         uint32_t                *clockOut,
 439         CARD32          *pllOut,
 440         CARD32          *pllBOut,
 441         NVPtr           pNv
 442 )
 443 {
 444         unsigned DeltaNew, DeltaOld;
 445         unsigned VClk, Freq;
 446         unsigned M, N, P;
 447         unsigned lowM, highM, highP;
 448
 449         DeltaOld = 0xFFFFFFFF;
 450
 451         *pllBOut = 0x80000401;  /* fixed at x4 for now */
 452
 453         VClk = (unsigned)clockIn;
 454
 455         /* Taken from Haiku, after someone with an NV28 had an issue */
 456         switch(pNv->NVArch) {
 457                 case 0x28:
 458                         lowM = 1;
 459                         highP = 32;
 460                         if (VClk > 340000) {
 461                                 highM = 2;
 462                         } else if (VClk > 200000) {
 463                                 highM = 4;
 464                         } else if (VClk > 150000) {
 465                                 highM = 6;
 466                         } else {
 467                                 highM = 14;
 468                         }
 469                         break;
 470                 default:
 471                         lowM = 1;
 472                         highP = 15;
 473                         if (VClk > 340000) {
 474                                 highM = 2;
 475                         } else if (VClk > 250000) {
 476                                 highM = 6;
 477                         } else {
 478                                 highM = 14;
 479                         }
 480                         break;
 481         }
 482
 483         for (P = 0; P <= highP; P++) {
 484                 Freq = VClk << P;
 485                 if ((Freq >= 400000) && (Freq <= 1000000)) {
 486                         for (M = lowM; M <= highM; M++) {
 487                                 N = ((VClk << P) * M) / (pNv->CrystalFreqKHz << 2);
 488                                 if ((N >= 5) && (N <= 255)) {
 489                                         Freq = (((pNv->CrystalFreqKHz << 2) * N) / M) >> P;
 490                                         if (Freq > VClk) {
 491                                                 DeltaNew = Freq - VClk;
 492                                         } else {
 493                                                 DeltaNew = VClk - Freq;
 494                                         }
 495                                         if (DeltaNew < DeltaOld) {
 496                                                 *pllOut   = (P << 16) | (N << 8) | M;
 497                                                 *clockOut = Freq;
 498                                                 DeltaOld  = DeltaNew;
 499                                         }
 500                                 }
 501                         }
 502                 }
 503         }
 504 }
 505
 506 /* Code taken from NVClock, with permission of the author (being a GPL->MIT code transfer). */
 507
 508 static void
 509 CalculateVClkNV4x_SingleVCO(NVPtr pNv, struct pll_lims *pll_lim, uint32_t clockIn, uint32_t *n1_best, uint32_t *m1_best, uint32_t *p_best)
 510 {
 511         uint32_t clock, M, N, P;
 512         uint32_t delta, bestDelta, minM, maxM, minN, maxN, maxP;
 513         uint32_t minVCOInputFreq, minVCOFreq, maxVCOFreq;
 514         uint32_t VCOFreq;
 515         uint32_t refClk = pNv->CrystalFreqKHz;
 516         bestDelta = clockIn;
 517
 518         /* bios clocks are in MHz, we use KHz */
 519         minVCOInputFreq = pll_lim->vco1.min_inputfreq*1000;
 520         minVCOFreq = pll_lim->vco1.minfreq*1000;
 521         maxVCOFreq = pll_lim->vco1.maxfreq*1000;
 522         minM = pll_lim->vco1.min_m;
 523         maxM = pll_lim->vco1.max_m;
 524         minN = pll_lim->vco1.min_n;
 525         maxN = pll_lim->vco1.max_n;
 526
 527         maxP = 6;
 528
 529         /* The optimal frequency for the PLL to work at is somewhere in the center of its range.
 530         /  Choose a post divider in such a way to achieve this.
 531         /  The G8x nv driver does something similar but they they derive a minP and maxP. That
 532         /  doesn't seem required as you get so many matching clocks that you don't enter a second
 533         /  iteration for P. (The minP / maxP values in the nv driver only differ at most 1, so it is for
 534         /  some rare corner cases.
 535         */
 536         for (P=0, VCOFreq=maxVCOFreq/2; clockIn<=VCOFreq && P <= maxP; P++)
 537         {
 538                 VCOFreq /= 2;
 539         }
 540
 541         /* Calculate the m and n values. There are a lot of values which give the same speed;
 542         /  We choose the speed for which the difference with the request speed is as small as possible.
 543         */
 544         for (M=minM; M<=maxM; M++)
 545         {
 546                 /* The VCO has a minimum input frequency */
 547                 if ((refClk/M) < minVCOInputFreq)
 548                         break;
 549
 550                 for (N=minN; N<=maxN; N++)
 551                 {
 552                         /* Calculate the frequency generated by VCO1 */
 553                         clock = (int)(refClk * N / (float)M);
 554
 555                         /* Verify if the clock lies within the output limits of VCO1 */
 556                         if (clock < minVCOFreq)
 557                                 continue;
 558                         else if (clock > maxVCOFreq) /* It is no use to continue as the clock will only become higher */
 559                                 break;
 560
 561                         clock >>= P;
 562                         delta = abs((int)(clockIn - clock));
 563                         /* When the difference is 0 or less than .5% accept the speed */
 564                         if (((delta == 0) || ((float)delta/(float)clockIn <= 0.005)))
 565                         {
 566                                 *m1_best = M;
 567                                 *n1_best = N;
 568                                 *p_best = P;
 569                                 return;
 570                         }
 571
 572                         /* When the new difference is smaller than the old one, use this one */
 573                         if (delta < bestDelta)
 574                         {
 575                                 bestDelta = delta;
 576                                 *m1_best = M;
 577                                 *n1_best = N;
 578                                 *p_best = P;
 579                         }
 580                 }
 581         }
 582 }
 583
 584 static void
 585 CalculateVClkNV4x_DoubleVCO(NVPtr pNv, struct pll_lims *pll_lim, uint32_t clockIn, uint32_t *n1_best, uint32_t *n2_best, uint32_t *m1_best, uint32_t *m2_best, uint32_t *p_best)
 586 {
 587         uint32_t clock1, clock2, M, M2, N, N2, P;
 588         uint32_t delta, bestDelta, minM, minM2, maxM, maxM2, minN, minN2, maxN, maxN2, maxP;
 589         uint32_t minVCOInputFreq, minVCO2InputFreq, maxVCO2InputFreq, minVCOFreq, minVCO2Freq, maxVCOFreq, maxVCO2Freq;
 590         uint32_t VCO2Freq, maxClock;
 591         uint32_t refClk = pNv->CrystalFreqKHz;
 592         bestDelta = clockIn;
 593
 594         /* bios clocks are in MHz, we use KHz */
 595         minVCOInputFreq = pll_lim->vco1.min_inputfreq*1000;
 596         minVCOFreq = pll_lim->vco1.minfreq*1000;
 597         maxVCOFreq = pll_lim->vco1.maxfreq*1000;
 598         minM = pll_lim->vco1.min_m;
 599         maxM = pll_lim->vco1.max_m;
 600         minN = pll_lim->vco1.min_n;
 601         maxN = pll_lim->vco1.max_n;
 602
 603         minVCO2InputFreq = pll_lim->vco2.min_inputfreq*1000;
 604         maxVCO2InputFreq = pll_lim->vco2.max_inputfreq*1000;
 605         minVCO2Freq = pll_lim->vco2.minfreq*1000;
 606         maxVCO2Freq = pll_lim->vco2.maxfreq*1000;
 607         minM2 = pll_lim->vco2.min_m;
 608         maxM2 = pll_lim->vco2.max_m;
 609         minN2 = pll_lim->vco2.min_n;
 610         maxN2 = pll_lim->vco2.max_n;
 611
 612         maxP = 6;
 613
 614         maxClock = maxVCO2Freq;
 615         /* If the requested clock is behind the bios limits, try it anyway */
 616         if (clockIn > maxVCO2Freq)
 617                 maxClock = clockIn + clockIn/200; /* Add a .5% margin */
 618
 619         /* The optimal frequency for the PLL to work at is somewhere in the center of its range.
 620         /  Choose a post divider in such a way to achieve this.
 621         /  The G8x nv driver does something similar but they they derive a minP and maxP. That
 622         /  doesn't seem required as you get so many matching clocks that you don't enter a second
 623         /  iteration for P. (The minP / maxP values in the nv driver only differ at most 1, so it is for
 624         /  some rare corner cases.
 625         */
 626         for (P=0, VCO2Freq=maxClock/2; clockIn<=VCO2Freq && P <= maxP; P++)
 627         {
 628                 VCO2Freq /= 2;
 629         }
 630
 631         /* The PLLs on Geforce6/7 hardware can operate in a single stage made with only 1 VCO
 632         /  and a cascade mode of two VCOs. This second mode is in general used for relatively high
 633         /  frequencies. The loop below calculates the divider and multiplier ratios for the cascade
 634         /  mode. The code takes into account limits defined in the video bios.
 635         */
 636         for (M=minM; M<=maxM; M++)
 637         {
 638                 /* The VCO has a minimum input frequency */
 639                 if ((refClk/M) < minVCOInputFreq)
 640                         break;
 641
 642                 for (N=minN; N<=maxN; N++)
 643                 {
 644                         /* Calculate the frequency generated by VCO1 */
 645                         clock1 = (int)(refClk * N / (float)M);
 646                         /* Verify if the clock lies within the output limits of VCO1 */
 647                         if ( (clock1 < minVCOFreq) )
 648                                 continue;
 649                         else if (clock1 > maxVCOFreq) /* For future N, the clock will only increase so stop; xorg nv continues but that is useless */
 650                                 break;
 651
 652                         for (M2=minM2; M2<=maxM2; M2++)
 653                         {
 654                                 /* The clock fed to the second VCO needs to lie within a certain input range */
 655                                 if (clock1 / M2 < minVCO2InputFreq)
 656                                         break;
 657                                 else if (clock1 / M2 > maxVCO2InputFreq)
 658                                         continue;
 659
 660                                 N2 = (int)((float)((clockIn << P) * M * M2) / (float)(refClk * N)+.5);
 661                                 if( (N2 < minN2) || (N2 > maxN2) )
 662                                         continue;
 663
 664                                 /* The clock before being fed to the post-divider needs to lie within a certain range.
 665                                 /  Further there are some limits on N2/M2.
 666                                 */
 667                                 clock2 = (int)((float)(N*N2)/(M*M2) * refClk);
 668                                 if( (clock2 < minVCO2Freq) || (clock2 > maxClock))// || ((N2 / M2) < 4) || ((N2 / M2) > 10) )
 669                                         continue;
 670
 671                                 /* The post-divider delays the 'high' clock to create a low clock if requested.
 672                                 /  This post-divider exists because the VCOs can only generate frequencies within
 673                                 /  a limited frequency range. This range has been tuned to lie around half of its max
 674                                 /  input frequency. It tries to calculate all clocks (including lower ones) around this
 675                                 /  'center' frequency.
 676                                 */
 677                                 clock2 >>= P;
 678                                 delta = abs((int)(clockIn - clock2));
 679
 680                                 /* When the difference is 0 or less than .5% accept the speed */
 681                                 if (((delta == 0) || ((float)delta/(float)clockIn <= 0.005)))
 682                                 {
 683                                         *m1_best = M;
 684                                         *m2_best = M2;
 685                                         *n1_best = N;
 686                                         *n2_best = N2;
 687                                         *p_best = P;
 688                                         return;
 689                                 }
 690
 691                                 /* When the new difference is smaller than the old one, use this one */
 692                                 if (delta < bestDelta)
 693                                 {
 694                                         bestDelta = delta;
 695                                         *m1_best = M;
 696                                         *m2_best = M2;
 697                                         *n1_best = N;
 698                                         *n2_best = N2;
 699                                         *p_best = P;
 700                                 }
 701                         }
 702                 }
 703         }
 704 }
 705
 706 /* BIG NOTE: modifying vpll1 and vpll2 does not work, what bit is the switch to allow it? */
 707
 708 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
 709 /* They are only valid for NV4x, appearantly reordered for NV5x */
 710 /* gpu pll: 0x4000 + 0x4004
 711  * unknown pll: 0x4008 + 0x400c
 712  * vpll1: 0x4010 + 0x4014
 713  * vpll2: 0x4018 + 0x401c
 714  * unknown pll: 0x4020 + 0x4024
 715  * unknown pll: 0x4038 + 0x403c
 716  * Some of the unknown's are probably memory pll's.
 717  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
 718  * 1 and 2 refer to the registers of each pair. There is only one post divider.
 719  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
 720  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
 721  *     bit8: A switch that turns of the second divider and multiplier off.
 722  *     bit12: Also a switch, i haven't seen it yet.
 723  *     bit16-19: p-divider
 724  *     but 28-31: Something related to the mode that is used (see bit8).
 725  * 2) bit0-7: m-divider (a)
 726  *     bit8-15: n-multiplier (a)
 727  *     bit16-23: m-divider (b)
 728  *     bit24-31: n-multiplier (b)
 729  */
 730
 731 /* Modifying the gpu pll for example requires:
 732  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 733  * This is not needed for the vpll's which have their own bits.
 734  */
 735
 736 static void
 737 CalculateVClkNV4x(
 738         ScrnInfoPtr pScrn,
 739         uint32_t requested_clock,
 740         uint32_t *given_clock,
 741         uint32_t *pll_a,
 742         uint32_t *pll_b,
 743         uint32_t *reg580,
 744         Bool    *db1_ratio,
 745         Bool primary
 746 )
 747 {
 748         NVPtr pNv = NVPTR(pScrn);
 749         struct pll_lims pll_lim;
 750         /* We have 2 mulitpliers, 2 dividers and one post divider */
 751         /* Note that p is only 3 bits */
 752         uint32_t m1_best = 0, m2_best = 0, n1_best = 0, n2_best = 0, p_best = 0;
 753         uint32_t special_bits = 0;
 754
 755         if (primary) {
 756                 if (!get_bit_pll_limits(pScrn, VPLL1, &pll_lim))
 757                         return;
 758         } else
 759                 if (!get_bit_pll_limits(pScrn, VPLL2, &pll_lim))
 760                         return;
 761
 762         if (requested_clock < pll_lim.vco1.maxfreq*1000) { /* single VCO */
 763                 *db1_ratio = TRUE;
 764                 /* Turn the second set of divider and multiplier off */
 765                 /* Bogus data, the same nvidia uses */
 766                 n2_best = 1;
 767                 m2_best = 31;
 768                 CalculateVClkNV4x_SingleVCO(pNv, &pll_lim, requested_clock, &n1_best, &m1_best, &p_best);
 769         } else { /* dual VCO */
 770                 *db1_ratio = FALSE;
 771                 CalculateVClkNV4x_DoubleVCO(pNv, &pll_lim, requested_clock, &n1_best, &n2_best, &m1_best, &m2_best, &p_best);
 772         }
 773
 774         /* Are this all (relevant) G70 cards? */
 775         if (pNv->NVArch == 0x4B || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
 776                 /* This is a big guess, but should be reasonable until we can narrow it down. */
 777                 if (*db1_ratio) {
 778                         special_bits = 0x1;
 779                 } else {
 780                         special_bits = 0x3;
 781                 }
 782         }
 783
 784         /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
 785         /* Let's keep the special bits, if the bios already set them */
 786         *pll_a = (special_bits << 30) | (p_best << 16) | (n1_best << 8) | (m1_best << 0);
 787         *pll_b = (1 << 31) | (n2_best << 8) | (m2_best << 0);
 788
 789         if (*db1_ratio) {
 790                 if (primary) {
 791                         *reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 792                 } else {
 793                         *reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 794                 }
 795         } else {
 796                 if (primary) {
 797                         *reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
 798                 } else {
 799                         *reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
 800                 }
 801         }
 802
 803         if (*db1_ratio) {
 804                 ErrorF("vpll: n1 %d m1 %d p %d db1_ratio %d\n", n1_best, m1_best, p_best, *db1_ratio);
 805         } else {
 806                 ErrorF("vpll: n1 %d n2 %d m1 %d m2 %d p %d db1_ratio %d\n", n1_best, n2_best, m1_best, m2_best, p_best, *db1_ratio);
 807         }
 808 }
 809
 810 static void nv40_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 811 {
 812         state->vpll1_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 813         state->vpll1_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 814         state->vpll2_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 815         state->vpll2_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 816         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 817         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 818         state->reg580 = nvReadRAMDAC0(pNv, NV_RAMDAC_580);
 819         state->reg594 = nvReadRAMDAC0(pNv, NV_RAMDAC_594);
 820 }
 821
 822 static void nv40_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 823 {
 824         ScrnInfoPtr pScrn = crtc->scrn;
 825         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 826         NVPtr pNv = NVPTR(pScrn);
 827         CARD32 fp_debug_0[2];
 828         uint32_t index[2];
 829         fp_debug_0[0] = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
 830         fp_debug_0[1] = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
 831
 832         uint32_t reg_c040_old = nvReadMC(pNv, 0xc040);
 833
 834         /* The TMDS_PLL switch is on the actual ramdac */
 835         if (state->crosswired) {
 836                 index[0] = 1;
 837                 index[1] = 0;
 838                 ErrorF("Crosswired pll state load\n");
 839         } else {
 840                 index[0] = 0;
 841                 index[1] = 1;
 842         }
 843
 844         if (state->vpll2_b) {
 845                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0,
 846                         fp_debug_0[index[1]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 847
 848                 /* Wait for the situation to stabilise */
 849                 usleep(5000);
 850
 851                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 852                 /* for vpll2 change bits 18 and 19 are disabled */
 853                 reg_c040 &= ~(0x3 << 18);
 854                 nvWriteMC(pNv, 0xc040, reg_c040);
 855
 856                 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 857                 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 858
 859                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2_a);
 860                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 861
 862                 ErrorF("writing pllsel %08X\n", state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 863                 /* Let's keep the primary vpll off */
 864                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 865
 866                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 867                 ErrorF("writing reg580 %08X\n", state->reg580);
 868
 869                 /* We need to wait a while */
 870                 usleep(5000);
 871                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 872
 873                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[1]]);
 874
 875                 /* Wait for the situation to stabilise */
 876                 usleep(5000);
 877         }
 878
 879         if (state->vpll1_b) {
 880                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0,
 881                         fp_debug_0[index[0]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 882
 883                 /* Wait for the situation to stabilise */
 884                 usleep(5000);
 885
 886                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 887                 /* for vpll2 change bits 16 and 17 are disabled */
 888                 reg_c040 &= ~(0x3 << 16);
 889                 nvWriteMC(pNv, 0xc040, reg_c040);
 890
 891                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 892                 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 893
 894                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll1_a);
 895                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpll1_b);
 896
 897                 ErrorF("writing pllsel %08X\n", state->pllsel);
 898                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 899
 900                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 901                 ErrorF("writing reg580 %08X\n", state->reg580);
 902
 903                 /* We need to wait a while */
 904                 usleep(5000);
 905                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 906
 907                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[0]]);
 908
 909                 /* Wait for the situation to stabilise */
 910                 usleep(5000);
 911         }
 912
 913         /* Let's be sure not to wake up any crtc's from dpms. */
 914         /* But we do want to keep our newly set crtc awake. */
 915         if (nv_crtc->head == 1) {
 916                 nvWriteMC(pNv, 0xc040, reg_c040_old | (pNv->misc_info.reg_c040 & (0x3 << 18)));
 917         } else {
 918                 nvWriteMC(pNv, 0xc040, reg_c040_old | (pNv->misc_info.reg_c040 & (0x3 << 16)));
 919         }
 920
 921         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 922         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 923
 924         ErrorF("writing reg594 %08X\n", state->reg594);
 925         nvWriteRAMDAC0(pNv, NV_RAMDAC_594, state->reg594);
 926 }
 927
 928 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 929 {
 930         state->vpll = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 931         if(pNv->twoHeads) {
 932                 state->vpll2 = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 933         }
 934         if(pNv->twoStagePLL) {
 935                 state->vpllB = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 936                 state->vpll2B = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 937         }
 938         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 939         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 940 }
 941
 942
 943 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 944 {
 945         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 946         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 947
 948         if (state->vpll2) {
 949                 if(pNv->twoHeads) {
 950                         ErrorF("writing vpll2 %08X\n", state->vpll2);
 951                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2);
 952                 }
 953                 if(pNv->twoStagePLL) {
 954                         ErrorF("writing vpll2B %08X\n", state->vpll2B);
 955                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2B);
 956                 }
 957         }
 958
 959         if (state->vpll) {
 960                 ErrorF("writing vpll %08X\n", state->vpll);
 961                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll);
 962                 if(pNv->twoStagePLL) {
 963                         ErrorF("writing vpllB %08X\n", state->vpllB);
 964                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpllB);
 965                 }
 966         }
 967
 968         ErrorF("writing pllsel %08X\n", state->pllsel);
 969         nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 970 }
 971
 972 #define IS_NV44P (pNv->NVArch >= 0x44 ? 1 : 0)
 973 #define SEL_CLK_OFFSET (nv_get_sel_clk_offset(pNv->NVArch, nv_output->bus))
 974
 975 #define WIPE_OTHER_CLOCKS(_sel_clk, _head, _bus) (nv_wipe_other_clocks(_sel_clk, pNv->NVArch, _head, _bus))
 976
 977 /*
 978  * Calculate extended mode parameters (SVGA) and save in a
 979  * mode state structure.
 980  * State is not specific to a single crtc, but shared.
 981  */
 982 void nv_crtc_calc_state_ext(
 983         xf86CrtcPtr     crtc,
 984         int                     bpp,
 985         int                     DisplayWidth, /* Does this change after setting the mode? */
 986         int                     CrtcHDisplay,
 987         int                     CrtcVDisplay,
 988         int                     dotClock,
 989         int                     flags
 990 )
 991 {
 992         ScrnInfoPtr pScrn = crtc->scrn;
 993         uint32_t pixelDepth, VClk = 0;
 994         CARD32 CursorStart;
 995         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 996         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 997         NVCrtcRegPtr regp;
 998         NVPtr pNv = NVPTR(pScrn);
 999         RIVA_HW_STATE *state;
1000         int num_crtc_enabled, i;
1001
1002         state = &pNv->ModeReg;
1003
1004         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1005
1006         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1007         NVOutputPrivatePtr nv_output = NULL;
1008         if (output) {
1009                 nv_output = output->driver_private;
1010         }
1011
1012         /*
1013          * Extended RIVA registers.
1014          */
1015         pixelDepth = (bpp + 1)/8;
1016         if (pNv->Architecture == NV_ARCH_40) {
1017                 /* Does register 0x580 already have a value? */
1018                 if (!state->reg580) {
1019                         state->reg580 = pNv->misc_info.ramdac_0_reg_580;
1020                 }
1021                 if (nv_crtc->head == 1) {
1022                         CalculateVClkNV4x(pScrn, dotClock, &VClk, &state->vpll2_a, &state->vpll2_b, &state->reg580, &state->db1_ratio[1], FALSE);
1023                 } else {
1024                         CalculateVClkNV4x(pScrn, dotClock, &VClk, &state->vpll1_a, &state->vpll1_b, &state->reg580, &state->db1_ratio[0], TRUE);
1025                 }
1026         } else if (pNv->twoStagePLL) {
1027                 CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB, pNv);
1028         } else {
1029                 CalcVClock(dotClock, &VClk, &state->pll, pNv);
1030         }
1031
1032         switch (pNv->Architecture) {
1033         case NV_ARCH_04:
1034                 nv4UpdateArbitrationSettings(VClk,
1035                                                 pixelDepth * 8,
1036                                                 &(state->arbitration0),
1037                                                 &(state->arbitration1),
1038                                                 pNv);
1039                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
1040                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
1041                 if (flags & V_DBLSCAN)
1042                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
1043                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
1044                 state->pllsel   |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
1045                 state->config   = 0x00001114;
1046                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
1047                 break;
1048         case NV_ARCH_10:
1049         case NV_ARCH_20:
1050         case NV_ARCH_30:
1051         default:
1052                 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
1053                         ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
1054                         state->arbitration0 = 128;
1055                         state->arbitration1 = 0x0480;
1056                 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
1057                         ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
1058                         nForceUpdateArbitrationSettings(VClk,
1059                                                 pixelDepth * 8,
1060                                                 &(state->arbitration0),
1061                                                 &(state->arbitration1),
1062                                                 pNv);
1063                 } else if (pNv->Architecture < NV_ARCH_30) {
1064                         nv10UpdateArbitrationSettings(VClk,
1065                                                 pixelDepth * 8,
1066                                                 &(state->arbitration0),
1067                                                 &(state->arbitration1),
1068                                                 pNv);
1069                 } else {
1070                         nv30UpdateArbitrationSettings(pNv,
1071                                                 &(state->arbitration0),
1072                                                 &(state->arbitration1));
1073                 }
1074
1075                 if (nv_crtc->head == 1) {
1076                         CursorStart = pNv->Cursor2->offset;
1077                 } else {
1078                         CursorStart = pNv->Cursor->offset;
1079                 }
1080
1081                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
1082                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
1083                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
1084
1085                 if (flags & V_DBLSCAN)
1086                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
1087
1088                 state->config   = nvReadFB(pNv, NV_PFB_CFG0);
1089                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
1090                 break;
1091         }
1092
1093         /* okay do we have 2 CRTCs running ? */
1094         num_crtc_enabled = 0;
1095         for (i = 0; i < xf86_config->num_crtc; i++) {
1096                 if (xf86_config->crtc[i]->enabled) {
1097                         num_crtc_enabled++;
1098                 }
1099         }
1100
1101         ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
1102
1103         if (pNv->Architecture < NV_ARCH_40) {
1104                 /* We need this before the next code */
1105                 if (nv_crtc->head == 1) {
1106                         state->vpll2 = state->pll;
1107                         state->vpll2B = state->pllB;
1108                 } else {
1109                         state->vpll = state->pll;
1110                         state->vpllB = state->pllB;
1111                 }
1112         }
1113
1114         /* The main stuff seems to be valid for NV3x also. */
1115         if (pNv->Architecture >= NV_ARCH_30) {
1116                 /* This register is only used on the primary ramdac */
1117                 /* This seems to be needed to select the proper clocks, otherwise bad things happen */
1118
1119                 if (!state->sel_clk)
1120                         state->sel_clk = pNv->misc_info.sel_clk & ~(0xf << 16);
1121
1122                 if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
1123                         /* Only wipe when are a relevant (digital) output. */
1124                         state->sel_clk &= ~(0xf << 16);
1125                         Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1126                         /* Even with two dvi, this should not conflict. */
1127                         if (crossed_clocks) {
1128                                 state->sel_clk |= (0x1 << 16);
1129                         } else {
1130                                 state->sel_clk |= (0x4 << 16);
1131                         }
1132                 }
1133
1134                 /* Some cards, specifically dual dvi/lvds cards set another bitrange.
1135                  * I suspect inverse beheaviour to the normal bitrange, but i am not a 100% certain about this.
1136                  * This is all based on default settings found in mmio-traces.
1137                  * The blob never changes these, as it doesn't run unusual output configurations.
1138                  * It seems to prefer situations that avoid changing these bits (for a good reason?).
1139                  * I still don't know the purpose of value 2, it's similar to 4, but what exactly does it do?
1140                  */
1141
1142                 /* Some extra info:
1143                  * nv30:
1144                  *      bit 0           NVClk spread spectrum on/off
1145                  *      bit 2           MemClk spread spectrum on/off
1146                  *      bit 4           PixClk1 spread spectrum on/off
1147                  *      bit 6           PixClk2 spread spectrum on/off
1148
1149                  *      nv40:
1150                  *      what causes setting of bits not obvious but:
1151                  *      bits 4&5                relate to headA
1152                  *      bits 6&7                relate to headB
1153                 */
1154                 if (pNv->Architecture == NV_ARCH_40) {
1155                         for (i = 0; i < 4; i++) {
1156                                 uint32_t var = (state->sel_clk & (0xf << 4*i)) >> 4*i;
1157                                 if (var == 0x1 || var == 0x4) {
1158                                         state->sel_clk &= ~(0xf << 4*i);
1159                                         Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1160                                         if (crossed_clocks) {
1161                                                 state->sel_clk |= (0x4 << 4*i);
1162                                         } else {
1163                                                 state->sel_clk |= (0x1 << 4*i);
1164                                         }
1165                                         break; /* This should only occur once. */
1166                                 }
1167                         }
1168                 }
1169
1170                 /* Are we crosswired? */
1171                 if (output && nv_crtc->head != nv_output->preferred_output) {
1172                         state->crosswired = TRUE;
1173                 } else {
1174                         state->crosswired = FALSE;
1175                 }
1176
1177                 if (nv_crtc->head == 1) {
1178                         if (state->db1_ratio[1])
1179                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1180                 } else if (nv_crtc->head == 0) {
1181                         if (state->db1_ratio[0])
1182                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1183                 }
1184         } else {
1185                 /* Do NV1x/NV2x cards need anything in sel_clk? */
1186                 state->sel_clk = 0x0;
1187                 state->crosswired = FALSE;
1188         }
1189
1190         /* The NV40 seems to have more similarities to NV3x than other cards. */
1191         if (pNv->NVArch < 0x41) {
1192                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL;
1193                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL;
1194         }
1195
1196         if (nv_crtc->head == 1) {
1197                 if (!state->db1_ratio[1]) {
1198                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1199                 } else {
1200                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1201                 }
1202                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
1203         } else {
1204                 if (!state->db1_ratio[0]) {
1205                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1206                 } else {
1207                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1208                 }
1209                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
1210         }
1211
1212         /* The blob uses this always, so let's do the same */
1213         if (pNv->Architecture == NV_ARCH_40) {
1214                 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
1215         }
1216
1217         /* The primary output doesn't seem to care */
1218         if (nv_output->preferred_output == 1) { /* This is the "output" */
1219                 /* non-zero values are for analog, don't know about tv-out and the likes */
1220                 if (output && nv_output->type != OUTPUT_ANALOG) {
1221                         state->reg594 = 0x0;
1222                 } else {
1223                         /* Are we a flexible output? */
1224                         if (ffs(pNv->dcb_table.entry[nv_output->dcb_entry].or) & OUTPUT_0) {
1225                                 state->reg594 = 0x1;
1226                                 pNv->restricted_mode = FALSE;
1227                         } else {
1228                                 state->reg594 = 0x0;
1229                                 pNv->restricted_mode = TRUE;
1230                         }
1231
1232                         /* More values exist, but they seem related to the 3rd dac (tv-out?) somehow */
1233                         /* bit 16-19 are bits that are set on some G70 cards */
1234                         /* Those bits are also set to the 3rd OUTPUT register */
1235                         if (nv_crtc->head == 1) {
1236                                 state->reg594 |= 0x100;
1237                         }
1238                 }
1239         }
1240
1241         regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
1242         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
1243         if (pNv->Architecture >= NV_ARCH_30) {
1244                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
1245         }
1246
1247         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
1248         regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
1249 }
1250
1251 static void
1252 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
1253 {
1254         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1255         ScrnInfoPtr pScrn = crtc->scrn;
1256         NVPtr pNv = NVPTR(pScrn);
1257         unsigned char seq1 = 0, crtc17 = 0;
1258         unsigned char crtc1A;
1259
1260         ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->head, mode);
1261
1262         NVCrtcSetOwner(crtc);
1263
1264         crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
1265         switch(mode) {
1266                 case DPMSModeStandby:
1267                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
1268                 seq1 = 0x20;
1269                 crtc17 = 0x80;
1270                 crtc1A |= 0x80;
1271                 break;
1272         case DPMSModeSuspend:
1273                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
1274                 seq1 = 0x20;
1275                 crtc17 = 0x80;
1276                 crtc1A |= 0x40;
1277                 break;
1278         case DPMSModeOff:
1279                 /* Screen: Off; HSync: Off, VSync: Off */
1280                 seq1 = 0x20;
1281                 crtc17 = 0x00;
1282                 crtc1A |= 0xC0;
1283                 break;
1284         case DPMSModeOn:
1285         default:
1286                 /* Screen: On; HSync: On, VSync: On */
1287                 seq1 = 0x00;
1288                 crtc17 = 0x80;
1289                 break;
1290         }
1291
1292         NVVgaSeqReset(crtc, TRUE);
1293         /* Each head has it's own sequencer, so we can turn it off when we want */
1294         seq1 |= (NVReadVgaSeq(crtc, 0x01) & ~0x20);
1295         NVWriteVgaSeq(crtc, 0x1, seq1);
1296         crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
1297         usleep(10000);
1298         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
1299         NVVgaSeqReset(crtc, FALSE);
1300
1301         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
1302
1303         /* We can completely disable a vpll if the crtc is off. */
1304         if (pNv->Architecture == NV_ARCH_40) {
1305                 uint32_t reg_c040_old = nvReadMC(pNv, 0xc040);
1306                 if (mode == DPMSModeOn) {
1307                         nvWriteMC(pNv, 0xc040, reg_c040_old | (pNv->misc_info.reg_c040 & (0x3 << (16 + 2*nv_crtc->head))));
1308                 } else {
1309                         nvWriteMC(pNv, 0xc040, reg_c040_old & ~(pNv->misc_info.reg_c040 & (0x3 << (16 + 2*nv_crtc->head))));
1310                 }
1311         }
1312
1313         /* I hope this is the right place */
1314         if (crtc->enabled && mode == DPMSModeOn) {
1315                 pNv->crtc_active[nv_crtc->head] = TRUE;
1316         } else {
1317                 pNv->crtc_active[nv_crtc->head] = FALSE;
1318         }
1319 }
1320
1321 static Bool
1322 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
1323                      DisplayModePtr adjusted_mode)
1324 {
1325         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1326         ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->head);
1327
1328         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1329         NVOutputPrivatePtr nv_output = NULL;
1330         if (output) {
1331                 nv_output = output->driver_private;
1332         }
1333
1334         /* For internal panels and gpu scaling on DVI we need the native mode */
1335         if (output && (nv_output->type == OUTPUT_LVDS || (nv_output->type == OUTPUT_TMDS && nv_output->scaling_mode != SCALE_PANEL))) {
1336                 adjusted_mode->HDisplay = nv_output->native_mode->HDisplay;
1337                 adjusted_mode->HSkew = nv_output->native_mode->HSkew;
1338                 adjusted_mode->HSyncStart = nv_output->native_mode->HSyncStart;
1339                 adjusted_mode->HSyncEnd = nv_output->native_mode->HSyncEnd;
1340                 adjusted_mode->HTotal = nv_output->native_mode->HTotal;
1341                 adjusted_mode->VDisplay = nv_output->native_mode->VDisplay;
1342                 adjusted_mode->VScan = nv_output->native_mode->VScan;
1343                 adjusted_mode->VSyncStart = nv_output->native_mode->VSyncStart;
1344                 adjusted_mode->VSyncEnd = nv_output->native_mode->VSyncEnd;
1345                 adjusted_mode->VTotal = nv_output->native_mode->VTotal;
1346                 adjusted_mode->Clock = nv_output->native_mode->Clock;
1347
1348                 xf86SetModeCrtc(adjusted_mode, INTERLACE_HALVE_V);
1349         }
1350
1351         return TRUE;
1352 }
1353
1354 static void
1355 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1356 {
1357         ScrnInfoPtr pScrn = crtc->scrn;
1358         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1359         NVCrtcRegPtr regp;
1360         NVPtr pNv = NVPTR(pScrn);
1361         NVFBLayout *pLayout = &pNv->CurrentLayout;
1362         int depth = pScrn->depth;
1363
1364         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1365
1366         /* Calculate our timings */
1367         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
1368         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
1369         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
1370         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
1371         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
1372         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
1373         int vertDisplay         = mode->CrtcVDisplay                    - 1;
1374         int vertStart           = mode->CrtcVSyncStart          - 1;
1375         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
1376         int vertTotal           = mode->CrtcVTotal                      - 2;
1377         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
1378         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
1379
1380         Bool is_fp = FALSE;
1381
1382         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1383         NVOutputPrivatePtr nv_output = NULL;
1384         if (output) {
1385                 nv_output = output->driver_private;
1386
1387                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1388                         is_fp = TRUE;
1389         }
1390
1391         ErrorF("Mode clock: %d\n", mode->Clock);
1392         ErrorF("Adjusted mode clock: %d\n", adjusted_mode->Clock);
1393
1394         /* Reverted to what nv did, because that works for all resolutions on flatpanels */
1395         if (is_fp) {
1396                 vertStart = vertTotal - 3;
1397                 vertEnd = vertTotal - 2;
1398                 vertBlankStart = vertStart;
1399                 horizStart = horizTotal - 5;
1400                 horizEnd = horizTotal - 2;
1401                 horizBlankEnd = horizTotal + 4;
1402                 if (pNv->overlayAdaptor) {
1403                         /* This reportedly works around Xv some overlay bandwidth problems*/
1404                         horizTotal += 2;
1405                 }
1406         }
1407
1408         if(mode->Flags & V_INTERLACE)
1409                 vertTotal |= 1;
1410
1411         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
1412         ErrorF("horizStart: 0x%X \n", horizStart);
1413         ErrorF("horizEnd: 0x%X \n", horizEnd);
1414         ErrorF("horizTotal: 0x%X \n", horizTotal);
1415         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
1416         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
1417         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
1418         ErrorF("vertStart: 0x%X \n", vertStart);
1419         ErrorF("vertEnd: 0x%X \n", vertEnd);
1420         ErrorF("vertTotal: 0x%X \n", vertTotal);
1421         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
1422         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
1423
1424         /*
1425         * compute correct Hsync & Vsync polarity
1426         */
1427         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
1428                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
1429
1430                 regp->MiscOutReg = 0x23;
1431                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
1432                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
1433         } else {
1434                 int VDisplay = mode->VDisplay;
1435                 if (mode->Flags & V_DBLSCAN)
1436                         VDisplay *= 2;
1437                 if (mode->VScan > 1)
1438                         VDisplay *= mode->VScan;
1439                 if (VDisplay < 400) {
1440                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
1441                 } else if (VDisplay < 480) {
1442                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
1443                 } else if (VDisplay < 768) {
1444                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
1445                 } else {
1446                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
1447                 }
1448         }
1449
1450         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
1451
1452         /*
1453         * Time Sequencer
1454         */
1455         if (depth == 4) {
1456                 regp->Sequencer[0] = 0x02;
1457         } else {
1458                 regp->Sequencer[0] = 0x00;
1459         }
1460         /* 0x20 disables the sequencer */
1461         if (mode->Flags & V_CLKDIV2) {
1462                 regp->Sequencer[1] = 0x29;
1463         } else {
1464                 regp->Sequencer[1] = 0x21;
1465         }
1466         if (depth == 1) {
1467                 regp->Sequencer[2] = 1 << BIT_PLANE;
1468         } else {
1469                 regp->Sequencer[2] = 0x0F;
1470                 regp->Sequencer[3] = 0x00;                     /* Font select */
1471         }
1472         if (depth < 8) {
1473                 regp->Sequencer[4] = 0x06;                             /* Misc */
1474         } else {
1475                 regp->Sequencer[4] = 0x0E;                             /* Misc */
1476         }
1477
1478         /*
1479         * CRTC Controller
1480         */
1481         regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
1482         regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
1483         regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
1484         regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0)
1485                                 | SetBit(7);
1486         regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
1487         regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
1488                                 | SetBitField(horizEnd,4:0,4:0);
1489         regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
1490         regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
1491                                 | SetBitField(vertDisplay,8:8,1:1)
1492                                 | SetBitField(vertStart,8:8,2:2)
1493                                 | SetBitField(vertBlankStart,8:8,3:3)
1494                                 | SetBit(4)
1495                                 | SetBitField(vertTotal,9:9,5:5)
1496                                 | SetBitField(vertDisplay,9:9,6:6)
1497                                 | SetBitField(vertStart,9:9,7:7);
1498         regp->CRTC[NV_VGA_CRTCX_PRROWSCN]  = 0x00;
1499         regp->CRTC[NV_VGA_CRTCX_MAXSCLIN]  = SetBitField(vertBlankStart,9:9,5:5)
1500                                 | SetBit(6)
1501                                 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00);
1502         regp->CRTC[NV_VGA_CRTCX_VGACURCTRL] = 0x00;
1503         regp->CRTC[0xb] = 0x00;
1504         regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00;
1505         regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
1506         regp->CRTC[0xe] = 0x00;
1507         regp->CRTC[0xf] = 0x00;
1508         regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
1509         regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
1510         regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
1511         regp->CRTC[0x14] = 0x00;
1512         regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
1513         regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
1514         regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
1515         /* 0x80 enables the sequencer, we don't want that */
1516         if (depth < 8) {
1517                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xE3 & ~0x80;
1518         } else {
1519                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80;
1520         }
1521         regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
1522
1523         /*
1524          * Some extended CRTC registers (they are not saved with the rest of the vga regs).
1525          */
1526
1527         regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
1528                                 | SetBitField(vertBlankStart,10:10,3:3)
1529                                 | SetBitField(vertStart,10:10,2:2)
1530                                 | SetBitField(vertDisplay,10:10,1:1)
1531                                 | SetBitField(vertTotal,10:10,0:0);
1532
1533         regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
1534                                 | SetBitField(horizDisplay,8:8,1:1)
1535                                 | SetBitField(horizBlankStart,8:8,2:2)
1536                                 | SetBitField(horizStart,8:8,3:3);
1537
1538         regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
1539                                 | SetBitField(vertDisplay,11:11,2:2)
1540                                 | SetBitField(vertStart,11:11,4:4)
1541                                 | SetBitField(vertBlankStart,11:11,6:6);
1542
1543         if(mode->Flags & V_INTERLACE) {
1544                 horizTotal = (horizTotal >> 1) & ~1;
1545                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
1546                 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
1547         } else {
1548                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff;  /* interlace off */
1549         }
1550
1551         /*
1552         * Theory resumes here....
1553         */
1554
1555         /*
1556         * Graphics Display Controller
1557         */
1558         regp->Graphics[0] = 0x00;
1559         regp->Graphics[1] = 0x00;
1560         regp->Graphics[2] = 0x00;
1561         regp->Graphics[3] = 0x00;
1562         if (depth == 1) {
1563                 regp->Graphics[4] = BIT_PLANE;
1564                 regp->Graphics[5] = 0x00;
1565         } else {
1566                 regp->Graphics[4] = 0x00;
1567                 if (depth == 4) {
1568                         regp->Graphics[5] = 0x02;
1569                 } else {
1570                         regp->Graphics[5] = 0x40;
1571                 }
1572         }
1573         regp->Graphics[6] = 0x05;   /* only map 64k VGA memory !!!! */
1574         regp->Graphics[7] = 0x0F;
1575         regp->Graphics[8] = 0xFF;
1576
1577         /* I ditched the mono stuff */
1578         regp->Attribute[0]  = 0x00; /* standard colormap translation */
1579         regp->Attribute[1]  = 0x01;
1580         regp->Attribute[2]  = 0x02;
1581         regp->Attribute[3]  = 0x03;
1582         regp->Attribute[4]  = 0x04;
1583         regp->Attribute[5]  = 0x05;
1584         regp->Attribute[6]  = 0x06;
1585         regp->Attribute[7]  = 0x07;
1586         regp->Attribute[8]  = 0x08;
1587         regp->Attribute[9]  = 0x09;
1588         regp->Attribute[10] = 0x0A;
1589         regp->Attribute[11] = 0x0B;
1590         regp->Attribute[12] = 0x0C;
1591         regp->Attribute[13] = 0x0D;
1592         regp->Attribute[14] = 0x0E;
1593         regp->Attribute[15] = 0x0F;
1594         /* These two below are non-vga */
1595         regp->Attribute[16] = 0x01;
1596         regp->Attribute[17] = 0x00;
1597         regp->Attribute[18] = 0x0F;
1598         regp->Attribute[19] = 0x00;
1599         regp->Attribute[20] = 0x00;
1600 }
1601
1602 #define MAX_H_VALUE(i) ((0x1ff + i) << 3)
1603 #define MAX_V_VALUE(i) ((0xfff + i) << 0)
1604
1605 /**
1606  * Sets up registers for the given mode/adjusted_mode pair.
1607  *
1608  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1609  *
1610  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1611  * be easily turned on/off after this.
1612  */
1613 static void
1614 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1615 {
1616         ScrnInfoPtr pScrn = crtc->scrn;
1617         NVPtr pNv = NVPTR(pScrn);
1618         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1619         NVFBLayout *pLayout = &pNv->CurrentLayout;
1620         NVCrtcRegPtr regp, savep;
1621         unsigned int i;
1622         Bool is_fp = FALSE;
1623
1624         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1625         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1626
1627         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1628         NVOutputPrivatePtr nv_output = NULL;
1629         if (output) {
1630                 nv_output = output->driver_private;
1631
1632                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1633                         is_fp = TRUE;
1634         }
1635
1636         /* Registers not directly related to the (s)vga mode */
1637
1638         /* bit2 = 0 -> fine pitched crtc granularity */
1639         /* The rest disables double buffering on CRTC access */
1640         regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
1641
1642         if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
1643                 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1644                 if (nv_crtc->head == 0) {
1645                         regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1646                 }
1647
1648                 if (is_fp) {
1649                         regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0) | (1 << 1);
1650                 }
1651         } else {
1652                 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
1653                 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
1654         }
1655
1656         /* Sometimes 0x10 is used, what is this? */
1657         regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1658         /* Some kind of tmds switch for older cards */
1659         if (pNv->Architecture < NV_ARCH_40) {
1660                 regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
1661         }
1662
1663         /*
1664         * Initialize DAC palette.
1665         */
1666         if(pLayout->bitsPerPixel != 8 ) {
1667                 for (i = 0; i < 256; i++) {
1668                         regp->DAC[i*3]     = i;
1669                         regp->DAC[(i*3)+1] = i;
1670                         regp->DAC[(i*3)+2] = i;
1671                 }
1672         }
1673
1674         /*
1675         * Calculate the extended registers.
1676         */
1677
1678         if(pLayout->depth < 24) {
1679                 i = pLayout->depth;
1680         } else {
1681                 i = 32;
1682         }
1683
1684         /* What is the meaning of this register? */
1685         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1686         regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
1687
1688         /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1689         /* But what are those special conditions? */
1690         if (pNv->Architecture <= NV_ARCH_30) {
1691                 if (is_fp) {
1692                         if(nv_crtc->head == 1) {
1693                                 regp->head |= NV_CRTC_FSEL_FPP1;
1694                         } else if (pNv->twoHeads) {
1695                                 regp->head |= NV_CRTC_FSEL_FPP2;
1696                         }
1697                 }
1698         } else {
1699                 /* Some G70 cards have either FPP1 or FPP2 set, copy this if it's already present */
1700                 if (nv_crtc->head == 1 && pNv->NVArch > 0x44) {
1701                         regp->head |= savep->head & (NV_CRTC_FSEL_FPP1 | NV_CRTC_FSEL_FPP2);
1702                 }
1703         }
1704
1705         /* Except for rare conditions I2C is enabled on the primary crtc */
1706         if (nv_crtc->head == 0) {
1707                 if (pNv->overlayAdaptor) {
1708                         regp->head |= NV_CRTC_FSEL_OVERLAY;
1709                 }
1710                 regp->head |= NV_CRTC_FSEL_I2C;
1711         }
1712
1713         /* This is not what nv does, but it is what the blob does (for nv4x at least) */
1714         /* This fixes my cursor corruption issue */
1715         regp->cursorConfig = 0x0;
1716         if(mode->Flags & V_DBLSCAN)
1717                 regp->cursorConfig |= (1 << 4);
1718         if (pNv->alphaCursor) {
1719                 /* bit28 means we go into alpha blend mode and not rely on the current ROP */
1720                 regp->cursorConfig |= 0x14011000;
1721         } else {
1722                 regp->cursorConfig |= 0x02000000;
1723         }
1724
1725         /* Unblock some timings */
1726         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1727         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1728
1729         /* What is the purpose of this register? */
1730         /* 0x14 may be disabled? */
1731         regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1732
1733         /* 0x00 is disabled, 0x22 crt and 0x88 dfp */
1734         /* 0x11 is LVDS? */
1735         if (is_fp) {
1736                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1737         } else {
1738                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1739         }
1740
1741         /* These values seem to vary */
1742         if (nv_crtc->head == 1) {
1743                 regp->CRTC[NV_VGA_CRTCX_3C] = 0x0;
1744         } else {
1745                 regp->CRTC[NV_VGA_CRTCX_3C] = 0x70;
1746         }
1747
1748         /* 0x80 seems to be used very often, if not always */
1749         regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1750
1751         if (nv_crtc->head == 1) {
1752                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x0;
1753         } else {
1754                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x1;
1755         }
1756
1757         if (is_fp)
1758                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x80;
1759
1760         /* Are these(0x55 and 0x56) also timing related registers, since disabling them does nothing? */
1761         regp->CRTC[NV_VGA_CRTCX_55] = 0x0;
1762
1763         /* Common values like 0x14 and 0x04 are converted to 0x10 and 0x00 */
1764         regp->CRTC[NV_VGA_CRTCX_56] = 0x0;
1765
1766         /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1*/
1767         if (nv_crtc->head == 1) {
1768                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52;
1769         } else {
1770                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52 + 4;
1771         }
1772
1773         /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1774         regp->unk81c = nvReadCRTC0(pNv, NV_CRTC_081C);
1775
1776         regp->unk830 = mode->CrtcVDisplay - 3;
1777         regp->unk834 = mode->CrtcVDisplay - 1;
1778
1779         /* This is what the blob does */
1780         regp->unk850 = nvReadCRTC(pNv, 0, NV_CRTC_0850);
1781
1782         /* Never ever modify gpio, unless you know very well what you're doing */
1783         regp->gpio = nvReadCRTC(pNv, 0, NV_CRTC_GPIO);
1784
1785         /* Switch to non-vga mode (the so called HSYNC mode) */
1786         regp->config = 0x2;
1787
1788         /* Some misc regs */
1789         regp->CRTC[NV_VGA_CRTCX_43] = 0x1;
1790         if (pNv->Architecture == NV_ARCH_40) {
1791                 regp->CRTC[NV_VGA_CRTCX_85] = 0xFF;
1792                 regp->CRTC[NV_VGA_CRTCX_86] = 0x1;
1793         }
1794
1795         /*
1796          * Calculate the state that is common to all crtc's (stored in the state struct).
1797          */
1798         ErrorF("crtc %d %d %d\n", nv_crtc->head, mode->CrtcHDisplay, pScrn->displayWidth);
1799         nv_crtc_calc_state_ext(crtc,
1800                                 i,
1801                                 pScrn->displayWidth,
1802                                 mode->CrtcHDisplay,
1803                                 mode->CrtcVDisplay,
1804                                 adjusted_mode->Clock,
1805                                 mode->Flags);
1806
1807         /* Enable slaved mode */
1808         if (is_fp) {
1809                 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1810         }
1811 }
1812
1813 static void
1814 nv_crtc_mode_set_ramdac_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1815 {
1816         ScrnInfoPtr pScrn = crtc->scrn;
1817         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1818         NVCrtcRegPtr regp;
1819         NVPtr pNv = NVPTR(pScrn);
1820         NVFBLayout *pLayout = &pNv->CurrentLayout;
1821         Bool is_fp = FALSE;
1822         Bool is_lvds = FALSE;
1823         float aspect_ratio, panel_ratio;
1824         uint32_t h_scale, v_scale;
1825
1826         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1827
1828         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1829         NVOutputPrivatePtr nv_output = NULL;
1830         if (output) {
1831                 nv_output = output->driver_private;
1832
1833                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1834                         is_fp = TRUE;
1835
1836                 if (nv_output->type == OUTPUT_LVDS)
1837                         is_lvds = TRUE;
1838         }
1839
1840         if (is_fp) {
1841                 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
1842                 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
1843                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HDisplay;
1844                 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
1845                 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
1846                 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
1847                 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
1848
1849                 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
1850                 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
1851                 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VDisplay;
1852                 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
1853                 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
1854                 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
1855                 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
1856
1857                 ErrorF("Horizontal:\n");
1858                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
1859                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
1860                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
1861                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
1862                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
1863                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
1864                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
1865
1866                 ErrorF("Vertical:\n");
1867                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
1868                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
1869                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
1870                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
1871                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
1872                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
1873                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
1874         }
1875
1876         /*
1877         * bit0: positive vsync
1878         * bit4: positive hsync
1879         * bit8: enable center mode
1880         * bit9: enable native mode
1881         * bit26: a bit sometimes seen on some g70 cards
1882         * bit31: set for dual link LVDS
1883         * nv10reg contains a few more things, but i don't quite get what it all means.
1884         */
1885
1886         if (pNv->Architecture >= NV_ARCH_30) {
1887                 regp->fp_control = 0x01100000;
1888         } else {
1889                 regp->fp_control = 0x00000000;
1890         }
1891
1892         if (is_fp) {
1893                 regp->fp_control |= (1 << 28);
1894         } else {
1895                 regp->fp_control |= (2 << 28);
1896                 if (pNv->Architecture < NV_ARCH_30)
1897                         regp->fp_control |= (1 << 24);
1898         }
1899
1900         if (is_lvds && pNv->VBIOS.fp.dual_link) {
1901                 regp->fp_control |= (8 << 28);
1902         } else {
1903                 /* If the special bit exists, it exists on both ramdac's */
1904                 regp->fp_control |= nvReadRAMDAC0(pNv, NV_RAMDAC_FP_CONTROL) & (1 << 26);
1905         }
1906
1907         if (is_fp) {
1908                 if (nv_output->scaling_mode == SCALE_PANEL) { /* panel needs to scale */
1909                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
1910                 /* This is also true for panel scaling, so we must put the panel scale check first */
1911                 } else if (mode->Clock == adjusted_mode->Clock) { /* native mode */
1912                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
1913                 } else { /* gpu needs to scale */
1914                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1915                 }
1916         }
1917
1918         /* Deal with vsync/hsync polarity */
1919         if (is_fp) {
1920                 if (adjusted_mode->Flags & V_PVSYNC) {
1921                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
1922                 }
1923
1924                 if (adjusted_mode->Flags & V_PHSYNC) {
1925                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
1926                 }
1927         } else {
1928                 /* The blob doesn't always do this, but often */
1929                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_VSYNC_DISABLE;
1930                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_HSYNC_DISABLE;
1931         }
1932
1933         if (is_fp) {
1934                 ErrorF("Pre-panel scaling\n");
1935                 ErrorF("panel-size:%dx%d\n", nv_output->fpWidth, nv_output->fpHeight);
1936                 panel_ratio = (nv_output->fpWidth)/(float)(nv_output->fpHeight);
1937                 ErrorF("panel_ratio=%f\n", panel_ratio);
1938                 aspect_ratio = (mode->HDisplay)/(float)(mode->VDisplay);
1939                 ErrorF("aspect_ratio=%f\n", aspect_ratio);
1940                 /* Scale factors is the so called 20.12 format, taken from Haiku */
1941                 h_scale = ((1 << 12) * mode->HDisplay)/nv_output->fpWidth;
1942                 v_scale = ((1 << 12) * mode->VDisplay)/nv_output->fpHeight;
1943                 ErrorF("h_scale=%d\n", h_scale);
1944                 ErrorF("v_scale=%d\n", v_scale);
1945
1946                 /* This can override HTOTAL and VTOTAL */
1947                 regp->debug_2 = 0;
1948
1949                 /* We want automatic scaling */
1950                 regp->debug_1 = 0;
1951
1952                 regp->fp_hvalid_start = 0;
1953                 regp->fp_hvalid_end = (nv_output->fpWidth - 1);
1954
1955                 regp->fp_vvalid_start = 0;
1956                 regp->fp_vvalid_end = (nv_output->fpHeight - 1);
1957
1958                 /* 0 = panel scaling */
1959                 if (nv_output->scaling_mode == SCALE_PANEL) {
1960                         ErrorF("Flat panel is doing the scaling.\n");
1961                 } else {
1962                         ErrorF("GPU is doing the scaling.\n");
1963
1964                         if (nv_output->scaling_mode == SCALE_ASPECT) {
1965                                 /* GPU scaling happens automaticly at a ratio of 1.33 */
1966                                 /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
1967                                 if (h_scale != (1 << 12) && (panel_ratio > (aspect_ratio + 0.10))) {
1968                                         uint32_t diff;
1969
1970                                         ErrorF("Scaling resolution on a widescreen panel\n");
1971
1972                                         /* Scaling in both directions needs to the same */
1973                                         h_scale = v_scale;
1974
1975                                         /* Set a new horizontal scale factor and enable testmode (bit12) */
1976                                         regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
1977
1978                                         diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
1979                                         regp->fp_hvalid_start = diff/2;
1980                                         regp->fp_hvalid_end = nv_output->fpWidth - (diff/2) - 1;
1981                                 }
1982
1983                                 /* Same scaling, just for panels with aspect ratio's smaller than 1 */
1984                                 if (v_scale != (1 << 12) && (panel_ratio < (aspect_ratio - 0.10))) {
1985                                         uint32_t diff;
1986
1987                                         ErrorF("Scaling resolution on a portrait panel\n");
1988
1989                                         /* Scaling in both directions needs to the same */
1990                                         v_scale = h_scale;
1991
1992                                         /* Set a new vertical scale factor and enable testmode (bit28) */
1993                                         regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
1994
1995                                         diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
1996                                         regp->fp_vvalid_start = diff/2;
1997                                         regp->fp_vvalid_end = nv_output->fpHeight - (diff/2) - 1;
1998                                 }
1999                         }
2000                 }
2001
2002                 ErrorF("Post-panel scaling\n");
2003         }
2004
2005         if (pNv->Architecture >= NV_ARCH_10) {
2006                 /* Bios and blob don't seem to do anything (else) */
2007                 regp->nv10_cursync = (1<<25);
2008         }
2009
2010         /* These are the common blob values, minus a few fp specific bit's */
2011         /* Let's keep the TMDS pll and fpclock running in all situations */
2012         regp->debug_0 = 0x1101100;
2013
2014         if (is_fp && nv_output->scaling_mode != SCALE_NOSCALE) {
2015                 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_XSCALE_ENABLED;
2016                 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_YSCALE_ENABLED;
2017         } else if (is_fp) { /* no_scale mode, so we must center it */
2018                 uint32_t diff;
2019
2020                 diff = nv_output->fpWidth - mode->HDisplay;
2021                 regp->fp_hvalid_start = diff/2;
2022                 regp->fp_hvalid_end = (nv_output->fpWidth - diff/2 - 1);
2023
2024                 diff = nv_output->fpHeight - mode->VDisplay;
2025                 regp->fp_vvalid_start = diff/2;
2026                 regp->fp_vvalid_end = (nv_output->fpHeight - diff/2 - 1);
2027         }
2028
2029         /* Is this crtc bound or output bound? */
2030         /* Does the bios TMDS script try to change this sometimes? */
2031         if (is_fp) {
2032                 /* I am not completely certain, but seems to be set only for dfp's */
2033                 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED;
2034         }
2035
2036         if (output)
2037                 ErrorF("output %d debug_0 %08X\n", nv_output->preferred_output, regp->debug_0);
2038
2039         /* Flatpanel support needs at least a NV10 */
2040         if(pNv->twoHeads) {
2041                 /* The blob does this differently. */
2042                 /* TODO: Find out what precisely and why. */
2043                 if(pNv->FPDither || (is_lvds && pNv->VBIOS.fp.if_is_18bit)) {
2044                         if (pNv->NVArch == 0x11) {
2045                                 regp->dither = 0x00010000;
2046                         } else {
2047                                 regp->dither = 0x00000001;
2048                         }
2049                 }
2050         }
2051
2052         /* Kindly borrowed from haiku driver */
2053         /* bit4 and bit5 activate indirect mode trough color palette */
2054         switch (pLayout->depth) {
2055                 case 32:
2056                 case 16:
2057                         regp->general = 0x00101130;
2058                         break;
2059                 case 24:
2060                 case 15:
2061                         regp->general = 0x00100130;
2062                         break;
2063                 case 8:
2064                 default:
2065                         regp->general = 0x00101100;
2066                         break;
2067         }
2068
2069         if (pNv->alphaCursor) {
2070                 /* PIPE_LONG mode, something to do with the size of the cursor? */
2071                 regp->general |= (1<<29);
2072         }
2073
2074         /* Some values the blob sets */
2075         /* This may apply to the real ramdac that is being used (for crosswired situations) */
2076         /* Nevertheless, it's unlikely to cause many problems, since the values are equal for both */
2077         regp->unk_a20 = 0x0;
2078         regp->unk_a24 = 0xfffff;
2079         regp->unk_a34 = 0x1;
2080 }
2081
2082 /**
2083  * Sets up registers for the given mode/adjusted_mode pair.
2084  *
2085  * The clocks, CRTCs and outputs attached to this CRTC must be off.
2086  *
2087  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
2088  * be easily turned on/off after this.
2089  */
2090 static void
2091 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
2092                  DisplayModePtr adjusted_mode,
2093                  int x, int y)
2094 {
2095         ScrnInfoPtr pScrn = crtc->scrn;
2096         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2097         NVPtr pNv = NVPTR(pScrn);
2098
2099         ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->head);
2100
2101         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->head);
2102         xf86PrintModeline(pScrn->scrnIndex, mode);
2103         NVCrtcSetOwner(crtc);
2104
2105         nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
2106         nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
2107         nv_crtc_mode_set_ramdac_regs(crtc, mode, adjusted_mode);
2108
2109         NVVgaProtect(crtc, TRUE);
2110         nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
2111         nv_crtc_load_state_ext(crtc, &pNv->ModeReg, FALSE);
2112         NVCrtcLoadPalette(crtc);
2113         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
2114         if (pNv->Architecture == NV_ARCH_40) {
2115                 nv40_crtc_load_state_pll(crtc, &pNv->ModeReg);
2116         } else {
2117                 nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
2118         }
2119
2120         NVVgaProtect(crtc, FALSE);
2121
2122         NVCrtcSetBase(crtc, x, y);
2123
2124 #if X_BYTE_ORDER == X_BIG_ENDIAN
2125         /* turn on LFB swapping */
2126         {
2127                 unsigned char tmp;
2128
2129                 tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
2130                 tmp |= (1 << 7);
2131                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
2132         }
2133 #endif
2134 }
2135
2136 void nv_crtc_save(xf86CrtcPtr crtc)
2137 {
2138         ScrnInfoPtr pScrn = crtc->scrn;
2139         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2140         NVPtr pNv = NVPTR(pScrn);
2141
2142         ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->head);
2143
2144         /* We just came back from terminal, so unlock */
2145         NVCrtcLockUnlock(crtc, FALSE);
2146
2147         NVCrtcSetOwner(crtc);
2148         nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
2149         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
2150         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
2151         if (pNv->Architecture == NV_ARCH_40) {
2152                 nv40_crtc_save_state_pll(pNv, &pNv->SavedReg);
2153         } else {
2154                 nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
2155         }
2156 }
2157
2158 void nv_crtc_restore(xf86CrtcPtr crtc)
2159 {
2160         ScrnInfoPtr pScrn = crtc->scrn;
2161         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2162         NVPtr pNv = NVPTR(pScrn);
2163         RIVA_HW_STATE *state;
2164
2165         state = &pNv->SavedReg;
2166
2167         ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->head);
2168
2169         NVCrtcSetOwner(crtc);
2170
2171         /* Just to be safe */
2172         NVCrtcLockUnlock(crtc, FALSE);
2173
2174         NVVgaProtect(crtc, TRUE);
2175         nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
2176         nv_crtc_load_state_ext(crtc, &pNv->SavedReg, TRUE);
2177         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
2178         if (pNv->Architecture == NV_ARCH_40) {
2179                 nv40_crtc_load_state_pll(crtc, &pNv->SavedReg);
2180         } else {
2181                 nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
2182         }
2183         nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->vtOWNER);
2184         NVVgaProtect(crtc, FALSE);
2185 }
2186
2187 void
2188 NVResetCrtcConfig(xf86CrtcPtr crtc, Bool set)
2189 {
2190         ScrnInfoPtr pScrn = crtc->scrn;
2191         NVPtr pNv = NVPTR(pScrn);
2192         CARD32 val = 0;
2193
2194         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2195
2196         if (set) {
2197                 NVCrtcRegPtr regp;
2198
2199                 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2200                 val = regp->head;
2201         }
2202
2203         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL, val);
2204 }
2205
2206 void nv_crtc_prepare(xf86CrtcPtr crtc)
2207 {
2208         ScrnInfoPtr pScrn = crtc->scrn;
2209         NVPtr pNv = NVPTR(pScrn);
2210         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2211
2212         ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->head);
2213
2214         /* Just in case */
2215         NVCrtcLockUnlock(crtc, 0);
2216
2217         NVResetCrtcConfig(crtc, FALSE);
2218
2219         crtc->funcs->dpms(crtc, DPMSModeOff);
2220
2221         /* Sync the engine before adjust mode */
2222         if (pNv->EXADriverPtr) {
2223                 exaMarkSync(pScrn->pScreen);
2224                 exaWaitSync(pScrn->pScreen);
2225         }
2226
2227         NVCrtcBlankScreen(crtc, FALSE); /* Blank screen */
2228
2229         /* Some more preperation. */
2230         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG, 0x1); /* Go to non-vga mode/out of enhanced mode */
2231         uint32_t reg900 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900);
2232         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 & ~0x10000);
2233         /* Set FP_CONTROL to a neutral mode, (almost) off i believe. */
2234         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, 0x21100222);
2235
2236         usleep(5000); /* Give it some time to settle */
2237 }
2238
2239 void nv_crtc_commit(xf86CrtcPtr crtc)
2240 {
2241         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2242         ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->head);
2243
2244         crtc->funcs->dpms (crtc, DPMSModeOn);
2245
2246         if (crtc->scrn->pScreen != NULL)
2247                 xf86_reload_cursors (crtc->scrn->pScreen);
2248
2249         NVResetCrtcConfig(crtc, TRUE);
2250 }
2251
2252 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
2253 {
2254         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2255         ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->head);
2256
2257         return FALSE;
2258 }
2259
2260 static void nv_crtc_unlock(xf86CrtcPtr crtc)
2261 {
2262         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2263         ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->head);
2264 }
2265
2266 static void
2267 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
2268                                         int size)
2269 {
2270         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2271         ScrnInfoPtr pScrn = crtc->scrn;
2272         NVPtr pNv = NVPTR(pScrn);
2273         int i, j;
2274
2275         NVCrtcRegPtr regp;
2276         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2277
2278         switch (pNv->CurrentLayout.depth) {
2279         case 15:
2280                 /* R5G5B5 */
2281                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
2282                 for (i = 0; i < 32; i++) {
2283                         for (j = 0; j < 8; j++) {
2284                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2285                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
2286                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2287                         }
2288                 }
2289                 break;
2290         case 16:
2291                 /* R5G6B5 */
2292                 /* First deal with the 5 bit colors */
2293                 for (i = 0; i < 32; i++) {
2294                         for (j = 0; j < 8; j++) {
2295                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2296                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2297                         }
2298                 }
2299                 /* Now deal with the 6 bit color */
2300                 for (i = 0; i < 64; i++) {
2301                         for (j = 0; j < 4; j++) {
2302                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
2303                         }
2304                 }
2305                 break;
2306         default:
2307                 /* R8G8B8 */
2308                 for (i = 0; i < 256; i++) {
2309                         regp->DAC[i * 3] = red[i] >> 8;
2310                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
2311                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
2312                 }
2313                 break;
2314         }
2315
2316         NVCrtcLoadPalette(crtc);
2317 }
2318
2319 /**
2320  * Allocates memory for a locked-in-framebuffer shadow of the given
2321  * width and height for this CRTC's rotated shadow framebuffer.
2322  */
2323
2324 static void *
2325 nv_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
2326 {
2327         ErrorF("nv_crtc_shadow_allocate is called\n");
2328         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2329         ScrnInfoPtr pScrn = crtc->scrn;
2330 #if !NOUVEAU_EXA_PIXMAPS
2331         ScreenPtr pScreen = pScrn->pScreen;
2332 #endif /* !NOUVEAU_EXA_PIXMAPS */
2333         NVPtr pNv = NVPTR(pScrn);
2334         void *offset;
2335
2336         unsigned long rotate_pitch;
2337         int size, align = 64;
2338
2339         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2340         size = rotate_pitch * height;
2341
2342         assert(nv_crtc->shadow == NULL);
2343 #if NOUVEAU_EXA_PIXMAPS
2344         if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN,
2345                         align, size, &nv_crtc->shadow)) {
2346                 ErrorF("Failed to allocate memory for shadow buffer!\n");
2347                 return NULL;
2348         }
2349
2350         if (nv_crtc->shadow && nouveau_bo_map(nv_crtc->shadow, NOUVEAU_BO_RDWR)) {
2351                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2352                                 "Failed to map shadow buffer.\n");
2353                 return NULL;
2354         }
2355
2356         offset = nv_crtc->shadow->map;
2357 #else
2358         nv_crtc->shadow = exaOffscreenAlloc(pScreen, size, align, TRUE, NULL, NULL);
2359         if (nv_crtc->shadow == NULL) {
2360                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2361                         "Couldn't allocate shadow memory for rotated CRTC\n");
2362                 return NULL;
2363         }
2364         offset = pNv->FB->map + nv_crtc->shadow->offset;
2365 #endif /* NOUVEAU_EXA_PIXMAPS */
2366
2367         return offset;
2368 }
2369
2370 /**
2371  * Creates a pixmap for this CRTC's rotated shadow framebuffer.
2372  */
2373 static PixmapPtr
2374 nv_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
2375 {
2376         ErrorF("nv_crtc_shadow_create is called\n");
2377         ScrnInfoPtr pScrn = crtc->scrn;
2378 #if NOUVEAU_EXA_PIXMAPS
2379         ScreenPtr pScreen = pScrn->pScreen;
2380         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2381 #endif /* NOUVEAU_EXA_PIXMAPS */
2382         unsigned long rotate_pitch;
2383         PixmapPtr rotate_pixmap;
2384 #if NOUVEAU_EXA_PIXMAPS
2385         struct nouveau_pixmap *nvpix;
2386 #endif /* NOUVEAU_EXA_PIXMAPS */
2387
2388         if (!data)
2389                 data = crtc->funcs->shadow_allocate (crtc, width, height);
2390
2391         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2392
2393 #if NOUVEAU_EXA_PIXMAPS
2394         /* Create a dummy pixmap, to get a private that will be accepted by the system.*/
2395         rotate_pixmap = pScreen->CreatePixmap(pScreen,
2396                                                                 0, /* width */
2397                                                                 0, /* height */
2398         #ifdef CREATE_PIXMAP_USAGE_SCRATCH /* there seems to have been no api bump */
2399                                                                 pScrn->depth,
2400                                                                 0);
2401         #else
2402                                                                 pScrn->depth);
2403         #endif /* CREATE_PIXMAP_USAGE_SCRATCH */
2404 #else
2405         rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen,
2406                                                                 width, height,
2407                                                                 pScrn->depth,
2408                                                                 pScrn->bitsPerPixel,
2409                                                                 rotate_pitch,
2410                                                                 data);
2411 #endif /* NOUVEAU_EXA_PIXMAPS */
2412
2413         if (rotate_pixmap == NULL) {
2414                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2415                         "Couldn't allocate shadow pixmap for rotated CRTC\n");
2416         }
2417
2418 #if NOUVEAU_EXA_PIXMAPS
2419         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2420         if (!nvpix) {
2421                 ErrorF("No shadow private, stage 1\n");
2422         } else {
2423                 nvpix->bo = nv_crtc->shadow;
2424                 nvpix->mapped = TRUE;
2425         }
2426
2427         /* Modify the pixmap to actually be the one we need. */
2428         pScreen->ModifyPixmapHeader(rotate_pixmap,
2429                                         width,
2430                                         height,
2431                                         pScrn->depth,
2432                                         pScrn->bitsPerPixel,
2433                                         rotate_pitch,
2434                                         data);
2435
2436         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2437         if (!nvpix || !nvpix->bo)
2438                 ErrorF("No shadow private, stage 2\n");
2439 #endif /* NOUVEAU_EXA_PIXMAPS */
2440
2441         return rotate_pixmap;
2442 }
2443
2444 static void
2445 nv_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
2446 {
2447         ErrorF("nv_crtc_shadow_destroy is called\n");
2448         ScrnInfoPtr pScrn = crtc->scrn;
2449         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2450         ScreenPtr pScreen = pScrn->pScreen;
2451
2452         if (rotate_pixmap) { /* This should also unmap the buffer object if relevant. */
2453                 pScreen->DestroyPixmap(rotate_pixmap);
2454         }
2455
2456 #if !NOUVEAU_EXA_PIXMAPS
2457         if (data && nv_crtc->shadow) {
2458                 exaOffscreenFree(pScreen, nv_crtc->shadow);
2459         }
2460 #endif /* !NOUVEAU_EXA_PIXMAPS */
2461
2462         nv_crtc->shadow = NULL;
2463 }
2464
2465 /* NV04-NV10 doesn't support alpha cursors */
2466 static const xf86CrtcFuncsRec nv_crtc_funcs = {
2467         .dpms = nv_crtc_dpms,
2468         .save = nv_crtc_save, /* XXX */
2469         .restore = nv_crtc_restore, /* XXX */
2470         .mode_fixup = nv_crtc_mode_fixup,
2471         .mode_set = nv_crtc_mode_set,
2472         .prepare = nv_crtc_prepare,
2473         .commit = nv_crtc_commit,
2474         .destroy = NULL, /* XXX */
2475         .lock = nv_crtc_lock,
2476         .unlock = nv_crtc_unlock,
2477         .set_cursor_colors = nv_crtc_set_cursor_colors,
2478         .set_cursor_position = nv_crtc_set_cursor_position,
2479         .show_cursor = nv_crtc_show_cursor,
2480         .hide_cursor = nv_crtc_hide_cursor,
2481         .load_cursor_image = nv_crtc_load_cursor_image,
2482         .gamma_set = nv_crtc_gamma_set,
2483         .shadow_create = nv_crtc_shadow_create,
2484         .shadow_allocate = nv_crtc_shadow_allocate,
2485         .shadow_destroy = nv_crtc_shadow_destroy,
2486 };
2487
2488 /* NV11 and up has support for alpha cursors. */
2489 /* Due to different maximum sizes we cannot allow it to use normal cursors */
2490 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
2491         .dpms = nv_crtc_dpms,
2492         .save = nv_crtc_save, /* XXX */
2493         .restore = nv_crtc_restore, /* XXX */
2494         .mode_fixup = nv_crtc_mode_fixup,
2495         .mode_set = nv_crtc_mode_set,
2496         .prepare = nv_crtc_prepare,
2497         .commit = nv_crtc_commit,
2498         .destroy = NULL, /* XXX */
2499         .lock = nv_crtc_lock,
2500         .unlock = nv_crtc_unlock,
2501         .set_cursor_colors = NULL, /* Alpha cursors do not need this */
2502         .set_cursor_position = nv_crtc_set_cursor_position,
2503         .show_cursor = nv_crtc_show_cursor,
2504         .hide_cursor = nv_crtc_hide_cursor,
2505         .load_cursor_argb = nv_crtc_load_cursor_argb,
2506         .gamma_set = nv_crtc_gamma_set,
2507         .shadow_create = nv_crtc_shadow_create,
2508         .shadow_allocate = nv_crtc_shadow_allocate,
2509         .shadow_destroy = nv_crtc_shadow_destroy,
2510 };
2511
2512
2513 void
2514 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
2515 {
2516         NVPtr pNv = NVPTR(pScrn);
2517         xf86CrtcPtr crtc;
2518         NVCrtcPrivatePtr nv_crtc;
2519
2520         if (pNv->NVArch >= 0x11) {
2521                 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
2522         } else {
2523                 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
2524         }
2525         if (crtc == NULL)
2526                 return;
2527
2528         nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
2529         nv_crtc->head = crtc_num;
2530
2531         crtc->driver_private = nv_crtc;
2532
2533         NVCrtcLockUnlock(crtc, FALSE);
2534 }
2535
2536 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2537 {
2538         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2539         int i;
2540         NVCrtcRegPtr regp;
2541
2542         regp = &state->crtc_reg[nv_crtc->head];
2543
2544         NVWriteMiscOut(crtc, regp->MiscOutReg);
2545
2546         for (i = 1; i < 5; i++)
2547                 NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
2548
2549         /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
2550         NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
2551
2552         for (i = 0; i < 25; i++)
2553                 NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
2554
2555         for (i = 0; i < 9; i++)
2556                 NVWriteVgaGr(crtc, i, regp->Graphics[i]);
2557
2558         NVEnablePalette(crtc);
2559         for (i = 0; i < 21; i++)
2560                 NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
2561
2562         NVDisablePalette(crtc);
2563 }
2564
2565 static void nv_crtc_fix_nv40_hw_cursor(xf86CrtcPtr crtc)
2566 {
2567         /* TODO - implement this properly */
2568         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2569         ScrnInfoPtr pScrn = crtc->scrn;
2570         NVPtr pNv = NVPTR(pScrn);
2571
2572         if (pNv->Architecture == NV_ARCH_40) {  /* HW bug */
2573                 volatile CARD32 curpos = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS);
2574                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS, curpos);
2575         }
2576 }
2577 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override)
2578 {
2579         ScrnInfoPtr pScrn = crtc->scrn;
2580         NVPtr pNv = NVPTR(pScrn);
2581         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2582         NVCrtcRegPtr regp;
2583         int i;
2584
2585         regp = &state->crtc_reg[nv_crtc->head];
2586
2587         /* If we ever get down to pre-nv10 cards, then we must reinstate some limits. */
2588         nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
2589         nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
2590         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
2591         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
2592         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2593         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2594         nvWriteMC(pNv, 0x1588, 0);
2595
2596         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
2597         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
2598         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO, regp->gpio);
2599         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0830, regp->unk830);
2600         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0834, regp->unk834);
2601         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0850, regp->unk850);
2602         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_081C, regp->unk81c);
2603
2604         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG, regp->config);
2605         uint32_t reg900 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900);
2606         if (regp->config == 0x2) { /* enhanced "horizontal only" non-vga mode */
2607                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 | 0x10000);
2608         } else {
2609                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 & ~0x10000);
2610         }
2611
2612         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
2613         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
2614
2615         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
2616         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
2617         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3C, regp->CRTC[NV_VGA_CRTCX_3C]);
2618         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
2619         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_4B, regp->CRTC[NV_VGA_CRTCX_4B]);
2620         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
2621         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_56, regp->CRTC[NV_VGA_CRTCX_56]);
2622         if (override) {
2623                 for (i = 0; i < 0x10; i++)
2624                         NVWriteVGACR5758(pNv, nv_crtc->head, i, regp->CR58[i]);
2625         }
2626         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
2627         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
2628
2629         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
2630         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
2631         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
2632         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
2633         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
2634         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
2635         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
2636         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
2637         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
2638         if (pNv->Architecture >= NV_ARCH_30) {
2639                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
2640         }
2641
2642         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_43, regp->CRTC[NV_VGA_CRTCX_43]);
2643         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_85, regp->CRTC[NV_VGA_CRTCX_85]);
2644         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_86, regp->CRTC[NV_VGA_CRTCX_86]);
2645
2646         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
2647         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
2648         nv_crtc_fix_nv40_hw_cursor(crtc);
2649         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
2650         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
2651
2652         /* Setting 1 on this value gives you interrupts for every vblank period. */
2653         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_EN_0, 0);
2654         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
2655
2656         pNv->CurrentState = state;
2657 }
2658
2659 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2660 {
2661         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2662         int i;
2663         NVCrtcRegPtr regp;
2664
2665         regp = &state->crtc_reg[nv_crtc->head];
2666
2667         regp->MiscOutReg = NVReadMiscOut(crtc);
2668
2669         for (i = 0; i < 25; i++)
2670                 regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
2671
2672         NVEnablePalette(crtc);
2673         for (i = 0; i < 21; i++)
2674                 regp->Attribute[i] = NVReadVgaAttr(crtc, i);
2675         NVDisablePalette(crtc);
2676
2677         for (i = 0; i < 9; i++)
2678                 regp->Graphics[i] = NVReadVgaGr(crtc, i);
2679
2680         for (i = 1; i < 5; i++)
2681                 regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
2682
2683 }
2684
2685 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2686 {
2687         ScrnInfoPtr pScrn = crtc->scrn;
2688         NVPtr pNv = NVPTR(pScrn);
2689         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2690         NVCrtcRegPtr regp;
2691         int i;
2692
2693         regp = &state->crtc_reg[nv_crtc->head];
2694
2695         /* If we ever get down to pre-nv10 cards, then we must reinstate some limits. */
2696         regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
2697         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
2698         regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
2699         regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
2700         regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
2701         regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
2702         regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
2703
2704         regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
2705         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
2706         if (pNv->Architecture >= NV_ARCH_30) {
2707                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
2708         }
2709         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
2710         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
2711         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
2712         regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
2713
2714         regp->gpio = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO);
2715         regp->unk830 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0830);
2716         regp->unk834 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0834);
2717         regp->unk850 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0850);
2718         regp->unk81c = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_081C);
2719
2720         regp->config = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG);
2721
2722         regp->head = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL);
2723         regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
2724         regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
2725
2726         regp->cursorConfig = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG);
2727
2728         regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
2729         regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
2730         regp->CRTC[NV_VGA_CRTCX_3C] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3C);
2731         regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
2732         regp->CRTC[NV_VGA_CRTCX_4B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_4B);
2733         regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
2734         regp->CRTC[NV_VGA_CRTCX_56] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_56);
2735         for (i = 0; i < 0x10; i++)
2736                 regp->CR58[i] = NVReadVGACR5758(pNv, nv_crtc->head, i);
2737
2738         regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
2739         regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
2740         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
2741         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
2742
2743         regp->CRTC[NV_VGA_CRTCX_43] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_43);
2744         regp->CRTC[NV_VGA_CRTCX_85] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_85);
2745         regp->CRTC[NV_VGA_CRTCX_86] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_86);
2746 }
2747
2748 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2749 {
2750         ScrnInfoPtr pScrn = crtc->scrn;
2751         NVPtr pNv = NVPTR(pScrn);
2752         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2753         NVCrtcRegPtr regp;
2754         int i;
2755
2756         regp = &state->crtc_reg[nv_crtc->head];
2757
2758         regp->general = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL);
2759
2760         regp->fp_control        = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL);
2761         regp->debug_0   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0);
2762         regp->debug_1   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1);
2763         regp->debug_2   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2);
2764
2765         regp->unk_a20 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20);
2766         regp->unk_a24 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24);
2767         regp->unk_a34 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34);
2768
2769         if (pNv->NVArch == 0x11) {
2770                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11);
2771         } else if (pNv->twoHeads) {
2772                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER);
2773         }
2774         regp->nv10_cursync = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC);
2775
2776         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2777
2778         for (i = 0; i < 7; i++) {
2779                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2780                 regp->fp_horiz_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2781         }
2782
2783         for (i = 0; i < 7; i++) {
2784                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2785                 regp->fp_vert_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2786         }
2787
2788         regp->fp_hvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START);
2789         regp->fp_hvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END);
2790         regp->fp_vvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START);
2791         regp->fp_vvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END);
2792 }
2793
2794 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2795 {
2796         ScrnInfoPtr pScrn = crtc->scrn;
2797         NVPtr pNv = NVPTR(pScrn);
2798         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2799         NVCrtcRegPtr regp;
2800         int i;
2801
2802         regp = &state->crtc_reg[nv_crtc->head];
2803
2804         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL, regp->general);
2805
2806         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control);
2807         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0, regp->debug_0);
2808         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
2809         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
2810
2811         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20, regp->unk_a20);
2812         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24, regp->unk_a24);
2813         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34, regp->unk_a34);
2814
2815         if (pNv->NVArch == 0x11) {
2816                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11, regp->dither);
2817         } else if (pNv->twoHeads) {
2818                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER, regp->dither);
2819         }
2820         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
2821
2822         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2823
2824         for (i = 0; i < 7; i++) {
2825                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2826                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_horiz_regs[i]);
2827         }
2828
2829         for (i = 0; i < 7; i++) {
2830                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2831                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_vert_regs[i]);
2832         }
2833
2834         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START, regp->fp_hvalid_start);
2835         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END, regp->fp_hvalid_end);
2836         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START, regp->fp_vvalid_start);
2837         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END, regp->fp_vvalid_end);
2838 }
2839
2840 void
2841 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y)
2842 {
2843         ScrnInfoPtr pScrn = crtc->scrn;
2844         NVPtr pNv = NVPTR(pScrn);
2845         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2846         NVFBLayout *pLayout = &pNv->CurrentLayout;
2847         CARD32 start = 0;
2848
2849         ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
2850
2851         start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
2852         if (crtc->rotatedData != NULL) { /* we do not exist on the real framebuffer */
2853 #if NOUVEAU_EXA_PIXMAPS
2854                 start = nv_crtc->shadow->offset;
2855 #else
2856                 start = pNv->FB->offset + nv_crtc->shadow->offset; /* We do exist relative to the framebuffer */
2857 #endif
2858         } else {
2859                 start += pNv->FB->offset;
2860         }
2861
2862         /* 30 bits addresses in 32 bits according to haiku */
2863         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_START, start & 0xfffffffc);
2864
2865         /* set NV4/NV10 byte adress: (bit0 - 1) */
2866         NVWriteVgaAttr(crtc, 0x13, (start & 0x3) << 1);
2867
2868         crtc->x = x;
2869         crtc->y = y;
2870 }
2871
2872 static void NVCrtcWriteDacMask(xf86CrtcPtr crtc, CARD8 value)
2873 {
2874   ScrnInfoPtr pScrn = crtc->scrn;
2875   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2876   NVPtr pNv = NVPTR(pScrn);
2877   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2878
2879   NV_WR08(pDACReg, VGA_DAC_MASK, value);
2880 }
2881
2882 static CARD8 NVCrtcReadDacMask(xf86CrtcPtr crtc)
2883 {
2884   ScrnInfoPtr pScrn = crtc->scrn;
2885   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2886   NVPtr pNv = NVPTR(pScrn);
2887   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2888
2889   return NV_RD08(pDACReg, VGA_DAC_MASK);
2890 }
2891
2892 static void NVCrtcWriteDacReadAddr(xf86CrtcPtr crtc, CARD8 value)
2893 {
2894   ScrnInfoPtr pScrn = crtc->scrn;
2895   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2896   NVPtr pNv = NVPTR(pScrn);
2897   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2898
2899   NV_WR08(pDACReg, VGA_DAC_READ_ADDR, value);
2900 }
2901
2902 static void NVCrtcWriteDacWriteAddr(xf86CrtcPtr crtc, CARD8 value)
2903 {
2904   ScrnInfoPtr pScrn = crtc->scrn;
2905   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2906   NVPtr pNv = NVPTR(pScrn);
2907   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2908
2909   NV_WR08(pDACReg, VGA_DAC_WRITE_ADDR, value);
2910 }
2911
2912 static void NVCrtcWriteDacData(xf86CrtcPtr crtc, CARD8 value)
2913 {
2914   ScrnInfoPtr pScrn = crtc->scrn;
2915   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2916   NVPtr pNv = NVPTR(pScrn);
2917   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2918
2919   NV_WR08(pDACReg, VGA_DAC_DATA, value);
2920 }
2921
2922 static CARD8 NVCrtcReadDacData(xf86CrtcPtr crtc, CARD8 value)
2923 {
2924   ScrnInfoPtr pScrn = crtc->scrn;
2925   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2926   NVPtr pNv = NVPTR(pScrn);
2927   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2928
2929   return NV_RD08(pDACReg, VGA_DAC_DATA);
2930 }
2931
2932 void NVCrtcLoadPalette(xf86CrtcPtr crtc)
2933 {
2934         int i;
2935         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2936         NVCrtcRegPtr regp;
2937         ScrnInfoPtr pScrn = crtc->scrn;
2938         NVPtr pNv = NVPTR(pScrn);
2939
2940         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2941
2942         NVCrtcSetOwner(crtc);
2943         NVCrtcWriteDacMask(crtc, 0xff);
2944         NVCrtcWriteDacWriteAddr(crtc, 0x00);
2945
2946         for (i = 0; i<768; i++) {
2947                 NVCrtcWriteDacData(crtc, regp->DAC[i]);
2948         }
2949         NVDisablePalette(crtc);
2950 }
2951
2952 /* on = unblank */
2953 void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
2954 {
2955         unsigned char scrn;
2956
2957         NVCrtcSetOwner(crtc);
2958
2959         scrn = NVReadVgaSeq(crtc, 0x01);
2960         if (on) {
2961                 scrn &= ~0x20;
2962         } else {
2963                 scrn |= 0x20;
2964         }
2965
2966         NVVgaSeqReset(crtc, TRUE);
2967         NVWriteVgaSeq(crtc, 0x01, scrn);
2968         NVVgaSeqReset(crtc, FALSE);
2969 }
2970
2971 /*************************************************************************** \
2972 |*                                                                           *|
2973 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
2974 |*                                                                           *|
2975 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
2976 |*     international laws.  Users and possessors of this source code are     *|
2977 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
2978 |*     use this code in individual and commercial software.                  *|
2979 |*                                                                           *|
2980 |*     Any use of this source code must include,  in the user documenta-     *|
2981 |*     tion and  internal comments to the code,  notices to the end user     *|
2982 |*     as follows:                                                           *|
2983 |*                                                                           *|
2984 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
2985 |*                                                                           *|
2986 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
2987 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
2988 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
2989 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
2990 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
2991 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
2992 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
2993 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
2994 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
2995 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
2996 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
2997 |*                                                                           *|
2998 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
2999 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
3000 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
3001 |*     computer  software  documentation,"  as such  terms  are  used in     *|
3002 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
3003 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
3004 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
3005 |*     all U.S. Government End Users  acquire the source code  with only     *|
3006 |*     those rights set forth herein.                                        *|
3007 |*                                                                           *|
3008  \***************************************************************************/