2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
19 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
20 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include "nv_include.h"
28 /* FIXME: put these somewhere */
29 #define CRTC_INDEX_COLOR (VGA_IOBASE_COLOR + VGA_CRTC_INDEX_OFFSET)
30 #define NV_VGA_CRTCX_OWNER_HEADA 0x0
31 #define NV_VGA_CRTCX_OWNER_HEADB 0x3
32 #define NV_PBUS_PCI_NV_19 0x0000184C
33 #define NV_PBUS_PCI_NV_20 0x00001850
34 #define NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED 0x00000000
35 #define NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED 0x00000001
36 #define NV_PEXTDEV_BOOT_0 0x00101000
37 /* undef, as we want the +0x00100000 version */
39 #define NV_PFB_CFG0 0x00100200
40 #define NV_PFB_REFCTRL 0x00100210
41 #define NV_PFB_REFCTRL_VALID_1 0x80000000
42 #define NV_PRAMIN_ROM_OFFSET 0x00700000
50 static int crtchead = 0;
52 /* this will need remembering across a suspend */
53 static uint32_t saved_nv_pfb_cfg0;
60 static uint16_t le16_to_cpu(const uint16_t x)
62 #if X_BYTE_ORDER == X_BIG_ENDIAN
69 static uint32_t le32_to_cpu(const uint32_t x)
71 #if X_BYTE_ORDER == X_BIG_ENDIAN
78 static Bool nv_cksum(const uint8_t *data, unsigned int length)
80 /* there's a few checksums in the BIOS, so here's a generic checking function */
84 for (i = 0; i < length; i++)
93 static int NVValidVBIOS(ScrnInfoPtr pScrn, const uint8_t *data)
95 /* check for BIOS signature */
96 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
97 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
98 "... BIOS signature not found\n");
102 if (nv_cksum(data, data[2] * 512)) {
103 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
104 "... BIOS checksum invalid\n");
105 /* probably ought to set a do_not_execute flag for table parsing here,
106 * assuming most BIOSen are valid */
109 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "... appears to be valid\n");
114 static void NVShadowVBIOS_PROM(ScrnInfoPtr pScrn, uint8_t *data)
116 NVPtr pNv = NVPTR(pScrn);
119 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
120 "Attempting to locate BIOS image in PROM\n");
122 /* enable ROM access */
123 nvWriteMC(pNv, NV_PBUS_PCI_NV_20, NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED);
124 for (i = 0; i < NV_PROM_SIZE; i++) {
125 /* according to nvclock, we need that to work around a 6600GT/6800LE bug */
126 data[i] = pNv->PROM[i];
127 data[i] = pNv->PROM[i];
128 data[i] = pNv->PROM[i];
129 data[i] = pNv->PROM[i];
130 data[i] = pNv->PROM[i];
132 /* disable ROM access */
133 nvWriteMC(pNv, NV_PBUS_PCI_NV_20, NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
136 static void NVShadowVBIOS_PRAMIN(ScrnInfoPtr pScrn, uint32_t *data)
138 NVPtr pNv = NVPTR(pScrn);
139 const uint32_t *pramin = (uint32_t *)&pNv->REGS[NV_PRAMIN_ROM_OFFSET/4];
140 uint32_t old_bar0_pramin = 0;
142 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
143 "Attempting to locate BIOS image in PRAMIN\n");
145 if (pNv->Architecture >= NV_ARCH_50) {
148 vbios_vram = (pNv->REGS[0x619f04/4] & ~0xff) << 8;
150 vbios_vram = pNv->REGS[0x1700/4] << 16;
151 vbios_vram += 0xf0000;
154 old_bar0_pramin = pNv->REGS[0x1700/4];
155 pNv->REGS[0x1700/4] = vbios_vram >> 16;
158 memcpy(data, pramin, NV_PROM_SIZE);
160 if (pNv->Architecture >= NV_ARCH_50) {
161 pNv->REGS[0x1700/4] = old_bar0_pramin;
165 static void NVVBIOS_PCIROM(ScrnInfoPtr pScrn, uint8_t *data)
167 NVPtr pNv = NVPTR(pScrn);
169 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
170 "Attempting to use PCI ROM BIOS image\n");
172 #if XSERVER_LIBPCIACCESS
173 pci_device_read_rom(pNv->PciInfo, data);
175 xf86ReadPciBIOS(0, pNv->PciTag, 0, data, NV_PROM_SIZE);
179 static Bool NVShadowVBIOS(ScrnInfoPtr pScrn, uint8_t *data)
181 NVShadowVBIOS_PROM(pScrn, data);
182 if (NVValidVBIOS(pScrn, data) == 2)
185 NVShadowVBIOS_PRAMIN(pScrn, (uint32_t *)data);
186 if (NVValidVBIOS(pScrn, data))
190 NVVBIOS_PCIROM(pScrn, data);
191 if (NVValidVBIOS(pScrn, data))
203 int length_multiplier;
204 Bool (*handler)(ScrnInfoPtr pScrn, bios_t *, uint16_t, init_exec_t *);
213 static void parse_init_table(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset, init_exec_t *iexec);
215 #define MACRO_INDEX_SIZE 2
217 #define CONDITION_SIZE 12
218 #define IO_FLAG_CONDITION_SIZE 9
226 static int nv_valid_reg(NVPtr pNv, uint32_t reg)
228 /* C51 has misaligned regs on purpose. Marvellous */
229 if ((reg & 0x3 && pNv->VBIOS.chip_version != 0x51) ||
230 (reg & 0x2 && pNv->VBIOS.chip_version == 0x51)) {
231 ErrorF("========== misaligned reg 0x%08X ==========\n", reg);
235 #define WITHIN(x,y,z) ((x>=y)&&(x<y+z))
236 if (WITHIN(reg,NV_PRAMIN_OFFSET,NV_PRAMIN_SIZE))
238 if (WITHIN(reg,NV_PCRTC0_OFFSET,NV_PCRTC0_SIZE))
240 if (WITHIN(reg,NV_PRAMDAC0_OFFSET,NV_PRAMDAC0_SIZE))
242 if (WITHIN(reg,NV_PFB_OFFSET,NV_PFB_SIZE))
244 if (WITHIN(reg,NV_PFIFO_OFFSET,NV_PFIFO_SIZE))
246 if (WITHIN(reg,NV_PGRAPH_OFFSET,NV_PGRAPH_SIZE))
248 if (WITHIN(reg,NV_PEXTDEV_OFFSET,NV_PEXTDEV_SIZE))
250 if (WITHIN(reg,NV_PTIMER_OFFSET,NV_PTIMER_SIZE))
252 if (WITHIN(reg,NV_PVIDEO_OFFSET,NV_PVIDEO_SIZE))
254 if (WITHIN(reg,NV_PMC_OFFSET,NV_PMC_SIZE))
256 if (WITHIN(reg,NV_FIFO_OFFSET,NV_FIFO_SIZE))
258 if (WITHIN(reg,NV_PCIO0_OFFSET,NV_PCIO0_SIZE))
260 if (WITHIN(reg,NV_PDIO0_OFFSET,NV_PDIO0_SIZE))
262 if (WITHIN(reg,NV_PVIO_OFFSET,NV_PVIO_SIZE))
264 if (WITHIN(reg,NV_PROM_OFFSET,NV_PROM_SIZE))
266 if (WITHIN(reg,NV_PRAMIN_ROM_OFFSET,NV_PROM_SIZE))
269 if (WITHIN(reg,0x88000,0x1000))
273 ErrorF("========== unknown reg 0x%08X ==========\n", reg);
278 static uint32_t nv32_rd(ScrnInfoPtr pScrn, uint32_t reg)
280 NVPtr pNv = NVPTR(pScrn);
283 if (!nv_valid_reg(pNv, reg))
286 /* C51 sometimes uses regs with bit0 set in the address. For these
287 * cases there should exist a translation in a BIOS table to an IO
288 * port address which the BIOS uses for accessing the reg
290 * These only seem to appear for the power control regs to a flat panel
291 * and in C51 mmio traces the normal regs for 0x1308 and 0x1310 are
292 * used - hence the mask below. An S3 suspend-resume mmio trace from a
293 * C51 will be required to see if this is true for the power microcode
294 * in 0x14.., or whether the direct IO port access method is needed
299 data = pNv->REGS[reg/4];
302 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
303 " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
308 static int nv32_wr(ScrnInfoPtr pScrn, uint32_t reg, uint32_t data)
310 NVPtr pNv = NVPTR(pScrn);
312 if (!nv_valid_reg(pNv, reg))
315 /* see note in nv32_rd */
322 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
323 " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
325 if (pNv->VBIOS.execute) {
327 pNv->REGS[reg/4] = data;
333 static uint8_t nv_idx_port_rd(ScrnInfoPtr pScrn, uint16_t port, uint8_t index)
335 NVPtr pNv = NVPTR(pScrn);
336 volatile uint8_t *ptr = crtchead ? pNv->PCIO1 : pNv->PCIO0;
339 VGA_WR08(ptr, port, index);
340 data = VGA_RD08(ptr, port + 1);
343 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
344 " Indexed read: Port: 0x%04X, Index: 0x%02X, Head: 0x%02X, Data: 0x%02X\n",
345 port, index, crtchead, data);
350 static void nv_idx_port_wr(ScrnInfoPtr pScrn, uint16_t port, uint8_t index, uint8_t data)
352 NVPtr pNv = NVPTR(pScrn);
353 volatile uint8_t *ptr;
355 /* The current head is maintained in a file scope variable crtchead.
356 * We trap changes to CRTCX_OWNER and update the head variable
357 * and hence the register set written.
358 * As CRTCX_OWNER only exists on CRTC0, we update crtchead to head0
359 * in advance of the write, and to head1 after the write
361 if (port == CRTC_INDEX_COLOR && index == NV_VGA_CRTCX_OWNER && data != NV_VGA_CRTCX_OWNER_HEADB)
363 ptr = crtchead ? pNv->PCIO1 : pNv->PCIO0;
366 nv_idx_port_rd(pScrn, port, index);
368 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
369 " Indexed write: Port: 0x%04X, Index: 0x%02X, Head: 0x%02X, Data: 0x%02X\n",
370 port, index, crtchead, data);
372 if (pNv->VBIOS.execute) {
374 VGA_WR08(ptr, port, index);
375 VGA_WR08(ptr, port + 1, data);
378 if (port == CRTC_INDEX_COLOR && index == NV_VGA_CRTCX_OWNER && data == NV_VGA_CRTCX_OWNER_HEADB)
382 #define ACCESS_UNLOCK 0
383 #define ACCESS_LOCK 1
384 static void crtc_access(ScrnInfoPtr pScrn, Bool lock)
386 NVPtr pNv = NVPTR(pScrn);
387 int savedhead = crtchead;
390 /* necessary external dependancy (twoHeads) */
392 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_OWNER, NV_VGA_CRTCX_OWNER_HEADA);
393 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_LOCK, lock ? 0x99 : 0x57);
394 cr11 = nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_VSYNCE);
395 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_VSYNCE, lock ? cr11 | 0x80 : cr11 & ~0x80);
398 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_OWNER, NV_VGA_CRTCX_OWNER_HEADB);
399 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_LOCK, lock ? 0x99 : 0x57);
400 cr11 = nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_VSYNCE);
401 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_VSYNCE, lock ? cr11 | 0x80 : cr11 & ~0x80);
404 crtchead = savedhead;
407 static Bool io_flag_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, uint8_t cond)
409 /* The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
410 * for the CRTC index; 1 byte for the mask to apply to the value
411 * retrieved from the CRTC; 1 byte for the shift right to apply to the
412 * masked CRTC value; 2 bytes for the offset to the flag array, to
413 * which the shifted value is added; 1 byte for the mask applied to the
414 * value read from the flag array; and 1 byte for the value to compare
415 * against the masked byte from the flag table.
418 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
419 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[condptr])));
420 uint8_t crtcindex = bios->data[condptr + 2];
421 uint8_t mask = bios->data[condptr + 3];
422 uint8_t shift = bios->data[condptr + 4];
423 uint16_t flagarray = le16_to_cpu(*((uint16_t *)(&bios->data[condptr + 5])));
424 uint8_t flagarraymask = bios->data[condptr + 7];
425 uint8_t cmpval = bios->data[condptr + 8];
429 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
430 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, Cmpval: 0x%02X\n",
431 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
433 data = nv_idx_port_rd(pScrn, crtcport, crtcindex);
435 data = bios->data[flagarray + ((data & mask) >> shift)];
436 data &= flagarraymask;
439 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
440 "0x%04X: Checking if 0x%02X equals 0x%02X\n",
441 offset, data, cmpval);
449 uint32_t getMNP_single(ScrnInfoPtr pScrn, uint32_t clk, int *bestNM, int *bestlog2P)
451 /* Find M, N and P for a single stage PLL
453 * Note that some bioses (NV3x) have lookup tables of precomputed MNP
454 * values, but we're too lazy to use those atm
456 * "clk" parameter in kHz
457 * returns calculated clock
460 bios_t *bios = &NVPTR(pScrn)->VBIOS;
462 int maxlog2P, log2P, P;
464 uint32_t minvco = bios->fminvco;
465 uint32_t maxvco = bios->fmaxvco;
468 unsigned int bestdelta = UINT_MAX;
469 uint32_t bestclk = 0;
471 unsigned int crystal_strap_mask = 1 << 6;
472 /* open coded pNv->twoHeads test */
473 if (bios->chip_version > 0x10 && bios->chip_version != 0x15 &&
474 bios->chip_version != 0x1a && bios->chip_version != 0x20)
475 crystal_strap_mask |= 1 << 22;
476 switch (nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) & crystal_strap_mask) {
486 case (1 << 22 | 1 << 6):
492 /* this division verified for nv20, nv28 (Haiku), nv34 -- nv17 is guessed */
493 /* possibly correlated with introduction of 27MHz crystal */
494 if (bios->chip_version <= 0x16 || bios->chip_version == 0x20) {
510 if ((clk << maxlog2P) < minvco) {
511 minvco = clk << maxlog2P;
514 if (clk + clk/200 > maxvco) /* +0.5% */
515 maxvco = clk + clk/200;
517 /* NV34 goes maxlog2P->0, NV20 goes 0->maxlog2P */
518 for (log2P = 0; log2P <= maxlog2P; log2P++) {
526 /* nv_hw.c in nv driver uses 7 and 8 for minM */
527 for (M = 1; M <= maxM; M++) {
528 /* add crystal/2 to round better */
529 N = (clkP * M + crystal/2) / crystal;
530 if (N > 256) /* we lost */
533 /* more rounding additions */
534 calcclk = ((N * crystal + P/2) / P + M/2) / M;
535 delta = abs(calcclk - clk);
536 /* we do an exhaustive search rather than terminating
537 * on an optimality condition...
539 if (delta < bestdelta) {
542 *bestNM = N << 8 | M;
544 if (delta == 0) /* except this one */
555 Bool get_pll_limits(ScrnInfoPtr pScrn, uint32_t reg, struct pll_lims *pll_lim);
557 int getMNP_double(ScrnInfoPtr pScrn, uint32_t reg, int clk, int *bestNM1, int *bestNM2, int *bestlog2P)
559 /* Find M, N and P for a two stage PLL
561 * Note that some bioses (NV30+) have lookup tables of precomputed MNP
562 * values, but we're too lazy to use those atm
564 * "clk" parameter in kHz
565 * returns calculated clock
568 struct pll_lims pll_lim;
570 /* high regs (such as in the mac g5 table) are not -= 4 */
573 if (!get_pll_limits(pScrn, reg - 4, &pll_lim))
576 int minvco1 = pll_lim.vco1.minfreq, maxvco1 = pll_lim.vco1.maxfreq;
577 int minvco2 = pll_lim.vco2.minfreq, maxvco2 = pll_lim.vco2.maxfreq;
578 int minU1 = pll_lim.vco1.min_inputfreq, minU2 = pll_lim.vco2.min_inputfreq;
579 int maxU1 = pll_lim.vco1.max_inputfreq, maxU2 = pll_lim.vco2.max_inputfreq;
580 int minM1 = pll_lim.vco1.min_m, maxM1 = pll_lim.vco1.max_m;
581 int minN1 = pll_lim.vco1.min_n, maxN1 = pll_lim.vco1.max_n;
582 int minM2 = pll_lim.vco2.min_m, maxM2 = pll_lim.vco2.max_m;
583 int minN2 = pll_lim.vco2.min_n, maxN2 = pll_lim.vco2.max_n;
584 Bool fixedgain2 = (minM2 == maxM2 && minN2 == maxN2);
586 int M1, N1, M2, N2, log2P;
587 int clkP, calcclk1, calcclk2, calcclkout;
588 int delta, bestdelta = INT_MAX;
592 crystal = pll_lim.refclk;
594 switch (nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) & (1 << 22 | 1 << 6)) {
604 case (1 << 22 | 1 << 6):
609 int vco2 = (maxvco2 - maxvco2/200) / 2;
610 for (log2P = 0; log2P < 6 && clk <= (vco2 >> log2P); log2P++) /* log2P is maximum of 6 */
614 if (maxvco2 < clk + clk/200) /* +0.5% */
615 maxvco2 = clk + clk/200;
617 for (M1 = minM1; M1 <= maxM1; M1++) {
618 if (crystal/M1 < minU1)
620 if (crystal/M1 > maxU1)
623 for (N1 = minN1; N1 <= maxN1; N1++) {
624 calcclk1 = crystal * N1 / M1;
625 if (calcclk1 < minvco1)
627 if (calcclk1 > maxvco1)
630 for (M2 = minM2; M2 <= maxM2; M2++) {
631 if (calcclk1/M2 < minU2)
633 if (calcclk1/M2 > maxU2)
636 /* add calcclk1/2 to round better */
637 N2 = (clkP * M2 + calcclk1/2) / calcclk1;
644 if (N2/M2 < 4 || N2/M2 > 10)
647 calcclk2 = calcclk1 * N2 / M2;
648 if (calcclk2 < minvco2)
650 if (calcclk2 > maxvco2)
655 calcclkout = calcclk2 >> log2P;
656 delta = abs(calcclkout - clk);
657 /* we do an exhaustive search rather than terminating
658 * on an optimality condition...
660 if (delta < bestdelta) {
662 bestclk = calcclkout;
663 *bestNM1 = N1 << 8 | M1;
664 *bestNM2 = N2 << 8 | M2;
666 if (delta == 0) /* except this one */
676 static void setPLL_single(ScrnInfoPtr pScrn, uint32_t reg, int NM, int log2P)
680 pll = nv32_rd(pScrn, reg);
681 if (pll == (log2P << 16 | NM))
682 return; /* already set */
685 //this stuff is present on my nv34 and something similar on the nv31
686 //it is not on nv20, and I don't know how useful or necessary it is
688 uint32_t saved_1584, shift_1584;
689 Bool frob1584 = FALSE;
710 saved_1584 = nv32_rd(pScrn, 0x00001584);
711 nv32_wr(pScrn, 0x00001584, (saved_1584 & ~(0xf << shift_1584)) | 1 << shift_1584);
716 pll = (pll & 0xffff0000) | NM;
717 nv32_wr(pScrn, reg, pll);
723 /* then write P as well */
724 nv32_wr(pScrn, reg, (pll & 0xfff8ffff) | log2P << 16);
728 nv32_wr(pScrn, 0x00001584, saved_1584);
732 static void setPLL_double_highregs(ScrnInfoPtr pScrn, uint32_t reg1, int NM1, int NM2, int log2P)
734 bios_t *bios = &NVPTR(pScrn)->VBIOS;
735 uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70);
736 uint32_t oldpll1 = nv32_rd(pScrn, reg1), oldpll2 = nv32_rd(pScrn, reg2);
737 uint32_t pll1 = (oldpll1 & 0xfff80000) | log2P << 16 | NM1;
738 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | NM2;
739 uint32_t saved1584 = 0, savedc040 = 0, maskc040 = ~0;
742 if (oldpll1 == pll1 && oldpll2 == pll2)
743 return; /* already set */
745 if (reg1 == 0x680500) {
747 maskc040 = ~(3 << 20);
749 if (reg1 == 0x680504) {
751 maskc040 = ~(3 << 22);
753 if (shift1584 >= 0) {
754 saved1584 = nv32_rd(pScrn, 0x1584);
755 nv32_wr(pScrn, 0x1584, (saved1584 & ~(0xf << shift1584)) | 1 << shift1584);
758 if (bios->chip_version >= 0x40) {
759 savedc040 = nv32_rd(pScrn, 0xc040);
760 nv32_wr(pScrn, 0xc040, savedc040 & maskc040);
762 if (reg1 == 0x680508)
763 nv32_wr(pScrn, 0x680580, nv32_rd(pScrn, 0x680580) & ~(1 << 28));
764 if (reg1 == 0x680520)
765 nv32_wr(pScrn, 0x680580, nv32_rd(pScrn, 0x680580) & ~(1 << 8));
768 nv32_wr(pScrn, reg2, pll2);
769 nv32_wr(pScrn, reg1, pll1);
771 if (shift1584 >= 0) {
772 nv32_wr(pScrn, 0x1584, saved1584);
773 if (bios->chip_version >= 0x40)
774 nv32_wr(pScrn, 0xc040, savedc040);
778 static void setPLL_double_lowregs(ScrnInfoPtr pScrn, uint32_t NMNMreg, int NM1, int NM2, int log2P)
780 /* When setting PLLs, there is a merry game of disabling and enabling
781 * various bits of hardware during the process. This function is a
782 * synthesis of six nv40 traces, nearly each card doing a subtly
783 * different thing. With luck all the necessary bits for each card are
784 * combined herein. Without luck it deviates from each card's formula
785 * so as to not work on any :)
788 uint32_t Preg = NMNMreg - 4;
789 uint32_t oldPval = nv32_rd(pScrn, Preg);
790 uint32_t NMNM = NM2 << 16 | NM1;
791 uint32_t Pval = (oldPval & ((Preg == 0x4020) ? ~(0x11 << 16) : ~(1 << 16))) | 0xc << 28 | log2P << 16;
792 uint32_t saved4600 = 0;
793 /* some cards have different maskc040s */
794 uint32_t maskc040 = ~(3 << 14), savedc040;
796 if (nv32_rd(pScrn, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval)
802 maskc040 = ~(3 << 26);
804 if (Preg == 0x4020) {
805 struct pll_lims pll_lim;
808 if (!get_pll_limits(pScrn, Preg, &pll_lim))
811 Pval2 = log2P + pll_lim.p_bias;
812 if (Pval2 > pll_lim.max_p)
813 Pval2 = pll_lim.max_p;
814 Pval |= 1 << 28 | Pval2 << 20;
816 saved4600 = nv32_rd(pScrn, 0x4600);
817 nv32_wr(pScrn, 0x4600, saved4600 | 1 << 31);
820 nv32_wr(pScrn, Preg, oldPval | 1 << 28);
821 nv32_wr(pScrn, Preg, Pval & ~(1 << 30));
822 if (Preg == 0x4020) {
823 Pval |= 1 << 23 | 1 << 12;
824 nv32_wr(pScrn, 0x4020, Pval & ~(3 << 30));
825 nv32_wr(pScrn, 0x4038, Pval & ~(3 << 30));
828 savedc040 = nv32_rd(pScrn, 0xc040);
829 nv32_wr(pScrn, 0xc040, savedc040 & maskc040);
831 nv32_wr(pScrn, NMNMreg, NMNM);
832 if (NMNMreg == 0x4024)
833 nv32_wr(pScrn, 0x403c, NMNM);
835 nv32_wr(pScrn, Preg, Pval);
836 if (Preg == 0x4020) {
838 nv32_wr(pScrn, 0x4020, Pval);
839 nv32_wr(pScrn, 0x4038, Pval);
840 nv32_wr(pScrn, 0x4600, saved4600);
843 nv32_wr(pScrn, 0xc040, savedc040);
845 if (Preg == 0x4020) {
846 nv32_wr(pScrn, 0x4020, Pval & ~(1 << 28));
847 nv32_wr(pScrn, 0x4038, Pval & ~(1 << 28));
851 static void setPLL(ScrnInfoPtr pScrn, bios_t *bios, uint32_t reg, uint32_t clk)
854 int NM1 = 0xbeef, NM2 = 0xdead, log2P;
856 if (bios->chip_version >= 0x40 || bios->chip_version == 0x31 || bios->chip_version == 0x36) {
857 getMNP_double(pScrn, reg, clk, &NM1, &NM2, &log2P);
859 setPLL_double_highregs(pScrn, reg, NM1, NM2, log2P);
861 setPLL_double_lowregs(pScrn, reg, NM1, NM2, log2P);
863 getMNP_single(pScrn, clk, &NM1, &log2P);
864 setPLL_single(pScrn, reg, NM1, log2P);
869 static Bool init_prog(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
871 /* INIT_PROG opcode: 0x31
873 * offset (8 bit): opcode
874 * offset + 1 (32 bit): reg
875 * offset + 5 (32 bit): and mask
876 * offset + 9 (8 bit): shift right
877 * offset + 10 (8 bit): number of configurations
878 * offset + 11 (32 bit): register
879 * offset + 15 (32 bit): configuration 1
882 * Starting at offset + 15 there are "number of configurations"
883 * 32 bit values. To find out which configuration value to use
884 * read "CRTC reg" on the CRTC controller with index "CRTC index"
885 * and bitwise AND this value with "and mask" and then bit shift the
886 * result "shift right" bits to the right.
887 * Assign "register" with appropriate configuration value.
890 CARD32 reg = *((CARD32 *) (&bios->data[offset + 1]));
891 CARD32 and = *((CARD32 *) (&bios->data[offset + 5]));
892 CARD8 shiftr = *((CARD8 *) (&bios->data[offset + 9]));
893 CARD8 nr = *((CARD8 *) (&bios->data[offset + 10]));
894 CARD32 reg2 = *((CARD32 *) (&bios->data[offset + 11]));
896 CARD32 configval, tmp;
898 if (iexec->execute) {
899 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: REG: 0x%04X\n", offset,
902 tmp = nv32_rd(pScrn, reg);
903 configuration = (tmp & and) >> shiftr;
905 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONFIGURATION TO USE: 0x%02X\n",
906 offset, configuration);
908 if (configuration <= nr) {
911 *((CARD32 *) (&bios->data[offset + 15 + configuration * 4]));
913 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: REG: 0x%08X, VALUE: 0x%08X\n", offset,
916 tmp = nv32_rd(pScrn, reg2);
917 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CURRENT VALUE IS: 0x%08X\n",
919 nv32_wr(pScrn, reg2, configval);
926 static Bool init_io_restrict_prog(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
928 /* INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
930 * offset (8 bit): opcode
931 * offset + 1 (16 bit): CRTC port
932 * offset + 3 (8 bit): CRTC index
933 * offset + 4 (8 bit): mask
934 * offset + 5 (8 bit): shift
935 * offset + 6 (8 bit): count
936 * offset + 7 (32 bit): register
937 * offset + 11 (32 bit): configuration 1
940 * Starting at offset + 11 there are "count" 32 bit values.
941 * To find out which value to use read index "CRTC index" on "CRTC port",
942 * AND this value with "mask" and then bit shift right "shift" bits.
943 * Read the appropriate value using this index and write to "register"
946 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
947 uint8_t crtcindex = bios->data[offset + 3];
948 uint8_t mask = bios->data[offset + 4];
949 uint8_t shift = bios->data[offset + 5];
950 uint8_t count = bios->data[offset + 6];
951 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7])));
959 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
960 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
961 offset, crtcport, crtcindex, mask, shift, count, reg);
963 config = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) >> shift;
964 if (config > count) {
965 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
966 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
967 offset, config, count);
971 configval = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 11 + config * 4])));
974 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
975 "0x%04X: Writing config %02X\n", offset, config);
977 nv32_wr(pScrn, reg, configval);
982 static Bool init_repeat(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
984 /* INIT_REPEAT opcode: 0x33 ('3')
986 * offset (8 bit): opcode
987 * offset + 1 (8 bit): count
989 * Execute script following this opcode up to INIT_REPEAT_END
993 uint8_t count = bios->data[offset + 1];
996 /* no iexec->execute check by design */
998 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
999 "0x%04X: REPEATING FOLLOWING SEGMENT %d TIMES\n",
1002 iexec->repeat = TRUE;
1004 /* count - 1, as the script block will execute once when we leave this
1005 * opcode -- this is compatible with bios behaviour as:
1006 * a) the block is always executed at least once, even if count == 0
1007 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
1010 for (i = 0; i < count - 1; i++)
1011 parse_init_table(pScrn, bios, offset + 2, iexec);
1013 iexec->repeat = FALSE;
1018 static Bool init_io_restrict_pll(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1020 /* INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
1022 * offset (8 bit): opcode
1023 * offset + 1 (16 bit): CRTC port
1024 * offset + 3 (8 bit): CRTC index
1025 * offset + 4 (8 bit): mask
1026 * offset + 5 (8 bit): shift
1027 * offset + 6 (8 bit): IO flag condition index
1028 * offset + 7 (8 bit): count
1029 * offset + 8 (32 bit): register
1030 * offset + 12 (16 bit): frequency 1
1033 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
1034 * Set PLL register "register" to coefficients for frequency n,
1035 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1036 * "mask" and shifted right by "shift". If "IO flag condition index" > 0,
1037 * and condition met, double frequency before setting it.
1040 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1041 uint8_t crtcindex = bios->data[offset + 3];
1042 uint8_t mask = bios->data[offset + 4];
1043 uint8_t shift = bios->data[offset + 5];
1044 int8_t io_flag_condition_idx = bios->data[offset + 6];
1045 uint8_t count = bios->data[offset + 7];
1046 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 8])));
1050 if (!iexec->execute)
1053 if (DEBUGLEVEL >= 6)
1054 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1055 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, IO Flag Condition: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1056 offset, crtcport, crtcindex, mask, shift, io_flag_condition_idx, count, reg);
1058 config = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) >> shift;
1059 if (config > count) {
1060 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1061 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1062 offset, config, count);
1066 freq = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 12 + config * 2])));
1068 if (io_flag_condition_idx > 0) {
1069 if (io_flag_condition(pScrn, bios, offset, io_flag_condition_idx)) {
1070 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1071 "0x%04X: CONDITION FULFILLED - FREQ DOUBLED\n", offset);
1074 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1075 "0x%04X: CONDITION IS NOT FULFILLED. FREQ UNCHANGED\n", offset);
1078 if (DEBUGLEVEL >= 6)
1079 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1080 "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
1081 offset, reg, config, freq);
1083 setPLL(pScrn, bios, reg, freq * 10);
1088 static Bool init_end_repeat(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1090 /* INIT_END_REPEAT opcode: 0x36 ('6')
1092 * offset (8 bit): opcode
1094 * Marks the end of the block for INIT_REPEAT to repeat
1097 /* no iexec->execute check by design */
1099 /* iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
1100 * we're not in repeat mode
1108 static Bool init_copy(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1110 /* INIT_COPY opcode: 0x37 ('7')
1112 * offset (8 bit): opcode
1113 * offset + 1 (32 bit): register
1114 * offset + 5 (8 bit): shift
1115 * offset + 6 (8 bit): srcmask
1116 * offset + 7 (16 bit): CRTC port
1117 * offset + 9 (8 bit): CRTC index
1118 * offset + 10 (8 bit): mask
1120 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
1121 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC port
1124 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1125 uint8_t shift = bios->data[offset + 5];
1126 uint8_t srcmask = bios->data[offset + 6];
1127 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 7])));
1128 uint8_t crtcindex = bios->data[offset + 9];
1129 uint8_t mask = bios->data[offset + 10];
1133 if (!iexec->execute)
1136 if (DEBUGLEVEL >= 6)
1137 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1138 "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1139 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1141 data = nv32_rd(pScrn, reg);
1146 data <<= (0x100 - shift);
1150 crtcdata = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) | (uint8_t)data;
1151 nv_idx_port_wr(pScrn, crtcport, crtcindex, crtcdata);
1156 static Bool init_not(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1158 /* INIT_NOT opcode: 0x38 ('8')
1160 * offset (8 bit): opcode
1162 * Invert the current execute / no-execute condition (i.e. "else")
1165 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1166 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
1168 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1169 "0x%04X: ------ EXECUTING FOLLOWING COMMANDS ------\n", offset);
1171 iexec->execute = !iexec->execute;
1175 static Bool init_io_flag_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1177 /* INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1179 * offset (8 bit): opcode
1180 * offset + 1 (8 bit): condition number
1182 * Check condition "condition number" in the IO flag condition table.
1183 * If condition not met skip subsequent opcodes until condition
1184 * is inverted (INIT_NOT), or we hit INIT_RESUME
1187 uint8_t cond = bios->data[offset + 1];
1189 if (!iexec->execute)
1192 if (io_flag_condition(pScrn, bios, offset, cond))
1193 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1194 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n", offset);
1196 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1197 "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
1198 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1199 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
1200 iexec->execute = FALSE;
1206 Bool init_idx_addr_latched(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1208 /* INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1210 * offset (8 bit): opcode
1211 * offset + 1 (32 bit): control register
1212 * offset + 5 (32 bit): data register
1213 * offset + 9 (32 bit): mask
1214 * offset + 13 (32 bit): data
1215 * offset + 17 (8 bit): count
1216 * offset + 18 (8 bit): address 1
1217 * offset + 19 (8 bit): data 1
1220 * For each of "count" address and data pairs, write "data n" to "data register",
1221 * read the current value of "control register", and write it back once ANDed
1222 * with "mask", ORed with "data", and ORed with "address n"
1225 uint32_t controlreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1226 uint32_t datareg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1227 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
1228 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 13])));
1229 uint8_t count = bios->data[offset + 17];
1233 if (!iexec->execute)
1236 if (DEBUGLEVEL >= 6)
1237 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1238 "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1239 offset, controlreg, datareg, mask, data, count);
1241 for (i = 0; i < count; i++) {
1242 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1243 uint8_t instdata = bios->data[offset + 19 + i * 2];
1245 if (DEBUGLEVEL >= 6)
1246 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1247 "0x%04X: Address: 0x%02X, Data: 0x%02X\n", offset, instaddress, instdata);
1249 nv32_wr(pScrn, datareg, instdata);
1250 value = (nv32_rd(pScrn, controlreg) & mask) | data | instaddress;
1251 nv32_wr(pScrn, controlreg, value);
1257 static Bool init_io_restrict_pll2(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1259 /* INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1261 * offset (8 bit): opcode
1262 * offset + 1 (16 bit): CRTC port
1263 * offset + 3 (8 bit): CRTC index
1264 * offset + 4 (8 bit): mask
1265 * offset + 5 (8 bit): shift
1266 * offset + 6 (8 bit): count
1267 * offset + 7 (32 bit): register
1268 * offset + 11 (32 bit): frequency 1
1271 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1272 * Set PLL register "register" to coefficients for frequency n,
1273 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1274 * "mask" and shifted right by "shift".
1277 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1278 uint8_t crtcindex = bios->data[offset + 3];
1279 uint8_t mask = bios->data[offset + 4];
1280 uint8_t shift = bios->data[offset + 5];
1281 uint8_t count = bios->data[offset + 6];
1282 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7])));
1286 if (!iexec->execute)
1289 if (DEBUGLEVEL >= 6)
1290 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1291 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1292 offset, crtcport, crtcindex, mask, shift, count, reg);
1297 config = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) >> shift;
1298 if (config > count) {
1299 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1300 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1301 offset, config, count);
1305 freq = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 11 + config * 4])));
1307 if (DEBUGLEVEL >= 6)
1308 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1309 "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1310 offset, reg, config, freq);
1312 setPLL(pScrn, bios, reg, freq);
1317 static Bool init_pll2(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1319 /* INIT_PLL2 opcode: 0x4B ('K')
1321 * offset (8 bit): opcode
1322 * offset + 1 (32 bit): register
1323 * offset + 5 (32 bit): freq
1325 * Set PLL register "register" to coefficients for frequency "freq"
1328 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1329 uint32_t freq = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1331 if (!iexec->execute)
1334 if (DEBUGLEVEL >= 6)
1335 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1336 "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1339 setPLL(pScrn, bios, reg, freq);
1344 static uint32_t get_tmds_index_reg(ScrnInfoPtr pScrn, uint8_t mlv)
1346 /* For mlv < 0x80, it is an index into a table of TMDS base addresses
1347 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by CR58 for CR57 = 0
1348 * to index a table of offsets to the basic 0x6808b0 address
1349 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by CR58 for CR57 = 0
1350 * to index a table of offsets to the basic 0x6808b0 address, and then flip the offset by 8
1353 NVPtr pNv = NVPTR(pScrn);
1354 int pramdac_offset[13] = {0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000};
1355 uint32_t pramdac_table[4] = {0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8};
1358 /* here we assume that the DCB table has already been parsed */
1361 /* This register needs to be written to set index for reading CR58 */
1362 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, 0x57, 0);
1363 dcb_entry = nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, 0x58);
1364 if (dcb_entry > pNv->dcb_table.entries) {
1365 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1366 "CR58 doesn't have a valid DCB entry currently (%02X)\n", dcb_entry);
1369 dacoffset = pramdac_offset[pNv->dcb_table.entry[dcb_entry].or];
1372 return (0x6808b0 + dacoffset);
1374 if (mlv > (sizeof(pramdac_table) / sizeof(uint32_t))) {
1375 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1376 "Magic Lookup Value too big (%02X)\n", mlv);
1379 return pramdac_table[mlv];
1383 static Bool init_tmds(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1385 /* INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1387 * offset (8 bit): opcode
1388 * offset + 1 (8 bit): magic lookup value
1389 * offset + 2 (8 bit): TMDS address
1390 * offset + 3 (8 bit): mask
1391 * offset + 4 (8 bit): data
1393 * Read the data reg for TMDS address "TMDS address", AND it with mask
1394 * and OR it with data, then write it back
1395 * "magic lookup value" determines which TMDS base address register is used --
1396 * see get_tmds_index_reg()
1399 uint8_t mlv = bios->data[offset + 1];
1400 uint32_t tmdsaddr = bios->data[offset + 2];
1401 uint8_t mask = bios->data[offset + 3];
1402 uint8_t data = bios->data[offset + 4];
1403 uint32_t reg, value;
1405 if (!iexec->execute)
1408 if (DEBUGLEVEL >= 6)
1409 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1410 "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1411 offset, mlv, tmdsaddr, mask, data);
1413 reg = get_tmds_index_reg(pScrn, mlv);
1415 nv32_wr(pScrn, reg, tmdsaddr | 0x10000);
1416 value = (nv32_rd(pScrn, reg + 4) & mask) | data;
1417 nv32_wr(pScrn, reg + 4, value);
1418 nv32_wr(pScrn, reg, tmdsaddr);
1423 Bool init_zm_tmds_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1425 /* INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1427 * offset (8 bit): opcode
1428 * offset + 1 (8 bit): magic lookup value
1429 * offset + 2 (8 bit): count
1430 * offset + 3 (8 bit): addr 1
1431 * offset + 4 (8 bit): data 1
1434 * For each of "count" TMDS address and data pairs write "data n" to "addr n"
1435 * "magic lookup value" determines which TMDS base address register is used --
1436 * see get_tmds_index_reg()
1439 uint8_t mlv = bios->data[offset + 1];
1440 uint8_t count = bios->data[offset + 2];
1444 if (!iexec->execute)
1447 if (DEBUGLEVEL >= 6)
1448 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1449 "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1450 offset, mlv, count);
1452 reg = get_tmds_index_reg(pScrn, mlv);
1454 for (i = 0; i < count; i++) {
1455 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1456 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1458 nv32_wr(pScrn, reg + 4, tmdsdata);
1459 nv32_wr(pScrn, reg, tmdsaddr);
1465 Bool init_cr_idx_adr_latch(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1467 /* INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1469 * offset (8 bit): opcode
1470 * offset + 1 (8 bit): CRTC index1
1471 * offset + 2 (8 bit): CRTC index2
1472 * offset + 3 (8 bit): baseaddr
1473 * offset + 4 (8 bit): count
1474 * offset + 5 (8 bit): data 1
1477 * For each of "count" address and data pairs, write "baseaddr + n" to
1478 * "CRTC index1" and "data n" to "CRTC index2"
1479 * Once complete, restore initial value read from "CRTC index1"
1481 uint8_t crtcindex1 = bios->data[offset + 1];
1482 uint8_t crtcindex2 = bios->data[offset + 2];
1483 uint8_t baseaddr = bios->data[offset + 3];
1484 uint8_t count = bios->data[offset + 4];
1485 uint8_t oldaddr, data;
1488 if (!iexec->execute)
1491 if (DEBUGLEVEL >= 6)
1492 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1493 "0x%04X: Index1: 0x%02X, Index2: 0x%02X, BaseAddr: 0x%02X, Count: 0x%02X\n",
1494 offset, crtcindex1, crtcindex2, baseaddr, count);
1496 oldaddr = nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, crtcindex1);
1498 for (i = 0; i < count; i++) {
1499 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex1, baseaddr + i);
1501 data = bios->data[offset + 5 + i];
1502 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex2, data);
1505 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex1, oldaddr);
1510 Bool init_cr(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1512 /* INIT_CR opcode: 0x52 ('R')
1514 * offset (8 bit): opcode
1515 * offset + 1 (8 bit): CRTC index
1516 * offset + 2 (8 bit): mask
1517 * offset + 3 (8 bit): data
1519 * Assign the value of at "CRTC index" ANDed with mask and ORed with data
1520 * back to "CRTC index"
1523 uint8_t crtcindex = bios->data[offset + 1];
1524 uint8_t mask = bios->data[offset + 2];
1525 uint8_t data = bios->data[offset + 3];
1528 if (!iexec->execute)
1531 if (DEBUGLEVEL >= 6)
1532 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1533 "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1534 offset, crtcindex, mask, data);
1536 value = (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, crtcindex) & mask) | data;
1537 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex, value);
1542 static Bool init_zm_cr(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1544 /* INIT_ZM_CR opcode: 0x53 ('S')
1546 * offset (8 bit): opcode
1547 * offset + 1 (8 bit): CRTC index
1548 * offset + 2 (8 bit): value
1550 * Assign "value" to CRTC register with index "CRTC index".
1553 uint8_t crtcindex = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1554 uint8_t data = bios->data[offset + 2];
1556 if (!iexec->execute)
1559 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex, data);
1564 static Bool init_zm_cr_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1566 /* INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1568 * offset (8 bit): opcode
1569 * offset + 1 (8 bit): count
1570 * offset + 2 (8 bit): CRTC index 1
1571 * offset + 3 (8 bit): value 1
1574 * For "count", assign "value n" to CRTC register with index "CRTC index n".
1577 uint8_t count = bios->data[offset + 1];
1580 if (!iexec->execute)
1583 for (i = 0; i < count; i++)
1584 init_zm_cr(pScrn, bios, offset + 2 + 2 * i - 1, iexec);
1589 static Bool init_condition_time(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1591 /* INIT_CONDITION_TIME opcode: 0x56 ('V')
1593 * offset (8 bit): opcode
1594 * offset + 1 (8 bit): condition number
1595 * offset + 2 (8 bit): retries / 50
1597 * Check condition "condition number" in the condition table.
1598 * The condition table entry has 4 bytes for the address of the
1599 * register to check, 4 bytes for a mask and 4 for a test value.
1600 * If condition not met sleep for 2ms, and repeat upto "retries" times.
1601 * If still not met after retries, clear execution flag for this table.
1604 uint8_t cond = bios->data[offset + 1];
1605 uint16_t retries = bios->data[offset + 2];
1606 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
1607 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[condptr])));
1608 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 4])));
1609 uint32_t cmpval = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 8])));
1612 if (!iexec->execute)
1617 if (DEBUGLEVEL >= 6)
1618 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1619 "0x%04X: Cond: 0x%02X, Retries: 0x%02X\n", offset, cond, retries);
1621 for (; retries > 0; retries--) {
1622 data = nv32_rd(pScrn, reg) & mask;
1624 if (DEBUGLEVEL >= 6)
1625 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1626 "0x%04X: Checking if 0x%08X equals 0x%08X\n",
1627 offset, data, cmpval);
1629 if (data != cmpval) {
1630 if (DEBUGLEVEL >= 6)
1631 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1632 "0x%04X: Condition not met, sleeping for 2ms\n", offset);
1635 if (DEBUGLEVEL >= 6)
1636 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1637 "0x%04X: Condition met, continuing\n", offset);
1642 if (data != cmpval) {
1643 if (DEBUGLEVEL >= 6)
1644 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1645 "0x%04X: Condition still not met, skiping following opcodes\n", offset);
1646 iexec->execute = FALSE;
1652 static Bool init_zm_reg_sequence(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1654 /* INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1656 * offset (8 bit): opcode
1657 * offset + 1 (32 bit): base register
1658 * offset + 5 (8 bit): count
1659 * offset + 6 (32 bit): value 1
1662 * Starting at offset + 6 there are "count" 32 bit values.
1663 * For "count" iterations set "base register" + 4 * current_iteration
1664 * to "value current_iteration"
1667 uint32_t basereg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1668 uint32_t count = bios->data[offset + 5];
1671 if (!iexec->execute)
1674 if (DEBUGLEVEL >= 6)
1675 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1676 "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1677 offset, basereg, count);
1679 for (i = 0; i < count; i++) {
1680 uint32_t reg = basereg + i * 4;
1681 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 6 + i * 4])));
1683 nv32_wr(pScrn, reg, data);
1690 static Bool init_indirect_reg(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
1692 /* INIT_INDIRECT_REG opcode: 0x5A
1694 * offset (8 bit): opcode
1695 * offset + 1 (32 bit): register
1696 * offset + 5 (16 bit): adress offset (in bios)
1698 * Lookup value at offset data in the bios and write it to reg
1700 CARD32 reg = *((CARD32 *) (&bios->data[offset + 1]));
1701 CARD16 data = le16_to_cpu(*((CARD16 *) (&bios->data[offset + 5])));
1702 CARD32 data2 = bios->data[data];
1704 if (iexec->execute) {
1705 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1706 "0x%04X: REG: 0x%04X, DATA AT: 0x%04X, VALUE IS: 0x%08X\n",
1707 offset, reg, data, data2);
1709 if (DEBUGLEVEL >= 6) {
1711 tmpval = nv32_rd(pScrn, reg);
1712 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CURRENT VALUE IS: 0x%08X\n", offset, tmpval);
1715 nv32_wr(pScrn, reg, data2);
1721 static Bool init_sub_direct(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1723 /* INIT_SUB_DIRECT opcode: 0x5B ('[')
1725 * offset (8 bit): opcode
1726 * offset + 1 (16 bit): subroutine offset (in bios)
1728 * Calls a subroutine that will execute commands until INIT_DONE
1732 uint16_t sub_offset = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1734 if (!iexec->execute)
1737 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: EXECUTING SUB-ROUTINE AT 0x%04X\n",
1738 offset, sub_offset);
1740 parse_init_table(pScrn, bios, sub_offset, iexec);
1742 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: END OF SUB-ROUTINE AT 0x%04X\n",
1743 offset, sub_offset);
1748 static Bool init_copy_nv_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1750 /* INIT_COPY_NV_REG opcode: 0x5F ('_')
1752 * offset (8 bit): opcode
1753 * offset + 1 (32 bit): src reg
1754 * offset + 5 (8 bit): shift
1755 * offset + 6 (32 bit): src mask
1756 * offset + 10 (32 bit): xor
1757 * offset + 14 (32 bit): dst reg
1758 * offset + 18 (32 bit): dst mask
1760 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
1761 * "src mask", then XOR with "xor". Write this OR'd with
1762 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
1765 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
1766 uint8_t shift = bios->data[offset + 5];
1767 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
1768 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
1769 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
1770 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
1771 uint32_t srcvalue, dstvalue;
1773 if (!iexec->execute)
1776 if (DEBUGLEVEL >= 6)
1777 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1778 "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
1779 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
1781 srcvalue = nv32_rd(pScrn, srcreg);
1786 srcvalue <<= (0x100 - shift);
1788 srcvalue = (srcvalue & srcmask) ^ xor;
1790 dstvalue = nv32_rd(pScrn, dstreg) & dstmask;
1792 nv32_wr(pScrn, dstreg, dstvalue | srcvalue);
1797 static Bool init_zm_index_io(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1799 /* INIT_ZM_INDEX_IO opcode: 0x62 ('b')
1801 * offset (8 bit): opcode
1802 * offset + 1 (16 bit): CRTC port
1803 * offset + 3 (8 bit): CRTC index
1804 * offset + 4 (8 bit): data
1806 * Write "data" to index "CRTC index" of "CRTC port"
1808 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1809 uint8_t crtcindex = bios->data[offset + 3];
1810 uint8_t data = bios->data[offset + 4];
1812 if (!iexec->execute)
1815 nv_idx_port_wr(pScrn, crtcport, crtcindex, data);
1820 static Bool init_compute_mem(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1822 /* INIT_COMPUTE_MEM opcode: 0x63 ('c')
1824 * offset (8 bit): opcode
1826 * This opcode is meant to set NV_PFB_CFG0 (0x100200) appropriately so
1827 * that the hardware can correctly calculate how much VRAM it has
1828 * (and subsequently report that value in 0x10020C)
1830 * The implementation of this opcode in general consists of two parts:
1831 * 1) determination of the memory bus width
1832 * 2) determination of how many of the card's RAM pads have ICs attached
1834 * 1) is done by a cunning combination of writes to offsets 0x1c and
1835 * 0x3c in the framebuffer, and seeing whether the written values are
1836 * read back correctly. This then affects bits 4-7 of NV_PFB_CFG0
1838 * 2) is done by a cunning combination of writes to an offset slightly
1839 * less than the maximum memory reported by 0x10020C, then seeing if
1840 * the test pattern can be read back. This then affects bits 12-15 of
1843 * In this context a "cunning combination" may include multiple reads
1844 * and writes to varying locations, often alternating the test pattern
1845 * and 0, doubtless to make sure buffers are filled, residual charges
1846 * on tracks are removed etc.
1848 * Unfortunately, the "cunning combination"s mentioned above, and the
1849 * changes to the bits in NV_PFB_CFG0 differ with nearly every bios
1852 * Therefore, we cheat and assume the value of NV_PFB_CFG0 with which
1853 * we started was correct, and use that instead
1856 /* no iexec->execute check by design */
1858 /* on every card I've seen, this step gets done for us earlier in the init scripts
1859 uint8_t crdata = nv_idx_port_rd(pScrn, VGA_SEQ_INDEX, 0x01);
1860 nv_idx_port_wr(pScrn, VGA_SEQ_INDEX, 0x01, crdata | 0x20);
1863 /* this also has probably been done in the scripts, but an mmio trace of
1864 * s3 resume shows nvidia doing it anyway (unlike the VGA_SEQ_INDEX write)
1866 nv32_wr(pScrn, NV_PFB_REFCTRL, NV_PFB_REFCTRL_VALID_1);
1868 /* write back the saved configuration value */
1869 nv32_wr(pScrn, NV_PFB_CFG0, saved_nv_pfb_cfg0);
1874 static Bool init_reset(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1876 /* INIT_RESET opcode: 0x65 ('e')
1878 * offset (8 bit): opcode
1879 * offset + 1 (32 bit): register
1880 * offset + 5 (32 bit): value1
1881 * offset + 9 (32 bit): value2
1883 * Assign "value1" to "register", then assign "value2" to "register"
1886 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1887 uint32_t value1 = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1888 uint32_t value2 = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
1889 uint32_t pci_nv_19, pci_nv_20;
1891 /* no iexec->execute check by design */
1893 pci_nv_19 = nv32_rd(pScrn, NV_PBUS_PCI_NV_19);
1894 nv32_wr(pScrn, NV_PBUS_PCI_NV_19, 0);
1895 nv32_wr(pScrn, reg, value1);
1899 nv32_wr(pScrn, reg, value2);
1900 nv32_wr(pScrn, NV_PBUS_PCI_NV_19, pci_nv_19);
1902 pci_nv_20 = nv32_rd(pScrn, NV_PBUS_PCI_NV_20);
1903 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
1904 nv32_wr(pScrn, NV_PBUS_PCI_NV_20, pci_nv_20);
1910 static Bool init_index_io8(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
1912 /* INIT_INDEX_IO8 opcode: 0x69
1914 * offset (8 bit): opcode
1915 * offset + 1 (16 bit): CRTC reg
1916 * offset + 3 (8 bit): and mask
1917 * offset + 4 (8 bit): or with
1922 NVPtr pNv = NVPTR(pScrn);
1923 volatile CARD8 *ptr = crtchead ? pNv->PCIO1 : pNv->PCIO0;
1924 CARD16 reg = le16_to_cpu(*((CARD16 *)(&bios->data[offset + 1])));
1925 CARD8 and = *((CARD8 *)(&bios->data[offset + 3]));
1926 CARD8 or = *((CARD8 *)(&bios->data[offset + 4]));
1929 if (iexec->execute) {
1930 data = (VGA_RD08(ptr, reg) & and) | or;
1932 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1933 "0x%04X: CRTC REG: 0x%04X, VALUE: 0x%02X\n",
1935 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CURRENT VALUE IS: 0x%02X\n", offset,
1936 VGA_RD08(ptr, reg));
1938 #ifdef PERFORM_WRITE
1939 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "init_index_io8 crtcreg 0x%X value 0x%X\n",reg,data);
1941 VGA_WR08(ptr, reg, data);
1948 static Bool init_sub(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1950 /* INIT_SUB opcode: 0x6B ('k')
1952 * offset (8 bit): opcode
1953 * offset + 1 (8 bit): script number
1955 * Execute script number "script number", as a subroutine
1958 uint8_t sub = bios->data[offset + 1];
1960 if (!iexec->execute)
1963 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1964 "0x%04X: EXECUTING SUB-SCRIPT %d\n", offset, sub);
1966 parse_init_table(pScrn, bios,
1967 le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + sub * 2]))),
1970 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1971 "0x%04X: END OF SUB-SCRIPT %d\n", offset, sub);
1977 static Bool init_ram_condition(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
1979 /* INIT_RAM_CONDITION opcode: 0x6D
1981 * offset (8 bit): opcode
1982 * offset + 1 (8 bit): and mask
1983 * offset + 2 (8 bit): cmpval
1985 * Test if (NV_PFB_BOOT & and mask) matches cmpval
1987 NVPtr pNv = NVPTR(pScrn);
1988 CARD8 and = *((CARD8 *) (&bios->data[offset + 1]));
1989 CARD8 cmpval = *((CARD8 *) (&bios->data[offset + 2]));
1992 if (iexec->execute) {
1993 data=(pNv->PFB[NV_PFB_BOOT/4])∧
1995 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1996 "0x%04X: CHECKING IF REGVAL: 0x%08X equals COND: 0x%08X\n",
1997 offset, data, cmpval);
1999 if (data == cmpval) {
2000 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2001 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n",
2004 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
2005 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2006 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
2007 iexec->execute = FALSE;
2014 static Bool init_nv_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2016 /* INIT_NV_REG opcode: 0x6E ('n')
2018 * offset (8 bit): opcode
2019 * offset + 1 (32 bit): register
2020 * offset + 5 (32 bit): mask
2021 * offset + 9 (32 bit): data
2023 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2026 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2027 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
2028 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
2030 if (!iexec->execute)
2033 if (DEBUGLEVEL >= 6)
2034 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2035 "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2036 offset, reg, mask, data);
2038 nv32_wr(pScrn, reg, (nv32_rd(pScrn, reg) & mask) | data);
2043 static Bool init_macro(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2045 /* INIT_MACRO opcode: 0x6F ('o')
2047 * offset (8 bit): opcode
2048 * offset + 1 (8 bit): macro number
2050 * Look up macro index "macro number" in the macro index table.
2051 * The macro index table entry has 1 byte for the index in the macro table,
2052 * and 1 byte for the number of times to repeat the macro.
2053 * The macro table entry has 4 bytes for the register address and
2054 * 4 bytes for the value to write to that register
2057 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2058 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2059 uint8_t macro_tbl_idx = bios->data[tmp];
2060 uint8_t count = bios->data[tmp + 1];
2064 if (!iexec->execute)
2067 if (DEBUGLEVEL >= 6)
2068 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2069 "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, Count: 0x%02X\n",
2070 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2072 for (i = 0; i < count; i++) {
2073 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2075 reg = le32_to_cpu(*((uint32_t *)(&bios->data[macroentryptr])));
2076 data = le32_to_cpu(*((uint32_t *)(&bios->data[macroentryptr + 4])));
2078 nv32_wr(pScrn, reg, data);
2084 static Bool init_done(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2086 /* INIT_DONE opcode: 0x71 ('q')
2088 * offset (8 bit): opcode
2090 * End the current script
2093 /* mild retval abuse to stop parsing this table */
2097 static Bool init_resume(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2099 /* INIT_RESUME opcode: 0x72 ('r')
2101 * offset (8 bit): opcode
2103 * End the current execute / no-execute condition
2109 iexec->execute = TRUE;;
2110 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2111 "0x%04X: ---- EXECUTING FOLLOWING COMMANDS ----\n", offset);
2117 static Bool init_ram_condition2(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
2119 /* INIT_RAM_CONDITION2 opcode: 0x73
2121 * offset (8 bit): opcode
2122 * offset + 1 (8 bit): and mask
2123 * offset + 2 (8 bit): cmpval
2125 * Test if (NV_EXTDEV_BOOT & and mask) matches cmpval
2127 NVPtr pNv = NVPTR(pScrn);
2128 CARD32 and = *((CARD32 *) (&bios->data[offset + 1]));
2129 CARD32 cmpval = *((CARD32 *) (&bios->data[offset + 5]));
2132 if (iexec->execute) {
2133 data=(nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT))∧
2135 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2136 "0x%04X: CHECKING IF REGVAL: 0x%08X equals COND: 0x%08X\n",
2137 offset, data, cmpval);
2139 if (data == cmpval) {
2140 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2141 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n",
2144 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
2145 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2146 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
2147 iexec->execute = FALSE;
2154 static Bool init_time(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2156 /* INIT_TIME opcode: 0x74 ('t')
2158 * offset (8 bit): opcode
2159 * offset + 1 (16 bit): time
2161 * Sleep for "time" microseconds.
2164 uint16_t time = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
2166 if (!iexec->execute)
2169 if (DEBUGLEVEL >= 6)
2170 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2171 "0x%04X: Sleeping for 0x%04X microseconds\n", offset, time);
2178 static Bool init_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2180 /* INIT_CONDITION opcode: 0x75 ('u')
2182 * offset (8 bit): opcode
2183 * offset + 1 (8 bit): condition number
2185 * Check condition "condition number" in the condition table.
2186 * The condition table entry has 4 bytes for the address of the
2187 * register to check, 4 bytes for a mask and 4 for a test value.
2188 * If condition not met skip subsequent opcodes until condition
2189 * is inverted (INIT_NOT), or we hit INIT_RESUME
2192 uint8_t cond = bios->data[offset + 1];
2193 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
2194 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[condptr])));
2195 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 4])));
2196 uint32_t cmpval = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 8])));
2199 if (!iexec->execute)
2202 if (DEBUGLEVEL >= 6)
2203 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2204 "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X, Cmpval: 0x%08X\n",
2205 offset, cond, reg, mask, cmpval);
2207 data = nv32_rd(pScrn, reg) & mask;
2209 if (DEBUGLEVEL >= 6)
2210 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2211 "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2212 offset, data, cmpval);
2214 if (data == cmpval) {
2215 if (DEBUGLEVEL >= 6)
2216 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2217 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n", offset);
2219 if (DEBUGLEVEL >= 6)
2220 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2221 "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
2222 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2223 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
2224 iexec->execute = FALSE;
2230 static Bool init_index_io(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2232 /* INIT_INDEX_IO opcode: 0x78 ('x')
2234 * offset (8 bit): opcode
2235 * offset + 1 (16 bit): CRTC port
2236 * offset + 3 (8 bit): CRTC index
2237 * offset + 4 (8 bit): mask
2238 * offset + 5 (8 bit): data
2240 * Read value at index "CRTC index" on "CRTC port", AND with "mask", OR with "data", write-back
2243 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
2244 uint8_t crtcindex = bios->data[offset + 3];
2245 uint8_t mask = bios->data[offset + 4];
2246 uint8_t data = bios->data[offset + 5];
2249 if (!iexec->execute)
2252 if (DEBUGLEVEL >= 6)
2253 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2254 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
2255 offset, crtcport, crtcindex, mask, data);
2257 value = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) | data;
2258 nv_idx_port_wr(pScrn, crtcport, crtcindex, value);
2263 static Bool init_pll(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2265 /* INIT_PLL opcode: 0x79 ('y')
2267 * offset (8 bit): opcode
2268 * offset + 1 (32 bit): register
2269 * offset + 5 (16 bit): freq
2271 * Set PLL register "register" to coefficients for frequency (10kHz) "freq"
2274 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2275 uint16_t freq = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 5])));
2277 if (!iexec->execute)
2280 if (DEBUGLEVEL >= 6)
2281 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2282 "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n",
2285 setPLL(pScrn, bios, reg, freq * 10);
2290 static Bool init_zm_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2292 /* INIT_ZM_REG opcode: 0x7A ('z')
2294 * offset (8 bit): opcode
2295 * offset + 1 (32 bit): register
2296 * offset + 5 (32 bit): value
2298 * Assign "value" to "register"
2301 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2302 uint32_t value = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
2304 if (!iexec->execute)
2307 nv32_wr(pScrn, reg, value);
2312 /* hack to avoid moving the itbl_entry array before this function */
2313 int init_ram_restrict_zm_reg_group_blocklen = 0;
2315 static Bool init_ram_restrict_zm_reg_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2317 /* INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
2319 * offset (8 bit): opcode
2320 * offset + 1 (32 bit): reg
2321 * offset + 5 (8 bit): regincrement
2322 * offset + 6 (8 bit): count
2323 * offset + 7 (32 bit): value 1,1
2326 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2327 * ram_restrict_table_ptr. The value read from here is 'n', and
2328 * "value 1,n" gets written to "reg". This repeats "count" times and on
2329 * each iteration 'm', "reg" increases by "regincrement" and
2330 * "value m,n" is used. The extent of n is limited by a number read
2331 * from the 'M' BIT table, herein called "blocklen"
2334 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2335 uint8_t regincrement = bios->data[offset + 5];
2336 uint8_t count = bios->data[offset + 6];
2337 uint32_t strap_ramcfg, data;
2342 /* previously set by 'M' BIT table */
2343 blocklen = init_ram_restrict_zm_reg_group_blocklen;
2345 if (!iexec->execute)
2349 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2350 "0x%04X: Zero block length - has the M table been parsed?\n", offset);
2354 strap_ramcfg = (nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
2355 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
2357 if (DEBUGLEVEL >= 6)
2358 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2359 "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
2360 offset, reg, regincrement, count, strap_ramcfg, index);
2362 for (i = 0; i < count; i++) {
2363 data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7 + index * 4 + blocklen * i])));
2365 nv32_wr(pScrn, reg, data);
2367 reg += regincrement;
2373 static Bool init_copy_zm_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2375 /* INIT_COPY_ZM_REG opcode: 0x90 ('')
2377 * offset (8 bit): opcode
2378 * offset + 1 (32 bit): src reg
2379 * offset + 5 (32 bit): dst reg
2381 * Put contents of "src reg" into "dst reg"
2384 uint32_t srcreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2385 uint32_t dstreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
2387 if (!iexec->execute)
2390 nv32_wr(pScrn, dstreg, nv32_rd(pScrn, srcreg));
2395 static Bool init_zm_reg_group_addr_latched(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2397 /* INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
2399 * offset (8 bit): opcode
2400 * offset + 1 (32 bit): src reg
2401 * offset + 5 (8 bit): count
2402 * offset + 6 (32 bit): data 1
2405 * For each of "count" values write "data n" to "src reg"
2408 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2409 uint8_t count = bios->data[offset + 5];
2412 if (!iexec->execute)
2415 for (i = 0; i < count; i++) {
2416 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 6 + 4 * i])));
2417 nv32_wr(pScrn, reg, data);
2423 static Bool init_reserved(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2425 /* INIT_RESERVED opcode: 0x92 ('')
2427 * offset (8 bit): opcode
2429 * Seemingly does nothing
2435 static init_tbl_entry_t itbl_entry[] = {
2436 /* command name , id , length , offset , mult , command handler */
2437 // { "INIT_PROG" , 0x31, 15 , 10 , 4 , init_prog },
2438 { "INIT_IO_RESTRICT_PROG" , 0x32, 11 , 6 , 4 , init_io_restrict_prog },
2439 { "INIT_REPEAT" , 0x33, 2 , 0 , 0 , init_repeat },
2440 { "INIT_IO_RESTRICT_PLL" , 0x34, 12 , 7 , 2 , init_io_restrict_pll },
2441 { "INIT_END_REPEAT" , 0x36, 1 , 0 , 0 , init_end_repeat },
2442 { "INIT_COPY" , 0x37, 11 , 0 , 0 , init_copy },
2443 { "INIT_NOT" , 0x38, 1 , 0 , 0 , init_not },
2444 { "INIT_IO_FLAG_CONDITION" , 0x39, 2 , 0 , 0 , init_io_flag_condition },
2445 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, 18 , 17 , 2 , init_idx_addr_latched },
2446 { "INIT_IO_RESTRICT_PLL2" , 0x4A, 11 , 6 , 4 , init_io_restrict_pll2 },
2447 { "INIT_PLL2" , 0x4B, 9 , 0 , 0 , init_pll2 },
2448 /* { "INIT_I2C_BYTE" , 0x4C, x , x , x , init_i2c_byte }, */
2449 /* { "INIT_ZM_I2C_BYTE" , 0x4D, x , x , x , init_zm_i2c_byte }, */
2450 /* { "INIT_ZM_I2C" , 0x4E, x , x , x , init_zm_i2c }, */
2451 { "INIT_TMDS" , 0x4F, 5 , 0 , 0 , init_tmds },
2452 { "INIT_ZM_TMDS_GROUP" , 0x50, 3 , 2 , 2 , init_zm_tmds_group },
2453 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, 5 , 4 , 1 , init_cr_idx_adr_latch },
2454 { "INIT_CR" , 0x52, 4 , 0 , 0 , init_cr },
2455 { "INIT_ZM_CR" , 0x53, 3 , 0 , 0 , init_zm_cr },
2456 { "INIT_ZM_CR_GROUP" , 0x54, 2 , 1 , 2 , init_zm_cr_group },
2457 { "INIT_CONDITION_TIME" , 0x56, 3 , 0 , 0 , init_condition_time },
2458 { "INIT_ZM_REG_SEQUENCE" , 0x58, 6 , 5 , 4 , init_zm_reg_sequence },
2459 // { "INIT_INDIRECT_REG" , 0x5A, 7 , 0 , 0 , init_indirect_reg },
2460 { "INIT_SUB_DIRECT" , 0x5B, 3 , 0 , 0 , init_sub_direct },
2461 { "INIT_COPY_NV_REG" , 0x5F, 22 , 0 , 0 , init_copy_nv_reg },
2462 { "INIT_ZM_INDEX_IO" , 0x62, 5 , 0 , 0 , init_zm_index_io },
2463 { "INIT_COMPUTE_MEM" , 0x63, 1 , 0 , 0 , init_compute_mem },
2464 { "INIT_RESET" , 0x65, 13 , 0 , 0 , init_reset },
2465 /* { "INIT_NEXT" , 0x66, x , x , x , init_next }, */
2466 /* { "INIT_NEXT" , 0x67, x , x , x , init_next }, */
2467 /* { "INIT_NEXT" , 0x68, x , x , x , init_next }, */
2468 // { "INIT_INDEX_IO8" , 0x69, 5 , 0 , 0 , init_index_io8 },
2469 { "INIT_SUB" , 0x6B, 2 , 0 , 0 , init_sub },
2470 // { "INIT_RAM_CONDITION" , 0x6D, 3 , 0 , 0 , init_ram_condition },
2471 { "INIT_NV_REG" , 0x6E, 13 , 0 , 0 , init_nv_reg },
2472 { "INIT_MACRO" , 0x6F, 2 , 0 , 0 , init_macro },
2473 { "INIT_DONE" , 0x71, 1 , 0 , 0 , init_done },
2474 { "INIT_RESUME" , 0x72, 1 , 0 , 0 , init_resume },
2475 // { "INIT_RAM_CONDITION2" , 0x73, 9 , 0 , 0 , init_ram_condition2 },
2476 { "INIT_TIME" , 0x74, 3 , 0 , 0 , init_time },
2477 { "INIT_CONDITION" , 0x75, 2 , 0 , 0 , init_condition },
2478 /* { "INIT_IO_CONDITION" , 0x76, x , x , x , init_io_condition }, */
2479 { "INIT_INDEX_IO" , 0x78, 6 , 0 , 0 , init_index_io },
2480 { "INIT_PLL" , 0x79, 7 , 0 , 0 , init_pll },
2481 { "INIT_ZM_REG" , 0x7A, 9 , 0 , 0 , init_zm_reg },
2482 /* INIT_RAM_RESTRICT_ZM_REG_GROUP's mult is loaded by M table in BIT */
2483 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, 7 , 6 , 0 , init_ram_restrict_zm_reg_group },
2484 { "INIT_COPY_ZM_REG" , 0x90, 9 , 0 , 0 , init_copy_zm_reg },
2485 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, 6 , 5 , 4 , init_zm_reg_group_addr_latched },
2486 { "INIT_RESERVED" , 0x92, 1 , 0 , 0 , init_reserved },
2487 { 0 , 0 , 0 , 0 , 0 , 0 }
2490 static unsigned int get_init_table_entry_length(bios_t *bios, unsigned int offset, int i)
2492 /* Calculates the length of a given init table entry. */
2493 return itbl_entry[i].length + bios->data[offset + itbl_entry[i].length_offset]*itbl_entry[i].length_multiplier;
2496 static void parse_init_table(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset, init_exec_t *iexec)
2498 /* Parses all commands in a init table. */
2500 /* We start out executing all commands found in the
2501 * init table. Some op codes may change the status
2502 * of this variable to SKIP, which will cause
2503 * the following op codes to perform no operation until
2504 * the value is changed back to EXECUTE.
2510 /* Loop until INIT_DONE causes us to break out of the loop
2511 * (or until offset > bios length just in case... )
2512 * (and no more than 10000 iterations just in case... ) */
2513 while ((offset < bios->length) && (count++ < 10000)) {
2514 id = bios->data[offset];
2516 /* Find matching id in itbl_entry */
2517 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
2520 if (itbl_entry[i].name) {
2521 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: [ (0x%02X) - %s ]\n",
2522 offset, itbl_entry[i].id, itbl_entry[i].name);
2524 /* execute eventual command handler */
2525 if (itbl_entry[i].handler)
2526 if (!(*itbl_entry[i].handler)(pScrn, bios, offset, iexec))
2529 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2530 "0x%04X: Init table command not found: 0x%02X\n", offset, id);
2534 /* Add the offset of the current command including all data
2535 * of that command. The offset will then be pointing on the
2538 offset += get_init_table_entry_length(bios, offset, i);
2542 static void parse_init_tables(ScrnInfoPtr pScrn, bios_t *bios)
2544 /* Loops and calls parse_init_table() for each present table. */
2548 init_exec_t iexec = {TRUE, FALSE};
2550 while ((table = le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + i]))))) {
2552 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: Parsing init table %d\n",
2555 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2556 "0x%04X: ------ EXECUTING FOLLOWING COMMANDS ------\n", table);
2558 parse_init_table(pScrn, bios, table, &iexec);
2563 void link_head_and_output(ScrnInfoPtr pScrn, int head, int dcb_entry, Bool overrideval)
2565 /* The BIOS scripts don't do this for us, sadly
2566 * Luckily we do know the values ;-)
2568 * head < 0 indicates we wish to force a setting with the overrideval
2569 * (for VT restore etc.)
2572 NVPtr pNv = NVPTR(pScrn);
2573 int preferred_output = (ffs(pNv->dcb_table.entry[dcb_entry].or) & OUTPUT_1) >> 1;
2574 uint8_t tmds04 = 0x80;
2575 uint32_t tmds_ctrl, tmds_ctrl2;
2577 /* Bit 3 crosswires output and bus. */
2578 if (head >= 0 && head != preferred_output)
2580 if (head < 0 && overrideval)
2583 if (pNv->dcb_table.entry[dcb_entry].type == OUTPUT_LVDS)
2586 tmds_ctrl = NV_PRAMDAC0_OFFSET + (preferred_output ? NV_PRAMDAC0_SIZE : 0) + NV_RAMDAC_FP_TMDS_CONTROL;
2587 tmds_ctrl2 = NV_PRAMDAC0_OFFSET + (preferred_output ? NV_PRAMDAC0_SIZE : 0) + NV_RAMDAC_FP_TMDS_CONTROL_2;
2589 Bool oldexecute = pNv->VBIOS.execute;
2590 pNv->VBIOS.execute = TRUE;
2591 nv32_wr(pScrn, tmds_ctrl + 4, tmds04);
2592 nv32_wr(pScrn, tmds_ctrl, 0x04);
2593 if (pNv->dcb_table.entry[dcb_entry].type == OUTPUT_LVDS && pNv->VBIOS.fp.dual_link)
2594 nv32_wr(pScrn, tmds_ctrl2 + 4, tmds04 ^ 0x08);
2596 /* I have encountered no dvi (dual-link or not) that sets to anything else. */
2597 /* Does this change beyond the 165 MHz boundary? */
2598 nv32_wr(pScrn, tmds_ctrl2 + 4, 0x0);
2600 nv32_wr(pScrn, tmds_ctrl2, 0x04);
2601 pNv->VBIOS.execute = oldexecute;
2604 static void call_lvds_manufacturer_script(ScrnInfoPtr pScrn, int head, int dcb_entry, enum LVDS_script script)
2606 NVPtr pNv = NVPTR(pScrn);
2607 bios_t *bios = &pNv->VBIOS;
2608 init_exec_t iexec = {TRUE, FALSE};
2610 uint8_t sub = bios->data[bios->fp.xlated_entry + script];
2611 uint16_t scriptofs = le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + sub * 2])));
2612 Bool power_off_for_reset;
2613 uint16_t off_on_delay;
2615 if (!bios->fp.xlated_entry || !sub || !scriptofs)
2618 if (script == LVDS_INIT && bios->data[scriptofs] != 'q') {
2619 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "LVDS init script not stubbed\n");
2623 power_off_for_reset = bios->data[bios->fp.xlated_entry] & 1;
2624 off_on_delay = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.xlated_entry + 7]);
2626 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
2627 call_lvds_manufacturer_script(pScrn, head, dcb_entry, LVDS_RESET);
2628 if (script == LVDS_RESET && power_off_for_reset)
2629 call_lvds_manufacturer_script(pScrn, head, dcb_entry, LVDS_PANEL_OFF);
2631 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Calling LVDS script %d:\n", script);
2632 pNv->VBIOS.execute = TRUE;
2633 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_OWNER,
2634 head ? NV_VGA_CRTCX_OWNER_HEADB : NV_VGA_CRTCX_OWNER_HEADA);
2635 parse_init_table(pScrn, bios, scriptofs, &iexec);
2636 pNv->VBIOS.execute = FALSE;
2638 if (script == LVDS_PANEL_OFF)
2639 usleep(off_on_delay * 1000);
2640 if (script == LVDS_RESET)
2641 link_head_and_output(pScrn, head, dcb_entry, FALSE);
2644 static uint16_t clkcmptable(bios_t *bios, uint16_t clktable, int pxclk)
2646 int compare_record_len, i = 0;
2647 uint16_t compareclk, scriptptr = 0;
2649 if (bios->major_version < 5) /* pre BIT */
2650 compare_record_len = 3;
2652 compare_record_len = 4;
2655 compareclk = le16_to_cpu(*((uint16_t *)&bios->data[clktable + compare_record_len * i]));
2656 if (pxclk >= compareclk * 10) {
2657 if (bios->major_version < 5) {
2658 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
2659 scriptptr = le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + tmdssub * 2])));
2661 scriptptr = le16_to_cpu(*((uint16_t *)&bios->data[clktable + 2 + compare_record_len * i]));
2665 } while (compareclk);
2670 static void rundigitaloutscript(ScrnInfoPtr pScrn, uint16_t scriptptr, int head, int dcb_entry)
2672 bios_t *bios = &NVPTR(pScrn)->VBIOS;
2673 init_exec_t iexec = {TRUE, FALSE};
2675 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: Parsing digital output script table\n", scriptptr);
2676 bios->execute = TRUE;
2677 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_OWNER,
2678 head ? NV_VGA_CRTCX_OWNER_HEADB : NV_VGA_CRTCX_OWNER_HEADA);
2679 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, 0x57, 0);
2680 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, 0x58, dcb_entry);
2681 parse_init_table(pScrn, bios, scriptptr, &iexec);
2682 bios->execute = FALSE;
2684 link_head_and_output(pScrn, head, dcb_entry, FALSE);
2687 static void run_lvds_table(ScrnInfoPtr pScrn, int head, int dcb_entry, enum LVDS_script script, int pxclk)
2689 /* The BIT LVDS table's header has the information to setup the
2690 * necessary registers. Following the standard 4 byte header are:
2691 * A bitmask byte and a dual-link transition pxclk value for use in
2692 * selecting the init script when not using straps; 4 script pointers
2693 * for panel power, selected by output and on/off; and 8 table pointers
2694 * for panel init, the needed one determined by output, and bits in the
2695 * conf byte. These tables are similar to the TMDS tables, consisting
2696 * of a list of pxclks and script pointers.
2699 NVPtr pNv = NVPTR(pScrn);
2700 bios_t *bios = &pNv->VBIOS;
2701 unsigned int fpstrapping, outputset = (pNv->dcb_table.entry[dcb_entry].or == 4) ? 1 : 0;
2702 uint16_t scriptptr = 0, clktable;
2703 uint8_t clktableptr = 0;
2705 fpstrapping = (nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
2707 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
2708 run_lvds_table(pScrn, head, dcb_entry, LVDS_RESET, pxclk);
2709 /* no sign of the "panel off for reset" bit, but it's safer to assume we should */
2710 if (script == LVDS_RESET)
2711 run_lvds_table(pScrn, head, dcb_entry, LVDS_PANEL_OFF, pxclk);
2713 /* for now we assume version 3.0 table - g80 support will need some changes */
2718 case LVDS_BACKLIGHT_ON: // check applicability of the script for this
2720 scriptptr = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
2722 case LVDS_BACKLIGHT_OFF: // check applicability of the script for this
2723 case LVDS_PANEL_OFF:
2724 scriptptr = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
2727 if (pNv->dcb_table.entry[dcb_entry].lvdsconf.use_straps_for_mode ||
2728 (fpstrapping != 0x0f && bios->data[bios->fp.xlated_entry + 1] != 0x0f)) {
2729 if (bios->fp.dual_link)
2731 if (bios->fp.BITbit1)
2734 uint8_t fallback = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
2735 int fallbackcmpval = (pNv->dcb_table.entry[dcb_entry].or == 4) ? 4 : 1;
2737 if (pxclk >= bios->fp.duallink_transition_clk) {
2739 fallbackcmpval *= 2;
2741 if (fallbackcmpval & fallback)
2745 /* adding outputset * 8 may not be correct */
2746 clktable = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 15 + clktableptr * 2 + outputset * 8]);
2748 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Pixel clock comparison table not found\n");
2751 scriptptr = clkcmptable(bios, clktable, pxclk);
2755 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "LVDS output init script not found\n");
2758 rundigitaloutscript(pScrn, scriptptr, head, dcb_entry);
2761 void call_lvds_script(ScrnInfoPtr pScrn, int head, int dcb_entry, enum LVDS_script script, int pxclk)
2763 /* LVDS operations are multiplexed in an effort to present a single API
2764 * which works with two vastly differing underlying structures.
2765 * This acts as the demux
2768 bios_t *bios = &NVPTR(pScrn)->VBIOS;
2769 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
2774 if (lvds_ver < 0x30)
2775 call_lvds_manufacturer_script(pScrn, head, dcb_entry, script);
2777 run_lvds_table(pScrn, head, dcb_entry, script, pxclk);
2781 uint16_t fptablepointer;
2782 uint16_t fpxlatetableptr;
2783 uint16_t fpxlatemanufacturertableptr;
2787 static void parse_fp_mode_table(ScrnInfoPtr pScrn, bios_t *bios, struct fppointers *fpp)
2789 unsigned int fpstrapping;
2791 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
2793 DisplayModePtr mode;
2795 fpstrapping = (nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
2797 if (fpp->fptablepointer == 0x0 || fpp->fpxlatetableptr == 0x0) {
2798 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2799 "Pointers to flat panel table invalid\n");
2803 fptable = &bios->data[fpp->fptablepointer];
2805 fptable_ver = fptable[0];
2807 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2808 "Found flat panel mode table revision %d.%d\n",
2809 fptable_ver >> 4, fptable_ver & 0xf);
2811 switch (fptable_ver) {
2812 /* BMP version 0x5.0x11 BIOSen have version 1 like tables, but no version field,
2813 * and miss one of the spread spectrum/PWM bytes.
2814 * This could affect early GF2Go parts (not seen any appropriate ROMs though).
2815 * Here we assume that a version of 0x05 matches this case (combining with a
2816 * BMP version check would be better), as the common case for the panel type
2817 * field is 0x0005, and that is in fact what we are reading the first byte of. */
2818 case 0x05: /* some NV10, 11, 15, 16 */
2822 case 0x10: /* some NV15/16, and NV11+ */
2826 case 0x20: /* NV40+ */
2827 headerlen = fptable[1];
2828 recordlen = fptable[2];
2829 fpentries = fptable[3];
2830 /* fptable[4] is the minimum RAMDAC_FP_HCRTC->RAMDAC_FP_HSYNC_START gap.
2831 * Only seen 0x4b (=75) which is what is used in nv_crtc.c anyway,
2832 * so we're not using this table value for now
2837 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2838 "FP Table revision not currently supported\n");
2842 fpindex = bios->data[fpp->fpxlatetableptr + fpstrapping * fpp->xlatwidth];
2843 if (fpindex > fpentries) {
2844 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2845 "Bad flat panel table index\n");
2849 /* reserved values - means that ddc or hard coded edid should be used */
2850 if (fpindex == 0xf && fpstrapping == 0xf) {
2851 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Ignoring FP table\n");
2855 if (!(mode = xcalloc(1, sizeof(DisplayModeRec))))
2858 int modeofs = headerlen + recordlen * fpindex + ofs;
2859 mode->Clock = le16_to_cpu(*(uint16_t *)&fptable[modeofs]) * 10;
2860 mode->HDisplay = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 2]);
2861 mode->HSyncStart = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 10] + 1);
2862 mode->HSyncEnd = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 12] + 1);
2863 mode->HTotal = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 14] + 1);
2864 mode->VDisplay = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 16]);
2865 mode->VSyncStart = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 24] + 1);
2866 mode->VSyncEnd = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 26] + 1);
2867 mode->VTotal = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 28] + 1);
2868 mode->Flags |= (fptable[modeofs + 30] & 0x10) ? V_PHSYNC : V_NHSYNC;
2869 mode->Flags |= (fptable[modeofs + 30] & 0x1) ? V_PVSYNC : V_NVSYNC;
2872 * bytes 1-2 are "panel type", including bits on whether Colour/mono, single/dual link, and type (TFT etc.)
2873 * bytes 3-6 are bits per colour in RGBX
2875 * 13-14 is HValid Start
2876 * 15-16 is HValid End
2877 * bytes 38-39 relate to spread spectrum settings
2878 * bytes 40-43 are something to do with PWM */
2880 mode->prev = mode->next = NULL;
2881 mode->status = MODE_OK;
2882 mode->type = M_T_DRIVER | M_T_PREFERRED;
2883 xf86SetModeDefaultName(mode);
2885 // if (XF86_CRTC_CONFIG_PTR(pScrn)->debug_modes) {
2886 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2887 "Found flat panel mode in BIOS tables:\n");
2888 xf86PrintModeline(pScrn->scrnIndex, mode);
2891 bios->fp.native_mode = mode;
2894 static void parse_lvds_manufacturer_table_init(ScrnInfoPtr pScrn, bios_t *bios, struct fppointers *fpp)
2896 /* The LVDS table changed considerably with BIT bioses. Previously
2897 * there was a header of version and record length, followed by several
2898 * records, indexed by a seperate xlat table, indexed in turn by the fp
2899 * strap in EXTDEV_BOOT. Each record had a config byte, followed by 6
2900 * script numbers for use by INIT_SUB which controlled panel init and
2901 * power, and finally a dword of ms to sleep between power off and on
2904 * The BIT LVDS table has the typical BIT table header: version byte,
2905 * header length byte, record length byte, and a byte for the maximum
2906 * number of records that can be held in the table. At byte 5 in the
2907 * header is the dual-link transition pxclk (in 10s kHz) - if straps
2908 * are not being used for the panel, this specifies the frequency at
2909 * which modes should be set up in the dual link style.
2911 * The table following the header serves as an integrated config and
2912 * xlat table: the records in the table are indexed by the FP strap
2913 * nibble in EXTDEV_BOOT, and each record has two bytes - the first as
2914 * a config byte, the second for indexing the fp mode table pointed to
2915 * by the BIT 'D' table
2918 unsigned int fpstrapping, lvdsmanufacturerindex = 0;
2919 uint8_t lvds_ver, headerlen, recordlen;
2921 fpstrapping = (nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
2923 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
2924 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2925 "Pointer to LVDS manufacturer table invalid\n");
2929 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
2931 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2932 "Found LVDS manufacturer table revision %d.%d\n",
2933 lvds_ver >> 4, lvds_ver & 0xf);
2936 case 0x0a: /* pre NV40 */
2937 lvdsmanufacturerindex = bios->data[fpp->fpxlatemanufacturertableptr + fpstrapping];
2940 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
2943 case 0x30: /* NV4x */
2944 lvdsmanufacturerindex = fpstrapping;
2945 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
2946 if (headerlen < 0x1f) {
2947 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2948 "LVDS table header not understood\n");
2951 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
2953 case 0x40: /* It changed again with gf8 :o( */
2955 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2956 "LVDS table revision not currently supported\n");
2960 uint16_t lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + headerlen + recordlen * lvdsmanufacturerindex;
2963 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
2964 bios->fp.dual_link = bios->data[lvdsofs] & 4;
2965 bios->fp.if_is_18bit = !(bios->data[lvdsofs] & 16);
2968 /* no sign of the "reset for panel on" bit, but it's safer to assume we should */
2969 bios->fp.reset_after_pclk_change = TRUE;
2970 bios->fp.dual_link = bios->data[lvdsofs] & 1;
2971 bios->fp.BITbit1 = bios->data[lvdsofs] & 2;
2972 /* BMP likely has something like this, but I have no dump to point to where it is */
2973 bios->fp.duallink_transition_clk = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
2974 fpp->fpxlatetableptr = bios->fp.lvdsmanufacturerpointer + headerlen + 1;
2975 fpp->xlatwidth = recordlen;
2980 void run_tmds_table(ScrnInfoPtr pScrn, int dcb_entry, int head, int pxclk)
2982 /* the dcb_entry parameter is the index of the appropriate DCB entry
2983 * the pxclk parameter is in kHz
2985 * This runs the TMDS regs setting code found on BIT bios cards
2987 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
2988 * ffs(or) == 3, use the second.
2991 NVPtr pNv = NVPTR(pScrn);
2992 bios_t *bios = &pNv->VBIOS;
2993 uint16_t clktable = 0, scriptptr;
2995 if (pNv->dcb_table.entry[dcb_entry].location) /* off chip */
2998 switch (ffs(pNv->dcb_table.entry[dcb_entry].or)) {
3000 clktable = bios->tmds.output0_script_ptr;
3004 clktable = bios->tmds.output1_script_ptr;
3009 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Pixel clock comparison table not found\n");
3013 scriptptr = clkcmptable(bios, clktable, pxclk);
3016 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TMDS output init script not found\n");
3020 rundigitaloutscript(pScrn, scriptptr, head, dcb_entry);
3023 static void parse_bios_version(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset)
3025 /* offset + 0 (8 bits): Micro version
3026 * offset + 1 (8 bits): Minor version
3027 * offset + 2 (8 bits): Chip version
3028 * offset + 3 (8 bits): Major version
3031 bios->major_version = bios->data[offset + 3];
3032 bios->chip_version = bios->data[offset + 2];
3033 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Bios version %02x.%02x.%02x.%02x\n",
3034 bios->data[offset + 3], bios->data[offset + 2],
3035 bios->data[offset + 1], bios->data[offset]);
3038 //int getMNP_double_plltype(ScrnInfoPtr pScrn, enum pll_types plltype, int clk, int *NM1, int *NM2, int *log2P)
3039 int get_pll_limits_plltype(ScrnInfoPtr pScrn, enum pll_types plltype, struct pll_lims *pll_lim)
3042 * Here we just try to find a register matching plltype in the PLL
3043 * limits table. The table is better explained in get_pll_limits below.
3046 bios_t *bios = &NVPTR(pScrn)->VBIOS;
3048 if (!bios->pll_limit_tbl_ptr) {
3049 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Pointer to PLL limits table invalid\n");
3053 switch (bios->data[bios->pll_limit_tbl_ptr]) {
3055 return get_pll_limits(pScrn, 0, pll_lim);
3056 // return getMNP_double(pScrn, 0, clk, NM1, NM2, log2P);
3060 uint8_t headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
3061 uint8_t recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
3062 uint8_t entries = bios->data[bios->pll_limit_tbl_ptr + 3];
3063 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
3067 for (i = 1; i < entries; i++) {
3068 uint32_t cmpreg = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + recordlen * i])));
3070 if (plltype == VPLL1 && (cmpreg == 0x680508 || cmpreg == 0x4010)) {
3074 if (plltype == VPLL2 && (cmpreg == 0x680520 || cmpreg == 0x4018)) {
3080 return get_pll_limits(pScrn, reg, pll_lim);
3081 // return getMNP_double(pScrn, reg, clk, NM1, NM2, log2P);
3084 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3085 "PLL limits table revision not currently supported\n");
3090 Bool get_pll_limits(ScrnInfoPtr pScrn, uint32_t reg, struct pll_lims *pll_lim)
3094 * Version 0x10: NV31
3095 * One byte header (version), one record of 24 bytes
3096 * Version 0x11: NV36 - Not implemented
3097 * Seems to have same record style as 0x10, but 3 records rather than 1
3098 * Version 0x20: Found on Geforce 6 cards
3099 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
3100 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
3101 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record length
3104 bios_t *bios = &NVPTR(pScrn)->VBIOS;
3105 uint8_t pll_lim_ver, headerlen, recordlen, entries;
3106 int pllindex = 0, i;
3108 if (!bios->pll_limit_tbl_ptr) {
3109 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Pointer to PLL limits table invalid\n");
3113 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
3115 if (DEBUGLEVEL >= 6)
3116 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3117 "Found PLL limits table version 0x%X\n", pll_lim_ver);
3119 switch (pll_lim_ver) {
3128 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
3129 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
3130 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
3133 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3134 "PLL limits table revision not currently supported\n");
3138 /* initialize all members to zero */
3139 memset (pll_lim, 0, sizeof(struct pll_lims));
3141 if (pll_lim_ver == 0x10) {
3142 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex;
3144 pll_lim->vco1.minfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs])));
3145 pll_lim->vco1.maxfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 4])));
3146 pll_lim->vco2.minfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 8])));
3147 pll_lim->vco2.maxfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 12])));
3148 pll_lim->vco1.min_inputfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 16])));
3149 pll_lim->vco2.min_inputfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 20])));
3150 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
3152 /* these values taken from nv31. nv30, nv36 might do better with different ones */
3153 pll_lim->vco1.min_n = 0x1;
3154 pll_lim->vco1.max_n = 0xff;
3155 pll_lim->vco1.min_m = 0x1;
3156 pll_lim->vco1.max_m = 0xd;
3157 pll_lim->vco2.min_n = 0x4;
3158 pll_lim->vco2.max_n = 0x46;
3159 if (bios->chip_version == 0x30)
3160 /* only 5 bits available for N2 on nv30 */
3161 pll_lim->vco2.max_n = 0x1f;
3162 if (bios->chip_version == 0x31)
3163 /* on nv31, N2 is compared to maxN2 (0x46) and maxM2 (0x4),
3164 * so set maxN2 to 0x4 and save a comparison
3166 pll_lim->vco2.max_n = 0x4;
3167 pll_lim->vco2.min_m = 0x1;
3168 pll_lim->vco2.max_m = 0x4;
3169 } else { /* ver 0x20, 0x21 */
3170 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
3172 /* first entry is default match, if nothing better. warn if reg field nonzero */
3173 if (le32_to_cpu(*((uint32_t *)&bios->data[plloffs])))
3174 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
3175 "Default PLL limit entry has non-zero register field\n");
3177 for (i = 1; i < entries; i++)
3178 if (le32_to_cpu(*((uint32_t *)&bios->data[plloffs + recordlen * i])) == reg) {
3183 plloffs += recordlen * pllindex;
3185 if (DEBUGLEVEL >= 6)
3186 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Loading PLL limits for reg 0x%08x\n",
3187 pllindex ? reg : 0);
3189 /* frequencies are stored in tables in MHz, kHz are more useful, so we convert */
3191 /* What output frequencies can each VCO generate? */
3192 pll_lim->vco1.minfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 4]))) * 1000;
3193 pll_lim->vco1.maxfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 6]))) * 1000;
3194 pll_lim->vco2.minfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 8]))) * 1000;
3195 pll_lim->vco2.maxfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 10]))) * 1000;
3197 /* What input frequencies do they accept (past the m-divider)? */
3198 pll_lim->vco1.min_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 12]))) * 1000;
3199 pll_lim->vco2.min_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 14]))) * 1000;
3200 pll_lim->vco1.max_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 16]))) * 1000;
3201 pll_lim->vco2.max_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 18]))) * 1000;
3203 /* What values are accepted as multiplier and divider? */
3204 pll_lim->vco1.min_n = bios->data[plloffs + 20];
3205 pll_lim->vco1.max_n = bios->data[plloffs + 21];
3206 pll_lim->vco1.min_m = bios->data[plloffs + 22];
3207 pll_lim->vco1.max_m = bios->data[plloffs + 23];
3208 pll_lim->vco2.min_n = bios->data[plloffs + 24];
3209 pll_lim->vco2.max_n = bios->data[plloffs + 25];
3210 pll_lim->vco2.min_m = bios->data[plloffs + 26];
3211 pll_lim->vco2.max_m = bios->data[plloffs + 27];
3213 pll_lim->min_p = bios->data[plloffs + 28];
3214 pll_lim->max_p = bios->data[plloffs + 29];
3215 pll_lim->p_bias = bios->data[plloffs + 30];
3217 if (recordlen > 0x22)
3218 pll_lim->refclk = le32_to_cpu(*((uint32_t *)&bios->data[plloffs + 31]));
3221 #if 1 /* for easy debugging */
3222 ErrorF("pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
3223 ErrorF("pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
3224 ErrorF("pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
3225 ErrorF("pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
3227 ErrorF("pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
3228 ErrorF("pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
3229 ErrorF("pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
3230 ErrorF("pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
3232 ErrorF("pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
3233 ErrorF("pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
3234 ErrorF("pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
3235 ErrorF("pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
3236 ErrorF("pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
3237 ErrorF("pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
3238 ErrorF("pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
3239 ErrorF("pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
3241 ErrorF("pll.min_p: %d\n", pll_lim->min_p);
3242 ErrorF("pll.max_p: %d\n", pll_lim->max_p);
3243 ErrorF("pll.p_bias: %d\n", pll_lim->p_bias);
3245 ErrorF("pll.refclk: %d\n", pll_lim->refclk);
3251 static int parse_bit_B_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3253 /* offset + 0 (32 bits): BIOS version dword
3255 * There's a bunch of bits in this table other than the bios version
3256 * that we don't use - their use currently unknown
3259 if (bitentry->length < 0x4) {
3260 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3261 "Do not understand B table entry\n");
3265 parse_bios_version(pScrn, bios, bitentry->offset);
3270 static int parse_bit_C_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3272 /* offset + 8 (16 bits): PLL limits table pointer
3274 * There's more in here, but that's unknown.
3277 if (bitentry->length < 10) {
3278 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Do not understand C table entry\n");
3282 bios->pll_limit_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 8])));
3287 static int parse_bit_display_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry, struct fppointers *fpp)
3289 /* Parses the flat panel table segment that the bit entry points to.
3290 * Starting at bitentry->offset:
3292 * offset + 0 (16 bits): FIXME table pointer
3293 * offset + 2 (16 bits): mode table pointer
3296 if (bitentry->length != 4) {
3297 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3298 "Do not understand BIT display table entry\n");
3302 fpp->fptablepointer = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 2])));
3307 static unsigned int parse_bit_init_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3309 /* Parses the init table segment that the bit entry points to.
3310 * Starting at bitentry->offset:
3312 * offset + 0 (16 bits): init script tables pointer
3313 * offset + 2 (16 bits): macro index table pointer
3314 * offset + 4 (16 bits): macro table pointer
3315 * offset + 6 (16 bits): condition table pointer
3316 * offset + 8 (16 bits): io condition table pointer
3317 * offset + 10 (16 bits): io flag condition table pointer
3318 * offset + 12 (16 bits): init function table pointer
3322 if (bitentry->length < 14) {
3323 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3324 "Unable to recognize BIT init table entry\n");
3328 bios->init_script_tbls_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
3329 bios->macro_index_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 2])));
3330 bios->macro_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 4])));
3331 bios->condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 6])));
3332 bios->io_condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 8])));
3333 bios->io_flag_condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 10])));
3334 bios->init_function_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 12])));
3339 static int parse_bit_i_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3341 /* offset + 13 (16 bits): pointer to table containing DAC load detection comparison values
3343 * There's other things in this table, purpose unknown
3348 if (bitentry->length < 15) {
3349 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3350 "BIT i table not long enough for DAC load detection comparison table\n");
3354 offset = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 13])));
3356 /* doesn't exist on g80 */
3360 /* The first value in the table, following the header, is the comparison value
3361 * Purpose of subsequent values unknown - TV load detection?
3364 uint8_t version = bios->data[offset];
3366 if (version != 0x00 && version != 0x10) {
3367 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
3368 "DAC load detection comparison table version %d.%d not known\n",
3369 version >> 4, version & 0xf);
3373 uint8_t headerlen = bios->data[offset + 1];
3375 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3376 "DAC load detection comparison table version %x found\n", version);
3378 bios->dactestval = le32_to_cpu(*((uint32_t *)(&bios->data[offset + headerlen])));
3383 static int parse_bit_lvds_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry, struct fppointers *fpp)
3385 /* Parses the LVDS table segment that the bit entry points to.
3386 * Starting at bitentry->offset:
3388 * offset + 0 (16 bits): LVDS strap xlate table pointer
3391 if (bitentry->length != 2) {
3392 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3393 "Do not understand BIT LVDS table entry\n");
3397 /* no idea if it's still called the LVDS manufacturer table, but the concept's close enough */
3398 bios->fp.lvdsmanufacturerpointer = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
3400 parse_lvds_manufacturer_table_init(pScrn, bios, fpp);
3405 static int parse_bit_M_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3407 /* offset + 2 (8 bits): number of options in an INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
3408 * offset + 3 (16 bits): pointer to strap xlate table for RAM restrict option selection
3410 * There's a bunch of bits in this table other than the RAM restrict
3411 * stuff that we don't use - their use currently unknown
3416 /* Older bios versions don't have a sufficiently long table for what we want */
3417 if (bitentry->length < 0x5)
3420 /* set up multiplier for INIT_RAM_RESTRICT_ZM_REG_GROUP */
3421 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != 0x8f); i++)
3423 itbl_entry[i].length_multiplier = bios->data[bitentry->offset + 2] * 4;
3424 init_ram_restrict_zm_reg_group_blocklen = itbl_entry[i].length_multiplier;
3426 bios->ram_restrict_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 3])));
3431 static int parse_bit_tmds_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3433 /* Parses the pointer to the TMDS table
3435 * Starting at bitentry->offset:
3437 * offset + 0 (16 bits): TMDS table pointer
3439 * The TMDS table is typically found just before the DCB table, with a
3440 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
3443 * At offset +7 is a pointer to a script, which I don't know how to run yet
3444 * At offset +9 is a pointer to another script, likewise
3445 * Offset +11 has a pointer to a table where the first word is a pxclk
3446 * frequency and the second word a pointer to a script, which should be
3447 * run if the comparison pxclk frequency is less than the pxclk desired.
3448 * This repeats for decreasing comparison frequencies
3449 * Offset +13 has a pointer to a similar table
3450 * The selection of table (and possibly +7/+9 script) is dictated by
3451 * "or" from the DCB.
3454 uint16_t tmdstableptr, script1, script2;
3456 if (bitentry->length != 2) {
3457 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3458 "Do not understand BIT TMDS table entry\n");
3462 tmdstableptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
3464 if (tmdstableptr == 0x0) {
3465 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Pointer to TMDS table invalid\n");
3469 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Found TMDS table revision %d.%d\n",
3470 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
3472 /* These two scripts are odd: they don't seem to get run even when they are not stubbed */
3473 script1 = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 7]));
3474 script2 = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 9]));
3475 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
3476 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TMDS table script pointers not stubbed\n");
3478 bios->tmds.output0_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 11]));
3479 bios->tmds.output1_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 13]));
3484 static void parse_bit_structure(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset)
3486 bit_entry_t bitentry;
3488 struct fppointers fpp;
3489 NVPtr pNv = NVPTR(pScrn);
3491 memset(&fpp, 0, sizeof(struct fppointers));
3494 bitentry.id[0] = bios->data[offset];
3495 bitentry.id[1] = bios->data[offset + 1];
3496 bitentry.length = le16_to_cpu(*((uint16_t *)&bios->data[offset + 2]));
3497 bitentry.offset = le16_to_cpu(*((uint16_t *)&bios->data[offset + 4]));
3499 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3500 "0x%04X: Found BIT command with id 0x%02X (%c)\n",
3501 offset, bitentry.id[0], bitentry.id[0]);
3503 switch (bitentry.id[0]) {
3505 /* id[0] = 0 and id[1] = 0 ==> end of BIT struture */
3506 if (bitentry.id[1] == 0)
3510 parse_bit_B_tbl_entry(pScrn, bios, &bitentry);
3513 parse_bit_C_tbl_entry(pScrn, bios, &bitentry);
3516 parse_bit_display_tbl_entry(pScrn, bios, &bitentry, &fpp);
3519 parse_bit_init_tbl_entry(pScrn, bios, &bitentry);
3522 parse_bit_i_tbl_entry(pScrn, bios, &bitentry);
3525 parse_bit_lvds_tbl_entry(pScrn, bios, &bitentry, &fpp);
3527 case 'M': /* memory? */
3528 parse_bit_M_tbl_entry(pScrn, bios, &bitentry);
3531 parse_bit_tmds_tbl_entry(pScrn, bios, &bitentry);
3535 offset += sizeof(bit_entry_t);
3538 /* C and M tables have to be parsed before init can run */
3539 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3540 "Parsing previously deferred init table entry\n");
3541 parse_init_tables(pScrn, bios);
3543 /* If it's not a laptop, you probably don't care about LVDS */
3544 /* FIXME: detect mobile BIOS? */
3548 /* Need D and L tables parsed before doing this */
3549 parse_fp_mode_table(pScrn, bios, &fpp);
3552 static void parse_bmp_structure(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset)
3554 /* Parse the BMP structure for useful things
3556 * offset + 5: BMP major version
3557 * offset + 6: BMP minor version
3558 * offset + 10: BCD encoded BIOS version
3560 * offset + 18: init script table pointer (for bios versions < 5.10h)
3561 * offset + 20: extra init script table pointer (for bios versions < 5.10h)
3563 * offset + 24: FIXME
3564 * offset + 26: FIXME
3565 * offset + 28: FIXME
3567 * offset + 54: index of I2C CRTC pair to use for CRT output
3568 * offset + 55: index of I2C CRTC pair to use for TV output
3569 * offset + 56: index of I2C CRTC pair to use for flat panel output
3570 * offset + 58: write CRTC index for I2C pair 0
3571 * offset + 59: read CRTC index for I2C pair 0
3572 * offset + 60: write CRTC index for I2C pair 1
3573 * offset + 61: read CRTC index for I2C pair 1
3575 * offset + 67: maximum internal PLL frequency (single stage PLL)
3576 * offset + 71: minimum internal PLL frequency (single stage PLL)
3578 * offset + 75: script table pointers, as for parse_bit_init_tbl_entry
3580 * offset + 89: TMDS single link output A table pointer
3581 * offset + 91: TMDS single link output B table pointer
3582 * offset + 105: flat panel timings table pointer
3583 * offset + 107: flat panel strapping translation table pointer
3584 * offset + 117: LVDS manufacturer panel config table pointer
3585 * offset + 119: LVDS manufacturer strapping translation table pointer
3587 * offset + 142: PLL limits table pointer
3590 NVPtr pNv = NVPTR(pScrn);
3592 struct fppointers fpp;
3593 memset(&fpp, 0, sizeof(struct fppointers));
3595 uint8_t bmp_version_major = bios->data[offset + 5];
3596 uint8_t bmp_version_minor = bios->data[offset + 6];
3598 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BMP version %d.%d\n",
3599 bmp_version_major, bmp_version_minor);
3601 /* version 6 could theoretically exist, but I suspect BIT happened instead */
3602 if (bmp_version_major < 2 || bmp_version_major > 5) {
3603 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "You have an unsupported BMP version. Please send in your bios\n");
3607 if (bmp_version_major == 2)
3608 bmplength = 48; /* exact for 2.01 - not sure if minor version used in versions < 5 */
3609 else if (bmp_version_major == 3)
3610 bmplength = 54; /* guessed - mem init tables added in this version */
3611 else if (bmp_version_major == 4 || bmp_version_minor < 0x1) /* don't know if 5.0 exists... */
3612 bmplength = 62; /* guessed - BMP I2C indices added in version 4*/
3613 else if (bmp_version_minor < 0x6)
3614 bmplength = 67; /* exact for 5.01 */
3615 else if (bmp_version_minor < 0x10)
3616 bmplength = 75; /* exact for 5.06 */
3617 else if (bmp_version_minor == 0x10)
3618 bmplength = 89; /* exact for 5.10h */
3619 else if (bmp_version_minor < 0x14)
3620 bmplength = 118; /* exact for 5.11h */
3621 else if (bmp_version_minor < 0x24) /* not sure of version where pll limits came in;
3622 * certainly exist by 0x24 though */
3623 /* length not exact: this is long enough to get lvds members */
3626 /* length not exact: this is long enough to get pll limit member */
3630 if (nv_cksum(bios->data + offset, 8)) {
3631 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Bad BMP checksum\n");
3635 parse_bios_version(pScrn, bios, offset + 10);
3637 bios->init_script_tbls_ptr = le16_to_cpu(*(uint16_t *)&bios->data[offset + 18]);
3638 bios->extra_init_script_tbl_ptr = le16_to_cpu(*(uint16_t *)&bios->data[offset + 20]);
3641 // FIXME needed for pre v16? - haiku uses this in its COMPUTE_MEM on early biosen
3642 if (bmp_version_major > 2) {
3643 uint16_t meminittbl = le16_to_cpu(*(uint16_t *)&bios->data[offset + 24]);
3644 uint16_t sdrmemseqtbl = le16_to_cpu(*(uint16_t *)&bios->data[offset + 26]);
3645 uint16_t ddrmemseqtbl = le16_to_cpu(*(uint16_t *)&bios->data[offset + 28]);
3649 uint16_t legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
3651 legacy_i2c_offset = offset + 54;
3652 bios->legacy_i2c_indices.crt = bios->data[legacy_i2c_offset];
3653 bios->legacy_i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
3654 bios->legacy_i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
3655 pNv->dcb_table.i2c_write[0] = bios->data[legacy_i2c_offset + 4];
3656 pNv->dcb_table.i2c_read[0] = bios->data[legacy_i2c_offset + 5];
3657 pNv->dcb_table.i2c_write[1] = bios->data[legacy_i2c_offset + 6];
3658 pNv->dcb_table.i2c_read[1] = bios->data[legacy_i2c_offset + 7];
3660 if (bmplength > 74) {
3661 bios->fmaxvco = le32_to_cpu(*((uint32_t *)&bios->data[offset + 67]));
3662 bios->fminvco = le32_to_cpu(*((uint32_t *)&bios->data[offset + 71]));
3664 if (bmplength > 88) {
3665 bit_entry_t initbitentry;
3666 initbitentry.length = 14;
3667 initbitentry.offset = offset + 75;
3668 parse_bit_init_tbl_entry(pScrn, bios, &initbitentry);
3670 if (bmplength > 92) {
3671 bios->tmds.output0_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[offset + 89]));
3672 bios->tmds.output1_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[offset + 91]));
3674 if (bmplength > 108) {
3675 fpp.fptablepointer = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 105])));
3676 fpp.fpxlatetableptr = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 107])));
3679 if (bmplength > 120) {
3680 bios->fp.lvdsmanufacturerpointer = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 117])));
3681 fpp.fpxlatemanufacturertableptr = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 119])));
3683 if (bmplength > 143)
3684 bios->pll_limit_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 142])));
3686 /* want pll_limit_tbl_ptr set (if available) before init is run */
3687 if (bmp_version_major < 5 || bmp_version_minor < 0x10) {
3688 init_exec_t iexec = {TRUE, FALSE};
3689 parse_init_table(pScrn, bios, bios->init_script_tbls_ptr, &iexec);
3690 parse_init_table(pScrn, bios, bios->extra_init_script_tbl_ptr, &iexec);
3692 parse_init_tables(pScrn, bios);
3694 /* If it's not a laptop, you probably don't care about fptables */
3695 /* FIXME: detect mobile BIOS? */
3699 parse_fp_mode_table(pScrn, bios, &fpp);
3700 parse_lvds_manufacturer_table_init(pScrn, bios, &fpp);
3701 /* I've never seen a valid LVDS_INIT script, so we'll do a test for it here */
3702 call_lvds_script(pScrn, 0, 0, LVDS_INIT, 0);
3705 static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
3709 for (i = 0; i <= (n - len); i++) {
3710 for (j = 0; j < len; j++)
3711 if (data[i + j] != str[j])
3720 static Bool parse_dcb_entry(ScrnInfoPtr pScrn, uint8_t dcb_version, uint32_t conn, uint32_t conf, struct dcb_entry *entry)
3722 NVPtr pNv = NVPTR(pScrn);
3724 memset(entry, 0, sizeof (struct dcb_entry));
3726 /* safe defaults for a crt */
3728 entry->i2c_index = 0;
3731 entry->location = 0;
3733 entry->duallink_possible = FALSE;
3735 if (dcb_version >= 0x20) {
3736 entry->type = conn & 0xf;
3737 entry->i2c_index = (conn >> 4) & 0xf;
3738 entry->heads = (conn >> 8) & 0xf;
3739 entry->bus = (conn >> 16) & 0xf;
3740 entry->location = (conn >> 20) & 0xf;
3741 entry->or = (conn >> 24) & 0xf;
3742 /* Normal entries consist of a single bit, but dual link has the
3743 * adjacent more significant bit set too
3745 if ((1 << (ffs(entry->or) - 1)) * 3 == entry->or)
3746 entry->duallink_possible = TRUE;
3748 switch (entry->type) {
3750 if (conf & 0xfffffffa)
3751 ErrorF("Unknown LVDS configuration bits, please report\n");
3753 entry->lvdsconf.use_straps_for_mode = TRUE;
3755 entry->lvdsconf.use_power_scripts = TRUE;
3758 } else if (dcb_version >= 0x14 ) {
3759 if (conn != 0xf0003f00 && conn != 0xf2204301 && conn != 0xf2045f14 && conn != 0xf2205004 && conn != 0xf4204011) {
3760 ErrorF("Unknown DCB 1.4 / 1.5 entry, please report\n");
3761 /* cause output setting to fail, so message is seen */
3762 pNv->dcb_table.entries = 0;
3765 /* most of the below is a "best guess" atm */
3766 entry->type = conn & 0xf;
3767 if (entry->type == 4) { /* digital */
3769 entry->type = OUTPUT_LVDS;
3771 /* FIXME: do we need to add a DVI-A analogue output in this case,
3772 * assuming this connector is DVI-I, not pure DVI-D?
3774 entry->type = OUTPUT_TMDS;
3776 /* what's in bits 5-13? could be some brooktree/chrontel/philips thing, in tv case */
3777 entry->i2c_index = (conn >> 14) & 0xf;
3778 /* raw heads field is in range 0-1, so move to 1-2 */
3779 entry->heads = ((conn >> 18) & 0x7) + 1;
3780 entry->location = (conn >> 21) & 0xf;
3781 entry->bus = (conn >> 25) & 0x7;
3782 /* set or to be same as heads -- hopefully safe enough */
3783 entry->or = entry->heads;
3785 switch (entry->type) {
3787 /* these are probably buried in conn's unknown bits */
3788 entry->lvdsconf.use_straps_for_mode = TRUE;
3789 entry->lvdsconf.use_power_scripts = TRUE;
3792 } else if (dcb_version >= 0x12) {
3793 /* use the defaults for a crt
3794 * v1.2 tables often have other entries though - need a trace
3796 entry->type = conn & 0xf; // this is valid, but will probably confuse the randr stuff
3798 } else { /* pre DCB / v1.1 - use the safe defaults for a crt */
3799 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3800 "No information in BIOS output table; assuming a CRT output exists\n");
3801 entry->i2c_index = pNv->VBIOS.legacy_i2c_indices.crt;
3804 pNv->dcb_table.entries++;
3810 read_dcb_i2c_table(ScrnInfoPtr pScrn, bios_t *bios, uint8_t dcb_version, uint16_t i2ctabptr)
3812 NVPtr pNv = NVPTR(pScrn);
3814 uint8_t headerlen = 0;
3816 int recordoffset = 0, rdofs = 1, wrofs = 0;
3819 i2c_entries = MAX_NUM_DCB_ENTRIES;
3820 memset(pNv->dcb_table.i2c_read, 0, sizeof(pNv->dcb_table.i2c_read));
3821 memset(pNv->dcb_table.i2c_write, 0, sizeof(pNv->dcb_table.i2c_write));
3823 i2ctable = &bios->data[i2ctabptr];
3825 if (dcb_version >= 0x30) {
3826 if (i2ctable[0] != dcb_version) { /* necessary? */
3827 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3828 "DCB I2C table version mismatch (%02X vs %02X)\n",
3829 i2ctable[0], dcb_version);
3832 headerlen = i2ctable[1];
3833 i2c_entries = i2ctable[2];
3834 if (i2ctable[0] >= 0x40) {
3835 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3836 "G80 DCB I2C table detected, arrgh\n"); /* they're plain weird */
3840 /* it's your own fault if you call this function on a DCB 1.1 BIOS --
3841 * the below assumes DCB 1.2
3843 if (dcb_version < 0x14) {
3849 for (i = 0; i < i2c_entries; i++)
3850 if (i2ctable[headerlen + 4 * i + 3] != 0xff) {
3851 pNv->dcb_table.i2c_read[i] = i2ctable[headerlen + recordoffset + rdofs + 4 * i];
3852 pNv->dcb_table.i2c_write[i] = i2ctable[headerlen + recordoffset + wrofs + 4 * i];
3856 static unsigned int parse_dcb_table(ScrnInfoPtr pScrn, bios_t *bios)
3858 NVPtr pNv = NVPTR(pScrn);
3859 uint16_t dcbptr, i2ctabptr = 0;
3861 uint8_t dcb_version, headerlen = 0x4, entries = MAX_NUM_DCB_ENTRIES;
3862 Bool configblock = TRUE;
3863 int recordlength = 8, confofs = 4;
3866 pNv->dcb_table.entries = 0;
3868 /* get the offset from 0x36 */
3869 dcbptr = le16_to_cpu(*(uint16_t *)&bios->data[0x36]);
3871 if (dcbptr == 0x0) {
3872 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3873 "No Display Configuration Block pointer found\n");
3874 /* this situation likely means a really old card, pre DCB, so we'll add the safe CRT entry */
3875 parse_dcb_entry(pScrn, 0, 0, 0, &pNv->dcb_table.entry[0]);
3879 dcbtable = &bios->data[dcbptr];
3881 /* get DCB version */
3882 dcb_version = dcbtable[0];
3883 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3884 "Display Configuration Block version %d.%d found\n",
3885 dcb_version >> 4, dcb_version & 0xf);
3887 if (dcb_version >= 0x20) { /* NV17+ */
3890 if (dcb_version >= 0x30) { /* NV40+ */
3891 headerlen = dcbtable[1];
3892 entries = dcbtable[2];
3893 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[4]);
3894 sig = le32_to_cpu(*(uint32_t *)&dcbtable[6]);
3896 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3897 "DCB header length %02X, with %02X possible entries\n",
3898 headerlen, entries);
3900 /* dcb_block_count = *(dcbtable[1]); */
3901 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
3902 sig = le32_to_cpu(*(uint32_t *)&dcbtable[4]);
3906 if (sig != 0x4edcbdcb) {
3907 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3908 "Bad Display Configuration Block signature (%08X)\n", sig);
3911 } else if (dcb_version >= 0x14) { /* some NV15/16, and NV11+ */
3915 strncpy(sig, (char *)&dcbtable[-7], 7);
3916 /* dcb_block_count = *(dcbtable[1]); */
3917 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
3921 if (strcmp(sig, "DEV_REC")) {
3922 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3923 "Bad Display Configuration Block signature (%s)\n", sig);
3926 } else if (dcb_version >= 0x12) { /* some NV6/10, and NV15+ */
3927 /* dcb_block_count = *(dcbtable[1]); */
3928 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
3929 configblock = FALSE;
3930 } else { /* NV5+, maybe NV4 */
3931 /* DCB 1.1 seems to be quite unhelpful - we'll just add the safe CRT entry */
3932 parse_dcb_entry(pScrn, dcb_version, 0, 0, &pNv->dcb_table.entry[0]);
3936 if (entries >= MAX_NUM_DCB_ENTRIES)
3937 entries = MAX_NUM_DCB_ENTRIES;
3939 for (i = 0; i < entries; i++) {
3940 uint32_t connection, config = 0;
3942 connection = le32_to_cpu(*(uint32_t *)&dcbtable[headerlen + recordlength * i]);
3944 config = le32_to_cpu(*(uint32_t *)&dcbtable[headerlen + confofs + recordlength * i]);
3946 /* Should we allow discontinuous DCBs? Certainly DCB I2C tables
3947 * can be discontinuous */
3948 if ((connection & 0x0000000f) == 0x0000000f) /* end of records */
3951 ErrorF("Raw DCB entry %d: %08x %08x\n", i, connection, config);
3952 if (!parse_dcb_entry(pScrn, dcb_version, connection, config, &pNv->dcb_table.entry[i]))
3956 read_dcb_i2c_table(pScrn, bios, dcb_version, i2ctabptr);
3958 /* DCB v2.0, in particular, lists each output combination separately.
3959 * Here we merge compatible entries to have fewer outputs, with more options
3961 for (i = 0; i < pNv->dcb_table.entries; i++) {
3962 struct dcb_entry *ient = &pNv->dcb_table.entry[i];
3965 for (j = i + 1; j < pNv->dcb_table.entries; j++) {
3966 struct dcb_entry *jent = &pNv->dcb_table.entry[j];
3968 if (jent->type == 100) /* already merged entry */
3971 if (jent->i2c_index == ient->i2c_index && jent->type == ient->type && jent->location == ient->location) {
3972 /* only merge heads field when output field is the same --
3973 * we could merge output field for same heads, but dual link,
3974 * the resultant need to make several merging passes, and lack
3975 * of applicable real life cases has deterred this so far
3977 if (jent->or == ient->or) {
3978 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3979 "Merging DCB entries %d and %d\n", i, j);
3980 ient->heads |= jent->heads;
3981 jent->type = 100; /* dummy value */
3987 /* Compact entries merged into others out of dcb_table */
3989 for (i = 0; i < pNv->dcb_table.entries; i++) {
3990 if ( pNv->dcb_table.entry[i].type == 100 )
3993 if (newentries != i)
3994 memcpy(&pNv->dcb_table.entry[newentries], &pNv->dcb_table.entry[i], sizeof(struct dcb_entry));
3998 pNv->dcb_table.entries = newentries;
4000 return pNv->dcb_table.entries;
4003 static void load_nv17_hw_sequencer_ucode(ScrnInfoPtr pScrn, bios_t *bios, uint16_t hwsq_offset, int entry)
4005 /* BMP based cards, from NV17, need a microcode loading to correctly
4006 * control the GPIO etc for LVDS panels
4008 * BIT based cards seem to do this directly in the init scripts
4010 * The microcode entries are found by the "HWSQ" signature.
4011 * The header following has the number of entries, and the entry size
4013 * An entry consists of a dword to write to the sequencer control reg
4014 * (0x00001304), followed by the ucode bytes, written sequentially,
4015 * starting at reg 0x00001400
4018 uint8_t bytes_to_write;
4021 if (bios->data[hwsq_offset] <= entry) {
4022 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
4023 "Too few entries in HW sequencer table for requested entry\n");
4027 bytes_to_write = bios->data[hwsq_offset + 1];
4029 if (bytes_to_write != 36) {
4030 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown HW sequencer entry size\n");
4034 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Loading NV17 power sequencing microcode\n");
4036 uint16_t hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
4038 /* set sequencer control */
4039 nv32_wr(pScrn, 0x00001304, le32_to_cpu(*(uint32_t *)&bios->data[hwsq_entry_offset]));
4040 bytes_to_write -= 4;
4043 for (i = 0; i < bytes_to_write; i += 4)
4044 nv32_wr(pScrn, 0x00001400 + i, le32_to_cpu(*(uint32_t *)&bios->data[hwsq_entry_offset + i + 4]));
4046 /* twiddle 0x1098 */
4047 nv32_wr(pScrn, 0x00001098, nv32_rd(pScrn, 0x00001098) | 0x18);
4050 static void read_bios_edid(ScrnInfoPtr pScrn)
4052 bios_t *bios = &NVPTR(pScrn)->VBIOS;
4053 const uint8_t edid_sig[] = { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
4054 uint16_t offset = 0, newoffset;
4055 int searchlen = NV_PROM_SIZE, i;
4058 if (!(newoffset = findstr(&bios->data[offset], searchlen, edid_sig, 8)))
4060 offset += newoffset;
4061 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
4064 searchlen -= offset;
4068 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Found EDID in BIOS\n");
4070 bios->fp.edid = xalloc(EDID1_LEN);
4071 for (i = 0; i < EDID1_LEN; i++)
4072 bios->fp.edid[i] = bios->data[offset + i];
4075 Bool NVInitVBIOS(ScrnInfoPtr pScrn)
4077 NVPtr pNv = NVPTR(pScrn);
4079 memset(&pNv->VBIOS, 0, sizeof(bios_t));
4080 pNv->VBIOS.data = xalloc(NV_PROM_SIZE);
4082 if (!NVShadowVBIOS(pScrn, pNv->VBIOS.data)) {
4083 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4084 "No valid BIOS image found\n");
4085 xfree(pNv->VBIOS.data);
4089 pNv->VBIOS.length = pNv->VBIOS.data[2] * 512;
4090 if (pNv->VBIOS.length > NV_PROM_SIZE)
4091 pNv->VBIOS.length = NV_PROM_SIZE;
4096 Bool NVRunVBIOSInit(ScrnInfoPtr pScrn)
4098 NVPtr pNv = NVPTR(pScrn);
4099 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
4100 const uint8_t bit_signature[] = { 'B', 'I', 'T' };
4101 int offset, ret = 0;
4103 crtc_access(pScrn, ACCESS_UNLOCK);
4105 if ((offset = findstr(pNv->VBIOS.data, pNv->VBIOS.length, bit_signature, sizeof(bit_signature)))) {
4106 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BIT BIOS found\n");
4107 parse_bit_structure(pScrn, &pNv->VBIOS, offset + 4);
4108 } else if ((offset = findstr(pNv->VBIOS.data, pNv->VBIOS.length, bmp_signature, sizeof(bmp_signature)))) {
4109 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
4112 if ((hwsq_offset = findstr(pNv->VBIOS.data, pNv->VBIOS.length, hwsq_signature, sizeof(hwsq_signature))))
4113 /* always use entry 0? */
4114 load_nv17_hw_sequencer_ucode(pScrn, &pNv->VBIOS, hwsq_offset + sizeof(hwsq_signature), 0);
4116 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BMP BIOS found\n");
4117 parse_bmp_structure(pScrn, &pNv->VBIOS, offset);
4119 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
4120 "No known BIOS signature found\n");
4124 crtc_access(pScrn, ACCESS_LOCK);
4132 unsigned int NVParseBios(ScrnInfoPtr pScrn)
4134 NVPtr pNv = NVPTR(pScrn);
4135 uint32_t saved_nv_pextdev_boot_0;
4137 if (!NVInitVBIOS(pScrn))
4140 /* these will need remembering across a suspend */
4141 saved_nv_pextdev_boot_0 = nv32_rd(pScrn, NV_PEXTDEV_BOOT_0);
4142 saved_nv_pfb_cfg0 = nv32_rd(pScrn, NV_PFB_CFG0);
4144 pNv->VBIOS.execute = FALSE;
4146 nv32_wr(pScrn, NV_PEXTDEV_BOOT_0, saved_nv_pextdev_boot_0);
4148 if (!NVRunVBIOSInit(pScrn))
4151 if (parse_dcb_table(pScrn, &pNv->VBIOS))
4152 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
4153 "Found %d entries in DCB\n", pNv->dcb_table.entries);
4155 if (pNv->Mobile && !pNv->VBIOS.fp.native_mode)
4156 read_bios_edid(pScrn);