git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 2006 Dave Airlie
   3  * Copyright 2007 Maarten Maathuis
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
  26  * decleration is at the bottom of this file as it is rather ugly
  27  */
  28
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include <assert.h>
  34 #include "xf86.h"
  35 #include "os.h"
  36 #include "mibank.h"
  37 #include "globals.h"
  38 #include "xf86.h"
  39 #include "xf86Priv.h"
  40 #include "xf86DDC.h"
  41 #include "mipointer.h"
  42 #include "windowstr.h"
  43 #include <randrstr.h>
  44 #include <X11/extensions/render.h>
  45
  46 #include "xf86Crtc.h"
  47 #include "nv_include.h"
  48
  49 #include "vgaHW.h"
  50
  51 #define CRTC_INDEX 0x3d4
  52 #define CRTC_DATA 0x3d5
  53 #define CRTC_IN_STAT_1 0x3da
  54
  55 #define WHITE_VALUE 0x3F
  56 #define BLACK_VALUE 0x00
  57 #define OVERSCAN_VALUE 0x01
  58
  59 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  60 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override);
  61 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  62 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  63 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  64 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  65
  66 static uint8_t NVReadPVIO(xf86CrtcPtr crtc, uint32_t address)
  67 {
  68         ScrnInfoPtr pScrn = crtc->scrn;
  69         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  70         NVPtr pNv = NVPTR(pScrn);
  71
  72         /* Only NV4x have two pvio ranges */
  73         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  74                 DDXMMIOH("NVReadPVIO: head %d reg %08x val %02x\n", 1, address + NV_PVIO_OFFSET + NV_PVIO_SIZE, NV_RD08(pNv->PVIO1, address));
  75                 return NV_RD08(pNv->PVIO1, address);
  76         } else {
  77                 DDXMMIOH("NVReadPVIO: head %d reg %08x val %02x\n", 0, address + NV_PVIO_OFFSET, NV_RD08(pNv->PVIO0, address));
  78                 return NV_RD08(pNv->PVIO0, address);
  79         }
  80 }
  81
  82 static void NVWritePVIO(xf86CrtcPtr crtc, uint32_t address, uint8_t value)
  83 {
  84         ScrnInfoPtr pScrn = crtc->scrn;
  85         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  86         NVPtr pNv = NVPTR(pScrn);
  87
  88         DDXMMIOH("NVWritePVIO: head %d reg %08x val %02x\n", nv_crtc->head, address + NV_PVIO_OFFSET + (nv_crtc->head ? NV_PVIO_SIZE : 0), value);
  89         /* Only NV4x have two pvio ranges */
  90         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  91                 NV_WR08(pNv->PVIO1, address, value);
  92         } else {
  93                 NV_WR08(pNv->PVIO0, address, value);
  94         }
  95 }
  96
  97 static void NVWriteMiscOut(xf86CrtcPtr crtc, uint8_t value)
  98 {
  99         NVWritePVIO(crtc, VGA_MISC_OUT_W, value);
 100 }
 101
 102 static uint8_t NVReadMiscOut(xf86CrtcPtr crtc)
 103 {
 104         return NVReadPVIO(crtc, VGA_MISC_OUT_R);
 105 }
 106
 107 void NVWriteVGA(NVPtr pNv, int head, uint8_t index, uint8_t value)
 108 {
 109         volatile uint8_t *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 110
 111         DDXMMIOH("NVWriteVGA: head %d index 0x%02x data 0x%02x\n", head, index, value);
 112         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 113         NV_WR08(pCRTCReg, CRTC_DATA, value);
 114 }
 115
 116 uint8_t NVReadVGA(NVPtr pNv, int head, uint8_t index)
 117 {
 118         volatile uint8_t *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 119
 120         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 121         DDXMMIOH("NVReadVGA: head %d index 0x%02x data 0x%02x\n", head, index, NV_RD08(pCRTCReg, CRTC_DATA));
 122         return NV_RD08(pCRTCReg, CRTC_DATA);
 123 }
 124
 125 /* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
 126  * I suspect they in fact do nothing, but are merely a way to carry useful
 127  * per-head variables around
 128  *
 129  * Known uses:
 130  * CR57         CR58
 131  * 0x00         index to the appropriate dcb entry (or 7f for inactive)
 132  * 0x02         dcb entry's "or" value (or 00 for inactive)
 133  * 0x03         bit0 set for dual link (LVDS, possibly elsewhere too)
 134  * 0x08 or 0x09 pxclk in MHz
 135  * 0x0f         laptop panel info -     low nibble for PEXTDEV_BOOT strap
 136  *                                      high nibble for xlat strap value
 137  */
 138
 139 void NVWriteVGACR5758(NVPtr pNv, int head, uint8_t index, uint8_t value)
 140 {
 141         NVWriteVGA(pNv, head, 0x57, index);
 142         NVWriteVGA(pNv, head, 0x58, value);
 143 }
 144
 145 uint8_t NVReadVGACR5758(NVPtr pNv, int head, uint8_t index)
 146 {
 147         NVWriteVGA(pNv, head, 0x57, index);
 148         return NVReadVGA(pNv, head, 0x58);
 149 }
 150
 151 void NVWriteVgaCrtc(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 152 {
 153         ScrnInfoPtr pScrn = crtc->scrn;
 154         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 155         NVPtr pNv = NVPTR(pScrn);
 156
 157         NVWriteVGA(pNv, nv_crtc->head, index, value);
 158 }
 159
 160 uint8_t NVReadVgaCrtc(xf86CrtcPtr crtc, uint8_t index)
 161 {
 162         ScrnInfoPtr pScrn = crtc->scrn;
 163         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 164         NVPtr pNv = NVPTR(pScrn);
 165
 166         return NVReadVGA(pNv, nv_crtc->head, index);
 167 }
 168
 169 static void NVWriteVgaSeq(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 170 {
 171         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 172         NVWritePVIO(crtc, VGA_SEQ_DATA, value);
 173 }
 174
 175 static uint8_t NVReadVgaSeq(xf86CrtcPtr crtc, uint8_t index)
 176 {
 177         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 178         return NVReadPVIO(crtc, VGA_SEQ_DATA);
 179 }
 180
 181 static void NVWriteVgaGr(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 182 {
 183         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 184         NVWritePVIO(crtc, VGA_GRAPH_DATA, value);
 185 }
 186
 187 static uint8_t NVReadVgaGr(xf86CrtcPtr crtc, uint8_t index)
 188 {
 189         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 190         return NVReadPVIO(crtc, VGA_GRAPH_DATA);
 191 }
 192
 193
 194 static void NVWriteVgaAttr(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 195 {
 196         ScrnInfoPtr pScrn = crtc->scrn;
 197         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 198         NVPtr pNv = NVPTR(pScrn);
 199         volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 200
 201         DDXMMIOH("NVWriteVgaAttr: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, CRTC_IN_STAT_1, NV_RD08(pCRTCReg, CRTC_IN_STAT_1));
 202         NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 203         if (nv_crtc->paletteEnabled)
 204                 index &= ~0x20;
 205         else
 206                 index |= 0x20;
 207
 208         DDXMMIOH("NVWriteVgaAttr: head %d index 0x%02x data 0x%02x\n", nv_crtc->head, index, value);
 209         NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 210         NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
 211 }
 212
 213 static uint8_t NVReadVgaAttr(xf86CrtcPtr crtc, uint8_t index)
 214 {
 215         ScrnInfoPtr pScrn = crtc->scrn;
 216         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 217         NVPtr pNv = NVPTR(pScrn);
 218         volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 219
 220         DDXMMIOH("NVReadVgaAttr: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, CRTC_IN_STAT_1, NV_RD08(pCRTCReg, CRTC_IN_STAT_1));
 221         NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 222         if (nv_crtc->paletteEnabled)
 223                 index &= ~0x20;
 224         else
 225                 index |= 0x20;
 226
 227         NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 228         DDXMMIOH("NVReadVgaAttr: head %d index 0x%02x data 0x%02x\n", nv_crtc->head, index, NV_RD08(pCRTCReg, VGA_ATTR_DATA_R));
 229         return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
 230 }
 231
 232 static void NVCrtcSetOwner(xf86CrtcPtr crtc)
 233 {
 234         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 235         ScrnInfoPtr pScrn = crtc->scrn;
 236         NVPtr pNv = NVPTR(pScrn);
 237         /* Non standard beheaviour required by NV11 */
 238         if (pNv) {
 239                 uint8_t owner = NVReadVGA(pNv, 0, NV_VGA_CRTCX_OWNER);
 240                 ErrorF("pre-Owner: 0x%X\n", owner);
 241                 if (owner == 0x04) {
 242                         uint32_t pbus84 = nvReadMC(pNv, 0x1084);
 243                         ErrorF("pbus84: 0x%X\n", pbus84);
 244                         pbus84 &= ~(1<<28);
 245                         ErrorF("pbus84: 0x%X\n", pbus84);
 246                         nvWriteMC(pNv, 0x1084, pbus84);
 247                 }
 248                 /* The blob never writes owner to pcio1, so should we */
 249                 if (pNv->NVArch == 0x11) {
 250                         NVWriteVGA(pNv, 0, NV_VGA_CRTCX_OWNER, 0xff);
 251                 }
 252                 NVWriteVGA(pNv, 0, NV_VGA_CRTCX_OWNER, nv_crtc->head * 0x3);
 253                 owner = NVReadVGA(pNv, 0, NV_VGA_CRTCX_OWNER);
 254                 ErrorF("post-Owner: 0x%X\n", owner);
 255         } else {
 256                 ErrorF("pNv pointer is NULL\n");
 257         }
 258 }
 259
 260 static void
 261 NVEnablePalette(xf86CrtcPtr crtc)
 262 {
 263         ScrnInfoPtr pScrn = crtc->scrn;
 264         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 265         NVPtr pNv = NVPTR(pScrn);
 266         volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 267
 268         DDXMMIOH("NVEnablePalette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, CRTC_IN_STAT_1, NV_RD08(pCRTCReg, CRTC_IN_STAT_1));
 269         NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 270         DDXMMIOH("NVEnablePalette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_ATTR_INDEX, 0);
 271         NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
 272         nv_crtc->paletteEnabled = TRUE;
 273 }
 274
 275 static void
 276 NVDisablePalette(xf86CrtcPtr crtc)
 277 {
 278         ScrnInfoPtr pScrn = crtc->scrn;
 279         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 280         NVPtr pNv = NVPTR(pScrn);
 281         volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 282
 283         DDXMMIOH("NVDisablePalette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, CRTC_IN_STAT_1, NV_RD08(pCRTCReg, CRTC_IN_STAT_1));
 284         NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 285         DDXMMIOH("NVEnablePalette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_ATTR_INDEX, 0x20);
 286         NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
 287         nv_crtc->paletteEnabled = FALSE;
 288 }
 289
 290 static void NVWriteVgaReg(xf86CrtcPtr crtc, uint32_t reg, uint8_t value)
 291 {
 292         ScrnInfoPtr pScrn = crtc->scrn;
 293         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 294         NVPtr pNv = NVPTR(pScrn);
 295         volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 296
 297         DDXMMIOH("NVWriteVgaReg: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, reg, value);
 298         NV_WR08(pCRTCReg, reg, value);
 299 }
 300
 301 /* perform a sequencer reset */
 302 static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
 303 {
 304   if (start)
 305     NVWriteVgaSeq(crtc, 0x00, 0x1);
 306   else
 307     NVWriteVgaSeq(crtc, 0x00, 0x3);
 308
 309 }
 310 static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
 311 {
 312         uint8_t tmp;
 313
 314         if (on) {
 315                 tmp = NVReadVgaSeq(crtc, 0x1);
 316                 NVVgaSeqReset(crtc, TRUE);
 317                 NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
 318
 319                 NVEnablePalette(crtc);
 320         } else {
 321                 /*
 322                  * Reenable sequencer, then turn on screen.
 323                  */
 324                 tmp = NVReadVgaSeq(crtc, 0x1);
 325                 NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20); /* reenable display */
 326                 NVVgaSeqReset(crtc, FALSE);
 327
 328                 NVDisablePalette(crtc);
 329         }
 330 }
 331
 332 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool Lock)
 333 {
 334         NVPtr pNv = NVPTR(crtc->scrn);
 335         uint8_t cr11;
 336
 337         if (pNv->twoHeads)
 338                 NVCrtcSetOwner(crtc);
 339
 340         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57);
 341         cr11 = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE);
 342         if (Lock) cr11 |= 0x80;
 343         else cr11 &= ~0x80;
 344         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE, cr11);
 345 }
 346
 347 xf86OutputPtr
 348 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
 349 {
 350         ScrnInfoPtr pScrn = crtc->scrn;
 351         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 352         int i;
 353         for (i = 0; i < xf86_config->num_output; i++) {
 354                 xf86OutputPtr output = xf86_config->output[i];
 355
 356                 if (output->crtc == crtc) {
 357                         return output;
 358                 }
 359         }
 360
 361         return NULL;
 362 }
 363
 364 xf86CrtcPtr
 365 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
 366 {
 367         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 368         int i;
 369
 370         for (i = 0; i < xf86_config->num_crtc; i++) {
 371                 xf86CrtcPtr crtc = xf86_config->crtc[i];
 372                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 373                 if (nv_crtc->head == index)
 374                         return crtc;
 375         }
 376
 377         return NULL;
 378 }
 379
 380 /*
 381  * Calculate the Video Clock parameters for the PLL.
 382  */
 383 /* Code taken from NVClock, with permission of the author (being a GPL->MIT code transfer). */
 384
 385 static void
 386 CalculateVClkNV4x_SingleVCO(NVPtr pNv, struct pll_lims *pll_lim, uint32_t clockIn, uint32_t *n1_best, uint32_t *m1_best, uint32_t *p_best)
 387 {
 388         uint32_t clock, M, N, P;
 389         uint32_t delta, bestDelta, minM, maxM, minN, maxN, maxP;
 390         uint32_t minVCOInputFreq, minVCOFreq, maxVCOFreq;
 391         uint32_t VCOFreq;
 392         uint32_t refClk = pNv->CrystalFreqKHz;
 393         bestDelta = clockIn;
 394
 395         minVCOInputFreq = pll_lim->vco1.min_inputfreq;
 396         minVCOFreq = pll_lim->vco1.minfreq;
 397         maxVCOFreq = pll_lim->vco1.maxfreq;
 398         minM = pll_lim->vco1.min_m;
 399         maxM = pll_lim->vco1.max_m;
 400         minN = pll_lim->vco1.min_n;
 401         maxN = pll_lim->vco1.max_n;
 402
 403         maxP = 6;
 404
 405         /* The optimal frequency for the PLL to work at is somewhere in the center of its range.
 406         /  Choose a post divider in such a way to achieve this.
 407         /  The G8x nv driver does something similar but they they derive a minP and maxP. That
 408         /  doesn't seem required as you get so many matching clocks that you don't enter a second
 409         /  iteration for P. (The minP / maxP values in the nv driver only differ at most 1, so it is for
 410         /  some rare corner cases.
 411         */
 412         for (P=0, VCOFreq=maxVCOFreq/2; clockIn<=VCOFreq && P <= maxP; P++)
 413         {
 414                 VCOFreq /= 2;
 415         }
 416
 417         /* Calculate the m and n values. There are a lot of values which give the same speed;
 418         /  We choose the speed for which the difference with the request speed is as small as possible.
 419         */
 420         for (M=minM; M<=maxM; M++)
 421         {
 422                 /* The VCO has a minimum input frequency */
 423                 if ((refClk/M) < minVCOInputFreq)
 424                         break;
 425
 426                 for (N=minN; N<=maxN; N++)
 427                 {
 428                         /* Calculate the frequency generated by VCO1 */
 429                         clock = (int)(refClk * N / (float)M);
 430
 431                         /* Verify if the clock lies within the output limits of VCO1 */
 432                         if (clock < minVCOFreq)
 433                                 continue;
 434                         else if (clock > maxVCOFreq) /* It is no use to continue as the clock will only become higher */
 435                                 break;
 436
 437                         clock >>= P;
 438                         delta = abs((int)(clockIn - clock));
 439                         /* When the difference is 0 or less than .5% accept the speed */
 440                         if (((delta == 0) || ((float)delta/(float)clockIn <= 0.005)))
 441                         {
 442                                 *m1_best = M;
 443                                 *n1_best = N;
 444                                 *p_best = P;
 445                                 return;
 446                         }
 447
 448                         /* When the new difference is smaller than the old one, use this one */
 449                         if (delta < bestDelta)
 450                         {
 451                                 bestDelta = delta;
 452                                 *m1_best = M;
 453                                 *n1_best = N;
 454                                 *p_best = P;
 455                         }
 456                 }
 457         }
 458 }
 459
 460 static void
 461 CalculateVClkNV4x_DoubleVCO(NVPtr pNv, struct pll_lims *pll_lim, uint32_t clockIn, uint32_t *n1_best, uint32_t *n2_best, uint32_t *m1_best, uint32_t *m2_best, uint32_t *p_best)
 462 {
 463         uint32_t clock1, clock2, M, M2, N, N2, P;
 464         uint32_t delta, bestDelta, minM, minM2, maxM, maxM2, minN, minN2, maxN, maxN2, maxP;
 465         uint32_t minVCOInputFreq, minVCO2InputFreq, maxVCO2InputFreq, minVCOFreq, minVCO2Freq, maxVCOFreq, maxVCO2Freq;
 466         uint32_t VCO2Freq, maxClock;
 467         uint32_t refClk = pNv->CrystalFreqKHz;
 468         bestDelta = clockIn;
 469
 470         minVCOInputFreq = pll_lim->vco1.min_inputfreq;
 471         minVCOFreq = pll_lim->vco1.minfreq;
 472         maxVCOFreq = pll_lim->vco1.maxfreq;
 473         minM = pll_lim->vco1.min_m;
 474         maxM = pll_lim->vco1.max_m;
 475         minN = pll_lim->vco1.min_n;
 476         maxN = pll_lim->vco1.max_n;
 477
 478         minVCO2InputFreq = pll_lim->vco2.min_inputfreq;
 479         maxVCO2InputFreq = pll_lim->vco2.max_inputfreq;
 480         minVCO2Freq = pll_lim->vco2.minfreq;
 481         maxVCO2Freq = pll_lim->vco2.maxfreq;
 482         minM2 = pll_lim->vco2.min_m;
 483         maxM2 = pll_lim->vco2.max_m;
 484         minN2 = pll_lim->vco2.min_n;
 485         maxN2 = pll_lim->vco2.max_n;
 486
 487         maxP = 6;
 488
 489         maxClock = maxVCO2Freq;
 490         /* If the requested clock is behind the bios limits, try it anyway */
 491         if (clockIn > maxVCO2Freq)
 492                 maxClock = clockIn + clockIn/200; /* Add a .5% margin */
 493
 494         /* The optimal frequency for the PLL to work at is somewhere in the center of its range.
 495         /  Choose a post divider in such a way to achieve this.
 496         /  The G8x nv driver does something similar but they they derive a minP and maxP. That
 497         /  doesn't seem required as you get so many matching clocks that you don't enter a second
 498         /  iteration for P. (The minP / maxP values in the nv driver only differ at most 1, so it is for
 499         /  some rare corner cases.
 500         */
 501         for (P=0, VCO2Freq=maxClock/2; clockIn<=VCO2Freq && P <= maxP; P++)
 502         {
 503                 VCO2Freq /= 2;
 504         }
 505
 506         /* The PLLs on Geforce6/7 hardware can operate in a single stage made with only 1 VCO
 507         /  and a cascade mode of two VCOs. This second mode is in general used for relatively high
 508         /  frequencies. The loop below calculates the divider and multiplier ratios for the cascade
 509         /  mode. The code takes into account limits defined in the video bios.
 510         */
 511         for (M=minM; M<=maxM; M++)
 512         {
 513                 /* The VCO has a minimum input frequency */
 514                 if ((refClk/M) < minVCOInputFreq)
 515                         break;
 516
 517                 for (N=minN; N<=maxN; N++)
 518                 {
 519                         /* Calculate the frequency generated by VCO1 */
 520                         clock1 = (int)(refClk * N / (float)M);
 521                         /* Verify if the clock lies within the output limits of VCO1 */
 522                         if ( (clock1 < minVCOFreq) )
 523                                 continue;
 524                         else if (clock1 > maxVCOFreq) /* For future N, the clock will only increase so stop; xorg nv continues but that is useless */
 525                                 break;
 526
 527                         for (M2=minM2; M2<=maxM2; M2++)
 528                         {
 529                                 /* The clock fed to the second VCO needs to lie within a certain input range */
 530                                 if (clock1 / M2 < minVCO2InputFreq)
 531                                         break;
 532                                 else if (clock1 / M2 > maxVCO2InputFreq)
 533                                         continue;
 534
 535                                 N2 = (int)((float)((clockIn << P) * M * M2) / (float)(refClk * N)+.5);
 536                                 if( (N2 < minN2) || (N2 > maxN2) )
 537                                         continue;
 538
 539                                 /* The clock before being fed to the post-divider needs to lie within a certain range.
 540                                 /  Further there are some limits on N2/M2.
 541                                 */
 542                                 clock2 = (int)((float)(N*N2)/(M*M2) * refClk);
 543                                 if( (clock2 < minVCO2Freq) || (clock2 > maxClock))// || ((N2 / M2) < 4) || ((N2 / M2) > 10) )
 544                                         continue;
 545
 546                                 /* The post-divider delays the 'high' clock to create a low clock if requested.
 547                                 /  This post-divider exists because the VCOs can only generate frequencies within
 548                                 /  a limited frequency range. This range has been tuned to lie around half of its max
 549                                 /  input frequency. It tries to calculate all clocks (including lower ones) around this
 550                                 /  'center' frequency.
 551                                 */
 552                                 clock2 >>= P;
 553                                 delta = abs((int)(clockIn - clock2));
 554
 555                                 /* When the difference is 0 or less than .5% accept the speed */
 556                                 if (((delta == 0) || ((float)delta/(float)clockIn <= 0.005)))
 557                                 {
 558                                         *m1_best = M;
 559                                         *m2_best = M2;
 560                                         *n1_best = N;
 561                                         *n2_best = N2;
 562                                         *p_best = P;
 563                                         return;
 564                                 }
 565
 566                                 /* When the new difference is smaller than the old one, use this one */
 567                                 if (delta < bestDelta)
 568                                 {
 569                                         bestDelta = delta;
 570                                         *m1_best = M;
 571                                         *m2_best = M2;
 572                                         *n1_best = N;
 573                                         *n2_best = N2;
 574                                         *p_best = P;
 575                                 }
 576                         }
 577                 }
 578         }
 579 }
 580
 581 /* BIG NOTE: modifying vpll1 and vpll2 does not work, what bit is the switch to allow it? */
 582
 583 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
 584 /* They are only valid for NV4x, appearantly reordered for NV5x */
 585 /* gpu pll: 0x4000 + 0x4004
 586  * unknown pll: 0x4008 + 0x400c
 587  * vpll1: 0x4010 + 0x4014
 588  * vpll2: 0x4018 + 0x401c
 589  * unknown pll: 0x4020 + 0x4024
 590  * unknown pll: 0x4038 + 0x403c
 591  * Some of the unknown's are probably memory pll's.
 592  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
 593  * 1 and 2 refer to the registers of each pair. There is only one post divider.
 594  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
 595  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
 596  *     bit8: A switch that turns of the second divider and multiplier off.
 597  *     bit12: Also a switch, i haven't seen it yet.
 598  *     bit16-19: p-divider
 599  *     but 28-31: Something related to the mode that is used (see bit8).
 600  * 2) bit0-7: m-divider (a)
 601  *     bit8-15: n-multiplier (a)
 602  *     bit16-23: m-divider (b)
 603  *     bit24-31: n-multiplier (b)
 604  */
 605
 606 /* Modifying the gpu pll for example requires:
 607  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 608  * This is not needed for the vpll's which have their own bits.
 609  */
 610
 611 static void
 612 CalculateVClkNV4x(
 613         ScrnInfoPtr pScrn,
 614         uint32_t requested_clock,
 615         uint32_t *given_clock,
 616         uint32_t *pll_a,
 617         uint32_t *pll_b,
 618         uint32_t *reg580,
 619         Bool    *db1_ratio,
 620         Bool primary
 621 )
 622 {
 623         NVPtr pNv = NVPTR(pScrn);
 624         uint32_t pll_lim_reg;
 625         struct pll_lims pll_lim;
 626         /* We have 2 mulitpliers, 2 dividers and one post divider */
 627         /* Note that p is only 3 bits */
 628         int NM1 = 0xbeef, NM2 = 0xdead, log2P = 0;
 629         uint32_t special_bits = 0;
 630
 631         if (primary) {
 632                 if (!get_pll_limits_reg(pScrn, VPLL1, &pll_lim_reg))
 633                         return;
 634         } else
 635                 if (!get_pll_limits_reg(pScrn, VPLL2, &pll_lim_reg))
 636                         return;
 637
 638         get_pll_limits(pScrn, pll_lim_reg, &pll_lim);
 639
 640         if (requested_clock < pll_lim.vco1.maxfreq && pNv->NVArch > 0x40) { /* single VCO */
 641                 *db1_ratio = TRUE;
 642                 /* Turn the second set of divider and multiplier off */
 643                 /* Bogus data, the same nvidia uses */
 644                 NM2 = 0x11f;
 645                 *given_clock = getMNP_single(pScrn, pll_lim_reg, requested_clock, &NM1, &log2P);
 646         } else { /* dual VCO */
 647                 *db1_ratio = FALSE;
 648                 *given_clock = getMNP_double(pScrn, pll_lim_reg, requested_clock, &NM1, &NM2, &log2P);
 649         }
 650
 651         /* Are this all (relevant) G70 cards? */
 652         if (pNv->NVArch == 0x4B || pNv->NVArch == 0x46 || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
 653                 /* This is a big guess, but should be reasonable until we can narrow it down. */
 654                 if (*db1_ratio) {
 655                         special_bits = 0x1;
 656                 } else {
 657                         special_bits = 0x3;
 658                 }
 659         }
 660
 661         /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
 662         *pll_a = (special_bits << 30) | (log2P << 16) | NM1;
 663         /* This VCO2 bit is an educated guess, but it needs to stay on for NV4x. */
 664         *pll_b = NV31_RAMDAC_ENABLE_VCO2 | NM2;
 665
 666         if (*db1_ratio) {
 667                 if (primary) {
 668                         *reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 669                 } else {
 670                         *reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 671                 }
 672         } else {
 673                 if (primary) {
 674                         *reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
 675                 } else {
 676                         *reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
 677                 }
 678         }
 679
 680         if (*db1_ratio) {
 681                 ErrorF("vpll: n1 %d m1 %d p %d db1_ratio %d\n", NM1 >> 8, NM1 & 0xff, log2P, *db1_ratio);
 682         } else {
 683                 ErrorF("vpll: n1 %d n2 %d m1 %d m2 %d p %d db1_ratio %d\n", NM1 >> 8, NM2 >> 8, NM1 & 0xff, NM2 & 0xff, log2P, *db1_ratio);
 684         }
 685 }
 686
 687 static void nv40_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 688 {
 689         state->vpll1_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 690         state->vpll1_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 691         state->vpll2_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 692         state->vpll2_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 693         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 694         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 695         state->reg580 = nvReadRAMDAC0(pNv, NV_RAMDAC_580);
 696         state->reg594 = nvReadRAMDAC0(pNv, NV_RAMDAC_594);
 697 }
 698
 699 static void nv40_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 700 {
 701         ScrnInfoPtr pScrn = crtc->scrn;
 702         NVPtr pNv = NVPTR(pScrn);
 703         uint32_t fp_debug_0[2];
 704         uint32_t index[2];
 705         fp_debug_0[0] = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
 706         fp_debug_0[1] = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
 707
 708         /* The TMDS_PLL switch is on the actual ramdac */
 709         if (state->crosswired) {
 710                 index[0] = 1;
 711                 index[1] = 0;
 712                 ErrorF("Crosswired pll state load\n");
 713         } else {
 714                 index[0] = 0;
 715                 index[1] = 1;
 716         }
 717
 718         if (state->vpll2_b && state->vpll_changed[1]) {
 719                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0,
 720                         fp_debug_0[index[1]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 721
 722                 /* Wait for the situation to stabilise */
 723                 usleep(5000);
 724
 725                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 726                 /* for vpll2 change bits 18 and 19 are disabled */
 727                 reg_c040 &= ~(0x3 << 18);
 728                 nvWriteMC(pNv, 0xc040, reg_c040);
 729
 730                 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 731                 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 732
 733                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2_a);
 734                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 735
 736                 ErrorF("writing pllsel %08X\n", state->pllsel);
 737                 /* Don't turn vpll1 off. */
 738                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 739
 740                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 741                 ErrorF("writing reg580 %08X\n", state->reg580);
 742
 743                 /* We need to wait a while */
 744                 usleep(5000);
 745                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 746
 747                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[1]]);
 748
 749                 /* Wait for the situation to stabilise */
 750                 usleep(5000);
 751         }
 752
 753         if (state->vpll1_b && state->vpll_changed[0]) {
 754                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0,
 755                         fp_debug_0[index[0]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 756
 757                 /* Wait for the situation to stabilise */
 758                 usleep(5000);
 759
 760                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 761                 /* for vpll2 change bits 16 and 17 are disabled */
 762                 reg_c040 &= ~(0x3 << 16);
 763                 nvWriteMC(pNv, 0xc040, reg_c040);
 764
 765                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 766                 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 767
 768                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll1_a);
 769                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpll1_b);
 770
 771                 ErrorF("writing pllsel %08X\n", state->pllsel);
 772                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 773
 774                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 775                 ErrorF("writing reg580 %08X\n", state->reg580);
 776
 777                 /* We need to wait a while */
 778                 usleep(5000);
 779                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 780
 781                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[0]]);
 782
 783                 /* Wait for the situation to stabilise */
 784                 usleep(5000);
 785         }
 786
 787         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 788         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 789
 790         ErrorF("writing reg594 %08X\n", state->reg594);
 791         nvWriteRAMDAC0(pNv, NV_RAMDAC_594, state->reg594);
 792
 793         /* All clocks have been set at this point. */
 794         state->vpll_changed[0] = FALSE;
 795         state->vpll_changed[1] = FALSE;
 796 }
 797
 798 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 799 {
 800         state->vpll1_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 801         if (pNv->twoHeads) {
 802                 state->vpll2_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 803         }
 804         if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 805                 state->vpll1_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 806                 state->vpll2_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 807         }
 808         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 809         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 810 }
 811
 812
 813 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 814 {
 815         /* This sequence is important, the NV28 is very sensitive in this area. */
 816         /* Keep pllsel last and sel_clk first. */
 817         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 818         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 819
 820         if (state->vpll2_a && state->vpll_changed[1]) {
 821                 if (pNv->twoHeads) {
 822                         ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 823                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2_a);
 824                 }
 825                 if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 826                         ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 827                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 828                 }
 829         }
 830
 831         if (state->vpll1_a && state->vpll_changed[0]) {
 832                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 833                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll1_a);
 834                 if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 835                         ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 836                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpll1_b);
 837                 }
 838         }
 839
 840         ErrorF("writing pllsel %08X\n", state->pllsel);
 841         nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 842
 843         /* All clocks have been set at this point. */
 844         state->vpll_changed[0] = FALSE;
 845         state->vpll_changed[1] = FALSE;
 846 }
 847
 848 #define IS_NV44P (pNv->NVArch >= 0x44 ? 1 : 0)
 849 #define SEL_CLK_OFFSET (nv_get_sel_clk_offset(pNv->NVArch, nv_output->bus))
 850
 851 #define WIPE_OTHER_CLOCKS(_sel_clk, _head, _bus) (nv_wipe_other_clocks(_sel_clk, pNv->NVArch, _head, _bus))
 852
 853 /*
 854  * Calculate extended mode parameters (SVGA) and save in a
 855  * mode state structure.
 856  * State is not specific to a single crtc, but shared.
 857  */
 858 void nv_crtc_calc_state_ext(
 859         xf86CrtcPtr             crtc,
 860         DisplayModePtr  mode,
 861         int                             bpp,
 862         int                             DisplayWidth, /* Does this change after setting the mode? */
 863         int                             CrtcHDisplay,
 864         int                             CrtcVDisplay,
 865         int                             dotClock,
 866         int                             flags
 867 )
 868 {
 869         ScrnInfoPtr pScrn = crtc->scrn;
 870         uint32_t pixelDepth, VClk = 0;
 871         uint32_t CursorStart;
 872         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 873         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 874         NVCrtcRegPtr regp;
 875         NVPtr pNv = NVPTR(pScrn);
 876         RIVA_HW_STATE *state;
 877         int num_crtc_enabled, i;
 878         uint32_t old_clock_a = 0, old_clock_b = 0;
 879
 880         state = &pNv->ModeReg;
 881
 882         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 883
 884         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 885         NVOutputPrivatePtr nv_output = NULL;
 886         Bool is_fp = FALSE;
 887         if (output) {
 888                 nv_output = output->driver_private;
 889                 if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)
 890                         is_fp = TRUE;
 891         }
 892
 893         /* Store old clock. */
 894         if (nv_crtc->head == 1) {
 895                 old_clock_a = state->vpll2_a;
 896                 old_clock_b = state->vpll2_b;
 897         } else {
 898                 old_clock_a = state->vpll1_a;
 899                 old_clock_b = state->vpll1_b;
 900         }
 901
 902         /*
 903          * Extended RIVA registers.
 904          */
 905         /* This is pitch related, not mode related. */
 906         pixelDepth = (bpp + 1)/8;
 907         if (pNv->Architecture == NV_ARCH_40) {
 908                 /* Does register 0x580 already have a value? */
 909                 if (!state->reg580) {
 910                         state->reg580 = pNv->misc_info.ramdac_0_reg_580;
 911                 }
 912                 if (nv_crtc->head == 1) {
 913                         CalculateVClkNV4x(pScrn, dotClock, &VClk, &state->vpll2_a, &state->vpll2_b, &state->reg580, &state->db1_ratio[1], FALSE);
 914                 } else {
 915                         CalculateVClkNV4x(pScrn, dotClock, &VClk, &state->vpll1_a, &state->vpll1_b, &state->reg580, &state->db1_ratio[0], TRUE);
 916                 }
 917         } else if (pNv->twoStagePLL) {
 918                 int NM1, NM2, log2P;
 919                 VClk = getMNP_double(pScrn, 0, dotClock, &NM1, &NM2, &log2P);
 920                 if (pNv->NVArch == 0x30) {
 921                         /* See nvregisters.xml for details. */
 922                         state->pll = log2P << 16 | NM1 | (NM2 & 7) << 4 | ((NM2 >> 8) & 7) << 19 | ((NM2 >> 11) & 3) << 24 | NV30_RAMDAC_ENABLE_VCO2;
 923                 } else {
 924                         state->pll = log2P << 16 | NM1;
 925                         state->pllB = NV31_RAMDAC_ENABLE_VCO2 | NM2;
 926                 }
 927         } else {
 928                 int NM, log2P;
 929                 VClk = getMNP_single(pScrn, 0, dotClock, &NM, &log2P);
 930                 state->pll = log2P << 16 | NM;
 931         }
 932
 933         if (pNv->Architecture < NV_ARCH_40) {
 934                 if (nv_crtc->head == 1) {
 935                         state->vpll2_a = state->pll;
 936                         state->vpll2_b = state->pllB;
 937                 } else {
 938                         state->vpll1_a = state->pll;
 939                         state->vpll1_b = state->pllB;
 940                 }
 941         }
 942
 943         /* always reset vpll, just to be sure. */
 944         state->vpll_changed[nv_crtc->head] = TRUE;
 945
 946         switch (pNv->Architecture) {
 947         case NV_ARCH_04:
 948                 nv4UpdateArbitrationSettings(VClk,
 949                                                 pixelDepth * 8,
 950                                                 &(state->arbitration0),
 951                                                 &(state->arbitration1),
 952                                                 pNv);
 953                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
 954                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
 955                 if (flags & V_DBLSCAN)
 956                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 957                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
 958                 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
 959                 state->config = 0x00001114;
 960                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 961                 break;
 962         case NV_ARCH_10:
 963         case NV_ARCH_20:
 964         case NV_ARCH_30:
 965         default:
 966                 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
 967                         ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
 968                         state->arbitration0 = 128;
 969                         state->arbitration1 = 0x0480;
 970                 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
 971                         ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
 972                         nForceUpdateArbitrationSettings(VClk,
 973                                                 pixelDepth * 8,
 974                                                 &(state->arbitration0),
 975                                                 &(state->arbitration1),
 976                                                 pNv);
 977                 } else if (pNv->Architecture < NV_ARCH_30) {
 978                         nv10UpdateArbitrationSettings(VClk,
 979                                                 pixelDepth * 8,
 980                                                 &(state->arbitration0),
 981                                                 &(state->arbitration1),
 982                                                 pNv);
 983                 } else {
 984                         nv30UpdateArbitrationSettings(pNv,
 985                                                 &(state->arbitration0),
 986                                                 &(state->arbitration1));
 987                 }
 988
 989                 if (nv_crtc->head == 1) {
 990                         CursorStart = pNv->Cursor2->offset;
 991                 } else {
 992                         CursorStart = pNv->Cursor->offset;
 993                 }
 994
 995                 if (!NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
 996                         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
 997                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
 998                         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
 999                 } else {
1000                         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x0;
1001                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0x0;
1002                         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x0;
1003                 }
1004
1005                 if (flags & V_DBLSCAN)
1006                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
1007
1008                 state->config   = nvReadFB(pNv, NV_PFB_CFG0);
1009                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
1010                 break;
1011         }
1012
1013         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1014                 /* This is a bit of a guess. */
1015                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] |= 0xB8;
1016         }
1017
1018         /* okay do we have 2 CRTCs running ? */
1019         num_crtc_enabled = 0;
1020         for (i = 0; i < xf86_config->num_crtc; i++) {
1021                 if (xf86_config->crtc[i]->enabled) {
1022                         num_crtc_enabled++;
1023                 }
1024         }
1025
1026         ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
1027
1028         /* The main stuff seems to be valid for NV3x also. */
1029         if (pNv->Architecture >= NV_ARCH_30) {
1030                 /* This register is only used on the primary ramdac */
1031                 /* This seems to be needed to select the proper clocks, otherwise bad things happen */
1032
1033                 if (!state->sel_clk)
1034                         state->sel_clk = pNv->misc_info.sel_clk & ~(0xf << 16);
1035
1036                 if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
1037                         /* Only wipe when are a relevant (digital) output. */
1038                         state->sel_clk &= ~(0xf << 16);
1039                         Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1040                         /* Even with two dvi, this should not conflict. */
1041                         if (crossed_clocks) {
1042                                 state->sel_clk |= (0x1 << 16);
1043                         } else {
1044                                 state->sel_clk |= (0x4 << 16);
1045                         }
1046                 }
1047
1048                 /* Some cards, specifically dual dvi/lvds cards set another bitrange.
1049                  * I suspect inverse beheaviour to the normal bitrange, but i am not a 100% certain about this.
1050                  * This is all based on default settings found in mmio-traces.
1051                  * The blob never changes these, as it doesn't run unusual output configurations.
1052                  * It seems to prefer situations that avoid changing these bits (for a good reason?).
1053                  * I still don't know the purpose of value 2, it's similar to 4, but what exactly does it do?
1054                  */
1055
1056                 /* Some extra info:
1057                  * nv30:
1058                  *      bit 0           NVClk spread spectrum on/off
1059                  *      bit 2           MemClk spread spectrum on/off
1060                  *      bit 4           PixClk1 spread spectrum on/off
1061                  *      bit 6           PixClk2 spread spectrum on/off
1062
1063                  *      nv40:
1064                  *      what causes setting of bits not obvious but:
1065                  *      bits 4&5                relate to headA
1066                 *       bits 6&7                relate to headB
1067                 */
1068                 /* Only let digital outputs mess with this, otherwise strange output routings may mess it up. */
1069                 if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
1070                         if (pNv->Architecture == NV_ARCH_40) {
1071                                 for (i = 0; i < 4; i++) {
1072                                         uint32_t var = (state->sel_clk & (0xf << 4*i)) >> 4*i;
1073                                         if (var == 0x1 || var == 0x4) {
1074                                                 state->sel_clk &= ~(0xf << 4*i);
1075                                                 Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1076                                                 if (crossed_clocks) {
1077                                                         state->sel_clk |= (0x4 << 4*i);
1078                                                 } else {
1079                                                         state->sel_clk |= (0x1 << 4*i);
1080                                                 }
1081                                                 break; /* This should only occur once. */
1082                                         }
1083                                 }
1084                         /* Based on NV31M. */
1085                         } else if (pNv->Architecture == NV_ARCH_30) {
1086                                 for (i = 0; i < 4; i++) {
1087                                         uint32_t var = (state->sel_clk & (0xf << 4*i)) >> 4*i;
1088                                         if (var == 0x4 || var == 0x5) {
1089                                                 state->sel_clk &= ~(0xf << 4*i);
1090                                                 Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1091                                                 if (crossed_clocks) {
1092                                                         state->sel_clk |= (0x4 << 4*i);
1093                                                 } else {
1094                                                         state->sel_clk |= (0x5 << 4*i);
1095                                                 }
1096                                                 break; /* This should only occur once. */
1097                                         }
1098                                 }
1099                         }
1100                 }
1101         }
1102
1103         /* Are we crosswired? */
1104         if (output && nv_crtc->head != nv_output->preferred_output) {
1105                 state->crosswired = TRUE;
1106         } else {
1107                 state->crosswired = FALSE;
1108         }
1109
1110         if (nv_crtc->head == 1) {
1111                 if (state->db1_ratio[1]) {
1112                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1113                 } else if (nv_crtc->head == 0) {
1114                         if (state->db1_ratio[0])
1115                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1116                 }
1117         } else {
1118                 /* Do NV1x/NV2x cards need anything in sel_clk? */
1119                 state->sel_clk = 0x0;
1120                 state->crosswired = FALSE;
1121         }
1122
1123         /* The NV40 seems to have more similarities to NV3x than other cards. */
1124         if (pNv->NVArch < 0x41) {
1125                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL;
1126                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL;
1127         }
1128
1129         if (nv_crtc->head == 1) {
1130                 if (!state->db1_ratio[1]) {
1131                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1132                 } else {
1133                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1134                 }
1135                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
1136         } else {
1137                 if (!state->db1_ratio[0]) {
1138                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1139                 } else {
1140                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1141                 }
1142                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
1143         }
1144
1145         /* The blob uses this always, so let's do the same */
1146         if (pNv->Architecture == NV_ARCH_40) {
1147                 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
1148         }
1149
1150         /* The primary output resource doesn't seem to care */
1151         if (output && pNv->Architecture == NV_ARCH_40 && nv_output->output_resource == 1) { /* This is the "output" */
1152                 /* non-zero values are for analog, don't know about tv-out and the likes */
1153                 if (output && nv_output->type != OUTPUT_ANALOG) {
1154                         state->reg594 = 0x0;
1155                 } else if (output) {
1156                         /* Are we a flexible output? */
1157                         if (ffs(pNv->dcb_table.entry[nv_output->dcb_entry].or) & OUTPUT_0) {
1158                                 state->reg594 = 0x1;
1159                                 pNv->restricted_mode = FALSE;
1160                         } else {
1161                                 state->reg594 = 0x0;
1162                                 pNv->restricted_mode = TRUE;
1163                         }
1164
1165                         /* More values exist, but they seem related to the 3rd dac (tv-out?) somehow */
1166                         /* bit 16-19 are bits that are set on some G70 cards */
1167                         /* Those bits are also set to the 3rd OUTPUT register */
1168                         if (nv_crtc->head == 1) {
1169                                 state->reg594 |= 0x100;
1170                         }
1171                 }
1172         }
1173
1174         regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
1175         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
1176         if (pNv->Architecture >= NV_ARCH_30) {
1177                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
1178         }
1179
1180         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1181                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = ((CrtcHDisplay/16) & 0x700) >> 3;
1182         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1183                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((CrtcHDisplay*bpp)/64) & 0x700) >> 3;
1184         } else { /* framebuffer can be larger than crtc scanout area. */
1185                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
1186         }
1187         regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
1188 }
1189
1190 static void
1191 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
1192 {
1193         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1194
1195         ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->head, mode);
1196
1197         if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */
1198                 return;
1199
1200         nv_crtc->last_dpms = mode;
1201
1202         ScrnInfoPtr pScrn = crtc->scrn;
1203         NVPtr pNv = NVPTR(pScrn);
1204         unsigned char seq1 = 0, crtc17 = 0;
1205         unsigned char crtc1A;
1206
1207         if (pNv->twoHeads)
1208                 NVCrtcSetOwner(crtc);
1209
1210         crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
1211         switch(mode) {
1212                 case DPMSModeStandby:
1213                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
1214                 seq1 = 0x20;
1215                 crtc17 = 0x80;
1216                 crtc1A |= 0x80;
1217                 break;
1218         case DPMSModeSuspend:
1219                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
1220                 seq1 = 0x20;
1221                 crtc17 = 0x80;
1222                 crtc1A |= 0x40;
1223                 break;
1224         case DPMSModeOff:
1225                 /* Screen: Off; HSync: Off, VSync: Off */
1226                 seq1 = 0x20;
1227                 crtc17 = 0x00;
1228                 crtc1A |= 0xC0;
1229                 break;
1230         case DPMSModeOn:
1231         default:
1232                 /* Screen: On; HSync: On, VSync: On */
1233                 seq1 = 0x00;
1234                 crtc17 = 0x80;
1235                 break;
1236         }
1237
1238         NVVgaSeqReset(crtc, TRUE);
1239         /* Each head has it's own sequencer, so we can turn it off when we want */
1240         seq1 |= (NVReadVgaSeq(crtc, 0x01) & ~0x20);
1241         NVWriteVgaSeq(crtc, 0x1, seq1);
1242         crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
1243         usleep(10000);
1244         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
1245         NVVgaSeqReset(crtc, FALSE);
1246
1247         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
1248
1249         /* I hope this is the right place */
1250         if (crtc->enabled && mode == DPMSModeOn) {
1251                 pNv->crtc_active[nv_crtc->head] = TRUE;
1252         } else {
1253                 pNv->crtc_active[nv_crtc->head] = FALSE;
1254         }
1255 }
1256
1257 static Bool
1258 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
1259                      DisplayModePtr adjusted_mode)
1260 {
1261         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1262         ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->head);
1263
1264         return TRUE;
1265 }
1266
1267 static void
1268 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1269 {
1270         ScrnInfoPtr pScrn = crtc->scrn;
1271         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1272         NVCrtcRegPtr regp;
1273         NVPtr pNv = NVPTR(pScrn);
1274         NVFBLayout *pLayout = &pNv->CurrentLayout;
1275         int depth = pScrn->depth;
1276
1277         /* This is pitch/memory size related. */
1278         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE))
1279                 depth = pNv->console_mode[nv_crtc->head].bpp;
1280
1281         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1282
1283         /* Calculate our timings */
1284         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
1285         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
1286         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
1287         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
1288         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
1289         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
1290         int vertDisplay         = mode->CrtcVDisplay                    - 1;
1291         int vertStart           = mode->CrtcVSyncStart          - 1;
1292         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
1293         int vertTotal           = mode->CrtcVTotal                      - 2;
1294         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
1295         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
1296
1297         Bool is_fp = FALSE;
1298
1299         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1300         NVOutputPrivatePtr nv_output = NULL;
1301         if (output) {
1302                 nv_output = output->driver_private;
1303
1304                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1305                         is_fp = TRUE;
1306         }
1307
1308         ErrorF("Mode clock: %d\n", mode->Clock);
1309         ErrorF("Adjusted mode clock: %d\n", adjusted_mode->Clock);
1310
1311         /* Reverted to what nv did, because that works for all resolutions on flatpanels */
1312         if (is_fp) {
1313                 vertStart = vertTotal - 3;
1314                 vertEnd = vertTotal - 2;
1315                 vertBlankStart = vertStart;
1316                 horizStart = horizTotal - 5;
1317                 horizEnd = horizTotal - 2;
1318                 horizBlankEnd = horizTotal + 4;
1319                 if (pNv->overlayAdaptor && pNv->Architecture >= NV_ARCH_10) {
1320                         /* This reportedly works around Xv some overlay bandwidth problems*/
1321                         horizTotal += 2;
1322                 }
1323         }
1324
1325         if (mode->Flags & V_INTERLACE)
1326                 vertTotal |= 1;
1327
1328         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
1329         ErrorF("horizStart: 0x%X \n", horizStart);
1330         ErrorF("horizEnd: 0x%X \n", horizEnd);
1331         ErrorF("horizTotal: 0x%X \n", horizTotal);
1332         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
1333         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
1334         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
1335         ErrorF("vertStart: 0x%X \n", vertStart);
1336         ErrorF("vertEnd: 0x%X \n", vertEnd);
1337         ErrorF("vertTotal: 0x%X \n", vertTotal);
1338         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
1339         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
1340
1341         /*
1342         * compute correct Hsync & Vsync polarity
1343         */
1344         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
1345                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
1346
1347                 regp->MiscOutReg = 0x23;
1348                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
1349                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
1350         } else {
1351                 int VDisplay = mode->VDisplay;
1352                 if (mode->Flags & V_DBLSCAN)
1353                         VDisplay *= 2;
1354                 if (mode->VScan > 1)
1355                         VDisplay *= mode->VScan;
1356                 if (VDisplay < 400) {
1357                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
1358                 } else if (VDisplay < 480) {
1359                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
1360                 } else if (VDisplay < 768) {
1361                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
1362                 } else {
1363                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
1364                 }
1365         }
1366
1367         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
1368
1369         /*
1370         * Time Sequencer
1371         */
1372         regp->Sequencer[0] = 0x00;
1373         /* 0x20 disables the sequencer */
1374         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1375                 if (mode->HDisplay == 720) {
1376                         regp->Sequencer[1] = 0x21; /* enable 9/8 mode */
1377                 } else {
1378                         regp->Sequencer[1] = 0x20;
1379                 }
1380         } else {
1381                 if (mode->Flags & V_CLKDIV2) {
1382                         regp->Sequencer[1] = 0x29;
1383                 } else {
1384                         regp->Sequencer[1] = 0x21;
1385                 }
1386         }
1387         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1388                 regp->Sequencer[2] = 0x03; /* select 2 out of 4 planes */
1389         } else {
1390                 regp->Sequencer[2] = 0x0F;
1391         }
1392         regp->Sequencer[3] = 0x00;                     /* Font select */
1393         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1394                 regp->Sequencer[4] = 0x02;
1395         } else {
1396                 regp->Sequencer[4] = 0x0E;                             /* Misc */
1397         }
1398
1399         /*
1400         * CRTC Controller
1401         */
1402         regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
1403         regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
1404         regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
1405         regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0)
1406                                 | SetBit(7);
1407         regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
1408         regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
1409                                 | SetBitField(horizEnd,4:0,4:0);
1410         regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
1411         regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
1412                                 | SetBitField(vertDisplay,8:8,1:1)
1413                                 | SetBitField(vertStart,8:8,2:2)
1414                                 | SetBitField(vertBlankStart,8:8,3:3)
1415                                 | SetBit(4)
1416                                 | SetBitField(vertTotal,9:9,5:5)
1417                                 | SetBitField(vertDisplay,9:9,6:6)
1418                                 | SetBitField(vertStart,9:9,7:7);
1419         regp->CRTC[NV_VGA_CRTCX_PRROWSCN]  = 0x00;
1420         regp->CRTC[NV_VGA_CRTCX_MAXSCLIN]  = SetBitField(vertBlankStart,9:9,5:5)
1421                                 | SetBit(6)
1422                                 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00)
1423                                 | (NVMatchModePrivate(mode, NV_MODE_VGA) ? 0xF : 0x00); /* 8x15 chars */
1424         if (NVMatchModePrivate(mode, NV_MODE_VGA)) { /* Were do these cursor offsets come from? */
1425                 regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0xD; /* start scanline */
1426                 regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0xE; /* end scanline */
1427         } else {
1428                 regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0x00;
1429                 regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0x00;
1430         }
1431         regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00;
1432         regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
1433         regp->CRTC[0xe] = 0x00;
1434         regp->CRTC[0xf] = 0x00;
1435         regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
1436         /* What is the meaning of bit5, it is empty in the vga spec. */
1437         regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) |
1438                                                                         (NVMatchModePrivate(mode, NV_MODE_VGA) ? 0 : SetBit(5));
1439         regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
1440         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1441                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = (mode->CrtcHDisplay/16);
1442         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1443                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((mode->CrtcHDisplay*depth)/64);
1444         } else { /* framebuffer can be larger than crtc scanout area. */
1445                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
1446         }
1447         if (depth == 4) { /* How can these values be calculated? */
1448                 regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x1F;
1449         } else {
1450                 regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x00;
1451         }
1452         regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
1453         regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
1454         /* 0x80 enables the sequencer, we don't want that */
1455         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1456                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xA3 & ~0x80;
1457         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1458                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xE3 & ~0x80;
1459         } else {
1460                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80;
1461         }
1462         regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
1463
1464         /*
1465          * Some extended CRTC registers (they are not saved with the rest of the vga regs).
1466          */
1467
1468         regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
1469                                 | SetBitField(vertBlankStart,10:10,3:3)
1470                                 | SetBitField(vertStart,10:10,2:2)
1471                                 | SetBitField(vertDisplay,10:10,1:1)
1472                                 | SetBitField(vertTotal,10:10,0:0);
1473
1474         regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
1475                                 | SetBitField(horizDisplay,8:8,1:1)
1476                                 | SetBitField(horizBlankStart,8:8,2:2)
1477                                 | SetBitField(horizStart,8:8,3:3);
1478
1479         regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
1480                                 | SetBitField(vertDisplay,11:11,2:2)
1481                                 | SetBitField(vertStart,11:11,4:4)
1482                                 | SetBitField(vertBlankStart,11:11,6:6);
1483
1484         if(mode->Flags & V_INTERLACE) {
1485                 horizTotal = (horizTotal >> 1) & ~1;
1486                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
1487                 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
1488         } else {
1489                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff;  /* interlace off */
1490         }
1491
1492         /*
1493         * Theory resumes here....
1494         */
1495
1496         /*
1497         * Graphics Display Controller
1498         */
1499         regp->Graphics[0] = 0x00;
1500         regp->Graphics[1] = 0x00;
1501         regp->Graphics[2] = 0x00;
1502         regp->Graphics[3] = 0x00;
1503         regp->Graphics[4] = 0x00;
1504         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1505                 regp->Graphics[5] = 0x10;
1506                 regp->Graphics[6] = 0x0E; /* map 32k mem */
1507                 regp->Graphics[7] = 0x00;
1508         } else {
1509                 regp->Graphics[5] = 0x40; /* 256 color mode */
1510                 regp->Graphics[6] = 0x05; /* map 64k mem + graphic mode */
1511                 regp->Graphics[7] = 0x0F;
1512         }
1513         regp->Graphics[8] = 0xFF;
1514
1515         /* I ditched the mono stuff */
1516         regp->Attribute[0]  = 0x00; /* standard colormap translation */
1517         regp->Attribute[1]  = 0x01;
1518         regp->Attribute[2]  = 0x02;
1519         regp->Attribute[3]  = 0x03;
1520         regp->Attribute[4]  = 0x04;
1521         regp->Attribute[5]  = 0x05;
1522         regp->Attribute[6]  = 0x06;
1523         regp->Attribute[7]  = 0x07;
1524         regp->Attribute[8]  = 0x08;
1525         regp->Attribute[9]  = 0x09;
1526         regp->Attribute[10] = 0x0A;
1527         regp->Attribute[11] = 0x0B;
1528         regp->Attribute[12] = 0x0C;
1529         regp->Attribute[13] = 0x0D;
1530         regp->Attribute[14] = 0x0E;
1531         regp->Attribute[15] = 0x0F;
1532         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1533                 regp->Attribute[16] = 0x0C; /* Line Graphics Enable + Blink enable */
1534         } else {
1535                 regp->Attribute[16] = 0x01; /* Enable graphic mode */
1536         }
1537         /* Non-vga */
1538         regp->Attribute[17] = 0x00;
1539         regp->Attribute[18] = 0x0F; /* enable all color planes */
1540         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1541                 regp->Attribute[19] = 0x08; /* shift bits by 8 */
1542         } else {
1543                 regp->Attribute[19] = 0x00;
1544         }
1545         regp->Attribute[20] = 0x00;
1546 }
1547
1548 #define MAX_H_VALUE(i) ((0x1ff + i) << 3)
1549 #define MAX_V_VALUE(i) ((0xfff + i) << 0)
1550
1551 /**
1552  * Sets up registers for the given mode/adjusted_mode pair.
1553  *
1554  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1555  *
1556  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1557  * be easily turned on/off after this.
1558  */
1559 static void
1560 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1561 {
1562         ScrnInfoPtr pScrn = crtc->scrn;
1563         NVPtr pNv = NVPTR(pScrn);
1564         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1565         NVFBLayout *pLayout = &pNv->CurrentLayout;
1566         NVCrtcRegPtr regp, savep;
1567         uint32_t i, depth;
1568         Bool is_fp = FALSE;
1569         Bool is_lvds = FALSE;
1570
1571         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1572         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1573
1574         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1575         NVOutputPrivatePtr nv_output = NULL;
1576         if (output) {
1577                 nv_output = output->driver_private;
1578
1579                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1580                         is_fp = TRUE;
1581
1582                 if (nv_output->type == OUTPUT_LVDS)
1583                         is_lvds = TRUE;
1584         }
1585
1586         /* Registers not directly related to the (s)vga mode */
1587
1588         /* bit2 = 0 -> fine pitched crtc granularity */
1589         /* The rest disables double buffering on CRTC access */
1590         regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
1591
1592         if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
1593                 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1594                 if (nv_crtc->head == 0) {
1595                         regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1596                 }
1597
1598                 if (is_fp) {
1599                         regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0);
1600                         if (!NVMatchModePrivate(mode, NV_MODE_VGA)) {
1601                                 regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 1);
1602                         }
1603                 }
1604         } else {
1605                 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
1606                 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
1607         }
1608
1609         /* Sometimes 0x10 is used, what is this? */
1610         regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1611         /* Some kind of tmds switch for older cards */
1612         if (pNv->Architecture < NV_ARCH_40) {
1613                 regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
1614         }
1615
1616         /*
1617         * Initialize DAC palette.
1618         * Will only be written when depth != 8.
1619         */
1620         for (i = 0; i < 256; i++) {
1621                 regp->DAC[i*3] = i;
1622                 regp->DAC[(i*3)+1] = i;
1623                 regp->DAC[(i*3)+2] = i;
1624         }
1625
1626         /*
1627         * Calculate the extended registers.
1628         */
1629
1630         if (pLayout->depth < 24) {
1631                 depth = pLayout->depth;
1632         } else {
1633                 depth = 32;
1634         }
1635
1636         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1637                 /* bpp is pitch related. */
1638                 depth = pNv->console_mode[nv_crtc->head].bpp;
1639         }
1640
1641         /* What is the meaning of this register? */
1642         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1643         regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
1644
1645         regp->head = 0;
1646
1647         /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1648         /* But what are those special conditions? */
1649         if (pNv->Architecture <= NV_ARCH_30) {
1650                 if (is_fp) {
1651                         if(nv_crtc->head == 1) {
1652                                 regp->head |= NV_CRTC_FSEL_FPP1;
1653                         } else if (pNv->twoHeads) {
1654                                 regp->head |= NV_CRTC_FSEL_FPP2;
1655                         }
1656                 }
1657         } else {
1658                 /* Most G70 cards have FPP2 set on the secondary CRTC. */
1659                 if (nv_crtc->head == 1 && pNv->NVArch > 0x44) {
1660                         regp->head |= NV_CRTC_FSEL_FPP2;
1661                 }
1662         }
1663
1664         /* Except for rare conditions I2C is enabled on the primary crtc */
1665         if (nv_crtc->head == 0) {
1666                 regp->head |= NV_CRTC_FSEL_I2C;
1667         }
1668
1669         /* Set overlay to desired crtc. */
1670         if (pNv->overlayAdaptor) {
1671                 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(pNv);
1672                 if (pPriv->overlayCRTC == nv_crtc->head)
1673                         regp->head |= NV_CRTC_FSEL_OVERLAY;
1674         }
1675
1676         /* This is not what nv does, but it is what the blob does (for nv4x at least) */
1677         /* This fixes my cursor corruption issue */
1678         regp->cursorConfig = 0x0;
1679         if(mode->Flags & V_DBLSCAN)
1680                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_DOUBLE_SCAN;
1681         if (pNv->alphaCursor && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1682                 regp->cursorConfig |=   (NV_CRTC_CURSOR_CONFIG_32BPP |
1683                                                         NV_CRTC_CURSOR_CONFIG_64PIXELS |
1684                                                         NV_CRTC_CURSOR_CONFIG_64LINES |
1685                                                         NV_CRTC_CURSOR_CONFIG_ALPHA_BLEND);
1686         } else {
1687                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_32LINES;
1688         }
1689
1690         /* Unblock some timings */
1691         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1692         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1693
1694         /* What is the purpose of this register? */
1695         /* 0x14 may be disabled? */
1696         regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1697
1698         /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
1699         if (is_lvds) {
1700                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x11;
1701         } else if (is_fp) {
1702                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1703         } else {
1704                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1705         }
1706
1707         /* These values seem to vary */
1708         /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
1709         regp->CRTC[NV_VGA_CRTCX_3C] = savep->CRTC[NV_VGA_CRTCX_3C];
1710
1711         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1712                 regp->CRTC[NV_VGA_CRTCX_45] = 0x0;
1713         } else {
1714                 regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1715         }
1716
1717         /* What does this do?:
1718          * bit0: crtc0
1719          * bit6: lvds
1720          * bit7: lvds + tmds (only in X)
1721          */
1722         if (nv_crtc->head == 0)
1723                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x1;
1724         else
1725                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x0;
1726
1727         if (is_lvds)
1728                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x40;
1729
1730         if (is_fp && !NVMatchModePrivate(mode, NV_MODE_VGA))
1731                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x80;
1732
1733         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) { /* we need consistent restore. */
1734                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[nv_crtc->head];
1735         } else {
1736                 /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1.*/
1737                 if (nv_crtc->head == 1) {
1738                         regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[0];
1739                 } else {
1740                         regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[0] + 4;
1741                 }
1742         }
1743
1744         if (pNv->twoHeads)
1745                 /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1746                 regp->unk81c = nvReadCRTC0(pNv, NV_CRTC_081C);
1747
1748         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1749                 regp->unk830 = 0;
1750                 regp->unk834 = 0;
1751         } else {
1752                 regp->unk830 = mode->CrtcVDisplay - 3;
1753                 regp->unk834 = mode->CrtcVDisplay - 1;
1754         }
1755
1756         if (pNv->twoHeads)
1757                 /* This is what the blob does */
1758                 regp->unk850 = nvReadCRTC(pNv, 0, NV_CRTC_0850);
1759
1760         /* Never ever modify gpio, unless you know very well what you're doing */
1761         regp->gpio = nvReadCRTC(pNv, 0, NV_CRTC_GPIO);
1762
1763         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1764                 regp->config = 0x0; /* VGA mode */
1765         } else {
1766                 regp->config = 0x2; /* HSYNC mode */
1767         }
1768
1769         /* Some misc regs */
1770         regp->CRTC[NV_VGA_CRTCX_43] = 0x1;
1771         if (pNv->Architecture == NV_ARCH_40) {
1772                 regp->CRTC[NV_VGA_CRTCX_85] = 0xFF;
1773                 regp->CRTC[NV_VGA_CRTCX_86] = 0x1;
1774         }
1775
1776         /*
1777          * Calculate the state that is common to all crtc's (stored in the state struct).
1778          */
1779         ErrorF("crtc %d %d %d\n", nv_crtc->head, mode->CrtcHDisplay, pScrn->displayWidth);
1780         nv_crtc_calc_state_ext(crtc,
1781                                 mode,
1782                                 depth,
1783                                 pScrn->displayWidth,
1784                                 mode->CrtcHDisplay,
1785                                 mode->CrtcVDisplay,
1786                                 adjusted_mode->Clock,
1787                                 mode->Flags);
1788
1789         /* Enable slaved mode */
1790         if (is_fp) {
1791                 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1792         }
1793 }
1794
1795 static void
1796 nv_crtc_mode_set_ramdac_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1797 {
1798         ScrnInfoPtr pScrn = crtc->scrn;
1799         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1800         NVCrtcRegPtr regp, savep;
1801         NVPtr pNv = NVPTR(pScrn);
1802         NVFBLayout *pLayout = &pNv->CurrentLayout;
1803         Bool is_fp = FALSE;
1804         Bool is_lvds = FALSE;
1805         float aspect_ratio, panel_ratio;
1806         uint32_t h_scale, v_scale;
1807
1808         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1809         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1810
1811         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1812         NVOutputPrivatePtr nv_output = NULL;
1813         if (output) {
1814                 nv_output = output->driver_private;
1815
1816                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1817                         is_fp = TRUE;
1818
1819                 if (nv_output->type == OUTPUT_LVDS)
1820                         is_lvds = TRUE;
1821         }
1822
1823         if (is_fp) {
1824                 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
1825                 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
1826                 /* This is what the blob does. */
1827                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HSyncStart - 75 - 1;
1828                 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
1829                 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
1830                 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
1831                 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
1832
1833                 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
1834                 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
1835                 /* This is what the blob does. */
1836                 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VTotal - 5 - 1;
1837                 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
1838                 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
1839                 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
1840                 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
1841
1842                 ErrorF("Horizontal:\n");
1843                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
1844                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
1845                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
1846                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
1847                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
1848                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
1849                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
1850
1851                 ErrorF("Vertical:\n");
1852                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
1853                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
1854                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
1855                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
1856                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
1857                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
1858                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
1859         }
1860
1861         /*
1862         * bit0: positive vsync
1863         * bit4: positive hsync
1864         * bit8: enable center mode
1865         * bit9: enable native mode
1866         * bit24: 12/24 bit interface (12bit=on, 24bit=off)
1867         * bit26: a bit sometimes seen on some g70 cards
1868         * bit28: fp display enable bit
1869         * bit31: set for dual link LVDS
1870         * nv10reg contains a few more things, but i don't quite get what it all means.
1871         */
1872
1873         if (pNv->Architecture >= NV_ARCH_30)
1874                 regp->fp_control[nv_crtc->head] = 0x00100000;
1875         else
1876                 regp->fp_control[nv_crtc->head] = 0x00000000;
1877
1878         /* Deal with vsync/hsync polarity */
1879         /* LVDS screens do set this, but modes with +ve syncs are very rare */
1880         if (is_fp) {
1881                 if (adjusted_mode->Flags & V_PVSYNC)
1882                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
1883                 if (adjusted_mode->Flags & V_PHSYNC)
1884                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
1885         } else {
1886                 /* The blob doesn't always do this, but often */
1887                 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_VSYNC_DISABLE;
1888                 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_HSYNC_DISABLE;
1889         }
1890
1891         if (is_fp) {
1892                 if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) /* seems to be used almost always */
1893                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1894                 else if (nv_output->scaling_mode == SCALE_PANEL) /* panel needs to scale */
1895                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
1896                 /* This is also true for panel scaling, so we must put the panel scale check first */
1897                 else if (mode->Clock == adjusted_mode->Clock) /* native mode */
1898                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
1899                 else /* gpu needs to scale */
1900                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1901         }
1902
1903         if (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
1904                 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
1905
1906         /* If the special bit exists, it exists on both ramdacs */
1907         regp->fp_control[nv_crtc->head] |= nvReadRAMDAC0(pNv, NV_RAMDAC_FP_CONTROL) & (1 << 26);
1908
1909         if (is_fp)
1910                 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS;
1911         else
1912                 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE;
1913
1914         Bool lvds_use_straps = pNv->dcb_table.entry[nv_output->dcb_entry].lvdsconf.use_straps_for_mode;
1915         if (is_lvds && ((lvds_use_straps && pNv->VBIOS.fp.dual_link) || (!lvds_use_straps && adjusted_mode->Clock >= pNv->VBIOS.fp.duallink_transition_clk)))
1916                 regp->fp_control[nv_crtc->head] |= (8 << 28);
1917
1918         if (is_fp) {
1919                 ErrorF("Pre-panel scaling\n");
1920                 ErrorF("panel-size:%dx%d\n", nv_output->fpWidth, nv_output->fpHeight);
1921                 panel_ratio = (nv_output->fpWidth)/(float)(nv_output->fpHeight);
1922                 ErrorF("panel_ratio=%f\n", panel_ratio);
1923                 aspect_ratio = (mode->HDisplay)/(float)(mode->VDisplay);
1924                 ErrorF("aspect_ratio=%f\n", aspect_ratio);
1925                 /* Scale factors is the so called 20.12 format, taken from Haiku */
1926                 h_scale = ((1 << 12) * mode->HDisplay)/nv_output->fpWidth;
1927                 v_scale = ((1 << 12) * mode->VDisplay)/nv_output->fpHeight;
1928                 ErrorF("h_scale=%d\n", h_scale);
1929                 ErrorF("v_scale=%d\n", v_scale);
1930
1931                 /* This can override HTOTAL and VTOTAL */
1932                 regp->debug_2 = 0;
1933
1934                 /* We want automatic scaling */
1935                 regp->debug_1 = 0;
1936
1937                 regp->fp_hvalid_start = 0;
1938                 regp->fp_hvalid_end = (nv_output->fpWidth - 1);
1939
1940                 regp->fp_vvalid_start = 0;
1941                 regp->fp_vvalid_end = (nv_output->fpHeight - 1);
1942
1943                 /* 0 = panel scaling */
1944                 if (nv_output->scaling_mode == SCALE_PANEL) {
1945                         ErrorF("Flat panel is doing the scaling.\n");
1946                 } else {
1947                         ErrorF("GPU is doing the scaling.\n");
1948
1949                         if (nv_output->scaling_mode == SCALE_ASPECT) {
1950                                 /* GPU scaling happens automaticly at a ratio of 1.33 */
1951                                 /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
1952                                 if (h_scale != (1 << 12) && (panel_ratio > (aspect_ratio + 0.10))) {
1953                                         uint32_t diff;
1954
1955                                         ErrorF("Scaling resolution on a widescreen panel\n");
1956
1957                                         /* Scaling in both directions needs to the same */
1958                                         h_scale = v_scale;
1959
1960                                         /* Set a new horizontal scale factor and enable testmode (bit12) */
1961                                         regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
1962
1963                                         diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
1964                                         regp->fp_hvalid_start = diff/2;
1965                                         regp->fp_hvalid_end = nv_output->fpWidth - (diff/2) - 1;
1966                                 }
1967
1968                                 /* Same scaling, just for panels with aspect ratio's smaller than 1 */
1969                                 if (v_scale != (1 << 12) && (panel_ratio < (aspect_ratio - 0.10))) {
1970                                         uint32_t diff;
1971
1972                                         ErrorF("Scaling resolution on a portrait panel\n");
1973
1974                                         /* Scaling in both directions needs to the same */
1975                                         v_scale = h_scale;
1976
1977                                         /* Set a new vertical scale factor and enable testmode (bit28) */
1978                                         regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
1979
1980                                         diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
1981                                         regp->fp_vvalid_start = diff/2;
1982                                         regp->fp_vvalid_end = nv_output->fpHeight - (diff/2) - 1;
1983                                 }
1984                         }
1985                 }
1986
1987                 ErrorF("Post-panel scaling\n");
1988         }
1989
1990         if (!is_fp && NVMatchModePrivate(mode, NV_MODE_VGA)) {
1991                 regp->debug_1 = 0x08000800;
1992         }
1993
1994         if (pNv->Architecture >= NV_ARCH_10) {
1995                 /* Bios and blob don't seem to do anything (else) */
1996                 if (!NVMatchModePrivate(mode, NV_MODE_CONSOLE))
1997                         regp->nv10_cursync = (1<<25);
1998                 else
1999                         regp->nv10_cursync = 0;
2000         }
2001
2002         /* These are the common blob values, minus a few fp specific bit's */
2003         /* Let's keep the TMDS pll and fpclock running in all situations */
2004         regp->debug_0[nv_crtc->head] = 0x1101100;
2005
2006         if (is_fp && nv_output->scaling_mode != SCALE_NOSCALE) {
2007                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_XSCALE_ENABLED;
2008                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_YSCALE_ENABLED;
2009         } else if (is_fp) { /* no_scale mode, so we must center it */
2010                 uint32_t diff;
2011
2012                 diff = nv_output->fpWidth - mode->HDisplay;
2013                 regp->fp_hvalid_start = diff/2;
2014                 regp->fp_hvalid_end = (nv_output->fpWidth - diff/2 - 1);
2015
2016                 diff = nv_output->fpHeight - mode->VDisplay;
2017                 regp->fp_vvalid_start = diff/2;
2018                 regp->fp_vvalid_end = (nv_output->fpHeight - diff/2 - 1);
2019         }
2020
2021         /* Is this crtc bound or output bound? */
2022         /* Does the bios TMDS script try to change this sometimes? */
2023         if (is_fp) {
2024                 /* I am not completely certain, but seems to be set only for dfp's */
2025                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED;
2026         }
2027
2028         if (output)
2029                 ErrorF("output %d debug_0 %08X\n", nv_output->output_resource, regp->debug_0[nv_crtc->head]);
2030
2031         /* Flatpanel support needs at least a NV10 */
2032         if (pNv->twoHeads) {
2033                 /* The blob does this differently. */
2034                 /* TODO: Find out what precisely and why. */
2035                 /* Let's not destroy any bits that were already present. */
2036                 if (pNv->FPDither || (is_lvds && pNv->VBIOS.fp.if_is_18bit)) {
2037                         if (pNv->NVArch == 0x11) {
2038                                 regp->dither = savep->dither | 0x00010000;
2039                         } else {
2040                                 regp->dither = savep->dither | 0x00000001;
2041                         }
2042                 } else {
2043                         regp->dither = savep->dither;
2044                 }
2045         }
2046
2047         uint8_t depth;
2048         /* This is mode related, not pitch. */
2049         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
2050                 depth = pNv->console_mode[nv_crtc->head].depth;
2051         } else {
2052                 depth = pLayout->depth;
2053         }
2054
2055         switch (depth) {
2056                 case 4:
2057                         regp->general = 0x00000100;
2058                         break;
2059                 case 24:
2060                 case 15:
2061                         regp->general = 0x00100100;
2062                         break;
2063                 case 32:
2064                 case 16:
2065                 case 8:
2066                 default:
2067                         regp->general = 0x00101100;
2068                         break;
2069         }
2070
2071         if (depth > 8 && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
2072                 regp->general |= 0x30; /* enable palette mode */
2073         }
2074
2075         if (pNv->alphaCursor && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
2076                 /* PIPE_LONG mode, something to do with the size of the cursor? */
2077                 regp->general |= (1<<29);
2078         }
2079
2080         /* Some values the blob sets */
2081         /* This may apply to the real ramdac that is being used (for crosswired situations) */
2082         /* Nevertheless, it's unlikely to cause many problems, since the values are equal for both */
2083         regp->unk_a20 = 0x0;
2084         regp->unk_a24 = 0xfffff;
2085         regp->unk_a34 = 0x1;
2086
2087         if (pNv->twoHeads) {
2088                 /* Do we also "own" the other register pair? */
2089                 /* If we own neither, they will just be ignored at load time. */
2090                 uint8_t other_head = (~nv_crtc->head) & 1;
2091                 if (pNv->fp_regs_owner[other_head] == nv_crtc->head) {
2092                         if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS) {
2093                                 regp->fp_control[other_head] = regp->fp_control[nv_crtc->head];
2094                                 regp->debug_0[other_head] = regp->debug_0[nv_crtc->head];
2095                                 /* Set TMDS_PLL and FPCLK, only seen for a NV31M so far. */
2096                                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK;
2097                                 regp->debug_0[other_head] |= NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL;
2098                         } else {
2099                                 ErrorF("This is BAD, we own more than one fp reg set, but are not a LVDS or TMDS output.\n");
2100                         }
2101                 }
2102         }
2103 }
2104
2105 /**
2106  * Sets up registers for the given mode/adjusted_mode pair.
2107  *
2108  * The clocks, CRTCs and outputs attached to this CRTC must be off.
2109  *
2110  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
2111  * be easily turned on/off after this.
2112  */
2113 static void
2114 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
2115                  DisplayModePtr adjusted_mode,
2116                  int x, int y)
2117 {
2118         ScrnInfoPtr pScrn = crtc->scrn;
2119         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2120         NVPtr pNv = NVPTR(pScrn);
2121         NVFBLayout *pLayout = &pNv->CurrentLayout;
2122
2123         ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->head);
2124
2125         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->head);
2126         xf86PrintModeline(pScrn->scrnIndex, mode);
2127         if (pNv->twoHeads)
2128                 NVCrtcSetOwner(crtc);
2129
2130         nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
2131         nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
2132         nv_crtc_mode_set_ramdac_regs(crtc, mode, adjusted_mode);
2133
2134         NVVgaProtect(crtc, TRUE);
2135         nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
2136         nv_crtc_load_state_ext(crtc, &pNv->ModeReg, FALSE);
2137         if (pLayout->depth > 8)
2138                 NVCrtcLoadPalette(crtc);
2139         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
2140         if (pNv->Architecture == NV_ARCH_40) {
2141                 nv40_crtc_load_state_pll(crtc, &pNv->ModeReg);
2142         } else {
2143                 nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
2144         }
2145
2146         NVVgaProtect(crtc, FALSE);
2147
2148         NVCrtcSetBase(crtc, x, y, NVMatchModePrivate(mode, NV_MODE_CONSOLE));
2149
2150 #if X_BYTE_ORDER == X_BIG_ENDIAN
2151         /* turn on LFB swapping */
2152         {
2153                 unsigned char tmp;
2154
2155                 tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
2156                 tmp |= (1 << 7);
2157                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
2158         }
2159 #endif
2160 }
2161
2162 /* This functions generates data that is not saved, but still is needed. */
2163 void nv_crtc_restore_generate(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2164 {
2165         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2166         ScrnInfoPtr pScrn = crtc->scrn;
2167         NVPtr pNv = NVPTR(pScrn);
2168         int i;
2169         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
2170
2171         /* It's a good idea to also save a default palette on shutdown. */
2172         for (i = 0; i < 256; i++) {
2173                 regp->DAC[i*3] = i;
2174                 regp->DAC[(i*3)+1] = i;
2175                 regp->DAC[(i*3)+2] = i;
2176         }
2177
2178         /* Noticed that reading this variable is problematic on one card. */
2179         if (pNv->NVArch == 0x11)
2180                 state->sel_clk = 0x0;
2181 }
2182
2183 void nv_crtc_save(xf86CrtcPtr crtc)
2184 {
2185         ScrnInfoPtr pScrn = crtc->scrn;
2186         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2187         NVPtr pNv = NVPTR(pScrn);
2188
2189         ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->head);
2190
2191         /* We just came back from terminal, so unlock */
2192         NVCrtcLockUnlock(crtc, FALSE);
2193
2194         if (pNv->twoHeads)
2195                 NVCrtcSetOwner(crtc);
2196         nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
2197         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
2198         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
2199         if (pNv->Architecture == NV_ARCH_40) {
2200                 nv40_crtc_save_state_pll(pNv, &pNv->SavedReg);
2201         } else {
2202                 nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
2203         }
2204 }
2205
2206 void nv_crtc_restore(xf86CrtcPtr crtc)
2207 {
2208         ScrnInfoPtr pScrn = crtc->scrn;
2209         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2210         NVPtr pNv = NVPTR(pScrn);
2211         RIVA_HW_STATE *state;
2212         NVCrtcRegPtr savep;
2213
2214         state = &pNv->SavedReg;
2215         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
2216
2217         ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->head);
2218
2219         if (pNv->twoHeads)
2220                 NVCrtcSetOwner(crtc);
2221
2222         /* Just to be safe */
2223         NVCrtcLockUnlock(crtc, FALSE);
2224
2225         NVVgaProtect(crtc, TRUE);
2226         nv_crtc_restore_generate(crtc, &pNv->SavedReg);
2227         nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
2228         nv_crtc_load_state_ext(crtc, &pNv->SavedReg, TRUE);
2229         if (savep->general & 0x30) /* Palette mode */
2230                 NVCrtcLoadPalette(crtc);
2231         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
2232
2233         /* Force restoring vpll. */
2234         state->vpll_changed[nv_crtc->head] = TRUE;
2235
2236         if (pNv->Architecture == NV_ARCH_40) {
2237                 nv40_crtc_load_state_pll(crtc, &pNv->SavedReg);
2238         } else {
2239                 nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
2240         }
2241         if (pNv->twoHeads)
2242                 nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->vtOWNER);
2243         NVVgaProtect(crtc, FALSE);
2244
2245         nv_crtc->last_dpms = NV_DPMS_CLEARED;
2246 }
2247
2248 static void
2249 NVResetCrtcConfig(xf86CrtcPtr crtc, Bool set)
2250 {
2251         ScrnInfoPtr pScrn = crtc->scrn;
2252         NVPtr pNv = NVPTR(pScrn);
2253
2254         if (pNv->twoHeads) {
2255                 uint32_t val = 0;
2256
2257                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2258
2259                 if (set) {
2260                         NVCrtcRegPtr regp;
2261
2262                         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2263                         val = regp->head;
2264                 }
2265
2266                 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL, val);
2267         }
2268 }
2269
2270 void nv_crtc_prepare(xf86CrtcPtr crtc)
2271 {
2272         ScrnInfoPtr pScrn = crtc->scrn;
2273         NVPtr pNv = NVPTR(pScrn);
2274         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2275
2276         ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->head);
2277
2278         /* Just in case */
2279         NVCrtcLockUnlock(crtc, 0);
2280
2281         NVResetCrtcConfig(crtc, FALSE);
2282
2283         crtc->funcs->dpms(crtc, DPMSModeOff);
2284
2285         /* Sync the engine before adjust mode */
2286         if (pNv->EXADriverPtr) {
2287                 exaMarkSync(pScrn->pScreen);
2288                 exaWaitSync(pScrn->pScreen);
2289         }
2290
2291         NVCrtcBlankScreen(crtc, FALSE); /* Blank screen */
2292
2293         /* Some more preperation. */
2294         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG, 0x1); /* Go to non-vga mode/out of enhanced mode */
2295         if (pNv->Architecture == NV_ARCH_40) {
2296                 uint32_t reg900 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900);
2297                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 & ~0x10000);
2298         }
2299 }
2300
2301 void nv_crtc_commit(xf86CrtcPtr crtc)
2302 {
2303         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2304         ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->head);
2305
2306         crtc->funcs->dpms (crtc, DPMSModeOn);
2307
2308         if (crtc->scrn->pScreen != NULL)
2309                 xf86_reload_cursors (crtc->scrn->pScreen);
2310
2311         NVResetCrtcConfig(crtc, TRUE);
2312 }
2313
2314 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
2315 {
2316         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2317         ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->head);
2318
2319         return FALSE;
2320 }
2321
2322 static void nv_crtc_unlock(xf86CrtcPtr crtc)
2323 {
2324         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2325         ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->head);
2326 }
2327
2328 static void
2329 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
2330                                         int size)
2331 {
2332         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2333         ScrnInfoPtr pScrn = crtc->scrn;
2334         NVPtr pNv = NVPTR(pScrn);
2335         int i, j;
2336
2337         NVCrtcRegPtr regp;
2338         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2339
2340         switch (pNv->CurrentLayout.depth) {
2341         case 15:
2342                 /* R5G5B5 */
2343                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
2344                 for (i = 0; i < 32; i++) {
2345                         for (j = 0; j < 8; j++) {
2346                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2347                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
2348                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2349                         }
2350                 }
2351                 break;
2352         case 16:
2353                 /* R5G6B5 */
2354                 /* First deal with the 5 bit colors */
2355                 for (i = 0; i < 32; i++) {
2356                         for (j = 0; j < 8; j++) {
2357                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2358                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2359                         }
2360                 }
2361                 /* Now deal with the 6 bit color */
2362                 for (i = 0; i < 64; i++) {
2363                         for (j = 0; j < 4; j++) {
2364                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
2365                         }
2366                 }
2367                 break;
2368         default:
2369                 /* R8G8B8 */
2370                 for (i = 0; i < 256; i++) {
2371                         regp->DAC[i * 3] = red[i] >> 8;
2372                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
2373                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
2374                 }
2375                 break;
2376         }
2377
2378         NVCrtcLoadPalette(crtc);
2379 }
2380
2381 /**
2382  * Allocates memory for a locked-in-framebuffer shadow of the given
2383  * width and height for this CRTC's rotated shadow framebuffer.
2384  */
2385
2386 static void *
2387 nv_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
2388 {
2389         ErrorF("nv_crtc_shadow_allocate is called\n");
2390         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2391         ScrnInfoPtr pScrn = crtc->scrn;
2392 #if !NOUVEAU_EXA_PIXMAPS
2393         ScreenPtr pScreen = pScrn->pScreen;
2394 #endif /* !NOUVEAU_EXA_PIXMAPS */
2395         NVPtr pNv = NVPTR(pScrn);
2396         void *offset;
2397
2398         unsigned long rotate_pitch;
2399         int size, align = 64;
2400
2401         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2402         size = rotate_pitch * height;
2403
2404         assert(nv_crtc->shadow == NULL);
2405 #if NOUVEAU_EXA_PIXMAPS
2406         if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN,
2407                         align, size, &nv_crtc->shadow)) {
2408                 ErrorF("Failed to allocate memory for shadow buffer!\n");
2409                 return NULL;
2410         }
2411
2412         if (nv_crtc->shadow && nouveau_bo_map(nv_crtc->shadow, NOUVEAU_BO_RDWR)) {
2413                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2414                                 "Failed to map shadow buffer.\n");
2415                 return NULL;
2416         }
2417
2418         offset = nv_crtc->shadow->map;
2419 #else
2420         nv_crtc->shadow = exaOffscreenAlloc(pScreen, size, align, TRUE, NULL, NULL);
2421         if (nv_crtc->shadow == NULL) {
2422                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2423                         "Couldn't allocate shadow memory for rotated CRTC\n");
2424                 return NULL;
2425         }
2426         offset = pNv->FB->map + nv_crtc->shadow->offset;
2427 #endif /* NOUVEAU_EXA_PIXMAPS */
2428
2429         return offset;
2430 }
2431
2432 /**
2433  * Creates a pixmap for this CRTC's rotated shadow framebuffer.
2434  */
2435 static PixmapPtr
2436 nv_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
2437 {
2438         ErrorF("nv_crtc_shadow_create is called\n");
2439         ScrnInfoPtr pScrn = crtc->scrn;
2440 #if NOUVEAU_EXA_PIXMAPS
2441         ScreenPtr pScreen = pScrn->pScreen;
2442         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2443 #endif /* NOUVEAU_EXA_PIXMAPS */
2444         unsigned long rotate_pitch;
2445         PixmapPtr rotate_pixmap;
2446 #if NOUVEAU_EXA_PIXMAPS
2447         struct nouveau_pixmap *nvpix;
2448 #endif /* NOUVEAU_EXA_PIXMAPS */
2449
2450         if (!data)
2451                 data = crtc->funcs->shadow_allocate (crtc, width, height);
2452
2453         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2454
2455 #if NOUVEAU_EXA_PIXMAPS
2456         /* Create a dummy pixmap, to get a private that will be accepted by the system.*/
2457         rotate_pixmap = pScreen->CreatePixmap(pScreen,
2458                                                                 0, /* width */
2459                                                                 0, /* height */
2460         #ifdef CREATE_PIXMAP_USAGE_SCRATCH /* there seems to have been no api bump */
2461                                                                 pScrn->depth,
2462                                                                 0);
2463         #else
2464                                                                 pScrn->depth);
2465         #endif /* CREATE_PIXMAP_USAGE_SCRATCH */
2466 #else
2467         rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen,
2468                                                                 width, height,
2469                                                                 pScrn->depth,
2470                                                                 pScrn->bitsPerPixel,
2471                                                                 rotate_pitch,
2472                                                                 data);
2473 #endif /* NOUVEAU_EXA_PIXMAPS */
2474
2475         if (rotate_pixmap == NULL) {
2476                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2477                         "Couldn't allocate shadow pixmap for rotated CRTC\n");
2478         }
2479
2480 #if NOUVEAU_EXA_PIXMAPS
2481         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2482         if (!nvpix) {
2483                 ErrorF("No shadow private, stage 1\n");
2484         } else {
2485                 nvpix->bo = nv_crtc->shadow;
2486                 nvpix->mapped = TRUE;
2487         }
2488
2489         /* Modify the pixmap to actually be the one we need. */
2490         pScreen->ModifyPixmapHeader(rotate_pixmap,
2491                                         width,
2492                                         height,
2493                                         pScrn->depth,
2494                                         pScrn->bitsPerPixel,
2495                                         rotate_pitch,
2496                                         data);
2497
2498         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2499         if (!nvpix || !nvpix->bo)
2500                 ErrorF("No shadow private, stage 2\n");
2501 #endif /* NOUVEAU_EXA_PIXMAPS */
2502
2503         return rotate_pixmap;
2504 }
2505
2506 static void
2507 nv_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
2508 {
2509         ErrorF("nv_crtc_shadow_destroy is called\n");
2510         ScrnInfoPtr pScrn = crtc->scrn;
2511         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2512         ScreenPtr pScreen = pScrn->pScreen;
2513
2514         if (rotate_pixmap) { /* This should also unmap the buffer object if relevant. */
2515                 pScreen->DestroyPixmap(rotate_pixmap);
2516         }
2517
2518 #if !NOUVEAU_EXA_PIXMAPS
2519         if (data && nv_crtc->shadow) {
2520                 exaOffscreenFree(pScreen, nv_crtc->shadow);
2521         }
2522 #endif /* !NOUVEAU_EXA_PIXMAPS */
2523
2524         nv_crtc->shadow = NULL;
2525 }
2526
2527 /* NV04-NV10 doesn't support alpha cursors */
2528 static const xf86CrtcFuncsRec nv_crtc_funcs = {
2529         .dpms = nv_crtc_dpms,
2530         .save = nv_crtc_save, /* XXX */
2531         .restore = nv_crtc_restore, /* XXX */
2532         .mode_fixup = nv_crtc_mode_fixup,
2533         .mode_set = nv_crtc_mode_set,
2534         .prepare = nv_crtc_prepare,
2535         .commit = nv_crtc_commit,
2536         .destroy = NULL, /* XXX */
2537         .lock = nv_crtc_lock,
2538         .unlock = nv_crtc_unlock,
2539         .set_cursor_colors = nv_crtc_set_cursor_colors,
2540         .set_cursor_position = nv_crtc_set_cursor_position,
2541         .show_cursor = nv_crtc_show_cursor,
2542         .hide_cursor = nv_crtc_hide_cursor,
2543         .load_cursor_image = nv_crtc_load_cursor_image,
2544         .gamma_set = nv_crtc_gamma_set,
2545         .shadow_create = nv_crtc_shadow_create,
2546         .shadow_allocate = nv_crtc_shadow_allocate,
2547         .shadow_destroy = nv_crtc_shadow_destroy,
2548 };
2549
2550 /* NV11 and up has support for alpha cursors. */
2551 /* Due to different maximum sizes we cannot allow it to use normal cursors */
2552 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
2553         .dpms = nv_crtc_dpms,
2554         .save = nv_crtc_save, /* XXX */
2555         .restore = nv_crtc_restore, /* XXX */
2556         .mode_fixup = nv_crtc_mode_fixup,
2557         .mode_set = nv_crtc_mode_set,
2558         .prepare = nv_crtc_prepare,
2559         .commit = nv_crtc_commit,
2560         .destroy = NULL, /* XXX */
2561         .lock = nv_crtc_lock,
2562         .unlock = nv_crtc_unlock,
2563         .set_cursor_colors = NULL, /* Alpha cursors do not need this */
2564         .set_cursor_position = nv_crtc_set_cursor_position,
2565         .show_cursor = nv_crtc_show_cursor,
2566         .hide_cursor = nv_crtc_hide_cursor,
2567         .load_cursor_argb = nv_crtc_load_cursor_argb,
2568         .gamma_set = nv_crtc_gamma_set,
2569         .shadow_create = nv_crtc_shadow_create,
2570         .shadow_allocate = nv_crtc_shadow_allocate,
2571         .shadow_destroy = nv_crtc_shadow_destroy,
2572 };
2573
2574
2575 void
2576 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
2577 {
2578         NVPtr pNv = NVPTR(pScrn);
2579         xf86CrtcPtr crtc;
2580         NVCrtcPrivatePtr nv_crtc;
2581
2582         if (pNv->NVArch >= 0x11) {
2583                 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
2584         } else {
2585                 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
2586         }
2587         if (crtc == NULL)
2588                 return;
2589
2590         nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
2591         nv_crtc->head = crtc_num;
2592         nv_crtc->last_dpms = NV_DPMS_CLEARED;
2593         pNv->fp_regs_owner[nv_crtc->head] = nv_crtc->head;
2594
2595         crtc->driver_private = nv_crtc;
2596
2597         NVCrtcLockUnlock(crtc, FALSE);
2598 }
2599
2600 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2601 {
2602         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2603         int i;
2604         NVCrtcRegPtr regp;
2605
2606         regp = &state->crtc_reg[nv_crtc->head];
2607
2608         NVWriteMiscOut(crtc, regp->MiscOutReg);
2609
2610         for (i = 1; i < 5; i++)
2611                 NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
2612
2613         /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
2614         NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
2615
2616         for (i = 0; i < 25; i++)
2617                 NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
2618
2619         for (i = 0; i < 9; i++)
2620                 NVWriteVgaGr(crtc, i, regp->Graphics[i]);
2621
2622         NVEnablePalette(crtc);
2623         for (i = 0; i < 21; i++)
2624                 NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
2625
2626         NVDisablePalette(crtc);
2627 }
2628
2629 static void nv_crtc_fix_nv40_hw_cursor(xf86CrtcPtr crtc)
2630 {
2631         /* TODO - implement this properly */
2632         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2633         ScrnInfoPtr pScrn = crtc->scrn;
2634         NVPtr pNv = NVPTR(pScrn);
2635
2636         if (pNv->Architecture == NV_ARCH_40) {  /* HW bug */
2637                 volatile uint32_t curpos = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS);
2638                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS, curpos);
2639         }
2640 }
2641 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override)
2642 {
2643         ScrnInfoPtr pScrn = crtc->scrn;
2644         NVPtr pNv = NVPTR(pScrn);
2645         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2646         NVCrtcRegPtr regp;
2647         int i;
2648
2649         regp = &state->crtc_reg[nv_crtc->head];
2650
2651         if (pNv->Architecture >= NV_ARCH_10) {
2652                 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
2653                 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
2654                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
2655                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
2656                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2657                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2658                 nvWriteMC(pNv, 0x1588, 0);
2659
2660                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
2661                 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
2662                 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0830, regp->unk830);
2663                 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0834, regp->unk834);
2664                 if (pNv->Architecture == NV_ARCH_40) {
2665                         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0850, regp->unk850);
2666                         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_081C, regp->unk81c);
2667                 }
2668
2669                 if (pNv->Architecture == NV_ARCH_40) {
2670                         uint32_t reg900 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900);
2671                         if (regp->config == 0x2) { /* enhanced "horizontal only" non-vga mode */
2672                                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 | 0x10000);
2673                         } else {
2674                                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 & ~0x10000);
2675                         }
2676                 }
2677         }
2678
2679         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG, regp->config);
2680         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO, regp->gpio);
2681
2682         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
2683         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
2684         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
2685         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
2686         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
2687         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
2688         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
2689         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
2690         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
2691         if (pNv->Architecture >= NV_ARCH_30)
2692                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
2693
2694         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
2695         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
2696         nv_crtc_fix_nv40_hw_cursor(crtc);
2697         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
2698         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
2699
2700         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
2701         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
2702         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3C, regp->CRTC[NV_VGA_CRTCX_3C]);
2703         if (pNv->Architecture >= NV_ARCH_10) {
2704                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
2705                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_43, regp->CRTC[NV_VGA_CRTCX_43]);
2706                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
2707                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_4B, regp->CRTC[NV_VGA_CRTCX_4B]);
2708                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
2709         }
2710         /* NV11 and NV20 stop at 0x52. */
2711         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
2712                 if (override)
2713                         for (i = 0; i < 0x10; i++)
2714                                 NVWriteVGACR5758(pNv, nv_crtc->head, i, regp->CR58[i]);
2715
2716                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
2717                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
2718
2719                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
2720
2721                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_85, regp->CRTC[NV_VGA_CRTCX_85]);
2722                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_86, regp->CRTC[NV_VGA_CRTCX_86]);
2723         }
2724
2725         /* Setting 1 on this value gives you interrupts for every vblank period. */
2726         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_EN_0, 0);
2727         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
2728
2729         pNv->CurrentState = state;
2730 }
2731
2732 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2733 {
2734         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2735         int i;
2736         NVCrtcRegPtr regp;
2737
2738         regp = &state->crtc_reg[nv_crtc->head];
2739
2740         regp->MiscOutReg = NVReadMiscOut(crtc);
2741
2742         for (i = 0; i < 25; i++)
2743                 regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
2744
2745         NVEnablePalette(crtc);
2746         for (i = 0; i < 21; i++)
2747                 regp->Attribute[i] = NVReadVgaAttr(crtc, i);
2748         NVDisablePalette(crtc);
2749
2750         for (i = 0; i < 9; i++)
2751                 regp->Graphics[i] = NVReadVgaGr(crtc, i);
2752
2753         for (i = 1; i < 5; i++)
2754                 regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
2755 }
2756
2757 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2758 {
2759         ScrnInfoPtr pScrn = crtc->scrn;
2760         NVPtr pNv = NVPTR(pScrn);
2761         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2762         NVCrtcRegPtr regp;
2763         int i;
2764
2765         regp = &state->crtc_reg[nv_crtc->head];
2766
2767         regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
2768         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
2769         regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
2770         regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
2771         regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
2772         regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
2773         regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
2774
2775         regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
2776         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
2777         regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
2778         if (pNv->Architecture >= NV_ARCH_30)
2779                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
2780         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
2781         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
2782         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
2783         regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
2784
2785         if (pNv->Architecture >= NV_ARCH_10) {
2786                 regp->unk830 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0830);
2787                 regp->unk834 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0834);
2788                 if (pNv->Architecture == NV_ARCH_40) {
2789                         regp->unk850 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0850);
2790                         regp->unk81c = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_081C);
2791                 }
2792                 if (pNv->twoHeads) {
2793                         regp->head = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL);
2794                         regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
2795                 }
2796                 regp->cursorConfig = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG);
2797         }
2798
2799         regp->gpio = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO);
2800         regp->config = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG);
2801
2802         regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
2803         regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
2804         regp->CRTC[NV_VGA_CRTCX_3C] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3C);
2805         if (pNv->Architecture >= NV_ARCH_10) {
2806                 regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
2807                 regp->CRTC[NV_VGA_CRTCX_43] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_43);
2808                 regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
2809                 regp->CRTC[NV_VGA_CRTCX_4B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_4B);
2810                 regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
2811         }
2812         /* NV11 and NV20 don't have this, they stop at 0x52. */
2813         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
2814                 for (i = 0; i < 0x10; i++)
2815                         regp->CR58[i] = NVReadVGACR5758(pNv, nv_crtc->head, i);
2816
2817                 regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
2818                 regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
2819                 regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
2820
2821                 regp->CRTC[NV_VGA_CRTCX_85] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_85);
2822                 regp->CRTC[NV_VGA_CRTCX_86] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_86);
2823         }
2824 }
2825
2826 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2827 {
2828         ScrnInfoPtr pScrn = crtc->scrn;
2829         NVPtr pNv = NVPTR(pScrn);
2830         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2831         NVCrtcRegPtr regp;
2832         int i;
2833
2834         regp = &state->crtc_reg[nv_crtc->head];
2835
2836         regp->general = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL);
2837
2838         regp->fp_control[0]     = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL);
2839         regp->debug_0[0]        = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
2840
2841         if (pNv->twoHeads) {
2842                 regp->fp_control[1]     = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_CONTROL);
2843                 regp->debug_0[1]        = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
2844
2845                 regp->debug_1   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1);
2846                 regp->debug_2   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2);
2847
2848                 regp->unk_a20 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20);
2849                 regp->unk_a24 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24);
2850                 regp->unk_a34 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34);
2851         }
2852
2853         if (pNv->NVArch == 0x11) {
2854                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11);
2855         } else if (pNv->twoHeads) {
2856                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER);
2857         }
2858         if (pNv->Architecture >= NV_ARCH_10)
2859                 regp->nv10_cursync = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC);
2860
2861         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2862
2863         for (i = 0; i < 7; i++) {
2864                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2865                 regp->fp_horiz_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2866         }
2867
2868         for (i = 0; i < 7; i++) {
2869                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2870                 regp->fp_vert_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2871         }
2872
2873         regp->fp_hvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START);
2874         regp->fp_hvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END);
2875         regp->fp_vvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START);
2876         regp->fp_vvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END);
2877 }
2878
2879 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2880 {
2881         ScrnInfoPtr pScrn = crtc->scrn;
2882         NVPtr pNv = NVPTR(pScrn);
2883         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2884         NVCrtcRegPtr regp;
2885         int i;
2886
2887         regp = &state->crtc_reg[nv_crtc->head];
2888
2889         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL, regp->general);
2890
2891         if (pNv->fp_regs_owner[0] == nv_crtc->head) {
2892                 nvWriteRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL, regp->fp_control[0]);
2893                 nvWriteRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0, regp->debug_0[0]);
2894         }
2895         if (pNv->twoHeads) {
2896                 if (pNv->fp_regs_owner[1] == nv_crtc->head) {
2897                         nvWriteRAMDAC(pNv, 1, NV_RAMDAC_FP_CONTROL, regp->fp_control[1]);
2898                         nvWriteRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0, regp->debug_0[1]);
2899                 }
2900                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
2901                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
2902                 if (pNv->NVArch == 0x30) { /* For unknown purposes. */
2903                         uint32_t reg890 = nvReadRAMDAC(pNv, nv_crtc->head, NV30_RAMDAC_890);
2904                         nvWriteRAMDAC(pNv, nv_crtc->head, NV30_RAMDAC_89C, reg890);
2905                 }
2906
2907                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20, regp->unk_a20);
2908                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24, regp->unk_a24);
2909                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34, regp->unk_a34);
2910         }
2911
2912         if (pNv->NVArch == 0x11) {
2913                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11, regp->dither);
2914         } else if (pNv->twoHeads) {
2915                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER, regp->dither);
2916         }
2917         if (pNv->Architecture >= NV_ARCH_10)
2918                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
2919
2920         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2921
2922         for (i = 0; i < 7; i++) {
2923                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2924                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_horiz_regs[i]);
2925         }
2926
2927         for (i = 0; i < 7; i++) {
2928                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2929                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_vert_regs[i]);
2930         }
2931
2932         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START, regp->fp_hvalid_start);
2933         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END, regp->fp_hvalid_end);
2934         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START, regp->fp_vvalid_start);
2935         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END, regp->fp_vvalid_end);
2936 }
2937
2938 void
2939 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y, Bool bios_restore)
2940 {
2941         ScrnInfoPtr pScrn = crtc->scrn;
2942         NVPtr pNv = NVPTR(pScrn);
2943         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2944         NVFBLayout *pLayout = &pNv->CurrentLayout;
2945         uint32_t start = 0;
2946
2947         ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
2948
2949         if (bios_restore) {
2950                 start = pNv->console_mode[nv_crtc->head].fb_start;
2951         } else {
2952                 start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
2953                 if (crtc->rotatedData != NULL) { /* we do not exist on the real framebuffer */
2954 #if NOUVEAU_EXA_PIXMAPS
2955                         start = nv_crtc->shadow->offset;
2956 #else
2957                         start = pNv->FB->offset + nv_crtc->shadow->offset; /* We do exist relative to the framebuffer */
2958 #endif
2959                 } else {
2960                         start += pNv->FB->offset;
2961                 }
2962         }
2963
2964         /* 30 bits addresses in 32 bits according to haiku */
2965         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_START, start & 0xfffffffc);
2966
2967         /* set NV4/NV10 byte adress: (bit0 - 1) */
2968         NVWriteVgaAttr(crtc, 0x13, (start & 0x3) << 1);
2969
2970         crtc->x = x;
2971         crtc->y = y;
2972 }
2973
2974 static void NVCrtcWriteDacMask(xf86CrtcPtr crtc, uint8_t value)
2975 {
2976         ScrnInfoPtr pScrn = crtc->scrn;
2977         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2978         NVPtr pNv = NVPTR(pScrn);
2979         volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2980
2981         DDXMMIOH("NVCrtcWriteDacMask: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_MASK, value);
2982         NV_WR08(pDACReg, VGA_DAC_MASK, value);
2983 }
2984
2985 static uint8_t NVCrtcReadDacMask(xf86CrtcPtr crtc)
2986 {
2987         ScrnInfoPtr pScrn = crtc->scrn;
2988         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2989         NVPtr pNv = NVPTR(pScrn);
2990         volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2991
2992         DDXMMIOH("NVCrtcReadDacMask: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_MASK, NV_RD08(pDACReg, VGA_DAC_MASK));
2993         return NV_RD08(pDACReg, VGA_DAC_MASK);
2994 }
2995
2996 static void NVCrtcWriteDacReadAddr(xf86CrtcPtr crtc, uint8_t value)
2997 {
2998         ScrnInfoPtr pScrn = crtc->scrn;
2999         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3000         NVPtr pNv = NVPTR(pScrn);
3001         volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3002
3003         DDXMMIOH("NVCrtcWriteDacReadAddr: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_READ_ADDR, value);
3004         NV_WR08(pDACReg, VGA_DAC_READ_ADDR, value);
3005 }
3006
3007 static void NVCrtcWriteDacWriteAddr(xf86CrtcPtr crtc, uint8_t value)
3008 {
3009         ScrnInfoPtr pScrn = crtc->scrn;
3010         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3011         NVPtr pNv = NVPTR(pScrn);
3012         volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3013
3014         DDXMMIOH("NVCrtcWriteDacWriteAddr: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_WRITE_ADDR, value);
3015         NV_WR08(pDACReg, VGA_DAC_WRITE_ADDR, value);
3016 }
3017
3018 static void NVCrtcWriteDacData(xf86CrtcPtr crtc, uint8_t value)
3019 {
3020         ScrnInfoPtr pScrn = crtc->scrn;
3021         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3022         NVPtr pNv = NVPTR(pScrn);
3023         volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3024
3025         DDXMMIOH("NVCrtcWriteDacData: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_DATA, value);
3026         NV_WR08(pDACReg, VGA_DAC_DATA, value);
3027 }
3028
3029 static uint8_t NVCrtcReadDacData(xf86CrtcPtr crtc, uint8_t value)
3030 {
3031         ScrnInfoPtr pScrn = crtc->scrn;
3032         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3033         NVPtr pNv = NVPTR(pScrn);
3034         volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3035
3036         DDXMMIOH("NVCrtcReadDacData: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_DATA, NV_RD08(pDACReg, VGA_DAC_DATA));
3037         return NV_RD08(pDACReg, VGA_DAC_DATA);
3038 }
3039
3040 void NVCrtcLoadPalette(xf86CrtcPtr crtc)
3041 {
3042         int i;
3043         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3044         NVCrtcRegPtr regp;
3045         ScrnInfoPtr pScrn = crtc->scrn;
3046         NVPtr pNv = NVPTR(pScrn);
3047
3048         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
3049
3050         if (pNv->twoHeads)
3051                 NVCrtcSetOwner(crtc);
3052         NVCrtcWriteDacMask(crtc, 0xff);
3053         NVCrtcWriteDacWriteAddr(crtc, 0x00);
3054
3055         for (i = 0; i<768; i++) {
3056                 NVCrtcWriteDacData(crtc, regp->DAC[i]);
3057         }
3058         NVDisablePalette(crtc);
3059 }
3060
3061 /* on = unblank */
3062 void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
3063 {
3064         NVPtr pNv = NVPTR(crtc->scrn);
3065         unsigned char scrn;
3066
3067         if (pNv->twoHeads)
3068                 NVCrtcSetOwner(crtc);
3069
3070         scrn = NVReadVgaSeq(crtc, 0x01);
3071         if (on) {
3072                 scrn &= ~0x20;
3073         } else {
3074                 scrn |= 0x20;
3075         }
3076
3077         NVVgaSeqReset(crtc, TRUE);
3078         NVWriteVgaSeq(crtc, 0x01, scrn);
3079         NVVgaSeqReset(crtc, FALSE);
3080 }
3081
3082 /* Reset a mode after a drastic output resource change for example. */
3083 void NVCrtcModeFix(xf86CrtcPtr crtc)
3084 {
3085         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3086         Bool need_unlock;
3087
3088         if (!crtc->enabled)
3089                 return;
3090
3091         if (!xf86ModesEqual(&crtc->mode, &crtc->desiredMode)) /* not currently in X */
3092                 return;
3093
3094         DisplayModePtr adjusted_mode = xf86DuplicateMode(&crtc->mode);
3095         uint8_t dpms_mode = nv_crtc->last_dpms;
3096
3097         /* Set the crtc mode again. */
3098         crtc->funcs->dpms(crtc, DPMSModeOff);
3099         need_unlock = crtc->funcs->lock(crtc);
3100         crtc->funcs->mode_fixup(crtc, &crtc->mode, adjusted_mode);
3101         crtc->funcs->prepare(crtc);
3102         crtc->funcs->mode_set(crtc, &crtc->mode, adjusted_mode, crtc->x, crtc->y);
3103         crtc->funcs->commit(crtc);
3104         if (need_unlock)
3105                 crtc->funcs->unlock(crtc);
3106         crtc->funcs->dpms(crtc, dpms_mode);
3107
3108         /* Free mode. */
3109         xfree(adjusted_mode);
3110 }
3111
3112 /*************************************************************************** \
3113 |*                                                                           *|
3114 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
3115 |*                                                                           *|
3116 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
3117 |*     international laws.  Users and possessors of this source code are     *|
3118 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
3119 |*     use this code in individual and commercial software.                  *|
3120 |*                                                                           *|
3121 |*     Any use of this source code must include,  in the user documenta-     *|
3122 |*     tion and  internal comments to the code,  notices to the end user     *|
3123 |*     as follows:                                                           *|
3124 |*                                                                           *|
3125 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
3126 |*                                                                           *|
3127 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
3128 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
3129 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
3130 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
3131 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
3132 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
3133 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
3134 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
3135 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
3136 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
3137 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
3138 |*                                                                           *|
3139 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
3140 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
3141 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
3142 |*     computer  software  documentation,"  as such  terms  are  used in     *|
3143 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
3144 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
3145 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
3146 |*     all U.S. Government End Users  acquire the source code  with only     *|
3147 |*     those rights set forth herein.                                        *|
3148 |*                                                                           *|
3149  \***************************************************************************/