2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
19 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
20 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include "nv_include.h"
28 /* FIXME: put these somewhere */
29 #define CRTC_INDEX_COLOR (VGA_IOBASE_COLOR + VGA_CRTC_INDEX_OFFSET)
30 #define NV_VGA_CRTCX_OWNER_HEADA 0x0
31 #define NV_VGA_CRTCX_OWNER_HEADB 0x3
32 #define NV_PBUS_PCI_NV_19 0x0000184C
33 #define NV_PBUS_PCI_NV_20 0x00001850
34 #define NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED 0x00000000
35 #define NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED 0x00000001
36 #define NV_PEXTDEV_BOOT_0 0x00101000
37 /* undef, as we want the +0x00100000 version */
39 #define NV_PFB_CFG0 0x00100200
40 #define NV_PFB_REFCTRL 0x00100210
41 #define NV_PFB_REFCTRL_VALID_1 0x80000000
42 #define NV_PRAMIN_ROM_OFFSET 0x00700000
50 static int crtchead = 0;
52 /* this will need remembering across a suspend */
53 static uint32_t saved_nv_pfb_cfg0;
60 static uint16_t le16_to_cpu(const uint16_t x)
62 #if X_BYTE_ORDER == X_BIG_ENDIAN
69 static uint32_t le32_to_cpu(const uint32_t x)
71 #if X_BYTE_ORDER == X_BIG_ENDIAN
78 static Bool nv_cksum(const uint8_t *data, unsigned int length)
80 /* there's a few checksums in the BIOS, so here's a generic checking function */
84 for (i = 0; i < length; i++)
93 static int NVValidVBIOS(ScrnInfoPtr pScrn, const uint8_t *data)
95 /* check for BIOS signature */
96 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
97 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
98 "... BIOS signature not found\n");
102 if (nv_cksum(data, data[2] * 512)) {
103 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
104 "... BIOS checksum invalid\n");
105 /* probably ought to set a do_not_execute flag for table parsing here,
106 * assuming most BIOSen are valid */
109 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "... appears to be valid\n");
114 static void NVShadowVBIOS_PROM(ScrnInfoPtr pScrn, uint8_t *data)
116 NVPtr pNv = NVPTR(pScrn);
119 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
120 "Attempting to locate BIOS image in PROM\n");
122 /* enable ROM access */
123 nvWriteMC(pNv, NV_PBUS_PCI_NV_20, NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED);
124 for (i = 0; i < NV_PROM_SIZE; i++) {
125 /* according to nvclock, we need that to work around a 6600GT/6800LE bug */
126 data[i] = pNv->PROM[i];
127 data[i] = pNv->PROM[i];
128 data[i] = pNv->PROM[i];
129 data[i] = pNv->PROM[i];
130 data[i] = pNv->PROM[i];
132 /* disable ROM access */
133 nvWriteMC(pNv, NV_PBUS_PCI_NV_20, NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
136 static void NVShadowVBIOS_PRAMIN(ScrnInfoPtr pScrn, uint32_t *data)
138 NVPtr pNv = NVPTR(pScrn);
139 const uint32_t *pramin = (uint32_t *)&pNv->REGS[NV_PRAMIN_ROM_OFFSET/4];
140 uint32_t old_bar0_pramin = 0;
142 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
143 "Attempting to locate BIOS image in PRAMIN\n");
145 if (pNv->Architecture >= NV_ARCH_50) {
148 vbios_vram = (pNv->REGS[0x619f04/4] & ~0xff) << 8;
150 vbios_vram = pNv->REGS[0x1700/4] << 16;
151 vbios_vram += 0xf0000;
154 old_bar0_pramin = pNv->REGS[0x1700/4];
155 pNv->REGS[0x1700/4] = vbios_vram >> 16;
158 memcpy(data, pramin, NV_PROM_SIZE);
160 if (pNv->Architecture >= NV_ARCH_50) {
161 pNv->REGS[0x1700/4] = old_bar0_pramin;
165 static void NVVBIOS_PCIROM(ScrnInfoPtr pScrn, uint8_t *data)
167 NVPtr pNv = NVPTR(pScrn);
169 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
170 "Attempting to use PCI ROM BIOS image\n");
172 #if XSERVER_LIBPCIACCESS
173 pci_device_read_rom(pNv->PciInfo, data);
175 xf86ReadPciBIOS(0, pNv->PciTag, 0, data, NV_PROM_SIZE);
179 static Bool NVShadowVBIOS(ScrnInfoPtr pScrn, uint8_t *data)
181 NVShadowVBIOS_PROM(pScrn, data);
182 if (NVValidVBIOS(pScrn, data) == 2)
185 NVShadowVBIOS_PRAMIN(pScrn, (uint32_t *)data);
186 if (NVValidVBIOS(pScrn, data))
190 NVVBIOS_PCIROM(pScrn, data);
191 if (NVValidVBIOS(pScrn, data))
203 int length_multiplier;
204 Bool (*handler)(ScrnInfoPtr pScrn, bios_t *, uint16_t, init_exec_t *);
213 static void parse_init_table(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset, init_exec_t *iexec);
215 #define MACRO_INDEX_SIZE 2
217 #define CONDITION_SIZE 12
218 #define IO_FLAG_CONDITION_SIZE 9
226 static int nv_valid_reg(NVPtr pNv, uint32_t reg)
228 /* C51 has misaligned regs on purpose. Marvellous */
229 if ((reg & 0x3 && pNv->VBIOS.chip_version != 0x51) ||
230 (reg & 0x2 && pNv->VBIOS.chip_version == 0x51)) {
231 ErrorF("========== misaligned reg 0x%08X ==========\n", reg);
235 #define WITHIN(x,y,z) ((x>=y)&&(x<y+z))
236 if (WITHIN(reg,NV_PRAMIN_OFFSET,NV_PRAMIN_SIZE))
238 if (WITHIN(reg,NV_PCRTC0_OFFSET,NV_PCRTC0_SIZE))
240 if (WITHIN(reg,NV_PRAMDAC0_OFFSET,NV_PRAMDAC0_SIZE))
242 if (WITHIN(reg,NV_PFB_OFFSET,NV_PFB_SIZE))
244 if (WITHIN(reg,NV_PFIFO_OFFSET,NV_PFIFO_SIZE))
246 if (WITHIN(reg,NV_PGRAPH_OFFSET,NV_PGRAPH_SIZE))
248 if (WITHIN(reg,NV_PEXTDEV_OFFSET,NV_PEXTDEV_SIZE))
250 if (WITHIN(reg,NV_PTIMER_OFFSET,NV_PTIMER_SIZE))
252 if (WITHIN(reg,NV_PVIDEO_OFFSET,NV_PVIDEO_SIZE))
254 if (WITHIN(reg,NV_PMC_OFFSET,NV_PMC_SIZE))
256 if (WITHIN(reg,NV_FIFO_OFFSET,NV_FIFO_SIZE))
258 if (WITHIN(reg,NV_PCIO0_OFFSET,NV_PCIO0_SIZE))
260 if (WITHIN(reg,NV_PDIO0_OFFSET,NV_PDIO0_SIZE))
262 if (WITHIN(reg,NV_PVIO_OFFSET,NV_PVIO_SIZE))
264 if (WITHIN(reg,NV_PROM_OFFSET,NV_PROM_SIZE))
266 if (WITHIN(reg,NV_PRAMIN_ROM_OFFSET,NV_PROM_SIZE))
269 if (WITHIN(reg,0x88000,0x1000))
273 ErrorF("========== unknown reg 0x%08X ==========\n", reg);
278 static uint32_t nv32_rd(ScrnInfoPtr pScrn, uint32_t reg)
280 NVPtr pNv = NVPTR(pScrn);
283 if (!nv_valid_reg(pNv, reg))
286 /* C51 sometimes uses regs with bit0 set in the address. For these
287 * cases there should exist a translation in a BIOS table to an IO
288 * port address which the BIOS uses for accessing the reg
290 * These only seem to appear for the power control regs to a flat panel
291 * and in C51 mmio traces the normal regs for 0x1308 and 0x1310 are
292 * used - hence the mask below. An S3 suspend-resume mmio trace from a
293 * C51 will be required to see if this is true for the power microcode
294 * in 0x14.., or whether the direct IO port access method is needed
299 data = pNv->REGS[reg/4];
302 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
303 " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
308 static int nv32_wr(ScrnInfoPtr pScrn, uint32_t reg, uint32_t data)
310 NVPtr pNv = NVPTR(pScrn);
312 if (!nv_valid_reg(pNv, reg))
315 /* see note in nv32_rd */
322 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
323 " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
325 if (pNv->VBIOS.execute) {
327 pNv->REGS[reg/4] = data;
333 static uint8_t nv_idx_port_rd(ScrnInfoPtr pScrn, uint16_t port, uint8_t index)
335 NVPtr pNv = NVPTR(pScrn);
336 volatile uint8_t *ptr = crtchead ? pNv->PCIO1 : pNv->PCIO0;
339 VGA_WR08(ptr, port, index);
340 data = VGA_RD08(ptr, port + 1);
343 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
344 " Indexed read: Port: 0x%04X, Index: 0x%02X, Head: 0x%02X, Data: 0x%02X\n",
345 port, index, crtchead, data);
350 static void nv_idx_port_wr(ScrnInfoPtr pScrn, uint16_t port, uint8_t index, uint8_t data)
352 NVPtr pNv = NVPTR(pScrn);
353 volatile uint8_t *ptr;
355 /* The current head is maintained in a file scope variable crtchead.
356 * We trap changes to CRTCX_OWNER and update the head variable
357 * and hence the register set written.
358 * As CRTCX_OWNER only exists on CRTC0, we update crtchead to head0
359 * in advance of the write, and to head1 after the write
361 if (port == CRTC_INDEX_COLOR && index == NV_VGA_CRTCX_OWNER && data != NV_VGA_CRTCX_OWNER_HEADB)
363 ptr = crtchead ? pNv->PCIO1 : pNv->PCIO0;
366 nv_idx_port_rd(pScrn, port, index);
368 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
369 " Indexed write: Port: 0x%04X, Index: 0x%02X, Head: 0x%02X, Data: 0x%02X\n",
370 port, index, crtchead, data);
372 if (pNv->VBIOS.execute) {
374 VGA_WR08(ptr, port, index);
375 VGA_WR08(ptr, port + 1, data);
378 if (port == CRTC_INDEX_COLOR && index == NV_VGA_CRTCX_OWNER && data == NV_VGA_CRTCX_OWNER_HEADB)
382 #define ACCESS_UNLOCK 0
383 #define ACCESS_LOCK 1
384 static void crtc_access(ScrnInfoPtr pScrn, Bool lock)
386 NVPtr pNv = NVPTR(pScrn);
387 int savedhead = crtchead;
390 /* necessary external dependancy (twoHeads) */
392 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_OWNER, NV_VGA_CRTCX_OWNER_HEADA);
393 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_LOCK, lock ? 0x99 : 0x57);
394 cr11 = nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_VSYNCE);
395 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_VSYNCE, lock ? cr11 | 0x80 : cr11 & ~0x80);
398 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_OWNER, NV_VGA_CRTCX_OWNER_HEADB);
399 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_LOCK, lock ? 0x99 : 0x57);
400 cr11 = nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_VSYNCE);
401 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_VSYNCE, lock ? cr11 | 0x80 : cr11 & ~0x80);
404 crtchead = savedhead;
407 static Bool io_flag_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, uint8_t cond)
409 /* The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
410 * for the CRTC index; 1 byte for the mask to apply to the value
411 * retrieved from the CRTC; 1 byte for the shift right to apply to the
412 * masked CRTC value; 2 bytes for the offset to the flag array, to
413 * which the shifted value is added; 1 byte for the mask applied to the
414 * value read from the flag array; and 1 byte for the value to compare
415 * against the masked byte from the flag table.
418 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
419 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[condptr])));
420 uint8_t crtcindex = bios->data[condptr + 2];
421 uint8_t mask = bios->data[condptr + 3];
422 uint8_t shift = bios->data[condptr + 4];
423 uint16_t flagarray = le16_to_cpu(*((uint16_t *)(&bios->data[condptr + 5])));
424 uint8_t flagarraymask = bios->data[condptr + 7];
425 uint8_t cmpval = bios->data[condptr + 8];
429 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
430 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, Cmpval: 0x%02X\n",
431 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
433 data = nv_idx_port_rd(pScrn, crtcport, crtcindex);
435 data = bios->data[flagarray + ((data & mask) >> shift)];
436 data &= flagarraymask;
439 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
440 "0x%04X: Checking if 0x%02X equals 0x%02X\n",
441 offset, data, cmpval);
449 uint32_t getMNP_single(ScrnInfoPtr pScrn, uint32_t clk, int *bestNM, int *bestlog2P)
451 /* Find M, N and P for a single stage PLL
453 * Note that some bioses (NV3x) have lookup tables of precomputed MNP
454 * values, but we're too lazy to use those atm
456 * "clk" parameter in kHz
457 * returns calculated clock
460 bios_t *bios = &NVPTR(pScrn)->VBIOS;
462 int maxlog2P, log2P, P;
464 uint32_t minvco = bios->fminvco;
465 uint32_t maxvco = bios->fmaxvco;
468 unsigned int bestdelta = UINT_MAX;
469 uint32_t bestclk = 0;
471 unsigned int crystal_strap_mask = 1 << 6;
472 /* open coded pNv->twoHeads test */
473 if (bios->chip_version > 0x10 && bios->chip_version != 0x15 &&
474 bios->chip_version != 0x1a && bios->chip_version != 0x20)
475 crystal_strap_mask |= 1 << 22;
476 switch (nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) & crystal_strap_mask) {
486 case (1 << 22 | 1 << 6):
492 /* this division verified for nv20, nv28 (Haiku), nv34 -- nv17 is guessed */
493 /* possibly correlated with introduction of 27MHz crystal */
494 if (bios->chip_version <= 0x16 || bios->chip_version == 0x20) {
510 if ((clk << maxlog2P) < minvco) {
511 minvco = clk << maxlog2P;
514 if (clk + clk/200 > maxvco) /* +0.5% */
515 maxvco = clk + clk/200;
517 /* NV34 goes maxlog2P->0, NV20 goes 0->maxlog2P */
518 for (log2P = 0; log2P <= maxlog2P; log2P++) {
526 /* nv_hw.c in nv driver uses 7 and 8 for minM */
527 for (M = 1; M <= maxM; M++) {
528 /* add crystal/2 to round better */
529 N = (clkP * M + crystal/2) / crystal;
530 if (N > 256) /* we lost */
533 /* more rounding additions */
534 calcclk = ((N * crystal + P/2) / P + M/2) / M;
535 delta = abs(calcclk - clk);
536 /* we do an exhaustive search rather than terminating
537 * on an optimality condition...
539 if (delta < bestdelta) {
542 *bestNM = N << 8 | M;
544 if (delta == 0) /* except this one */
555 Bool get_pll_limits(ScrnInfoPtr pScrn, uint32_t reg, struct pll_lims *pll_lim);
557 int getMNP_double(ScrnInfoPtr pScrn, uint32_t reg, int clk, int *bestNM1, int *bestNM2, int *bestlog2P)
559 /* Find M, N and P for a two stage PLL
561 * Note that some bioses (NV30+) have lookup tables of precomputed MNP
562 * values, but we're too lazy to use those atm
564 * "clk" parameter in kHz
565 * returns calculated clock
568 struct pll_lims pll_lim;
570 if (!get_pll_limits(pScrn, reg, &pll_lim))
573 int minvco1 = pll_lim.vco1.minfreq, maxvco1 = pll_lim.vco1.maxfreq;
574 int minvco2 = pll_lim.vco2.minfreq, maxvco2 = pll_lim.vco2.maxfreq;
575 int minU1 = pll_lim.vco1.min_inputfreq, minU2 = pll_lim.vco2.min_inputfreq;
576 int maxU1 = pll_lim.vco1.max_inputfreq, maxU2 = pll_lim.vco2.max_inputfreq;
577 int minM1 = pll_lim.vco1.min_m, maxM1 = pll_lim.vco1.max_m;
578 int minN1 = pll_lim.vco1.min_n, maxN1 = pll_lim.vco1.max_n;
579 int minM2 = pll_lim.vco2.min_m, maxM2 = pll_lim.vco2.max_m;
580 int minN2 = pll_lim.vco2.min_n, maxN2 = pll_lim.vco2.max_n;
582 int M1, N1, M2, N2, log2P;
583 int clkP, calcclk1, calcclk2, calcclkout;
584 int delta, bestdelta = INT_MAX;
588 crystal = pll_lim.refclk;
590 switch (nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) & (1 << 22 | 1 << 6)) {
600 case (1 << 22 | 1 << 6):
605 int vco2 = (maxvco2 - maxvco2/200) / 2;
606 for (log2P = 0; log2P < 6 && clk <= (vco2 >> log2P); log2P++) /* log2P is maximum of 6 */
610 if (maxvco2 < clk + clk/200) /* +0.5% */
611 maxvco2 = clk + clk/200;
613 for (M1 = minM1; M1 <= maxM1; M1++) {
614 if (crystal/M1 < minU1)
616 if (crystal/M1 > maxU1)
619 for (N1 = minN1; N1 <= maxN1; N1++) {
620 calcclk1 = crystal * N1 / M1;
621 if (calcclk1 < minvco1)
623 if (calcclk1 > maxvco1)
626 for (M2 = minM2; M2 <= maxM2; M2++) {
627 if (calcclk1/M2 < minU2)
629 if (calcclk1/M2 > maxU2)
632 /* add calcclk1/2 to round better */
633 N2 = (clkP * M2 + calcclk1/2) / calcclk1;
639 if (N2/M2 < 4 || N2/M2 > 10)
642 calcclk2 = calcclk1 * N2 / M2;
643 if (calcclk2 < minvco2)
645 if (calcclk2 > maxvco2)
648 calcclkout = calcclk2 >> log2P;
649 delta = abs(calcclkout - clk);
650 /* we do an exhaustive search rather than terminating
651 * on an optimality condition...
653 if (delta < bestdelta) {
655 bestclk = calcclkout;
656 *bestNM1 = N1 << 8 | M1;
657 *bestNM2 = N2 << 8 | M2;
659 if (delta == 0) /* except this one */
669 static void setPLL_single(ScrnInfoPtr pScrn, uint32_t reg, int NM, int log2P)
673 pll = nv32_rd(pScrn, reg);
674 if (pll == (log2P << 16 | NM))
675 return; /* already set */
678 //this stuff is present on my nv34 and something similar on the nv31
679 //it is not on nv20, and I don't know how useful or necessary it is
681 uint32_t saved_1584, shift_1584;
682 Bool frob1584 = FALSE;
703 saved_1584 = nv32_rd(pScrn, 0x00001584);
704 nv32_wr(pScrn, 0x00001584, (saved_1584 & ~(0xf << shift_1584)) | 1 << shift_1584);
709 pll = (pll & 0xffff0000) | NM;
710 nv32_wr(pScrn, reg, pll);
716 /* then write P as well */
717 nv32_wr(pScrn, reg, (pll & 0xfff8ffff) | log2P << 16);
721 nv32_wr(pScrn, 0x00001584, saved_1584);
725 static void setPLL_double_highregs(ScrnInfoPtr pScrn, uint32_t reg1, int NM1, int NM2, int log2P)
727 bios_t *bios = &NVPTR(pScrn)->VBIOS;
728 uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70);
729 uint32_t oldpll1 = nv32_rd(pScrn, reg1), oldpll2 = nv32_rd(pScrn, reg2);
730 uint32_t pll1 = (oldpll1 & 0xfff80000) | log2P << 16 | NM1;
731 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | NM2;
732 uint32_t saved1584, savedc040, maskc040 = ~0;
735 if (oldpll1 == pll1 && oldpll2 == pll2)
736 return; /* already set */
738 if (reg1 == 0x680500) {
740 maskc040 = ~(3 << 20);
742 if (reg1 == 0x680504) {
744 maskc040 = ~(3 << 22);
746 if (shift1584 >= 0) {
747 saved1584 = nv32_rd(pScrn, 0x1584);
748 nv32_wr(pScrn, 0x1584, (saved1584 & ~(0xf << shift1584)) | 1 << shift1584);
751 if (bios->chip_version >= 0x40) {
752 savedc040 = nv32_rd(pScrn, 0xc040);
753 nv32_wr(pScrn, 0xc040, savedc040 & maskc040);
755 if (reg1 == 0x680508)
756 nv32_wr(pScrn, 0x680580, nv32_rd(pScrn, 0x680580) & ~(1 << 28));
757 if (reg1 == 0x680520)
758 nv32_wr(pScrn, 0x680580, nv32_rd(pScrn, 0x680580) & ~(1 << 8));
761 nv32_wr(pScrn, reg2, pll2);
762 nv32_wr(pScrn, reg1, pll1);
764 if (shift1584 >= 0) {
765 nv32_wr(pScrn, 0x1584, saved1584);
766 if (bios->chip_version >= 0x40)
767 nv32_wr(pScrn, 0xc040, savedc040);
771 static void setPLL_double_lowregs(ScrnInfoPtr pScrn, uint32_t NMNMreg, int NM1, int NM2, int log2P)
773 /* When setting PLLs, there is a merry game of disabling and enabling
774 * various bits of hardware during the process. This function is a
775 * synthesis of six nv40 traces, nearly each card doing a subtly
776 * different thing. With luck all the necessary bits for each card are
777 * combined herein. Without luck it deviates from each card's formula
778 * so as to not work on any :)
781 uint32_t Preg = NMNMreg - 4;
782 uint32_t oldPval = nv32_rd(pScrn, Preg);
783 uint32_t NMNM = NM2 << 16 | NM1;
784 uint32_t Pval = (oldPval & ((Preg == 0x4020) ? ~(0x11 << 16) : ~(1 << 16))) | 0xc << 28 | log2P << 16;
785 uint32_t saved4600 = 0;
786 /* some cards have different maskc040s */
787 uint32_t maskc040 = ~(3 << 14), savedc040;
789 if (nv32_rd(pScrn, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval)
795 maskc040 = ~(3 << 26);
797 if (Preg == 0x4020) {
798 struct pll_lims pll_lim;
801 if (!get_pll_limits(pScrn, Preg, &pll_lim))
804 Pval2 = log2P + pll_lim.unk1e;
805 if (Pval2 > pll_lim.unk1d)
806 Pval2 = pll_lim.unk1d;
807 Pval |= 1 << 28 | Pval2 << 20;
809 saved4600 = nv32_rd(pScrn, 0x4600);
810 nv32_wr(pScrn, 0x4600, saved4600 | 1 << 31);
813 nv32_wr(pScrn, Preg, oldPval | 1 << 28);
814 nv32_wr(pScrn, Preg, Pval & ~(1 << 30));
815 if (Preg == 0x4020) {
816 Pval |= 1 << 23 | 1 << 12;
817 nv32_wr(pScrn, 0x4020, Pval & ~(3 << 30));
818 nv32_wr(pScrn, 0x4038, Pval & ~(3 << 30));
821 savedc040 = nv32_rd(pScrn, 0xc040);
822 nv32_wr(pScrn, 0xc040, savedc040 & maskc040);
824 nv32_wr(pScrn, NMNMreg, NMNM);
825 if (NMNMreg == 0x4024)
826 nv32_wr(pScrn, 0x403c, NMNM);
828 nv32_wr(pScrn, Preg, Pval);
829 if (Preg == 0x4020) {
831 nv32_wr(pScrn, 0x4020, Pval);
832 nv32_wr(pScrn, 0x4038, Pval);
833 nv32_wr(pScrn, 0x4600, saved4600);
836 nv32_wr(pScrn, 0xc040, savedc040);
838 if (Preg == 0x4020) {
839 nv32_wr(pScrn, 0x4020, Pval & ~(1 << 28));
840 nv32_wr(pScrn, 0x4038, Pval & ~(1 << 28));
844 static void setPLL(ScrnInfoPtr pScrn, bios_t *bios, uint32_t reg, uint32_t clk)
849 if (bios->chip_version >= 0x40 || bios->chip_version == 0x31 || bios->chip_version == 0x36) {
850 getMNP_double(pScrn, reg, clk, &NM1, &NM2, &log2P);
852 setPLL_double_highregs(pScrn, reg, NM1, NM2, log2P);
854 setPLL_double_lowregs(pScrn, reg, NM1, NM2, log2P);
856 getMNP_single(pScrn, clk, &NM1, &log2P);
857 setPLL_single(pScrn, reg, NM1, log2P);
862 static Bool init_prog(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
864 /* INIT_PROG opcode: 0x31
866 * offset (8 bit): opcode
867 * offset + 1 (32 bit): reg
868 * offset + 5 (32 bit): and mask
869 * offset + 9 (8 bit): shift right
870 * offset + 10 (8 bit): number of configurations
871 * offset + 11 (32 bit): register
872 * offset + 15 (32 bit): configuration 1
875 * Starting at offset + 15 there are "number of configurations"
876 * 32 bit values. To find out which configuration value to use
877 * read "CRTC reg" on the CRTC controller with index "CRTC index"
878 * and bitwise AND this value with "and mask" and then bit shift the
879 * result "shift right" bits to the right.
880 * Assign "register" with appropriate configuration value.
883 CARD32 reg = *((CARD32 *) (&bios->data[offset + 1]));
884 CARD32 and = *((CARD32 *) (&bios->data[offset + 5]));
885 CARD8 shiftr = *((CARD8 *) (&bios->data[offset + 9]));
886 CARD8 nr = *((CARD8 *) (&bios->data[offset + 10]));
887 CARD32 reg2 = *((CARD32 *) (&bios->data[offset + 11]));
889 CARD32 configval, tmp;
891 if (iexec->execute) {
892 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: REG: 0x%04X\n", offset,
895 tmp = nv32_rd(pScrn, reg);
896 configuration = (tmp & and) >> shiftr;
898 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONFIGURATION TO USE: 0x%02X\n",
899 offset, configuration);
901 if (configuration <= nr) {
904 *((CARD32 *) (&bios->data[offset + 15 + configuration * 4]));
906 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: REG: 0x%08X, VALUE: 0x%08X\n", offset,
909 tmp = nv32_rd(pScrn, reg2);
910 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CURRENT VALUE IS: 0x%08X\n",
912 nv32_wr(pScrn, reg2, configval);
919 static Bool init_io_restrict_prog(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
921 /* INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
923 * offset (8 bit): opcode
924 * offset + 1 (16 bit): CRTC port
925 * offset + 3 (8 bit): CRTC index
926 * offset + 4 (8 bit): mask
927 * offset + 5 (8 bit): shift
928 * offset + 6 (8 bit): count
929 * offset + 7 (32 bit): register
930 * offset + 11 (32 bit): configuration 1
933 * Starting at offset + 11 there are "count" 32 bit values.
934 * To find out which value to use read index "CRTC index" on "CRTC port",
935 * AND this value with "mask" and then bit shift right "shift" bits.
936 * Read the appropriate value using this index and write to "register"
939 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
940 uint8_t crtcindex = bios->data[offset + 3];
941 uint8_t mask = bios->data[offset + 4];
942 uint8_t shift = bios->data[offset + 5];
943 uint8_t count = bios->data[offset + 6];
944 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7])));
952 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
953 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
954 offset, crtcport, crtcindex, mask, shift, count, reg);
956 config = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) >> shift;
957 if (config > count) {
958 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
959 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
960 offset, config, count);
964 configval = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 11 + config * 4])));
967 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
968 "0x%04X: Writing config %02X\n", offset, config);
970 nv32_wr(pScrn, reg, configval);
975 static Bool init_repeat(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
977 /* INIT_REPEAT opcode: 0x33 ('3')
979 * offset (8 bit): opcode
980 * offset + 1 (8 bit): count
982 * Execute script following this opcode up to INIT_REPEAT_END
986 uint8_t count = bios->data[offset + 1];
989 /* no iexec->execute check by design */
991 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
992 "0x%04X: REPEATING FOLLOWING SEGMENT %d TIMES\n",
995 iexec->repeat = TRUE;
997 /* count - 1, as the script block will execute once when we leave this
998 * opcode -- this is compatible with bios behaviour as:
999 * a) the block is always executed at least once, even if count == 0
1000 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
1003 for (i = 0; i < count - 1; i++)
1004 parse_init_table(pScrn, bios, offset + 2, iexec);
1006 iexec->repeat = FALSE;
1011 static Bool init_io_restrict_pll(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1013 /* INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
1015 * offset (8 bit): opcode
1016 * offset + 1 (16 bit): CRTC port
1017 * offset + 3 (8 bit): CRTC index
1018 * offset + 4 (8 bit): mask
1019 * offset + 5 (8 bit): shift
1020 * offset + 6 (8 bit): IO flag condition index
1021 * offset + 7 (8 bit): count
1022 * offset + 8 (32 bit): register
1023 * offset + 12 (16 bit): frequency 1
1026 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
1027 * Set PLL register "register" to coefficients for frequency n,
1028 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1029 * "mask" and shifted right by "shift". If "IO flag condition index" > 0,
1030 * and condition met, double frequency before setting it.
1033 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1034 uint8_t crtcindex = bios->data[offset + 3];
1035 uint8_t mask = bios->data[offset + 4];
1036 uint8_t shift = bios->data[offset + 5];
1037 int8_t io_flag_condition_idx = bios->data[offset + 6];
1038 uint8_t count = bios->data[offset + 7];
1039 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 8])));
1043 if (!iexec->execute)
1046 if (DEBUGLEVEL >= 6)
1047 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1048 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, IO Flag Condition: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1049 offset, crtcport, crtcindex, mask, shift, io_flag_condition_idx, count, reg);
1051 config = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) >> shift;
1052 if (config > count) {
1053 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1054 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1055 offset, config, count);
1059 freq = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 12 + config * 2])));
1061 if (io_flag_condition_idx > 0) {
1062 if (io_flag_condition(pScrn, bios, offset, io_flag_condition_idx)) {
1063 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1064 "0x%04X: CONDITION FULFILLED - FREQ DOUBLED\n", offset);
1067 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1068 "0x%04X: CONDITION IS NOT FULFILLED. FREQ UNCHANGED\n", offset);
1071 if (DEBUGLEVEL >= 6)
1072 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1073 "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
1074 offset, reg, config, freq);
1076 setPLL(pScrn, bios, reg, freq * 10);
1081 static Bool init_end_repeat(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1083 /* INIT_END_REPEAT opcode: 0x36 ('6')
1085 * offset (8 bit): opcode
1087 * Marks the end of the block for INIT_REPEAT to repeat
1090 /* no iexec->execute check by design */
1092 /* iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
1093 * we're not in repeat mode
1101 static Bool init_copy(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1103 /* INIT_COPY opcode: 0x37 ('7')
1105 * offset (8 bit): opcode
1106 * offset + 1 (32 bit): register
1107 * offset + 5 (8 bit): shift
1108 * offset + 6 (8 bit): srcmask
1109 * offset + 7 (16 bit): CRTC port
1110 * offset + 9 (8 bit): CRTC index
1111 * offset + 10 (8 bit): mask
1113 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
1114 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC port
1117 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1118 uint8_t shift = bios->data[offset + 5];
1119 uint8_t srcmask = bios->data[offset + 6];
1120 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 7])));
1121 uint8_t crtcindex = bios->data[offset + 9];
1122 uint8_t mask = bios->data[offset + 10];
1126 if (!iexec->execute)
1129 if (DEBUGLEVEL >= 6)
1130 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1131 "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1132 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1134 data = nv32_rd(pScrn, reg);
1139 data <<= (0x100 - shift);
1143 crtcdata = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) | (uint8_t)data;
1144 nv_idx_port_wr(pScrn, crtcport, crtcindex, crtcdata);
1149 static Bool init_not(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1151 /* INIT_NOT opcode: 0x38 ('8')
1153 * offset (8 bit): opcode
1155 * Invert the current execute / no-execute condition (i.e. "else")
1158 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1159 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
1161 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1162 "0x%04X: ------ EXECUTING FOLLOWING COMMANDS ------\n", offset);
1164 iexec->execute = !iexec->execute;
1168 static Bool init_io_flag_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1170 /* INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1172 * offset (8 bit): opcode
1173 * offset + 1 (8 bit): condition number
1175 * Check condition "condition number" in the IO flag condition table.
1176 * If condition not met skip subsequent opcodes until condition
1177 * is inverted (INIT_NOT), or we hit INIT_RESUME
1180 uint8_t cond = bios->data[offset + 1];
1182 if (!iexec->execute)
1185 if (io_flag_condition(pScrn, bios, offset, cond))
1186 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1187 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n", offset);
1189 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1190 "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
1191 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1192 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
1193 iexec->execute = FALSE;
1199 Bool init_idx_addr_latched(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1201 /* INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1203 * offset (8 bit): opcode
1204 * offset + 1 (32 bit): control register
1205 * offset + 5 (32 bit): data register
1206 * offset + 9 (32 bit): mask
1207 * offset + 13 (32 bit): data
1208 * offset + 17 (8 bit): count
1209 * offset + 18 (8 bit): address 1
1210 * offset + 19 (8 bit): data 1
1213 * For each of "count" address and data pairs, write "data n" to "data register",
1214 * read the current value of "control register", and write it back once ANDed
1215 * with "mask", ORed with "data", and ORed with "address n"
1218 uint32_t controlreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1219 uint32_t datareg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1220 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
1221 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 13])));
1222 uint8_t count = bios->data[offset + 17];
1226 if (!iexec->execute)
1229 if (DEBUGLEVEL >= 6)
1230 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1231 "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1232 offset, controlreg, datareg, mask, data, count);
1234 for (i = 0; i < count; i++) {
1235 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1236 uint8_t instdata = bios->data[offset + 19 + i * 2];
1238 if (DEBUGLEVEL >= 6)
1239 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1240 "0x%04X: Address: 0x%02X, Data: 0x%02X\n", offset, instaddress, instdata);
1242 nv32_wr(pScrn, datareg, instdata);
1243 value = (nv32_rd(pScrn, controlreg) & mask) | data | instaddress;
1244 nv32_wr(pScrn, controlreg, value);
1250 static Bool init_io_restrict_pll2(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1252 /* INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1254 * offset (8 bit): opcode
1255 * offset + 1 (16 bit): CRTC port
1256 * offset + 3 (8 bit): CRTC index
1257 * offset + 4 (8 bit): mask
1258 * offset + 5 (8 bit): shift
1259 * offset + 6 (8 bit): count
1260 * offset + 7 (32 bit): register
1261 * offset + 11 (32 bit): frequency 1
1264 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1265 * Set PLL register "register" to coefficients for frequency n,
1266 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1267 * "mask" and shifted right by "shift".
1270 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1271 uint8_t crtcindex = bios->data[offset + 3];
1272 uint8_t mask = bios->data[offset + 4];
1273 uint8_t shift = bios->data[offset + 5];
1274 uint8_t count = bios->data[offset + 6];
1275 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7])));
1279 if (!iexec->execute)
1282 if (DEBUGLEVEL >= 6)
1283 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1284 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1285 offset, crtcport, crtcindex, mask, shift, count, reg);
1290 config = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) >> shift;
1291 if (config > count) {
1292 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1293 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1294 offset, config, count);
1298 freq = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 11 + config * 4])));
1300 if (DEBUGLEVEL >= 6)
1301 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1302 "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1303 offset, reg, config, freq);
1305 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: [ NOT YET IMPLEMENTED ]\n", offset);
1310 static Bool init_pll2(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1312 /* INIT_PLL2 opcode: 0x4B ('K')
1314 * offset (8 bit): opcode
1315 * offset + 1 (32 bit): register
1316 * offset + 5 (32 bit): freq
1318 * Set PLL register "register" to coefficients for frequency "freq"
1321 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1322 uint32_t freq = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1324 if (!iexec->execute)
1327 if (DEBUGLEVEL >= 6)
1328 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1329 "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1332 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: [ NOT YET IMPLEMENTED ]\n", offset);
1337 static uint32_t get_tmds_index_reg(ScrnInfoPtr pScrn, uint8_t mlv)
1339 /* For mlv < 0x80, it is an index into a table of TMDS base addresses
1340 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by CR58 for CR57 = 0
1341 * to index a table of offsets to the basic 0x6808b0 address
1342 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by CR58 for CR57 = 0
1343 * to index a table of offsets to the basic 0x6808b0 address, and then flip the offset by 8
1346 NVPtr pNv = NVPTR(pScrn);
1347 int pramdac_offset[13] = {0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000};
1348 uint32_t pramdac_table[4] = {0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8};
1351 /* here we assume that the DCB table has already been parsed */
1354 /* This register needs to be written to set index for reading CR58 */
1355 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, 0x57, 0);
1356 dcb_entry = nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, 0x58);
1357 if (dcb_entry > pNv->dcb_table.entries) {
1358 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1359 "CR58 doesn't have a valid DCB entry currently (%02X)\n", dcb_entry);
1362 dacoffset = pramdac_offset[pNv->dcb_table.entry[dcb_entry].or];
1365 return (0x6808b0 + dacoffset);
1367 if (mlv > (sizeof(pramdac_table) / sizeof(uint32_t))) {
1368 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1369 "Magic Lookup Value too big (%02X)\n", mlv);
1372 return pramdac_table[mlv];
1376 static Bool init_tmds(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1378 /* INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1380 * offset (8 bit): opcode
1381 * offset + 1 (8 bit): magic lookup value
1382 * offset + 2 (8 bit): TMDS address
1383 * offset + 3 (8 bit): mask
1384 * offset + 4 (8 bit): data
1386 * Read the data reg for TMDS address "TMDS address", AND it with mask
1387 * and OR it with data, then write it back
1388 * "magic lookup value" determines which TMDS base address register is used --
1389 * see get_tmds_index_reg()
1392 uint8_t mlv = bios->data[offset + 1];
1393 uint32_t tmdsaddr = bios->data[offset + 2];
1394 uint8_t mask = bios->data[offset + 3];
1395 uint8_t data = bios->data[offset + 4];
1396 uint32_t reg, value;
1398 if (!iexec->execute)
1401 if (DEBUGLEVEL >= 6)
1402 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1403 "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1404 offset, mlv, tmdsaddr, mask, data);
1406 reg = get_tmds_index_reg(pScrn, mlv);
1408 nv32_wr(pScrn, reg, tmdsaddr | 0x10000);
1409 value = (nv32_rd(pScrn, reg + 4) & mask) | data;
1410 nv32_wr(pScrn, reg + 4, value);
1411 nv32_wr(pScrn, reg, tmdsaddr);
1416 Bool init_zm_tmds_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1418 /* INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1420 * offset (8 bit): opcode
1421 * offset + 1 (8 bit): magic lookup value
1422 * offset + 2 (8 bit): count
1423 * offset + 3 (8 bit): addr 1
1424 * offset + 4 (8 bit): data 1
1427 * For each of "count" TMDS address and data pairs write "data n" to "addr n"
1428 * "magic lookup value" determines which TMDS base address register is used --
1429 * see get_tmds_index_reg()
1432 uint8_t mlv = bios->data[offset + 1];
1433 uint8_t count = bios->data[offset + 2];
1437 if (!iexec->execute)
1440 if (DEBUGLEVEL >= 6)
1441 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1442 "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1443 offset, mlv, count);
1445 reg = get_tmds_index_reg(pScrn, mlv);
1447 for (i = 0; i < count; i++) {
1448 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1449 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1451 nv32_wr(pScrn, reg + 4, tmdsdata);
1452 nv32_wr(pScrn, reg, tmdsaddr);
1458 Bool init_cr_idx_adr_latch(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1460 /* INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1462 * offset (8 bit): opcode
1463 * offset + 1 (8 bit): CRTC index1
1464 * offset + 2 (8 bit): CRTC index2
1465 * offset + 3 (8 bit): baseaddr
1466 * offset + 4 (8 bit): count
1467 * offset + 5 (8 bit): data 1
1470 * For each of "count" address and data pairs, write "baseaddr + n" to
1471 * "CRTC index1" and "data n" to "CRTC index2"
1472 * Once complete, restore initial value read from "CRTC index1"
1474 uint8_t crtcindex1 = bios->data[offset + 1];
1475 uint8_t crtcindex2 = bios->data[offset + 2];
1476 uint8_t baseaddr = bios->data[offset + 3];
1477 uint8_t count = bios->data[offset + 4];
1478 uint8_t oldaddr, data;
1481 if (!iexec->execute)
1484 if (DEBUGLEVEL >= 6)
1485 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1486 "0x%04X: Index1: 0x%02X, Index2: 0x%02X, BaseAddr: 0x%02X, Count: 0x%02X\n",
1487 offset, crtcindex1, crtcindex2, baseaddr, count);
1489 oldaddr = nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, crtcindex1);
1491 for (i = 0; i < count; i++) {
1492 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex1, baseaddr + i);
1494 data = bios->data[offset + 5 + i];
1495 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex2, data);
1498 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex1, oldaddr);
1503 Bool init_cr(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1505 /* INIT_CR opcode: 0x52 ('R')
1507 * offset (8 bit): opcode
1508 * offset + 1 (8 bit): CRTC index
1509 * offset + 2 (8 bit): mask
1510 * offset + 3 (8 bit): data
1512 * Assign the value of at "CRTC index" ANDed with mask and ORed with data
1513 * back to "CRTC index"
1516 uint8_t crtcindex = bios->data[offset + 1];
1517 uint8_t mask = bios->data[offset + 2];
1518 uint8_t data = bios->data[offset + 3];
1521 if (!iexec->execute)
1524 if (DEBUGLEVEL >= 6)
1525 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1526 "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1527 offset, crtcindex, mask, data);
1529 value = (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, crtcindex) & mask) | data;
1530 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex, value);
1535 static Bool init_zm_cr(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1537 /* INIT_ZM_CR opcode: 0x53 ('S')
1539 * offset (8 bit): opcode
1540 * offset + 1 (8 bit): CRTC index
1541 * offset + 2 (8 bit): value
1543 * Assign "value" to CRTC register with index "CRTC index".
1546 uint8_t crtcindex = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1547 uint8_t data = bios->data[offset + 2];
1549 if (!iexec->execute)
1552 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex, data);
1557 static Bool init_zm_cr_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1559 /* INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1561 * offset (8 bit): opcode
1562 * offset + 1 (8 bit): count
1563 * offset + 2 (8 bit): CRTC index 1
1564 * offset + 3 (8 bit): value 1
1567 * For "count", assign "value n" to CRTC register with index "CRTC index n".
1570 uint8_t count = bios->data[offset + 1];
1573 if (!iexec->execute)
1576 for (i = 0; i < count; i++)
1577 init_zm_cr(pScrn, bios, offset + 2 + 2 * i - 1, iexec);
1582 static Bool init_condition_time(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1584 /* INIT_CONDITION_TIME opcode: 0x56 ('V')
1586 * offset (8 bit): opcode
1587 * offset + 1 (8 bit): condition number
1588 * offset + 2 (8 bit): retries / 50
1590 * Check condition "condition number" in the condition table.
1591 * The condition table entry has 4 bytes for the address of the
1592 * register to check, 4 bytes for a mask and 4 for a test value.
1593 * If condition not met sleep for 2ms, and repeat upto "retries" times.
1594 * If still not met after retries, clear execution flag for this table.
1597 uint8_t cond = bios->data[offset + 1];
1598 uint16_t retries = bios->data[offset + 2];
1599 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
1600 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[condptr])));
1601 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 4])));
1602 uint32_t cmpval = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 8])));
1605 if (!iexec->execute)
1610 if (DEBUGLEVEL >= 6)
1611 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1612 "0x%04X: Cond: 0x%02X, Retries: 0x%02X\n", offset, cond, retries);
1614 for (; retries > 0; retries--) {
1615 data = nv32_rd(pScrn, reg) & mask;
1617 if (DEBUGLEVEL >= 6)
1618 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1619 "0x%04X: Checking if 0x%08X equals 0x%08X\n",
1620 offset, data, cmpval);
1622 if (data != cmpval) {
1623 if (DEBUGLEVEL >= 6)
1624 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1625 "0x%04X: Condition not met, sleeping for 2ms\n", offset);
1628 if (DEBUGLEVEL >= 6)
1629 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1630 "0x%04X: Condition met, continuing\n", offset);
1635 if (data != cmpval) {
1636 if (DEBUGLEVEL >= 6)
1637 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1638 "0x%04X: Condition still not met, skiping following opcodes\n", offset);
1639 iexec->execute = FALSE;
1645 static Bool init_zm_reg_sequence(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1647 /* INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1649 * offset (8 bit): opcode
1650 * offset + 1 (32 bit): base register
1651 * offset + 5 (8 bit): count
1652 * offset + 6 (32 bit): value 1
1655 * Starting at offset + 6 there are "count" 32 bit values.
1656 * For "count" iterations set "base register" + 4 * current_iteration
1657 * to "value current_iteration"
1660 uint32_t basereg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1661 uint32_t count = bios->data[offset + 5];
1664 if (!iexec->execute)
1667 if (DEBUGLEVEL >= 6)
1668 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1669 "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1670 offset, basereg, count);
1672 for (i = 0; i < count; i++) {
1673 uint32_t reg = basereg + i * 4;
1674 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 6 + i * 4])));
1676 nv32_wr(pScrn, reg, data);
1683 static Bool init_indirect_reg(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
1685 /* INIT_INDIRECT_REG opcode: 0x5A
1687 * offset (8 bit): opcode
1688 * offset + 1 (32 bit): register
1689 * offset + 5 (16 bit): adress offset (in bios)
1691 * Lookup value at offset data in the bios and write it to reg
1693 CARD32 reg = *((CARD32 *) (&bios->data[offset + 1]));
1694 CARD16 data = le16_to_cpu(*((CARD16 *) (&bios->data[offset + 5])));
1695 CARD32 data2 = bios->data[data];
1697 if (iexec->execute) {
1698 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1699 "0x%04X: REG: 0x%04X, DATA AT: 0x%04X, VALUE IS: 0x%08X\n",
1700 offset, reg, data, data2);
1702 if (DEBUGLEVEL >= 6) {
1704 tmpval = nv32_rd(pScrn, reg);
1705 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CURRENT VALUE IS: 0x%08X\n", offset, tmpval);
1708 nv32_wr(pScrn, reg, data2);
1714 static Bool init_sub_direct(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1716 /* INIT_SUB_DIRECT opcode: 0x5B ('[')
1718 * offset (8 bit): opcode
1719 * offset + 1 (16 bit): subroutine offset (in bios)
1721 * Calls a subroutine that will execute commands until INIT_DONE
1725 uint16_t sub_offset = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1727 if (!iexec->execute)
1730 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: EXECUTING SUB-ROUTINE AT 0x%04X\n",
1731 offset, sub_offset);
1733 parse_init_table(pScrn, bios, sub_offset, iexec);
1735 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: END OF SUB-ROUTINE AT 0x%04X\n",
1736 offset, sub_offset);
1741 static Bool init_copy_nv_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1743 /* INIT_COPY_NV_REG opcode: 0x5F ('_')
1745 * offset (8 bit): opcode
1746 * offset + 1 (32 bit): src reg
1747 * offset + 5 (8 bit): shift
1748 * offset + 6 (32 bit): src mask
1749 * offset + 10 (32 bit): xor
1750 * offset + 14 (32 bit): dst reg
1751 * offset + 18 (32 bit): dst mask
1753 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
1754 * "src mask", then XOR with "xor". Write this OR'd with
1755 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
1758 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
1759 uint8_t shift = bios->data[offset + 5];
1760 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
1761 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
1762 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
1763 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
1764 uint32_t srcvalue, dstvalue;
1766 if (!iexec->execute)
1769 if (DEBUGLEVEL >= 6)
1770 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1771 "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
1772 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
1774 srcvalue = nv32_rd(pScrn, srcreg);
1779 srcvalue <<= (0x100 - shift);
1781 srcvalue = (srcvalue & srcmask) ^ xor;
1783 dstvalue = nv32_rd(pScrn, dstreg) & dstmask;
1785 nv32_wr(pScrn, dstreg, dstvalue | srcvalue);
1790 static Bool init_zm_index_io(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1792 /* INIT_ZM_INDEX_IO opcode: 0x62 ('b')
1794 * offset (8 bit): opcode
1795 * offset + 1 (16 bit): CRTC port
1796 * offset + 3 (8 bit): CRTC index
1797 * offset + 4 (8 bit): data
1799 * Write "data" to index "CRTC index" of "CRTC port"
1801 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1802 uint8_t crtcindex = bios->data[offset + 3];
1803 uint8_t data = bios->data[offset + 4];
1805 if (!iexec->execute)
1808 nv_idx_port_wr(pScrn, crtcport, crtcindex, data);
1813 static Bool init_compute_mem(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1815 /* INIT_COMPUTE_MEM opcode: 0x63 ('c')
1817 * offset (8 bit): opcode
1819 * This opcode is meant to set NV_PFB_CFG0 (0x100200) appropriately so
1820 * that the hardware can correctly calculate how much VRAM it has
1821 * (and subsequently report that value in 0x10020C)
1823 * The implementation of this opcode in general consists of two parts:
1824 * 1) determination of the memory bus width
1825 * 2) determination of how many of the card's RAM pads have ICs attached
1827 * 1) is done by a cunning combination of writes to offsets 0x1c and
1828 * 0x3c in the framebuffer, and seeing whether the written values are
1829 * read back correctly. This then affects bits 4-7 of NV_PFB_CFG0
1831 * 2) is done by a cunning combination of writes to an offset slightly
1832 * less than the maximum memory reported by 0x10020C, then seeing if
1833 * the test pattern can be read back. This then affects bits 12-15 of
1836 * In this context a "cunning combination" may include multiple reads
1837 * and writes to varying locations, often alternating the test pattern
1838 * and 0, doubtless to make sure buffers are filled, residual charges
1839 * on tracks are removed etc.
1841 * Unfortunately, the "cunning combination"s mentioned above, and the
1842 * changes to the bits in NV_PFB_CFG0 differ with nearly every bios
1845 * Therefore, we cheat and assume the value of NV_PFB_CFG0 with which
1846 * we started was correct, and use that instead
1849 /* no iexec->execute check by design */
1851 /* on every card I've seen, this step gets done for us earlier in the init scripts
1852 uint8_t crdata = nv_idx_port_rd(pScrn, VGA_SEQ_INDEX, 0x01);
1853 nv_idx_port_wr(pScrn, VGA_SEQ_INDEX, 0x01, crdata | 0x20);
1856 /* this also has probably been done in the scripts, but an mmio trace of
1857 * s3 resume shows nvidia doing it anyway (unlike the VGA_SEQ_INDEX write)
1859 nv32_wr(pScrn, NV_PFB_REFCTRL, NV_PFB_REFCTRL_VALID_1);
1861 /* write back the saved configuration value */
1862 nv32_wr(pScrn, NV_PFB_CFG0, saved_nv_pfb_cfg0);
1867 static Bool init_reset(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1869 /* INIT_RESET opcode: 0x65 ('e')
1871 * offset (8 bit): opcode
1872 * offset + 1 (32 bit): register
1873 * offset + 5 (32 bit): value1
1874 * offset + 9 (32 bit): value2
1876 * Assign "value1" to "register", then assign "value2" to "register"
1879 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1880 uint32_t value1 = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1881 uint32_t value2 = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
1882 uint32_t pci_nv_19, pci_nv_20;
1884 /* no iexec->execute check by design */
1886 pci_nv_19 = nv32_rd(pScrn, NV_PBUS_PCI_NV_19);
1887 nv32_wr(pScrn, NV_PBUS_PCI_NV_19, 0);
1888 nv32_wr(pScrn, reg, value1);
1892 nv32_wr(pScrn, reg, value2);
1893 nv32_wr(pScrn, NV_PBUS_PCI_NV_19, pci_nv_19);
1895 pci_nv_20 = nv32_rd(pScrn, NV_PBUS_PCI_NV_20);
1896 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
1897 nv32_wr(pScrn, NV_PBUS_PCI_NV_20, pci_nv_20);
1903 static Bool init_index_io8(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
1905 /* INIT_INDEX_IO8 opcode: 0x69
1907 * offset (8 bit): opcode
1908 * offset + 1 (16 bit): CRTC reg
1909 * offset + 3 (8 bit): and mask
1910 * offset + 4 (8 bit): or with
1915 NVPtr pNv = NVPTR(pScrn);
1916 volatile CARD8 *ptr = crtchead ? pNv->PCIO1 : pNv->PCIO0;
1917 CARD16 reg = le16_to_cpu(*((CARD16 *)(&bios->data[offset + 1])));
1918 CARD8 and = *((CARD8 *)(&bios->data[offset + 3]));
1919 CARD8 or = *((CARD8 *)(&bios->data[offset + 4]));
1922 if (iexec->execute) {
1923 data = (VGA_RD08(ptr, reg) & and) | or;
1925 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1926 "0x%04X: CRTC REG: 0x%04X, VALUE: 0x%02X\n",
1928 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CURRENT VALUE IS: 0x%02X\n", offset,
1929 VGA_RD08(ptr, reg));
1931 #ifdef PERFORM_WRITE
1932 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "init_index_io8 crtcreg 0x%X value 0x%X\n",reg,data);
1934 VGA_WR08(ptr, reg, data);
1941 static Bool init_sub(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1943 /* INIT_SUB opcode: 0x6B ('k')
1945 * offset (8 bit): opcode
1946 * offset + 1 (8 bit): script number
1948 * Execute script number "script number", as a subroutine
1951 uint8_t sub = bios->data[offset + 1];
1953 if (!iexec->execute)
1956 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1957 "0x%04X: EXECUTING SUB-SCRIPT %d\n", offset, sub);
1959 parse_init_table(pScrn, bios,
1960 le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + sub * 2]))),
1963 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1964 "0x%04X: END OF SUB-SCRIPT %d\n", offset, sub);
1970 static Bool init_ram_condition(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
1972 /* INIT_RAM_CONDITION opcode: 0x6D
1974 * offset (8 bit): opcode
1975 * offset + 1 (8 bit): and mask
1976 * offset + 2 (8 bit): cmpval
1978 * Test if (NV_PFB_BOOT & and mask) matches cmpval
1980 NVPtr pNv = NVPTR(pScrn);
1981 CARD8 and = *((CARD8 *) (&bios->data[offset + 1]));
1982 CARD8 cmpval = *((CARD8 *) (&bios->data[offset + 2]));
1985 if (iexec->execute) {
1986 data=(pNv->PFB[NV_PFB_BOOT/4])∧
1988 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1989 "0x%04X: CHECKING IF REGVAL: 0x%08X equals COND: 0x%08X\n",
1990 offset, data, cmpval);
1992 if (data == cmpval) {
1993 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1994 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n",
1997 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
1998 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1999 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
2000 iexec->execute = FALSE;
2007 static Bool init_nv_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2009 /* INIT_NV_REG opcode: 0x6E ('n')
2011 * offset (8 bit): opcode
2012 * offset + 1 (32 bit): register
2013 * offset + 5 (32 bit): mask
2014 * offset + 9 (32 bit): data
2016 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2019 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2020 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
2021 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
2023 if (!iexec->execute)
2026 if (DEBUGLEVEL >= 6)
2027 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2028 "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2029 offset, reg, mask, data);
2031 nv32_wr(pScrn, reg, (nv32_rd(pScrn, reg) & mask) | data);
2036 static Bool init_macro(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2038 /* INIT_MACRO opcode: 0x6F ('o')
2040 * offset (8 bit): opcode
2041 * offset + 1 (8 bit): macro number
2043 * Look up macro index "macro number" in the macro index table.
2044 * The macro index table entry has 1 byte for the index in the macro table,
2045 * and 1 byte for the number of times to repeat the macro.
2046 * The macro table entry has 4 bytes for the register address and
2047 * 4 bytes for the value to write to that register
2050 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2051 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2052 uint8_t macro_tbl_idx = bios->data[tmp];
2053 uint8_t count = bios->data[tmp + 1];
2057 if (!iexec->execute)
2060 if (DEBUGLEVEL >= 6)
2061 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2062 "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, Count: 0x%02X\n",
2063 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2065 for (i = 0; i < count; i++) {
2066 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2068 reg = le32_to_cpu(*((uint32_t *)(&bios->data[macroentryptr])));
2069 data = le32_to_cpu(*((uint32_t *)(&bios->data[macroentryptr + 4])));
2071 nv32_wr(pScrn, reg, data);
2077 static Bool init_done(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2079 /* INIT_DONE opcode: 0x71 ('q')
2081 * offset (8 bit): opcode
2083 * End the current script
2086 /* mild retval abuse to stop parsing this table */
2090 static Bool init_resume(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2092 /* INIT_RESUME opcode: 0x72 ('r')
2094 * offset (8 bit): opcode
2096 * End the current execute / no-execute condition
2102 iexec->execute = TRUE;;
2103 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2104 "0x%04X: ---- EXECUTING FOLLOWING COMMANDS ----\n", offset);
2110 static Bool init_ram_condition2(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
2112 /* INIT_RAM_CONDITION2 opcode: 0x73
2114 * offset (8 bit): opcode
2115 * offset + 1 (8 bit): and mask
2116 * offset + 2 (8 bit): cmpval
2118 * Test if (NV_EXTDEV_BOOT & and mask) matches cmpval
2120 NVPtr pNv = NVPTR(pScrn);
2121 CARD32 and = *((CARD32 *) (&bios->data[offset + 1]));
2122 CARD32 cmpval = *((CARD32 *) (&bios->data[offset + 5]));
2125 if (iexec->execute) {
2126 data=(nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT))∧
2128 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2129 "0x%04X: CHECKING IF REGVAL: 0x%08X equals COND: 0x%08X\n",
2130 offset, data, cmpval);
2132 if (data == cmpval) {
2133 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2134 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n",
2137 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
2138 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2139 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
2140 iexec->execute = FALSE;
2147 static Bool init_time(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2149 /* INIT_TIME opcode: 0x74 ('t')
2151 * offset (8 bit): opcode
2152 * offset + 1 (16 bit): time
2154 * Sleep for "time" microseconds.
2157 uint16_t time = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
2159 if (!iexec->execute)
2162 if (DEBUGLEVEL >= 6)
2163 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2164 "0x%04X: Sleeping for 0x%04X microseconds\n", offset, time);
2171 static Bool init_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2173 /* INIT_CONDITION opcode: 0x75 ('u')
2175 * offset (8 bit): opcode
2176 * offset + 1 (8 bit): condition number
2178 * Check condition "condition number" in the condition table.
2179 * The condition table entry has 4 bytes for the address of the
2180 * register to check, 4 bytes for a mask and 4 for a test value.
2181 * If condition not met skip subsequent opcodes until condition
2182 * is inverted (INIT_NOT), or we hit INIT_RESUME
2185 uint8_t cond = bios->data[offset + 1];
2186 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
2187 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[condptr])));
2188 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 4])));
2189 uint32_t cmpval = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 8])));
2192 if (!iexec->execute)
2195 if (DEBUGLEVEL >= 6)
2196 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2197 "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X, Cmpval: 0x%08X\n",
2198 offset, cond, reg, mask, cmpval);
2200 data = nv32_rd(pScrn, reg) & mask;
2202 if (DEBUGLEVEL >= 6)
2203 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2204 "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2205 offset, data, cmpval);
2207 if (data == cmpval) {
2208 if (DEBUGLEVEL >= 6)
2209 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2210 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n", offset);
2212 if (DEBUGLEVEL >= 6)
2213 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2214 "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
2215 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2216 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
2217 iexec->execute = FALSE;
2223 static Bool init_index_io(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2225 /* INIT_INDEX_IO opcode: 0x78 ('x')
2227 * offset (8 bit): opcode
2228 * offset + 1 (16 bit): CRTC port
2229 * offset + 3 (8 bit): CRTC index
2230 * offset + 4 (8 bit): mask
2231 * offset + 5 (8 bit): data
2233 * Read value at index "CRTC index" on "CRTC port", AND with "mask", OR with "data", write-back
2236 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
2237 uint8_t crtcindex = bios->data[offset + 3];
2238 uint8_t mask = bios->data[offset + 4];
2239 uint8_t data = bios->data[offset + 5];
2242 if (!iexec->execute)
2245 if (DEBUGLEVEL >= 6)
2246 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2247 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
2248 offset, crtcport, crtcindex, mask, data);
2250 value = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) | data;
2251 nv_idx_port_wr(pScrn, crtcport, crtcindex, value);
2256 static Bool init_pll(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2258 /* INIT_PLL opcode: 0x79 ('y')
2260 * offset (8 bit): opcode
2261 * offset + 1 (32 bit): register
2262 * offset + 5 (16 bit): freq
2264 * Set PLL register "register" to coefficients for frequency (10kHz) "freq"
2267 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2268 uint16_t freq = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 5])));
2270 if (!iexec->execute)
2273 if (DEBUGLEVEL >= 6)
2274 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2275 "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n",
2278 setPLL(pScrn, bios, reg, freq * 10);
2283 static Bool init_zm_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2285 /* INIT_ZM_REG opcode: 0x7A ('z')
2287 * offset (8 bit): opcode
2288 * offset + 1 (32 bit): register
2289 * offset + 5 (32 bit): value
2291 * Assign "value" to "register"
2294 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2295 uint32_t value = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
2297 if (!iexec->execute)
2300 nv32_wr(pScrn, reg, value);
2305 /* hack to avoid moving the itbl_entry array before this function */
2306 int init_ram_restrict_zm_reg_group_blocklen = 0;
2308 static Bool init_ram_restrict_zm_reg_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2310 /* INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
2312 * offset (8 bit): opcode
2313 * offset + 1 (32 bit): reg
2314 * offset + 5 (8 bit): regincrement
2315 * offset + 6 (8 bit): count
2316 * offset + 7 (32 bit): value 1,1
2319 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2320 * ram_restrict_table_ptr. The value read from here is 'n', and
2321 * "value 1,n" gets written to "reg". This repeats "count" times and on
2322 * each iteration 'm', "reg" increases by "regincrement" and
2323 * "value m,n" is used. The extent of n is limited by a number read
2324 * from the 'M' BIT table, herein called "blocklen"
2327 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2328 uint8_t regincrement = bios->data[offset + 5];
2329 uint8_t count = bios->data[offset + 6];
2330 uint32_t strap_ramcfg, data;
2335 /* previously set by 'M' BIT table */
2336 blocklen = init_ram_restrict_zm_reg_group_blocklen;
2338 if (!iexec->execute)
2342 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2343 "0x%04X: Zero block length - has the M table been parsed?\n", offset);
2347 strap_ramcfg = (nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
2348 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
2350 if (DEBUGLEVEL >= 6)
2351 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2352 "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
2353 offset, reg, regincrement, count, strap_ramcfg, index);
2355 for (i = 0; i < count; i++) {
2356 data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7 + index * 4 + blocklen * i])));
2358 nv32_wr(pScrn, reg, data);
2360 reg += regincrement;
2366 static Bool init_copy_zm_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2368 /* INIT_COPY_ZM_REG opcode: 0x90 ('')
2370 * offset (8 bit): opcode
2371 * offset + 1 (32 bit): src reg
2372 * offset + 5 (32 bit): dst reg
2374 * Put contents of "src reg" into "dst reg"
2377 uint32_t srcreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2378 uint32_t dstreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
2380 if (!iexec->execute)
2383 nv32_wr(pScrn, dstreg, nv32_rd(pScrn, srcreg));
2388 static Bool init_zm_reg_group_addr_latched(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2390 /* INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
2392 * offset (8 bit): opcode
2393 * offset + 1 (32 bit): src reg
2394 * offset + 5 (8 bit): count
2395 * offset + 6 (32 bit): data 1
2398 * For each of "count" values write "data n" to "src reg"
2401 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2402 uint8_t count = bios->data[offset + 5];
2405 if (!iexec->execute)
2408 for (i = 0; i < count; i++) {
2409 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 6 + 4 * i])));
2410 nv32_wr(pScrn, reg, data);
2416 static Bool init_reserved(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2418 /* INIT_RESERVED opcode: 0x92 ('')
2420 * offset (8 bit): opcode
2422 * Seemingly does nothing
2428 static init_tbl_entry_t itbl_entry[] = {
2429 /* command name , id , length , offset , mult , command handler */
2430 // { "INIT_PROG" , 0x31, 15 , 10 , 4 , init_prog },
2431 { "INIT_IO_RESTRICT_PROG" , 0x32, 11 , 6 , 4 , init_io_restrict_prog },
2432 { "INIT_REPEAT" , 0x33, 2 , 0 , 0 , init_repeat },
2433 { "INIT_IO_RESTRICT_PLL" , 0x34, 12 , 7 , 2 , init_io_restrict_pll },
2434 { "INIT_END_REPEAT" , 0x36, 1 , 0 , 0 , init_end_repeat },
2435 { "INIT_COPY" , 0x37, 11 , 0 , 0 , init_copy },
2436 { "INIT_NOT" , 0x38, 1 , 0 , 0 , init_not },
2437 { "INIT_IO_FLAG_CONDITION" , 0x39, 2 , 0 , 0 , init_io_flag_condition },
2438 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, 18 , 17 , 2 , init_idx_addr_latched },
2439 { "INIT_IO_RESTRICT_PLL2" , 0x4A, 11 , 6 , 4 , init_io_restrict_pll2 },
2440 { "INIT_PLL2" , 0x4B, 9 , 0 , 0 , init_pll2 },
2441 /* { "INIT_I2C_BYTE" , 0x4C, x , x , x , init_i2c_byte }, */
2442 /* { "INIT_ZM_I2C_BYTE" , 0x4D, x , x , x , init_zm_i2c_byte }, */
2443 /* { "INIT_ZM_I2C" , 0x4E, x , x , x , init_zm_i2c }, */
2444 { "INIT_TMDS" , 0x4F, 5 , 0 , 0 , init_tmds },
2445 { "INIT_ZM_TMDS_GROUP" , 0x50, 3 , 2 , 2 , init_zm_tmds_group },
2446 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, 5 , 4 , 1 , init_cr_idx_adr_latch },
2447 { "INIT_CR" , 0x52, 4 , 0 , 0 , init_cr },
2448 { "INIT_ZM_CR" , 0x53, 3 , 0 , 0 , init_zm_cr },
2449 { "INIT_ZM_CR_GROUP" , 0x54, 2 , 1 , 2 , init_zm_cr_group },
2450 { "INIT_CONDITION_TIME" , 0x56, 3 , 0 , 0 , init_condition_time },
2451 { "INIT_ZM_REG_SEQUENCE" , 0x58, 6 , 5 , 4 , init_zm_reg_sequence },
2452 // { "INIT_INDIRECT_REG" , 0x5A, 7 , 0 , 0 , init_indirect_reg },
2453 { "INIT_SUB_DIRECT" , 0x5B, 3 , 0 , 0 , init_sub_direct },
2454 { "INIT_COPY_NV_REG" , 0x5F, 22 , 0 , 0 , init_copy_nv_reg },
2455 { "INIT_ZM_INDEX_IO" , 0x62, 5 , 0 , 0 , init_zm_index_io },
2456 { "INIT_COMPUTE_MEM" , 0x63, 1 , 0 , 0 , init_compute_mem },
2457 { "INIT_RESET" , 0x65, 13 , 0 , 0 , init_reset },
2458 /* { "INIT_NEXT" , 0x66, x , x , x , init_next }, */
2459 /* { "INIT_NEXT" , 0x67, x , x , x , init_next }, */
2460 /* { "INIT_NEXT" , 0x68, x , x , x , init_next }, */
2461 // { "INIT_INDEX_IO8" , 0x69, 5 , 0 , 0 , init_index_io8 },
2462 { "INIT_SUB" , 0x6B, 2 , 0 , 0 , init_sub },
2463 // { "INIT_RAM_CONDITION" , 0x6D, 3 , 0 , 0 , init_ram_condition },
2464 { "INIT_NV_REG" , 0x6E, 13 , 0 , 0 , init_nv_reg },
2465 { "INIT_MACRO" , 0x6F, 2 , 0 , 0 , init_macro },
2466 { "INIT_DONE" , 0x71, 1 , 0 , 0 , init_done },
2467 { "INIT_RESUME" , 0x72, 1 , 0 , 0 , init_resume },
2468 // { "INIT_RAM_CONDITION2" , 0x73, 9 , 0 , 0 , init_ram_condition2 },
2469 { "INIT_TIME" , 0x74, 3 , 0 , 0 , init_time },
2470 { "INIT_CONDITION" , 0x75, 2 , 0 , 0 , init_condition },
2471 /* { "INIT_IO_CONDITION" , 0x76, x , x , x , init_io_condition }, */
2472 { "INIT_INDEX_IO" , 0x78, 6 , 0 , 0 , init_index_io },
2473 { "INIT_PLL" , 0x79, 7 , 0 , 0 , init_pll },
2474 { "INIT_ZM_REG" , 0x7A, 9 , 0 , 0 , init_zm_reg },
2475 /* INIT_RAM_RESTRICT_ZM_REG_GROUP's mult is loaded by M table in BIT */
2476 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, 7 , 6 , 0 , init_ram_restrict_zm_reg_group },
2477 { "INIT_COPY_ZM_REG" , 0x90, 9 , 0 , 0 , init_copy_zm_reg },
2478 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, 6 , 5 , 4 , init_zm_reg_group_addr_latched },
2479 { "INIT_RESERVED" , 0x92, 1 , 0 , 0 , init_reserved },
2480 { 0 , 0 , 0 , 0 , 0 , 0 }
2483 static unsigned int get_init_table_entry_length(bios_t *bios, unsigned int offset, int i)
2485 /* Calculates the length of a given init table entry. */
2486 return itbl_entry[i].length + bios->data[offset + itbl_entry[i].length_offset]*itbl_entry[i].length_multiplier;
2489 static void parse_init_table(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset, init_exec_t *iexec)
2491 /* Parses all commands in a init table. */
2493 /* We start out executing all commands found in the
2494 * init table. Some op codes may change the status
2495 * of this variable to SKIP, which will cause
2496 * the following op codes to perform no operation until
2497 * the value is changed back to EXECUTE.
2503 /* Loop until INIT_DONE causes us to break out of the loop
2504 * (or until offset > bios length just in case... )
2505 * (and no more than 10000 iterations just in case... ) */
2506 while ((offset < bios->length) && (count++ < 10000)) {
2507 id = bios->data[offset];
2509 /* Find matching id in itbl_entry */
2510 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
2513 if (itbl_entry[i].name) {
2514 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: [ (0x%02X) - %s ]\n",
2515 offset, itbl_entry[i].id, itbl_entry[i].name);
2517 /* execute eventual command handler */
2518 if (itbl_entry[i].handler)
2519 if (!(*itbl_entry[i].handler)(pScrn, bios, offset, iexec))
2522 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2523 "0x%04X: Init table command not found: 0x%02X\n", offset, id);
2527 /* Add the offset of the current command including all data
2528 * of that command. The offset will then be pointing on the
2531 offset += get_init_table_entry_length(bios, offset, i);
2535 static void parse_init_tables(ScrnInfoPtr pScrn, bios_t *bios)
2537 /* Loops and calls parse_init_table() for each present table. */
2541 init_exec_t iexec = {TRUE, FALSE};
2543 while ((table = le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + i]))))) {
2545 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: Parsing init table %d\n",
2548 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2549 "0x%04X: ------ EXECUTING FOLLOWING COMMANDS ------\n", table);
2551 parse_init_table(pScrn, bios, table, &iexec);
2556 void link_head_and_output(ScrnInfoPtr pScrn, int head, int dcb_entry, Bool overrideval)
2558 /* The BIOS scripts don't do this for us, sadly
2559 * Luckily we do know the values ;-)
2561 * head < 0 indicates we wish to force a setting with the overrideval
2562 * (for VT restore etc.)
2565 NVPtr pNv = NVPTR(pScrn);
2566 int preferred_output = (ffs(pNv->dcb_table.entry[dcb_entry].or) & OUTPUT_1) >> 1;
2567 uint8_t tmds04 = 0x80;
2568 uint32_t tmds_ctrl, tmds_ctrl2;
2570 /* Bit 3 crosswires output and bus. */
2571 if (head >= 0 && head != preferred_output)
2573 if (head < 0 && overrideval)
2576 if (pNv->dcb_table.entry[dcb_entry].type == OUTPUT_LVDS)
2579 tmds_ctrl = NV_PRAMDAC0_OFFSET + (preferred_output ? NV_PRAMDAC0_SIZE : 0) + NV_RAMDAC_FP_TMDS_CONTROL;
2580 tmds_ctrl2 = NV_PRAMDAC0_OFFSET + (preferred_output ? NV_PRAMDAC0_SIZE : 0) + NV_RAMDAC_FP_TMDS_CONTROL_2;
2582 Bool oldexecute = pNv->VBIOS.execute;
2583 pNv->VBIOS.execute = TRUE;
2584 nv32_wr(pScrn, tmds_ctrl + 4, tmds04);
2585 nv32_wr(pScrn, tmds_ctrl, 0x04);
2586 if (pNv->dcb_table.entry[dcb_entry].type == OUTPUT_LVDS && pNv->VBIOS.fp.dual_link)
2587 nv32_wr(pScrn, tmds_ctrl2 + 4, tmds04 ^ 0x08);
2589 /* I have encountered no dvi (dual-link or not) that sets to anything else. */
2590 /* Does this change beyond the 165 MHz boundary? */
2591 nv32_wr(pScrn, tmds_ctrl2 + 4, 0x0);
2593 nv32_wr(pScrn, tmds_ctrl2, 0x04);
2594 pNv->VBIOS.execute = oldexecute;
2597 static void call_lvds_manufacturer_script(ScrnInfoPtr pScrn, int head, int dcb_entry, enum LVDS_script script)
2599 NVPtr pNv = NVPTR(pScrn);
2600 bios_t *bios = &pNv->VBIOS;
2601 init_exec_t iexec = {TRUE, FALSE};
2603 uint8_t sub = bios->data[bios->fp.xlated_entry + script];
2604 uint16_t scriptofs = le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + sub * 2])));
2605 Bool power_off_for_reset;
2606 uint16_t off_on_delay;
2608 if (!bios->fp.xlated_entry || !sub || !scriptofs)
2611 if (script == LVDS_INIT && bios->data[scriptofs] != 'q') {
2612 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "LVDS init script not stubbed\n");
2616 power_off_for_reset = bios->data[bios->fp.xlated_entry] & 1;
2617 off_on_delay = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.xlated_entry + 7]);
2619 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
2620 call_lvds_manufacturer_script(pScrn, head, dcb_entry, LVDS_RESET);
2621 if (script == LVDS_RESET && power_off_for_reset)
2622 call_lvds_manufacturer_script(pScrn, head, dcb_entry, LVDS_PANEL_OFF);
2624 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Calling LVDS script %d:\n", script);
2625 pNv->VBIOS.execute = TRUE;
2626 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_OWNER,
2627 head ? NV_VGA_CRTCX_OWNER_HEADB : NV_VGA_CRTCX_OWNER_HEADA);
2628 parse_init_table(pScrn, bios, scriptofs, &iexec);
2629 pNv->VBIOS.execute = FALSE;
2631 if (script == LVDS_PANEL_OFF)
2632 usleep(off_on_delay * 1000);
2633 if (script == LVDS_RESET)
2634 link_head_and_output(pScrn, head, dcb_entry, FALSE);
2637 static uint16_t clkcmptable(bios_t *bios, uint16_t clktable, int pxclk)
2639 int compare_record_len, i = 0;
2640 uint16_t compareclk, scriptptr = 0;
2642 if (bios->major_version < 5) /* pre BIT */
2643 compare_record_len = 3;
2645 compare_record_len = 4;
2648 compareclk = le16_to_cpu(*((uint16_t *)&bios->data[clktable + compare_record_len * i]));
2649 if (pxclk >= compareclk * 10) {
2650 if (bios->major_version < 5) {
2651 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
2652 scriptptr = le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + tmdssub * 2])));
2654 scriptptr = le16_to_cpu(*((uint16_t *)&bios->data[clktable + 2 + compare_record_len * i]));
2658 } while (compareclk);
2663 static void rundigitaloutscript(ScrnInfoPtr pScrn, uint16_t scriptptr, int head, int dcb_entry)
2665 bios_t *bios = &NVPTR(pScrn)->VBIOS;
2666 init_exec_t iexec = {TRUE, FALSE};
2668 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: Parsing digital output script table\n", scriptptr);
2669 bios->execute = TRUE;
2670 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_OWNER,
2671 head ? NV_VGA_CRTCX_OWNER_HEADB : NV_VGA_CRTCX_OWNER_HEADA);
2672 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, 0x57, 0);
2673 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, 0x58, dcb_entry);
2674 parse_init_table(pScrn, bios, scriptptr, &iexec);
2675 bios->execute = FALSE;
2677 link_head_and_output(pScrn, head, dcb_entry, FALSE);
2680 static void run_lvds_table(ScrnInfoPtr pScrn, int head, int dcb_entry, enum LVDS_script script, int pxclk)
2682 /* The BIT LVDS table's header has the information to setup the
2683 * necessary registers. Following the standard 4 byte header are:
2684 * A bitmask byte and a dual-link transition pxclk value for use in
2685 * selecting the init script when not using straps; 4 script pointers
2686 * for panel power, selected by output and on/off; and 8 table pointers
2687 * for panel init, the needed one determined by output, and bits in the
2688 * conf byte. These tables are similar to the TMDS tables, consisting
2689 * of a list of pxclks and script pointers.
2692 NVPtr pNv = NVPTR(pScrn);
2693 bios_t *bios = &pNv->VBIOS;
2694 unsigned int fpstrapping, outputset = (pNv->dcb_table.entry[dcb_entry].or == 4) ? 1 : 0;
2695 uint16_t scriptptr = 0, clktable;
2696 uint8_t clktableptr = 0;
2698 fpstrapping = (nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
2700 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
2701 run_lvds_table(pScrn, head, dcb_entry, LVDS_RESET, pxclk);
2702 /* no sign of the "panel off for reset" bit, but it's safer to assume we should */
2703 if (script == LVDS_RESET)
2704 run_lvds_table(pScrn, head, dcb_entry, LVDS_PANEL_OFF, pxclk);
2706 /* for now we assume version 3.0 table - g80 support will need some changes */
2711 case LVDS_BACKLIGHT_ON: // check applicability of the script for this
2713 scriptptr = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
2715 case LVDS_BACKLIGHT_OFF: // check applicability of the script for this
2716 case LVDS_PANEL_OFF:
2717 scriptptr = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
2720 if (pNv->dcb_table.entry[dcb_entry].lvdsconf.use_straps_for_mode ||
2721 (fpstrapping != 0x0f && bios->data[bios->fp.xlated_entry + 1] != 0x0f)) {
2722 if (bios->fp.dual_link)
2724 if (bios->fp.BITbit1)
2727 uint8_t fallback = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
2728 int fallbackcmpval = (pNv->dcb_table.entry[dcb_entry].or == 4) ? 4 : 1;
2730 if (pxclk >= bios->fp.duallink_transition_clk) {
2732 fallbackcmpval *= 2;
2734 if (fallbackcmpval & fallback)
2738 /* adding outputset * 8 may not be correct */
2739 clktable = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 15 + clktableptr * 2 + outputset * 8]);
2741 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Pixel clock comparison table not found\n");
2744 scriptptr = clkcmptable(bios, clktable, pxclk);
2748 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "LVDS output init script not found\n");
2751 rundigitaloutscript(pScrn, scriptptr, head, dcb_entry);
2754 void call_lvds_script(ScrnInfoPtr pScrn, int head, int dcb_entry, enum LVDS_script script, int pxclk)
2756 /* LVDS operations are multiplexed in an effort to present a single API
2757 * which works with two vastly differing underlying structures.
2758 * This acts as the demux
2761 bios_t *bios = &NVPTR(pScrn)->VBIOS;
2762 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
2767 if (lvds_ver < 0x30)
2768 call_lvds_manufacturer_script(pScrn, head, dcb_entry, script);
2770 run_lvds_table(pScrn, head, dcb_entry, script, pxclk);
2774 uint16_t fptablepointer;
2775 uint16_t fpxlatetableptr;
2776 uint16_t fpxlatemanufacturertableptr;
2780 static void parse_fp_mode_table(ScrnInfoPtr pScrn, bios_t *bios, struct fppointers *fpp)
2782 unsigned int fpstrapping;
2784 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
2786 DisplayModePtr mode;
2788 fpstrapping = (nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
2790 if (fpp->fptablepointer == 0x0 || fpp->fpxlatetableptr == 0x0) {
2791 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2792 "Pointers to flat panel table invalid\n");
2796 fptable = &bios->data[fpp->fptablepointer];
2798 fptable_ver = fptable[0];
2800 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2801 "Found flat panel mode table revision %d.%d\n",
2802 fptable_ver >> 4, fptable_ver & 0xf);
2804 switch (fptable_ver) {
2805 /* BMP version 0x5.0x11 BIOSen have version 1 like tables, but no version field,
2806 * and miss one of the spread spectrum/PWM bytes.
2807 * This could affect early GF2Go parts (not seen any appropriate ROMs though).
2808 * Here we assume that a version of 0x05 matches this case (combining with a
2809 * BMP version check would be better), as the common case for the panel type
2810 * field is 0x0005, and that is in fact what we are reading the first byte of. */
2811 case 0x05: /* some NV10, 11, 15, 16 */
2815 case 0x10: /* some NV15/16, and NV11+ */
2819 case 0x20: /* NV40+ */
2820 headerlen = fptable[1];
2821 recordlen = fptable[2];
2822 fpentries = fptable[3];
2823 /* fptable[4] is the minimum RAMDAC_FP_HCRTC->RAMDAC_FP_HSYNC_START gap.
2824 * Only seen 0x4b (=75) which is what is used in nv_crtc.c anyway,
2825 * so we're not using this table value for now
2830 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2831 "FP Table revision not currently supported\n");
2835 fpindex = bios->data[fpp->fpxlatetableptr + fpstrapping * fpp->xlatwidth];
2836 if (fpindex > fpentries) {
2837 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2838 "Bad flat panel table index\n");
2842 /* reserved values - means that ddc or hard coded edid should be used */
2843 if (fpindex == 0xf && fpstrapping == 0xf) {
2844 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Ignoring FP table\n");
2848 if (!(mode = xcalloc(1, sizeof(DisplayModeRec))))
2851 int modeofs = headerlen + recordlen * fpindex + ofs;
2852 mode->Clock = le16_to_cpu(*(uint16_t *)&fptable[modeofs]) * 10;
2853 mode->HDisplay = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 2]);
2854 mode->HSyncStart = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 10] + 1);
2855 mode->HSyncEnd = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 12] + 1);
2856 mode->HTotal = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 14] + 1);
2857 mode->VDisplay = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 16]);
2858 mode->VSyncStart = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 24] + 1);
2859 mode->VSyncEnd = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 26] + 1);
2860 mode->VTotal = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 28] + 1);
2861 mode->Flags |= (fptable[modeofs + 30] & 0x10) ? V_PHSYNC : V_NHSYNC;
2862 mode->Flags |= (fptable[modeofs + 30] & 0x1) ? V_PVSYNC : V_NVSYNC;
2865 * bytes 1-2 are "panel type", including bits on whether Colour/mono, single/dual link, and type (TFT etc.)
2866 * bytes 3-6 are bits per colour in RGBX
2868 * 13-14 is HValid Start
2869 * 15-16 is HValid End
2870 * bytes 38-39 relate to spread spectrum settings
2871 * bytes 40-43 are something to do with PWM */
2873 mode->prev = mode->next = NULL;
2874 mode->status = MODE_OK;
2875 mode->type = M_T_DRIVER | M_T_PREFERRED;
2876 xf86SetModeDefaultName(mode);
2878 // if (XF86_CRTC_CONFIG_PTR(pScrn)->debug_modes) {
2879 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2880 "Found flat panel mode in BIOS tables:\n");
2881 xf86PrintModeline(pScrn->scrnIndex, mode);
2884 bios->fp.native_mode = mode;
2887 static void parse_lvds_manufacturer_table_init(ScrnInfoPtr pScrn, bios_t *bios, struct fppointers *fpp)
2889 /* The LVDS table changed considerably with BIT bioses. Previously
2890 * there was a header of version and record length, followed by several
2891 * records, indexed by a seperate xlat table, indexed in turn by the fp
2892 * strap in EXTDEV_BOOT. Each record had a config byte, followed by 6
2893 * script numbers for use by INIT_SUB which controlled panel init and
2894 * power, and finally a dword of ms to sleep between power off and on
2897 * The BIT LVDS table has the typical BIT table header: version byte,
2898 * header length byte, record length byte, and a byte for the maximum
2899 * number of records that can be held in the table. At byte 5 in the
2900 * header is the dual-link transition pxclk (in 10s kHz) - if straps
2901 * are not being used for the panel, this specifies the frequency at
2902 * which modes should be set up in the dual link style.
2904 * The table following the header serves as an integrated config and
2905 * xlat table: the records in the table are indexed by the FP strap
2906 * nibble in EXTDEV_BOOT, and each record has two bytes - the first as
2907 * a config byte, the second for indexing the fp mode table pointed to
2908 * by the BIT 'D' table
2911 unsigned int fpstrapping, lvdsmanufacturerindex = 0;
2912 uint8_t lvds_ver, headerlen, recordlen;
2914 fpstrapping = (nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
2916 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
2917 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2918 "Pointer to LVDS manufacturer table invalid\n");
2922 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
2924 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2925 "Found LVDS manufacturer table revision %d.%d\n",
2926 lvds_ver >> 4, lvds_ver & 0xf);
2929 case 0x0a: /* pre NV40 */
2930 lvdsmanufacturerindex = bios->data[fpp->fpxlatemanufacturertableptr + fpstrapping];
2933 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
2936 case 0x30: /* NV4x */
2937 lvdsmanufacturerindex = fpstrapping;
2938 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
2939 if (headerlen < 0x1f) {
2940 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2941 "LVDS table header not understood\n");
2944 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
2946 case 0x40: /* It changed again with gf8 :o( */
2948 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2949 "LVDS table revision not currently supported\n");
2953 uint16_t lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + headerlen + recordlen * lvdsmanufacturerindex;
2956 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
2957 bios->fp.dual_link = bios->data[lvdsofs] & 4;
2958 bios->fp.if_is_18bit = !(bios->data[lvdsofs] & 16);
2961 /* no sign of the "reset for panel on" bit, but it's safer to assume we should */
2962 bios->fp.reset_after_pclk_change = TRUE;
2963 bios->fp.dual_link = bios->data[lvdsofs] & 1;
2964 bios->fp.BITbit1 = bios->data[lvdsofs] & 2;
2965 /* BMP likely has something like this, but I have no dump to point to where it is */
2966 bios->fp.duallink_transition_clk = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
2967 fpp->fpxlatetableptr = bios->fp.lvdsmanufacturerpointer + headerlen + 1;
2968 fpp->xlatwidth = recordlen;
2973 void run_tmds_table(ScrnInfoPtr pScrn, int dcb_entry, int head, int pxclk)
2975 /* the dcb_entry parameter is the index of the appropriate DCB entry
2976 * the pxclk parameter is in kHz
2978 * This runs the TMDS regs setting code found on BIT bios cards
2980 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
2981 * ffs(or) == 3, use the second.
2984 NVPtr pNv = NVPTR(pScrn);
2985 bios_t *bios = &pNv->VBIOS;
2986 uint16_t clktable = 0, scriptptr;
2988 if (pNv->dcb_table.entry[dcb_entry].location) /* off chip */
2991 switch (ffs(pNv->dcb_table.entry[dcb_entry].or)) {
2993 clktable = bios->tmds.output0_script_ptr;
2997 clktable = bios->tmds.output1_script_ptr;
3002 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Pixel clock comparison table not found\n");
3006 scriptptr = clkcmptable(bios, clktable, pxclk);
3009 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TMDS output init script not found\n");
3013 rundigitaloutscript(pScrn, scriptptr, head, dcb_entry);
3016 static void parse_bios_version(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset)
3018 /* offset + 0 (8 bits): Micro version
3019 * offset + 1 (8 bits): Minor version
3020 * offset + 2 (8 bits): Chip version
3021 * offset + 3 (8 bits): Major version
3024 bios->major_version = bios->data[offset + 3];
3025 bios->chip_version = bios->data[offset + 2];
3026 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Bios version %02x.%02x.%02x.%02x\n",
3027 bios->data[offset + 3], bios->data[offset + 2],
3028 bios->data[offset + 1], bios->data[offset]);
3031 //int getMNP_double_plltype(ScrnInfoPtr pScrn, enum pll_types plltype, int clk, int *NM1, int *NM2, int *log2P)
3032 int get_pll_limits_plltype(ScrnInfoPtr pScrn, enum pll_types plltype, struct pll_lims *pll_lim)
3035 * Here we just try to find a register matching plltype in the PLL
3036 * limits table. The table is better explained in get_pll_limits below.
3039 bios_t *bios = &NVPTR(pScrn)->VBIOS;
3042 if (!bios->pll_limit_tbl_ptr) {
3043 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Pointer to PLL limits table invalid\n");
3047 switch (bios->data[bios->pll_limit_tbl_ptr]) {
3049 return get_pll_limits(pScrn, 0, pll_lim);
3050 // return getMNP_double(pScrn, 0, clk, NM1, NM2, log2P);
3055 uint8_t headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
3056 uint8_t recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
3057 uint8_t entries = bios->data[bios->pll_limit_tbl_ptr + 3];
3058 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
3062 for (i = 1; i < entries; i++) {
3063 uint32_t cmpreg = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + recordlen * i])));
3064 /* version 0x21 compares (the_desired_reg - 4) with the reg field */
3067 if (plltype == VPLL1 && (cmpreg == 0x680508 || cmpreg == 0x4010)) {
3068 reg = cmpreg - regdelta;
3071 if (plltype == VPLL2 && (cmpreg == 0x680520 || cmpreg == 0x4018)) {
3072 reg = cmpreg - regdelta;
3077 return get_pll_limits(pScrn, reg, pll_lim);
3078 // return getMNP_double(pScrn, reg, clk, NM1, NM2, log2P);
3081 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3082 "PLL limits table revision not currently supported\n");
3087 Bool get_pll_limits(ScrnInfoPtr pScrn, uint32_t reg, struct pll_lims *pll_lim)
3091 * Version 0x10: NV31
3092 * One byte header (version), one record of 24 bytes
3093 * Version 0x11: NV36 - Not implemented
3094 * Seems to have same record style as 0x10, but 3 records rather than 1
3095 * Version 0x20: Found on Geforce 6 cards
3096 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
3097 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
3098 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record length
3101 bios_t *bios = &NVPTR(pScrn)->VBIOS;
3102 uint8_t pll_lim_ver, headerlen, recordlen, entries;
3103 int pllindex = 0, i;
3105 if (!bios->pll_limit_tbl_ptr) {
3106 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Pointer to PLL limits table invalid\n");
3110 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
3112 if (DEBUGLEVEL >= 6)
3113 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3114 "Found PLL limits table version 0x%X\n", pll_lim_ver);
3116 switch (pll_lim_ver) {
3124 /* version 0x21 compares (the_desired_reg - 4) with the reg field */
3127 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
3128 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
3129 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
3132 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3133 "PLL limits table revision not currently supported\n");
3137 /* initialize all members to zero */
3138 memset (pll_lim, 0, sizeof(struct pll_lims));
3140 if (pll_lim_ver == 0x10) {
3141 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex;
3143 pll_lim->vco1.minfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs])));
3144 pll_lim->vco1.maxfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 4])));
3145 pll_lim->vco2.minfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 8])));
3146 pll_lim->vco2.maxfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 12])));
3147 pll_lim->vco1.min_inputfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 16])));
3148 pll_lim->vco2.min_inputfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 20])));
3149 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
3151 /* these values taken from nv31. nv30, nv36 might do better with different ones */
3152 pll_lim->vco1.min_n = 0x1;
3153 pll_lim->vco1.max_n = 0xff;
3154 pll_lim->vco1.min_m = 0x1;
3155 pll_lim->vco1.max_m = 0xd;
3156 pll_lim->vco2.min_n = 0x4;
3157 pll_lim->vco2.max_n = 0x46;
3158 if (bios->chip_version == 0x30)
3159 /* only 5 bits available for N2 on nv30 */
3160 pll_lim->vco2.max_n = 0x1f;
3161 if (bios->chip_version == 0x31)
3162 /* on nv31, N2 is compared to maxN2 (0x46) and maxM2 (0x4),
3163 * so set maxN2 to 0x4 and save a comparison
3165 pll_lim->vco2.max_n = 0x4;
3166 pll_lim->vco2.min_m = 0x1;
3167 pll_lim->vco2.max_m = 0x4;
3168 } else { /* ver 0x20, 0x21 */
3169 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
3171 /* first entry is default match, if nothing better. warn if reg field nonzero */
3172 if (le32_to_cpu(*((uint32_t *)&bios->data[plloffs + recordlen])))
3173 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
3174 "Default PLL limit entry has non-zero register field\n");
3176 for (i = 1; i < entries; i++)
3177 if (le32_to_cpu(*((uint32_t *)&bios->data[plloffs + recordlen * i])) == reg) {
3182 plloffs += recordlen * pllindex;
3184 if (DEBUGLEVEL >= 6)
3185 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Loading PLL limits for reg 0x%08x\n", reg);
3187 /* frequencies are stored in tables in MHz, kHz are more useful, so we convert */
3189 /* What output frequencies can each VCO generate? */
3190 pll_lim->vco1.minfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 4]))) * 1000;
3191 pll_lim->vco1.maxfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 6]))) * 1000;
3192 pll_lim->vco2.minfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 8]))) * 1000;
3193 pll_lim->vco2.maxfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 10]))) * 1000;
3195 /* What input frequencies do they accept (past the m-divider)? */
3196 pll_lim->vco1.min_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 12]))) * 1000;
3197 pll_lim->vco2.min_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 14]))) * 1000;
3198 pll_lim->vco1.max_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 16]))) * 1000;
3199 pll_lim->vco2.max_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 18]))) * 1000;
3201 /* What values are accepted as multiplier and divider? */
3202 pll_lim->vco1.min_n = bios->data[plloffs + 20];
3203 pll_lim->vco1.max_n = bios->data[plloffs + 21];
3204 pll_lim->vco1.min_m = bios->data[plloffs + 22];
3205 pll_lim->vco1.max_m = bios->data[plloffs + 23];
3206 pll_lim->vco2.min_n = bios->data[plloffs + 24];
3207 pll_lim->vco2.max_n = bios->data[plloffs + 25];
3208 pll_lim->vco2.min_m = bios->data[plloffs + 26];
3209 pll_lim->vco2.max_m = bios->data[plloffs + 27];
3211 pll_lim->unk1c = bios->data[plloffs + 28]; /* minP? */
3212 pll_lim->unk1d = bios->data[plloffs + 29]; /* maxP? */
3213 pll_lim->unk1e = bios->data[plloffs + 30];
3215 if (recordlen > 0x22)
3216 pll_lim->refclk = le32_to_cpu(*((uint32_t *)&bios->data[plloffs + 31]));
3219 #if 1 /* for easy debugging */
3220 ErrorF("pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
3221 ErrorF("pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
3222 ErrorF("pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
3223 ErrorF("pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
3225 ErrorF("pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
3226 ErrorF("pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
3227 ErrorF("pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
3228 ErrorF("pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
3230 ErrorF("pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
3231 ErrorF("pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
3232 ErrorF("pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
3233 ErrorF("pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
3234 ErrorF("pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
3235 ErrorF("pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
3236 ErrorF("pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
3237 ErrorF("pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
3239 ErrorF("pll.unk1c: %d\n", pll_lim->unk1c);
3240 ErrorF("pll.unk1d: %d\n", pll_lim->unk1d);
3241 ErrorF("pll.unk1e: %d\n", pll_lim->unk1e);
3247 static int parse_bit_B_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3249 /* offset + 0 (32 bits): BIOS version dword
3251 * There's a bunch of bits in this table other than the bios version
3252 * that we don't use - their use currently unknown
3255 if (bitentry->length < 0x4) {
3256 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3257 "Do not understand B table entry\n");
3261 parse_bios_version(pScrn, bios, bitentry->offset);
3266 static int parse_bit_C_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3268 /* offset + 8 (16 bits): PLL limits table pointer
3270 * There's more in here, but that's unknown.
3273 if (bitentry->length < 10) {
3274 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Do not understand C table entry\n");
3278 bios->pll_limit_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 8])));
3283 static int parse_bit_display_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry, struct fppointers *fpp)
3285 /* Parses the flat panel table segment that the bit entry points to.
3286 * Starting at bitentry->offset:
3288 * offset + 0 (16 bits): FIXME table pointer
3289 * offset + 2 (16 bits): mode table pointer
3292 if (bitentry->length != 4) {
3293 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3294 "Do not understand BIT display table entry\n");
3298 fpp->fptablepointer = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 2])));
3303 static unsigned int parse_bit_init_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3305 /* Parses the init table segment that the bit entry points to.
3306 * Starting at bitentry->offset:
3308 * offset + 0 (16 bits): init script tables pointer
3309 * offset + 2 (16 bits): macro index table pointer
3310 * offset + 4 (16 bits): macro table pointer
3311 * offset + 6 (16 bits): condition table pointer
3312 * offset + 8 (16 bits): io condition table pointer
3313 * offset + 10 (16 bits): io flag condition table pointer
3314 * offset + 12 (16 bits): init function table pointer
3318 if (bitentry->length < 14) {
3319 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3320 "Unable to recognize BIT init table entry\n");
3324 bios->init_script_tbls_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
3325 bios->macro_index_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 2])));
3326 bios->macro_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 4])));
3327 bios->condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 6])));
3328 bios->io_condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 8])));
3329 bios->io_flag_condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 10])));
3330 bios->init_function_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 12])));
3335 static int parse_bit_i_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3337 /* offset + 13 (16 bits): pointer to table containing DAC load detection comparison values
3339 * There's other things in this table, purpose unknown
3344 if (bitentry->length < 15) {
3345 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3346 "BIT i table not long enough for DAC load detection comparison table\n");
3350 offset = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 13])));
3352 /* doesn't exist on g80 */
3356 /* The first value in the table, following the header, is the comparison value
3357 * Purpose of subsequent values unknown - TV load detection?
3360 uint8_t version = bios->data[offset];
3362 if (version != 0x00 && version != 0x10) {
3363 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
3364 "DAC load detection comparison table version %d.%d not known\n",
3365 version >> 4, version & 0xf);
3369 uint8_t headerlen = bios->data[offset + 1];
3371 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3372 "DAC load detection comparison table version %x found\n", version);
3374 bios->dactestval = le32_to_cpu(*((uint32_t *)(&bios->data[offset + headerlen])));
3379 static int parse_bit_lvds_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry, struct fppointers *fpp)
3381 /* Parses the LVDS table segment that the bit entry points to.
3382 * Starting at bitentry->offset:
3384 * offset + 0 (16 bits): LVDS strap xlate table pointer
3387 if (bitentry->length != 2) {
3388 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3389 "Do not understand BIT LVDS table entry\n");
3393 /* no idea if it's still called the LVDS manufacturer table, but the concept's close enough */
3394 bios->fp.lvdsmanufacturerpointer = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
3396 parse_lvds_manufacturer_table_init(pScrn, bios, fpp);
3401 static int parse_bit_M_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3403 /* offset + 2 (8 bits): number of options in an INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
3404 * offset + 3 (16 bits): pointer to strap xlate table for RAM restrict option selection
3406 * There's a bunch of bits in this table other than the RAM restrict
3407 * stuff that we don't use - their use currently unknown
3412 /* Older bios versions don't have a sufficiently long table for what we want */
3413 if (bitentry->length < 0x5)
3416 /* set up multiplier for INIT_RAM_RESTRICT_ZM_REG_GROUP */
3417 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != 0x8f); i++)
3419 itbl_entry[i].length_multiplier = bios->data[bitentry->offset + 2] * 4;
3420 init_ram_restrict_zm_reg_group_blocklen = itbl_entry[i].length_multiplier;
3422 bios->ram_restrict_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 3])));
3427 static int parse_bit_tmds_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3429 /* Parses the pointer to the TMDS table
3431 * Starting at bitentry->offset:
3433 * offset + 0 (16 bits): TMDS table pointer
3435 * The TMDS table is typically found just before the DCB table, with a
3436 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
3439 * At offset +7 is a pointer to a script, which I don't know how to run yet
3440 * At offset +9 is a pointer to another script, likewise
3441 * Offset +11 has a pointer to a table where the first word is a pxclk
3442 * frequency and the second word a pointer to a script, which should be
3443 * run if the comparison pxclk frequency is less than the pxclk desired.
3444 * This repeats for decreasing comparison frequencies
3445 * Offset +13 has a pointer to a similar table
3446 * The selection of table (and possibly +7/+9 script) is dictated by
3447 * "or" from the DCB.
3450 uint16_t tmdstableptr, script1, script2;
3452 if (bitentry->length != 2) {
3453 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3454 "Do not understand BIT TMDS table entry\n");
3458 tmdstableptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
3460 if (tmdstableptr == 0x0) {
3461 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Pointer to TMDS table invalid\n");
3465 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Found TMDS table revision %d.%d\n",
3466 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
3468 /* These two scripts are odd: they don't seem to get run even when they are not stubbed */
3469 script1 = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 7]));
3470 script2 = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 9]));
3471 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
3472 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TMDS table script pointers not stubbed\n");
3474 bios->tmds.output0_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 11]));
3475 bios->tmds.output1_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 13]));
3480 static void parse_bit_structure(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset)
3482 bit_entry_t bitentry;
3484 struct fppointers fpp;
3485 NVPtr pNv = NVPTR(pScrn);
3487 memset(&fpp, 0, sizeof(struct fppointers));
3490 bitentry.id[0] = bios->data[offset];
3491 bitentry.id[1] = bios->data[offset + 1];
3492 bitentry.length = le16_to_cpu(*((uint16_t *)&bios->data[offset + 2]));
3493 bitentry.offset = le16_to_cpu(*((uint16_t *)&bios->data[offset + 4]));
3495 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3496 "0x%04X: Found BIT command with id 0x%02X (%c)\n",
3497 offset, bitentry.id[0], bitentry.id[0]);
3499 switch (bitentry.id[0]) {
3501 /* id[0] = 0 and id[1] = 0 ==> end of BIT struture */
3502 if (bitentry.id[1] == 0)
3506 parse_bit_B_tbl_entry(pScrn, bios, &bitentry);
3509 parse_bit_C_tbl_entry(pScrn, bios, &bitentry);
3512 parse_bit_display_tbl_entry(pScrn, bios, &bitentry, &fpp);
3515 parse_bit_init_tbl_entry(pScrn, bios, &bitentry);
3518 parse_bit_i_tbl_entry(pScrn, bios, &bitentry);
3521 parse_bit_lvds_tbl_entry(pScrn, bios, &bitentry, &fpp);
3523 case 'M': /* memory? */
3524 parse_bit_M_tbl_entry(pScrn, bios, &bitentry);
3527 parse_bit_tmds_tbl_entry(pScrn, bios, &bitentry);
3531 offset += sizeof(bit_entry_t);
3534 /* C and M tables have to be parsed before init can run */
3535 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3536 "Parsing previously deferred init table entry\n");
3537 parse_init_tables(pScrn, bios);
3539 /* If it's not a laptop, you probably don't care about LVDS */
3540 /* FIXME: detect mobile BIOS? */
3544 /* Need D and L tables parsed before doing this */
3545 parse_fp_mode_table(pScrn, bios, &fpp);
3548 static void parse_bmp_structure(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset)
3550 /* Parse the BMP structure for useful things
3552 * offset + 5: BMP major version
3553 * offset + 6: BMP minor version
3554 * offset + 10: BCD encoded BIOS version
3556 * offset + 18: init script table pointer (for bios versions < 5.10h)
3557 * offset + 20: extra init script table pointer (for bios versions < 5.10h)
3559 * offset + 24: FIXME
3560 * offset + 26: FIXME
3561 * offset + 28: FIXME
3563 * offset + 54: index of I2C CRTC pair to use for CRT output
3564 * offset + 55: index of I2C CRTC pair to use for TV output
3565 * offset + 56: index of I2C CRTC pair to use for flat panel output
3566 * offset + 58: write CRTC index for I2C pair 0
3567 * offset + 59: read CRTC index for I2C pair 0
3568 * offset + 60: write CRTC index for I2C pair 1
3569 * offset + 61: read CRTC index for I2C pair 1
3571 * offset + 67: maximum internal PLL frequency (single stage PLL)
3572 * offset + 71: minimum internal PLL frequency (single stage PLL)
3574 * offset + 75: script table pointers, as for parse_bit_init_tbl_entry
3576 * offset + 89: TMDS single link output A table pointer
3577 * offset + 91: TMDS single link output B table pointer
3578 * offset + 105: flat panel timings table pointer
3579 * offset + 107: flat panel strapping translation table pointer
3580 * offset + 117: LVDS manufacturer panel config table pointer
3581 * offset + 119: LVDS manufacturer strapping translation table pointer
3583 * offset + 142: PLL limits table pointer
3586 NVPtr pNv = NVPTR(pScrn);
3588 struct fppointers fpp;
3589 memset(&fpp, 0, sizeof(struct fppointers));
3591 uint8_t bmp_version_major = bios->data[offset + 5];
3592 uint8_t bmp_version_minor = bios->data[offset + 6];
3594 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BMP version %d.%d\n",
3595 bmp_version_major, bmp_version_minor);
3597 /* version 6 could theoretically exist, but I suspect BIT happened instead */
3598 if (bmp_version_major < 2 || bmp_version_major > 5) {
3599 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "You have an unsupported BMP version. Please send in your bios\n");
3603 if (bmp_version_major == 2)
3604 bmplength = 48; /* exact for 2.01 - not sure if minor version used in versions < 5 */
3605 else if (bmp_version_major == 3)
3606 bmplength = 54; /* guessed - mem init tables added in this version */
3607 else if (bmp_version_major == 4 || bmp_version_minor < 0x1) /* don't know if 5.0 exists... */
3608 bmplength = 62; /* guessed - BMP I2C indices added in version 4*/
3609 else if (bmp_version_minor < 0x6)
3610 bmplength = 67; /* exact for 5.01 */
3611 else if (bmp_version_minor < 0x10)
3612 bmplength = 75; /* exact for 5.06 */
3613 else if (bmp_version_minor == 0x10)
3614 bmplength = 89; /* exact for 5.10h */
3615 else if (bmp_version_minor < 0x14)
3616 bmplength = 118; /* exact for 5.11h */
3617 else if (bmp_version_minor < 0x24) /* not sure of version where pll limits came in;
3618 * certainly exist by 0x24 though */
3619 /* length not exact: this is long enough to get lvds members */
3622 /* length not exact: this is long enough to get pll limit member */
3626 if (nv_cksum(bios->data + offset, 8)) {
3627 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Bad BMP checksum\n");
3631 parse_bios_version(pScrn, bios, offset + 10);
3633 bios->init_script_tbls_ptr = le16_to_cpu(*(uint16_t *)&bios->data[offset + 18]);
3634 bios->extra_init_script_tbl_ptr = le16_to_cpu(*(uint16_t *)&bios->data[offset + 20]);
3637 // FIXME needed for pre v16? - haiku uses this in its COMPUTE_MEM on early biosen
3638 if (bmp_version_major > 2) {
3639 uint16_t meminittbl = le16_to_cpu(*(uint16_t *)&bios->data[offset + 24]);
3640 uint16_t sdrmemseqtbl = le16_to_cpu(*(uint16_t *)&bios->data[offset + 26]);
3641 uint16_t ddrmemseqtbl = le16_to_cpu(*(uint16_t *)&bios->data[offset + 28]);
3645 uint16_t legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
3647 legacy_i2c_offset = offset + 54;
3648 bios->legacy_i2c_indices.crt = bios->data[legacy_i2c_offset];
3649 bios->legacy_i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
3650 bios->legacy_i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
3651 pNv->dcb_table.i2c_write[0] = bios->data[legacy_i2c_offset + 4];
3652 pNv->dcb_table.i2c_read[0] = bios->data[legacy_i2c_offset + 5];
3653 pNv->dcb_table.i2c_write[1] = bios->data[legacy_i2c_offset + 6];
3654 pNv->dcb_table.i2c_read[1] = bios->data[legacy_i2c_offset + 7];
3656 if (bmplength > 74) {
3657 bios->fmaxvco = le32_to_cpu(*((uint32_t *)&bios->data[offset + 67]));
3658 bios->fminvco = le32_to_cpu(*((uint32_t *)&bios->data[offset + 71]));
3660 if (bmplength > 88) {
3661 bit_entry_t initbitentry;
3662 initbitentry.length = 14;
3663 initbitentry.offset = offset + 75;
3664 parse_bit_init_tbl_entry(pScrn, bios, &initbitentry);
3666 if (bmplength > 92) {
3667 bios->tmds.output0_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[offset + 89]));
3668 bios->tmds.output1_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[offset + 91]));
3670 if (bmplength > 108) {
3671 fpp.fptablepointer = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 105])));
3672 fpp.fpxlatetableptr = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 107])));
3675 if (bmplength > 120) {
3676 bios->fp.lvdsmanufacturerpointer = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 117])));
3677 fpp.fpxlatemanufacturertableptr = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 119])));
3679 if (bmplength > 143)
3680 bios->pll_limit_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 142])));
3682 /* want pll_limit_tbl_ptr set (if available) before init is run */
3683 if (bmp_version_major < 5 || bmp_version_minor < 0x10) {
3684 init_exec_t iexec = {TRUE, FALSE};
3685 parse_init_table(pScrn, bios, bios->init_script_tbls_ptr, &iexec);
3686 parse_init_table(pScrn, bios, bios->extra_init_script_tbl_ptr, &iexec);
3688 parse_init_tables(pScrn, bios);
3690 /* If it's not a laptop, you probably don't care about fptables */
3691 /* FIXME: detect mobile BIOS? */
3695 parse_fp_mode_table(pScrn, bios, &fpp);
3696 parse_lvds_manufacturer_table_init(pScrn, bios, &fpp);
3697 /* I've never seen a valid LVDS_INIT script, so we'll do a test for it here */
3698 call_lvds_script(pScrn, 0, 0, LVDS_INIT, 0);
3701 static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
3705 for (i = 0; i <= (n - len); i++) {
3706 for (j = 0; j < len; j++)
3707 if (data[i + j] != str[j])
3716 static Bool parse_dcb_entry(ScrnInfoPtr pScrn, uint8_t dcb_version, uint32_t conn, uint32_t conf, struct dcb_entry *entry)
3718 NVPtr pNv = NVPTR(pScrn);
3720 memset(entry, 0, sizeof (struct dcb_entry));
3722 /* safe defaults for a crt */
3724 entry->i2c_index = 0;
3727 entry->location = 0;
3729 entry->duallink_possible = FALSE;
3731 if (dcb_version >= 0x20) {
3732 entry->type = conn & 0xf;
3733 entry->i2c_index = (conn >> 4) & 0xf;
3734 entry->heads = (conn >> 8) & 0xf;
3735 entry->bus = (conn >> 16) & 0xf;
3736 entry->location = (conn >> 20) & 0xf;
3737 entry->or = (conn >> 24) & 0xf;
3738 /* Normal entries consist of a single bit, but dual link has the
3739 * adjacent more significant bit set too
3741 if ((1 << (ffs(entry->or) - 1)) * 3 == entry->or)
3742 entry->duallink_possible = TRUE;
3744 switch (entry->type) {
3746 if (conf & 0xfffffffa)
3747 ErrorF("Unknown LVDS configuration bits, please report\n");
3749 entry->lvdsconf.use_straps_for_mode = TRUE;
3751 entry->lvdsconf.use_power_scripts = TRUE;
3754 } else if (dcb_version >= 0x14 ) {
3755 if (conn != 0xf0003f00 && conn != 0xf2204301 && conn != 0xf2045f14 && conn != 0xf2205004 && conn != 0xf4204011) {
3756 ErrorF("Unknown DCB 1.4 / 1.5 entry, please report\n");
3757 /* cause output setting to fail, so message is seen */
3758 pNv->dcb_table.entries = 0;
3761 /* most of the below is a "best guess" atm */
3762 entry->type = conn & 0xf;
3763 if (entry->type == 4) { /* digital */
3765 entry->type = OUTPUT_LVDS;
3767 /* FIXME: do we need to add a DVI-A analogue output in this case,
3768 * assuming this connector is DVI-I, not pure DVI-D?
3770 entry->type = OUTPUT_TMDS;
3772 /* what's in bits 5-13? could be some brooktree/chrontel/philips thing, in tv case */
3773 entry->i2c_index = (conn >> 14) & 0xf;
3774 /* raw heads field is in range 0-1, so move to 1-2 */
3775 entry->heads = ((conn >> 18) & 0x7) + 1;
3776 entry->location = (conn >> 21) & 0xf;
3777 entry->bus = (conn >> 25) & 0x7;
3778 /* set or to be same as heads -- hopefully safe enough */
3779 entry->or = entry->heads;
3781 switch (entry->type) {
3783 /* these are probably buried in conn's unknown bits */
3784 entry->lvdsconf.use_straps_for_mode = TRUE;
3785 entry->lvdsconf.use_power_scripts = TRUE;
3788 } else if (dcb_version >= 0x12) {
3789 /* use the defaults for a crt
3790 * v1.2 tables often have other entries though - need a trace
3792 entry->type = conn & 0xf; // this is valid, but will probably confuse the randr stuff
3794 } else { /* pre DCB / v1.1 - use the safe defaults for a crt */
3795 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3796 "No information in BIOS output table; assuming a CRT output exists\n");
3797 entry->i2c_index = pNv->VBIOS.legacy_i2c_indices.crt;
3800 pNv->dcb_table.entries++;
3806 read_dcb_i2c_table(ScrnInfoPtr pScrn, bios_t *bios, uint8_t dcb_version, uint16_t i2ctabptr)
3808 NVPtr pNv = NVPTR(pScrn);
3810 uint8_t headerlen = 0;
3812 int recordoffset = 0, rdofs = 1, wrofs = 0;
3815 i2c_entries = MAX_NUM_DCB_ENTRIES;
3816 memset(pNv->dcb_table.i2c_read, 0, sizeof(pNv->dcb_table.i2c_read));
3817 memset(pNv->dcb_table.i2c_write, 0, sizeof(pNv->dcb_table.i2c_write));
3819 i2ctable = &bios->data[i2ctabptr];
3821 if (dcb_version >= 0x30) {
3822 if (i2ctable[0] != dcb_version) { /* necessary? */
3823 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3824 "DCB I2C table version mismatch (%02X vs %02X)\n",
3825 i2ctable[0], dcb_version);
3828 headerlen = i2ctable[1];
3829 i2c_entries = i2ctable[2];
3830 if (i2ctable[0] >= 0x40) {
3831 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3832 "G80 DCB I2C table detected, arrgh\n"); /* they're plain weird */
3836 /* it's your own fault if you call this function on a DCB 1.1 BIOS --
3837 * the below assumes DCB 1.2
3839 if (dcb_version < 0x14) {
3845 for (i = 0; i < i2c_entries; i++)
3846 if (i2ctable[headerlen + 4 * i + 3] != 0xff) {
3847 pNv->dcb_table.i2c_read[i] = i2ctable[headerlen + recordoffset + rdofs + 4 * i];
3848 pNv->dcb_table.i2c_write[i] = i2ctable[headerlen + recordoffset + wrofs + 4 * i];
3852 static unsigned int parse_dcb_table(ScrnInfoPtr pScrn, bios_t *bios)
3854 NVPtr pNv = NVPTR(pScrn);
3855 uint16_t dcbptr, i2ctabptr = 0;
3857 uint8_t dcb_version, headerlen = 0x4, entries = MAX_NUM_DCB_ENTRIES;
3858 Bool configblock = TRUE;
3859 int recordlength = 8, confofs = 4;
3862 pNv->dcb_table.entries = 0;
3864 /* get the offset from 0x36 */
3865 dcbptr = le16_to_cpu(*(uint16_t *)&bios->data[0x36]);
3867 if (dcbptr == 0x0) {
3868 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3869 "No Display Configuration Block pointer found\n");
3870 /* this situation likely means a really old card, pre DCB, so we'll add the safe CRT entry */
3871 parse_dcb_entry(pScrn, 0, 0, 0, &pNv->dcb_table.entry[0]);
3875 dcbtable = &bios->data[dcbptr];
3877 /* get DCB version */
3878 dcb_version = dcbtable[0];
3879 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3880 "Display Configuration Block version %d.%d found\n",
3881 dcb_version >> 4, dcb_version & 0xf);
3883 if (dcb_version >= 0x20) { /* NV17+ */
3886 if (dcb_version >= 0x30) { /* NV40+ */
3887 headerlen = dcbtable[1];
3888 entries = dcbtable[2];
3889 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[4]);
3890 sig = le32_to_cpu(*(uint32_t *)&dcbtable[6]);
3892 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3893 "DCB header length %02X, with %02X possible entries\n",
3894 headerlen, entries);
3896 /* dcb_block_count = *(dcbtable[1]); */
3897 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
3898 sig = le32_to_cpu(*(uint32_t *)&dcbtable[4]);
3902 if (sig != 0x4edcbdcb) {
3903 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3904 "Bad Display Configuration Block signature (%08X)\n", sig);
3907 } else if (dcb_version >= 0x14) { /* some NV15/16, and NV11+ */
3911 strncpy(sig, (char *)&dcbtable[-7], 7);
3912 /* dcb_block_count = *(dcbtable[1]); */
3913 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
3917 if (strcmp(sig, "DEV_REC")) {
3918 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3919 "Bad Display Configuration Block signature (%s)\n", sig);
3922 } else if (dcb_version >= 0x12) { /* some NV6/10, and NV15+ */
3923 /* dcb_block_count = *(dcbtable[1]); */
3924 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
3925 configblock = FALSE;
3926 } else { /* NV5+, maybe NV4 */
3927 /* DCB 1.1 seems to be quite unhelpful - we'll just add the safe CRT entry */
3928 parse_dcb_entry(pScrn, dcb_version, 0, 0, &pNv->dcb_table.entry[0]);
3932 if (entries >= MAX_NUM_DCB_ENTRIES)
3933 entries = MAX_NUM_DCB_ENTRIES;
3935 for (i = 0; i < entries; i++) {
3936 uint32_t connection, config = 0;
3938 connection = le32_to_cpu(*(uint32_t *)&dcbtable[headerlen + recordlength * i]);
3940 config = le32_to_cpu(*(uint32_t *)&dcbtable[headerlen + confofs + recordlength * i]);
3942 /* Should we allow discontinuous DCBs? Certainly DCB I2C tables
3943 * can be discontinuous */
3944 if ((connection & 0x0000000f) == 0x0000000f) /* end of records */
3947 ErrorF("Raw DCB entry %d: %08x %08x\n", i, connection, config);
3948 if (!parse_dcb_entry(pScrn, dcb_version, connection, config, &pNv->dcb_table.entry[i]))
3952 read_dcb_i2c_table(pScrn, bios, dcb_version, i2ctabptr);
3954 /* DCB v2.0, in particular, lists each output combination separately.
3955 * Here we merge compatible entries to have fewer outputs, with more options
3957 for (i = 0; i < pNv->dcb_table.entries; i++) {
3958 struct dcb_entry *ient = &pNv->dcb_table.entry[i];
3961 for (j = i + 1; j < pNv->dcb_table.entries; j++) {
3962 struct dcb_entry *jent = &pNv->dcb_table.entry[j];
3964 if (jent->type == 100) /* already merged entry */
3967 if (jent->i2c_index == ient->i2c_index && jent->type == ient->type && jent->location == ient->location) {
3968 /* only merge heads field when output field is the same --
3969 * we could merge output field for same heads, but dual link,
3970 * the resultant need to make several merging passes, and lack
3971 * of applicable real life cases has deterred this so far
3973 if (jent->or == ient->or) {
3974 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3975 "Merging DCB entries %d and %d\n", i, j);
3976 ient->heads |= jent->heads;
3977 jent->type = 100; /* dummy value */
3983 /* Compact entries merged into others out of dcb_table */
3985 for (i = 0; i < pNv->dcb_table.entries; i++) {
3986 if ( pNv->dcb_table.entry[i].type == 100 )
3989 if (newentries != i)
3990 memcpy(&pNv->dcb_table.entry[newentries], &pNv->dcb_table.entry[i], sizeof(struct dcb_entry));
3994 pNv->dcb_table.entries = newentries;
3996 return pNv->dcb_table.entries;
3999 static void load_nv17_hw_sequencer_ucode(ScrnInfoPtr pScrn, bios_t *bios, uint16_t hwsq_offset, int entry)
4001 /* BMP based cards, from NV17, need a microcode loading to correctly
4002 * control the GPIO etc for LVDS panels
4004 * BIT based cards seem to do this directly in the init scripts
4006 * The microcode entries are found by the "HWSQ" signature.
4007 * The header following has the number of entries, and the entry size
4009 * An entry consists of a dword to write to the sequencer control reg
4010 * (0x00001304), followed by the ucode bytes, written sequentially,
4011 * starting at reg 0x00001400
4014 uint8_t bytes_to_write;
4017 if (bios->data[hwsq_offset] <= entry) {
4018 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
4019 "Too few entries in HW sequencer table for requested entry\n");
4023 bytes_to_write = bios->data[hwsq_offset + 1];
4025 if (bytes_to_write != 36) {
4026 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown HW sequencer entry size\n");
4030 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Loading NV17 power sequencing microcode\n");
4032 uint16_t hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
4034 /* set sequencer control */
4035 nv32_wr(pScrn, 0x00001304, le32_to_cpu(*(uint32_t *)&bios->data[hwsq_entry_offset]));
4036 bytes_to_write -= 4;
4039 for (i = 0; i < bytes_to_write; i += 4)
4040 nv32_wr(pScrn, 0x00001400 + i, le32_to_cpu(*(uint32_t *)&bios->data[hwsq_entry_offset + i + 4]));
4042 /* twiddle 0x1098 */
4043 nv32_wr(pScrn, 0x00001098, nv32_rd(pScrn, 0x00001098) | 0x18);
4046 static void read_bios_edid(ScrnInfoPtr pScrn)
4048 bios_t *bios = &NVPTR(pScrn)->VBIOS;
4049 const uint8_t edid_sig[] = { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
4050 uint16_t offset = 0, newoffset;
4051 int searchlen = NV_PROM_SIZE, i;
4054 if (!(newoffset = findstr(&bios->data[offset], searchlen, edid_sig, 8)))
4056 offset += newoffset;
4057 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
4060 searchlen -= offset;
4064 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Found EDID in BIOS\n");
4066 bios->fp.edid = xalloc(EDID1_LEN);
4067 for (i = 0; i < EDID1_LEN; i++)
4068 bios->fp.edid[i] = bios->data[offset + i];
4071 Bool NVInitVBIOS(ScrnInfoPtr pScrn)
4073 NVPtr pNv = NVPTR(pScrn);
4075 memset(&pNv->VBIOS, 0, sizeof(bios_t));
4076 pNv->VBIOS.data = xalloc(NV_PROM_SIZE);
4078 if (!NVShadowVBIOS(pScrn, pNv->VBIOS.data)) {
4079 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4080 "No valid BIOS image found\n");
4081 xfree(pNv->VBIOS.data);
4085 pNv->VBIOS.length = pNv->VBIOS.data[2] * 512;
4086 if (pNv->VBIOS.length > NV_PROM_SIZE)
4087 pNv->VBIOS.length = NV_PROM_SIZE;
4092 Bool NVRunVBIOSInit(ScrnInfoPtr pScrn)
4094 NVPtr pNv = NVPTR(pScrn);
4095 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
4096 const uint8_t bit_signature[] = { 'B', 'I', 'T' };
4097 int offset, ret = 0;
4099 crtc_access(pScrn, ACCESS_UNLOCK);
4101 if ((offset = findstr(pNv->VBIOS.data, pNv->VBIOS.length, bit_signature, sizeof(bit_signature)))) {
4102 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BIT BIOS found\n");
4103 parse_bit_structure(pScrn, &pNv->VBIOS, offset + 4);
4104 } else if ((offset = findstr(pNv->VBIOS.data, pNv->VBIOS.length, bmp_signature, sizeof(bmp_signature)))) {
4105 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
4108 if ((hwsq_offset = findstr(pNv->VBIOS.data, pNv->VBIOS.length, hwsq_signature, sizeof(hwsq_signature))))
4109 /* always use entry 0? */
4110 load_nv17_hw_sequencer_ucode(pScrn, &pNv->VBIOS, hwsq_offset + sizeof(hwsq_signature), 0);
4112 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BMP BIOS found\n");
4113 parse_bmp_structure(pScrn, &pNv->VBIOS, offset);
4115 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
4116 "No known BIOS signature found\n");
4120 crtc_access(pScrn, ACCESS_LOCK);
4128 unsigned int NVParseBios(ScrnInfoPtr pScrn)
4130 NVPtr pNv = NVPTR(pScrn);
4131 uint32_t saved_nv_pextdev_boot_0;
4133 if (!NVInitVBIOS(pScrn))
4136 /* these will need remembering across a suspend */
4137 saved_nv_pextdev_boot_0 = nv32_rd(pScrn, NV_PEXTDEV_BOOT_0);
4138 saved_nv_pfb_cfg0 = nv32_rd(pScrn, NV_PFB_CFG0);
4140 pNv->VBIOS.execute = FALSE;
4142 nv32_wr(pScrn, NV_PEXTDEV_BOOT_0, saved_nv_pextdev_boot_0);
4144 if (!NVRunVBIOSInit(pScrn))
4147 if (parse_dcb_table(pScrn, &pNv->VBIOS))
4148 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
4149 "Found %d entries in DCB\n", pNv->dcb_table.entries);
4151 if (pNv->Mobile && !pNv->VBIOS.fp.native_mode)
4152 read_bios_edid(pScrn);