1 /***************************************************************************\
3 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
5 |* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6 |* international laws. Users and possessors of this source code are *|
7 |* hereby granted a nonexclusive, royalty-free copyright license to *|
8 |* use this code in individual and commercial software. *|
10 |* Any use of this source code must include, in the user documenta- *|
11 |* tion and internal comments to the code, notices to the end user *|
14 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
16 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19 |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21 |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
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24 |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25 |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26 |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
28 |* U.S. Government End Users. This source code is a "commercial *|
29 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30 |* consisting of "commercial computer software" and "commercial *|
31 |* computer software documentation," as such terms are used in *|
32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33 |* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35 |* all U.S. Government End Users acquire the source code with only *|
36 |* those rights set forth herein. *|
38 \***************************************************************************/
39 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_hw.c,v 1.21 2006/06/16 00:19:33 mvojkovi Exp $ */
41 #include "nv_include.h"
45 /* Reminder: Do NOT use these functions for the randr-1.2 codepath. */
46 uint8_t nvReadVGA(NVPtr pNv, uint8_t index)
48 volatile const uint8_t *ptr = pNv->cur_head ? pNv->PCIO1 : pNv->PCIO0;
49 assert(pNv->randr12_enable == FALSE);
50 VGA_WR08(ptr, 0x03D4, index);
51 return VGA_RD08(ptr, 0x03D5);
53 void nvWriteVGA(NVPtr pNv, uint8_t index, uint8_t data)
55 volatile const uint8_t *ptr = pNv->cur_head ? pNv->PCIO1 : pNv->PCIO0;
56 assert(pNv->randr12_enable == FALSE);
57 VGA_WR08(ptr, 0x03D4, index);
58 VGA_WR08(ptr, 0x03D5, data);
61 uint32_t nvReadCRTC(NVPtr pNv, uint8_t head, uint32_t reg)
64 reg += NV_PCRTC0_SIZE;
65 assert(pNv->randr12_enable == FALSE);
66 DDXMMIOH("nvReadCRTC: head %d reg %08x val %08x\n", head, reg, (uint32_t)MMIO_IN32(pNv->REGS, reg));
67 return MMIO_IN32(pNv->REGS, reg);
70 void nvWriteCRTC(NVPtr pNv, uint8_t head, uint32_t reg, uint32_t val)
73 reg += NV_PCRTC0_SIZE;
74 assert(pNv->randr12_enable == FALSE);
75 DDXMMIOH("nvWriteCRTC: head %d reg %08x val %08x\n", head, reg, val);
76 MMIO_OUT32(pNv->REGS, reg, val);
86 nvWriteVGA(pNv, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57 );
88 cr11 = nvReadVGA(pNv, NV_VGA_CRTCX_VSYNCE);
89 if(Lock) cr11 |= 0x80;
91 nvWriteVGA(pNv, NV_VGA_CRTCX_VSYNCE, cr11);
94 int NVShowHideCursor (
99 int current = pNv->CurrentState->cursor1;
101 pNv->CurrentState->cursor1 = (pNv->CurrentState->cursor1 & 0xFE) |
104 nvWriteVGA(pNv, NV_VGA_CRTCX_CURCTL1, pNv->CurrentState->cursor1);
106 if(pNv->Architecture == NV_ARCH_40) { /* HW bug */
107 volatile CARD32 curpos = nvReadCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS);
108 nvWriteCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS, curpos);
111 return (current & 0x01);
114 /****************************************************************************\
116 * The video arbitration routines calculate some "magic" numbers. Fixes *
117 * the snow seen when accessing the framebuffer without it. *
118 * It just works (I hope). *
120 \****************************************************************************/
125 int graphics_burst_size;
126 int video_burst_size;
147 int graphics_burst_size;
148 int video_burst_size;
156 uint8_t mem_page_miss;
158 uint32_t memory_type;
159 uint32_t memory_width;
160 uint8_t enable_video;
161 uint8_t gr_during_vid;
168 static void nvGetClocks(NVPtr pNv, unsigned int *MClk, unsigned int *NVClk)
170 unsigned int pll, N, M, MB, NB, P;
172 if(pNv->Architecture >= NV_ARCH_40) {
173 Bool VCO2_off = FALSE;
174 pll = nvReadMC(pNv, 0x4020);
175 P = (pll >> 16) & 0x07;
176 /* There seem to be 2 (redundant?) switches to turn VCO2 off. */
179 if (!(pll & (1 << 30)))
181 pll = nvReadMC(pNv, 0x4024);
183 N = (pll >> 8) & 0xFF;
188 MB = (pll >> 16) & 0xFF;
189 NB = (pll >> 24) & 0xFF;
192 ErrorF("Something wrong with MPLL VCO2 settings, ignoring VCO2.\n");
197 *MClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
199 VCO2_off = FALSE; /* reset */
201 pll = nvReadMC(pNv, 0x4000);
202 P = (pll >> 16) & 0x07;
203 /* There seem to be 2 (redundant?) switches to turn VCO2 off. */
206 if (!(pll & (1 << 30)))
208 pll = nvReadMC(pNv, 0x4004);
210 N = (pll >> 8) & 0xFF;
215 MB = (pll >> 16) & 0xFF;
216 NB = (pll >> 24) & 0xFF;
219 ErrorF("Something wrong with NVPLL VCO2 settings, ignoring VCO2\n");
224 *NVClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
226 if(pNv->twoStagePLL) {
227 pll = NVReadRAMDAC(pNv, 0, NV_RAMDAC_MPLL);
229 N = (pll >> 8) & 0xFF;
230 P = (pll >> 16) & 0x0F;
231 pll = NVReadRAMDAC(pNv, 0, NV_RAMDAC_MPLL_B);
232 if(pll & 0x80000000) {
234 NB = (pll >> 8) & 0xFF;
239 *MClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
241 pll = NVReadRAMDAC(pNv, 0, NV_RAMDAC_NVPLL);
243 N = (pll >> 8) & 0xFF;
244 P = (pll >> 16) & 0x0F;
245 pll = NVReadRAMDAC(pNv, 0, NV_RAMDAC_NVPLL_B);
246 if(pll & 0x80000000) {
248 NB = (pll >> 8) & 0xFF;
253 *NVClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
255 if(((pNv->Chipset & 0x0ff0) == CHIPSET_NV30) ||
256 ((pNv->Chipset & 0x0ff0) == CHIPSET_NV35))
258 pll = NVReadRAMDAC(pNv, 0, NV_RAMDAC_MPLL);
260 N = (pll >> 8) & 0xFF;
261 P = (pll >> 16) & 0x07;
262 if(pll & 0x00000080) {
263 MB = (pll >> 4) & 0x07;
264 NB = (pll >> 19) & 0x1f;
269 *MClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
271 pll = NVReadRAMDAC(pNv, 0, NV_RAMDAC_NVPLL);
273 N = (pll >> 8) & 0xFF;
274 P = (pll >> 16) & 0x07;
275 if(pll & 0x00000080) {
276 MB = (pll >> 4) & 0x07;
277 NB = (pll >> 19) & 0x1f;
282 *NVClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
284 pll = NVReadRAMDAC(pNv, 0, NV_RAMDAC_MPLL);
286 N = (pll >> 8) & 0xFF;
287 P = (pll >> 16) & 0x0F;
288 *MClk = (N * pNv->CrystalFreqKHz / M) >> P;
290 pll = NVReadRAMDAC(pNv, 0, NV_RAMDAC_NVPLL);
292 N = (pll >> 8) & 0xFF;
293 P = (pll >> 16) & 0x0F;
294 *NVClk = (N * pNv->CrystalFreqKHz / M) >> P;
298 ErrorF("NVClock = %i MHz, MEMClock = %i MHz\n", *NVClk/1000, *MClk/1000);
303 void nv4CalcArbitration (
308 int data, pagemiss, cas,width, video_enable, bpp;
309 int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
310 int found, mclk_extra, mclk_loop, cbs, m1, p1;
311 int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
312 int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate;
313 int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt,clwm;
316 pclk_freq = arb->pclk_khz;
317 mclk_freq = arb->mclk_khz;
318 nvclk_freq = arb->nvclk_khz;
319 pagemiss = arb->mem_page_miss;
320 cas = arb->mem_latency;
321 width = arb->memory_width >> 6;
322 video_enable = arb->enable_video;
324 mp_enable = arb->enable_mp;
355 mclk_loop = mclks+mclk_extra;
356 us_m = mclk_loop *1000*1000 / mclk_freq;
357 us_n = nvclks*1000*1000 / nvclk_freq;
358 us_p = nvclks*1000*1000 / pclk_freq;
361 video_drain_rate = pclk_freq * 2;
362 crtc_drain_rate = pclk_freq * bpp/8;
366 vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq;
367 if (nvclk_freq * 2 > mclk_freq * width)
368 video_fill_us = cbs*1000*1000 / 16 / nvclk_freq ;
370 video_fill_us = cbs*1000*1000 / (8 * width) / mclk_freq;
371 us_video = vpm_us + us_m + us_n + us_p + video_fill_us;
372 vlwm = us_video * video_drain_rate/(1000*1000);
375 if (vlwm > 128) vbs = 64;
376 if (vlwm > (256-64)) vbs = 32;
377 if (nvclk_freq * 2 > mclk_freq * width)
378 video_fill_us = vbs *1000*1000/ 16 / nvclk_freq ;
380 video_fill_us = vbs*1000*1000 / (8 * width) / mclk_freq;
381 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
388 clwm = us_crt * crtc_drain_rate/(1000*1000);
393 crtc_drain_rate = pclk_freq * bpp/8;
396 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
397 us_crt = cpm_us + us_m + us_n + us_p ;
398 clwm = us_crt * crtc_drain_rate/(1000*1000);
401 m1 = clwm + cbs - 512;
402 p1 = m1 * pclk_freq / mclk_freq;
404 if ((p1 < m1) && (m1 > 0))
408 if (mclk_extra ==0) found = 1;
411 else if (video_enable)
413 if ((clwm > 511) || (vlwm > 255))
417 if (mclk_extra ==0) found = 1;
427 if (mclk_extra ==0) found = 1;
431 if (clwm < 384) clwm = 384;
432 if (vlwm < 128) vlwm = 128;
434 fifo->graphics_lwm = data;
435 fifo->graphics_burst_size = 128;
436 data = (int)((vlwm+15));
437 fifo->video_lwm = data;
438 fifo->video_burst_size = vbs;
442 void nv4UpdateArbitrationSettings (
450 nv4_fifo_info fifo_data;
451 nv4_sim_state sim_data;
452 unsigned int MClk, NVClk, cfg1;
454 nvGetClocks(pNv, &MClk, &NVClk);
456 cfg1 = nvReadFB(pNv, NV_PFB_CFG1);
457 sim_data.pix_bpp = (char)pixelDepth;
458 sim_data.enable_video = 0;
459 sim_data.enable_mp = 0;
460 sim_data.memory_width = (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64;
461 sim_data.mem_latency = (char)cfg1 & 0x0F;
462 sim_data.mem_aligned = 1;
463 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01));
464 sim_data.gr_during_vid = 0;
465 sim_data.pclk_khz = VClk;
466 sim_data.mclk_khz = MClk;
467 sim_data.nvclk_khz = NVClk;
468 nv4CalcArbitration(&fifo_data, &sim_data);
471 int b = fifo_data.graphics_burst_size >> 4;
473 while (b >>= 1) (*burst)++;
474 *lwm = fifo_data.graphics_lwm >> 3;
478 void nv10CalcArbitration (
479 nv10_fifo_info *fifo,
483 int data, pagemiss, width, video_enable, bpp;
484 int nvclks, mclks, pclks, vpagemiss, crtpagemiss;
486 int found, mclk_extra, mclk_loop, cbs, m1;
487 int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
488 int us_m, us_m_min, us_n, us_p, crtc_drain_rate;
490 int vpm_us, us_video, cpm_us, us_crt,clwm;
492 int m2us, us_pipe_min, p1clk, p2;
494 int us_min_mclk_extra;
497 pclk_freq = arb->pclk_khz; /* freq in KHz */
498 mclk_freq = arb->mclk_khz;
499 nvclk_freq = arb->nvclk_khz;
500 pagemiss = arb->mem_page_miss;
501 width = arb->memory_width/64;
502 video_enable = arb->enable_video;
504 mp_enable = arb->enable_mp;
509 pclks = 4; /* lwm detect. */
511 nvclks = 3; /* lwm -> sync. */
512 nvclks += 2; /* fbi bus cycles (1 req + 1 busy) */
514 mclks = 1; /* 2 edge sync. may be very close to edge so just put one. */
516 mclks += 1; /* arb_hp_req */
517 mclks += 5; /* ap_hp_req tiling pipeline */
519 mclks += 2; /* tc_req latency fifo */
520 mclks += 2; /* fb_cas_n_ memory request to fbio block */
521 mclks += 7; /* sm_d_rdv data returned from fbio block */
523 /* fb.rd.d.Put_gc need to accumulate 256 bits for read */
524 if (arb->memory_type == 0)
525 if (arb->memory_width == 64) /* 64 bit bus */
530 if (arb->memory_width == 64) /* 64 bit bus */
535 if ((!video_enable) && (arb->memory_width == 128))
537 mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */
542 mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */
543 /* mclk_extra = 4; */ /* Margin of error */
547 nvclks += 1; /* 2 edge sync. may be very close to edge so just put one. */
548 nvclks += 1; /* fbi_d_rdv_n */
549 nvclks += 1; /* Fbi_d_rdata */
550 nvclks += 1; /* crtfifo load */
553 mclks+=4; /* Mp can get in with a burst of 8. */
554 /* Extra clocks determined by heuristics */
562 mclk_loop = mclks+mclk_extra;
563 us_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */
564 us_m_min = mclks * 1000*1000 / mclk_freq; /* Minimum Mclk latency in us */
565 us_min_mclk_extra = min_mclk_extra *1000*1000 / mclk_freq;
566 us_n = nvclks*1000*1000 / nvclk_freq;/* nvclk latency in us */
567 us_p = pclks*1000*1000 / pclk_freq;/* nvclk latency in us */
568 us_pipe_min = us_m_min + us_n + us_p;
570 vus_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */
573 crtc_drain_rate = pclk_freq * bpp/8; /* MB/s */
575 vpagemiss = 1; /* self generating page miss */
576 vpagemiss += 1; /* One higher priority before */
578 crtpagemiss = 2; /* self generating page miss */
580 crtpagemiss += 1; /* if MA0 conflict */
582 vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq;
584 us_video = vpm_us + vus_m; /* Video has separate read return path */
586 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
588 us_video /* Wait for video */
589 +cpm_us /* CRT Page miss */
590 +us_m + us_n +us_p /* other latency */
593 clwm = us_crt * crtc_drain_rate/(1000*1000);
594 clwm++; /* fixed point <= float_point - 1. Fixes that */
596 crtc_drain_rate = pclk_freq * bpp/8; /* bpp * pclk/8 */
598 crtpagemiss = 1; /* self generating page miss */
599 crtpagemiss += 1; /* MA0 page miss */
601 crtpagemiss += 1; /* if MA0 conflict */
602 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
603 us_crt = cpm_us + us_m + us_n + us_p ;
604 clwm = us_crt * crtc_drain_rate/(1000*1000);
605 clwm++; /* fixed point <= float_point - 1. Fixes that */
607 /* Finally, a heuristic check when width == 64 bits */
609 nvclk_fill = nvclk_freq * 8;
610 if(crtc_drain_rate * 100 >= nvclk_fill * 102)
611 clwm = 0xfff; /*Large number to fail */
613 else if(crtc_drain_rate * 100 >= nvclk_fill * 98) {
626 clwm_rnd_down = ((int)clwm/8)*8;
627 if (clwm_rnd_down < clwm)
630 m1 = clwm + cbs - 1024; /* Amount of overfill */
631 m2us = us_pipe_min + us_min_mclk_extra;
633 /* pclk cycles to drain */
634 p1clk = m2us * pclk_freq/(1000*1000);
635 p2 = p1clk * bpp / 8; /* bytes drained. */
637 if((p2 < m1) && (m1 > 0)) {
640 if(min_mclk_extra == 0) {
642 found = 1; /* Can't adjust anymore! */
644 cbs = cbs/2; /* reduce the burst size */
650 if (clwm > 1023){ /* Have some margin */
653 if(min_mclk_extra == 0)
654 found = 1; /* Can't adjust anymore! */
660 if(clwm < (1024-cbs+8)) clwm = 1024-cbs+8;
662 /* printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n", clwm, data ); */
663 fifo->graphics_lwm = data; fifo->graphics_burst_size = cbs;
665 fifo->video_lwm = 1024; fifo->video_burst_size = 512;
669 void nv10UpdateArbitrationSettings (
677 nv10_fifo_info fifo_data;
678 nv10_sim_state sim_data;
679 unsigned int MClk, NVClk, cfg1;
681 nvGetClocks(pNv, &MClk, &NVClk);
683 cfg1 = nvReadFB(pNv, NV_PFB_CFG1);
684 sim_data.pix_bpp = (char)pixelDepth;
685 sim_data.enable_video = 1;
686 sim_data.enable_mp = 0;
687 sim_data.memory_type = (nvReadFB(pNv, NV_PFB_CFG0) & 0x01) ? 1 : 0;
688 sim_data.memory_width = (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64;
689 sim_data.mem_latency = (char)cfg1 & 0x0F;
690 sim_data.mem_aligned = 1;
691 sim_data.mem_page_miss = (char)(((cfg1>>4) &0x0F) + ((cfg1>>31) & 0x01));
692 sim_data.gr_during_vid = 0;
693 sim_data.pclk_khz = VClk;
694 sim_data.mclk_khz = MClk;
695 sim_data.nvclk_khz = NVClk;
696 nv10CalcArbitration(&fifo_data, &sim_data);
697 if (fifo_data.valid) {
698 int b = fifo_data.graphics_burst_size >> 4;
700 while (b >>= 1) (*burst)++;
701 *lwm = fifo_data.graphics_lwm >> 3;
706 void nv30UpdateArbitrationSettings (NVPtr pNv,
710 unsigned int MClk, NVClk;
711 unsigned int fifo_size, burst_size, graphics_lwm;
715 graphics_lwm = fifo_size - burst_size;
717 nvGetClocks(pNv, &MClk, &NVClk);
721 while(burst_size >>= 1) (*burst)++;
722 *lwm = graphics_lwm >> 3;
725 #ifdef XSERVER_LIBPCIACCESS
727 struct pci_device GetDeviceByPCITAG(uint32_t bus, uint32_t dev, uint32_t func)
729 const struct pci_slot_match match[] = { {0, bus, dev, func, 0} };
730 struct pci_device_iterator *iterator;
731 struct pci_device *device;
733 /* assume one device to exist */
734 iterator = pci_slot_match_iterator_create(match);
735 device = pci_device_next(iterator);
740 #endif /* XSERVER_LIBPCIACCESS */
742 void nForceUpdateArbitrationSettings (unsigned VClk,
749 nv10_fifo_info fifo_data;
750 nv10_sim_state sim_data;
751 unsigned int M, N, P, pll, MClk, NVClk, memctrl;
753 #ifdef XSERVER_LIBPCIACCESS
754 struct pci_device tmp;
755 #endif /* XSERVER_LIBPCIACCESS */
757 if((pNv->Chipset & 0x0FF0) == CHIPSET_NFORCE) {
758 unsigned int uMClkPostDiv;
760 #ifdef XSERVER_LIBPCIACCESS
761 tmp = GetDeviceByPCITAG(0, 0, 3);
762 PCI_DEV_READ_LONG(&tmp, 0x6C, &(uMClkPostDiv));
763 uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
765 uMClkPostDiv = (pciReadLong(pciTag(0, 0, 3), 0x6C) >> 8) & 0xf;
766 #endif /* XSERVER_LIBPCIACCESS */
767 if(!uMClkPostDiv) uMClkPostDiv = 4;
768 MClk = 400000 / uMClkPostDiv;
770 #ifdef XSERVER_LIBPCIACCESS
771 tmp = GetDeviceByPCITAG(0, 0, 5);
772 PCI_DEV_READ_LONG(&tmp, 0x4C, &(MClk));
775 MClk = pciReadLong(pciTag(0, 0, 5), 0x4C) / 1000;
776 #endif /* XSERVER_LIBPCIACCESS */
779 pll = NVReadRAMDAC(pNv, 0, NV_RAMDAC_NVPLL);
780 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
781 NVClk = (N * pNv->CrystalFreqKHz / M) >> P;
782 sim_data.pix_bpp = (char)pixelDepth;
783 sim_data.enable_video = 0;
784 sim_data.enable_mp = 0;
785 #ifdef XSERVER_LIBPCIACCESS
786 tmp = GetDeviceByPCITAG(0, 0, 1);
787 PCI_DEV_READ_LONG(&tmp, 0x7C, &(sim_data.memory_type));
788 sim_data.memory_type = (sim_data.memory_type >> 12) & 1;
790 sim_data.memory_type = (pciReadLong(pciTag(0, 0, 1), 0x7C) >> 12) & 1;
791 #endif /* XSERVER_LIBPCIACCESS */
792 sim_data.memory_width = 64;
794 #ifdef XSERVER_LIBPCIACCESS
795 /* This offset is 0, is this even usefull? */
796 tmp = GetDeviceByPCITAG(0, 0, 3);
797 PCI_DEV_READ_LONG(&tmp, 0x00, &(memctrl));
800 memctrl = pciReadLong(pciTag(0, 0, 3), 0x00) >> 16;
801 #endif /* XSERVER_LIBPCIACCESS */
803 if((memctrl == 0x1A9) || (memctrl == 0x1AB) || (memctrl == 0x1ED)) {
805 #ifdef XSERVER_LIBPCIACCESS
806 tmp = GetDeviceByPCITAG(0, 0, 2);
807 PCI_DEV_READ_LONG(&tmp, 0x40, &(dimm[0]));
808 PCI_DEV_READ_LONG(&tmp, 0x44, &(dimm[1]));
809 PCI_DEV_READ_LONG(&tmp, 0x48, &(dimm[2]));
811 for (i = 0; i < 3; i++) {
812 dimm[i] = (dimm[i] >> 8) & 0x4F;
815 dimm[0] = (pciReadLong(pciTag(0, 0, 2), 0x40) >> 8) & 0x4F;
816 dimm[1] = (pciReadLong(pciTag(0, 0, 2), 0x44) >> 8) & 0x4F;
817 dimm[2] = (pciReadLong(pciTag(0, 0, 2), 0x48) >> 8) & 0x4F;
820 if((dimm[0] + dimm[1]) != dimm[2]) {
822 "your nForce DIMMs are not arranged in optimal banks!\n");
826 sim_data.mem_latency = 3;
827 sim_data.mem_aligned = 1;
828 sim_data.mem_page_miss = 10;
829 sim_data.gr_during_vid = 0;
830 sim_data.pclk_khz = VClk;
831 sim_data.mclk_khz = MClk;
832 sim_data.nvclk_khz = NVClk;
833 nv10CalcArbitration(&fifo_data, &sim_data);
836 int b = fifo_data.graphics_burst_size >> 4;
838 while (b >>= 1) (*burst)++;
839 *lwm = fifo_data.graphics_lwm >> 3;
844 /****************************************************************************\
846 * RIVA Mode State Routines *
848 \****************************************************************************/
851 * Calculate the Video Clock parameters for the PLL.
853 static void CalcVClock (
860 unsigned lowM, highM;
861 unsigned DeltaNew, DeltaOld;
865 DeltaOld = 0xFFFFFFFF;
867 VClk = (unsigned)clockIn;
869 if (pNv->CrystalFreqKHz == 13500) {
877 for (P = 0; P <= 4; P++) {
879 if ((Freq >= 128000) && (Freq <= 350000)) {
880 for (M = lowM; M <= highM; M++) {
881 N = ((VClk << P) * M) / pNv->CrystalFreqKHz;
883 Freq = ((pNv->CrystalFreqKHz * N) / M) >> P;
885 DeltaNew = Freq - VClk;
887 DeltaNew = VClk - Freq;
888 if (DeltaNew < DeltaOld) {
889 *pllOut = (P << 16) | (N << 8) | M;
899 static void CalcVClock2Stage (
907 unsigned DeltaNew, DeltaOld;
911 DeltaOld = 0xFFFFFFFF;
913 *pllBOut = 0x80000401; /* fixed at x4 for now */
915 VClk = (unsigned)clockIn;
917 for (P = 0; P <= 6; P++) {
919 if ((Freq >= 400000) && (Freq <= 1000000)) {
920 for (M = 1; M <= 13; M++) {
921 N = ((VClk << P) * M) / (pNv->CrystalFreqKHz << 2);
922 if((N >= 5) && (N <= 255)) {
923 Freq = (((pNv->CrystalFreqKHz << 2) * N) / M) >> P;
925 DeltaNew = Freq - VClk;
927 DeltaNew = VClk - Freq;
928 if (DeltaNew < DeltaOld) {
929 *pllOut = (P << 16) | (N << 8) | M;
940 * Calculate extended mode parameters (SVGA) and save in a
941 * mode state structure.
943 void NVCalcStateExt (
945 RIVA_HW_STATE *state,
954 int pixelDepth, VClk = 0;
958 * Save mode parameters.
960 state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */
961 state->width = width;
962 state->height = height;
964 * Extended RIVA registers.
966 pixelDepth = (bpp + 1)/8;
968 CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB, pNv);
970 CalcVClock(dotClock, &VClk, &state->pll, pNv);
972 switch (pNv->Architecture)
975 nv4UpdateArbitrationSettings(VClk,
977 &(state->arbitration0),
978 &(state->arbitration1),
980 state->cursor0 = 0x00;
981 state->cursor1 = 0xbC;
982 if (flags & V_DBLSCAN)
984 state->cursor2 = 0x00000000;
985 state->pllsel = 0x10000700;
986 state->config = 0x00001114;
987 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
988 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
994 if(((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
995 ((pNv->Chipset & 0xfff0) == CHIPSET_C512))
997 state->arbitration0 = 128;
998 state->arbitration1 = 0x0480;
1000 if(((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
1001 ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2))
1003 nForceUpdateArbitrationSettings(VClk,
1005 &(state->arbitration0),
1006 &(state->arbitration1),
1008 } else if(pNv->Architecture < NV_ARCH_30) {
1009 nv10UpdateArbitrationSettings(VClk,
1011 &(state->arbitration0),
1012 &(state->arbitration1),
1015 nv30UpdateArbitrationSettings(pNv,
1016 &(state->arbitration0),
1017 &(state->arbitration1));
1019 CursorStart = pNv->Cursor->offset;
1020 state->cursor0 = 0x80 | (CursorStart >> 17);
1021 state->cursor1 = (CursorStart >> 11) << 2;
1022 state->cursor2 = CursorStart >> 24;
1023 if (flags & V_DBLSCAN)
1024 state->cursor1 |= 2;
1025 state->pllsel = 0x10000700;
1026 state->config = nvReadFB(pNv, NV_PFB_CFG0);
1027 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
1028 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
1032 if(bpp != 8) /* DirectColor */
1033 state->general |= 0x00000030;
1035 state->repaint0 = (((width / 8) * pixelDepth) & 0x700) >> 3;
1036 state->pixel = (pixelDepth > 2) ? 3 : pixelDepth;
1040 void NVLoadStateExt (
1042 RIVA_HW_STATE *state
1045 NVPtr pNv = NVPTR(pScrn);
1048 if(pNv->Architecture >= NV_ARCH_40) {
1049 switch(pNv->Chipset & 0xfff0) {
1058 temp = nvReadCurRAMDAC(pNv, NV_RAMDAC_TEST_CONTROL);
1059 nvWriteCurRAMDAC(pNv, NV_RAMDAC_TEST_CONTROL, temp | 0x00100000);
1066 if(pNv->Architecture >= NV_ARCH_10) {
1068 nvWriteCRTC(pNv, 0, NV_CRTC_FSEL, state->head);
1069 nvWriteCRTC(pNv, 1, NV_CRTC_FSEL, state->head2);
1071 temp = nvReadCurRAMDAC(pNv, NV_RAMDAC_NV10_CURSYNC);
1072 nvWriteCurRAMDAC(pNv, NV_RAMDAC_NV10_CURSYNC, temp | (1 << 25));
1074 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
1075 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
1076 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
1077 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
1078 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1079 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1080 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1081 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1082 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, 0);
1084 nvWriteCurCRTC(pNv, NV_CRTC_CURSOR_CONFIG, state->cursorConfig);
1085 nvWriteCurCRTC(pNv, NV_CRTC_0830, state->displayV - 3);
1086 nvWriteCurCRTC(pNv, NV_CRTC_0834, state->displayV - 1);
1088 if(pNv->FlatPanel) {
1089 if((pNv->Chipset & 0x0ff0) == CHIPSET_NV11) {
1090 nvWriteCurRAMDAC(pNv, NV_RAMDAC_DITHER_NV11, state->dither);
1093 nvWriteCurRAMDAC(pNv, NV_RAMDAC_FP_DITHER, state->dither);
1096 nvWriteVGA(pNv, NV_VGA_CRTCX_FP_HTIMING, state->timingH);
1097 nvWriteVGA(pNv, NV_VGA_CRTCX_FP_VTIMING, state->timingV);
1098 nvWriteVGA(pNv, NV_VGA_CRTCX_BUFFER, 0xfa);
1101 nvWriteVGA(pNv, NV_VGA_CRTCX_EXTRA, state->extra);
1104 nvWriteVGA(pNv, NV_VGA_CRTCX_REPAINT0, state->repaint0);
1105 nvWriteVGA(pNv, NV_VGA_CRTCX_REPAINT1, state->repaint1);
1106 nvWriteVGA(pNv, NV_VGA_CRTCX_LSR, state->screen);
1107 nvWriteVGA(pNv, NV_VGA_CRTCX_PIXEL, state->pixel);
1108 nvWriteVGA(pNv, NV_VGA_CRTCX_HEB, state->horiz);
1109 nvWriteVGA(pNv, NV_VGA_CRTCX_FIFO1, state->fifo);
1110 nvWriteVGA(pNv, NV_VGA_CRTCX_FIFO0, state->arbitration0);
1111 nvWriteVGA(pNv, NV_VGA_CRTCX_FIFO_LWM, state->arbitration1);
1112 if(pNv->Architecture >= NV_ARCH_30) {
1113 nvWriteVGA(pNv, NV_VGA_CRTCX_FIFO_LWM_NV30, state->arbitration1 >> 8);
1116 nvWriteVGA(pNv, NV_VGA_CRTCX_CURCTL0, state->cursor0);
1117 nvWriteVGA(pNv, NV_VGA_CRTCX_CURCTL1, state->cursor1);
1118 if(pNv->Architecture == NV_ARCH_40) { /* HW bug */
1119 volatile CARD32 curpos = nvReadCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS);
1120 nvWriteCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS, curpos);
1122 nvWriteVGA(pNv, NV_VGA_CRTCX_CURCTL2, state->cursor2);
1123 nvWriteVGA(pNv, NV_VGA_CRTCX_INTERLACE, state->interlace);
1125 if(!pNv->FlatPanel) {
1126 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
1127 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL, state->vpll);
1129 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2, state->vpll2);
1130 if(pNv->twoStagePLL) {
1131 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B, state->vpllB);
1132 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B, state->vpll2B);
1135 nvWriteCurRAMDAC(pNv, NV_RAMDAC_FP_CONTROL, state->scale);
1136 nvWriteCurRAMDAC(pNv, NV_RAMDAC_FP_HCRTC, state->crtcSync);
1138 nvWriteCurRAMDAC(pNv, NV_RAMDAC_GENERAL_CONTROL, state->general);
1140 nvWriteCurCRTC(pNv, NV_CRTC_INTR_EN_0, 0);
1141 nvWriteCurCRTC(pNv, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
1143 pNv->CurrentState = state;
1146 void NVUnloadStateExt
1149 RIVA_HW_STATE *state
1152 state->repaint0 = nvReadVGA(pNv, NV_VGA_CRTCX_REPAINT0);
1153 state->repaint1 = nvReadVGA(pNv, NV_VGA_CRTCX_REPAINT1);
1154 state->screen = nvReadVGA(pNv, NV_VGA_CRTCX_LSR);
1155 state->pixel = nvReadVGA(pNv, NV_VGA_CRTCX_PIXEL);
1156 state->horiz = nvReadVGA(pNv, NV_VGA_CRTCX_HEB);
1157 state->fifo = nvReadVGA(pNv, NV_VGA_CRTCX_FIFO1);
1158 state->arbitration0 = nvReadVGA(pNv, NV_VGA_CRTCX_FIFO0);
1159 state->arbitration1 = nvReadVGA(pNv, NV_VGA_CRTCX_FIFO_LWM);
1160 if(pNv->Architecture >= NV_ARCH_30) {
1161 state->arbitration1 |= (nvReadVGA(pNv, NV_VGA_CRTCX_FIFO_LWM_NV30) & 1) << 8;
1163 state->cursor0 = nvReadVGA(pNv, NV_VGA_CRTCX_CURCTL0);
1164 state->cursor1 = nvReadVGA(pNv, NV_VGA_CRTCX_CURCTL1);
1165 state->cursor2 = nvReadVGA(pNv, NV_VGA_CRTCX_CURCTL2);
1166 state->interlace = nvReadVGA(pNv, NV_VGA_CRTCX_INTERLACE);
1168 state->vpll = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL);
1170 state->vpll2 = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2);
1171 if(pNv->twoStagePLL) {
1172 state->vpllB = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B);
1173 state->vpll2B = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B);
1175 state->pllsel = NVReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT);
1176 state->general = nvReadCurRAMDAC(pNv, NV_RAMDAC_GENERAL_CONTROL);
1177 state->scale = nvReadCurRAMDAC(pNv, NV_RAMDAC_FP_CONTROL);
1178 state->config = nvReadFB(pNv, NV_PFB_CFG0);
1180 if(pNv->Architecture >= NV_ARCH_10) {
1182 state->head = nvReadCRTC(pNv, 0, NV_CRTC_FSEL);
1183 state->head2 = nvReadCRTC(pNv, 1, NV_CRTC_FSEL);
1184 state->crtcOwner = nvReadVGA(pNv, NV_VGA_CRTCX_OWNER);
1186 state->extra = nvReadVGA(pNv, NV_VGA_CRTCX_EXTRA);
1188 state->cursorConfig = nvReadCurCRTC(pNv, NV_CRTC_CURSOR_CONFIG);
1190 if((pNv->Chipset & 0x0ff0) == CHIPSET_NV11) {
1191 state->dither = nvReadCurRAMDAC(pNv, NV_RAMDAC_DITHER_NV11);
1194 state->dither = nvReadCurRAMDAC(pNv, NV_RAMDAC_FP_DITHER);
1197 if(pNv->FlatPanel) {
1198 state->timingH = nvReadVGA(pNv, NV_VGA_CRTCX_FP_HTIMING);
1199 state->timingV = nvReadVGA(pNv, NV_VGA_CRTCX_FP_VTIMING);
1203 if(pNv->FlatPanel) {
1204 state->crtcSync = nvReadCurRAMDAC(pNv, NV_RAMDAC_FP_HCRTC);
1208 void NVSetStartAddress (
1213 nvWriteCurCRTC(pNv, NV_CRTC_START, start);