2 * Copyright 2006 Dave Airlie
3 * Copyright 2007 Maarten Maathuis
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
26 * decleration is at the bottom of this file as it is rather ugly
41 #include "mipointer.h"
42 #include "windowstr.h"
44 #include <X11/extensions/render.h>
47 #include "nv_include.h"
51 #define CRTC_INDEX 0x3d4
52 #define CRTC_DATA 0x3d5
53 #define CRTC_IN_STAT_1 0x3da
55 #define WHITE_VALUE 0x3F
56 #define BLACK_VALUE 0x00
57 #define OVERSCAN_VALUE 0x01
59 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
60 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override);
61 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
62 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
63 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
64 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
66 static CARD8 NVReadPVIO(xf86CrtcPtr crtc, CARD32 address)
68 ScrnInfoPtr pScrn = crtc->scrn;
69 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
70 NVPtr pNv = NVPTR(pScrn);
72 /* Only NV4x have two pvio ranges */
73 if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
74 return NV_RD08(pNv->PVIO1, address);
76 return NV_RD08(pNv->PVIO0, address);
80 static void NVWritePVIO(xf86CrtcPtr crtc, CARD32 address, CARD8 value)
82 ScrnInfoPtr pScrn = crtc->scrn;
83 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
84 NVPtr pNv = NVPTR(pScrn);
86 /* Only NV4x have two pvio ranges */
87 if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
88 NV_WR08(pNv->PVIO1, address, value);
90 NV_WR08(pNv->PVIO0, address, value);
94 static void NVWriteMiscOut(xf86CrtcPtr crtc, CARD8 value)
96 NVWritePVIO(crtc, VGA_MISC_OUT_W, value);
99 static CARD8 NVReadMiscOut(xf86CrtcPtr crtc)
101 return NVReadPVIO(crtc, VGA_MISC_OUT_R);
104 void NVWriteVGA(NVPtr pNv, int head, CARD8 index, CARD8 value)
106 volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
108 NV_WR08(pCRTCReg, CRTC_INDEX, index);
109 NV_WR08(pCRTCReg, CRTC_DATA, value);
112 CARD8 NVReadVGA(NVPtr pNv, int head, CARD8 index)
114 volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
116 NV_WR08(pCRTCReg, CRTC_INDEX, index);
117 return NV_RD08(pCRTCReg, CRTC_DATA);
120 /* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
121 * I suspect they in fact do nothing, but are merely a way to carry useful
122 * per-head variables around
126 * 0x00 index to the appropriate dcb entry (or 7f for inactive)
127 * 0x02 dcb entry's "or" value (or 00 for inactive)
128 * 0x03 bit0 set for dual link (LVDS, possibly elsewhere too)
129 * 0x08 or 0x09 pxclk in MHz
130 * 0x0f laptop panel info - low nibble for PEXTDEV_BOOT strap
131 * high nibble for xlat strap value
134 void NVWriteVGACR5758(NVPtr pNv, int head, uint8_t index, uint8_t value)
136 NVWriteVGA(pNv, head, 0x57, index);
137 NVWriteVGA(pNv, head, 0x58, value);
140 uint8_t NVReadVGACR5758(NVPtr pNv, int head, uint8_t index)
142 NVWriteVGA(pNv, head, 0x57, index);
143 return NVReadVGA(pNv, head, 0x58);
146 void NVWriteVgaCrtc(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
148 ScrnInfoPtr pScrn = crtc->scrn;
149 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
150 NVPtr pNv = NVPTR(pScrn);
152 NVWriteVGA(pNv, nv_crtc->head, index, value);
155 CARD8 NVReadVgaCrtc(xf86CrtcPtr crtc, CARD8 index)
157 ScrnInfoPtr pScrn = crtc->scrn;
158 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
159 NVPtr pNv = NVPTR(pScrn);
161 return NVReadVGA(pNv, nv_crtc->head, index);
164 static void NVWriteVgaSeq(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
166 NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
167 NVWritePVIO(crtc, VGA_SEQ_DATA, value);
170 static CARD8 NVReadVgaSeq(xf86CrtcPtr crtc, CARD8 index)
172 NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
173 return NVReadPVIO(crtc, VGA_SEQ_DATA);
176 static void NVWriteVgaGr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
178 NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
179 NVWritePVIO(crtc, VGA_GRAPH_DATA, value);
182 static CARD8 NVReadVgaGr(xf86CrtcPtr crtc, CARD8 index)
184 NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
185 return NVReadPVIO(crtc, VGA_GRAPH_DATA);
189 static void NVWriteVgaAttr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
191 ScrnInfoPtr pScrn = crtc->scrn;
192 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
193 NVPtr pNv = NVPTR(pScrn);
194 volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
196 NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
197 if (nv_crtc->paletteEnabled)
201 NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
202 NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
205 static CARD8 NVReadVgaAttr(xf86CrtcPtr crtc, CARD8 index)
207 ScrnInfoPtr pScrn = crtc->scrn;
208 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
209 NVPtr pNv = NVPTR(pScrn);
210 volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
212 NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
213 if (nv_crtc->paletteEnabled)
217 NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
218 return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
221 void NVCrtcSetOwner(xf86CrtcPtr crtc)
223 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
224 ScrnInfoPtr pScrn = crtc->scrn;
225 NVPtr pNv = NVPTR(pScrn);
226 /* Non standard beheaviour required by NV11 */
228 uint8_t owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
229 ErrorF("pre-Owner: 0x%X\n", owner);
231 uint32_t pbus84 = nvReadMC(pNv, 0x1084);
232 ErrorF("pbus84: 0x%X\n", pbus84);
234 ErrorF("pbus84: 0x%X\n", pbus84);
235 nvWriteMC(pNv, 0x1084, pbus84);
237 /* The blob never writes owner to pcio1, so should we */
238 if (pNv->NVArch == 0x11) {
239 NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, 0xff);
241 NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, nv_crtc->head * 0x3);
242 owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
243 ErrorF("post-Owner: 0x%X\n", owner);
245 ErrorF("pNv pointer is NULL\n");
250 NVEnablePalette(xf86CrtcPtr crtc)
252 ScrnInfoPtr pScrn = crtc->scrn;
253 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
254 NVPtr pNv = NVPTR(pScrn);
255 volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
257 NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
258 NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
259 nv_crtc->paletteEnabled = TRUE;
263 NVDisablePalette(xf86CrtcPtr crtc)
265 ScrnInfoPtr pScrn = crtc->scrn;
266 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
267 NVPtr pNv = NVPTR(pScrn);
268 volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
270 NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
271 NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
272 nv_crtc->paletteEnabled = FALSE;
275 static void NVWriteVgaReg(xf86CrtcPtr crtc, CARD32 reg, CARD8 value)
277 ScrnInfoPtr pScrn = crtc->scrn;
278 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
279 NVPtr pNv = NVPTR(pScrn);
280 volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
282 NV_WR08(pCRTCReg, reg, value);
285 /* perform a sequencer reset */
286 static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
289 NVWriteVgaSeq(crtc, 0x00, 0x1);
291 NVWriteVgaSeq(crtc, 0x00, 0x3);
294 static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
299 tmp = NVReadVgaSeq(crtc, 0x1);
300 NVVgaSeqReset(crtc, TRUE);
301 NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
303 NVEnablePalette(crtc);
306 * Reenable sequencer, then turn on screen.
308 tmp = NVReadVgaSeq(crtc, 0x1);
309 NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20); /* reenable display */
310 NVVgaSeqReset(crtc, FALSE);
312 NVDisablePalette(crtc);
316 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool Lock)
320 NVCrtcSetOwner(crtc);
322 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57);
323 cr11 = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE);
324 if (Lock) cr11 |= 0x80;
326 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE, cr11);
330 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
332 ScrnInfoPtr pScrn = crtc->scrn;
333 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
335 for (i = 0; i < xf86_config->num_output; i++) {
336 xf86OutputPtr output = xf86_config->output[i];
338 if (output->crtc == crtc) {
347 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
349 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
352 for (i = 0; i < xf86_config->num_crtc; i++) {
353 xf86CrtcPtr crtc = xf86_config->crtc[i];
354 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
355 if (nv_crtc->head == index)
363 * Calculate the Video Clock parameters for the PLL.
365 /* Code taken from NVClock, with permission of the author (being a GPL->MIT code transfer). */
368 CalculateVClkNV4x_SingleVCO(NVPtr pNv, struct pll_lims *pll_lim, uint32_t clockIn, uint32_t *n1_best, uint32_t *m1_best, uint32_t *p_best)
370 uint32_t clock, M, N, P;
371 uint32_t delta, bestDelta, minM, maxM, minN, maxN, maxP;
372 uint32_t minVCOInputFreq, minVCOFreq, maxVCOFreq;
374 uint32_t refClk = pNv->CrystalFreqKHz;
377 /* bios clocks are in MHz, we use KHz */
378 minVCOInputFreq = pll_lim->vco1.min_inputfreq*1000;
379 minVCOFreq = pll_lim->vco1.minfreq*1000;
380 maxVCOFreq = pll_lim->vco1.maxfreq*1000;
381 minM = pll_lim->vco1.min_m;
382 maxM = pll_lim->vco1.max_m;
383 minN = pll_lim->vco1.min_n;
384 maxN = pll_lim->vco1.max_n;
388 /* The optimal frequency for the PLL to work at is somewhere in the center of its range.
389 / Choose a post divider in such a way to achieve this.
390 / The G8x nv driver does something similar but they they derive a minP and maxP. That
391 / doesn't seem required as you get so many matching clocks that you don't enter a second
392 / iteration for P. (The minP / maxP values in the nv driver only differ at most 1, so it is for
393 / some rare corner cases.
395 for (P=0, VCOFreq=maxVCOFreq/2; clockIn<=VCOFreq && P <= maxP; P++)
400 /* Calculate the m and n values. There are a lot of values which give the same speed;
401 / We choose the speed for which the difference with the request speed is as small as possible.
403 for (M=minM; M<=maxM; M++)
405 /* The VCO has a minimum input frequency */
406 if ((refClk/M) < minVCOInputFreq)
409 for (N=minN; N<=maxN; N++)
411 /* Calculate the frequency generated by VCO1 */
412 clock = (int)(refClk * N / (float)M);
414 /* Verify if the clock lies within the output limits of VCO1 */
415 if (clock < minVCOFreq)
417 else if (clock > maxVCOFreq) /* It is no use to continue as the clock will only become higher */
421 delta = abs((int)(clockIn - clock));
422 /* When the difference is 0 or less than .5% accept the speed */
423 if (((delta == 0) || ((float)delta/(float)clockIn <= 0.005)))
431 /* When the new difference is smaller than the old one, use this one */
432 if (delta < bestDelta)
444 CalculateVClkNV4x_DoubleVCO(NVPtr pNv, struct pll_lims *pll_lim, uint32_t clockIn, uint32_t *n1_best, uint32_t *n2_best, uint32_t *m1_best, uint32_t *m2_best, uint32_t *p_best)
446 uint32_t clock1, clock2, M, M2, N, N2, P;
447 uint32_t delta, bestDelta, minM, minM2, maxM, maxM2, minN, minN2, maxN, maxN2, maxP;
448 uint32_t minVCOInputFreq, minVCO2InputFreq, maxVCO2InputFreq, minVCOFreq, minVCO2Freq, maxVCOFreq, maxVCO2Freq;
449 uint32_t VCO2Freq, maxClock;
450 uint32_t refClk = pNv->CrystalFreqKHz;
453 /* bios clocks are in MHz, we use KHz */
454 minVCOInputFreq = pll_lim->vco1.min_inputfreq*1000;
455 minVCOFreq = pll_lim->vco1.minfreq*1000;
456 maxVCOFreq = pll_lim->vco1.maxfreq*1000;
457 minM = pll_lim->vco1.min_m;
458 maxM = pll_lim->vco1.max_m;
459 minN = pll_lim->vco1.min_n;
460 maxN = pll_lim->vco1.max_n;
462 minVCO2InputFreq = pll_lim->vco2.min_inputfreq*1000;
463 maxVCO2InputFreq = pll_lim->vco2.max_inputfreq*1000;
464 minVCO2Freq = pll_lim->vco2.minfreq*1000;
465 maxVCO2Freq = pll_lim->vco2.maxfreq*1000;
466 minM2 = pll_lim->vco2.min_m;
467 maxM2 = pll_lim->vco2.max_m;
468 minN2 = pll_lim->vco2.min_n;
469 maxN2 = pll_lim->vco2.max_n;
473 maxClock = maxVCO2Freq;
474 /* If the requested clock is behind the bios limits, try it anyway */
475 if (clockIn > maxVCO2Freq)
476 maxClock = clockIn + clockIn/200; /* Add a .5% margin */
478 /* The optimal frequency for the PLL to work at is somewhere in the center of its range.
479 / Choose a post divider in such a way to achieve this.
480 / The G8x nv driver does something similar but they they derive a minP and maxP. That
481 / doesn't seem required as you get so many matching clocks that you don't enter a second
482 / iteration for P. (The minP / maxP values in the nv driver only differ at most 1, so it is for
483 / some rare corner cases.
485 for (P=0, VCO2Freq=maxClock/2; clockIn<=VCO2Freq && P <= maxP; P++)
490 /* The PLLs on Geforce6/7 hardware can operate in a single stage made with only 1 VCO
491 / and a cascade mode of two VCOs. This second mode is in general used for relatively high
492 / frequencies. The loop below calculates the divider and multiplier ratios for the cascade
493 / mode. The code takes into account limits defined in the video bios.
495 for (M=minM; M<=maxM; M++)
497 /* The VCO has a minimum input frequency */
498 if ((refClk/M) < minVCOInputFreq)
501 for (N=minN; N<=maxN; N++)
503 /* Calculate the frequency generated by VCO1 */
504 clock1 = (int)(refClk * N / (float)M);
505 /* Verify if the clock lies within the output limits of VCO1 */
506 if ( (clock1 < minVCOFreq) )
508 else if (clock1 > maxVCOFreq) /* For future N, the clock will only increase so stop; xorg nv continues but that is useless */
511 for (M2=minM2; M2<=maxM2; M2++)
513 /* The clock fed to the second VCO needs to lie within a certain input range */
514 if (clock1 / M2 < minVCO2InputFreq)
516 else if (clock1 / M2 > maxVCO2InputFreq)
519 N2 = (int)((float)((clockIn << P) * M * M2) / (float)(refClk * N)+.5);
520 if( (N2 < minN2) || (N2 > maxN2) )
523 /* The clock before being fed to the post-divider needs to lie within a certain range.
524 / Further there are some limits on N2/M2.
526 clock2 = (int)((float)(N*N2)/(M*M2) * refClk);
527 if( (clock2 < minVCO2Freq) || (clock2 > maxClock))// || ((N2 / M2) < 4) || ((N2 / M2) > 10) )
530 /* The post-divider delays the 'high' clock to create a low clock if requested.
531 / This post-divider exists because the VCOs can only generate frequencies within
532 / a limited frequency range. This range has been tuned to lie around half of its max
533 / input frequency. It tries to calculate all clocks (including lower ones) around this
534 / 'center' frequency.
537 delta = abs((int)(clockIn - clock2));
539 /* When the difference is 0 or less than .5% accept the speed */
540 if (((delta == 0) || ((float)delta/(float)clockIn <= 0.005)))
550 /* When the new difference is smaller than the old one, use this one */
551 if (delta < bestDelta)
565 /* BIG NOTE: modifying vpll1 and vpll2 does not work, what bit is the switch to allow it? */
567 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
568 /* They are only valid for NV4x, appearantly reordered for NV5x */
569 /* gpu pll: 0x4000 + 0x4004
570 * unknown pll: 0x4008 + 0x400c
571 * vpll1: 0x4010 + 0x4014
572 * vpll2: 0x4018 + 0x401c
573 * unknown pll: 0x4020 + 0x4024
574 * unknown pll: 0x4038 + 0x403c
575 * Some of the unknown's are probably memory pll's.
576 * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
577 * 1 and 2 refer to the registers of each pair. There is only one post divider.
578 * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
579 * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
580 * bit8: A switch that turns of the second divider and multiplier off.
581 * bit12: Also a switch, i haven't seen it yet.
582 * bit16-19: p-divider
583 * but 28-31: Something related to the mode that is used (see bit8).
584 * 2) bit0-7: m-divider (a)
585 * bit8-15: n-multiplier (a)
586 * bit16-23: m-divider (b)
587 * bit24-31: n-multiplier (b)
590 /* Modifying the gpu pll for example requires:
591 * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
592 * This is not needed for the vpll's which have their own bits.
598 uint32_t requested_clock,
599 uint32_t *given_clock,
607 NVPtr pNv = NVPTR(pScrn);
608 struct pll_lims pll_lim;
609 /* We have 2 mulitpliers, 2 dividers and one post divider */
610 /* Note that p is only 3 bits */
611 uint32_t m1_best = 0, m2_best = 0, n1_best = 0, n2_best = 0, p_best = 0;
612 uint32_t special_bits = 0;
615 if (!get_pll_limits(pScrn, VPLL1, &pll_lim))
618 if (!get_pll_limits(pScrn, VPLL2, &pll_lim))
621 if (requested_clock < pll_lim.vco1.maxfreq*1000) { /* single VCO */
623 /* Turn the second set of divider and multiplier off */
624 /* Bogus data, the same nvidia uses */
627 CalculateVClkNV4x_SingleVCO(pNv, &pll_lim, requested_clock, &n1_best, &m1_best, &p_best);
628 } else { /* dual VCO */
630 CalculateVClkNV4x_DoubleVCO(pNv, &pll_lim, requested_clock, &n1_best, &n2_best, &m1_best, &m2_best, &p_best);
633 /* Are this all (relevant) G70 cards? */
634 if (pNv->NVArch == 0x4B || pNv->NVArch == 0x46 || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
635 /* This is a big guess, but should be reasonable until we can narrow it down. */
643 /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
644 /* Let's keep the special bits, if the bios already set them */
645 *pll_a = (special_bits << 30) | (p_best << 16) | (n1_best << 8) | (m1_best << 0);
646 *pll_b = (1 << 31) | (n2_best << 8) | (m2_best << 0);
650 *reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
652 *reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
656 *reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
658 *reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
663 ErrorF("vpll: n1 %d m1 %d p %d db1_ratio %d\n", n1_best, m1_best, p_best, *db1_ratio);
665 ErrorF("vpll: n1 %d n2 %d m1 %d m2 %d p %d db1_ratio %d\n", n1_best, n2_best, m1_best, m2_best, p_best, *db1_ratio);
669 static void nv40_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
671 state->vpll1_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
672 state->vpll1_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
673 state->vpll2_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
674 state->vpll2_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
675 state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
676 state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
677 state->reg580 = nvReadRAMDAC0(pNv, NV_RAMDAC_580);
678 state->reg594 = nvReadRAMDAC0(pNv, NV_RAMDAC_594);
681 static void nv40_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
683 ScrnInfoPtr pScrn = crtc->scrn;
684 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
685 NVPtr pNv = NVPTR(pScrn);
686 CARD32 fp_debug_0[2];
688 fp_debug_0[0] = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
689 fp_debug_0[1] = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
691 uint32_t reg_c040_old = nvReadMC(pNv, 0xc040);
693 /* The TMDS_PLL switch is on the actual ramdac */
694 if (state->crosswired) {
697 ErrorF("Crosswired pll state load\n");
703 if (state->vpll2_b) {
704 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0,
705 fp_debug_0[index[1]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
707 /* Wait for the situation to stabilise */
710 uint32_t reg_c040 = pNv->misc_info.reg_c040;
711 /* for vpll2 change bits 18 and 19 are disabled */
712 reg_c040 &= ~(0x3 << 18);
713 nvWriteMC(pNv, 0xc040, reg_c040);
715 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
716 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
718 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2_a);
719 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2_b);
721 ErrorF("writing pllsel %08X\n", state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
722 /* Let's keep the primary vpll off */
723 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
725 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
726 ErrorF("writing reg580 %08X\n", state->reg580);
728 /* We need to wait a while */
730 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
732 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[1]]);
734 /* Wait for the situation to stabilise */
738 if (state->vpll1_b) {
739 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0,
740 fp_debug_0[index[0]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
742 /* Wait for the situation to stabilise */
745 uint32_t reg_c040 = pNv->misc_info.reg_c040;
746 /* for vpll2 change bits 16 and 17 are disabled */
747 reg_c040 &= ~(0x3 << 16);
748 nvWriteMC(pNv, 0xc040, reg_c040);
750 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
751 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
753 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll1_a);
754 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpll1_b);
756 ErrorF("writing pllsel %08X\n", state->pllsel);
757 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
759 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
760 ErrorF("writing reg580 %08X\n", state->reg580);
762 /* We need to wait a while */
764 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
766 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[0]]);
768 /* Wait for the situation to stabilise */
772 /* Let's be sure not to wake up any crtc's from dpms. */
773 /* But we do want to keep our newly set crtc awake. */
774 if (nv_crtc->head == 1) {
775 nvWriteMC(pNv, 0xc040, reg_c040_old | (pNv->misc_info.reg_c040 & (0x3 << 18)));
777 nvWriteMC(pNv, 0xc040, reg_c040_old | (pNv->misc_info.reg_c040 & (0x3 << 16)));
780 ErrorF("writing sel_clk %08X\n", state->sel_clk);
781 nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
783 ErrorF("writing reg594 %08X\n", state->reg594);
784 nvWriteRAMDAC0(pNv, NV_RAMDAC_594, state->reg594);
787 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
789 state->vpll = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
791 state->vpll2 = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
793 if(pNv->twoStagePLL) {
794 state->vpllB = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
795 state->vpll2B = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
797 state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
798 state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
802 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
804 /* This sequence is important, the NV28 is very sensitive in this area. */
805 /* Keep pllsel last and sel_clk first. */
806 ErrorF("writing sel_clk %08X\n", state->sel_clk);
807 nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
811 ErrorF("writing vpll2 %08X\n", state->vpll2);
812 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2);
814 if(pNv->twoStagePLL) {
815 ErrorF("writing vpll2B %08X\n", state->vpll2B);
816 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2B);
821 ErrorF("writing vpll %08X\n", state->vpll);
822 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll);
823 if(pNv->twoStagePLL) {
824 ErrorF("writing vpllB %08X\n", state->vpllB);
825 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpllB);
829 ErrorF("writing pllsel %08X\n", state->pllsel);
830 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
833 #define IS_NV44P (pNv->NVArch >= 0x44 ? 1 : 0)
834 #define SEL_CLK_OFFSET (nv_get_sel_clk_offset(pNv->NVArch, nv_output->bus))
836 #define WIPE_OTHER_CLOCKS(_sel_clk, _head, _bus) (nv_wipe_other_clocks(_sel_clk, pNv->NVArch, _head, _bus))
839 * Calculate extended mode parameters (SVGA) and save in a
840 * mode state structure.
841 * State is not specific to a single crtc, but shared.
843 void nv_crtc_calc_state_ext(
846 int DisplayWidth, /* Does this change after setting the mode? */
853 ScrnInfoPtr pScrn = crtc->scrn;
854 uint32_t pixelDepth, VClk = 0;
856 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
857 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
859 NVPtr pNv = NVPTR(pScrn);
860 RIVA_HW_STATE *state;
861 int num_crtc_enabled, i;
863 state = &pNv->ModeReg;
865 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
867 xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
868 NVOutputPrivatePtr nv_output = NULL;
870 nv_output = output->driver_private;
874 * Extended RIVA registers.
876 pixelDepth = (bpp + 1)/8;
877 if (pNv->Architecture == NV_ARCH_40) {
878 /* Does register 0x580 already have a value? */
879 if (!state->reg580) {
880 state->reg580 = pNv->misc_info.ramdac_0_reg_580;
882 if (nv_crtc->head == 1) {
883 CalculateVClkNV4x(pScrn, dotClock, &VClk, &state->vpll2_a, &state->vpll2_b, &state->reg580, &state->db1_ratio[1], FALSE);
885 CalculateVClkNV4x(pScrn, dotClock, &VClk, &state->vpll1_a, &state->vpll1_b, &state->reg580, &state->db1_ratio[0], TRUE);
887 } else if (pNv->twoStagePLL) {
888 struct pll_lims pll_lim;
890 get_pll_limits(pScrn, 0, &pll_lim);
891 VClk = getMNP_double(pNv, &pll_lim, dotClock, &NM1, &NM2, &log2P);
892 state->pll = log2P << 16 | NM1;
893 state->pllB = 1 << 31 | NM2;
896 VClk = getMNP_single(pNv, dotClock, &NM, &log2P);
897 state->pll = log2P << 16 | NM;
900 switch (pNv->Architecture) {
902 nv4UpdateArbitrationSettings(VClk,
904 &(state->arbitration0),
905 &(state->arbitration1),
907 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
908 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
909 if (flags & V_DBLSCAN)
910 regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
911 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
912 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
913 state->config = 0x00001114;
914 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
920 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
921 ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
922 state->arbitration0 = 128;
923 state->arbitration1 = 0x0480;
924 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
925 ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
926 nForceUpdateArbitrationSettings(VClk,
928 &(state->arbitration0),
929 &(state->arbitration1),
931 } else if (pNv->Architecture < NV_ARCH_30) {
932 nv10UpdateArbitrationSettings(VClk,
934 &(state->arbitration0),
935 &(state->arbitration1),
938 nv30UpdateArbitrationSettings(pNv,
939 &(state->arbitration0),
940 &(state->arbitration1));
943 if (nv_crtc->head == 1) {
944 CursorStart = pNv->Cursor2->offset;
946 CursorStart = pNv->Cursor->offset;
949 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
950 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
951 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
953 if (flags & V_DBLSCAN)
954 regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
956 state->config = nvReadFB(pNv, NV_PFB_CFG0);
957 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
961 /* okay do we have 2 CRTCs running ? */
962 num_crtc_enabled = 0;
963 for (i = 0; i < xf86_config->num_crtc; i++) {
964 if (xf86_config->crtc[i]->enabled) {
969 ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
971 if (pNv->Architecture < NV_ARCH_40) {
972 /* We need this before the next code */
973 if (nv_crtc->head == 1) {
974 state->vpll2 = state->pll;
975 state->vpll2B = state->pllB;
977 state->vpll = state->pll;
978 state->vpllB = state->pllB;
982 /* The main stuff seems to be valid for NV3x also. */
983 if (pNv->Architecture >= NV_ARCH_30) {
984 /* This register is only used on the primary ramdac */
985 /* This seems to be needed to select the proper clocks, otherwise bad things happen */
988 state->sel_clk = pNv->misc_info.sel_clk & ~(0xf << 16);
990 if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
991 /* Only wipe when are a relevant (digital) output. */
992 state->sel_clk &= ~(0xf << 16);
993 Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
994 /* Even with two dvi, this should not conflict. */
995 if (crossed_clocks) {
996 state->sel_clk |= (0x1 << 16);
998 state->sel_clk |= (0x4 << 16);
1002 /* Some cards, specifically dual dvi/lvds cards set another bitrange.
1003 * I suspect inverse beheaviour to the normal bitrange, but i am not a 100% certain about this.
1004 * This is all based on default settings found in mmio-traces.
1005 * The blob never changes these, as it doesn't run unusual output configurations.
1006 * It seems to prefer situations that avoid changing these bits (for a good reason?).
1007 * I still don't know the purpose of value 2, it's similar to 4, but what exactly does it do?
1012 * bit 0 NVClk spread spectrum on/off
1013 * bit 2 MemClk spread spectrum on/off
1014 * bit 4 PixClk1 spread spectrum on/off
1015 * bit 6 PixClk2 spread spectrum on/off
1018 * what causes setting of bits not obvious but:
1019 * bits 4&5 relate to headA
1020 * bits 6&7 relate to headB
1022 if (pNv->Architecture == NV_ARCH_40) {
1023 for (i = 0; i < 4; i++) {
1024 uint32_t var = (state->sel_clk & (0xf << 4*i)) >> 4*i;
1025 if (var == 0x1 || var == 0x4) {
1026 state->sel_clk &= ~(0xf << 4*i);
1027 Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1028 if (crossed_clocks) {
1029 state->sel_clk |= (0x4 << 4*i);
1031 state->sel_clk |= (0x1 << 4*i);
1033 break; /* This should only occur once. */
1038 /* Are we crosswired? */
1039 if (output && nv_crtc->head != nv_output->preferred_output) {
1040 state->crosswired = TRUE;
1042 state->crosswired = FALSE;
1045 if (nv_crtc->head == 1) {
1046 if (state->db1_ratio[1])
1047 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1048 } else if (nv_crtc->head == 0) {
1049 if (state->db1_ratio[0])
1050 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1053 /* Do NV1x/NV2x cards need anything in sel_clk? */
1054 state->sel_clk = 0x0;
1055 state->crosswired = FALSE;
1058 /* The NV40 seems to have more similarities to NV3x than other cards. */
1059 if (pNv->NVArch < 0x41) {
1060 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL;
1061 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL;
1064 if (nv_crtc->head == 1) {
1065 if (!state->db1_ratio[1]) {
1066 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1068 state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1070 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
1072 if (!state->db1_ratio[0]) {
1073 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1075 state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1077 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
1080 /* The blob uses this always, so let's do the same */
1081 if (pNv->Architecture == NV_ARCH_40) {
1082 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
1085 /* The primary output doesn't seem to care */
1086 if (nv_output->preferred_output == 1) { /* This is the "output" */
1087 /* non-zero values are for analog, don't know about tv-out and the likes */
1088 if (output && nv_output->type != OUTPUT_ANALOG) {
1089 state->reg594 = 0x0;
1091 /* Are we a flexible output? */
1092 if (ffs(pNv->dcb_table.entry[nv_output->dcb_entry].or) & OUTPUT_0) {
1093 state->reg594 = 0x1;
1094 pNv->restricted_mode = FALSE;
1096 state->reg594 = 0x0;
1097 pNv->restricted_mode = TRUE;
1100 /* More values exist, but they seem related to the 3rd dac (tv-out?) somehow */
1101 /* bit 16-19 are bits that are set on some G70 cards */
1102 /* Those bits are also set to the 3rd OUTPUT register */
1103 if (nv_crtc->head == 1) {
1104 state->reg594 |= 0x100;
1109 regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
1110 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
1111 if (pNv->Architecture >= NV_ARCH_30) {
1112 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
1115 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
1116 regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
1120 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
1122 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1123 ScrnInfoPtr pScrn = crtc->scrn;
1124 NVPtr pNv = NVPTR(pScrn);
1125 unsigned char seq1 = 0, crtc17 = 0;
1126 unsigned char crtc1A;
1128 ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->head, mode);
1130 NVCrtcSetOwner(crtc);
1132 crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
1134 case DPMSModeStandby:
1135 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
1140 case DPMSModeSuspend:
1141 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
1147 /* Screen: Off; HSync: Off, VSync: Off */
1154 /* Screen: On; HSync: On, VSync: On */
1160 NVVgaSeqReset(crtc, TRUE);
1161 /* Each head has it's own sequencer, so we can turn it off when we want */
1162 seq1 |= (NVReadVgaSeq(crtc, 0x01) & ~0x20);
1163 NVWriteVgaSeq(crtc, 0x1, seq1);
1164 crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
1166 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
1167 NVVgaSeqReset(crtc, FALSE);
1169 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
1171 /* We can completely disable a vpll if the crtc is off. */
1172 if (pNv->Architecture == NV_ARCH_40) {
1173 uint32_t reg_c040_old = nvReadMC(pNv, 0xc040);
1174 if (mode == DPMSModeOn) {
1175 nvWriteMC(pNv, 0xc040, reg_c040_old | (pNv->misc_info.reg_c040 & (0x3 << (16 + 2*nv_crtc->head))));
1177 nvWriteMC(pNv, 0xc040, reg_c040_old & ~(pNv->misc_info.reg_c040 & (0x3 << (16 + 2*nv_crtc->head))));
1181 /* I hope this is the right place */
1182 if (crtc->enabled && mode == DPMSModeOn) {
1183 pNv->crtc_active[nv_crtc->head] = TRUE;
1185 pNv->crtc_active[nv_crtc->head] = FALSE;
1190 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
1191 DisplayModePtr adjusted_mode)
1193 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1194 ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->head);
1196 xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1197 NVOutputPrivatePtr nv_output = NULL;
1199 nv_output = output->driver_private;
1202 /* For internal panels and gpu scaling on DVI we need the native mode */
1203 if (output && (nv_output->type == OUTPUT_LVDS || (nv_output->type == OUTPUT_TMDS && nv_output->scaling_mode != SCALE_PANEL))) {
1204 adjusted_mode->HDisplay = nv_output->native_mode->HDisplay;
1205 adjusted_mode->HSkew = nv_output->native_mode->HSkew;
1206 adjusted_mode->HSyncStart = nv_output->native_mode->HSyncStart;
1207 adjusted_mode->HSyncEnd = nv_output->native_mode->HSyncEnd;
1208 adjusted_mode->HTotal = nv_output->native_mode->HTotal;
1209 adjusted_mode->VDisplay = nv_output->native_mode->VDisplay;
1210 adjusted_mode->VScan = nv_output->native_mode->VScan;
1211 adjusted_mode->VSyncStart = nv_output->native_mode->VSyncStart;
1212 adjusted_mode->VSyncEnd = nv_output->native_mode->VSyncEnd;
1213 adjusted_mode->VTotal = nv_output->native_mode->VTotal;
1214 adjusted_mode->Clock = nv_output->native_mode->Clock;
1216 xf86SetModeCrtc(adjusted_mode, INTERLACE_HALVE_V);
1223 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1225 ScrnInfoPtr pScrn = crtc->scrn;
1226 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1228 NVPtr pNv = NVPTR(pScrn);
1229 NVFBLayout *pLayout = &pNv->CurrentLayout;
1230 int depth = pScrn->depth;
1232 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1234 /* Calculate our timings */
1235 int horizDisplay = (mode->CrtcHDisplay >> 3) - 1;
1236 int horizStart = (mode->CrtcHSyncStart >> 3) - 1;
1237 int horizEnd = (mode->CrtcHSyncEnd >> 3) - 1;
1238 int horizTotal = (mode->CrtcHTotal >> 3) - 5;
1239 int horizBlankStart = (mode->CrtcHDisplay >> 3) - 1;
1240 int horizBlankEnd = (mode->CrtcHTotal >> 3) - 1;
1241 int vertDisplay = mode->CrtcVDisplay - 1;
1242 int vertStart = mode->CrtcVSyncStart - 1;
1243 int vertEnd = mode->CrtcVSyncEnd - 1;
1244 int vertTotal = mode->CrtcVTotal - 2;
1245 int vertBlankStart = mode->CrtcVDisplay - 1;
1246 int vertBlankEnd = mode->CrtcVTotal - 1;
1250 xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1251 NVOutputPrivatePtr nv_output = NULL;
1253 nv_output = output->driver_private;
1255 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1259 ErrorF("Mode clock: %d\n", mode->Clock);
1260 ErrorF("Adjusted mode clock: %d\n", adjusted_mode->Clock);
1262 /* Reverted to what nv did, because that works for all resolutions on flatpanels */
1264 vertStart = vertTotal - 3;
1265 vertEnd = vertTotal - 2;
1266 vertBlankStart = vertStart;
1267 horizStart = horizTotal - 5;
1268 horizEnd = horizTotal - 2;
1269 horizBlankEnd = horizTotal + 4;
1270 if (pNv->overlayAdaptor) {
1271 /* This reportedly works around Xv some overlay bandwidth problems*/
1276 if(mode->Flags & V_INTERLACE)
1279 ErrorF("horizDisplay: 0x%X \n", horizDisplay);
1280 ErrorF("horizStart: 0x%X \n", horizStart);
1281 ErrorF("horizEnd: 0x%X \n", horizEnd);
1282 ErrorF("horizTotal: 0x%X \n", horizTotal);
1283 ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
1284 ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
1285 ErrorF("vertDisplay: 0x%X \n", vertDisplay);
1286 ErrorF("vertStart: 0x%X \n", vertStart);
1287 ErrorF("vertEnd: 0x%X \n", vertEnd);
1288 ErrorF("vertTotal: 0x%X \n", vertTotal);
1289 ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
1290 ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
1293 * compute correct Hsync & Vsync polarity
1295 if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
1296 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
1298 regp->MiscOutReg = 0x23;
1299 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
1300 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
1302 int VDisplay = mode->VDisplay;
1303 if (mode->Flags & V_DBLSCAN)
1305 if (mode->VScan > 1)
1306 VDisplay *= mode->VScan;
1307 if (VDisplay < 400) {
1308 regp->MiscOutReg = 0xA3; /* +hsync -vsync */
1309 } else if (VDisplay < 480) {
1310 regp->MiscOutReg = 0x63; /* -hsync +vsync */
1311 } else if (VDisplay < 768) {
1312 regp->MiscOutReg = 0xE3; /* -hsync -vsync */
1314 regp->MiscOutReg = 0x23; /* +hsync +vsync */
1318 regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
1324 regp->Sequencer[0] = 0x02;
1326 regp->Sequencer[0] = 0x00;
1328 /* 0x20 disables the sequencer */
1329 if (mode->Flags & V_CLKDIV2) {
1330 regp->Sequencer[1] = 0x29;
1332 regp->Sequencer[1] = 0x21;
1335 regp->Sequencer[2] = 1 << BIT_PLANE;
1337 regp->Sequencer[2] = 0x0F;
1338 regp->Sequencer[3] = 0x00; /* Font select */
1341 regp->Sequencer[4] = 0x06; /* Misc */
1343 regp->Sequencer[4] = 0x0E; /* Misc */
1349 regp->CRTC[NV_VGA_CRTCX_HTOTAL] = Set8Bits(horizTotal);
1350 regp->CRTC[NV_VGA_CRTCX_HDISPE] = Set8Bits(horizDisplay);
1351 regp->CRTC[NV_VGA_CRTCX_HBLANKS] = Set8Bits(horizBlankStart);
1352 regp->CRTC[NV_VGA_CRTCX_HBLANKE] = SetBitField(horizBlankEnd,4:0,4:0)
1354 regp->CRTC[NV_VGA_CRTCX_HSYNCS] = Set8Bits(horizStart);
1355 regp->CRTC[NV_VGA_CRTCX_HSYNCE] = SetBitField(horizBlankEnd,5:5,7:7)
1356 | SetBitField(horizEnd,4:0,4:0);
1357 regp->CRTC[NV_VGA_CRTCX_VTOTAL] = SetBitField(vertTotal,7:0,7:0);
1358 regp->CRTC[NV_VGA_CRTCX_OVERFLOW] = SetBitField(vertTotal,8:8,0:0)
1359 | SetBitField(vertDisplay,8:8,1:1)
1360 | SetBitField(vertStart,8:8,2:2)
1361 | SetBitField(vertBlankStart,8:8,3:3)
1363 | SetBitField(vertTotal,9:9,5:5)
1364 | SetBitField(vertDisplay,9:9,6:6)
1365 | SetBitField(vertStart,9:9,7:7);
1366 regp->CRTC[NV_VGA_CRTCX_PRROWSCN] = 0x00;
1367 regp->CRTC[NV_VGA_CRTCX_MAXSCLIN] = SetBitField(vertBlankStart,9:9,5:5)
1369 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00);
1370 regp->CRTC[NV_VGA_CRTCX_VGACURCTRL] = 0x00;
1371 regp->CRTC[0xb] = 0x00;
1372 regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00;
1373 regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
1374 regp->CRTC[0xe] = 0x00;
1375 regp->CRTC[0xf] = 0x00;
1376 regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
1377 regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
1378 regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
1379 regp->CRTC[0x14] = 0x00;
1380 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
1381 regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
1382 regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
1383 /* 0x80 enables the sequencer, we don't want that */
1385 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xE3 & ~0x80;
1387 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80;
1389 regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
1392 * Some extended CRTC registers (they are not saved with the rest of the vga regs).
1395 regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
1396 | SetBitField(vertBlankStart,10:10,3:3)
1397 | SetBitField(vertStart,10:10,2:2)
1398 | SetBitField(vertDisplay,10:10,1:1)
1399 | SetBitField(vertTotal,10:10,0:0);
1401 regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
1402 | SetBitField(horizDisplay,8:8,1:1)
1403 | SetBitField(horizBlankStart,8:8,2:2)
1404 | SetBitField(horizStart,8:8,3:3);
1406 regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
1407 | SetBitField(vertDisplay,11:11,2:2)
1408 | SetBitField(vertStart,11:11,4:4)
1409 | SetBitField(vertBlankStart,11:11,6:6);
1411 if(mode->Flags & V_INTERLACE) {
1412 horizTotal = (horizTotal >> 1) & ~1;
1413 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
1414 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
1416 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff; /* interlace off */
1420 * Theory resumes here....
1424 * Graphics Display Controller
1426 regp->Graphics[0] = 0x00;
1427 regp->Graphics[1] = 0x00;
1428 regp->Graphics[2] = 0x00;
1429 regp->Graphics[3] = 0x00;
1431 regp->Graphics[4] = BIT_PLANE;
1432 regp->Graphics[5] = 0x00;
1434 regp->Graphics[4] = 0x00;
1436 regp->Graphics[5] = 0x02;
1438 regp->Graphics[5] = 0x40;
1441 regp->Graphics[6] = 0x05; /* only map 64k VGA memory !!!! */
1442 regp->Graphics[7] = 0x0F;
1443 regp->Graphics[8] = 0xFF;
1445 /* I ditched the mono stuff */
1446 regp->Attribute[0] = 0x00; /* standard colormap translation */
1447 regp->Attribute[1] = 0x01;
1448 regp->Attribute[2] = 0x02;
1449 regp->Attribute[3] = 0x03;
1450 regp->Attribute[4] = 0x04;
1451 regp->Attribute[5] = 0x05;
1452 regp->Attribute[6] = 0x06;
1453 regp->Attribute[7] = 0x07;
1454 regp->Attribute[8] = 0x08;
1455 regp->Attribute[9] = 0x09;
1456 regp->Attribute[10] = 0x0A;
1457 regp->Attribute[11] = 0x0B;
1458 regp->Attribute[12] = 0x0C;
1459 regp->Attribute[13] = 0x0D;
1460 regp->Attribute[14] = 0x0E;
1461 regp->Attribute[15] = 0x0F;
1462 /* These two below are non-vga */
1463 regp->Attribute[16] = 0x01;
1464 regp->Attribute[17] = 0x00;
1465 regp->Attribute[18] = 0x0F;
1466 regp->Attribute[19] = 0x00;
1467 regp->Attribute[20] = 0x00;
1470 #define MAX_H_VALUE(i) ((0x1ff + i) << 3)
1471 #define MAX_V_VALUE(i) ((0xfff + i) << 0)
1474 * Sets up registers for the given mode/adjusted_mode pair.
1476 * The clocks, CRTCs and outputs attached to this CRTC must be off.
1478 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1479 * be easily turned on/off after this.
1482 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1484 ScrnInfoPtr pScrn = crtc->scrn;
1485 NVPtr pNv = NVPTR(pScrn);
1486 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1487 NVFBLayout *pLayout = &pNv->CurrentLayout;
1488 NVCrtcRegPtr regp, savep;
1492 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1493 savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1495 xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1496 NVOutputPrivatePtr nv_output = NULL;
1498 nv_output = output->driver_private;
1500 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1504 /* Registers not directly related to the (s)vga mode */
1506 /* bit2 = 0 -> fine pitched crtc granularity */
1507 /* The rest disables double buffering on CRTC access */
1508 regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
1510 if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
1511 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1512 if (nv_crtc->head == 0) {
1513 regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1517 regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0) | (1 << 1);
1520 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
1521 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
1524 /* Sometimes 0x10 is used, what is this? */
1525 regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1526 /* Some kind of tmds switch for older cards */
1527 if (pNv->Architecture < NV_ARCH_40) {
1528 regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
1532 * Initialize DAC palette.
1533 * Not needed for 8 bits, but it shouldn't hurt either.
1535 for (i = 0; i < 256; i++) {
1537 regp->DAC[(i*3)+1] = i;
1538 regp->DAC[(i*3)+2] = i;
1542 * Calculate the extended registers.
1545 if(pLayout->depth < 24) {
1551 /* What is the meaning of this register? */
1552 /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1553 regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
1555 /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1556 /* But what are those special conditions? */
1557 if (pNv->Architecture <= NV_ARCH_30) {
1559 if(nv_crtc->head == 1) {
1560 regp->head |= NV_CRTC_FSEL_FPP1;
1561 } else if (pNv->twoHeads) {
1562 regp->head |= NV_CRTC_FSEL_FPP2;
1566 /* Some G70 cards have either FPP1 or FPP2 set, copy this if it's already present */
1567 if (nv_crtc->head == 1 && pNv->NVArch > 0x44) {
1568 regp->head |= savep->head & (NV_CRTC_FSEL_FPP1 | NV_CRTC_FSEL_FPP2);
1572 /* Except for rare conditions I2C is enabled on the primary crtc */
1573 if (nv_crtc->head == 0) {
1574 if (pNv->overlayAdaptor) {
1575 regp->head |= NV_CRTC_FSEL_OVERLAY;
1577 regp->head |= NV_CRTC_FSEL_I2C;
1580 /* This is not what nv does, but it is what the blob does (for nv4x at least) */
1581 /* This fixes my cursor corruption issue */
1582 regp->cursorConfig = 0x0;
1583 if(mode->Flags & V_DBLSCAN)
1584 regp->cursorConfig |= (1 << 4);
1585 if (pNv->alphaCursor) {
1586 /* bit28 means we go into alpha blend mode and not rely on the current ROP */
1587 regp->cursorConfig |= 0x14011000;
1589 regp->cursorConfig |= 0x02000000;
1592 /* Unblock some timings */
1593 regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1594 regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1596 /* What is the purpose of this register? */
1597 /* 0x14 may be disabled? */
1598 regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1600 /* 0x00 is disabled, 0x22 crt and 0x88 dfp */
1603 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1605 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1608 /* These values seem to vary */
1609 if (nv_crtc->head == 1) {
1610 regp->CRTC[NV_VGA_CRTCX_3C] = 0x0;
1612 regp->CRTC[NV_VGA_CRTCX_3C] = 0x70;
1615 /* 0x80 seems to be used very often, if not always */
1616 regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1618 if (nv_crtc->head == 1) {
1619 regp->CRTC[NV_VGA_CRTCX_4B] = 0x0;
1621 regp->CRTC[NV_VGA_CRTCX_4B] = 0x1;
1625 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x80;
1627 /* Are these(0x55 and 0x56) also timing related registers, since disabling them does nothing? */
1628 regp->CRTC[NV_VGA_CRTCX_55] = 0x0;
1630 /* Common values like 0x14 and 0x04 are converted to 0x10 and 0x00 */
1631 regp->CRTC[NV_VGA_CRTCX_56] = 0x0;
1633 /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1*/
1634 if (nv_crtc->head == 1) {
1635 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52;
1637 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52 + 4;
1640 /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1641 regp->unk81c = nvReadCRTC0(pNv, NV_CRTC_081C);
1643 regp->unk830 = mode->CrtcVDisplay - 3;
1644 regp->unk834 = mode->CrtcVDisplay - 1;
1646 /* This is what the blob does */
1647 regp->unk850 = nvReadCRTC(pNv, 0, NV_CRTC_0850);
1649 /* Never ever modify gpio, unless you know very well what you're doing */
1650 regp->gpio = nvReadCRTC(pNv, 0, NV_CRTC_GPIO);
1652 /* Switch to non-vga mode (the so called HSYNC mode) */
1655 /* Some misc regs */
1656 regp->CRTC[NV_VGA_CRTCX_43] = 0x1;
1657 if (pNv->Architecture == NV_ARCH_40) {
1658 regp->CRTC[NV_VGA_CRTCX_85] = 0xFF;
1659 regp->CRTC[NV_VGA_CRTCX_86] = 0x1;
1663 * Calculate the state that is common to all crtc's (stored in the state struct).
1665 ErrorF("crtc %d %d %d\n", nv_crtc->head, mode->CrtcHDisplay, pScrn->displayWidth);
1666 nv_crtc_calc_state_ext(crtc,
1668 pScrn->displayWidth,
1671 adjusted_mode->Clock,
1674 /* Enable slaved mode */
1676 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1681 nv_crtc_mode_set_ramdac_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1683 ScrnInfoPtr pScrn = crtc->scrn;
1684 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1686 NVPtr pNv = NVPTR(pScrn);
1687 NVFBLayout *pLayout = &pNv->CurrentLayout;
1689 Bool is_lvds = FALSE;
1690 float aspect_ratio, panel_ratio;
1691 uint32_t h_scale, v_scale;
1692 Bool magic_factor = TRUE;
1694 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1696 xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1697 NVOutputPrivatePtr nv_output = NULL;
1699 nv_output = output->driver_private;
1701 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1704 if (nv_output->type == OUTPUT_LVDS)
1709 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
1710 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
1711 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HDisplay;
1712 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
1713 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
1714 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
1715 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
1717 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
1718 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
1719 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VDisplay;
1720 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
1721 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
1722 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
1723 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
1725 ErrorF("Horizontal:\n");
1726 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
1727 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
1728 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
1729 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
1730 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
1731 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
1732 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
1734 ErrorF("Vertical:\n");
1735 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
1736 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
1737 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
1738 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
1739 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
1740 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
1741 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
1745 * bit0: positive vsync
1746 * bit4: positive hsync
1747 * bit8: enable center mode
1748 * bit9: enable native mode
1749 * bit26: a bit sometimes seen on some g70 cards
1750 * bit31: set for dual link LVDS
1751 * nv10reg contains a few more things, but i don't quite get what it all means.
1754 if (pNv->Architecture >= NV_ARCH_30) {
1755 regp->fp_control = 0x01100000;
1757 regp->fp_control = 0x00000000;
1761 regp->fp_control |= (1 << 28);
1763 regp->fp_control |= (2 << 28);
1764 if (pNv->Architecture < NV_ARCH_30)
1765 regp->fp_control |= (1 << 24);
1768 /* This has only been observerved on a 7300GO so far. */
1769 /* 0xc040: 0x340bd000. */
1770 if (is_lvds && pNv->Architecture == NV_ARCH_40 && !(pNv->misc_info.reg_c040 & 0xFFF))
1771 magic_factor = FALSE;
1773 if (is_lvds && pNv->VBIOS.fp.dual_link && magic_factor) {
1774 regp->fp_control |= (8 << 28);
1776 /* If the special bit exists, it exists on both ramdac's */
1777 regp->fp_control |= nvReadRAMDAC0(pNv, NV_RAMDAC_FP_CONTROL) & (1 << 26);
1781 if (nv_output->scaling_mode == SCALE_PANEL) { /* panel needs to scale */
1782 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
1783 /* This is also true for panel scaling, so we must put the panel scale check first */
1784 } else if (mode->Clock == adjusted_mode->Clock) { /* native mode */
1785 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
1786 } else { /* gpu needs to scale */
1787 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1791 /* Deal with vsync/hsync polarity */
1792 /* LVDS screens don't set this. */
1793 if (is_fp && !is_lvds) {
1794 if (adjusted_mode->Flags & V_PVSYNC) {
1795 regp->fp_control |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
1798 if (adjusted_mode->Flags & V_PHSYNC) {
1799 regp->fp_control |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
1801 } else if (!is_lvds) {
1802 /* The blob doesn't always do this, but often */
1803 regp->fp_control |= NV_RAMDAC_FP_CONTROL_VSYNC_DISABLE;
1804 regp->fp_control |= NV_RAMDAC_FP_CONTROL_HSYNC_DISABLE;
1808 ErrorF("Pre-panel scaling\n");
1809 ErrorF("panel-size:%dx%d\n", nv_output->fpWidth, nv_output->fpHeight);
1810 panel_ratio = (nv_output->fpWidth)/(float)(nv_output->fpHeight);
1811 ErrorF("panel_ratio=%f\n", panel_ratio);
1812 aspect_ratio = (mode->HDisplay)/(float)(mode->VDisplay);
1813 ErrorF("aspect_ratio=%f\n", aspect_ratio);
1814 /* Scale factors is the so called 20.12 format, taken from Haiku */
1815 h_scale = ((1 << 12) * mode->HDisplay)/nv_output->fpWidth;
1816 v_scale = ((1 << 12) * mode->VDisplay)/nv_output->fpHeight;
1817 ErrorF("h_scale=%d\n", h_scale);
1818 ErrorF("v_scale=%d\n", v_scale);
1820 /* This can override HTOTAL and VTOTAL */
1823 /* We want automatic scaling */
1826 regp->fp_hvalid_start = 0;
1827 regp->fp_hvalid_end = (nv_output->fpWidth - 1);
1829 regp->fp_vvalid_start = 0;
1830 regp->fp_vvalid_end = (nv_output->fpHeight - 1);
1832 /* 0 = panel scaling */
1833 if (nv_output->scaling_mode == SCALE_PANEL) {
1834 ErrorF("Flat panel is doing the scaling.\n");
1836 ErrorF("GPU is doing the scaling.\n");
1838 if (nv_output->scaling_mode == SCALE_ASPECT) {
1839 /* GPU scaling happens automaticly at a ratio of 1.33 */
1840 /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
1841 if (h_scale != (1 << 12) && (panel_ratio > (aspect_ratio + 0.10))) {
1844 ErrorF("Scaling resolution on a widescreen panel\n");
1846 /* Scaling in both directions needs to the same */
1849 /* Set a new horizontal scale factor and enable testmode (bit12) */
1850 regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
1852 diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
1853 regp->fp_hvalid_start = diff/2;
1854 regp->fp_hvalid_end = nv_output->fpWidth - (diff/2) - 1;
1857 /* Same scaling, just for panels with aspect ratio's smaller than 1 */
1858 if (v_scale != (1 << 12) && (panel_ratio < (aspect_ratio - 0.10))) {
1861 ErrorF("Scaling resolution on a portrait panel\n");
1863 /* Scaling in both directions needs to the same */
1866 /* Set a new vertical scale factor and enable testmode (bit28) */
1867 regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
1869 diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
1870 regp->fp_vvalid_start = diff/2;
1871 regp->fp_vvalid_end = nv_output->fpHeight - (diff/2) - 1;
1876 ErrorF("Post-panel scaling\n");
1879 if (pNv->Architecture >= NV_ARCH_10) {
1880 /* Bios and blob don't seem to do anything (else) */
1881 regp->nv10_cursync = (1<<25);
1884 /* These are the common blob values, minus a few fp specific bit's */
1885 /* Let's keep the TMDS pll and fpclock running in all situations */
1886 regp->debug_0 = 0x1101100;
1888 if (is_fp && nv_output->scaling_mode != SCALE_NOSCALE) {
1889 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_XSCALE_ENABLED;
1890 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_YSCALE_ENABLED;
1891 } else if (is_fp) { /* no_scale mode, so we must center it */
1894 diff = nv_output->fpWidth - mode->HDisplay;
1895 regp->fp_hvalid_start = diff/2;
1896 regp->fp_hvalid_end = (nv_output->fpWidth - diff/2 - 1);
1898 diff = nv_output->fpHeight - mode->VDisplay;
1899 regp->fp_vvalid_start = diff/2;
1900 regp->fp_vvalid_end = (nv_output->fpHeight - diff/2 - 1);
1903 /* Is this crtc bound or output bound? */
1904 /* Does the bios TMDS script try to change this sometimes? */
1906 /* I am not completely certain, but seems to be set only for dfp's */
1907 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED;
1911 ErrorF("output %d debug_0 %08X\n", nv_output->preferred_output, regp->debug_0);
1913 /* Flatpanel support needs at least a NV10 */
1915 /* The blob does this differently. */
1916 /* TODO: Find out what precisely and why. */
1917 if(pNv->FPDither || (is_lvds && pNv->VBIOS.fp.if_is_18bit)) {
1918 if (pNv->NVArch == 0x11) {
1919 regp->dither = 0x00010000;
1921 regp->dither = 0x00000001;
1926 /* Kindly borrowed from haiku driver */
1927 /* bit4 and bit5 activate indirect mode trough color palette */
1928 switch (pLayout->depth) {
1931 regp->general = 0x00101130;
1935 regp->general = 0x00100130;
1939 regp->general = 0x00101100;
1943 if (pNv->alphaCursor) {
1944 /* PIPE_LONG mode, something to do with the size of the cursor? */
1945 regp->general |= (1<<29);
1948 /* Some values the blob sets */
1949 /* This may apply to the real ramdac that is being used (for crosswired situations) */
1950 /* Nevertheless, it's unlikely to cause many problems, since the values are equal for both */
1951 regp->unk_a20 = 0x0;
1952 regp->unk_a24 = 0xfffff;
1953 regp->unk_a34 = 0x1;
1957 * Sets up registers for the given mode/adjusted_mode pair.
1959 * The clocks, CRTCs and outputs attached to this CRTC must be off.
1961 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1962 * be easily turned on/off after this.
1965 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
1966 DisplayModePtr adjusted_mode,
1969 ScrnInfoPtr pScrn = crtc->scrn;
1970 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1971 NVPtr pNv = NVPTR(pScrn);
1973 ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->head);
1975 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->head);
1976 xf86PrintModeline(pScrn->scrnIndex, mode);
1977 NVCrtcSetOwner(crtc);
1979 nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
1980 nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
1981 nv_crtc_mode_set_ramdac_regs(crtc, mode, adjusted_mode);
1983 NVVgaProtect(crtc, TRUE);
1984 nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
1985 nv_crtc_load_state_ext(crtc, &pNv->ModeReg, FALSE);
1986 NVCrtcLoadPalette(crtc);
1987 nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
1988 if (pNv->Architecture == NV_ARCH_40) {
1989 nv40_crtc_load_state_pll(crtc, &pNv->ModeReg);
1991 nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
1994 NVVgaProtect(crtc, FALSE);
1996 NVCrtcSetBase(crtc, x, y);
1998 #if X_BYTE_ORDER == X_BIG_ENDIAN
1999 /* turn on LFB swapping */
2003 tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
2005 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
2010 /* This functions generates data that is not saved, but still is needed. */
2011 void nv_crtc_restore_generate(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2013 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2015 NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
2017 /* It's a good idea to also save a default palette on shutdown. */
2018 for (i = 0; i < 256; i++) {
2020 regp->DAC[(i*3)+1] = i;
2021 regp->DAC[(i*3)+2] = i;
2025 void nv_crtc_save(xf86CrtcPtr crtc)
2027 ScrnInfoPtr pScrn = crtc->scrn;
2028 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2029 NVPtr pNv = NVPTR(pScrn);
2031 ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->head);
2033 /* We just came back from terminal, so unlock */
2034 NVCrtcLockUnlock(crtc, FALSE);
2036 NVCrtcSetOwner(crtc);
2037 nv_crtc_restore_generate(crtc, &pNv->SavedReg);
2038 nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
2039 nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
2040 nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
2041 if (pNv->Architecture == NV_ARCH_40) {
2042 nv40_crtc_save_state_pll(pNv, &pNv->SavedReg);
2044 nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
2048 void nv_crtc_restore(xf86CrtcPtr crtc)
2050 ScrnInfoPtr pScrn = crtc->scrn;
2051 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2052 NVPtr pNv = NVPTR(pScrn);
2053 RIVA_HW_STATE *state;
2055 state = &pNv->SavedReg;
2057 ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->head);
2059 NVCrtcSetOwner(crtc);
2061 /* Just to be safe */
2062 NVCrtcLockUnlock(crtc, FALSE);
2064 NVVgaProtect(crtc, TRUE);
2065 nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
2066 nv_crtc_load_state_ext(crtc, &pNv->SavedReg, TRUE);
2067 NVCrtcLoadPalette(crtc);
2068 nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
2069 if (pNv->Architecture == NV_ARCH_40) {
2070 nv40_crtc_load_state_pll(crtc, &pNv->SavedReg);
2072 nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
2074 nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->vtOWNER);
2075 NVVgaProtect(crtc, FALSE);
2079 NVResetCrtcConfig(xf86CrtcPtr crtc, Bool set)
2081 ScrnInfoPtr pScrn = crtc->scrn;
2082 NVPtr pNv = NVPTR(pScrn);
2085 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2090 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2094 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL, val);
2097 void nv_crtc_prepare(xf86CrtcPtr crtc)
2099 ScrnInfoPtr pScrn = crtc->scrn;
2100 NVPtr pNv = NVPTR(pScrn);
2101 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2103 ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->head);
2106 NVCrtcLockUnlock(crtc, 0);
2108 NVResetCrtcConfig(crtc, FALSE);
2110 crtc->funcs->dpms(crtc, DPMSModeOff);
2112 /* Sync the engine before adjust mode */
2113 if (pNv->EXADriverPtr) {
2114 exaMarkSync(pScrn->pScreen);
2115 exaWaitSync(pScrn->pScreen);
2118 NVCrtcBlankScreen(crtc, FALSE); /* Blank screen */
2120 /* Some more preperation. */
2121 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG, 0x1); /* Go to non-vga mode/out of enhanced mode */
2122 uint32_t reg900 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900);
2123 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 & ~0x10000);
2124 /* Set FP_CONTROL to a neutral mode, (almost) off i believe. */
2125 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, 0x21100222);
2127 usleep(5000); /* Give it some time to settle */
2130 void nv_crtc_commit(xf86CrtcPtr crtc)
2132 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2133 ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->head);
2135 crtc->funcs->dpms (crtc, DPMSModeOn);
2137 if (crtc->scrn->pScreen != NULL)
2138 xf86_reload_cursors (crtc->scrn->pScreen);
2140 NVResetCrtcConfig(crtc, TRUE);
2143 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
2145 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2146 ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->head);
2151 static void nv_crtc_unlock(xf86CrtcPtr crtc)
2153 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2154 ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->head);
2158 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
2161 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2162 ScrnInfoPtr pScrn = crtc->scrn;
2163 NVPtr pNv = NVPTR(pScrn);
2167 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2169 switch (pNv->CurrentLayout.depth) {
2172 /* We've got 5 bit (32 values) colors and 256 registers for each color */
2173 for (i = 0; i < 32; i++) {
2174 for (j = 0; j < 8; j++) {
2175 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2176 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
2177 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2183 /* First deal with the 5 bit colors */
2184 for (i = 0; i < 32; i++) {
2185 for (j = 0; j < 8; j++) {
2186 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2187 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2190 /* Now deal with the 6 bit color */
2191 for (i = 0; i < 64; i++) {
2192 for (j = 0; j < 4; j++) {
2193 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
2199 for (i = 0; i < 256; i++) {
2200 regp->DAC[i * 3] = red[i] >> 8;
2201 regp->DAC[(i * 3) + 1] = green[i] >> 8;
2202 regp->DAC[(i * 3) + 2] = blue[i] >> 8;
2207 NVCrtcLoadPalette(crtc);
2211 * Allocates memory for a locked-in-framebuffer shadow of the given
2212 * width and height for this CRTC's rotated shadow framebuffer.
2216 nv_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
2218 ErrorF("nv_crtc_shadow_allocate is called\n");
2219 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2220 ScrnInfoPtr pScrn = crtc->scrn;
2221 #if !NOUVEAU_EXA_PIXMAPS
2222 ScreenPtr pScreen = pScrn->pScreen;
2223 #endif /* !NOUVEAU_EXA_PIXMAPS */
2224 NVPtr pNv = NVPTR(pScrn);
2227 unsigned long rotate_pitch;
2228 int size, align = 64;
2230 rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2231 size = rotate_pitch * height;
2233 assert(nv_crtc->shadow == NULL);
2234 #if NOUVEAU_EXA_PIXMAPS
2235 if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN,
2236 align, size, &nv_crtc->shadow)) {
2237 ErrorF("Failed to allocate memory for shadow buffer!\n");
2241 if (nv_crtc->shadow && nouveau_bo_map(nv_crtc->shadow, NOUVEAU_BO_RDWR)) {
2242 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2243 "Failed to map shadow buffer.\n");
2247 offset = nv_crtc->shadow->map;
2249 nv_crtc->shadow = exaOffscreenAlloc(pScreen, size, align, TRUE, NULL, NULL);
2250 if (nv_crtc->shadow == NULL) {
2251 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2252 "Couldn't allocate shadow memory for rotated CRTC\n");
2255 offset = pNv->FB->map + nv_crtc->shadow->offset;
2256 #endif /* NOUVEAU_EXA_PIXMAPS */
2262 * Creates a pixmap for this CRTC's rotated shadow framebuffer.
2265 nv_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
2267 ErrorF("nv_crtc_shadow_create is called\n");
2268 ScrnInfoPtr pScrn = crtc->scrn;
2269 #if NOUVEAU_EXA_PIXMAPS
2270 ScreenPtr pScreen = pScrn->pScreen;
2271 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2272 #endif /* NOUVEAU_EXA_PIXMAPS */
2273 unsigned long rotate_pitch;
2274 PixmapPtr rotate_pixmap;
2275 #if NOUVEAU_EXA_PIXMAPS
2276 struct nouveau_pixmap *nvpix;
2277 #endif /* NOUVEAU_EXA_PIXMAPS */
2280 data = crtc->funcs->shadow_allocate (crtc, width, height);
2282 rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2284 #if NOUVEAU_EXA_PIXMAPS
2285 /* Create a dummy pixmap, to get a private that will be accepted by the system.*/
2286 rotate_pixmap = pScreen->CreatePixmap(pScreen,
2289 #ifdef CREATE_PIXMAP_USAGE_SCRATCH /* there seems to have been no api bump */
2294 #endif /* CREATE_PIXMAP_USAGE_SCRATCH */
2296 rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen,
2299 pScrn->bitsPerPixel,
2302 #endif /* NOUVEAU_EXA_PIXMAPS */
2304 if (rotate_pixmap == NULL) {
2305 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2306 "Couldn't allocate shadow pixmap for rotated CRTC\n");
2309 #if NOUVEAU_EXA_PIXMAPS
2310 nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2312 ErrorF("No shadow private, stage 1\n");
2314 nvpix->bo = nv_crtc->shadow;
2315 nvpix->mapped = TRUE;
2318 /* Modify the pixmap to actually be the one we need. */
2319 pScreen->ModifyPixmapHeader(rotate_pixmap,
2323 pScrn->bitsPerPixel,
2327 nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2328 if (!nvpix || !nvpix->bo)
2329 ErrorF("No shadow private, stage 2\n");
2330 #endif /* NOUVEAU_EXA_PIXMAPS */
2332 return rotate_pixmap;
2336 nv_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
2338 ErrorF("nv_crtc_shadow_destroy is called\n");
2339 ScrnInfoPtr pScrn = crtc->scrn;
2340 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2341 ScreenPtr pScreen = pScrn->pScreen;
2343 if (rotate_pixmap) { /* This should also unmap the buffer object if relevant. */
2344 pScreen->DestroyPixmap(rotate_pixmap);
2347 #if !NOUVEAU_EXA_PIXMAPS
2348 if (data && nv_crtc->shadow) {
2349 exaOffscreenFree(pScreen, nv_crtc->shadow);
2351 #endif /* !NOUVEAU_EXA_PIXMAPS */
2353 nv_crtc->shadow = NULL;
2356 /* NV04-NV10 doesn't support alpha cursors */
2357 static const xf86CrtcFuncsRec nv_crtc_funcs = {
2358 .dpms = nv_crtc_dpms,
2359 .save = nv_crtc_save, /* XXX */
2360 .restore = nv_crtc_restore, /* XXX */
2361 .mode_fixup = nv_crtc_mode_fixup,
2362 .mode_set = nv_crtc_mode_set,
2363 .prepare = nv_crtc_prepare,
2364 .commit = nv_crtc_commit,
2365 .destroy = NULL, /* XXX */
2366 .lock = nv_crtc_lock,
2367 .unlock = nv_crtc_unlock,
2368 .set_cursor_colors = nv_crtc_set_cursor_colors,
2369 .set_cursor_position = nv_crtc_set_cursor_position,
2370 .show_cursor = nv_crtc_show_cursor,
2371 .hide_cursor = nv_crtc_hide_cursor,
2372 .load_cursor_image = nv_crtc_load_cursor_image,
2373 .gamma_set = nv_crtc_gamma_set,
2374 .shadow_create = nv_crtc_shadow_create,
2375 .shadow_allocate = nv_crtc_shadow_allocate,
2376 .shadow_destroy = nv_crtc_shadow_destroy,
2379 /* NV11 and up has support for alpha cursors. */
2380 /* Due to different maximum sizes we cannot allow it to use normal cursors */
2381 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
2382 .dpms = nv_crtc_dpms,
2383 .save = nv_crtc_save, /* XXX */
2384 .restore = nv_crtc_restore, /* XXX */
2385 .mode_fixup = nv_crtc_mode_fixup,
2386 .mode_set = nv_crtc_mode_set,
2387 .prepare = nv_crtc_prepare,
2388 .commit = nv_crtc_commit,
2389 .destroy = NULL, /* XXX */
2390 .lock = nv_crtc_lock,
2391 .unlock = nv_crtc_unlock,
2392 .set_cursor_colors = NULL, /* Alpha cursors do not need this */
2393 .set_cursor_position = nv_crtc_set_cursor_position,
2394 .show_cursor = nv_crtc_show_cursor,
2395 .hide_cursor = nv_crtc_hide_cursor,
2396 .load_cursor_argb = nv_crtc_load_cursor_argb,
2397 .gamma_set = nv_crtc_gamma_set,
2398 .shadow_create = nv_crtc_shadow_create,
2399 .shadow_allocate = nv_crtc_shadow_allocate,
2400 .shadow_destroy = nv_crtc_shadow_destroy,
2405 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
2407 NVPtr pNv = NVPTR(pScrn);
2409 NVCrtcPrivatePtr nv_crtc;
2411 if (pNv->NVArch >= 0x11) {
2412 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
2414 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
2419 nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
2420 nv_crtc->head = crtc_num;
2422 crtc->driver_private = nv_crtc;
2424 NVCrtcLockUnlock(crtc, FALSE);
2427 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2429 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2433 regp = &state->crtc_reg[nv_crtc->head];
2435 NVWriteMiscOut(crtc, regp->MiscOutReg);
2437 for (i = 1; i < 5; i++)
2438 NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
2440 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
2441 NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
2443 for (i = 0; i < 25; i++)
2444 NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
2446 for (i = 0; i < 9; i++)
2447 NVWriteVgaGr(crtc, i, regp->Graphics[i]);
2449 NVEnablePalette(crtc);
2450 for (i = 0; i < 21; i++)
2451 NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
2453 NVDisablePalette(crtc);
2456 static void nv_crtc_fix_nv40_hw_cursor(xf86CrtcPtr crtc)
2458 /* TODO - implement this properly */
2459 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2460 ScrnInfoPtr pScrn = crtc->scrn;
2461 NVPtr pNv = NVPTR(pScrn);
2463 if (pNv->Architecture == NV_ARCH_40) { /* HW bug */
2464 volatile CARD32 curpos = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS);
2465 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS, curpos);
2468 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override)
2470 ScrnInfoPtr pScrn = crtc->scrn;
2471 NVPtr pNv = NVPTR(pScrn);
2472 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2476 regp = &state->crtc_reg[nv_crtc->head];
2478 /* If we ever get down to pre-nv10 cards, then we must reinstate some limits. */
2479 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
2480 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
2481 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
2482 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
2483 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2484 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2485 nvWriteMC(pNv, 0x1588, 0);
2487 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
2488 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
2489 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO, regp->gpio);
2490 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0830, regp->unk830);
2491 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0834, regp->unk834);
2492 if (pNv->Architecture == NV_ARCH_40) {
2493 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0850, regp->unk850);
2494 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_081C, regp->unk81c);
2497 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG, regp->config);
2498 uint32_t reg900 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900);
2499 if (pNv->Architecture == NV_ARCH_40) {
2500 if (regp->config == 0x2) { /* enhanced "horizontal only" non-vga mode */
2501 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 | 0x10000);
2503 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 & ~0x10000);
2507 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
2508 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
2510 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
2511 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
2512 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3C, regp->CRTC[NV_VGA_CRTCX_3C]);
2513 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
2514 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_4B, regp->CRTC[NV_VGA_CRTCX_4B]);
2515 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
2516 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_56, regp->CRTC[NV_VGA_CRTCX_56]);
2518 for (i = 0; i < 0x10; i++)
2519 NVWriteVGACR5758(pNv, nv_crtc->head, i, regp->CR58[i]);
2521 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
2522 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
2524 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
2525 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
2526 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
2527 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
2528 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
2529 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
2530 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
2531 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
2532 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
2533 if (pNv->Architecture >= NV_ARCH_30) {
2534 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
2537 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_43, regp->CRTC[NV_VGA_CRTCX_43]);
2538 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_85, regp->CRTC[NV_VGA_CRTCX_85]);
2539 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_86, regp->CRTC[NV_VGA_CRTCX_86]);
2541 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
2542 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
2543 nv_crtc_fix_nv40_hw_cursor(crtc);
2544 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
2545 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
2547 /* Setting 1 on this value gives you interrupts for every vblank period. */
2548 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_EN_0, 0);
2549 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
2551 pNv->CurrentState = state;
2554 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2556 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2560 regp = &state->crtc_reg[nv_crtc->head];
2562 regp->MiscOutReg = NVReadMiscOut(crtc);
2564 for (i = 0; i < 25; i++)
2565 regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
2567 NVEnablePalette(crtc);
2568 for (i = 0; i < 21; i++)
2569 regp->Attribute[i] = NVReadVgaAttr(crtc, i);
2570 NVDisablePalette(crtc);
2572 for (i = 0; i < 9; i++)
2573 regp->Graphics[i] = NVReadVgaGr(crtc, i);
2575 for (i = 1; i < 5; i++)
2576 regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
2580 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2582 ScrnInfoPtr pScrn = crtc->scrn;
2583 NVPtr pNv = NVPTR(pScrn);
2584 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2588 regp = &state->crtc_reg[nv_crtc->head];
2590 /* If we ever get down to pre-nv10 cards, then we must reinstate some limits. */
2591 regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
2592 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
2593 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
2594 regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
2595 regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
2596 regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
2597 regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
2599 regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
2600 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
2601 if (pNv->Architecture >= NV_ARCH_30) {
2602 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
2604 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
2605 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
2606 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
2607 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
2609 regp->gpio = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO);
2610 regp->unk830 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0830);
2611 regp->unk834 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0834);
2612 if (pNv->Architecture == NV_ARCH_40) {
2613 regp->unk850 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0850);
2614 regp->unk81c = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_081C);
2617 regp->config = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG);
2619 regp->head = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL);
2620 regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
2621 regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
2623 regp->cursorConfig = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG);
2625 regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
2626 regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
2627 regp->CRTC[NV_VGA_CRTCX_3C] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3C);
2628 regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
2629 regp->CRTC[NV_VGA_CRTCX_4B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_4B);
2630 regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
2631 regp->CRTC[NV_VGA_CRTCX_56] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_56);
2632 for (i = 0; i < 0x10; i++)
2633 regp->CR58[i] = NVReadVGACR5758(pNv, nv_crtc->head, i);
2635 regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
2636 regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
2637 regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
2638 regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
2640 regp->CRTC[NV_VGA_CRTCX_43] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_43);
2641 regp->CRTC[NV_VGA_CRTCX_85] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_85);
2642 regp->CRTC[NV_VGA_CRTCX_86] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_86);
2645 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2647 ScrnInfoPtr pScrn = crtc->scrn;
2648 NVPtr pNv = NVPTR(pScrn);
2649 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2653 regp = &state->crtc_reg[nv_crtc->head];
2655 regp->general = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL);
2657 regp->fp_control = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL);
2658 regp->debug_0 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0);
2659 regp->debug_1 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1);
2660 regp->debug_2 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2);
2662 regp->unk_a20 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20);
2663 regp->unk_a24 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24);
2664 regp->unk_a34 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34);
2666 if (pNv->NVArch == 0x11) {
2667 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11);
2668 } else if (pNv->twoHeads) {
2669 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER);
2671 regp->nv10_cursync = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC);
2673 /* The regs below are 0 for non-flatpanels, so you can load and save them */
2675 for (i = 0; i < 7; i++) {
2676 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2677 regp->fp_horiz_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2680 for (i = 0; i < 7; i++) {
2681 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2682 regp->fp_vert_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2685 regp->fp_hvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START);
2686 regp->fp_hvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END);
2687 regp->fp_vvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START);
2688 regp->fp_vvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END);
2691 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2693 ScrnInfoPtr pScrn = crtc->scrn;
2694 NVPtr pNv = NVPTR(pScrn);
2695 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2699 regp = &state->crtc_reg[nv_crtc->head];
2701 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL, regp->general);
2703 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control);
2704 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0, regp->debug_0);
2705 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
2706 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
2708 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20, regp->unk_a20);
2709 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24, regp->unk_a24);
2710 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34, regp->unk_a34);
2712 if (pNv->NVArch == 0x11) {
2713 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11, regp->dither);
2714 } else if (pNv->twoHeads) {
2715 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER, regp->dither);
2717 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
2719 /* The regs below are 0 for non-flatpanels, so you can load and save them */
2721 for (i = 0; i < 7; i++) {
2722 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2723 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_horiz_regs[i]);
2726 for (i = 0; i < 7; i++) {
2727 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2728 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_vert_regs[i]);
2731 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START, regp->fp_hvalid_start);
2732 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END, regp->fp_hvalid_end);
2733 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START, regp->fp_vvalid_start);
2734 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END, regp->fp_vvalid_end);
2738 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y)
2740 ScrnInfoPtr pScrn = crtc->scrn;
2741 NVPtr pNv = NVPTR(pScrn);
2742 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2743 NVFBLayout *pLayout = &pNv->CurrentLayout;
2746 ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
2748 start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
2749 if (crtc->rotatedData != NULL) { /* we do not exist on the real framebuffer */
2750 #if NOUVEAU_EXA_PIXMAPS
2751 start = nv_crtc->shadow->offset;
2753 start = pNv->FB->offset + nv_crtc->shadow->offset; /* We do exist relative to the framebuffer */
2756 start += pNv->FB->offset;
2759 /* 30 bits addresses in 32 bits according to haiku */
2760 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_START, start & 0xfffffffc);
2762 /* set NV4/NV10 byte adress: (bit0 - 1) */
2763 NVWriteVgaAttr(crtc, 0x13, (start & 0x3) << 1);
2769 static void NVCrtcWriteDacMask(xf86CrtcPtr crtc, CARD8 value)
2771 ScrnInfoPtr pScrn = crtc->scrn;
2772 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2773 NVPtr pNv = NVPTR(pScrn);
2774 volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2776 NV_WR08(pDACReg, VGA_DAC_MASK, value);
2779 static CARD8 NVCrtcReadDacMask(xf86CrtcPtr crtc)
2781 ScrnInfoPtr pScrn = crtc->scrn;
2782 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2783 NVPtr pNv = NVPTR(pScrn);
2784 volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2786 return NV_RD08(pDACReg, VGA_DAC_MASK);
2789 static void NVCrtcWriteDacReadAddr(xf86CrtcPtr crtc, CARD8 value)
2791 ScrnInfoPtr pScrn = crtc->scrn;
2792 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2793 NVPtr pNv = NVPTR(pScrn);
2794 volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2796 NV_WR08(pDACReg, VGA_DAC_READ_ADDR, value);
2799 static void NVCrtcWriteDacWriteAddr(xf86CrtcPtr crtc, CARD8 value)
2801 ScrnInfoPtr pScrn = crtc->scrn;
2802 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2803 NVPtr pNv = NVPTR(pScrn);
2804 volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2806 NV_WR08(pDACReg, VGA_DAC_WRITE_ADDR, value);
2809 static void NVCrtcWriteDacData(xf86CrtcPtr crtc, CARD8 value)
2811 ScrnInfoPtr pScrn = crtc->scrn;
2812 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2813 NVPtr pNv = NVPTR(pScrn);
2814 volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2816 NV_WR08(pDACReg, VGA_DAC_DATA, value);
2819 static CARD8 NVCrtcReadDacData(xf86CrtcPtr crtc, CARD8 value)
2821 ScrnInfoPtr pScrn = crtc->scrn;
2822 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2823 NVPtr pNv = NVPTR(pScrn);
2824 volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2826 return NV_RD08(pDACReg, VGA_DAC_DATA);
2829 void NVCrtcLoadPalette(xf86CrtcPtr crtc)
2832 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2834 ScrnInfoPtr pScrn = crtc->scrn;
2835 NVPtr pNv = NVPTR(pScrn);
2837 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2839 NVCrtcSetOwner(crtc);
2840 NVCrtcWriteDacMask(crtc, 0xff);
2841 NVCrtcWriteDacWriteAddr(crtc, 0x00);
2843 for (i = 0; i<768; i++) {
2844 NVCrtcWriteDacData(crtc, regp->DAC[i]);
2846 NVDisablePalette(crtc);
2850 void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
2854 NVCrtcSetOwner(crtc);
2856 scrn = NVReadVgaSeq(crtc, 0x01);
2863 NVVgaSeqReset(crtc, TRUE);
2864 NVWriteVgaSeq(crtc, 0x01, scrn);
2865 NVVgaSeqReset(crtc, FALSE);
2868 /*************************************************************************** \
2870 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
2872 |* NOTICE TO USER: The source code is copyrighted under U.S. and *|
2873 |* international laws. Users and possessors of this source code are *|
2874 |* hereby granted a nonexclusive, royalty-free copyright license to *|
2875 |* use this code in individual and commercial software. *|
2877 |* Any use of this source code must include, in the user documenta- *|
2878 |* tion and internal comments to the code, notices to the end user *|
2881 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
2883 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
2884 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
2885 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
2886 |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
2887 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
2888 |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
2889 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
2890 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
2891 |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
2892 |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
2893 |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
2895 |* U.S. Government End Users. This source code is a "commercial *|
2896 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
2897 |* consisting of "commercial computer software" and "commercial *|
2898 |* computer software documentation," as such terms are used in *|
2899 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
2900 |* ment only as a commercial end item. Consistent with 48 C.F.R. *|
2901 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
2902 |* all U.S. Government End Users acquire the source code with only *|
2903 |* those rights set forth herein. *|
2905 \***************************************************************************/