git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 2006 Dave Airlie
   3  * Copyright 2007 Maarten Maathuis
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
  26  * decleration is at the bottom of this file as it is rather ugly
  27  */
  28
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include <assert.h>
  34 #include "xf86.h"
  35 #include "os.h"
  36 #include "mibank.h"
  37 #include "globals.h"
  38 #include "xf86.h"
  39 #include "xf86Priv.h"
  40 #include "xf86DDC.h"
  41 #include "mipointer.h"
  42 #include "windowstr.h"
  43 #include <randrstr.h>
  44 #include <X11/extensions/render.h>
  45
  46 #include "xf86Crtc.h"
  47 #include "nv_include.h"
  48
  49 #include "vgaHW.h"
  50
  51 #define CRTC_INDEX 0x3d4
  52 #define CRTC_DATA 0x3d5
  53 #define CRTC_IN_STAT_1 0x3da
  54
  55 #define WHITE_VALUE 0x3F
  56 #define BLACK_VALUE 0x00
  57 #define OVERSCAN_VALUE 0x01
  58
  59 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  60 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override);
  61 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  62 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  63 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  64 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  65
  66 static CARD8 NVReadPVIO(xf86CrtcPtr crtc, CARD32 address)
  67 {
  68         ScrnInfoPtr pScrn = crtc->scrn;
  69         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  70         NVPtr pNv = NVPTR(pScrn);
  71
  72         /* Only NV4x have two pvio ranges */
  73         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  74                 return NV_RD08(pNv->PVIO1, address);
  75         } else {
  76                 return NV_RD08(pNv->PVIO0, address);
  77         }
  78 }
  79
  80 static void NVWritePVIO(xf86CrtcPtr crtc, CARD32 address, CARD8 value)
  81 {
  82         ScrnInfoPtr pScrn = crtc->scrn;
  83         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  84         NVPtr pNv = NVPTR(pScrn);
  85
  86         /* Only NV4x have two pvio ranges */
  87         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  88                 NV_WR08(pNv->PVIO1, address, value);
  89         } else {
  90                 NV_WR08(pNv->PVIO0, address, value);
  91         }
  92 }
  93
  94 static void NVWriteMiscOut(xf86CrtcPtr crtc, CARD8 value)
  95 {
  96         NVWritePVIO(crtc, VGA_MISC_OUT_W, value);
  97 }
  98
  99 static CARD8 NVReadMiscOut(xf86CrtcPtr crtc)
 100 {
 101         return NVReadPVIO(crtc, VGA_MISC_OUT_R);
 102 }
 103
 104 void NVWriteVGA(NVPtr pNv, int head, CARD8 index, CARD8 value)
 105 {
 106         volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 107
 108         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 109         NV_WR08(pCRTCReg, CRTC_DATA, value);
 110 }
 111
 112 CARD8 NVReadVGA(NVPtr pNv, int head, CARD8 index)
 113 {
 114         volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 115
 116         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 117         return NV_RD08(pCRTCReg, CRTC_DATA);
 118 }
 119
 120 /* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
 121  * I suspect they in fact do nothing, but are merely a way to carry useful
 122  * per-head variables around
 123  *
 124  * Known uses:
 125  * CR57         CR58
 126  * 0x00         index to the appropriate dcb entry (or 7f for inactive)
 127  * 0x02         dcb entry's "or" value (or 00 for inactive)
 128  * 0x03         bit0 set for dual link (LVDS, possibly elsewhere too)
 129  * 0x08 or 0x09 pxclk in MHz
 130  * 0x0f         laptop panel info -     low nibble for PEXTDEV_BOOT strap
 131  *                                      high nibble for xlat strap value
 132  */
 133
 134 void NVWriteVGACR5758(NVPtr pNv, int head, uint8_t index, uint8_t value)
 135 {
 136         NVWriteVGA(pNv, head, 0x57, index);
 137         NVWriteVGA(pNv, head, 0x58, value);
 138 }
 139
 140 uint8_t NVReadVGACR5758(NVPtr pNv, int head, uint8_t index)
 141 {
 142         NVWriteVGA(pNv, head, 0x57, index);
 143         return NVReadVGA(pNv, head, 0x58);
 144 }
 145
 146 void NVWriteVgaCrtc(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 147 {
 148         ScrnInfoPtr pScrn = crtc->scrn;
 149         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 150         NVPtr pNv = NVPTR(pScrn);
 151
 152         NVWriteVGA(pNv, nv_crtc->head, index, value);
 153 }
 154
 155 CARD8 NVReadVgaCrtc(xf86CrtcPtr crtc, CARD8 index)
 156 {
 157         ScrnInfoPtr pScrn = crtc->scrn;
 158         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 159         NVPtr pNv = NVPTR(pScrn);
 160
 161         return NVReadVGA(pNv, nv_crtc->head, index);
 162 }
 163
 164 static void NVWriteVgaSeq(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 165 {
 166         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 167         NVWritePVIO(crtc, VGA_SEQ_DATA, value);
 168 }
 169
 170 static CARD8 NVReadVgaSeq(xf86CrtcPtr crtc, CARD8 index)
 171 {
 172         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 173         return NVReadPVIO(crtc, VGA_SEQ_DATA);
 174 }
 175
 176 static void NVWriteVgaGr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 177 {
 178         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 179         NVWritePVIO(crtc, VGA_GRAPH_DATA, value);
 180 }
 181
 182 static CARD8 NVReadVgaGr(xf86CrtcPtr crtc, CARD8 index)
 183 {
 184         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 185         return NVReadPVIO(crtc, VGA_GRAPH_DATA);
 186 }
 187
 188
 189 static void NVWriteVgaAttr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 190 {
 191   ScrnInfoPtr pScrn = crtc->scrn;
 192   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 193   NVPtr pNv = NVPTR(pScrn);
 194   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 195
 196   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 197   if (nv_crtc->paletteEnabled)
 198     index &= ~0x20;
 199   else
 200     index |= 0x20;
 201   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 202   NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
 203 }
 204
 205 static CARD8 NVReadVgaAttr(xf86CrtcPtr crtc, CARD8 index)
 206 {
 207   ScrnInfoPtr pScrn = crtc->scrn;
 208   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 209   NVPtr pNv = NVPTR(pScrn);
 210   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 211
 212   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 213   if (nv_crtc->paletteEnabled)
 214     index &= ~0x20;
 215   else
 216     index |= 0x20;
 217   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 218   return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
 219 }
 220
 221 void NVCrtcSetOwner(xf86CrtcPtr crtc)
 222 {
 223         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 224         ScrnInfoPtr pScrn = crtc->scrn;
 225         NVPtr pNv = NVPTR(pScrn);
 226         /* Non standard beheaviour required by NV11 */
 227         if (pNv) {
 228                 uint8_t owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 229                 ErrorF("pre-Owner: 0x%X\n", owner);
 230                 if (owner == 0x04) {
 231                         uint32_t pbus84 = nvReadMC(pNv, 0x1084);
 232                         ErrorF("pbus84: 0x%X\n", pbus84);
 233                         pbus84 &= ~(1<<28);
 234                         ErrorF("pbus84: 0x%X\n", pbus84);
 235                         nvWriteMC(pNv, 0x1084, pbus84);
 236                 }
 237                 /* The blob never writes owner to pcio1, so should we */
 238                 if (pNv->NVArch == 0x11) {
 239                         NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, 0xff);
 240                 }
 241                 NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, nv_crtc->head * 0x3);
 242                 owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 243                 ErrorF("post-Owner: 0x%X\n", owner);
 244         } else {
 245                 ErrorF("pNv pointer is NULL\n");
 246         }
 247 }
 248
 249 static void
 250 NVEnablePalette(xf86CrtcPtr crtc)
 251 {
 252   ScrnInfoPtr pScrn = crtc->scrn;
 253   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 254   NVPtr pNv = NVPTR(pScrn);
 255   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 256
 257   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 258   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
 259   nv_crtc->paletteEnabled = TRUE;
 260 }
 261
 262 static void
 263 NVDisablePalette(xf86CrtcPtr crtc)
 264 {
 265   ScrnInfoPtr pScrn = crtc->scrn;
 266   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 267   NVPtr pNv = NVPTR(pScrn);
 268   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 269
 270   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 271   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
 272   nv_crtc->paletteEnabled = FALSE;
 273 }
 274
 275 static void NVWriteVgaReg(xf86CrtcPtr crtc, CARD32 reg, CARD8 value)
 276 {
 277  ScrnInfoPtr pScrn = crtc->scrn;
 278   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 279   NVPtr pNv = NVPTR(pScrn);
 280   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 281
 282   NV_WR08(pCRTCReg, reg, value);
 283 }
 284
 285 /* perform a sequencer reset */
 286 static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
 287 {
 288   if (start)
 289     NVWriteVgaSeq(crtc, 0x00, 0x1);
 290   else
 291     NVWriteVgaSeq(crtc, 0x00, 0x3);
 292
 293 }
 294 static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
 295 {
 296         CARD8 tmp;
 297
 298         if (on) {
 299                 tmp = NVReadVgaSeq(crtc, 0x1);
 300                 NVVgaSeqReset(crtc, TRUE);
 301                 NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
 302
 303                 NVEnablePalette(crtc);
 304         } else {
 305                 /*
 306                  * Reenable sequencer, then turn on screen.
 307                  */
 308                 tmp = NVReadVgaSeq(crtc, 0x1);
 309                 NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20); /* reenable display */
 310                 NVVgaSeqReset(crtc, FALSE);
 311
 312                 NVDisablePalette(crtc);
 313         }
 314 }
 315
 316 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool Lock)
 317 {
 318         CARD8 cr11;
 319
 320         NVCrtcSetOwner(crtc);
 321
 322         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57);
 323         cr11 = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE);
 324         if (Lock) cr11 |= 0x80;
 325         else cr11 &= ~0x80;
 326         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE, cr11);
 327 }
 328
 329 xf86OutputPtr
 330 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
 331 {
 332         ScrnInfoPtr pScrn = crtc->scrn;
 333         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 334         int i;
 335         for (i = 0; i < xf86_config->num_output; i++) {
 336                 xf86OutputPtr output = xf86_config->output[i];
 337
 338                 if (output->crtc == crtc) {
 339                         return output;
 340                 }
 341         }
 342
 343         return NULL;
 344 }
 345
 346 xf86CrtcPtr
 347 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
 348 {
 349         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 350         int i;
 351
 352         for (i = 0; i < xf86_config->num_crtc; i++) {
 353                 xf86CrtcPtr crtc = xf86_config->crtc[i];
 354                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 355                 if (nv_crtc->head == index)
 356                         return crtc;
 357         }
 358
 359         return NULL;
 360 }
 361
 362 /*
 363  * Calculate the Video Clock parameters for the PLL.
 364  */
 365 /* Code taken from NVClock, with permission of the author (being a GPL->MIT code transfer). */
 366
 367 static void
 368 CalculateVClkNV4x_SingleVCO(NVPtr pNv, struct pll_lims *pll_lim, uint32_t clockIn, uint32_t *n1_best, uint32_t *m1_best, uint32_t *p_best)
 369 {
 370         uint32_t clock, M, N, P;
 371         uint32_t delta, bestDelta, minM, maxM, minN, maxN, maxP;
 372         uint32_t minVCOInputFreq, minVCOFreq, maxVCOFreq;
 373         uint32_t VCOFreq;
 374         uint32_t refClk = pNv->CrystalFreqKHz;
 375         bestDelta = clockIn;
 376
 377         /* bios clocks are in MHz, we use KHz */
 378         minVCOInputFreq = pll_lim->vco1.min_inputfreq*1000;
 379         minVCOFreq = pll_lim->vco1.minfreq*1000;
 380         maxVCOFreq = pll_lim->vco1.maxfreq*1000;
 381         minM = pll_lim->vco1.min_m;
 382         maxM = pll_lim->vco1.max_m;
 383         minN = pll_lim->vco1.min_n;
 384         maxN = pll_lim->vco1.max_n;
 385
 386         maxP = 6;
 387
 388         /* The optimal frequency for the PLL to work at is somewhere in the center of its range.
 389         /  Choose a post divider in such a way to achieve this.
 390         /  The G8x nv driver does something similar but they they derive a minP and maxP. That
 391         /  doesn't seem required as you get so many matching clocks that you don't enter a second
 392         /  iteration for P. (The minP / maxP values in the nv driver only differ at most 1, so it is for
 393         /  some rare corner cases.
 394         */
 395         for (P=0, VCOFreq=maxVCOFreq/2; clockIn<=VCOFreq && P <= maxP; P++)
 396         {
 397                 VCOFreq /= 2;
 398         }
 399
 400         /* Calculate the m and n values. There are a lot of values which give the same speed;
 401         /  We choose the speed for which the difference with the request speed is as small as possible.
 402         */
 403         for (M=minM; M<=maxM; M++)
 404         {
 405                 /* The VCO has a minimum input frequency */
 406                 if ((refClk/M) < minVCOInputFreq)
 407                         break;
 408
 409                 for (N=minN; N<=maxN; N++)
 410                 {
 411                         /* Calculate the frequency generated by VCO1 */
 412                         clock = (int)(refClk * N / (float)M);
 413
 414                         /* Verify if the clock lies within the output limits of VCO1 */
 415                         if (clock < minVCOFreq)
 416                                 continue;
 417                         else if (clock > maxVCOFreq) /* It is no use to continue as the clock will only become higher */
 418                                 break;
 419
 420                         clock >>= P;
 421                         delta = abs((int)(clockIn - clock));
 422                         /* When the difference is 0 or less than .5% accept the speed */
 423                         if (((delta == 0) || ((float)delta/(float)clockIn <= 0.005)))
 424                         {
 425                                 *m1_best = M;
 426                                 *n1_best = N;
 427                                 *p_best = P;
 428                                 return;
 429                         }
 430
 431                         /* When the new difference is smaller than the old one, use this one */
 432                         if (delta < bestDelta)
 433                         {
 434                                 bestDelta = delta;
 435                                 *m1_best = M;
 436                                 *n1_best = N;
 437                                 *p_best = P;
 438                         }
 439                 }
 440         }
 441 }
 442
 443 static void
 444 CalculateVClkNV4x_DoubleVCO(NVPtr pNv, struct pll_lims *pll_lim, uint32_t clockIn, uint32_t *n1_best, uint32_t *n2_best, uint32_t *m1_best, uint32_t *m2_best, uint32_t *p_best)
 445 {
 446         uint32_t clock1, clock2, M, M2, N, N2, P;
 447         uint32_t delta, bestDelta, minM, minM2, maxM, maxM2, minN, minN2, maxN, maxN2, maxP;
 448         uint32_t minVCOInputFreq, minVCO2InputFreq, maxVCO2InputFreq, minVCOFreq, minVCO2Freq, maxVCOFreq, maxVCO2Freq;
 449         uint32_t VCO2Freq, maxClock;
 450         uint32_t refClk = pNv->CrystalFreqKHz;
 451         bestDelta = clockIn;
 452
 453         /* bios clocks are in MHz, we use KHz */
 454         minVCOInputFreq = pll_lim->vco1.min_inputfreq*1000;
 455         minVCOFreq = pll_lim->vco1.minfreq*1000;
 456         maxVCOFreq = pll_lim->vco1.maxfreq*1000;
 457         minM = pll_lim->vco1.min_m;
 458         maxM = pll_lim->vco1.max_m;
 459         minN = pll_lim->vco1.min_n;
 460         maxN = pll_lim->vco1.max_n;
 461
 462         minVCO2InputFreq = pll_lim->vco2.min_inputfreq*1000;
 463         maxVCO2InputFreq = pll_lim->vco2.max_inputfreq*1000;
 464         minVCO2Freq = pll_lim->vco2.minfreq*1000;
 465         maxVCO2Freq = pll_lim->vco2.maxfreq*1000;
 466         minM2 = pll_lim->vco2.min_m;
 467         maxM2 = pll_lim->vco2.max_m;
 468         minN2 = pll_lim->vco2.min_n;
 469         maxN2 = pll_lim->vco2.max_n;
 470
 471         maxP = 6;
 472
 473         maxClock = maxVCO2Freq;
 474         /* If the requested clock is behind the bios limits, try it anyway */
 475         if (clockIn > maxVCO2Freq)
 476                 maxClock = clockIn + clockIn/200; /* Add a .5% margin */
 477
 478         /* The optimal frequency for the PLL to work at is somewhere in the center of its range.
 479         /  Choose a post divider in such a way to achieve this.
 480         /  The G8x nv driver does something similar but they they derive a minP and maxP. That
 481         /  doesn't seem required as you get so many matching clocks that you don't enter a second
 482         /  iteration for P. (The minP / maxP values in the nv driver only differ at most 1, so it is for
 483         /  some rare corner cases.
 484         */
 485         for (P=0, VCO2Freq=maxClock/2; clockIn<=VCO2Freq && P <= maxP; P++)
 486         {
 487                 VCO2Freq /= 2;
 488         }
 489
 490         /* The PLLs on Geforce6/7 hardware can operate in a single stage made with only 1 VCO
 491         /  and a cascade mode of two VCOs. This second mode is in general used for relatively high
 492         /  frequencies. The loop below calculates the divider and multiplier ratios for the cascade
 493         /  mode. The code takes into account limits defined in the video bios.
 494         */
 495         for (M=minM; M<=maxM; M++)
 496         {
 497                 /* The VCO has a minimum input frequency */
 498                 if ((refClk/M) < minVCOInputFreq)
 499                         break;
 500
 501                 for (N=minN; N<=maxN; N++)
 502                 {
 503                         /* Calculate the frequency generated by VCO1 */
 504                         clock1 = (int)(refClk * N / (float)M);
 505                         /* Verify if the clock lies within the output limits of VCO1 */
 506                         if ( (clock1 < minVCOFreq) )
 507                                 continue;
 508                         else if (clock1 > maxVCOFreq) /* For future N, the clock will only increase so stop; xorg nv continues but that is useless */
 509                                 break;
 510
 511                         for (M2=minM2; M2<=maxM2; M2++)
 512                         {
 513                                 /* The clock fed to the second VCO needs to lie within a certain input range */
 514                                 if (clock1 / M2 < minVCO2InputFreq)
 515                                         break;
 516                                 else if (clock1 / M2 > maxVCO2InputFreq)
 517                                         continue;
 518
 519                                 N2 = (int)((float)((clockIn << P) * M * M2) / (float)(refClk * N)+.5);
 520                                 if( (N2 < minN2) || (N2 > maxN2) )
 521                                         continue;
 522
 523                                 /* The clock before being fed to the post-divider needs to lie within a certain range.
 524                                 /  Further there are some limits on N2/M2.
 525                                 */
 526                                 clock2 = (int)((float)(N*N2)/(M*M2) * refClk);
 527                                 if( (clock2 < minVCO2Freq) || (clock2 > maxClock))// || ((N2 / M2) < 4) || ((N2 / M2) > 10) )
 528                                         continue;
 529
 530                                 /* The post-divider delays the 'high' clock to create a low clock if requested.
 531                                 /  This post-divider exists because the VCOs can only generate frequencies within
 532                                 /  a limited frequency range. This range has been tuned to lie around half of its max
 533                                 /  input frequency. It tries to calculate all clocks (including lower ones) around this
 534                                 /  'center' frequency.
 535                                 */
 536                                 clock2 >>= P;
 537                                 delta = abs((int)(clockIn - clock2));
 538
 539                                 /* When the difference is 0 or less than .5% accept the speed */
 540                                 if (((delta == 0) || ((float)delta/(float)clockIn <= 0.005)))
 541                                 {
 542                                         *m1_best = M;
 543                                         *m2_best = M2;
 544                                         *n1_best = N;
 545                                         *n2_best = N2;
 546                                         *p_best = P;
 547                                         return;
 548                                 }
 549
 550                                 /* When the new difference is smaller than the old one, use this one */
 551                                 if (delta < bestDelta)
 552                                 {
 553                                         bestDelta = delta;
 554                                         *m1_best = M;
 555                                         *m2_best = M2;
 556                                         *n1_best = N;
 557                                         *n2_best = N2;
 558                                         *p_best = P;
 559                                 }
 560                         }
 561                 }
 562         }
 563 }
 564
 565 /* BIG NOTE: modifying vpll1 and vpll2 does not work, what bit is the switch to allow it? */
 566
 567 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
 568 /* They are only valid for NV4x, appearantly reordered for NV5x */
 569 /* gpu pll: 0x4000 + 0x4004
 570  * unknown pll: 0x4008 + 0x400c
 571  * vpll1: 0x4010 + 0x4014
 572  * vpll2: 0x4018 + 0x401c
 573  * unknown pll: 0x4020 + 0x4024
 574  * unknown pll: 0x4038 + 0x403c
 575  * Some of the unknown's are probably memory pll's.
 576  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
 577  * 1 and 2 refer to the registers of each pair. There is only one post divider.
 578  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
 579  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
 580  *     bit8: A switch that turns of the second divider and multiplier off.
 581  *     bit12: Also a switch, i haven't seen it yet.
 582  *     bit16-19: p-divider
 583  *     but 28-31: Something related to the mode that is used (see bit8).
 584  * 2) bit0-7: m-divider (a)
 585  *     bit8-15: n-multiplier (a)
 586  *     bit16-23: m-divider (b)
 587  *     bit24-31: n-multiplier (b)
 588  */
 589
 590 /* Modifying the gpu pll for example requires:
 591  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 592  * This is not needed for the vpll's which have their own bits.
 593  */
 594
 595 static void
 596 CalculateVClkNV4x(
 597         ScrnInfoPtr pScrn,
 598         uint32_t requested_clock,
 599         uint32_t *given_clock,
 600         uint32_t *pll_a,
 601         uint32_t *pll_b,
 602         uint32_t *reg580,
 603         Bool    *db1_ratio,
 604         Bool primary
 605 )
 606 {
 607         NVPtr pNv = NVPTR(pScrn);
 608         struct pll_lims pll_lim;
 609         /* We have 2 mulitpliers, 2 dividers and one post divider */
 610         /* Note that p is only 3 bits */
 611         uint32_t m1_best = 0, m2_best = 0, n1_best = 0, n2_best = 0, p_best = 0;
 612         uint32_t special_bits = 0;
 613
 614         if (primary) {
 615                 if (!get_pll_limits(pScrn, VPLL1, &pll_lim))
 616                         return;
 617         } else
 618                 if (!get_pll_limits(pScrn, VPLL2, &pll_lim))
 619                         return;
 620
 621         if (requested_clock < pll_lim.vco1.maxfreq*1000) { /* single VCO */
 622                 *db1_ratio = TRUE;
 623                 /* Turn the second set of divider and multiplier off */
 624                 /* Bogus data, the same nvidia uses */
 625                 n2_best = 1;
 626                 m2_best = 31;
 627                 CalculateVClkNV4x_SingleVCO(pNv, &pll_lim, requested_clock, &n1_best, &m1_best, &p_best);
 628         } else { /* dual VCO */
 629                 *db1_ratio = FALSE;
 630                 CalculateVClkNV4x_DoubleVCO(pNv, &pll_lim, requested_clock, &n1_best, &n2_best, &m1_best, &m2_best, &p_best);
 631         }
 632
 633         /* Are this all (relevant) G70 cards? */
 634         if (pNv->NVArch == 0x4B || pNv->NVArch == 0x46 || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
 635                 /* This is a big guess, but should be reasonable until we can narrow it down. */
 636                 if (*db1_ratio) {
 637                         special_bits = 0x1;
 638                 } else {
 639                         special_bits = 0x3;
 640                 }
 641         }
 642
 643         /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
 644         /* Let's keep the special bits, if the bios already set them */
 645         *pll_a = (special_bits << 30) | (p_best << 16) | (n1_best << 8) | (m1_best << 0);
 646         *pll_b = (1 << 31) | (n2_best << 8) | (m2_best << 0);
 647
 648         if (*db1_ratio) {
 649                 if (primary) {
 650                         *reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 651                 } else {
 652                         *reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 653                 }
 654         } else {
 655                 if (primary) {
 656                         *reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
 657                 } else {
 658                         *reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
 659                 }
 660         }
 661
 662         if (*db1_ratio) {
 663                 ErrorF("vpll: n1 %d m1 %d p %d db1_ratio %d\n", n1_best, m1_best, p_best, *db1_ratio);
 664         } else {
 665                 ErrorF("vpll: n1 %d n2 %d m1 %d m2 %d p %d db1_ratio %d\n", n1_best, n2_best, m1_best, m2_best, p_best, *db1_ratio);
 666         }
 667 }
 668
 669 static void nv40_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 670 {
 671         state->vpll1_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 672         state->vpll1_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 673         state->vpll2_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 674         state->vpll2_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 675         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 676         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 677         state->reg580 = nvReadRAMDAC0(pNv, NV_RAMDAC_580);
 678         state->reg594 = nvReadRAMDAC0(pNv, NV_RAMDAC_594);
 679 }
 680
 681 static void nv40_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 682 {
 683         ScrnInfoPtr pScrn = crtc->scrn;
 684         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 685         NVPtr pNv = NVPTR(pScrn);
 686         CARD32 fp_debug_0[2];
 687         uint32_t index[2];
 688         fp_debug_0[0] = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
 689         fp_debug_0[1] = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
 690
 691         uint32_t reg_c040_old = nvReadMC(pNv, 0xc040);
 692
 693         /* The TMDS_PLL switch is on the actual ramdac */
 694         if (state->crosswired) {
 695                 index[0] = 1;
 696                 index[1] = 0;
 697                 ErrorF("Crosswired pll state load\n");
 698         } else {
 699                 index[0] = 0;
 700                 index[1] = 1;
 701         }
 702
 703         if (state->vpll2_b) {
 704                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0,
 705                         fp_debug_0[index[1]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 706
 707                 /* Wait for the situation to stabilise */
 708                 usleep(5000);
 709
 710                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 711                 /* for vpll2 change bits 18 and 19 are disabled */
 712                 reg_c040 &= ~(0x3 << 18);
 713                 nvWriteMC(pNv, 0xc040, reg_c040);
 714
 715                 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 716                 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 717
 718                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2_a);
 719                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 720
 721                 ErrorF("writing pllsel %08X\n", state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 722                 /* Let's keep the primary vpll off */
 723                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 724
 725                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 726                 ErrorF("writing reg580 %08X\n", state->reg580);
 727
 728                 /* We need to wait a while */
 729                 usleep(5000);
 730                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 731
 732                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[1]]);
 733
 734                 /* Wait for the situation to stabilise */
 735                 usleep(5000);
 736         }
 737
 738         if (state->vpll1_b) {
 739                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0,
 740                         fp_debug_0[index[0]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 741
 742                 /* Wait for the situation to stabilise */
 743                 usleep(5000);
 744
 745                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 746                 /* for vpll2 change bits 16 and 17 are disabled */
 747                 reg_c040 &= ~(0x3 << 16);
 748                 nvWriteMC(pNv, 0xc040, reg_c040);
 749
 750                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 751                 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 752
 753                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll1_a);
 754                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpll1_b);
 755
 756                 ErrorF("writing pllsel %08X\n", state->pllsel);
 757                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 758
 759                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 760                 ErrorF("writing reg580 %08X\n", state->reg580);
 761
 762                 /* We need to wait a while */
 763                 usleep(5000);
 764                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 765
 766                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[0]]);
 767
 768                 /* Wait for the situation to stabilise */
 769                 usleep(5000);
 770         }
 771
 772         /* Let's be sure not to wake up any crtc's from dpms. */
 773         /* But we do want to keep our newly set crtc awake. */
 774         if (nv_crtc->head == 1) {
 775                 nvWriteMC(pNv, 0xc040, reg_c040_old | (pNv->misc_info.reg_c040 & (0x3 << 18)));
 776         } else {
 777                 nvWriteMC(pNv, 0xc040, reg_c040_old | (pNv->misc_info.reg_c040 & (0x3 << 16)));
 778         }
 779
 780         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 781         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 782
 783         ErrorF("writing reg594 %08X\n", state->reg594);
 784         nvWriteRAMDAC0(pNv, NV_RAMDAC_594, state->reg594);
 785 }
 786
 787 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 788 {
 789         state->vpll = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 790         if(pNv->twoHeads) {
 791                 state->vpll2 = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 792         }
 793         if(pNv->twoStagePLL) {
 794                 state->vpllB = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 795                 state->vpll2B = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 796         }
 797         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 798         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 799 }
 800
 801
 802 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 803 {
 804         /* This sequence is important, the NV28 is very sensitive in this area. */
 805         /* Keep pllsel last and sel_clk first. */
 806         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 807         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 808
 809         if (state->vpll2) {
 810                 if(pNv->twoHeads) {
 811                         ErrorF("writing vpll2 %08X\n", state->vpll2);
 812                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2);
 813                 }
 814                 if(pNv->twoStagePLL) {
 815                         ErrorF("writing vpll2B %08X\n", state->vpll2B);
 816                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2B);
 817                 }
 818         }
 819
 820         if (state->vpll) {
 821                 ErrorF("writing vpll %08X\n", state->vpll);
 822                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll);
 823                 if(pNv->twoStagePLL) {
 824                         ErrorF("writing vpllB %08X\n", state->vpllB);
 825                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpllB);
 826                 }
 827         }
 828
 829         ErrorF("writing pllsel %08X\n", state->pllsel);
 830         nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 831 }
 832
 833 #define IS_NV44P (pNv->NVArch >= 0x44 ? 1 : 0)
 834 #define SEL_CLK_OFFSET (nv_get_sel_clk_offset(pNv->NVArch, nv_output->bus))
 835
 836 #define WIPE_OTHER_CLOCKS(_sel_clk, _head, _bus) (nv_wipe_other_clocks(_sel_clk, pNv->NVArch, _head, _bus))
 837
 838 /*
 839  * Calculate extended mode parameters (SVGA) and save in a
 840  * mode state structure.
 841  * State is not specific to a single crtc, but shared.
 842  */
 843 void nv_crtc_calc_state_ext(
 844         xf86CrtcPtr     crtc,
 845         int                     bpp,
 846         int                     DisplayWidth, /* Does this change after setting the mode? */
 847         int                     CrtcHDisplay,
 848         int                     CrtcVDisplay,
 849         int                     dotClock,
 850         int                     flags
 851 )
 852 {
 853         ScrnInfoPtr pScrn = crtc->scrn;
 854         uint32_t pixelDepth, VClk = 0;
 855         CARD32 CursorStart;
 856         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 857         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 858         NVCrtcRegPtr regp;
 859         NVPtr pNv = NVPTR(pScrn);
 860         RIVA_HW_STATE *state;
 861         int num_crtc_enabled, i;
 862
 863         state = &pNv->ModeReg;
 864
 865         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 866
 867         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 868         NVOutputPrivatePtr nv_output = NULL;
 869         if (output) {
 870                 nv_output = output->driver_private;
 871         }
 872
 873         /*
 874          * Extended RIVA registers.
 875          */
 876         pixelDepth = (bpp + 1)/8;
 877         if (pNv->Architecture == NV_ARCH_40) {
 878                 /* Does register 0x580 already have a value? */
 879                 if (!state->reg580) {
 880                         state->reg580 = pNv->misc_info.ramdac_0_reg_580;
 881                 }
 882                 if (nv_crtc->head == 1) {
 883                         CalculateVClkNV4x(pScrn, dotClock, &VClk, &state->vpll2_a, &state->vpll2_b, &state->reg580, &state->db1_ratio[1], FALSE);
 884                 } else {
 885                         CalculateVClkNV4x(pScrn, dotClock, &VClk, &state->vpll1_a, &state->vpll1_b, &state->reg580, &state->db1_ratio[0], TRUE);
 886                 }
 887         } else if (pNv->twoStagePLL) {
 888                 struct pll_lims pll_lim;
 889                 int NM1, NM2, log2P;
 890                 get_pll_limits(pScrn, 0, &pll_lim);
 891                 VClk = getMNP_double(pNv, &pll_lim, dotClock, &NM1, &NM2, &log2P);
 892                 state->pll = log2P << 16 | NM1;
 893                 state->pllB = 1 << 31 | NM2;
 894         } else {
 895                 int NM, log2P;
 896                 VClk = getMNP_single(pNv, dotClock, &NM, &log2P);
 897                 state->pll = log2P << 16 | NM;
 898         }
 899
 900         switch (pNv->Architecture) {
 901         case NV_ARCH_04:
 902                 nv4UpdateArbitrationSettings(VClk,
 903                                                 pixelDepth * 8,
 904                                                 &(state->arbitration0),
 905                                                 &(state->arbitration1),
 906                                                 pNv);
 907                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
 908                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
 909                 if (flags & V_DBLSCAN)
 910                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 911                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
 912                 state->pllsel   |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
 913                 state->config   = 0x00001114;
 914                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 915                 break;
 916         case NV_ARCH_10:
 917         case NV_ARCH_20:
 918         case NV_ARCH_30:
 919         default:
 920                 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
 921                         ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
 922                         state->arbitration0 = 128;
 923                         state->arbitration1 = 0x0480;
 924                 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
 925                         ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
 926                         nForceUpdateArbitrationSettings(VClk,
 927                                                 pixelDepth * 8,
 928                                                 &(state->arbitration0),
 929                                                 &(state->arbitration1),
 930                                                 pNv);
 931                 } else if (pNv->Architecture < NV_ARCH_30) {
 932                         nv10UpdateArbitrationSettings(VClk,
 933                                                 pixelDepth * 8,
 934                                                 &(state->arbitration0),
 935                                                 &(state->arbitration1),
 936                                                 pNv);
 937                 } else {
 938                         nv30UpdateArbitrationSettings(pNv,
 939                                                 &(state->arbitration0),
 940                                                 &(state->arbitration1));
 941                 }
 942
 943                 if (nv_crtc->head == 1) {
 944                         CursorStart = pNv->Cursor2->offset;
 945                 } else {
 946                         CursorStart = pNv->Cursor->offset;
 947                 }
 948
 949                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
 950                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
 951                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
 952
 953                 if (flags & V_DBLSCAN)
 954                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 955
 956                 state->config   = nvReadFB(pNv, NV_PFB_CFG0);
 957                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 958                 break;
 959         }
 960
 961         /* okay do we have 2 CRTCs running ? */
 962         num_crtc_enabled = 0;
 963         for (i = 0; i < xf86_config->num_crtc; i++) {
 964                 if (xf86_config->crtc[i]->enabled) {
 965                         num_crtc_enabled++;
 966                 }
 967         }
 968
 969         ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
 970
 971         if (pNv->Architecture < NV_ARCH_40) {
 972                 /* We need this before the next code */
 973                 if (nv_crtc->head == 1) {
 974                         state->vpll2 = state->pll;
 975                         state->vpll2B = state->pllB;
 976                 } else {
 977                         state->vpll = state->pll;
 978                         state->vpllB = state->pllB;
 979                 }
 980         }
 981
 982         /* The main stuff seems to be valid for NV3x also. */
 983         if (pNv->Architecture >= NV_ARCH_30) {
 984                 /* This register is only used on the primary ramdac */
 985                 /* This seems to be needed to select the proper clocks, otherwise bad things happen */
 986
 987                 if (!state->sel_clk)
 988                         state->sel_clk = pNv->misc_info.sel_clk & ~(0xf << 16);
 989
 990                 if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
 991                         /* Only wipe when are a relevant (digital) output. */
 992                         state->sel_clk &= ~(0xf << 16);
 993                         Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
 994                         /* Even with two dvi, this should not conflict. */
 995                         if (crossed_clocks) {
 996                                 state->sel_clk |= (0x1 << 16);
 997                         } else {
 998                                 state->sel_clk |= (0x4 << 16);
 999                         }
1000                 }
1001
1002                 /* Some cards, specifically dual dvi/lvds cards set another bitrange.
1003                  * I suspect inverse beheaviour to the normal bitrange, but i am not a 100% certain about this.
1004                  * This is all based on default settings found in mmio-traces.
1005                  * The blob never changes these, as it doesn't run unusual output configurations.
1006                  * It seems to prefer situations that avoid changing these bits (for a good reason?).
1007                  * I still don't know the purpose of value 2, it's similar to 4, but what exactly does it do?
1008                  */
1009
1010                 /* Some extra info:
1011                  * nv30:
1012                  *      bit 0           NVClk spread spectrum on/off
1013                  *      bit 2           MemClk spread spectrum on/off
1014                  *      bit 4           PixClk1 spread spectrum on/off
1015                  *      bit 6           PixClk2 spread spectrum on/off
1016
1017                  *      nv40:
1018                  *      what causes setting of bits not obvious but:
1019                  *      bits 4&5                relate to headA
1020                  *      bits 6&7                relate to headB
1021                 */
1022                 if (pNv->Architecture == NV_ARCH_40) {
1023                         for (i = 0; i < 4; i++) {
1024                                 uint32_t var = (state->sel_clk & (0xf << 4*i)) >> 4*i;
1025                                 if (var == 0x1 || var == 0x4) {
1026                                         state->sel_clk &= ~(0xf << 4*i);
1027                                         Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1028                                         if (crossed_clocks) {
1029                                                 state->sel_clk |= (0x4 << 4*i);
1030                                         } else {
1031                                                 state->sel_clk |= (0x1 << 4*i);
1032                                         }
1033                                         break; /* This should only occur once. */
1034                                 }
1035                         }
1036                 }
1037
1038                 /* Are we crosswired? */
1039                 if (output && nv_crtc->head != nv_output->preferred_output) {
1040                         state->crosswired = TRUE;
1041                 } else {
1042                         state->crosswired = FALSE;
1043                 }
1044
1045                 if (nv_crtc->head == 1) {
1046                         if (state->db1_ratio[1])
1047                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1048                 } else if (nv_crtc->head == 0) {
1049                         if (state->db1_ratio[0])
1050                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1051                 }
1052         } else {
1053                 /* Do NV1x/NV2x cards need anything in sel_clk? */
1054                 state->sel_clk = 0x0;
1055                 state->crosswired = FALSE;
1056         }
1057
1058         /* The NV40 seems to have more similarities to NV3x than other cards. */
1059         if (pNv->NVArch < 0x41) {
1060                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL;
1061                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL;
1062         }
1063
1064         if (nv_crtc->head == 1) {
1065                 if (!state->db1_ratio[1]) {
1066                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1067                 } else {
1068                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1069                 }
1070                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
1071         } else {
1072                 if (!state->db1_ratio[0]) {
1073                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1074                 } else {
1075                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1076                 }
1077                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
1078         }
1079
1080         /* The blob uses this always, so let's do the same */
1081         if (pNv->Architecture == NV_ARCH_40) {
1082                 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
1083         }
1084
1085         /* The primary output resource doesn't seem to care */
1086         if (output && pNv->Architecture == NV_ARCH_40 && nv_output->output_resource == 1) { /* This is the "output" */
1087                 /* non-zero values are for analog, don't know about tv-out and the likes */
1088                 if (output && nv_output->type != OUTPUT_ANALOG) {
1089                         state->reg594 = 0x0;
1090                 } else if (output) {
1091                         /* Are we a flexible output? */
1092                         if (ffs(pNv->dcb_table.entry[nv_output->dcb_entry].or) & OUTPUT_0) {
1093                                 state->reg594 = 0x1;
1094                                 pNv->restricted_mode = FALSE;
1095                         } else {
1096                                 state->reg594 = 0x0;
1097                                 pNv->restricted_mode = TRUE;
1098                         }
1099
1100                         /* More values exist, but they seem related to the 3rd dac (tv-out?) somehow */
1101                         /* bit 16-19 are bits that are set on some G70 cards */
1102                         /* Those bits are also set to the 3rd OUTPUT register */
1103                         if (nv_crtc->head == 1) {
1104                                 state->reg594 |= 0x100;
1105                         }
1106                 }
1107         }
1108
1109         regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
1110         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
1111         if (pNv->Architecture >= NV_ARCH_30) {
1112                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
1113         }
1114
1115         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
1116         regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
1117 }
1118
1119 static void
1120 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
1121 {
1122         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1123         ScrnInfoPtr pScrn = crtc->scrn;
1124         NVPtr pNv = NVPTR(pScrn);
1125         unsigned char seq1 = 0, crtc17 = 0;
1126         unsigned char crtc1A;
1127
1128         ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->head, mode);
1129
1130         NVCrtcSetOwner(crtc);
1131
1132         crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
1133         switch(mode) {
1134                 case DPMSModeStandby:
1135                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
1136                 seq1 = 0x20;
1137                 crtc17 = 0x80;
1138                 crtc1A |= 0x80;
1139                 break;
1140         case DPMSModeSuspend:
1141                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
1142                 seq1 = 0x20;
1143                 crtc17 = 0x80;
1144                 crtc1A |= 0x40;
1145                 break;
1146         case DPMSModeOff:
1147                 /* Screen: Off; HSync: Off, VSync: Off */
1148                 seq1 = 0x20;
1149                 crtc17 = 0x00;
1150                 crtc1A |= 0xC0;
1151                 break;
1152         case DPMSModeOn:
1153         default:
1154                 /* Screen: On; HSync: On, VSync: On */
1155                 seq1 = 0x00;
1156                 crtc17 = 0x80;
1157                 break;
1158         }
1159
1160         NVVgaSeqReset(crtc, TRUE);
1161         /* Each head has it's own sequencer, so we can turn it off when we want */
1162         seq1 |= (NVReadVgaSeq(crtc, 0x01) & ~0x20);
1163         NVWriteVgaSeq(crtc, 0x1, seq1);
1164         crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
1165         usleep(10000);
1166         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
1167         NVVgaSeqReset(crtc, FALSE);
1168
1169         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
1170
1171         /* We can completely disable a vpll if the crtc is off. */
1172         if (pNv->Architecture == NV_ARCH_40) {
1173                 uint32_t reg_c040_old = nvReadMC(pNv, 0xc040);
1174                 if (mode == DPMSModeOn) {
1175                         nvWriteMC(pNv, 0xc040, reg_c040_old | (pNv->misc_info.reg_c040 & (0x3 << (16 + 2*nv_crtc->head))));
1176                 } else {
1177                         nvWriteMC(pNv, 0xc040, reg_c040_old & ~(pNv->misc_info.reg_c040 & (0x3 << (16 + 2*nv_crtc->head))));
1178                 }
1179         }
1180
1181         /* I hope this is the right place */
1182         if (crtc->enabled && mode == DPMSModeOn) {
1183                 pNv->crtc_active[nv_crtc->head] = TRUE;
1184         } else {
1185                 pNv->crtc_active[nv_crtc->head] = FALSE;
1186         }
1187 }
1188
1189 static Bool
1190 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
1191                      DisplayModePtr adjusted_mode)
1192 {
1193         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1194         ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->head);
1195
1196         return TRUE;
1197 }
1198
1199 static void
1200 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1201 {
1202         ScrnInfoPtr pScrn = crtc->scrn;
1203         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1204         NVCrtcRegPtr regp;
1205         NVPtr pNv = NVPTR(pScrn);
1206         NVFBLayout *pLayout = &pNv->CurrentLayout;
1207         int depth = pScrn->depth;
1208
1209         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1210
1211         /* Calculate our timings */
1212         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
1213         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
1214         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
1215         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
1216         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
1217         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
1218         int vertDisplay         = mode->CrtcVDisplay                    - 1;
1219         int vertStart           = mode->CrtcVSyncStart          - 1;
1220         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
1221         int vertTotal           = mode->CrtcVTotal                      - 2;
1222         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
1223         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
1224
1225         Bool is_fp = FALSE;
1226
1227         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1228         NVOutputPrivatePtr nv_output = NULL;
1229         if (output) {
1230                 nv_output = output->driver_private;
1231
1232                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1233                         is_fp = TRUE;
1234         }
1235
1236         ErrorF("Mode clock: %d\n", mode->Clock);
1237         ErrorF("Adjusted mode clock: %d\n", adjusted_mode->Clock);
1238
1239         /* Reverted to what nv did, because that works for all resolutions on flatpanels */
1240         if (is_fp) {
1241                 vertStart = vertTotal - 3;
1242                 vertEnd = vertTotal - 2;
1243                 vertBlankStart = vertStart;
1244                 horizStart = horizTotal - 5;
1245                 horizEnd = horizTotal - 2;
1246                 horizBlankEnd = horizTotal + 4;
1247                 if (pNv->overlayAdaptor) {
1248                         /* This reportedly works around Xv some overlay bandwidth problems*/
1249                         horizTotal += 2;
1250                 }
1251         }
1252
1253         if(mode->Flags & V_INTERLACE)
1254                 vertTotal |= 1;
1255
1256         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
1257         ErrorF("horizStart: 0x%X \n", horizStart);
1258         ErrorF("horizEnd: 0x%X \n", horizEnd);
1259         ErrorF("horizTotal: 0x%X \n", horizTotal);
1260         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
1261         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
1262         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
1263         ErrorF("vertStart: 0x%X \n", vertStart);
1264         ErrorF("vertEnd: 0x%X \n", vertEnd);
1265         ErrorF("vertTotal: 0x%X \n", vertTotal);
1266         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
1267         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
1268
1269         /*
1270         * compute correct Hsync & Vsync polarity
1271         */
1272         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
1273                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
1274
1275                 regp->MiscOutReg = 0x23;
1276                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
1277                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
1278         } else {
1279                 int VDisplay = mode->VDisplay;
1280                 if (mode->Flags & V_DBLSCAN)
1281                         VDisplay *= 2;
1282                 if (mode->VScan > 1)
1283                         VDisplay *= mode->VScan;
1284                 if (VDisplay < 400) {
1285                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
1286                 } else if (VDisplay < 480) {
1287                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
1288                 } else if (VDisplay < 768) {
1289                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
1290                 } else {
1291                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
1292                 }
1293         }
1294
1295         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
1296
1297         /*
1298         * Time Sequencer
1299         */
1300         if (depth == 4) {
1301                 regp->Sequencer[0] = 0x02;
1302         } else {
1303                 regp->Sequencer[0] = 0x00;
1304         }
1305         /* 0x20 disables the sequencer */
1306         if (mode->Flags & V_CLKDIV2) {
1307                 regp->Sequencer[1] = 0x29;
1308         } else {
1309                 regp->Sequencer[1] = 0x21;
1310         }
1311         if (depth == 1) {
1312                 regp->Sequencer[2] = 1 << BIT_PLANE;
1313         } else {
1314                 regp->Sequencer[2] = 0x0F;
1315                 regp->Sequencer[3] = 0x00;                     /* Font select */
1316         }
1317         if (depth < 8) {
1318                 regp->Sequencer[4] = 0x06;                             /* Misc */
1319         } else {
1320                 regp->Sequencer[4] = 0x0E;                             /* Misc */
1321         }
1322
1323         /*
1324         * CRTC Controller
1325         */
1326         regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
1327         regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
1328         regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
1329         regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0)
1330                                 | SetBit(7);
1331         regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
1332         regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
1333                                 | SetBitField(horizEnd,4:0,4:0);
1334         regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
1335         regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
1336                                 | SetBitField(vertDisplay,8:8,1:1)
1337                                 | SetBitField(vertStart,8:8,2:2)
1338                                 | SetBitField(vertBlankStart,8:8,3:3)
1339                                 | SetBit(4)
1340                                 | SetBitField(vertTotal,9:9,5:5)
1341                                 | SetBitField(vertDisplay,9:9,6:6)
1342                                 | SetBitField(vertStart,9:9,7:7);
1343         regp->CRTC[NV_VGA_CRTCX_PRROWSCN]  = 0x00;
1344         regp->CRTC[NV_VGA_CRTCX_MAXSCLIN]  = SetBitField(vertBlankStart,9:9,5:5)
1345                                 | SetBit(6)
1346                                 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00);
1347         regp->CRTC[NV_VGA_CRTCX_VGACURCTRL] = 0x00;
1348         regp->CRTC[0xb] = 0x00;
1349         regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00;
1350         regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
1351         regp->CRTC[0xe] = 0x00;
1352         regp->CRTC[0xf] = 0x00;
1353         regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
1354         regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
1355         regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
1356         regp->CRTC[0x14] = 0x00;
1357         regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
1358         regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
1359         regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
1360         /* 0x80 enables the sequencer, we don't want that */
1361         if (depth < 8) {
1362                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xE3 & ~0x80;
1363         } else {
1364                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80;
1365         }
1366         regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
1367
1368         /*
1369          * Some extended CRTC registers (they are not saved with the rest of the vga regs).
1370          */
1371
1372         regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
1373                                 | SetBitField(vertBlankStart,10:10,3:3)
1374                                 | SetBitField(vertStart,10:10,2:2)
1375                                 | SetBitField(vertDisplay,10:10,1:1)
1376                                 | SetBitField(vertTotal,10:10,0:0);
1377
1378         regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
1379                                 | SetBitField(horizDisplay,8:8,1:1)
1380                                 | SetBitField(horizBlankStart,8:8,2:2)
1381                                 | SetBitField(horizStart,8:8,3:3);
1382
1383         regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
1384                                 | SetBitField(vertDisplay,11:11,2:2)
1385                                 | SetBitField(vertStart,11:11,4:4)
1386                                 | SetBitField(vertBlankStart,11:11,6:6);
1387
1388         if(mode->Flags & V_INTERLACE) {
1389                 horizTotal = (horizTotal >> 1) & ~1;
1390                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
1391                 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
1392         } else {
1393                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff;  /* interlace off */
1394         }
1395
1396         /*
1397         * Theory resumes here....
1398         */
1399
1400         /*
1401         * Graphics Display Controller
1402         */
1403         regp->Graphics[0] = 0x00;
1404         regp->Graphics[1] = 0x00;
1405         regp->Graphics[2] = 0x00;
1406         regp->Graphics[3] = 0x00;
1407         if (depth == 1) {
1408                 regp->Graphics[4] = BIT_PLANE;
1409                 regp->Graphics[5] = 0x00;
1410         } else {
1411                 regp->Graphics[4] = 0x00;
1412                 if (depth == 4) {
1413                         regp->Graphics[5] = 0x02;
1414                 } else {
1415                         regp->Graphics[5] = 0x40;
1416                 }
1417         }
1418         regp->Graphics[6] = 0x05;   /* only map 64k VGA memory !!!! */
1419         regp->Graphics[7] = 0x0F;
1420         regp->Graphics[8] = 0xFF;
1421
1422         /* I ditched the mono stuff */
1423         regp->Attribute[0]  = 0x00; /* standard colormap translation */
1424         regp->Attribute[1]  = 0x01;
1425         regp->Attribute[2]  = 0x02;
1426         regp->Attribute[3]  = 0x03;
1427         regp->Attribute[4]  = 0x04;
1428         regp->Attribute[5]  = 0x05;
1429         regp->Attribute[6]  = 0x06;
1430         regp->Attribute[7]  = 0x07;
1431         regp->Attribute[8]  = 0x08;
1432         regp->Attribute[9]  = 0x09;
1433         regp->Attribute[10] = 0x0A;
1434         regp->Attribute[11] = 0x0B;
1435         regp->Attribute[12] = 0x0C;
1436         regp->Attribute[13] = 0x0D;
1437         regp->Attribute[14] = 0x0E;
1438         regp->Attribute[15] = 0x0F;
1439         /* These two below are non-vga */
1440         regp->Attribute[16] = 0x01;
1441         regp->Attribute[17] = 0x00;
1442         regp->Attribute[18] = 0x0F;
1443         regp->Attribute[19] = 0x00;
1444         regp->Attribute[20] = 0x00;
1445 }
1446
1447 #define MAX_H_VALUE(i) ((0x1ff + i) << 3)
1448 #define MAX_V_VALUE(i) ((0xfff + i) << 0)
1449
1450 /**
1451  * Sets up registers for the given mode/adjusted_mode pair.
1452  *
1453  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1454  *
1455  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1456  * be easily turned on/off after this.
1457  */
1458 static void
1459 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1460 {
1461         ScrnInfoPtr pScrn = crtc->scrn;
1462         NVPtr pNv = NVPTR(pScrn);
1463         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1464         NVFBLayout *pLayout = &pNv->CurrentLayout;
1465         NVCrtcRegPtr regp, savep;
1466         unsigned int i;
1467         Bool is_fp = FALSE;
1468         Bool is_lvds = FALSE;
1469
1470         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1471         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1472
1473         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1474         NVOutputPrivatePtr nv_output = NULL;
1475         if (output) {
1476                 nv_output = output->driver_private;
1477
1478                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1479                         is_fp = TRUE;
1480
1481                 if (nv_output->type == OUTPUT_LVDS)
1482                         is_lvds = TRUE;
1483         }
1484
1485         /* Registers not directly related to the (s)vga mode */
1486
1487         /* bit2 = 0 -> fine pitched crtc granularity */
1488         /* The rest disables double buffering on CRTC access */
1489         regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
1490
1491         if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
1492                 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1493                 if (nv_crtc->head == 0) {
1494                         regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1495                 }
1496
1497                 if (is_fp) {
1498                         regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0) | (1 << 1);
1499                 }
1500         } else {
1501                 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
1502                 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
1503         }
1504
1505         /* Sometimes 0x10 is used, what is this? */
1506         regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1507         /* Some kind of tmds switch for older cards */
1508         if (pNv->Architecture < NV_ARCH_40) {
1509                 regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
1510         }
1511
1512         /*
1513         * Initialize DAC palette.
1514         * Will only be written when depth != 8.
1515         */
1516         for (i = 0; i < 256; i++) {
1517                 regp->DAC[i*3] = i;
1518                 regp->DAC[(i*3)+1] = i;
1519                 regp->DAC[(i*3)+2] = i;
1520         }
1521
1522         /*
1523         * Calculate the extended registers.
1524         */
1525
1526         if(pLayout->depth < 24) {
1527                 i = pLayout->depth;
1528         } else {
1529                 i = 32;
1530         }
1531
1532         /* What is the meaning of this register? */
1533         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1534         regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
1535
1536         /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1537         /* But what are those special conditions? */
1538         if (pNv->Architecture <= NV_ARCH_30) {
1539                 if (is_fp) {
1540                         if(nv_crtc->head == 1) {
1541                                 regp->head |= NV_CRTC_FSEL_FPP1;
1542                         } else if (pNv->twoHeads) {
1543                                 regp->head |= NV_CRTC_FSEL_FPP2;
1544                         }
1545                 }
1546         } else {
1547                 /* Most G70 cards have FPP2 set on the secondary CRTC. */
1548                 if (nv_crtc->head == 1 && pNv->NVArch > 0x44) {
1549                         regp->head |= NV_CRTC_FSEL_FPP2;
1550                 }
1551         }
1552
1553         /* Except for rare conditions I2C is enabled on the primary crtc */
1554         if (nv_crtc->head == 0) {
1555                 if (pNv->overlayAdaptor) {
1556                         regp->head |= NV_CRTC_FSEL_OVERLAY;
1557                 }
1558                 regp->head |= NV_CRTC_FSEL_I2C;
1559         }
1560
1561         /* This is not what nv does, but it is what the blob does (for nv4x at least) */
1562         /* This fixes my cursor corruption issue */
1563         regp->cursorConfig = 0x0;
1564         if(mode->Flags & V_DBLSCAN)
1565                 regp->cursorConfig |= (1 << 4);
1566         if (pNv->alphaCursor) {
1567                 /* bit28 means we go into alpha blend mode and not rely on the current ROP */
1568                 regp->cursorConfig |= 0x14011000;
1569         } else {
1570                 regp->cursorConfig |= 0x02000000;
1571         }
1572
1573         /* Unblock some timings */
1574         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1575         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1576
1577         /* What is the purpose of this register? */
1578         /* 0x14 may be disabled? */
1579         regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1580
1581         /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
1582         if (is_lvds) {
1583                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x11;
1584         } else if (is_fp) {
1585                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1586         } else {
1587                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1588         }
1589
1590         /* These values seem to vary */
1591         /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
1592         regp->CRTC[NV_VGA_CRTCX_3C] = savep->CRTC[NV_VGA_CRTCX_3C];
1593
1594         /* 0x80 seems to be used very often, if not always */
1595         regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1596
1597         /* Some cards have 0x41 instead of 0x1 (for crtc 0), it doesn't hurt to just use the old value. */
1598         regp->CRTC[NV_VGA_CRTCX_4B] = savep->CRTC[NV_VGA_CRTCX_4B];
1599
1600         if (is_fp)
1601                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x80;
1602
1603         /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1*/
1604         if (nv_crtc->head == 1) {
1605                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52;
1606         } else {
1607                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52 + 4;
1608         }
1609
1610         /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1611         regp->unk81c = nvReadCRTC0(pNv, NV_CRTC_081C);
1612
1613         regp->unk830 = mode->CrtcVDisplay - 3;
1614         regp->unk834 = mode->CrtcVDisplay - 1;
1615
1616         /* This is what the blob does */
1617         regp->unk850 = nvReadCRTC(pNv, 0, NV_CRTC_0850);
1618
1619         /* Never ever modify gpio, unless you know very well what you're doing */
1620         regp->gpio = nvReadCRTC(pNv, 0, NV_CRTC_GPIO);
1621
1622         /* Switch to non-vga mode (the so called HSYNC mode) */
1623         regp->config = 0x2;
1624
1625         /* Some misc regs */
1626         regp->CRTC[NV_VGA_CRTCX_43] = 0x1;
1627         if (pNv->Architecture == NV_ARCH_40) {
1628                 regp->CRTC[NV_VGA_CRTCX_85] = 0xFF;
1629                 regp->CRTC[NV_VGA_CRTCX_86] = 0x1;
1630         }
1631
1632         /*
1633          * Calculate the state that is common to all crtc's (stored in the state struct).
1634          */
1635         ErrorF("crtc %d %d %d\n", nv_crtc->head, mode->CrtcHDisplay, pScrn->displayWidth);
1636         nv_crtc_calc_state_ext(crtc,
1637                                 i,
1638                                 pScrn->displayWidth,
1639                                 mode->CrtcHDisplay,
1640                                 mode->CrtcVDisplay,
1641                                 adjusted_mode->Clock,
1642                                 mode->Flags);
1643
1644         /* Enable slaved mode */
1645         if (is_fp) {
1646                 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1647         }
1648 }
1649
1650 static void
1651 nv_crtc_mode_set_ramdac_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1652 {
1653         ScrnInfoPtr pScrn = crtc->scrn;
1654         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1655         NVCrtcRegPtr regp, savep;
1656         NVPtr pNv = NVPTR(pScrn);
1657         NVFBLayout *pLayout = &pNv->CurrentLayout;
1658         Bool is_fp = FALSE;
1659         Bool is_lvds = FALSE;
1660         float aspect_ratio, panel_ratio;
1661         uint32_t h_scale, v_scale;
1662
1663         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1664         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1665
1666         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1667         NVOutputPrivatePtr nv_output = NULL;
1668         if (output) {
1669                 nv_output = output->driver_private;
1670
1671                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1672                         is_fp = TRUE;
1673
1674                 if (nv_output->type == OUTPUT_LVDS)
1675                         is_lvds = TRUE;
1676         }
1677
1678         if (is_fp) {
1679                 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
1680                 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
1681                 /* This is what the blob does. */
1682                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HSyncStart - 75 - 1;
1683                 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
1684                 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
1685                 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
1686                 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
1687
1688                 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
1689                 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
1690                 /* This is what the blob does. */
1691                 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VTotal - 5 - 1;
1692                 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
1693                 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
1694                 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
1695                 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
1696
1697                 /* Quirks, maybe move them somewere else? */
1698                 if (is_lvds) {
1699                         switch(pNv->NVArch) {
1700                                 case 0x46: /* 7300GO */
1701                                         /* Only native mode needed, is there some logic to this? */
1702                                         if (mode->HDisplay == 1280 && mode->VDisplay == 800) {
1703                                                 regp->fp_horiz_regs[REG_DISP_CRTC] = 0x4c6;
1704                                         }
1705                                         break;
1706                                 default:
1707                                         break;
1708                         }
1709                 }
1710
1711                 ErrorF("Horizontal:\n");
1712                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
1713                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
1714                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
1715                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
1716                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
1717                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
1718                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
1719
1720                 ErrorF("Vertical:\n");
1721                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
1722                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
1723                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
1724                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
1725                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
1726                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
1727                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
1728         }
1729
1730         /*
1731         * bit0: positive vsync
1732         * bit4: positive hsync
1733         * bit8: enable center mode
1734         * bit9: enable native mode
1735         * bit26: a bit sometimes seen on some g70 cards
1736         * bit31: set for dual link LVDS
1737         * nv10reg contains a few more things, but i don't quite get what it all means.
1738         */
1739
1740         if (pNv->Architecture >= NV_ARCH_30) {
1741                 regp->fp_control = 0x01100000;
1742         } else {
1743                 regp->fp_control = 0x00000000;
1744         }
1745
1746         if (is_fp) {
1747                 regp->fp_control |= (1 << 28);
1748         } else {
1749                 regp->fp_control |= (2 << 28);
1750                 if (pNv->Architecture < NV_ARCH_30)
1751                         regp->fp_control |= (1 << 24);
1752         }
1753
1754         /* Some 7300GO cards get a quad view if this bit is set, even though they are duallink. */
1755         /* This was seen on 2 cards. */
1756         if (is_lvds && pNv->VBIOS.fp.dual_link && pNv->NVArch != 0x46) {
1757                 regp->fp_control |= (8 << 28);
1758         } else {
1759                 /* If the special bit exists, it exists on both ramdac's */
1760                 regp->fp_control |= nvReadRAMDAC0(pNv, NV_RAMDAC_FP_CONTROL) & (1 << 26);
1761         }
1762
1763         if (is_fp) {
1764                 if (nv_output->scaling_mode == SCALE_PANEL || is_lvds) { /* panel needs to scale */
1765                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
1766                 /* This is also true for panel scaling, so we must put the panel scale check first */
1767                 } else if (mode->Clock == adjusted_mode->Clock) { /* native mode */
1768                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
1769                 } else { /* gpu needs to scale */
1770                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1771                 }
1772         }
1773
1774         /* Deal with vsync/hsync polarity */
1775         /* LVDS screens don't set this. */
1776         if (is_fp && !is_lvds) {
1777                 if (adjusted_mode->Flags & V_PVSYNC) {
1778                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
1779                 }
1780
1781                 if (adjusted_mode->Flags & V_PHSYNC) {
1782                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
1783                 }
1784         } else if (!is_lvds) {
1785                 /* The blob doesn't always do this, but often */
1786                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_VSYNC_DISABLE;
1787                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_HSYNC_DISABLE;
1788         }
1789
1790         if (is_fp) {
1791                 ErrorF("Pre-panel scaling\n");
1792                 ErrorF("panel-size:%dx%d\n", nv_output->fpWidth, nv_output->fpHeight);
1793                 panel_ratio = (nv_output->fpWidth)/(float)(nv_output->fpHeight);
1794                 ErrorF("panel_ratio=%f\n", panel_ratio);
1795                 aspect_ratio = (mode->HDisplay)/(float)(mode->VDisplay);
1796                 ErrorF("aspect_ratio=%f\n", aspect_ratio);
1797                 /* Scale factors is the so called 20.12 format, taken from Haiku */
1798                 h_scale = ((1 << 12) * mode->HDisplay)/nv_output->fpWidth;
1799                 v_scale = ((1 << 12) * mode->VDisplay)/nv_output->fpHeight;
1800                 ErrorF("h_scale=%d\n", h_scale);
1801                 ErrorF("v_scale=%d\n", v_scale);
1802
1803                 /* This can override HTOTAL and VTOTAL */
1804                 regp->debug_2 = 0;
1805
1806                 /* We want automatic scaling */
1807                 regp->debug_1 = 0;
1808
1809                 regp->fp_hvalid_start = 0;
1810                 regp->fp_hvalid_end = (nv_output->fpWidth - 1);
1811
1812                 regp->fp_vvalid_start = 0;
1813                 regp->fp_vvalid_end = (nv_output->fpHeight - 1);
1814
1815                 /* 0 = panel scaling */
1816                 if (nv_output->scaling_mode == SCALE_PANEL) {
1817                         ErrorF("Flat panel is doing the scaling.\n");
1818                 } else {
1819                         ErrorF("GPU is doing the scaling.\n");
1820
1821                         if (nv_output->scaling_mode == SCALE_ASPECT) {
1822                                 /* GPU scaling happens automaticly at a ratio of 1.33 */
1823                                 /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
1824                                 if (h_scale != (1 << 12) && (panel_ratio > (aspect_ratio + 0.10))) {
1825                                         uint32_t diff;
1826
1827                                         ErrorF("Scaling resolution on a widescreen panel\n");
1828
1829                                         /* Scaling in both directions needs to the same */
1830                                         h_scale = v_scale;
1831
1832                                         /* Set a new horizontal scale factor and enable testmode (bit12) */
1833                                         regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
1834
1835                                         diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
1836                                         regp->fp_hvalid_start = diff/2;
1837                                         regp->fp_hvalid_end = nv_output->fpWidth - (diff/2) - 1;
1838                                 }
1839
1840                                 /* Same scaling, just for panels with aspect ratio's smaller than 1 */
1841                                 if (v_scale != (1 << 12) && (panel_ratio < (aspect_ratio - 0.10))) {
1842                                         uint32_t diff;
1843
1844                                         ErrorF("Scaling resolution on a portrait panel\n");
1845
1846                                         /* Scaling in both directions needs to the same */
1847                                         v_scale = h_scale;
1848
1849                                         /* Set a new vertical scale factor and enable testmode (bit28) */
1850                                         regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
1851
1852                                         diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
1853                                         regp->fp_vvalid_start = diff/2;
1854                                         regp->fp_vvalid_end = nv_output->fpHeight - (diff/2) - 1;
1855                                 }
1856                         }
1857                 }
1858
1859                 ErrorF("Post-panel scaling\n");
1860         }
1861
1862         if (pNv->Architecture >= NV_ARCH_10) {
1863                 /* Bios and blob don't seem to do anything (else) */
1864                 regp->nv10_cursync = (1<<25);
1865         }
1866
1867         /* These are the common blob values, minus a few fp specific bit's */
1868         /* Let's keep the TMDS pll and fpclock running in all situations */
1869         regp->debug_0 = 0x1101100;
1870
1871         if (is_fp && nv_output->scaling_mode != SCALE_NOSCALE) {
1872                 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_XSCALE_ENABLED;
1873                 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_YSCALE_ENABLED;
1874         } else if (is_fp) { /* no_scale mode, so we must center it */
1875                 uint32_t diff;
1876
1877                 diff = nv_output->fpWidth - mode->HDisplay;
1878                 regp->fp_hvalid_start = diff/2;
1879                 regp->fp_hvalid_end = (nv_output->fpWidth - diff/2 - 1);
1880
1881                 diff = nv_output->fpHeight - mode->VDisplay;
1882                 regp->fp_vvalid_start = diff/2;
1883                 regp->fp_vvalid_end = (nv_output->fpHeight - diff/2 - 1);
1884         }
1885
1886         /* Is this crtc bound or output bound? */
1887         /* Does the bios TMDS script try to change this sometimes? */
1888         if (is_fp) {
1889                 /* I am not completely certain, but seems to be set only for dfp's */
1890                 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED;
1891         }
1892
1893         if (output)
1894                 ErrorF("output %d debug_0 %08X\n", nv_output->output_resource, regp->debug_0);
1895
1896         /* Flatpanel support needs at least a NV10 */
1897         if (pNv->twoHeads) {
1898                 /* The blob does this differently. */
1899                 /* TODO: Find out what precisely and why. */
1900                 /* Let's not destroy any bits that were already present. */
1901                 if (pNv->FPDither || (is_lvds && pNv->VBIOS.fp.if_is_18bit)) {
1902                         if (pNv->NVArch == 0x11) {
1903                                 regp->dither = savep->dither | 0x00010000;
1904                         } else {
1905                                 regp->dither = savep->dither | 0x00000001;
1906                         }
1907                 } else {
1908                         regp->dither = savep->dither;
1909                 }
1910         }
1911
1912         /* Kindly borrowed from haiku driver */
1913         /* bit4 and bit5 activate indirect mode trough color palette */
1914         switch (pLayout->depth) {
1915                 case 32:
1916                 case 16:
1917                         regp->general = 0x00101130;
1918                         break;
1919                 case 24:
1920                 case 15:
1921                         regp->general = 0x00100130;
1922                         break;
1923                 case 8:
1924                 default:
1925                         regp->general = 0x00101100;
1926                         break;
1927         }
1928
1929         if (pNv->alphaCursor) {
1930                 /* PIPE_LONG mode, something to do with the size of the cursor? */
1931                 regp->general |= (1<<29);
1932         }
1933
1934         /* Some values the blob sets */
1935         /* This may apply to the real ramdac that is being used (for crosswired situations) */
1936         /* Nevertheless, it's unlikely to cause many problems, since the values are equal for both */
1937         regp->unk_a20 = 0x0;
1938         regp->unk_a24 = 0xfffff;
1939         regp->unk_a34 = 0x1;
1940 }
1941
1942 /**
1943  * Sets up registers for the given mode/adjusted_mode pair.
1944  *
1945  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1946  *
1947  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1948  * be easily turned on/off after this.
1949  */
1950 static void
1951 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
1952                  DisplayModePtr adjusted_mode,
1953                  int x, int y)
1954 {
1955         ScrnInfoPtr pScrn = crtc->scrn;
1956         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1957         NVPtr pNv = NVPTR(pScrn);
1958         NVFBLayout *pLayout = &pNv->CurrentLayout;
1959
1960         ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->head);
1961
1962         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->head);
1963         xf86PrintModeline(pScrn->scrnIndex, mode);
1964         NVCrtcSetOwner(crtc);
1965
1966         nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
1967         nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
1968         nv_crtc_mode_set_ramdac_regs(crtc, mode, adjusted_mode);
1969
1970         NVVgaProtect(crtc, TRUE);
1971         nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
1972         nv_crtc_load_state_ext(crtc, &pNv->ModeReg, FALSE);
1973         if (pLayout->depth != 8)
1974                 NVCrtcLoadPalette(crtc);
1975         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
1976         if (pNv->Architecture == NV_ARCH_40) {
1977                 nv40_crtc_load_state_pll(crtc, &pNv->ModeReg);
1978         } else {
1979                 nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
1980         }
1981
1982         NVVgaProtect(crtc, FALSE);
1983
1984         NVCrtcSetBase(crtc, x, y);
1985
1986 #if X_BYTE_ORDER == X_BIG_ENDIAN
1987         /* turn on LFB swapping */
1988         {
1989                 unsigned char tmp;
1990
1991                 tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
1992                 tmp |= (1 << 7);
1993                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
1994         }
1995 #endif
1996 }
1997
1998 /* This functions generates data that is not saved, but still is needed. */
1999 void nv_crtc_restore_generate(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2000 {
2001         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2002         int i;
2003         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
2004
2005         /* It's a good idea to also save a default palette on shutdown. */
2006         for (i = 0; i < 256; i++) {
2007                 regp->DAC[i*3] = i;
2008                 regp->DAC[(i*3)+1] = i;
2009                 regp->DAC[(i*3)+2] = i;
2010         }
2011 }
2012
2013 void nv_crtc_save(xf86CrtcPtr crtc)
2014 {
2015         ScrnInfoPtr pScrn = crtc->scrn;
2016         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2017         NVPtr pNv = NVPTR(pScrn);
2018
2019         ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->head);
2020
2021         /* We just came back from terminal, so unlock */
2022         NVCrtcLockUnlock(crtc, FALSE);
2023
2024         NVCrtcSetOwner(crtc);
2025         nv_crtc_restore_generate(crtc, &pNv->SavedReg);
2026         nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
2027         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
2028         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
2029         if (pNv->Architecture == NV_ARCH_40) {
2030                 nv40_crtc_save_state_pll(pNv, &pNv->SavedReg);
2031         } else {
2032                 nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
2033         }
2034 }
2035
2036 void nv_crtc_restore(xf86CrtcPtr crtc)
2037 {
2038         ScrnInfoPtr pScrn = crtc->scrn;
2039         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2040         NVPtr pNv = NVPTR(pScrn);
2041         RIVA_HW_STATE *state;
2042         NVCrtcRegPtr savep;
2043
2044         state = &pNv->SavedReg;
2045         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
2046
2047         ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->head);
2048
2049         NVCrtcSetOwner(crtc);
2050
2051         /* Just to be safe */
2052         NVCrtcLockUnlock(crtc, FALSE);
2053
2054         NVVgaProtect(crtc, TRUE);
2055         nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
2056         nv_crtc_load_state_ext(crtc, &pNv->SavedReg, TRUE);
2057         if (savep->general & 0x30) /* Palette mode */
2058                 NVCrtcLoadPalette(crtc);
2059         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
2060         if (pNv->Architecture == NV_ARCH_40) {
2061                 nv40_crtc_load_state_pll(crtc, &pNv->SavedReg);
2062         } else {
2063                 nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
2064         }
2065         nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->vtOWNER);
2066         NVVgaProtect(crtc, FALSE);
2067 }
2068
2069 void
2070 NVResetCrtcConfig(xf86CrtcPtr crtc, Bool set)
2071 {
2072         ScrnInfoPtr pScrn = crtc->scrn;
2073         NVPtr pNv = NVPTR(pScrn);
2074         CARD32 val = 0;
2075
2076         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2077
2078         if (set) {
2079                 NVCrtcRegPtr regp;
2080
2081                 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2082                 val = regp->head;
2083         }
2084
2085         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL, val);
2086 }
2087
2088 void nv_crtc_prepare(xf86CrtcPtr crtc)
2089 {
2090         ScrnInfoPtr pScrn = crtc->scrn;
2091         NVPtr pNv = NVPTR(pScrn);
2092         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2093
2094         ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->head);
2095
2096         /* Just in case */
2097         NVCrtcLockUnlock(crtc, 0);
2098
2099         NVResetCrtcConfig(crtc, FALSE);
2100
2101         crtc->funcs->dpms(crtc, DPMSModeOff);
2102
2103         /* Sync the engine before adjust mode */
2104         if (pNv->EXADriverPtr) {
2105                 exaMarkSync(pScrn->pScreen);
2106                 exaWaitSync(pScrn->pScreen);
2107         }
2108
2109         NVCrtcBlankScreen(crtc, FALSE); /* Blank screen */
2110
2111         /* Some more preperation. */
2112         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG, 0x1); /* Go to non-vga mode/out of enhanced mode */
2113         uint32_t reg900 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900);
2114         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 & ~0x10000);
2115         /* Set FP_CONTROL to a neutral mode, (almost) off i believe. */
2116         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, 0x21100222);
2117
2118         usleep(5000); /* Give it some time to settle */
2119 }
2120
2121 void nv_crtc_commit(xf86CrtcPtr crtc)
2122 {
2123         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2124         ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->head);
2125
2126         crtc->funcs->dpms (crtc, DPMSModeOn);
2127
2128         if (crtc->scrn->pScreen != NULL)
2129                 xf86_reload_cursors (crtc->scrn->pScreen);
2130
2131         NVResetCrtcConfig(crtc, TRUE);
2132 }
2133
2134 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
2135 {
2136         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2137         ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->head);
2138
2139         return FALSE;
2140 }
2141
2142 static void nv_crtc_unlock(xf86CrtcPtr crtc)
2143 {
2144         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2145         ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->head);
2146 }
2147
2148 static void
2149 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
2150                                         int size)
2151 {
2152         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2153         ScrnInfoPtr pScrn = crtc->scrn;
2154         NVPtr pNv = NVPTR(pScrn);
2155         int i, j;
2156
2157         NVCrtcRegPtr regp;
2158         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2159
2160         switch (pNv->CurrentLayout.depth) {
2161         case 15:
2162                 /* R5G5B5 */
2163                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
2164                 for (i = 0; i < 32; i++) {
2165                         for (j = 0; j < 8; j++) {
2166                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2167                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
2168                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2169                         }
2170                 }
2171                 break;
2172         case 16:
2173                 /* R5G6B5 */
2174                 /* First deal with the 5 bit colors */
2175                 for (i = 0; i < 32; i++) {
2176                         for (j = 0; j < 8; j++) {
2177                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2178                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2179                         }
2180                 }
2181                 /* Now deal with the 6 bit color */
2182                 for (i = 0; i < 64; i++) {
2183                         for (j = 0; j < 4; j++) {
2184                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
2185                         }
2186                 }
2187                 break;
2188         default:
2189                 /* R8G8B8 */
2190                 for (i = 0; i < 256; i++) {
2191                         regp->DAC[i * 3] = red[i] >> 8;
2192                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
2193                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
2194                 }
2195                 break;
2196         }
2197
2198         NVCrtcLoadPalette(crtc);
2199 }
2200
2201 /**
2202  * Allocates memory for a locked-in-framebuffer shadow of the given
2203  * width and height for this CRTC's rotated shadow framebuffer.
2204  */
2205
2206 static void *
2207 nv_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
2208 {
2209         ErrorF("nv_crtc_shadow_allocate is called\n");
2210         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2211         ScrnInfoPtr pScrn = crtc->scrn;
2212 #if !NOUVEAU_EXA_PIXMAPS
2213         ScreenPtr pScreen = pScrn->pScreen;
2214 #endif /* !NOUVEAU_EXA_PIXMAPS */
2215         NVPtr pNv = NVPTR(pScrn);
2216         void *offset;
2217
2218         unsigned long rotate_pitch;
2219         int size, align = 64;
2220
2221         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2222         size = rotate_pitch * height;
2223
2224         assert(nv_crtc->shadow == NULL);
2225 #if NOUVEAU_EXA_PIXMAPS
2226         if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN,
2227                         align, size, &nv_crtc->shadow)) {
2228                 ErrorF("Failed to allocate memory for shadow buffer!\n");
2229                 return NULL;
2230         }
2231
2232         if (nv_crtc->shadow && nouveau_bo_map(nv_crtc->shadow, NOUVEAU_BO_RDWR)) {
2233                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2234                                 "Failed to map shadow buffer.\n");
2235                 return NULL;
2236         }
2237
2238         offset = nv_crtc->shadow->map;
2239 #else
2240         nv_crtc->shadow = exaOffscreenAlloc(pScreen, size, align, TRUE, NULL, NULL);
2241         if (nv_crtc->shadow == NULL) {
2242                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2243                         "Couldn't allocate shadow memory for rotated CRTC\n");
2244                 return NULL;
2245         }
2246         offset = pNv->FB->map + nv_crtc->shadow->offset;
2247 #endif /* NOUVEAU_EXA_PIXMAPS */
2248
2249         return offset;
2250 }
2251
2252 /**
2253  * Creates a pixmap for this CRTC's rotated shadow framebuffer.
2254  */
2255 static PixmapPtr
2256 nv_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
2257 {
2258         ErrorF("nv_crtc_shadow_create is called\n");
2259         ScrnInfoPtr pScrn = crtc->scrn;
2260 #if NOUVEAU_EXA_PIXMAPS
2261         ScreenPtr pScreen = pScrn->pScreen;
2262         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2263 #endif /* NOUVEAU_EXA_PIXMAPS */
2264         unsigned long rotate_pitch;
2265         PixmapPtr rotate_pixmap;
2266 #if NOUVEAU_EXA_PIXMAPS
2267         struct nouveau_pixmap *nvpix;
2268 #endif /* NOUVEAU_EXA_PIXMAPS */
2269
2270         if (!data)
2271                 data = crtc->funcs->shadow_allocate (crtc, width, height);
2272
2273         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2274
2275 #if NOUVEAU_EXA_PIXMAPS
2276         /* Create a dummy pixmap, to get a private that will be accepted by the system.*/
2277         rotate_pixmap = pScreen->CreatePixmap(pScreen,
2278                                                                 0, /* width */
2279                                                                 0, /* height */
2280         #ifdef CREATE_PIXMAP_USAGE_SCRATCH /* there seems to have been no api bump */
2281                                                                 pScrn->depth,
2282                                                                 0);
2283         #else
2284                                                                 pScrn->depth);
2285         #endif /* CREATE_PIXMAP_USAGE_SCRATCH */
2286 #else
2287         rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen,
2288                                                                 width, height,
2289                                                                 pScrn->depth,
2290                                                                 pScrn->bitsPerPixel,
2291                                                                 rotate_pitch,
2292                                                                 data);
2293 #endif /* NOUVEAU_EXA_PIXMAPS */
2294
2295         if (rotate_pixmap == NULL) {
2296                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2297                         "Couldn't allocate shadow pixmap for rotated CRTC\n");
2298         }
2299
2300 #if NOUVEAU_EXA_PIXMAPS
2301         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2302         if (!nvpix) {
2303                 ErrorF("No shadow private, stage 1\n");
2304         } else {
2305                 nvpix->bo = nv_crtc->shadow;
2306                 nvpix->mapped = TRUE;
2307         }
2308
2309         /* Modify the pixmap to actually be the one we need. */
2310         pScreen->ModifyPixmapHeader(rotate_pixmap,
2311                                         width,
2312                                         height,
2313                                         pScrn->depth,
2314                                         pScrn->bitsPerPixel,
2315                                         rotate_pitch,
2316                                         data);
2317
2318         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2319         if (!nvpix || !nvpix->bo)
2320                 ErrorF("No shadow private, stage 2\n");
2321 #endif /* NOUVEAU_EXA_PIXMAPS */
2322
2323         return rotate_pixmap;
2324 }
2325
2326 static void
2327 nv_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
2328 {
2329         ErrorF("nv_crtc_shadow_destroy is called\n");
2330         ScrnInfoPtr pScrn = crtc->scrn;
2331         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2332         ScreenPtr pScreen = pScrn->pScreen;
2333
2334         if (rotate_pixmap) { /* This should also unmap the buffer object if relevant. */
2335                 pScreen->DestroyPixmap(rotate_pixmap);
2336         }
2337
2338 #if !NOUVEAU_EXA_PIXMAPS
2339         if (data && nv_crtc->shadow) {
2340                 exaOffscreenFree(pScreen, nv_crtc->shadow);
2341         }
2342 #endif /* !NOUVEAU_EXA_PIXMAPS */
2343
2344         nv_crtc->shadow = NULL;
2345 }
2346
2347 /* NV04-NV10 doesn't support alpha cursors */
2348 static const xf86CrtcFuncsRec nv_crtc_funcs = {
2349         .dpms = nv_crtc_dpms,
2350         .save = nv_crtc_save, /* XXX */
2351         .restore = nv_crtc_restore, /* XXX */
2352         .mode_fixup = nv_crtc_mode_fixup,
2353         .mode_set = nv_crtc_mode_set,
2354         .prepare = nv_crtc_prepare,
2355         .commit = nv_crtc_commit,
2356         .destroy = NULL, /* XXX */
2357         .lock = nv_crtc_lock,
2358         .unlock = nv_crtc_unlock,
2359         .set_cursor_colors = nv_crtc_set_cursor_colors,
2360         .set_cursor_position = nv_crtc_set_cursor_position,
2361         .show_cursor = nv_crtc_show_cursor,
2362         .hide_cursor = nv_crtc_hide_cursor,
2363         .load_cursor_image = nv_crtc_load_cursor_image,
2364         .gamma_set = nv_crtc_gamma_set,
2365         .shadow_create = nv_crtc_shadow_create,
2366         .shadow_allocate = nv_crtc_shadow_allocate,
2367         .shadow_destroy = nv_crtc_shadow_destroy,
2368 };
2369
2370 /* NV11 and up has support for alpha cursors. */
2371 /* Due to different maximum sizes we cannot allow it to use normal cursors */
2372 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
2373         .dpms = nv_crtc_dpms,
2374         .save = nv_crtc_save, /* XXX */
2375         .restore = nv_crtc_restore, /* XXX */
2376         .mode_fixup = nv_crtc_mode_fixup,
2377         .mode_set = nv_crtc_mode_set,
2378         .prepare = nv_crtc_prepare,
2379         .commit = nv_crtc_commit,
2380         .destroy = NULL, /* XXX */
2381         .lock = nv_crtc_lock,
2382         .unlock = nv_crtc_unlock,
2383         .set_cursor_colors = NULL, /* Alpha cursors do not need this */
2384         .set_cursor_position = nv_crtc_set_cursor_position,
2385         .show_cursor = nv_crtc_show_cursor,
2386         .hide_cursor = nv_crtc_hide_cursor,
2387         .load_cursor_argb = nv_crtc_load_cursor_argb,
2388         .gamma_set = nv_crtc_gamma_set,
2389         .shadow_create = nv_crtc_shadow_create,
2390         .shadow_allocate = nv_crtc_shadow_allocate,
2391         .shadow_destroy = nv_crtc_shadow_destroy,
2392 };
2393
2394
2395 void
2396 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
2397 {
2398         NVPtr pNv = NVPTR(pScrn);
2399         xf86CrtcPtr crtc;
2400         NVCrtcPrivatePtr nv_crtc;
2401
2402         if (pNv->NVArch >= 0x11) {
2403                 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
2404         } else {
2405                 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
2406         }
2407         if (crtc == NULL)
2408                 return;
2409
2410         nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
2411         nv_crtc->head = crtc_num;
2412
2413         crtc->driver_private = nv_crtc;
2414
2415         NVCrtcLockUnlock(crtc, FALSE);
2416 }
2417
2418 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2419 {
2420         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2421         int i;
2422         NVCrtcRegPtr regp;
2423
2424         regp = &state->crtc_reg[nv_crtc->head];
2425
2426         NVWriteMiscOut(crtc, regp->MiscOutReg);
2427
2428         for (i = 1; i < 5; i++)
2429                 NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
2430
2431         /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
2432         NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
2433
2434         for (i = 0; i < 25; i++)
2435                 NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
2436
2437         for (i = 0; i < 9; i++)
2438                 NVWriteVgaGr(crtc, i, regp->Graphics[i]);
2439
2440         NVEnablePalette(crtc);
2441         for (i = 0; i < 21; i++)
2442                 NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
2443
2444         NVDisablePalette(crtc);
2445 }
2446
2447 static void nv_crtc_fix_nv40_hw_cursor(xf86CrtcPtr crtc)
2448 {
2449         /* TODO - implement this properly */
2450         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2451         ScrnInfoPtr pScrn = crtc->scrn;
2452         NVPtr pNv = NVPTR(pScrn);
2453
2454         if (pNv->Architecture == NV_ARCH_40) {  /* HW bug */
2455                 volatile CARD32 curpos = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS);
2456                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS, curpos);
2457         }
2458 }
2459 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override)
2460 {
2461         ScrnInfoPtr pScrn = crtc->scrn;
2462         NVPtr pNv = NVPTR(pScrn);
2463         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2464         NVCrtcRegPtr regp;
2465         int i;
2466
2467         regp = &state->crtc_reg[nv_crtc->head];
2468
2469         /* If we ever get down to pre-nv10 cards, then we must reinstate some limits. */
2470         nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
2471         nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
2472         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
2473         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
2474         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2475         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2476         nvWriteMC(pNv, 0x1588, 0);
2477
2478         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
2479         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
2480         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO, regp->gpio);
2481         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0830, regp->unk830);
2482         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0834, regp->unk834);
2483         if (pNv->Architecture == NV_ARCH_40) {
2484                 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0850, regp->unk850);
2485                 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_081C, regp->unk81c);
2486         }
2487
2488         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG, regp->config);
2489         uint32_t reg900 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900);
2490         if (pNv->Architecture == NV_ARCH_40) {
2491                 if (regp->config == 0x2) { /* enhanced "horizontal only" non-vga mode */
2492                         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 | 0x10000);
2493                 } else {
2494                         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 & ~0x10000);
2495                 }
2496         }
2497
2498         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
2499         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
2500
2501         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
2502         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
2503         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3C, regp->CRTC[NV_VGA_CRTCX_3C]);
2504         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
2505         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_4B, regp->CRTC[NV_VGA_CRTCX_4B]);
2506         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
2507         if (override) {
2508                 for (i = 0; i < 0x10; i++)
2509                         NVWriteVGACR5758(pNv, nv_crtc->head, i, regp->CR58[i]);
2510         }
2511         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
2512         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
2513
2514         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
2515         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
2516         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
2517         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
2518         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
2519         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
2520         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
2521         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
2522         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
2523         if (pNv->Architecture >= NV_ARCH_30) {
2524                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
2525         }
2526
2527         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_43, regp->CRTC[NV_VGA_CRTCX_43]);
2528         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_85, regp->CRTC[NV_VGA_CRTCX_85]);
2529         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_86, regp->CRTC[NV_VGA_CRTCX_86]);
2530
2531         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
2532         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
2533         nv_crtc_fix_nv40_hw_cursor(crtc);
2534         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
2535         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
2536
2537         /* Setting 1 on this value gives you interrupts for every vblank period. */
2538         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_EN_0, 0);
2539         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
2540
2541         pNv->CurrentState = state;
2542 }
2543
2544 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2545 {
2546         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2547         int i;
2548         NVCrtcRegPtr regp;
2549
2550         regp = &state->crtc_reg[nv_crtc->head];
2551
2552         regp->MiscOutReg = NVReadMiscOut(crtc);
2553
2554         for (i = 0; i < 25; i++)
2555                 regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
2556
2557         NVEnablePalette(crtc);
2558         for (i = 0; i < 21; i++)
2559                 regp->Attribute[i] = NVReadVgaAttr(crtc, i);
2560         NVDisablePalette(crtc);
2561
2562         for (i = 0; i < 9; i++)
2563                 regp->Graphics[i] = NVReadVgaGr(crtc, i);
2564
2565         for (i = 1; i < 5; i++)
2566                 regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
2567
2568 }
2569
2570 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2571 {
2572         ScrnInfoPtr pScrn = crtc->scrn;
2573         NVPtr pNv = NVPTR(pScrn);
2574         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2575         NVCrtcRegPtr regp;
2576         int i;
2577
2578         regp = &state->crtc_reg[nv_crtc->head];
2579
2580         /* If we ever get down to pre-nv10 cards, then we must reinstate some limits. */
2581         regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
2582         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
2583         regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
2584         regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
2585         regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
2586         regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
2587         regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
2588
2589         regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
2590         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
2591         if (pNv->Architecture >= NV_ARCH_30) {
2592                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
2593         }
2594         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
2595         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
2596         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
2597         regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
2598
2599         regp->gpio = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO);
2600         regp->unk830 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0830);
2601         regp->unk834 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0834);
2602         if (pNv->Architecture == NV_ARCH_40) {
2603                 regp->unk850 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0850);
2604                 regp->unk81c = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_081C);
2605         }
2606
2607         regp->config = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG);
2608
2609         regp->head = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL);
2610         regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
2611         regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
2612
2613         regp->cursorConfig = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG);
2614
2615         regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
2616         regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
2617         regp->CRTC[NV_VGA_CRTCX_3C] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3C);
2618         regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
2619         regp->CRTC[NV_VGA_CRTCX_4B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_4B);
2620         regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
2621         for (i = 0; i < 0x10; i++)
2622                 regp->CR58[i] = NVReadVGACR5758(pNv, nv_crtc->head, i);
2623
2624         regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
2625         regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
2626         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
2627         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
2628
2629         regp->CRTC[NV_VGA_CRTCX_43] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_43);
2630         regp->CRTC[NV_VGA_CRTCX_85] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_85);
2631         regp->CRTC[NV_VGA_CRTCX_86] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_86);
2632 }
2633
2634 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2635 {
2636         ScrnInfoPtr pScrn = crtc->scrn;
2637         NVPtr pNv = NVPTR(pScrn);
2638         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2639         NVCrtcRegPtr regp;
2640         int i;
2641
2642         regp = &state->crtc_reg[nv_crtc->head];
2643
2644         regp->general = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL);
2645
2646         regp->fp_control        = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL);
2647         regp->debug_0   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0);
2648         regp->debug_1   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1);
2649         regp->debug_2   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2);
2650
2651         regp->unk_a20 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20);
2652         regp->unk_a24 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24);
2653         regp->unk_a34 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34);
2654
2655         if (pNv->NVArch == 0x11) {
2656                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11);
2657         } else if (pNv->twoHeads) {
2658                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER);
2659         }
2660         regp->nv10_cursync = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC);
2661
2662         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2663
2664         for (i = 0; i < 7; i++) {
2665                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2666                 regp->fp_horiz_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2667         }
2668
2669         for (i = 0; i < 7; i++) {
2670                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2671                 regp->fp_vert_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2672         }
2673
2674         regp->fp_hvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START);
2675         regp->fp_hvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END);
2676         regp->fp_vvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START);
2677         regp->fp_vvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END);
2678 }
2679
2680 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2681 {
2682         ScrnInfoPtr pScrn = crtc->scrn;
2683         NVPtr pNv = NVPTR(pScrn);
2684         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2685         NVCrtcRegPtr regp;
2686         int i;
2687
2688         regp = &state->crtc_reg[nv_crtc->head];
2689
2690         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL, regp->general);
2691
2692         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control);
2693         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0, regp->debug_0);
2694         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
2695         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
2696
2697         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20, regp->unk_a20);
2698         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24, regp->unk_a24);
2699         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34, regp->unk_a34);
2700
2701         if (pNv->NVArch == 0x11) {
2702                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11, regp->dither);
2703         } else if (pNv->twoHeads) {
2704                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER, regp->dither);
2705         }
2706         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
2707
2708         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2709
2710         for (i = 0; i < 7; i++) {
2711                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2712                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_horiz_regs[i]);
2713         }
2714
2715         for (i = 0; i < 7; i++) {
2716                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2717                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_vert_regs[i]);
2718         }
2719
2720         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START, regp->fp_hvalid_start);
2721         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END, regp->fp_hvalid_end);
2722         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START, regp->fp_vvalid_start);
2723         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END, regp->fp_vvalid_end);
2724 }
2725
2726 void
2727 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y)
2728 {
2729         ScrnInfoPtr pScrn = crtc->scrn;
2730         NVPtr pNv = NVPTR(pScrn);
2731         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2732         NVFBLayout *pLayout = &pNv->CurrentLayout;
2733         CARD32 start = 0;
2734
2735         ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
2736
2737         start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
2738         if (crtc->rotatedData != NULL) { /* we do not exist on the real framebuffer */
2739 #if NOUVEAU_EXA_PIXMAPS
2740                 start = nv_crtc->shadow->offset;
2741 #else
2742                 start = pNv->FB->offset + nv_crtc->shadow->offset; /* We do exist relative to the framebuffer */
2743 #endif
2744         } else {
2745                 start += pNv->FB->offset;
2746         }
2747
2748         /* 30 bits addresses in 32 bits according to haiku */
2749         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_START, start & 0xfffffffc);
2750
2751         /* set NV4/NV10 byte adress: (bit0 - 1) */
2752         NVWriteVgaAttr(crtc, 0x13, (start & 0x3) << 1);
2753
2754         crtc->x = x;
2755         crtc->y = y;
2756 }
2757
2758 static void NVCrtcWriteDacMask(xf86CrtcPtr crtc, CARD8 value)
2759 {
2760   ScrnInfoPtr pScrn = crtc->scrn;
2761   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2762   NVPtr pNv = NVPTR(pScrn);
2763   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2764
2765   NV_WR08(pDACReg, VGA_DAC_MASK, value);
2766 }
2767
2768 static CARD8 NVCrtcReadDacMask(xf86CrtcPtr crtc)
2769 {
2770   ScrnInfoPtr pScrn = crtc->scrn;
2771   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2772   NVPtr pNv = NVPTR(pScrn);
2773   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2774
2775   return NV_RD08(pDACReg, VGA_DAC_MASK);
2776 }
2777
2778 static void NVCrtcWriteDacReadAddr(xf86CrtcPtr crtc, CARD8 value)
2779 {
2780   ScrnInfoPtr pScrn = crtc->scrn;
2781   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2782   NVPtr pNv = NVPTR(pScrn);
2783   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2784
2785   NV_WR08(pDACReg, VGA_DAC_READ_ADDR, value);
2786 }
2787
2788 static void NVCrtcWriteDacWriteAddr(xf86CrtcPtr crtc, CARD8 value)
2789 {
2790   ScrnInfoPtr pScrn = crtc->scrn;
2791   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2792   NVPtr pNv = NVPTR(pScrn);
2793   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2794
2795   NV_WR08(pDACReg, VGA_DAC_WRITE_ADDR, value);
2796 }
2797
2798 static void NVCrtcWriteDacData(xf86CrtcPtr crtc, CARD8 value)
2799 {
2800   ScrnInfoPtr pScrn = crtc->scrn;
2801   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2802   NVPtr pNv = NVPTR(pScrn);
2803   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2804
2805   NV_WR08(pDACReg, VGA_DAC_DATA, value);
2806 }
2807
2808 static CARD8 NVCrtcReadDacData(xf86CrtcPtr crtc, CARD8 value)
2809 {
2810   ScrnInfoPtr pScrn = crtc->scrn;
2811   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2812   NVPtr pNv = NVPTR(pScrn);
2813   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2814
2815   return NV_RD08(pDACReg, VGA_DAC_DATA);
2816 }
2817
2818 void NVCrtcLoadPalette(xf86CrtcPtr crtc)
2819 {
2820         int i;
2821         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2822         NVCrtcRegPtr regp;
2823         ScrnInfoPtr pScrn = crtc->scrn;
2824         NVPtr pNv = NVPTR(pScrn);
2825
2826         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2827
2828         NVCrtcSetOwner(crtc);
2829         NVCrtcWriteDacMask(crtc, 0xff);
2830         NVCrtcWriteDacWriteAddr(crtc, 0x00);
2831
2832         for (i = 0; i<768; i++) {
2833                 NVCrtcWriteDacData(crtc, regp->DAC[i]);
2834         }
2835         NVDisablePalette(crtc);
2836 }
2837
2838 /* on = unblank */
2839 void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
2840 {
2841         unsigned char scrn;
2842
2843         NVCrtcSetOwner(crtc);
2844
2845         scrn = NVReadVgaSeq(crtc, 0x01);
2846         if (on) {
2847                 scrn &= ~0x20;
2848         } else {
2849                 scrn |= 0x20;
2850         }
2851
2852         NVVgaSeqReset(crtc, TRUE);
2853         NVWriteVgaSeq(crtc, 0x01, scrn);
2854         NVVgaSeqReset(crtc, FALSE);
2855 }
2856
2857 /*************************************************************************** \
2858 |*                                                                           *|
2859 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
2860 |*                                                                           *|
2861 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
2862 |*     international laws.  Users and possessors of this source code are     *|
2863 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
2864 |*     use this code in individual and commercial software.                  *|
2865 |*                                                                           *|
2866 |*     Any use of this source code must include,  in the user documenta-     *|
2867 |*     tion and  internal comments to the code,  notices to the end user     *|
2868 |*     as follows:                                                           *|
2869 |*                                                                           *|
2870 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
2871 |*                                                                           *|
2872 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
2873 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
2874 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
2875 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
2876 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
2877 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
2878 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
2879 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
2880 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
2881 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
2882 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
2883 |*                                                                           *|
2884 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
2885 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
2886 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
2887 |*     computer  software  documentation,"  as such  terms  are  used in     *|
2888 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
2889 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
2890 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
2891 |*     all U.S. Government End Users  acquire the source code  with only     *|
2892 |*     those rights set forth herein.                                        *|
2893 |*                                                                           *|
2894  \***************************************************************************/