2 * Copyright 2006 Dave Airlie
3 * Copyright 2007 Maarten Maathuis
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
26 * decleration is at the bottom of this file as it is rather ugly
41 #include "mipointer.h"
42 #include "windowstr.h"
44 #include <X11/extensions/render.h>
47 #include "nv_include.h"
51 #define CRTC_INDEX 0x3d4
52 #define CRTC_DATA 0x3d5
53 #define CRTC_IN_STAT_1 0x3da
55 #define WHITE_VALUE 0x3F
56 #define BLACK_VALUE 0x00
57 #define OVERSCAN_VALUE 0x01
59 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
60 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override);
61 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
62 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
63 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
64 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
66 static uint8_t NVReadPVIO(xf86CrtcPtr crtc, uint32_t address)
68 ScrnInfoPtr pScrn = crtc->scrn;
69 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
70 NVPtr pNv = NVPTR(pScrn);
72 /* Only NV4x have two pvio ranges */
73 if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
74 return NV_RD08(pNv->PVIO1, address);
76 return NV_RD08(pNv->PVIO0, address);
80 static void NVWritePVIO(xf86CrtcPtr crtc, uint32_t address, uint8_t value)
82 ScrnInfoPtr pScrn = crtc->scrn;
83 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
84 NVPtr pNv = NVPTR(pScrn);
86 /* Only NV4x have two pvio ranges */
87 if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
88 NV_WR08(pNv->PVIO1, address, value);
90 NV_WR08(pNv->PVIO0, address, value);
94 static void NVWriteMiscOut(xf86CrtcPtr crtc, uint8_t value)
96 NVWritePVIO(crtc, VGA_MISC_OUT_W, value);
99 static uint8_t NVReadMiscOut(xf86CrtcPtr crtc)
101 return NVReadPVIO(crtc, VGA_MISC_OUT_R);
104 void NVWriteVGA(NVPtr pNv, int head, uint8_t index, uint8_t value)
106 volatile uint8_t *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
108 #ifdef NOUVEAU_MODESET_TRACE
109 ErrorF("NVWriteVGA: idx %d data 0x%x head %d\n", index, value, head);
112 NV_WR08(pCRTCReg, CRTC_INDEX, index);
113 NV_WR08(pCRTCReg, CRTC_DATA, value);
116 uint8_t NVReadVGA(NVPtr pNv, int head, uint8_t index)
118 volatile uint8_t *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
120 NV_WR08(pCRTCReg, CRTC_INDEX, index);
121 return NV_RD08(pCRTCReg, CRTC_DATA);
124 /* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
125 * I suspect they in fact do nothing, but are merely a way to carry useful
126 * per-head variables around
130 * 0x00 index to the appropriate dcb entry (or 7f for inactive)
131 * 0x02 dcb entry's "or" value (or 00 for inactive)
132 * 0x03 bit0 set for dual link (LVDS, possibly elsewhere too)
133 * 0x08 or 0x09 pxclk in MHz
134 * 0x0f laptop panel info - low nibble for PEXTDEV_BOOT strap
135 * high nibble for xlat strap value
138 void NVWriteVGACR5758(NVPtr pNv, int head, uint8_t index, uint8_t value)
140 NVWriteVGA(pNv, head, 0x57, index);
141 NVWriteVGA(pNv, head, 0x58, value);
144 uint8_t NVReadVGACR5758(NVPtr pNv, int head, uint8_t index)
146 NVWriteVGA(pNv, head, 0x57, index);
147 return NVReadVGA(pNv, head, 0x58);
150 void NVWriteVgaCrtc(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
152 ScrnInfoPtr pScrn = crtc->scrn;
153 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
154 NVPtr pNv = NVPTR(pScrn);
156 NVWriteVGA(pNv, nv_crtc->head, index, value);
159 uint8_t NVReadVgaCrtc(xf86CrtcPtr crtc, uint8_t index)
161 ScrnInfoPtr pScrn = crtc->scrn;
162 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
163 NVPtr pNv = NVPTR(pScrn);
165 return NVReadVGA(pNv, nv_crtc->head, index);
168 static void NVWriteVgaSeq(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
170 NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
171 NVWritePVIO(crtc, VGA_SEQ_DATA, value);
174 static uint8_t NVReadVgaSeq(xf86CrtcPtr crtc, uint8_t index)
176 NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
177 return NVReadPVIO(crtc, VGA_SEQ_DATA);
180 static void NVWriteVgaGr(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
182 NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
183 NVWritePVIO(crtc, VGA_GRAPH_DATA, value);
186 static uint8_t NVReadVgaGr(xf86CrtcPtr crtc, uint8_t index)
188 NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
189 return NVReadPVIO(crtc, VGA_GRAPH_DATA);
193 static void NVWriteVgaAttr(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
195 ScrnInfoPtr pScrn = crtc->scrn;
196 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
197 NVPtr pNv = NVPTR(pScrn);
198 volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
200 NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
201 if (nv_crtc->paletteEnabled)
205 NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
206 NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
209 static uint8_t NVReadVgaAttr(xf86CrtcPtr crtc, uint8_t index)
211 ScrnInfoPtr pScrn = crtc->scrn;
212 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
213 NVPtr pNv = NVPTR(pScrn);
214 volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
216 NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
217 if (nv_crtc->paletteEnabled)
221 NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
222 return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
225 void NVCrtcSetOwner(xf86CrtcPtr crtc)
227 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
228 ScrnInfoPtr pScrn = crtc->scrn;
229 NVPtr pNv = NVPTR(pScrn);
230 /* Non standard beheaviour required by NV11 */
232 uint8_t owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
233 ErrorF("pre-Owner: 0x%X\n", owner);
235 uint32_t pbus84 = nvReadMC(pNv, 0x1084);
236 ErrorF("pbus84: 0x%X\n", pbus84);
238 ErrorF("pbus84: 0x%X\n", pbus84);
239 nvWriteMC(pNv, 0x1084, pbus84);
241 /* The blob never writes owner to pcio1, so should we */
242 if (pNv->NVArch == 0x11) {
243 NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, 0xff);
245 NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, nv_crtc->head * 0x3);
246 owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
247 ErrorF("post-Owner: 0x%X\n", owner);
249 ErrorF("pNv pointer is NULL\n");
254 NVEnablePalette(xf86CrtcPtr crtc)
256 ScrnInfoPtr pScrn = crtc->scrn;
257 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
258 NVPtr pNv = NVPTR(pScrn);
259 volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
261 NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
262 NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
263 nv_crtc->paletteEnabled = TRUE;
267 NVDisablePalette(xf86CrtcPtr crtc)
269 ScrnInfoPtr pScrn = crtc->scrn;
270 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
271 NVPtr pNv = NVPTR(pScrn);
272 volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
274 NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
275 NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
276 nv_crtc->paletteEnabled = FALSE;
279 static void NVWriteVgaReg(xf86CrtcPtr crtc, uint32_t reg, uint8_t value)
281 ScrnInfoPtr pScrn = crtc->scrn;
282 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
283 NVPtr pNv = NVPTR(pScrn);
284 volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
286 NV_WR08(pCRTCReg, reg, value);
289 /* perform a sequencer reset */
290 static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
293 NVWriteVgaSeq(crtc, 0x00, 0x1);
295 NVWriteVgaSeq(crtc, 0x00, 0x3);
298 static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
303 tmp = NVReadVgaSeq(crtc, 0x1);
304 NVVgaSeqReset(crtc, TRUE);
305 NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
307 NVEnablePalette(crtc);
310 * Reenable sequencer, then turn on screen.
312 tmp = NVReadVgaSeq(crtc, 0x1);
313 NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20); /* reenable display */
314 NVVgaSeqReset(crtc, FALSE);
316 NVDisablePalette(crtc);
320 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool Lock)
324 NVCrtcSetOwner(crtc);
326 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57);
327 cr11 = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE);
328 if (Lock) cr11 |= 0x80;
330 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE, cr11);
334 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
336 ScrnInfoPtr pScrn = crtc->scrn;
337 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
339 for (i = 0; i < xf86_config->num_output; i++) {
340 xf86OutputPtr output = xf86_config->output[i];
342 if (output->crtc == crtc) {
351 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
353 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
356 for (i = 0; i < xf86_config->num_crtc; i++) {
357 xf86CrtcPtr crtc = xf86_config->crtc[i];
358 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
359 if (nv_crtc->head == index)
367 * Calculate the Video Clock parameters for the PLL.
369 /* Code taken from NVClock, with permission of the author (being a GPL->MIT code transfer). */
372 CalculateVClkNV4x_SingleVCO(NVPtr pNv, struct pll_lims *pll_lim, uint32_t clockIn, uint32_t *n1_best, uint32_t *m1_best, uint32_t *p_best)
374 uint32_t clock, M, N, P;
375 uint32_t delta, bestDelta, minM, maxM, minN, maxN, maxP;
376 uint32_t minVCOInputFreq, minVCOFreq, maxVCOFreq;
378 uint32_t refClk = pNv->CrystalFreqKHz;
381 /* bios clocks are in MHz, we use KHz */
382 minVCOInputFreq = pll_lim->vco1.min_inputfreq*1000;
383 minVCOFreq = pll_lim->vco1.minfreq*1000;
384 maxVCOFreq = pll_lim->vco1.maxfreq*1000;
385 minM = pll_lim->vco1.min_m;
386 maxM = pll_lim->vco1.max_m;
387 minN = pll_lim->vco1.min_n;
388 maxN = pll_lim->vco1.max_n;
392 /* The optimal frequency for the PLL to work at is somewhere in the center of its range.
393 / Choose a post divider in such a way to achieve this.
394 / The G8x nv driver does something similar but they they derive a minP and maxP. That
395 / doesn't seem required as you get so many matching clocks that you don't enter a second
396 / iteration for P. (The minP / maxP values in the nv driver only differ at most 1, so it is for
397 / some rare corner cases.
399 for (P=0, VCOFreq=maxVCOFreq/2; clockIn<=VCOFreq && P <= maxP; P++)
404 /* Calculate the m and n values. There are a lot of values which give the same speed;
405 / We choose the speed for which the difference with the request speed is as small as possible.
407 for (M=minM; M<=maxM; M++)
409 /* The VCO has a minimum input frequency */
410 if ((refClk/M) < minVCOInputFreq)
413 for (N=minN; N<=maxN; N++)
415 /* Calculate the frequency generated by VCO1 */
416 clock = (int)(refClk * N / (float)M);
418 /* Verify if the clock lies within the output limits of VCO1 */
419 if (clock < minVCOFreq)
421 else if (clock > maxVCOFreq) /* It is no use to continue as the clock will only become higher */
425 delta = abs((int)(clockIn - clock));
426 /* When the difference is 0 or less than .5% accept the speed */
427 if (((delta == 0) || ((float)delta/(float)clockIn <= 0.005)))
435 /* When the new difference is smaller than the old one, use this one */
436 if (delta < bestDelta)
448 CalculateVClkNV4x_DoubleVCO(NVPtr pNv, struct pll_lims *pll_lim, uint32_t clockIn, uint32_t *n1_best, uint32_t *n2_best, uint32_t *m1_best, uint32_t *m2_best, uint32_t *p_best)
450 uint32_t clock1, clock2, M, M2, N, N2, P;
451 uint32_t delta, bestDelta, minM, minM2, maxM, maxM2, minN, minN2, maxN, maxN2, maxP;
452 uint32_t minVCOInputFreq, minVCO2InputFreq, maxVCO2InputFreq, minVCOFreq, minVCO2Freq, maxVCOFreq, maxVCO2Freq;
453 uint32_t VCO2Freq, maxClock;
454 uint32_t refClk = pNv->CrystalFreqKHz;
457 /* bios clocks are in MHz, we use KHz */
458 minVCOInputFreq = pll_lim->vco1.min_inputfreq*1000;
459 minVCOFreq = pll_lim->vco1.minfreq*1000;
460 maxVCOFreq = pll_lim->vco1.maxfreq*1000;
461 minM = pll_lim->vco1.min_m;
462 maxM = pll_lim->vco1.max_m;
463 minN = pll_lim->vco1.min_n;
464 maxN = pll_lim->vco1.max_n;
466 minVCO2InputFreq = pll_lim->vco2.min_inputfreq*1000;
467 maxVCO2InputFreq = pll_lim->vco2.max_inputfreq*1000;
468 minVCO2Freq = pll_lim->vco2.minfreq*1000;
469 maxVCO2Freq = pll_lim->vco2.maxfreq*1000;
470 minM2 = pll_lim->vco2.min_m;
471 maxM2 = pll_lim->vco2.max_m;
472 minN2 = pll_lim->vco2.min_n;
473 maxN2 = pll_lim->vco2.max_n;
477 maxClock = maxVCO2Freq;
478 /* If the requested clock is behind the bios limits, try it anyway */
479 if (clockIn > maxVCO2Freq)
480 maxClock = clockIn + clockIn/200; /* Add a .5% margin */
482 /* The optimal frequency for the PLL to work at is somewhere in the center of its range.
483 / Choose a post divider in such a way to achieve this.
484 / The G8x nv driver does something similar but they they derive a minP and maxP. That
485 / doesn't seem required as you get so many matching clocks that you don't enter a second
486 / iteration for P. (The minP / maxP values in the nv driver only differ at most 1, so it is for
487 / some rare corner cases.
489 for (P=0, VCO2Freq=maxClock/2; clockIn<=VCO2Freq && P <= maxP; P++)
494 /* The PLLs on Geforce6/7 hardware can operate in a single stage made with only 1 VCO
495 / and a cascade mode of two VCOs. This second mode is in general used for relatively high
496 / frequencies. The loop below calculates the divider and multiplier ratios for the cascade
497 / mode. The code takes into account limits defined in the video bios.
499 for (M=minM; M<=maxM; M++)
501 /* The VCO has a minimum input frequency */
502 if ((refClk/M) < minVCOInputFreq)
505 for (N=minN; N<=maxN; N++)
507 /* Calculate the frequency generated by VCO1 */
508 clock1 = (int)(refClk * N / (float)M);
509 /* Verify if the clock lies within the output limits of VCO1 */
510 if ( (clock1 < minVCOFreq) )
512 else if (clock1 > maxVCOFreq) /* For future N, the clock will only increase so stop; xorg nv continues but that is useless */
515 for (M2=minM2; M2<=maxM2; M2++)
517 /* The clock fed to the second VCO needs to lie within a certain input range */
518 if (clock1 / M2 < minVCO2InputFreq)
520 else if (clock1 / M2 > maxVCO2InputFreq)
523 N2 = (int)((float)((clockIn << P) * M * M2) / (float)(refClk * N)+.5);
524 if( (N2 < minN2) || (N2 > maxN2) )
527 /* The clock before being fed to the post-divider needs to lie within a certain range.
528 / Further there are some limits on N2/M2.
530 clock2 = (int)((float)(N*N2)/(M*M2) * refClk);
531 if( (clock2 < minVCO2Freq) || (clock2 > maxClock))// || ((N2 / M2) < 4) || ((N2 / M2) > 10) )
534 /* The post-divider delays the 'high' clock to create a low clock if requested.
535 / This post-divider exists because the VCOs can only generate frequencies within
536 / a limited frequency range. This range has been tuned to lie around half of its max
537 / input frequency. It tries to calculate all clocks (including lower ones) around this
538 / 'center' frequency.
541 delta = abs((int)(clockIn - clock2));
543 /* When the difference is 0 or less than .5% accept the speed */
544 if (((delta == 0) || ((float)delta/(float)clockIn <= 0.005)))
554 /* When the new difference is smaller than the old one, use this one */
555 if (delta < bestDelta)
569 /* BIG NOTE: modifying vpll1 and vpll2 does not work, what bit is the switch to allow it? */
571 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
572 /* They are only valid for NV4x, appearantly reordered for NV5x */
573 /* gpu pll: 0x4000 + 0x4004
574 * unknown pll: 0x4008 + 0x400c
575 * vpll1: 0x4010 + 0x4014
576 * vpll2: 0x4018 + 0x401c
577 * unknown pll: 0x4020 + 0x4024
578 * unknown pll: 0x4038 + 0x403c
579 * Some of the unknown's are probably memory pll's.
580 * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
581 * 1 and 2 refer to the registers of each pair. There is only one post divider.
582 * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
583 * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
584 * bit8: A switch that turns of the second divider and multiplier off.
585 * bit12: Also a switch, i haven't seen it yet.
586 * bit16-19: p-divider
587 * but 28-31: Something related to the mode that is used (see bit8).
588 * 2) bit0-7: m-divider (a)
589 * bit8-15: n-multiplier (a)
590 * bit16-23: m-divider (b)
591 * bit24-31: n-multiplier (b)
594 /* Modifying the gpu pll for example requires:
595 * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
596 * This is not needed for the vpll's which have their own bits.
602 uint32_t requested_clock,
603 uint32_t *given_clock,
611 NVPtr pNv = NVPTR(pScrn);
612 struct pll_lims pll_lim;
613 /* We have 2 mulitpliers, 2 dividers and one post divider */
614 /* Note that p is only 3 bits */
615 uint32_t m1_best = 0, m2_best = 0, n1_best = 0, n2_best = 0, p_best = 0;
616 uint32_t special_bits = 0;
619 if (!get_pll_limits(pScrn, VPLL1, &pll_lim))
622 if (!get_pll_limits(pScrn, VPLL2, &pll_lim))
625 if (requested_clock < pll_lim.vco1.maxfreq*1000 && pNv->NVArch > 0x40) { /* single VCO */
627 /* Turn the second set of divider and multiplier off */
628 /* Bogus data, the same nvidia uses */
631 CalculateVClkNV4x_SingleVCO(pNv, &pll_lim, requested_clock, &n1_best, &m1_best, &p_best);
632 } else { /* dual VCO */
634 CalculateVClkNV4x_DoubleVCO(pNv, &pll_lim, requested_clock, &n1_best, &n2_best, &m1_best, &m2_best, &p_best);
637 /* Are this all (relevant) G70 cards? */
638 if (pNv->NVArch == 0x4B || pNv->NVArch == 0x46 || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
639 /* This is a big guess, but should be reasonable until we can narrow it down. */
647 /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
648 /* Let's keep the special bits, if the bios already set them */
649 *pll_a = (special_bits << 30) | (p_best << 16) | (n1_best << 8) | (m1_best << 0);
650 *pll_b = (1 << 31) | (n2_best << 8) | (m2_best << 0);
654 *reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
656 *reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
660 *reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
662 *reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
667 ErrorF("vpll: n1 %d m1 %d p %d db1_ratio %d\n", n1_best, m1_best, p_best, *db1_ratio);
669 ErrorF("vpll: n1 %d n2 %d m1 %d m2 %d p %d db1_ratio %d\n", n1_best, n2_best, m1_best, m2_best, p_best, *db1_ratio);
673 static void nv40_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
675 state->vpll1_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
676 state->vpll1_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
677 state->vpll2_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
678 state->vpll2_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
679 state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
680 state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
681 state->reg580 = nvReadRAMDAC0(pNv, NV_RAMDAC_580);
682 state->reg594 = nvReadRAMDAC0(pNv, NV_RAMDAC_594);
685 static void nv40_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
687 ScrnInfoPtr pScrn = crtc->scrn;
688 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
689 NVPtr pNv = NVPTR(pScrn);
690 uint32_t fp_debug_0[2];
692 fp_debug_0[0] = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
693 fp_debug_0[1] = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
695 uint32_t reg_c040_old = nvReadMC(pNv, 0xc040);
697 /* The TMDS_PLL switch is on the actual ramdac */
698 if (state->crosswired) {
701 ErrorF("Crosswired pll state load\n");
707 if (state->vpll2_b && state->vpll_changed[1]) {
708 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0,
709 fp_debug_0[index[1]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
711 /* Wait for the situation to stabilise */
714 uint32_t reg_c040 = pNv->misc_info.reg_c040;
715 /* for vpll2 change bits 18 and 19 are disabled */
716 reg_c040 &= ~(0x3 << 18);
717 nvWriteMC(pNv, 0xc040, reg_c040);
719 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
720 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
722 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2_a);
723 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2_b);
725 ErrorF("writing pllsel %08X\n", state->pllsel);
726 /* Don't turn vpll1 off. */
727 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
729 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
730 ErrorF("writing reg580 %08X\n", state->reg580);
732 /* We need to wait a while */
734 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
736 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[1]]);
738 /* Wait for the situation to stabilise */
742 if (state->vpll1_b && state->vpll_changed[0]) {
743 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0,
744 fp_debug_0[index[0]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
746 /* Wait for the situation to stabilise */
749 uint32_t reg_c040 = pNv->misc_info.reg_c040;
750 /* for vpll2 change bits 16 and 17 are disabled */
751 reg_c040 &= ~(0x3 << 16);
752 nvWriteMC(pNv, 0xc040, reg_c040);
754 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
755 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
757 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll1_a);
758 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpll1_b);
760 ErrorF("writing pllsel %08X\n", state->pllsel);
761 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
763 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
764 ErrorF("writing reg580 %08X\n", state->reg580);
766 /* We need to wait a while */
768 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
770 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[0]]);
772 /* Wait for the situation to stabilise */
776 /* Let's be sure not to wake up any crtc's from dpms. */
777 /* But we do want to keep our newly set crtc awake. */
778 if (nv_crtc->head == 1) {
779 nvWriteMC(pNv, 0xc040, reg_c040_old | (pNv->misc_info.reg_c040 & (0x3 << 18)));
781 nvWriteMC(pNv, 0xc040, reg_c040_old | (pNv->misc_info.reg_c040 & (0x3 << 16)));
784 ErrorF("writing sel_clk %08X\n", state->sel_clk);
785 nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
787 ErrorF("writing reg594 %08X\n", state->reg594);
788 nvWriteRAMDAC0(pNv, NV_RAMDAC_594, state->reg594);
790 /* All clocks have been set at this point. */
791 state->vpll_changed[0] = FALSE;
792 state->vpll_changed[1] = FALSE;
795 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
797 state->vpll1_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
799 state->vpll2_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
801 if(pNv->twoStagePLL) {
802 state->vpll1_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
803 state->vpll2_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
805 state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
806 state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
810 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
812 /* This sequence is important, the NV28 is very sensitive in this area. */
813 /* Keep pllsel last and sel_clk first. */
814 ErrorF("writing sel_clk %08X\n", state->sel_clk);
815 nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
817 if (state->vpll2_a && state->vpll_changed[1]) {
819 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
820 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2_a);
822 if(pNv->twoStagePLL) {
823 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
824 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2_b);
828 if (state->vpll1_a && state->vpll_changed[0]) {
829 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
830 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll1_a);
831 if(pNv->twoStagePLL) {
832 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
833 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpll1_b);
837 ErrorF("writing pllsel %08X\n", state->pllsel);
838 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
840 /* All clocks have been set at this point. */
841 state->vpll_changed[0] = FALSE;
842 state->vpll_changed[1] = FALSE;
845 #define IS_NV44P (pNv->NVArch >= 0x44 ? 1 : 0)
846 #define SEL_CLK_OFFSET (nv_get_sel_clk_offset(pNv->NVArch, nv_output->bus))
848 #define WIPE_OTHER_CLOCKS(_sel_clk, _head, _bus) (nv_wipe_other_clocks(_sel_clk, pNv->NVArch, _head, _bus))
851 * Calculate extended mode parameters (SVGA) and save in a
852 * mode state structure.
853 * State is not specific to a single crtc, but shared.
855 void nv_crtc_calc_state_ext(
858 int DisplayWidth, /* Does this change after setting the mode? */
865 ScrnInfoPtr pScrn = crtc->scrn;
866 uint32_t pixelDepth, VClk = 0;
867 uint32_t CursorStart;
868 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
869 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
871 NVPtr pNv = NVPTR(pScrn);
872 RIVA_HW_STATE *state;
873 int num_crtc_enabled, i;
874 uint32_t old_clock_a = 0, old_clock_b = 0;
876 state = &pNv->ModeReg;
878 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
880 xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
881 NVOutputPrivatePtr nv_output = NULL;
883 nv_output = output->driver_private;
886 /* Store old clock. */
887 if (nv_crtc->head == 1) {
888 old_clock_a = state->vpll2_a;
889 old_clock_b = state->vpll2_b;
891 old_clock_a = state->vpll1_a;
892 old_clock_b = state->vpll1_b;
896 * Extended RIVA registers.
898 pixelDepth = (bpp + 1)/8;
899 if (pNv->Architecture == NV_ARCH_40) {
900 /* Does register 0x580 already have a value? */
901 if (!state->reg580) {
902 state->reg580 = pNv->misc_info.ramdac_0_reg_580;
904 if (nv_crtc->head == 1) {
905 CalculateVClkNV4x(pScrn, dotClock, &VClk, &state->vpll2_a, &state->vpll2_b, &state->reg580, &state->db1_ratio[1], FALSE);
907 CalculateVClkNV4x(pScrn, dotClock, &VClk, &state->vpll1_a, &state->vpll1_b, &state->reg580, &state->db1_ratio[0], TRUE);
909 } else if (pNv->twoStagePLL) {
910 struct pll_lims pll_lim;
912 get_pll_limits(pScrn, 0, &pll_lim);
913 VClk = getMNP_double(pScrn, &pll_lim, dotClock, &NM1, &NM2, &log2P);
914 state->pll = log2P << 16 | NM1;
915 state->pllB = 1 << 31 | NM2;
918 VClk = getMNP_single(pScrn, dotClock, &NM, &log2P);
919 state->pll = log2P << 16 | NM;
922 if (pNv->Architecture < NV_ARCH_40) {
923 if (nv_crtc->head == 1) {
924 state->vpll2_a = state->pll;
925 state->vpll2_b = state->pllB;
927 state->vpll1_a = state->pll;
928 state->vpll1_b = state->pllB;
932 if (nv_crtc->head == 1) {
933 state->vpll_changed[1] = ((state->vpll2_a == old_clock_a) && (state->vpll2_b == old_clock_b)) ? FALSE : TRUE;
935 state->vpll_changed[0] = ((state->vpll1_a == old_clock_a) && (state->vpll1_b == old_clock_b)) ? FALSE : TRUE;
938 switch (pNv->Architecture) {
940 nv4UpdateArbitrationSettings(VClk,
942 &(state->arbitration0),
943 &(state->arbitration1),
945 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
946 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
947 if (flags & V_DBLSCAN)
948 regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
949 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
950 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
951 state->config = 0x00001114;
952 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
958 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
959 ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
960 state->arbitration0 = 128;
961 state->arbitration1 = 0x0480;
962 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
963 ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
964 nForceUpdateArbitrationSettings(VClk,
966 &(state->arbitration0),
967 &(state->arbitration1),
969 } else if (pNv->Architecture < NV_ARCH_30) {
970 nv10UpdateArbitrationSettings(VClk,
972 &(state->arbitration0),
973 &(state->arbitration1),
976 nv30UpdateArbitrationSettings(pNv,
977 &(state->arbitration0),
978 &(state->arbitration1));
981 if (nv_crtc->head == 1) {
982 CursorStart = pNv->Cursor2->offset;
984 CursorStart = pNv->Cursor->offset;
987 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
988 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
989 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
991 if (flags & V_DBLSCAN)
992 regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
994 state->config = nvReadFB(pNv, NV_PFB_CFG0);
995 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
999 /* okay do we have 2 CRTCs running ? */
1000 num_crtc_enabled = 0;
1001 for (i = 0; i < xf86_config->num_crtc; i++) {
1002 if (xf86_config->crtc[i]->enabled) {
1007 ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
1009 /* The main stuff seems to be valid for NV3x also. */
1010 if (pNv->Architecture >= NV_ARCH_30) {
1011 /* This register is only used on the primary ramdac */
1012 /* This seems to be needed to select the proper clocks, otherwise bad things happen */
1014 if (!state->sel_clk)
1015 state->sel_clk = pNv->misc_info.sel_clk & ~(0xf << 16);
1017 if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
1018 /* Only wipe when are a relevant (digital) output. */
1019 state->sel_clk &= ~(0xf << 16);
1020 Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1021 /* Even with two dvi, this should not conflict. */
1022 if (crossed_clocks) {
1023 state->sel_clk |= (0x1 << 16);
1025 state->sel_clk |= (0x4 << 16);
1029 /* Some cards, specifically dual dvi/lvds cards set another bitrange.
1030 * I suspect inverse beheaviour to the normal bitrange, but i am not a 100% certain about this.
1031 * This is all based on default settings found in mmio-traces.
1032 * The blob never changes these, as it doesn't run unusual output configurations.
1033 * It seems to prefer situations that avoid changing these bits (for a good reason?).
1034 * I still don't know the purpose of value 2, it's similar to 4, but what exactly does it do?
1039 * bit 0 NVClk spread spectrum on/off
1040 * bit 2 MemClk spread spectrum on/off
1041 * bit 4 PixClk1 spread spectrum on/off
1042 * bit 6 PixClk2 spread spectrum on/off
1045 * what causes setting of bits not obvious but:
1046 * bits 4&5 relate to headA
1047 * bits 6&7 relate to headB
1049 /* Only let digital outputs mess with this, otherwise strange output routings may mess it up. */
1050 if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
1051 if (pNv->Architecture >= NV_ARCH_30) {
1052 for (i = 0; i < 4; i++) {
1053 uint32_t var = (state->sel_clk & (0xf << 4*i)) >> 4*i;
1054 if (var == 0x1 || var == 0x4) {
1055 state->sel_clk &= ~(0xf << 4*i);
1056 Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1057 if (crossed_clocks) {
1058 state->sel_clk |= (0x4 << 4*i);
1060 state->sel_clk |= (0x1 << 4*i);
1062 break; /* This should only occur once. */
1068 /* Are we crosswired? */
1069 if (output && nv_crtc->head != nv_output->preferred_output) {
1070 state->crosswired = TRUE;
1072 state->crosswired = FALSE;
1075 if (nv_crtc->head == 1) {
1076 if (state->db1_ratio[1])
1077 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1078 } else if (nv_crtc->head == 0) {
1079 if (state->db1_ratio[0])
1080 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1083 /* Do NV1x/NV2x cards need anything in sel_clk? */
1084 state->sel_clk = 0x0;
1085 state->crosswired = FALSE;
1088 /* The NV40 seems to have more similarities to NV3x than other cards. */
1089 if (pNv->NVArch < 0x41) {
1090 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL;
1091 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL;
1094 if (nv_crtc->head == 1) {
1095 if (!state->db1_ratio[1]) {
1096 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1098 state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1100 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
1102 if (!state->db1_ratio[0]) {
1103 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1105 state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1107 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
1110 /* The blob uses this always, so let's do the same */
1111 if (pNv->Architecture == NV_ARCH_40) {
1112 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
1115 /* The primary output resource doesn't seem to care */
1116 if (output && pNv->Architecture == NV_ARCH_40 && nv_output->output_resource == 1) { /* This is the "output" */
1117 /* non-zero values are for analog, don't know about tv-out and the likes */
1118 if (output && nv_output->type != OUTPUT_ANALOG) {
1119 state->reg594 = 0x0;
1120 } else if (output) {
1121 /* Are we a flexible output? */
1122 if (ffs(pNv->dcb_table.entry[nv_output->dcb_entry].or) & OUTPUT_0) {
1123 state->reg594 = 0x1;
1124 pNv->restricted_mode = FALSE;
1126 state->reg594 = 0x0;
1127 pNv->restricted_mode = TRUE;
1130 /* More values exist, but they seem related to the 3rd dac (tv-out?) somehow */
1131 /* bit 16-19 are bits that are set on some G70 cards */
1132 /* Those bits are also set to the 3rd OUTPUT register */
1133 if (nv_crtc->head == 1) {
1134 state->reg594 |= 0x100;
1139 regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
1140 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
1141 if (pNv->Architecture >= NV_ARCH_30) {
1142 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
1145 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
1146 regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
1150 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
1152 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1154 ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->head, mode);
1156 if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */
1159 nv_crtc->last_dpms = mode;
1161 ScrnInfoPtr pScrn = crtc->scrn;
1162 NVPtr pNv = NVPTR(pScrn);
1163 unsigned char seq1 = 0, crtc17 = 0;
1164 unsigned char crtc1A;
1166 NVCrtcSetOwner(crtc);
1168 crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
1170 case DPMSModeStandby:
1171 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
1176 case DPMSModeSuspend:
1177 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
1183 /* Screen: Off; HSync: Off, VSync: Off */
1190 /* Screen: On; HSync: On, VSync: On */
1196 NVVgaSeqReset(crtc, TRUE);
1197 /* Each head has it's own sequencer, so we can turn it off when we want */
1198 seq1 |= (NVReadVgaSeq(crtc, 0x01) & ~0x20);
1199 NVWriteVgaSeq(crtc, 0x1, seq1);
1200 crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
1202 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
1203 NVVgaSeqReset(crtc, FALSE);
1205 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
1207 /* We can completely disable a vpll if the crtc is off. */
1208 if (pNv->Architecture == NV_ARCH_40) {
1209 uint32_t reg_c040_old = nvReadMC(pNv, 0xc040);
1210 if (mode == DPMSModeOn) {
1211 nvWriteMC(pNv, 0xc040, reg_c040_old | (pNv->misc_info.reg_c040 & (0x3 << (16 + 2*nv_crtc->head))));
1213 nvWriteMC(pNv, 0xc040, reg_c040_old & ~(pNv->misc_info.reg_c040 & (0x3 << (16 + 2*nv_crtc->head))));
1217 /* I hope this is the right place */
1218 if (crtc->enabled && mode == DPMSModeOn) {
1219 pNv->crtc_active[nv_crtc->head] = TRUE;
1221 pNv->crtc_active[nv_crtc->head] = FALSE;
1226 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
1227 DisplayModePtr adjusted_mode)
1229 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1230 ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->head);
1236 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1238 ScrnInfoPtr pScrn = crtc->scrn;
1239 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1241 NVPtr pNv = NVPTR(pScrn);
1242 NVFBLayout *pLayout = &pNv->CurrentLayout;
1243 int depth = pScrn->depth;
1245 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1247 /* Calculate our timings */
1248 int horizDisplay = (mode->CrtcHDisplay >> 3) - 1;
1249 int horizStart = (mode->CrtcHSyncStart >> 3) - 1;
1250 int horizEnd = (mode->CrtcHSyncEnd >> 3) - 1;
1251 int horizTotal = (mode->CrtcHTotal >> 3) - 5;
1252 int horizBlankStart = (mode->CrtcHDisplay >> 3) - 1;
1253 int horizBlankEnd = (mode->CrtcHTotal >> 3) - 1;
1254 int vertDisplay = mode->CrtcVDisplay - 1;
1255 int vertStart = mode->CrtcVSyncStart - 1;
1256 int vertEnd = mode->CrtcVSyncEnd - 1;
1257 int vertTotal = mode->CrtcVTotal - 2;
1258 int vertBlankStart = mode->CrtcVDisplay - 1;
1259 int vertBlankEnd = mode->CrtcVTotal - 1;
1263 xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1264 NVOutputPrivatePtr nv_output = NULL;
1266 nv_output = output->driver_private;
1268 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1272 ErrorF("Mode clock: %d\n", mode->Clock);
1273 ErrorF("Adjusted mode clock: %d\n", adjusted_mode->Clock);
1275 /* Reverted to what nv did, because that works for all resolutions on flatpanels */
1277 vertStart = vertTotal - 3;
1278 vertEnd = vertTotal - 2;
1279 vertBlankStart = vertStart;
1280 horizStart = horizTotal - 5;
1281 horizEnd = horizTotal - 2;
1282 horizBlankEnd = horizTotal + 4;
1283 if (pNv->overlayAdaptor) {
1284 /* This reportedly works around Xv some overlay bandwidth problems*/
1289 if(mode->Flags & V_INTERLACE)
1292 ErrorF("horizDisplay: 0x%X \n", horizDisplay);
1293 ErrorF("horizStart: 0x%X \n", horizStart);
1294 ErrorF("horizEnd: 0x%X \n", horizEnd);
1295 ErrorF("horizTotal: 0x%X \n", horizTotal);
1296 ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
1297 ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
1298 ErrorF("vertDisplay: 0x%X \n", vertDisplay);
1299 ErrorF("vertStart: 0x%X \n", vertStart);
1300 ErrorF("vertEnd: 0x%X \n", vertEnd);
1301 ErrorF("vertTotal: 0x%X \n", vertTotal);
1302 ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
1303 ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
1306 * compute correct Hsync & Vsync polarity
1308 if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
1309 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
1311 regp->MiscOutReg = 0x23;
1312 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
1313 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
1315 int VDisplay = mode->VDisplay;
1316 if (mode->Flags & V_DBLSCAN)
1318 if (mode->VScan > 1)
1319 VDisplay *= mode->VScan;
1320 if (VDisplay < 400) {
1321 regp->MiscOutReg = 0xA3; /* +hsync -vsync */
1322 } else if (VDisplay < 480) {
1323 regp->MiscOutReg = 0x63; /* -hsync +vsync */
1324 } else if (VDisplay < 768) {
1325 regp->MiscOutReg = 0xE3; /* -hsync -vsync */
1327 regp->MiscOutReg = 0x23; /* +hsync +vsync */
1331 regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
1337 regp->Sequencer[0] = 0x02;
1339 regp->Sequencer[0] = 0x00;
1341 /* 0x20 disables the sequencer */
1342 if (mode->Flags & V_CLKDIV2) {
1343 regp->Sequencer[1] = 0x29;
1345 regp->Sequencer[1] = 0x21;
1348 regp->Sequencer[2] = 1 << BIT_PLANE;
1350 regp->Sequencer[2] = 0x0F;
1351 regp->Sequencer[3] = 0x00; /* Font select */
1354 regp->Sequencer[4] = 0x06; /* Misc */
1356 regp->Sequencer[4] = 0x0E; /* Misc */
1362 regp->CRTC[NV_VGA_CRTCX_HTOTAL] = Set8Bits(horizTotal);
1363 regp->CRTC[NV_VGA_CRTCX_HDISPE] = Set8Bits(horizDisplay);
1364 regp->CRTC[NV_VGA_CRTCX_HBLANKS] = Set8Bits(horizBlankStart);
1365 regp->CRTC[NV_VGA_CRTCX_HBLANKE] = SetBitField(horizBlankEnd,4:0,4:0)
1367 regp->CRTC[NV_VGA_CRTCX_HSYNCS] = Set8Bits(horizStart);
1368 regp->CRTC[NV_VGA_CRTCX_HSYNCE] = SetBitField(horizBlankEnd,5:5,7:7)
1369 | SetBitField(horizEnd,4:0,4:0);
1370 regp->CRTC[NV_VGA_CRTCX_VTOTAL] = SetBitField(vertTotal,7:0,7:0);
1371 regp->CRTC[NV_VGA_CRTCX_OVERFLOW] = SetBitField(vertTotal,8:8,0:0)
1372 | SetBitField(vertDisplay,8:8,1:1)
1373 | SetBitField(vertStart,8:8,2:2)
1374 | SetBitField(vertBlankStart,8:8,3:3)
1376 | SetBitField(vertTotal,9:9,5:5)
1377 | SetBitField(vertDisplay,9:9,6:6)
1378 | SetBitField(vertStart,9:9,7:7);
1379 regp->CRTC[NV_VGA_CRTCX_PRROWSCN] = 0x00;
1380 regp->CRTC[NV_VGA_CRTCX_MAXSCLIN] = SetBitField(vertBlankStart,9:9,5:5)
1382 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00);
1383 regp->CRTC[NV_VGA_CRTCX_VGACURCTRL] = 0x00;
1384 regp->CRTC[0xb] = 0x00;
1385 regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00;
1386 regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
1387 regp->CRTC[0xe] = 0x00;
1388 regp->CRTC[0xf] = 0x00;
1389 regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
1390 regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
1391 regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
1392 regp->CRTC[0x14] = 0x00;
1393 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
1394 regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
1395 regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
1396 /* 0x80 enables the sequencer, we don't want that */
1398 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xE3 & ~0x80;
1400 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80;
1402 regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
1405 * Some extended CRTC registers (they are not saved with the rest of the vga regs).
1408 regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
1409 | SetBitField(vertBlankStart,10:10,3:3)
1410 | SetBitField(vertStart,10:10,2:2)
1411 | SetBitField(vertDisplay,10:10,1:1)
1412 | SetBitField(vertTotal,10:10,0:0);
1414 regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
1415 | SetBitField(horizDisplay,8:8,1:1)
1416 | SetBitField(horizBlankStart,8:8,2:2)
1417 | SetBitField(horizStart,8:8,3:3);
1419 regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
1420 | SetBitField(vertDisplay,11:11,2:2)
1421 | SetBitField(vertStart,11:11,4:4)
1422 | SetBitField(vertBlankStart,11:11,6:6);
1424 if(mode->Flags & V_INTERLACE) {
1425 horizTotal = (horizTotal >> 1) & ~1;
1426 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
1427 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
1429 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff; /* interlace off */
1433 * Theory resumes here....
1437 * Graphics Display Controller
1439 regp->Graphics[0] = 0x00;
1440 regp->Graphics[1] = 0x00;
1441 regp->Graphics[2] = 0x00;
1442 regp->Graphics[3] = 0x00;
1444 regp->Graphics[4] = BIT_PLANE;
1445 regp->Graphics[5] = 0x00;
1447 regp->Graphics[4] = 0x00;
1449 regp->Graphics[5] = 0x02;
1451 regp->Graphics[5] = 0x40;
1454 regp->Graphics[6] = 0x05; /* only map 64k VGA memory !!!! */
1455 regp->Graphics[7] = 0x0F;
1456 regp->Graphics[8] = 0xFF;
1458 /* I ditched the mono stuff */
1459 regp->Attribute[0] = 0x00; /* standard colormap translation */
1460 regp->Attribute[1] = 0x01;
1461 regp->Attribute[2] = 0x02;
1462 regp->Attribute[3] = 0x03;
1463 regp->Attribute[4] = 0x04;
1464 regp->Attribute[5] = 0x05;
1465 regp->Attribute[6] = 0x06;
1466 regp->Attribute[7] = 0x07;
1467 regp->Attribute[8] = 0x08;
1468 regp->Attribute[9] = 0x09;
1469 regp->Attribute[10] = 0x0A;
1470 regp->Attribute[11] = 0x0B;
1471 regp->Attribute[12] = 0x0C;
1472 regp->Attribute[13] = 0x0D;
1473 regp->Attribute[14] = 0x0E;
1474 regp->Attribute[15] = 0x0F;
1475 /* These two below are non-vga */
1476 regp->Attribute[16] = 0x01;
1477 regp->Attribute[17] = 0x00;
1478 regp->Attribute[18] = 0x0F;
1479 regp->Attribute[19] = 0x00;
1480 regp->Attribute[20] = 0x00;
1483 #define MAX_H_VALUE(i) ((0x1ff + i) << 3)
1484 #define MAX_V_VALUE(i) ((0xfff + i) << 0)
1487 * Sets up registers for the given mode/adjusted_mode pair.
1489 * The clocks, CRTCs and outputs attached to this CRTC must be off.
1491 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1492 * be easily turned on/off after this.
1495 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1497 ScrnInfoPtr pScrn = crtc->scrn;
1498 NVPtr pNv = NVPTR(pScrn);
1499 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1500 NVFBLayout *pLayout = &pNv->CurrentLayout;
1501 NVCrtcRegPtr regp, savep;
1504 Bool is_lvds = FALSE;
1506 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1507 savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1509 xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1510 NVOutputPrivatePtr nv_output = NULL;
1512 nv_output = output->driver_private;
1514 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1517 if (nv_output->type == OUTPUT_LVDS)
1521 /* Registers not directly related to the (s)vga mode */
1523 /* bit2 = 0 -> fine pitched crtc granularity */
1524 /* The rest disables double buffering on CRTC access */
1525 regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
1527 if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
1528 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1529 if (nv_crtc->head == 0) {
1530 regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1534 regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0) | (1 << 1);
1537 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
1538 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
1541 /* Sometimes 0x10 is used, what is this? */
1542 regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1543 /* Some kind of tmds switch for older cards */
1544 if (pNv->Architecture < NV_ARCH_40) {
1545 regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
1549 * Initialize DAC palette.
1550 * Will only be written when depth != 8.
1552 for (i = 0; i < 256; i++) {
1554 regp->DAC[(i*3)+1] = i;
1555 regp->DAC[(i*3)+2] = i;
1559 * Calculate the extended registers.
1562 if(pLayout->depth < 24) {
1568 /* What is the meaning of this register? */
1569 /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1570 regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
1572 /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1573 /* But what are those special conditions? */
1574 if (pNv->Architecture <= NV_ARCH_30) {
1576 if(nv_crtc->head == 1) {
1577 regp->head |= NV_CRTC_FSEL_FPP1;
1578 } else if (pNv->twoHeads) {
1579 regp->head |= NV_CRTC_FSEL_FPP2;
1583 /* Most G70 cards have FPP2 set on the secondary CRTC. */
1584 if (nv_crtc->head == 1 && pNv->NVArch > 0x44) {
1585 regp->head |= NV_CRTC_FSEL_FPP2;
1589 /* Except for rare conditions I2C is enabled on the primary crtc */
1590 if (nv_crtc->head == 0) {
1591 if (pNv->overlayAdaptor) {
1592 regp->head |= NV_CRTC_FSEL_OVERLAY;
1594 regp->head |= NV_CRTC_FSEL_I2C;
1597 /* This is not what nv does, but it is what the blob does (for nv4x at least) */
1598 /* This fixes my cursor corruption issue */
1599 regp->cursorConfig = 0x0;
1600 if(mode->Flags & V_DBLSCAN)
1601 regp->cursorConfig |= (1 << 4);
1602 if (pNv->alphaCursor) {
1603 /* bit28 means we go into alpha blend mode and not rely on the current ROP */
1604 regp->cursorConfig |= 0x14011000;
1606 regp->cursorConfig |= 0x02000000;
1609 /* Unblock some timings */
1610 regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1611 regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1613 /* What is the purpose of this register? */
1614 /* 0x14 may be disabled? */
1615 regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1617 /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
1619 regp->CRTC[NV_VGA_CRTCX_3B] = 0x11;
1621 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1623 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1626 /* These values seem to vary */
1627 /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
1628 regp->CRTC[NV_VGA_CRTCX_3C] = savep->CRTC[NV_VGA_CRTCX_3C];
1630 /* 0x80 seems to be used very often, if not always */
1631 regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1633 /* Some cards have 0x41 instead of 0x1 (for crtc 0), it doesn't hurt to just use the old value. */
1634 regp->CRTC[NV_VGA_CRTCX_4B] = savep->CRTC[NV_VGA_CRTCX_4B];
1637 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x80;
1639 /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1*/
1640 if (nv_crtc->head == 1) {
1641 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52;
1643 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52 + 4;
1646 /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1647 regp->unk81c = nvReadCRTC0(pNv, NV_CRTC_081C);
1649 regp->unk830 = mode->CrtcVDisplay - 3;
1650 regp->unk834 = mode->CrtcVDisplay - 1;
1652 /* This is what the blob does */
1653 regp->unk850 = nvReadCRTC(pNv, 0, NV_CRTC_0850);
1655 /* Never ever modify gpio, unless you know very well what you're doing */
1656 regp->gpio = nvReadCRTC(pNv, 0, NV_CRTC_GPIO);
1658 /* Switch to non-vga mode (the so called HSYNC mode) */
1661 /* Some misc regs */
1662 regp->CRTC[NV_VGA_CRTCX_43] = 0x1;
1663 if (pNv->Architecture == NV_ARCH_40) {
1664 regp->CRTC[NV_VGA_CRTCX_85] = 0xFF;
1665 regp->CRTC[NV_VGA_CRTCX_86] = 0x1;
1669 * Calculate the state that is common to all crtc's (stored in the state struct).
1671 ErrorF("crtc %d %d %d\n", nv_crtc->head, mode->CrtcHDisplay, pScrn->displayWidth);
1672 nv_crtc_calc_state_ext(crtc,
1674 pScrn->displayWidth,
1677 adjusted_mode->Clock,
1680 /* Enable slaved mode */
1682 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1687 nv_crtc_mode_set_ramdac_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1689 ScrnInfoPtr pScrn = crtc->scrn;
1690 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1691 NVCrtcRegPtr regp, savep;
1692 NVPtr pNv = NVPTR(pScrn);
1693 NVFBLayout *pLayout = &pNv->CurrentLayout;
1695 Bool is_lvds = FALSE;
1696 float aspect_ratio, panel_ratio;
1697 uint32_t h_scale, v_scale;
1699 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1700 savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1702 xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1703 NVOutputPrivatePtr nv_output = NULL;
1705 nv_output = output->driver_private;
1707 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1710 if (nv_output->type == OUTPUT_LVDS)
1715 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
1716 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
1717 /* This is what the blob does. */
1718 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HSyncStart - 75 - 1;
1719 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
1720 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
1721 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
1722 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
1724 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
1725 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
1726 /* This is what the blob does. */
1727 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VTotal - 5 - 1;
1728 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
1729 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
1730 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
1731 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
1733 /* Quirks, maybe move them somewere else? */
1735 switch(pNv->NVArch) {
1736 case 0x46: /* 7300GO */
1737 /* Only native mode needed, is there some logic to this? */
1738 if (mode->HDisplay == 1280 && mode->VDisplay == 800) {
1739 regp->fp_horiz_regs[REG_DISP_CRTC] = 0x4c6;
1747 ErrorF("Horizontal:\n");
1748 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
1749 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
1750 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
1751 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
1752 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
1753 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
1754 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
1756 ErrorF("Vertical:\n");
1757 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
1758 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
1759 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
1760 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
1761 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
1762 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
1763 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
1767 * bit0: positive vsync
1768 * bit4: positive hsync
1769 * bit8: enable center mode
1770 * bit9: enable native mode
1771 * bit26: a bit sometimes seen on some g70 cards
1772 * bit31: set for dual link LVDS
1773 * nv10reg contains a few more things, but i don't quite get what it all means.
1776 if (pNv->Architecture >= NV_ARCH_30) {
1777 regp->fp_control = 0x01100000;
1779 regp->fp_control = 0x00000000;
1783 regp->fp_control |= (1 << 28);
1785 regp->fp_control |= (2 << 28);
1786 if (pNv->Architecture < NV_ARCH_30)
1787 regp->fp_control |= (1 << 24);
1790 /* Some 7300GO cards get a quad view if this bit is set, even though they are duallink. */
1791 /* This was seen on 2 cards. */
1792 if (is_lvds && pNv->VBIOS.fp.dual_link && pNv->NVArch != 0x46) {
1793 regp->fp_control |= (8 << 28);
1796 /* If the special bit exists, it exists on both ramdac's */
1797 regp->fp_control |= nvReadRAMDAC0(pNv, NV_RAMDAC_FP_CONTROL) & (1 << 26);
1800 if (nv_output->scaling_mode == SCALE_PANEL) { /* panel needs to scale */
1801 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
1802 /* This is also true for panel scaling, so we must put the panel scale check first */
1803 } else if (mode->Clock == adjusted_mode->Clock) { /* native mode */
1804 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
1805 } else { /* gpu needs to scale */
1806 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1810 /* Deal with vsync/hsync polarity */
1811 /* LVDS screens don't set this. */
1812 if (is_fp && !is_lvds) {
1813 if (adjusted_mode->Flags & V_PVSYNC) {
1814 regp->fp_control |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
1817 if (adjusted_mode->Flags & V_PHSYNC) {
1818 regp->fp_control |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
1820 } else if (!is_lvds) {
1821 /* The blob doesn't always do this, but often */
1822 regp->fp_control |= NV_RAMDAC_FP_CONTROL_VSYNC_DISABLE;
1823 regp->fp_control |= NV_RAMDAC_FP_CONTROL_HSYNC_DISABLE;
1827 ErrorF("Pre-panel scaling\n");
1828 ErrorF("panel-size:%dx%d\n", nv_output->fpWidth, nv_output->fpHeight);
1829 panel_ratio = (nv_output->fpWidth)/(float)(nv_output->fpHeight);
1830 ErrorF("panel_ratio=%f\n", panel_ratio);
1831 aspect_ratio = (mode->HDisplay)/(float)(mode->VDisplay);
1832 ErrorF("aspect_ratio=%f\n", aspect_ratio);
1833 /* Scale factors is the so called 20.12 format, taken from Haiku */
1834 h_scale = ((1 << 12) * mode->HDisplay)/nv_output->fpWidth;
1835 v_scale = ((1 << 12) * mode->VDisplay)/nv_output->fpHeight;
1836 ErrorF("h_scale=%d\n", h_scale);
1837 ErrorF("v_scale=%d\n", v_scale);
1839 /* This can override HTOTAL and VTOTAL */
1842 /* We want automatic scaling */
1845 regp->fp_hvalid_start = 0;
1846 regp->fp_hvalid_end = (nv_output->fpWidth - 1);
1848 regp->fp_vvalid_start = 0;
1849 regp->fp_vvalid_end = (nv_output->fpHeight - 1);
1851 /* 0 = panel scaling */
1852 if (nv_output->scaling_mode == SCALE_PANEL) {
1853 ErrorF("Flat panel is doing the scaling.\n");
1855 ErrorF("GPU is doing the scaling.\n");
1857 if (nv_output->scaling_mode == SCALE_ASPECT) {
1858 /* GPU scaling happens automaticly at a ratio of 1.33 */
1859 /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
1860 if (h_scale != (1 << 12) && (panel_ratio > (aspect_ratio + 0.10))) {
1863 ErrorF("Scaling resolution on a widescreen panel\n");
1865 /* Scaling in both directions needs to the same */
1868 /* Set a new horizontal scale factor and enable testmode (bit12) */
1869 regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
1871 diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
1872 regp->fp_hvalid_start = diff/2;
1873 regp->fp_hvalid_end = nv_output->fpWidth - (diff/2) - 1;
1876 /* Same scaling, just for panels with aspect ratio's smaller than 1 */
1877 if (v_scale != (1 << 12) && (panel_ratio < (aspect_ratio - 0.10))) {
1880 ErrorF("Scaling resolution on a portrait panel\n");
1882 /* Scaling in both directions needs to the same */
1885 /* Set a new vertical scale factor and enable testmode (bit28) */
1886 regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
1888 diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
1889 regp->fp_vvalid_start = diff/2;
1890 regp->fp_vvalid_end = nv_output->fpHeight - (diff/2) - 1;
1895 ErrorF("Post-panel scaling\n");
1898 if (pNv->Architecture >= NV_ARCH_10) {
1899 /* Bios and blob don't seem to do anything (else) */
1900 regp->nv10_cursync = (1<<25);
1903 /* These are the common blob values, minus a few fp specific bit's */
1904 /* Let's keep the TMDS pll and fpclock running in all situations */
1905 regp->debug_0 = 0x1101100;
1907 if (is_fp && nv_output->scaling_mode != SCALE_NOSCALE) {
1908 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_XSCALE_ENABLED;
1909 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_YSCALE_ENABLED;
1910 } else if (is_fp) { /* no_scale mode, so we must center it */
1913 diff = nv_output->fpWidth - mode->HDisplay;
1914 regp->fp_hvalid_start = diff/2;
1915 regp->fp_hvalid_end = (nv_output->fpWidth - diff/2 - 1);
1917 diff = nv_output->fpHeight - mode->VDisplay;
1918 regp->fp_vvalid_start = diff/2;
1919 regp->fp_vvalid_end = (nv_output->fpHeight - diff/2 - 1);
1922 /* Is this crtc bound or output bound? */
1923 /* Does the bios TMDS script try to change this sometimes? */
1925 /* I am not completely certain, but seems to be set only for dfp's */
1926 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED;
1930 ErrorF("output %d debug_0 %08X\n", nv_output->output_resource, regp->debug_0);
1932 /* Flatpanel support needs at least a NV10 */
1933 if (pNv->twoHeads) {
1934 /* The blob does this differently. */
1935 /* TODO: Find out what precisely and why. */
1936 /* Let's not destroy any bits that were already present. */
1937 if (pNv->FPDither || (is_lvds && pNv->VBIOS.fp.if_is_18bit)) {
1938 if (pNv->NVArch == 0x11) {
1939 regp->dither = savep->dither | 0x00010000;
1941 regp->dither = savep->dither | 0x00000001;
1944 regp->dither = savep->dither;
1948 /* Kindly borrowed from haiku driver */
1949 /* bit4 and bit5 activate indirect mode trough color palette */
1950 switch (pLayout->depth) {
1953 regp->general = 0x00101130;
1957 regp->general = 0x00100130;
1961 regp->general = 0x00101100;
1965 if (pNv->alphaCursor) {
1966 /* PIPE_LONG mode, something to do with the size of the cursor? */
1967 regp->general |= (1<<29);
1970 /* Some values the blob sets */
1971 /* This may apply to the real ramdac that is being used (for crosswired situations) */
1972 /* Nevertheless, it's unlikely to cause many problems, since the values are equal for both */
1973 regp->unk_a20 = 0x0;
1974 regp->unk_a24 = 0xfffff;
1975 regp->unk_a34 = 0x1;
1979 * Sets up registers for the given mode/adjusted_mode pair.
1981 * The clocks, CRTCs and outputs attached to this CRTC must be off.
1983 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1984 * be easily turned on/off after this.
1987 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
1988 DisplayModePtr adjusted_mode,
1991 ScrnInfoPtr pScrn = crtc->scrn;
1992 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1993 NVPtr pNv = NVPTR(pScrn);
1994 NVFBLayout *pLayout = &pNv->CurrentLayout;
1996 ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->head);
1998 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->head);
1999 xf86PrintModeline(pScrn->scrnIndex, mode);
2000 NVCrtcSetOwner(crtc);
2002 nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
2003 nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
2004 nv_crtc_mode_set_ramdac_regs(crtc, mode, adjusted_mode);
2006 NVVgaProtect(crtc, TRUE);
2007 nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
2008 nv_crtc_load_state_ext(crtc, &pNv->ModeReg, FALSE);
2009 if (pLayout->depth != 8)
2010 NVCrtcLoadPalette(crtc);
2011 nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
2012 if (pNv->Architecture == NV_ARCH_40) {
2013 nv40_crtc_load_state_pll(crtc, &pNv->ModeReg);
2015 nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
2018 NVVgaProtect(crtc, FALSE);
2020 NVCrtcSetBase(crtc, x, y);
2022 #if X_BYTE_ORDER == X_BIG_ENDIAN
2023 /* turn on LFB swapping */
2027 tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
2029 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
2034 /* This functions generates data that is not saved, but still is needed. */
2035 void nv_crtc_restore_generate(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2037 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2038 ScrnInfoPtr pScrn = crtc->scrn;
2039 NVPtr pNv = NVPTR(pScrn);
2041 NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
2043 /* It's a good idea to also save a default palette on shutdown. */
2044 for (i = 0; i < 256; i++) {
2046 regp->DAC[(i*3)+1] = i;
2047 regp->DAC[(i*3)+2] = i;
2050 /* Noticed that reading this variable is problematic on one card. */
2051 if (pNv->NVArch == 0x11)
2052 state->sel_clk = 0x0;
2055 void nv_crtc_save(xf86CrtcPtr crtc)
2057 ScrnInfoPtr pScrn = crtc->scrn;
2058 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2059 NVPtr pNv = NVPTR(pScrn);
2061 ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->head);
2063 /* We just came back from terminal, so unlock */
2064 NVCrtcLockUnlock(crtc, FALSE);
2066 NVCrtcSetOwner(crtc);
2067 nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
2068 nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
2069 nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
2070 if (pNv->Architecture == NV_ARCH_40) {
2071 nv40_crtc_save_state_pll(pNv, &pNv->SavedReg);
2073 nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
2077 void nv_crtc_restore(xf86CrtcPtr crtc)
2079 ScrnInfoPtr pScrn = crtc->scrn;
2080 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2081 NVPtr pNv = NVPTR(pScrn);
2082 RIVA_HW_STATE *state;
2085 state = &pNv->SavedReg;
2086 savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
2088 ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->head);
2090 NVCrtcSetOwner(crtc);
2092 /* Just to be safe */
2093 NVCrtcLockUnlock(crtc, FALSE);
2095 NVVgaProtect(crtc, TRUE);
2096 nv_crtc_restore_generate(crtc, &pNv->SavedReg);
2097 nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
2098 nv_crtc_load_state_ext(crtc, &pNv->SavedReg, TRUE);
2099 if (savep->general & 0x30) /* Palette mode */
2100 NVCrtcLoadPalette(crtc);
2101 nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
2103 /* Force restoring pll's. */
2104 state->vpll_changed[0] = TRUE;
2105 state->vpll_changed[1] = TRUE;
2107 if (pNv->Architecture == NV_ARCH_40) {
2108 nv40_crtc_load_state_pll(crtc, &pNv->SavedReg);
2110 nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
2112 nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->vtOWNER);
2113 NVVgaProtect(crtc, FALSE);
2117 NVResetCrtcConfig(xf86CrtcPtr crtc, Bool set)
2119 ScrnInfoPtr pScrn = crtc->scrn;
2120 NVPtr pNv = NVPTR(pScrn);
2123 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2128 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2132 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL, val);
2135 void nv_crtc_prepare(xf86CrtcPtr crtc)
2137 ScrnInfoPtr pScrn = crtc->scrn;
2138 NVPtr pNv = NVPTR(pScrn);
2139 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2141 ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->head);
2144 NVCrtcLockUnlock(crtc, 0);
2146 NVResetCrtcConfig(crtc, FALSE);
2148 crtc->funcs->dpms(crtc, DPMSModeOff);
2150 /* Sync the engine before adjust mode */
2151 if (pNv->EXADriverPtr) {
2152 exaMarkSync(pScrn->pScreen);
2153 exaWaitSync(pScrn->pScreen);
2156 NVCrtcBlankScreen(crtc, FALSE); /* Blank screen */
2158 /* Some more preperation. */
2159 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG, 0x1); /* Go to non-vga mode/out of enhanced mode */
2160 if (pNv->Architecture == NV_ARCH_40) {
2161 uint32_t reg900 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900);
2162 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 & ~0x10000);
2166 void nv_crtc_commit(xf86CrtcPtr crtc)
2168 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2169 ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->head);
2171 crtc->funcs->dpms (crtc, DPMSModeOn);
2173 if (crtc->scrn->pScreen != NULL)
2174 xf86_reload_cursors (crtc->scrn->pScreen);
2176 NVResetCrtcConfig(crtc, TRUE);
2179 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
2181 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2182 ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->head);
2187 static void nv_crtc_unlock(xf86CrtcPtr crtc)
2189 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2190 ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->head);
2194 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
2197 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2198 ScrnInfoPtr pScrn = crtc->scrn;
2199 NVPtr pNv = NVPTR(pScrn);
2203 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2205 switch (pNv->CurrentLayout.depth) {
2208 /* We've got 5 bit (32 values) colors and 256 registers for each color */
2209 for (i = 0; i < 32; i++) {
2210 for (j = 0; j < 8; j++) {
2211 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2212 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
2213 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2219 /* First deal with the 5 bit colors */
2220 for (i = 0; i < 32; i++) {
2221 for (j = 0; j < 8; j++) {
2222 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2223 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2226 /* Now deal with the 6 bit color */
2227 for (i = 0; i < 64; i++) {
2228 for (j = 0; j < 4; j++) {
2229 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
2235 for (i = 0; i < 256; i++) {
2236 regp->DAC[i * 3] = red[i] >> 8;
2237 regp->DAC[(i * 3) + 1] = green[i] >> 8;
2238 regp->DAC[(i * 3) + 2] = blue[i] >> 8;
2243 NVCrtcLoadPalette(crtc);
2247 * Allocates memory for a locked-in-framebuffer shadow of the given
2248 * width and height for this CRTC's rotated shadow framebuffer.
2252 nv_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
2254 ErrorF("nv_crtc_shadow_allocate is called\n");
2255 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2256 ScrnInfoPtr pScrn = crtc->scrn;
2257 #if !NOUVEAU_EXA_PIXMAPS
2258 ScreenPtr pScreen = pScrn->pScreen;
2259 #endif /* !NOUVEAU_EXA_PIXMAPS */
2260 NVPtr pNv = NVPTR(pScrn);
2263 unsigned long rotate_pitch;
2264 int size, align = 64;
2266 rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2267 size = rotate_pitch * height;
2269 assert(nv_crtc->shadow == NULL);
2270 #if NOUVEAU_EXA_PIXMAPS
2271 if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN,
2272 align, size, &nv_crtc->shadow)) {
2273 ErrorF("Failed to allocate memory for shadow buffer!\n");
2277 if (nv_crtc->shadow && nouveau_bo_map(nv_crtc->shadow, NOUVEAU_BO_RDWR)) {
2278 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2279 "Failed to map shadow buffer.\n");
2283 offset = nv_crtc->shadow->map;
2285 nv_crtc->shadow = exaOffscreenAlloc(pScreen, size, align, TRUE, NULL, NULL);
2286 if (nv_crtc->shadow == NULL) {
2287 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2288 "Couldn't allocate shadow memory for rotated CRTC\n");
2291 offset = pNv->FB->map + nv_crtc->shadow->offset;
2292 #endif /* NOUVEAU_EXA_PIXMAPS */
2298 * Creates a pixmap for this CRTC's rotated shadow framebuffer.
2301 nv_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
2303 ErrorF("nv_crtc_shadow_create is called\n");
2304 ScrnInfoPtr pScrn = crtc->scrn;
2305 #if NOUVEAU_EXA_PIXMAPS
2306 ScreenPtr pScreen = pScrn->pScreen;
2307 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2308 #endif /* NOUVEAU_EXA_PIXMAPS */
2309 unsigned long rotate_pitch;
2310 PixmapPtr rotate_pixmap;
2311 #if NOUVEAU_EXA_PIXMAPS
2312 struct nouveau_pixmap *nvpix;
2313 #endif /* NOUVEAU_EXA_PIXMAPS */
2316 data = crtc->funcs->shadow_allocate (crtc, width, height);
2318 rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2320 #if NOUVEAU_EXA_PIXMAPS
2321 /* Create a dummy pixmap, to get a private that will be accepted by the system.*/
2322 rotate_pixmap = pScreen->CreatePixmap(pScreen,
2325 #ifdef CREATE_PIXMAP_USAGE_SCRATCH /* there seems to have been no api bump */
2330 #endif /* CREATE_PIXMAP_USAGE_SCRATCH */
2332 rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen,
2335 pScrn->bitsPerPixel,
2338 #endif /* NOUVEAU_EXA_PIXMAPS */
2340 if (rotate_pixmap == NULL) {
2341 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2342 "Couldn't allocate shadow pixmap for rotated CRTC\n");
2345 #if NOUVEAU_EXA_PIXMAPS
2346 nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2348 ErrorF("No shadow private, stage 1\n");
2350 nvpix->bo = nv_crtc->shadow;
2351 nvpix->mapped = TRUE;
2354 /* Modify the pixmap to actually be the one we need. */
2355 pScreen->ModifyPixmapHeader(rotate_pixmap,
2359 pScrn->bitsPerPixel,
2363 nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2364 if (!nvpix || !nvpix->bo)
2365 ErrorF("No shadow private, stage 2\n");
2366 #endif /* NOUVEAU_EXA_PIXMAPS */
2368 return rotate_pixmap;
2372 nv_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
2374 ErrorF("nv_crtc_shadow_destroy is called\n");
2375 ScrnInfoPtr pScrn = crtc->scrn;
2376 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2377 ScreenPtr pScreen = pScrn->pScreen;
2379 if (rotate_pixmap) { /* This should also unmap the buffer object if relevant. */
2380 pScreen->DestroyPixmap(rotate_pixmap);
2383 #if !NOUVEAU_EXA_PIXMAPS
2384 if (data && nv_crtc->shadow) {
2385 exaOffscreenFree(pScreen, nv_crtc->shadow);
2387 #endif /* !NOUVEAU_EXA_PIXMAPS */
2389 nv_crtc->shadow = NULL;
2392 /* NV04-NV10 doesn't support alpha cursors */
2393 static const xf86CrtcFuncsRec nv_crtc_funcs = {
2394 .dpms = nv_crtc_dpms,
2395 .save = nv_crtc_save, /* XXX */
2396 .restore = nv_crtc_restore, /* XXX */
2397 .mode_fixup = nv_crtc_mode_fixup,
2398 .mode_set = nv_crtc_mode_set,
2399 .prepare = nv_crtc_prepare,
2400 .commit = nv_crtc_commit,
2401 .destroy = NULL, /* XXX */
2402 .lock = nv_crtc_lock,
2403 .unlock = nv_crtc_unlock,
2404 .set_cursor_colors = nv_crtc_set_cursor_colors,
2405 .set_cursor_position = nv_crtc_set_cursor_position,
2406 .show_cursor = nv_crtc_show_cursor,
2407 .hide_cursor = nv_crtc_hide_cursor,
2408 .load_cursor_image = nv_crtc_load_cursor_image,
2409 .gamma_set = nv_crtc_gamma_set,
2410 .shadow_create = nv_crtc_shadow_create,
2411 .shadow_allocate = nv_crtc_shadow_allocate,
2412 .shadow_destroy = nv_crtc_shadow_destroy,
2415 /* NV11 and up has support for alpha cursors. */
2416 /* Due to different maximum sizes we cannot allow it to use normal cursors */
2417 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
2418 .dpms = nv_crtc_dpms,
2419 .save = nv_crtc_save, /* XXX */
2420 .restore = nv_crtc_restore, /* XXX */
2421 .mode_fixup = nv_crtc_mode_fixup,
2422 .mode_set = nv_crtc_mode_set,
2423 .prepare = nv_crtc_prepare,
2424 .commit = nv_crtc_commit,
2425 .destroy = NULL, /* XXX */
2426 .lock = nv_crtc_lock,
2427 .unlock = nv_crtc_unlock,
2428 .set_cursor_colors = NULL, /* Alpha cursors do not need this */
2429 .set_cursor_position = nv_crtc_set_cursor_position,
2430 .show_cursor = nv_crtc_show_cursor,
2431 .hide_cursor = nv_crtc_hide_cursor,
2432 .load_cursor_argb = nv_crtc_load_cursor_argb,
2433 .gamma_set = nv_crtc_gamma_set,
2434 .shadow_create = nv_crtc_shadow_create,
2435 .shadow_allocate = nv_crtc_shadow_allocate,
2436 .shadow_destroy = nv_crtc_shadow_destroy,
2441 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
2443 NVPtr pNv = NVPTR(pScrn);
2445 NVCrtcPrivatePtr nv_crtc;
2447 if (pNv->NVArch >= 0x11) {
2448 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
2450 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
2455 nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
2456 nv_crtc->head = crtc_num;
2458 crtc->driver_private = nv_crtc;
2460 NVCrtcLockUnlock(crtc, FALSE);
2463 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2465 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2469 regp = &state->crtc_reg[nv_crtc->head];
2471 NVWriteMiscOut(crtc, regp->MiscOutReg);
2473 for (i = 1; i < 5; i++)
2474 NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
2476 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
2477 NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
2479 for (i = 0; i < 25; i++)
2480 NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
2482 for (i = 0; i < 9; i++)
2483 NVWriteVgaGr(crtc, i, regp->Graphics[i]);
2485 NVEnablePalette(crtc);
2486 for (i = 0; i < 21; i++)
2487 NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
2489 NVDisablePalette(crtc);
2492 static void nv_crtc_fix_nv40_hw_cursor(xf86CrtcPtr crtc)
2494 /* TODO - implement this properly */
2495 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2496 ScrnInfoPtr pScrn = crtc->scrn;
2497 NVPtr pNv = NVPTR(pScrn);
2499 if (pNv->Architecture == NV_ARCH_40) { /* HW bug */
2500 volatile uint32_t curpos = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS);
2501 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS, curpos);
2504 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override)
2506 ScrnInfoPtr pScrn = crtc->scrn;
2507 NVPtr pNv = NVPTR(pScrn);
2508 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2512 regp = &state->crtc_reg[nv_crtc->head];
2514 /* If we ever get down to pre-nv10 cards, then we must reinstate some limits. */
2515 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
2516 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
2517 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
2518 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
2519 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2520 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2521 nvWriteMC(pNv, 0x1588, 0);
2523 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
2524 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
2525 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO, regp->gpio);
2526 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0830, regp->unk830);
2527 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0834, regp->unk834);
2528 if (pNv->Architecture == NV_ARCH_40) {
2529 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0850, regp->unk850);
2530 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_081C, regp->unk81c);
2533 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG, regp->config);
2534 if (pNv->Architecture == NV_ARCH_40) {
2535 uint32_t reg900 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900);
2536 if (regp->config == 0x2) { /* enhanced "horizontal only" non-vga mode */
2537 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 | 0x10000);
2539 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_900, reg900 & ~0x10000);
2543 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
2544 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
2545 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
2546 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
2547 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
2548 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
2549 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
2550 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
2551 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
2552 if (pNv->Architecture >= NV_ARCH_30) {
2553 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
2556 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
2557 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
2558 nv_crtc_fix_nv40_hw_cursor(crtc);
2559 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
2560 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
2562 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
2563 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
2564 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3C, regp->CRTC[NV_VGA_CRTCX_3C]);
2565 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
2566 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_43, regp->CRTC[NV_VGA_CRTCX_43]);
2567 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
2568 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_4B, regp->CRTC[NV_VGA_CRTCX_4B]);
2569 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
2570 /* NV11 and NV20 stop at 0x52. */
2571 if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
2573 for (i = 0; i < 0x10; i++)
2574 NVWriteVGACR5758(pNv, nv_crtc->head, i, regp->CR58[i]);
2576 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
2577 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
2579 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
2581 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_85, regp->CRTC[NV_VGA_CRTCX_85]);
2582 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_86, regp->CRTC[NV_VGA_CRTCX_86]);
2585 /* Setting 1 on this value gives you interrupts for every vblank period. */
2586 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_EN_0, 0);
2587 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
2589 pNv->CurrentState = state;
2592 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2594 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2598 regp = &state->crtc_reg[nv_crtc->head];
2600 regp->MiscOutReg = NVReadMiscOut(crtc);
2602 for (i = 0; i < 25; i++)
2603 regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
2605 NVEnablePalette(crtc);
2606 for (i = 0; i < 21; i++)
2607 regp->Attribute[i] = NVReadVgaAttr(crtc, i);
2608 NVDisablePalette(crtc);
2610 for (i = 0; i < 9; i++)
2611 regp->Graphics[i] = NVReadVgaGr(crtc, i);
2613 for (i = 1; i < 5; i++)
2614 regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
2618 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2620 ScrnInfoPtr pScrn = crtc->scrn;
2621 NVPtr pNv = NVPTR(pScrn);
2622 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2626 regp = &state->crtc_reg[nv_crtc->head];
2628 /* If we ever get down to pre-nv10 cards, then we must reinstate some limits. */
2629 regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
2630 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
2631 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
2632 regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
2633 regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
2634 regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
2635 regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
2637 regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
2638 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
2639 regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
2640 if (pNv->Architecture >= NV_ARCH_30) {
2641 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
2643 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
2644 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
2645 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
2646 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
2648 regp->gpio = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO);
2649 regp->unk830 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0830);
2650 regp->unk834 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0834);
2651 if (pNv->Architecture == NV_ARCH_40) {
2652 regp->unk850 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0850);
2653 regp->unk81c = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_081C);
2656 regp->config = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG);
2658 regp->head = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL);
2659 regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
2660 regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
2662 regp->cursorConfig = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG);
2664 regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
2665 regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
2666 regp->CRTC[NV_VGA_CRTCX_3C] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3C);
2667 regp->CRTC[NV_VGA_CRTCX_43] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_43);
2668 regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
2669 regp->CRTC[NV_VGA_CRTCX_4B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_4B);
2670 regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
2671 /* NV11 and NV20 don't have this, they stop at 0x52. */
2672 if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
2673 for (i = 0; i < 0x10; i++)
2674 regp->CR58[i] = NVReadVGACR5758(pNv, nv_crtc->head, i);
2676 regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
2677 regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
2678 regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
2680 regp->CRTC[NV_VGA_CRTCX_85] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_85);
2681 regp->CRTC[NV_VGA_CRTCX_86] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_86);
2685 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2687 ScrnInfoPtr pScrn = crtc->scrn;
2688 NVPtr pNv = NVPTR(pScrn);
2689 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2693 regp = &state->crtc_reg[nv_crtc->head];
2695 regp->general = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL);
2697 regp->fp_control = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL);
2698 regp->debug_0 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0);
2699 regp->debug_1 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1);
2700 regp->debug_2 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2);
2702 regp->unk_a20 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20);
2703 regp->unk_a24 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24);
2704 regp->unk_a34 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34);
2706 if (pNv->NVArch == 0x11) {
2707 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11);
2708 } else if (pNv->twoHeads) {
2709 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER);
2711 regp->nv10_cursync = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC);
2713 /* The regs below are 0 for non-flatpanels, so you can load and save them */
2715 for (i = 0; i < 7; i++) {
2716 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2717 regp->fp_horiz_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2720 for (i = 0; i < 7; i++) {
2721 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2722 regp->fp_vert_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2725 regp->fp_hvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START);
2726 regp->fp_hvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END);
2727 regp->fp_vvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START);
2728 regp->fp_vvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END);
2731 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2733 ScrnInfoPtr pScrn = crtc->scrn;
2734 NVPtr pNv = NVPTR(pScrn);
2735 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2739 regp = &state->crtc_reg[nv_crtc->head];
2741 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL, regp->general);
2743 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control);
2744 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0, regp->debug_0);
2745 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
2746 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
2748 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20, regp->unk_a20);
2749 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24, regp->unk_a24);
2750 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34, regp->unk_a34);
2752 if (pNv->NVArch == 0x11) {
2753 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11, regp->dither);
2754 } else if (pNv->twoHeads) {
2755 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER, regp->dither);
2757 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
2759 /* The regs below are 0 for non-flatpanels, so you can load and save them */
2761 for (i = 0; i < 7; i++) {
2762 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2763 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_horiz_regs[i]);
2766 for (i = 0; i < 7; i++) {
2767 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2768 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_vert_regs[i]);
2771 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START, regp->fp_hvalid_start);
2772 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END, regp->fp_hvalid_end);
2773 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START, regp->fp_vvalid_start);
2774 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END, regp->fp_vvalid_end);
2778 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y)
2780 ScrnInfoPtr pScrn = crtc->scrn;
2781 NVPtr pNv = NVPTR(pScrn);
2782 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2783 NVFBLayout *pLayout = &pNv->CurrentLayout;
2786 ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
2788 start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
2789 if (crtc->rotatedData != NULL) { /* we do not exist on the real framebuffer */
2790 #if NOUVEAU_EXA_PIXMAPS
2791 start = nv_crtc->shadow->offset;
2793 start = pNv->FB->offset + nv_crtc->shadow->offset; /* We do exist relative to the framebuffer */
2796 start += pNv->FB->offset;
2799 /* 30 bits addresses in 32 bits according to haiku */
2800 nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_START, start & 0xfffffffc);
2802 /* set NV4/NV10 byte adress: (bit0 - 1) */
2803 NVWriteVgaAttr(crtc, 0x13, (start & 0x3) << 1);
2809 static void NVCrtcWriteDacMask(xf86CrtcPtr crtc, uint8_t value)
2811 ScrnInfoPtr pScrn = crtc->scrn;
2812 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2813 NVPtr pNv = NVPTR(pScrn);
2814 volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2816 NV_WR08(pDACReg, VGA_DAC_MASK, value);
2819 static uint8_t NVCrtcReadDacMask(xf86CrtcPtr crtc)
2821 ScrnInfoPtr pScrn = crtc->scrn;
2822 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2823 NVPtr pNv = NVPTR(pScrn);
2824 volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2826 return NV_RD08(pDACReg, VGA_DAC_MASK);
2829 static void NVCrtcWriteDacReadAddr(xf86CrtcPtr crtc, uint8_t value)
2831 ScrnInfoPtr pScrn = crtc->scrn;
2832 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2833 NVPtr pNv = NVPTR(pScrn);
2834 volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2836 NV_WR08(pDACReg, VGA_DAC_READ_ADDR, value);
2839 static void NVCrtcWriteDacWriteAddr(xf86CrtcPtr crtc, uint8_t value)
2841 ScrnInfoPtr pScrn = crtc->scrn;
2842 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2843 NVPtr pNv = NVPTR(pScrn);
2844 volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2846 NV_WR08(pDACReg, VGA_DAC_WRITE_ADDR, value);
2849 static void NVCrtcWriteDacData(xf86CrtcPtr crtc, uint8_t value)
2851 ScrnInfoPtr pScrn = crtc->scrn;
2852 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2853 NVPtr pNv = NVPTR(pScrn);
2854 volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2856 NV_WR08(pDACReg, VGA_DAC_DATA, value);
2859 static uint8_t NVCrtcReadDacData(xf86CrtcPtr crtc, uint8_t value)
2861 ScrnInfoPtr pScrn = crtc->scrn;
2862 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2863 NVPtr pNv = NVPTR(pScrn);
2864 volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2866 return NV_RD08(pDACReg, VGA_DAC_DATA);
2869 void NVCrtcLoadPalette(xf86CrtcPtr crtc)
2872 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2874 ScrnInfoPtr pScrn = crtc->scrn;
2875 NVPtr pNv = NVPTR(pScrn);
2877 regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2879 NVCrtcSetOwner(crtc);
2880 NVCrtcWriteDacMask(crtc, 0xff);
2881 NVCrtcWriteDacWriteAddr(crtc, 0x00);
2883 for (i = 0; i<768; i++) {
2884 NVCrtcWriteDacData(crtc, regp->DAC[i]);
2886 NVDisablePalette(crtc);
2890 void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
2894 NVCrtcSetOwner(crtc);
2896 scrn = NVReadVgaSeq(crtc, 0x01);
2903 NVVgaSeqReset(crtc, TRUE);
2904 NVWriteVgaSeq(crtc, 0x01, scrn);
2905 NVVgaSeqReset(crtc, FALSE);
2908 /*************************************************************************** \
2910 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
2912 |* NOTICE TO USER: The source code is copyrighted under U.S. and *|
2913 |* international laws. Users and possessors of this source code are *|
2914 |* hereby granted a nonexclusive, royalty-free copyright license to *|
2915 |* use this code in individual and commercial software. *|
2917 |* Any use of this source code must include, in the user documenta- *|
2918 |* tion and internal comments to the code, notices to the end user *|
2921 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
2923 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
2924 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
2925 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
2926 |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
2927 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
2928 |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
2929 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
2930 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
2931 |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
2932 |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
2933 |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
2935 |* U.S. Government End Users. This source code is a "commercial *|
2936 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
2937 |* consisting of "commercial computer software" and "commercial *|
2938 |* computer software documentation," as such terms are used in *|
2939 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
2940 |* ment only as a commercial end item. Consistent with 48 C.F.R. *|
2941 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
2942 |* all U.S. Government End Users acquire the source code with only *|
2943 |* those rights set forth herein. *|
2945 \***************************************************************************/