git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 1993-2003 NVIDIA, Corporation
   3  * Copyright 2006 Dave Airlie
   4  * Copyright 2007 Maarten Maathuis
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include "nv_include.h"
  27
  28 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  29 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  30 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  31 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  32 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  33 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  34 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  35 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  36
  37 static uint32_t NVCrtcReadCRTC(xf86CrtcPtr crtc, uint32_t reg)
  38 {
  39         ScrnInfoPtr pScrn = crtc->scrn;
  40         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
  41         NVPtr pNv = NVPTR(pScrn);
  42
  43         return NVReadCRTC(pNv, nv_crtc->head, reg);
  44 }
  45
  46 static void NVCrtcWriteCRTC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
  47 {
  48         ScrnInfoPtr pScrn = crtc->scrn;
  49         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
  50         NVPtr pNv = NVPTR(pScrn);
  51
  52         NVWriteCRTC(pNv, nv_crtc->head, reg, val);
  53 }
  54
  55 static uint32_t NVCrtcReadRAMDAC(xf86CrtcPtr crtc, uint32_t reg)
  56 {
  57         ScrnInfoPtr pScrn = crtc->scrn;
  58         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
  59         NVPtr pNv = NVPTR(pScrn);
  60
  61         return NVReadRAMDAC(pNv, nv_crtc->head, reg);
  62 }
  63
  64 static void NVCrtcWriteRAMDAC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
  65 {
  66         ScrnInfoPtr pScrn = crtc->scrn;
  67         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
  68         NVPtr pNv = NVPTR(pScrn);
  69
  70         NVWriteRAMDAC(pNv, nv_crtc->head, reg, val);
  71 }
  72
  73 void NVCrtcLockUnlock(xf86CrtcPtr crtc, bool lock)
  74 {
  75         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
  76         NVPtr pNv = NVPTR(crtc->scrn);
  77
  78         if (pNv->twoHeads)
  79                 NVSetOwner(pNv, nv_crtc->head);
  80         NVLockVgaCrtc(pNv, nv_crtc->head, lock);
  81 }
  82
  83 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
  84 /* They are only valid for NV4x, appearantly reordered for NV5x */
  85 /* gpu pll: 0x4000 + 0x4004
  86  * unknown pll: 0x4008 + 0x400c
  87  * vpll1: 0x4010 + 0x4014
  88  * vpll2: 0x4018 + 0x401c
  89  * unknown pll: 0x4020 + 0x4024
  90  * unknown pll: 0x4038 + 0x403c
  91  * Some of the unknown's are probably memory pll's.
  92  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
  93  * 1 and 2 refer to the registers of each pair. There is only one post divider.
  94  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
  95  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
  96  *     bit8: A switch that turns of the second divider and multiplier off.
  97  *     bit12: Also a switch, i haven't seen it yet.
  98  *     bit16-19: p-divider
  99  *     but 28-31: Something related to the mode that is used (see bit8).
 100  * 2) bit0-7: m-divider (a)
 101  *     bit8-15: n-multiplier (a)
 102  *     bit16-23: m-divider (b)
 103  *     bit24-31: n-multiplier (b)
 104  */
 105
 106 /* Modifying the gpu pll for example requires:
 107  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 108  * This is not needed for the vpll's which have their own bits.
 109  */
 110
 111 static void nv_crtc_save_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 112 {
 113         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 114         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
 115         NVPtr pNv = NVPTR(crtc->scrn);
 116
 117         if (nv_crtc->head) {
 118                 regp->vpll_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2);
 119                 if (pNv->twoStagePLL)
 120                         regp->vpll_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B);
 121         } else {
 122                 regp->vpll_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL);
 123                 if (pNv->twoStagePLL)
 124                         regp->vpll_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B);
 125         }
 126         if (pNv->twoHeads)
 127                 state->sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
 128         state->pllsel = NVReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT);
 129         if (pNv->Architecture == NV_ARCH_40)
 130                 state->reg580 = NVReadRAMDAC(pNv, 0, NV_RAMDAC_580);
 131 }
 132
 133 static void nv_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 134 {
 135         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 136         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
 137         ScrnInfoPtr pScrn = crtc->scrn;
 138         NVPtr pNv = NVPTR(pScrn);
 139         uint32_t savedc040 = 0;
 140
 141         /* This sequence is important, the NV28 is very sensitive in this area. */
 142         /* Keep pllsel last and sel_clk first. */
 143         if (pNv->twoHeads)
 144                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, state->sel_clk);
 145
 146         if (pNv->Architecture == NV_ARCH_40) {
 147                 savedc040 = nvReadMC(pNv, 0xc040);
 148
 149                 /* for vpll1 change bits 16 and 17 are disabled */
 150                 /* for vpll2 change bits 18 and 19 are disabled */
 151                 nvWriteMC(pNv, 0xc040, savedc040 & ~(3 << (16 + nv_crtc->head * 2)));
 152         }
 153
 154         if (nv_crtc->head) {
 155                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2, regp->vpll_a);
 156                 if (pNv->twoStagePLL)
 157                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B, regp->vpll_b);
 158         } else {
 159                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL, regp->vpll_a);
 160                 if (pNv->twoStagePLL)
 161                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B, regp->vpll_b);
 162         }
 163
 164         if (pNv->Architecture == NV_ARCH_40) {
 165                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_580, state->reg580);
 166
 167                 /* We need to wait a while */
 168                 usleep(5000);
 169                 nvWriteMC(pNv, 0xc040, savedc040);
 170         }
 171
 172         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_PLL_SELECT %08X\n", state->pllsel);
 173         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
 174 }
 175
 176 static void nv_crtc_cursor_set(xf86CrtcPtr crtc)
 177 {
 178         NVPtr pNv = NVPTR(crtc->scrn);
 179         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 180         uint32_t cursor_start;
 181         uint8_t *CRTC = pNv->ModeReg.crtc_reg[nv_crtc->head].CRTC;
 182
 183         if (pNv->Architecture == NV_ARCH_04)
 184                 cursor_start = 0x5E00 << 2;
 185         else
 186                 cursor_start = nv_crtc->head ? pNv->Cursor2->offset : pNv->Cursor->offset;
 187
 188         CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = cursor_start >> 17;
 189         if (pNv->Architecture != NV_ARCH_04)
 190                 CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] |= NV_CIO_CRE_HCUR_ASI;
 191         CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = (cursor_start >> 11) << 2;
 192         if (crtc->mode.Flags & V_DBLSCAN)
 193                 CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |= NV_CIO_CRE_HCUR_ADDR1_CUR_DBL;
 194         CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = cursor_start >> 24;
 195
 196         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR0_INDEX, CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX]);
 197         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR1_INDEX, CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX]);
 198         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR2_INDEX, CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX]);
 199         if (pNv->Architecture == NV_ARCH_40)
 200                 nv_fix_nv40_hw_cursor(pNv, nv_crtc->head);
 201 }
 202
 203 static void nv_crtc_calc_state_ext(xf86CrtcPtr crtc, DisplayModePtr mode, int dot_clock)
 204 {
 205         ScrnInfoPtr pScrn = crtc->scrn;
 206         NVPtr pNv = NVPTR(pScrn);
 207         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 208         RIVA_HW_STATE *state = &pNv->ModeReg;
 209         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
 210         struct pll_lims pll_lim;
 211         int NM1 = 0xbeef, NM2 = 0, log2P = 0, VClk = 0;
 212         uint32_t g70_pll_special_bits = 0;
 213         bool nv4x_single_stage_pll_mode = false;
 214         uint8_t arbitration0;
 215         uint16_t arbitration1;
 216
 217         if (!get_pll_limits(pScrn, nv_crtc->head ? VPLL2 : VPLL1, &pll_lim))
 218                 return;
 219
 220         if (pNv->twoStagePLL || pNv->NVArch == 0x30 || pNv->NVArch == 0x35) {
 221                 if (dot_clock < pll_lim.vco1.maxfreq && pNv->NVArch > 0x40) { /* use a single VCO */
 222                         nv4x_single_stage_pll_mode = true;
 223                         /* Turn the second set of divider and multiplier off */
 224                         /* Bogus data, the same nvidia uses */
 225                         NM2 = 0x11f;
 226                         VClk = getMNP_single(pScrn, &pll_lim, dot_clock, &NM1, &log2P);
 227                 } else
 228                         VClk = getMNP_double(pScrn, &pll_lim, dot_clock, &NM1, &NM2, &log2P);
 229         } else
 230                 VClk = getMNP_single(pScrn, &pll_lim, dot_clock, &NM1, &log2P);
 231
 232         /* Are these all the (relevant) G70 cards? */
 233         if (pNv->NVArch == 0x4B || pNv->NVArch == 0x46 || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
 234                 /* This is a big guess, but should be reasonable until we can narrow it down. */
 235                 /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
 236                 if (nv4x_single_stage_pll_mode)
 237                         g70_pll_special_bits = 0x1;
 238                 else
 239                         g70_pll_special_bits = 0x3;
 240         }
 241
 242         if (pNv->NVArch == 0x30 || pNv->NVArch == 0x35)
 243                 /* See nvregisters.xml for details. */
 244                 regp->vpll_a = (NM2 & (0x18 << 8)) << 13 | (NM2 & (0x7 << 8)) << 11 | log2P << 16 | NV30_RAMDAC_ENABLE_VCO2 | (NM2 & 7) << 4 | NM1;
 245         else
 246                 regp->vpll_a = g70_pll_special_bits << 30 | log2P << 16 | NM1;
 247         regp->vpll_b = NV31_RAMDAC_ENABLE_VCO2 | NM2;
 248
 249         if (nv4x_single_stage_pll_mode) {
 250                 if (nv_crtc->head == 0)
 251                         state->reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 252                 else
 253                         state->reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 254         } else {
 255                 if (nv_crtc->head == 0)
 256                         state->reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
 257                 else
 258                         state->reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
 259         }
 260
 261         /* The NV40 seems to have more similarities to NV3x than other NV4x */
 262         if (pNv->NVArch < 0x41)
 263                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL |
 264                                  NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL;
 265         /* The blob uses this always, so let's do the same */
 266         if (pNv->Architecture == NV_ARCH_40)
 267                 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
 268
 269         if (nv_crtc->head == 1) {
 270                 if (!nv4x_single_stage_pll_mode)
 271                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 272                 else
 273                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 274                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
 275         } else {
 276                 if (!nv4x_single_stage_pll_mode)
 277                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 278                 else
 279                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 280                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
 281         }
 282
 283         if ((!pNv->twoStagePLL && pNv->NVArch != 0x30 && pNv->NVArch != 0x35) || nv4x_single_stage_pll_mode)
 284                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vpll: n %d m %d log2p %d\n", NM1 >> 8, NM1 & 0xff, log2P);
 285         else
 286                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", NM1 >> 8, NM2 >> 8, NM1 & 0xff, NM2 & 0xff, log2P);
 287
 288         if (pNv->Architecture < NV_ARCH_30)
 289                 nv4_10UpdateArbitrationSettings(pScrn, VClk, pScrn->bitsPerPixel, &arbitration0, &arbitration1);
 290         else if ((pNv->Chipset & 0xfff0) == CHIPSET_C51 ||
 291                  (pNv->Chipset & 0xfff0) == CHIPSET_C512) {
 292                 arbitration0 = 128;
 293                 arbitration1 = 0x0480;
 294         } else
 295                 nv30UpdateArbitrationSettings(&arbitration0, &arbitration1);
 296
 297         regp->CRTC[NV_CIO_CRE_FF_INDEX] = arbitration0;
 298         regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arbitration1 & 0xff;
 299         if (pNv->Architecture >= NV_ARCH_30)
 300                 regp->CRTC[NV_CIO_CRE_47] = arbitration1 >> 8;
 301
 302         nv_crtc_cursor_set(crtc);
 303 }
 304
 305 static void
 306 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
 307 {
 308         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 309         ScrnInfoPtr pScrn = crtc->scrn;
 310         NVPtr pNv = NVPTR(pScrn);
 311         unsigned char seq1 = 0, crtc17 = 0;
 312         unsigned char crtc1A;
 313
 314         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Setting dpms mode %d on CRTC %d\n", mode, nv_crtc->head);
 315
 316         if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */
 317                 return;
 318
 319         nv_crtc->last_dpms = mode;
 320
 321         if (pNv->twoHeads)
 322                 NVSetOwner(pNv, nv_crtc->head);
 323
 324         crtc1A = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC1_INDEX) & ~0xC0;
 325         switch(mode) {
 326                 case DPMSModeStandby:
 327                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
 328                 seq1 = 0x20;
 329                 crtc17 = 0x80;
 330                 crtc1A |= 0x80;
 331                 break;
 332         case DPMSModeSuspend:
 333                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
 334                 seq1 = 0x20;
 335                 crtc17 = 0x80;
 336                 crtc1A |= 0x40;
 337                 break;
 338         case DPMSModeOff:
 339                 /* Screen: Off; HSync: Off, VSync: Off */
 340                 seq1 = 0x20;
 341                 crtc17 = 0x00;
 342                 crtc1A |= 0xC0;
 343                 break;
 344         case DPMSModeOn:
 345         default:
 346                 /* Screen: On; HSync: On, VSync: On */
 347                 seq1 = 0x00;
 348                 crtc17 = 0x80;
 349                 break;
 350         }
 351
 352         NVVgaSeqReset(pNv, nv_crtc->head, true);
 353         /* Each head has it's own sequencer, so we can turn it off when we want */
 354         seq1 |= (NVReadVgaSeq(pNv, nv_crtc->head, NV_VIO_SR_CLOCK_INDEX) & ~0x20);
 355         NVWriteVgaSeq(pNv, nv_crtc->head, NV_VIO_SR_CLOCK_INDEX, seq1);
 356         crtc17 |= (NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CR_MODE_INDEX) & ~0x80);
 357         usleep(10000);
 358         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CR_MODE_INDEX, crtc17);
 359         NVVgaSeqReset(pNv, nv_crtc->head, false);
 360
 361         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC1_INDEX, crtc1A);
 362 }
 363
 364 static Bool
 365 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
 366                      DisplayModePtr adjusted_mode)
 367 {
 368         return TRUE;
 369 }
 370
 371 static void
 372 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
 373 {
 374         ScrnInfoPtr pScrn = crtc->scrn;
 375         NVPtr pNv = NVPTR(pScrn);
 376         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 377         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 378
 379         /* Calculate our timings */
 380         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
 381         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
 382         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
 383         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
 384         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
 385         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
 386         int vertDisplay         = mode->CrtcVDisplay                    - 1;
 387         int vertStart           = mode->CrtcVSyncStart          - 1;
 388         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
 389         int vertTotal           = mode->CrtcVTotal                      - 2;
 390         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
 391         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
 392
 393         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 394         bool fp_output = false;
 395         int i;
 396
 397         for (i = 0; i < xf86_config->num_output; i++) {
 398                 xf86OutputPtr output = xf86_config->output[i];
 399                 struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 400
 401                 if (output->crtc == crtc && (nv_encoder->dcb->type == OUTPUT_LVDS ||
 402                                              nv_encoder->dcb->type == OUTPUT_TMDS))
 403                         fp_output = true;
 404         }
 405
 406         if (fp_output) {
 407                 vertStart = vertTotal - 3;
 408                 vertEnd = vertTotal - 2;
 409                 vertBlankStart = vertStart;
 410                 horizStart = horizTotal - 5;
 411                 horizEnd = horizTotal - 2;
 412                 horizBlankEnd = horizTotal + 4;
 413                 if (pNv->overlayAdaptor && pNv->Architecture >= NV_ARCH_10)
 414                         /* This reportedly works around some video overlay bandwidth problems */
 415                         horizTotal += 2;
 416         }
 417
 418         if (mode->Flags & V_INTERLACE)
 419                 vertTotal |= 1;
 420
 421 #if 0
 422         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
 423         ErrorF("horizStart: 0x%X \n", horizStart);
 424         ErrorF("horizEnd: 0x%X \n", horizEnd);
 425         ErrorF("horizTotal: 0x%X \n", horizTotal);
 426         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
 427         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
 428         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
 429         ErrorF("vertStart: 0x%X \n", vertStart);
 430         ErrorF("vertEnd: 0x%X \n", vertEnd);
 431         ErrorF("vertTotal: 0x%X \n", vertTotal);
 432         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
 433         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
 434 #endif
 435
 436         /*
 437         * compute correct Hsync & Vsync polarity
 438         */
 439         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
 440                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
 441
 442                 regp->MiscOutReg = 0x23;
 443                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
 444                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
 445         } else {
 446                 int VDisplay = mode->VDisplay;
 447                 if (mode->Flags & V_DBLSCAN)
 448                         VDisplay *= 2;
 449                 if (mode->VScan > 1)
 450                         VDisplay *= mode->VScan;
 451                 if (VDisplay < 400)
 452                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
 453                 else if (VDisplay < 480)
 454                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
 455                 else if (VDisplay < 768)
 456                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
 457                 else
 458                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
 459         }
 460
 461         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
 462
 463         /*
 464         * Time Sequencer
 465         */
 466         regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00;
 467         /* 0x20 disables the sequencer */
 468         if (mode->Flags & V_CLKDIV2)
 469                 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29;
 470         else
 471                 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21;
 472         regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F;
 473         regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00;
 474         regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E;
 475
 476         /*
 477         * CRTC Controller
 478         */
 479         regp->CRTC[NV_CIO_CR_HDT_INDEX]  = Set8Bits(horizTotal);
 480         regp->CRTC[NV_CIO_CR_HDE_INDEX]  = Set8Bits(horizDisplay);
 481         regp->CRTC[NV_CIO_CR_HBS_INDEX]  = Set8Bits(horizBlankStart);
 482         regp->CRTC[NV_CIO_CR_HBE_INDEX]  = SetBitField(horizBlankEnd,4:0,4:0)
 483                                 | SetBit(7);
 484         regp->CRTC[NV_CIO_CR_HRS_INDEX]  = Set8Bits(horizStart);
 485         regp->CRTC[NV_CIO_CR_HRE_INDEX]  = SetBitField(horizBlankEnd,5:5,7:7)
 486                                 | SetBitField(horizEnd,4:0,4:0);
 487         regp->CRTC[NV_CIO_CR_VDT_INDEX]  = SetBitField(vertTotal,7:0,7:0);
 488         regp->CRTC[NV_CIO_CR_OVL_INDEX]  = SetBitField(vertTotal,8:8,0:0)
 489                                 | SetBitField(vertDisplay,8:8,1:1)
 490                                 | SetBitField(vertStart,8:8,2:2)
 491                                 | SetBitField(vertBlankStart,8:8,3:3)
 492                                 | SetBit(4)
 493                                 | SetBitField(vertTotal,9:9,5:5)
 494                                 | SetBitField(vertDisplay,9:9,6:6)
 495                                 | SetBitField(vertStart,9:9,7:7);
 496         regp->CRTC[NV_CIO_CR_RSAL_INDEX]  = 0x00;
 497         regp->CRTC[NV_CIO_CR_CELL_HT_INDEX]  = SetBitField(vertBlankStart,9:9,5:5)
 498                                 | SetBit(6)
 499                                 | (mode->Flags & V_DBLSCAN) * NV_CIO_CR_CELL_HT_SCANDBL;
 500         regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00;
 501         regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00;
 502         regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00;
 503         regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00;
 504         regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00;
 505         regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00;
 506         regp->CRTC[NV_CIO_CR_VRS_INDEX] = Set8Bits(vertStart);
 507         /* What is the meaning of bit5, it is empty in the vga spec. */
 508         regp->CRTC[NV_CIO_CR_VRE_INDEX] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
 509         regp->CRTC[NV_CIO_CR_VDE_INDEX] = Set8Bits(vertDisplay);
 510         /* framebuffer can be larger than crtc scanout area. */
 511         regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = pScrn->displayWidth / 8 * pScrn->bitsPerPixel / 8;
 512         regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00;
 513         regp->CRTC[NV_CIO_CR_VBS_INDEX] = Set8Bits(vertBlankStart);
 514         regp->CRTC[NV_CIO_CR_VBE_INDEX] = Set8Bits(vertBlankEnd);
 515         regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43;
 516         regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff;
 517
 518         /*
 519          * Some extended CRTC registers (they are not saved with the rest of the vga regs).
 520          */
 521
 522         /* framebuffer can be larger than crtc scanout area. */
 523         regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = ((pScrn->displayWidth / 8 * pScrn->bitsPerPixel / 8) & 0x700) >> 3;
 524         regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->CrtcHDisplay < 1280 ? 0x04 : 0x00;
 525         regp->CRTC[NV_CIO_CRE_LSR_INDEX] = SetBitField(horizBlankEnd,6:6,4:4)
 526                                 | SetBitField(vertBlankStart,10:10,3:3)
 527                                 | SetBitField(vertStart,10:10,2:2)
 528                                 | SetBitField(vertDisplay,10:10,1:1)
 529                                 | SetBitField(vertTotal,10:10,0:0);
 530
 531         regp->CRTC[NV_CIO_CRE_HEB__INDEX] = SetBitField(horizTotal,8:8,0:0)
 532                                 | SetBitField(horizDisplay,8:8,1:1)
 533                                 | SetBitField(horizBlankStart,8:8,2:2)
 534                                 | SetBitField(horizStart,8:8,3:3);
 535
 536         regp->CRTC[NV_CIO_CRE_EBR_INDEX] = SetBitField(vertTotal,11:11,0:0)
 537                                 | SetBitField(vertDisplay,11:11,2:2)
 538                                 | SetBitField(vertStart,11:11,4:4)
 539                                 | SetBitField(vertBlankStart,11:11,6:6);
 540
 541         if(mode->Flags & V_INTERLACE) {
 542                 horizTotal = (horizTotal >> 1) & ~1;
 543                 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = Set8Bits(horizTotal);
 544                 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= SetBitField(horizTotal,8:8,4:4);
 545         } else
 546                 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff;  /* interlace off */
 547
 548         /*
 549         * Graphics Display Controller
 550         */
 551         regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00;
 552         regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00;
 553         regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00;
 554         regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00;
 555         regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00;
 556         regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */
 557         regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */
 558         regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F;
 559         regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF;
 560
 561         regp->Attribute[0]  = 0x00; /* standard colormap translation */
 562         regp->Attribute[1]  = 0x01;
 563         regp->Attribute[2]  = 0x02;
 564         regp->Attribute[3]  = 0x03;
 565         regp->Attribute[4]  = 0x04;
 566         regp->Attribute[5]  = 0x05;
 567         regp->Attribute[6]  = 0x06;
 568         regp->Attribute[7]  = 0x07;
 569         regp->Attribute[8]  = 0x08;
 570         regp->Attribute[9]  = 0x09;
 571         regp->Attribute[10] = 0x0A;
 572         regp->Attribute[11] = 0x0B;
 573         regp->Attribute[12] = 0x0C;
 574         regp->Attribute[13] = 0x0D;
 575         regp->Attribute[14] = 0x0E;
 576         regp->Attribute[15] = 0x0F;
 577         regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */
 578         /* Non-vga */
 579         regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00;
 580         regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */
 581         regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00;
 582         regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00;
 583 }
 584
 585 /**
 586  * Sets up registers for the given mode/adjusted_mode pair.
 587  *
 588  * The clocks, CRTCs and outputs attached to this CRTC must be off.
 589  *
 590  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
 591  * be easily turned on/off after this.
 592  */
 593 static void
 594 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode)
 595 {
 596         ScrnInfoPtr pScrn = crtc->scrn;
 597         NVPtr pNv = NVPTR(pScrn);
 598         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 599         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 600         NVCrtcRegPtr savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
 601         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 602         bool lvds_output = false, tmds_output = false;
 603         int i;
 604
 605         for (i = 0; i < xf86_config->num_output; i++) {
 606                 xf86OutputPtr output = xf86_config->output[i];
 607                 struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 608
 609                 if (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_LVDS)
 610                         lvds_output = true;
 611                 if (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_TMDS)
 612                         tmds_output = true;
 613         }
 614
 615         /* Registers not directly related to the (s)vga mode */
 616
 617         /* bit2 = 0 -> fine pitched crtc granularity */
 618         /* The rest disables double buffering on CRTC access */
 619         regp->CRTC[NV_CIO_CRE_21] = 0xfa;
 620
 621         /* the blob sometimes sets |= 0x10 (which is the same as setting |=
 622          * 1 << 30 on 0x60.830), for no apparent reason */
 623         regp->CRTC[NV_CIO_CRE_59] = 0x0;
 624         if (tmds_output && pNv->Architecture < NV_ARCH_40)
 625                 regp->CRTC[NV_CIO_CRE_59] |= 0x1;
 626
 627         /* What is the meaning of this register? */
 628         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
 629         regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5);
 630
 631         regp->head = 0;
 632         /* Except for rare conditions I2C is enabled on the primary crtc */
 633         if (nv_crtc->head == 0)
 634                 regp->head |= NV_CRTC_FSEL_I2C;
 635         /* Set overlay to desired crtc. */
 636         if (pNv->overlayAdaptor) {
 637                 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(pNv);
 638                 if (pPriv->overlayCRTC == nv_crtc->head)
 639                         regp->head |= NV_CRTC_FSEL_OVERLAY;
 640         }
 641
 642         /* This is not what nv does, but it is what the blob does (for nv4x at least) */
 643         /* This fixes my cursor corruption issue */
 644         regp->cursorConfig = 0x0;
 645         if(mode->Flags & V_DBLSCAN)
 646                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_DOUBLE_SCAN;
 647         if (pNv->alphaCursor) {
 648                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_32BPP |
 649                                       NV_CRTC_CURSOR_CONFIG_64PIXELS |
 650                                       NV_CRTC_CURSOR_CONFIG_64LINES |
 651                                       NV_CRTC_CURSOR_CONFIG_ALPHA_BLEND;
 652         } else
 653                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_32LINES;
 654
 655         /* Unblock some timings */
 656         regp->CRTC[NV_CIO_CRE_53] = 0;
 657         regp->CRTC[NV_CIO_CRE_54] = 0;
 658
 659         /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
 660         if (lvds_output)
 661                 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11;
 662         else if (tmds_output)
 663                 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88;
 664         else
 665                 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22;
 666
 667         /* These values seem to vary */
 668         /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
 669         regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX];
 670
 671         regp->CRTC[NV_CIO_CRE_CSB] = 0x80;
 672
 673         /* What does this do?:
 674          * bit0: crtc0
 675          * bit6: lvds
 676          * bit7: (only in X)
 677          */
 678         if (nv_crtc->head == 0)
 679                 regp->CRTC[NV_CIO_CRE_4B] = 0x81;
 680         else
 681                 regp->CRTC[NV_CIO_CRE_4B] = 0x80;
 682
 683         if (lvds_output)
 684                 regp->CRTC[NV_CIO_CRE_4B] |= 0x40;
 685
 686         /* The blob seems to take the current value from crtc 0, add 4 to that
 687          * and reuse the old value for crtc 1 */
 688         regp->CRTC[NV_CIO_CRE_52] = pNv->SavedReg.crtc_reg[0].CRTC[NV_CIO_CRE_52];
 689         if (!nv_crtc->head)
 690                 regp->CRTC[NV_CIO_CRE_52] += 4;
 691
 692         regp->unk830 = mode->CrtcVDisplay - 3;
 693         regp->unk834 = mode->CrtcVDisplay - 1;
 694
 695         if (pNv->twoHeads)
 696                 /* This is what the blob does */
 697                 regp->unk850 = NVReadCRTC(pNv, 0, NV_CRTC_0850);
 698
 699         /* Never ever modify gpio, unless you know very well what you're doing */
 700         regp->gpio = NVReadCRTC(pNv, 0, NV_CRTC_GPIO);
 701
 702         if (pNv->twoHeads)
 703                 regp->gpio_ext = NVReadCRTC(pNv, 0, NV_CRTC_GPIO_EXT);
 704
 705         regp->config = NV_PCRTC_CONFIG_START_ADDRESS_HSYNC;
 706
 707         /* Some misc regs */
 708         if (pNv->Architecture == NV_ARCH_40) {
 709                 regp->CRTC[NV_CIO_CRE_85] = 0xFF;
 710                 regp->CRTC[NV_CIO_CRE_86] = 0x1;
 711         }
 712
 713         regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (pScrn->depth + 1) / 8;
 714         /* Enable slaved mode */
 715         if (lvds_output || tmds_output)
 716                 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7);
 717
 718         /* Generic PRAMDAC regs */
 719
 720         if (pNv->Architecture >= NV_ARCH_10)
 721                 /* Only bit that bios and blob set. */
 722                 regp->nv10_cursync = (1 << 25);
 723
 724         switch (pScrn->depth) {
 725                 case 24:
 726                 case 15:
 727                         regp->general = 0x00100130;
 728                         break;
 729                 case 16:
 730                 default:
 731                         regp->general = 0x00101130;
 732                         break;
 733         }
 734         if (pNv->alphaCursor)
 735                 /* PIPE_LONG mode, something to do with the size of the cursor? */
 736                 regp->general |= 1 << 29;
 737
 738         regp->unk_630 = 0; /* turn off green mode (tv test pattern?) */
 739
 740         /* Some values the blob sets */
 741         regp->unk_a20 = 0x0;
 742         regp->unk_a24 = 0xfffff;
 743         regp->unk_a34 = 0x1;
 744 }
 745
 746 /* this could be set in nv_output, but would require some rework of load/save */
 747 static void
 748 nv_crtc_mode_set_fp_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
 749 {
 750         ScrnInfoPtr pScrn = crtc->scrn;
 751         NVPtr pNv = NVPTR(pScrn);
 752         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 753         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 754         NVCrtcRegPtr savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
 755         struct nouveau_encoder *nv_encoder = NULL;
 756         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 757         bool is_fp = false;
 758         bool is_lvds = false;
 759         uint32_t mode_ratio, panel_ratio;
 760         int i;
 761
 762         for (i = 0; i < xf86_config->num_output; i++) {
 763                 xf86OutputPtr output = xf86_config->output[i];
 764                 /* assuming one fp output per crtc seems ok */
 765                 nv_encoder = to_nouveau_encoder(output);
 766
 767                 if (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_LVDS)
 768                         is_lvds = true;
 769                 if (is_lvds || (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_TMDS)) {
 770                         is_fp = true;
 771                         break;
 772                 }
 773         }
 774         if (!is_fp)
 775                 return;
 776
 777         regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
 778         regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
 779         if ((adjusted_mode->HSyncStart - adjusted_mode->HDisplay) >= pNv->VBIOS.digital_min_front_porch)
 780                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HDisplay;
 781         else
 782                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HSyncStart - pNv->VBIOS.digital_min_front_porch - 1;
 783         regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
 784         regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
 785         regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
 786         regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
 787
 788         regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
 789         regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
 790         regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VTotal - 5 - 1;
 791         regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
 792         regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
 793         regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
 794         regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
 795
 796         /*
 797         * bit0: positive vsync
 798         * bit4: positive hsync
 799         * bit8: enable center mode
 800         * bit9: enable native mode
 801         * bit24: 12/24 bit interface (12bit=on, 24bit=off)
 802         * bit26: a bit sometimes seen on some g70 cards
 803         * bit28: fp display enable bit
 804         * bit31: set for dual link LVDS
 805         */
 806
 807         regp->fp_control = (savep->fp_control & 0x04100000) |
 808                            NV_RAMDAC_FP_CONTROL_DISPEN_POS;
 809
 810         /* Deal with vsync/hsync polarity */
 811         /* LVDS screens do set this, but modes with +ve syncs are very rare */
 812         if (adjusted_mode->Flags & V_PVSYNC)
 813                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
 814         if (adjusted_mode->Flags & V_PHSYNC)
 815                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
 816
 817         if (nv_encoder->scaling_mode == SCALE_PANEL ||
 818             nv_encoder->scaling_mode == SCALE_NOSCALE) /* panel needs to scale */
 819                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
 820         /* This is also true for panel scaling, so we must put the panel scale check first */
 821         else if (mode->HDisplay == adjusted_mode->HDisplay &&
 822                  mode->VDisplay == adjusted_mode->VDisplay) /* native mode */
 823                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
 824         else /* gpu needs to scale */
 825                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
 826
 827         if (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
 828                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_WIDTH_12;
 829
 830         if (is_lvds && pNv->VBIOS.fp.dual_link)
 831                 regp->fp_control |= (8 << 28);
 832
 833         /* Use the generic value, and enable x-scaling, y-scaling, and the TMDS enable bit */
 834         regp->debug_0 = 0x01101191;
 835         /* We want automatic scaling */
 836         regp->debug_1 = 0;
 837         /* This can override HTOTAL and VTOTAL */
 838         regp->debug_2 = 0;
 839
 840         /* Use 20.12 fixed point format to avoid floats */
 841         mode_ratio = (1 << 12) * mode->HDisplay / mode->VDisplay;
 842         panel_ratio = (1 << 12) * adjusted_mode->HDisplay / adjusted_mode->VDisplay;
 843         /* if ratios are equal, SCALE_ASPECT will automatically (and correctly)
 844          * get treated the same as SCALE_FULLSCREEN */
 845         if (nv_encoder->scaling_mode == SCALE_ASPECT && mode_ratio != panel_ratio) {
 846                 uint32_t diff, scale;
 847
 848                 if (mode_ratio < panel_ratio) {
 849                         /* vertical needs to expand to glass size (automatic)
 850                          * horizontal needs to be scaled at vertical scale factor
 851                          * to maintain aspect */
 852
 853                         scale = (1 << 12) * mode->VDisplay / adjusted_mode->VDisplay;
 854                         regp->debug_1 = 1 << 12 | ((scale >> 1) & 0xfff);
 855
 856                         /* restrict area of screen used, horizontally */
 857                         diff = adjusted_mode->HDisplay -
 858                                adjusted_mode->VDisplay * mode_ratio / (1 << 12);
 859                         regp->fp_horiz_regs[REG_DISP_VALID_START] += diff / 2;
 860                         regp->fp_horiz_regs[REG_DISP_VALID_END] -= diff / 2;
 861                 }
 862
 863                 if (mode_ratio > panel_ratio) {
 864                         /* horizontal needs to expand to glass size (automatic)
 865                          * vertical needs to be scaled at horizontal scale factor
 866                          * to maintain aspect */
 867
 868                         scale = (1 << 12) * mode->HDisplay / adjusted_mode->HDisplay;
 869                         regp->debug_1 = 1 << 28 | ((scale >> 1) & 0xfff) << 16;
 870
 871                         /* restrict area of screen used, vertically */
 872                         diff = adjusted_mode->VDisplay -
 873                                (1 << 12) * adjusted_mode->HDisplay / mode_ratio;
 874                         regp->fp_vert_regs[REG_DISP_VALID_START] += diff / 2;
 875                         regp->fp_vert_regs[REG_DISP_VALID_END] -= diff / 2;
 876                 }
 877         }
 878
 879         /* Flatpanel support needs at least a NV10 */
 880         if (pNv->twoHeads) {
 881                 /* Output property. */
 882                 if (nv_encoder && nv_encoder->dithering) {
 883                         if (pNv->NVArch == 0x11)
 884                                 regp->dither = savep->dither | 0x00010000;
 885                         else {
 886                                 int i;
 887                                 regp->dither = savep->dither | 0x00000001;
 888                                 for (i = 0; i < 3; i++) {
 889                                         regp->dither_regs[i] = 0xe4e4e4e4;
 890                                         regp->dither_regs[i + 3] = 0x44444444;
 891                                 }
 892                         }
 893                 } else {
 894                         if (pNv->NVArch != 0x11) {
 895                                 /* reset them */
 896                                 int i;
 897                                 for (i = 0; i < 3; i++) {
 898                                         regp->dither_regs[i] = savep->dither_regs[i];
 899                                         regp->dither_regs[i + 3] = savep->dither_regs[i + 3];
 900                                 }
 901                         }
 902                         regp->dither = savep->dither;
 903                 }
 904         } else
 905                 regp->dither = savep->dither;
 906 }
 907
 908 /**
 909  * Sets up registers for the given mode/adjusted_mode pair.
 910  *
 911  * The clocks, CRTCs and outputs attached to this CRTC must be off.
 912  *
 913  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
 914  * be easily turned on/off after this.
 915  */
 916 static void
 917 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
 918                  DisplayModePtr adjusted_mode,
 919                  int x, int y)
 920 {
 921         ScrnInfoPtr pScrn = crtc->scrn;
 922         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 923         NVPtr pNv = NVPTR(pScrn);
 924
 925         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CTRC mode on CRTC %d:\n", nv_crtc->head);
 926         xf86PrintModeline(pScrn->scrnIndex, mode);
 927         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Output mode on CRTC %d:\n", nv_crtc->head);
 928         xf86PrintModeline(pScrn->scrnIndex, adjusted_mode);
 929
 930         if (pNv->twoHeads)
 931                 NVSetOwner(pNv, nv_crtc->head);
 932
 933         nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
 934
 935         /* calculated in output_prepare, nv40 needs it written before calculating PLLs */
 936         if (pNv->Architecture == NV_ARCH_40)
 937                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, pNv->ModeReg.sel_clk);
 938         nv_crtc_mode_set_regs(crtc, mode);
 939         nv_crtc_mode_set_fp_regs(crtc, mode, adjusted_mode);
 940         nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->Clock);
 941
 942         NVVgaProtect(pNv, nv_crtc->head, true);
 943         nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
 944         nv_crtc_load_state_ext(crtc, &pNv->ModeReg);
 945         nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
 946         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
 947         nv_crtc_load_state_pll(crtc, &pNv->ModeReg);
 948
 949         NVVgaProtect(pNv, nv_crtc->head, false);
 950
 951         NVCrtcSetBase(crtc, x, y);
 952
 953 #if X_BYTE_ORDER == X_BIG_ENDIAN
 954         /* turn on LFB swapping */
 955         {
 956                 uint8_t tmp = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RCR);
 957                 tmp |= NV_CIO_CRE_RCR_ENDIAN_BIG;
 958                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RCR, tmp);
 959         }
 960 #endif
 961 }
 962
 963 static void nv_crtc_save(xf86CrtcPtr crtc)
 964 {
 965         ScrnInfoPtr pScrn = crtc->scrn;
 966         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 967         NVPtr pNv = NVPTR(pScrn);
 968
 969         /* We just came back from terminal, so unlock */
 970         NVCrtcLockUnlock(crtc, false);
 971
 972         nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
 973         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
 974         nv_crtc_save_state_palette(crtc, &pNv->SavedReg);
 975         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
 976         nv_crtc_save_state_pll(crtc, &pNv->SavedReg);
 977
 978         /* init some state to saved value */
 979         pNv->ModeReg.reg580 = pNv->SavedReg.reg580;
 980         pNv->ModeReg.sel_clk = pNv->SavedReg.sel_clk & ~(0x5 << 16);
 981         pNv->ModeReg.crtc_reg[nv_crtc->head].CRTC[NV_CIO_CRE_LCD__INDEX] = pNv->SavedReg.crtc_reg[nv_crtc->head].CRTC[NV_CIO_CRE_LCD__INDEX];
 982 }
 983
 984 static void nv_crtc_restore(xf86CrtcPtr crtc)
 985 {
 986         ScrnInfoPtr pScrn = crtc->scrn;
 987         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 988         NVPtr pNv = NVPTR(pScrn);
 989         RIVA_HW_STATE *state;
 990         NVCrtcRegPtr savep;
 991
 992         state = &pNv->SavedReg;
 993         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
 994
 995         /* Just to be safe */
 996         NVCrtcLockUnlock(crtc, false);
 997
 998         NVVgaProtect(pNv, nv_crtc->head, true);
 999         nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
1000         nv_crtc_load_state_ext(crtc, &pNv->SavedReg);
1001         nv_crtc_load_state_palette(crtc, &pNv->SavedReg);
1002         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
1003         nv_crtc_load_state_pll(crtc, &pNv->SavedReg);
1004         NVVgaProtect(pNv, nv_crtc->head, false);
1005
1006         nv_crtc->last_dpms = NV_DPMS_CLEARED;
1007 }
1008
1009 static void nv_crtc_prepare(xf86CrtcPtr crtc)
1010 {
1011         ScrnInfoPtr pScrn = crtc->scrn;
1012         NVPtr pNv = NVPTR(pScrn);
1013         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1014
1015         /* Just in case */
1016         NVCrtcLockUnlock(crtc, 0);
1017
1018         crtc->funcs->dpms(crtc, DPMSModeOff);
1019
1020         /* Sync the engine before adjust mode */
1021         if (pNv->EXADriverPtr) {
1022                 exaMarkSync(pScrn->pScreen);
1023                 exaWaitSync(pScrn->pScreen);
1024         }
1025
1026         NVBlankScreen(pNv, nv_crtc->head, true);
1027
1028         /* Some more preperation. */
1029         NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA);
1030         if (pNv->Architecture == NV_ARCH_40) {
1031                 uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
1032                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
1033         }
1034 }
1035
1036 static void nv_crtc_commit(xf86CrtcPtr crtc)
1037 {
1038         crtc->funcs->dpms (crtc, DPMSModeOn);
1039
1040         if (crtc->scrn->pScreen != NULL) {
1041                 NVPtr pNv = NVPTR(crtc->scrn);
1042
1043                 xf86_reload_cursors (crtc->scrn->pScreen);
1044                 if (!pNv->alphaCursor) {
1045                         /* this works round the fact that xf86_reload_cursors
1046                          * will quite happily show the hw cursor when it knows
1047                          * the hardware can't do alpha, and the current cursor
1048                          * has an alpha channel
1049                          */
1050                         xf86ForceHWCursor(crtc->scrn->pScreen, 1);
1051                         xf86ForceHWCursor(crtc->scrn->pScreen, 0);
1052                 }
1053         }
1054 }
1055
1056 static void nv_crtc_destroy(xf86CrtcPtr crtc)
1057 {
1058         xfree(to_nouveau_crtc(crtc));
1059 }
1060
1061 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
1062 {
1063         return FALSE;
1064 }
1065
1066 static void nv_crtc_unlock(xf86CrtcPtr crtc)
1067 {
1068 }
1069
1070 static void
1071 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
1072                                         int size)
1073 {
1074         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1075         ScrnInfoPtr pScrn = crtc->scrn;
1076         NVPtr pNv = NVPTR(pScrn);
1077         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1078         int i, j;
1079
1080         switch (pScrn->depth) {
1081         case 15:
1082                 /* R5G5B5 */
1083                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
1084                 for (i = 0; i < 32; i++)
1085                         for (j = 0; j < 8; j++) {
1086                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1087                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
1088                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1089                         }
1090                 break;
1091         case 16:
1092                 /* R5G6B5 */
1093                 /* First deal with the 5 bit colors */
1094                 for (i = 0; i < 32; i++)
1095                         for (j = 0; j < 8; j++) {
1096                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1097                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1098                         }
1099                 /* Now deal with the 6 bit color */
1100                 for (i = 0; i < 64; i++)
1101                         for (j = 0; j < 4; j++)
1102                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
1103                 break;
1104         default:
1105                 /* R8G8B8 */
1106                 for (i = 0; i < 256; i++) {
1107                         regp->DAC[i * 3] = red[i] >> 8;
1108                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
1109                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
1110                 }
1111                 break;
1112         }
1113
1114         nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
1115 }
1116
1117 /**
1118  * Allocates memory for a locked-in-framebuffer shadow of the given
1119  * width and height for this CRTC's rotated shadow framebuffer.
1120  */
1121
1122 static void *
1123 nv_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
1124 {
1125         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1126         ScrnInfoPtr pScrn = crtc->scrn;
1127 #if !NOUVEAU_EXA_PIXMAPS
1128         ScreenPtr pScreen = pScrn->pScreen;
1129 #endif /* !NOUVEAU_EXA_PIXMAPS */
1130         NVPtr pNv = NVPTR(pScrn);
1131         void *offset;
1132
1133         unsigned long rotate_pitch;
1134         int size, align = 64;
1135
1136         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
1137         size = rotate_pitch * height;
1138
1139         assert(nv_crtc->shadow == NULL);
1140 #if NOUVEAU_EXA_PIXMAPS
1141         if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN,
1142                         align, size, &nv_crtc->shadow)) {
1143                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to allocate memory for shadow buffer!\n");
1144                 return NULL;
1145         }
1146
1147         if (nv_crtc->shadow && nouveau_bo_map(nv_crtc->shadow, NOUVEAU_BO_RDWR)) {
1148                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1149                                 "Failed to map shadow buffer.\n");
1150                 return NULL;
1151         }
1152
1153         offset = nv_crtc->shadow->map;
1154 #else
1155         nv_crtc->shadow = exaOffscreenAlloc(pScreen, size, align, TRUE, NULL, NULL);
1156         if (nv_crtc->shadow == NULL) {
1157                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1158                         "Couldn't allocate shadow memory for rotated CRTC.\n");
1159                 return NULL;
1160         }
1161         offset = pNv->FB->map + nv_crtc->shadow->offset;
1162 #endif /* NOUVEAU_EXA_PIXMAPS */
1163
1164         return offset;
1165 }
1166
1167 /**
1168  * Creates a pixmap for this CRTC's rotated shadow framebuffer.
1169  */
1170 static PixmapPtr
1171 nv_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
1172 {
1173         ScrnInfoPtr pScrn = crtc->scrn;
1174 #if NOUVEAU_EXA_PIXMAPS
1175         ScreenPtr pScreen = pScrn->pScreen;
1176         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1177 #endif /* NOUVEAU_EXA_PIXMAPS */
1178         unsigned long rotate_pitch;
1179         PixmapPtr rotate_pixmap;
1180 #if NOUVEAU_EXA_PIXMAPS
1181         struct nouveau_pixmap *nvpix;
1182 #endif /* NOUVEAU_EXA_PIXMAPS */
1183
1184         if (!data)
1185                 data = crtc->funcs->shadow_allocate (crtc, width, height);
1186
1187         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
1188
1189 #if NOUVEAU_EXA_PIXMAPS
1190         /* Create a dummy pixmap, to get a private that will be accepted by the system.*/
1191         rotate_pixmap = pScreen->CreatePixmap(pScreen,
1192                                                                 0, /* width */
1193                                                                 0, /* height */
1194         #ifdef CREATE_PIXMAP_USAGE_SCRATCH /* there seems to have been no api bump */
1195                                                                 pScrn->depth,
1196                                                                 0);
1197         #else
1198                                                                 pScrn->depth);
1199         #endif /* CREATE_PIXMAP_USAGE_SCRATCH */
1200 #else
1201         rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen,
1202                                                                 width, height,
1203                                                                 pScrn->depth,
1204                                                                 pScrn->bitsPerPixel,
1205                                                                 rotate_pitch,
1206                                                                 data);
1207 #endif /* NOUVEAU_EXA_PIXMAPS */
1208
1209         if (rotate_pixmap == NULL) {
1210                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1211                         "Couldn't allocate shadow pixmap for rotated CRTC\n");
1212         }
1213
1214 #if NOUVEAU_EXA_PIXMAPS
1215         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
1216         if (!nvpix) {
1217                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No initial shadow private available for rotation.\n");
1218         } else {
1219                 nvpix->bo = nv_crtc->shadow;
1220                 nvpix->mapped = TRUE;
1221         }
1222
1223         /* Modify the pixmap to actually be the one we need. */
1224         pScreen->ModifyPixmapHeader(rotate_pixmap,
1225                                         width,
1226                                         height,
1227                                         pScrn->depth,
1228                                         pScrn->bitsPerPixel,
1229                                         rotate_pitch,
1230                                         data);
1231
1232         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
1233         if (!nvpix || !nvpix->bo)
1234                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No final shadow private available for rotation.\n");
1235 #endif /* NOUVEAU_EXA_PIXMAPS */
1236
1237         return rotate_pixmap;
1238 }
1239
1240 static void
1241 nv_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
1242 {
1243         ScrnInfoPtr pScrn = crtc->scrn;
1244         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1245         ScreenPtr pScreen = pScrn->pScreen;
1246
1247         if (rotate_pixmap) { /* This should also unmap the buffer object if relevant. */
1248                 pScreen->DestroyPixmap(rotate_pixmap);
1249         }
1250
1251 #if !NOUVEAU_EXA_PIXMAPS
1252         if (data && nv_crtc->shadow) {
1253                 exaOffscreenFree(pScreen, nv_crtc->shadow);
1254         }
1255 #endif /* !NOUVEAU_EXA_PIXMAPS */
1256
1257         nv_crtc->shadow = NULL;
1258 }
1259
1260 static const xf86CrtcFuncsRec nv_crtc_funcs = {
1261         .dpms = nv_crtc_dpms,
1262         .save = nv_crtc_save,
1263         .restore = nv_crtc_restore,
1264         .mode_fixup = nv_crtc_mode_fixup,
1265         .mode_set = nv_crtc_mode_set,
1266         .prepare = nv_crtc_prepare,
1267         .commit = nv_crtc_commit,
1268         .destroy = nv_crtc_destroy,
1269         .lock = nv_crtc_lock,
1270         .unlock = nv_crtc_unlock,
1271         .set_cursor_colors = NULL, /* Alpha cursors do not need this */
1272         .set_cursor_position = nv_crtc_set_cursor_position,
1273         .show_cursor = nv_crtc_show_cursor,
1274         .hide_cursor = nv_crtc_hide_cursor,
1275         .load_cursor_argb = nv_crtc_load_cursor_argb,
1276         .gamma_set = nv_crtc_gamma_set,
1277         .shadow_create = nv_crtc_shadow_create,
1278         .shadow_allocate = nv_crtc_shadow_allocate,
1279         .shadow_destroy = nv_crtc_shadow_destroy,
1280 };
1281
1282 void
1283 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
1284 {
1285         NVPtr pNv = NVPTR(pScrn);
1286         static xf86CrtcFuncsRec crtcfuncs;
1287         xf86CrtcPtr crtc;
1288         struct nouveau_crtc *nv_crtc;
1289         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[crtc_num];
1290         int i;
1291
1292         crtcfuncs = nv_crtc_funcs;
1293
1294         /* NV04-NV10 doesn't support alpha cursors */
1295         if (pNv->NVArch < 0x11) {
1296                 crtcfuncs.set_cursor_colors = nv_crtc_set_cursor_colors;
1297                 crtcfuncs.load_cursor_image = nv_crtc_load_cursor_image;
1298                 crtcfuncs.load_cursor_argb = NULL;
1299         }
1300         if (pNv->NoAccel) {
1301                 crtcfuncs.shadow_create = NULL;
1302                 crtcfuncs.shadow_allocate = NULL;
1303                 crtcfuncs.shadow_destroy = NULL;
1304         }
1305
1306         if (!(crtc = xf86CrtcCreate(pScrn, &crtcfuncs)))
1307                 return;
1308
1309         if (!(nv_crtc = xcalloc(1, sizeof (struct nouveau_crtc)))) {
1310                 xf86CrtcDestroy(crtc);
1311                 return;
1312         }
1313
1314         nv_crtc->head = crtc_num;
1315         nv_crtc->last_dpms = NV_DPMS_CLEARED;
1316
1317         crtc->driver_private = nv_crtc;
1318
1319         /* Initialise the default LUT table. */
1320         for (i = 0; i < 256; i++) {
1321                 regp->DAC[i*3] = i;
1322                 regp->DAC[(i*3)+1] = i;
1323                 regp->DAC[(i*3)+2] = i;
1324         }
1325
1326         NVCrtcLockUnlock(crtc, false);
1327 }
1328
1329 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1330 {
1331         ScrnInfoPtr pScrn = crtc->scrn;
1332         NVPtr pNv = NVPTR(pScrn);
1333         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1334         int i;
1335         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
1336
1337         NVWritePRMVIO(pNv, nv_crtc->head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg);
1338
1339         for (i = 0; i < 5; i++)
1340                 NVWriteVgaSeq(pNv, nv_crtc->head, i, regp->Sequencer[i]);
1341
1342         for (i = 0; i < 25; i++)
1343                 NVWriteVgaCrtc(pNv, nv_crtc->head, i, regp->CRTC[i]);
1344
1345         for (i = 0; i < 9; i++)
1346                 NVWriteVgaGr(pNv, nv_crtc->head, i, regp->Graphics[i]);
1347
1348         NVSetEnablePalette(pNv, nv_crtc->head, true);
1349         for (i = 0; i < 21; i++)
1350                 NVWriteVgaAttr(pNv, nv_crtc->head, i, regp->Attribute[i]);
1351
1352         NVSetEnablePalette(pNv, nv_crtc->head, false);
1353 }
1354
1355 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1356 {
1357         ScrnInfoPtr pScrn = crtc->scrn;
1358         NVPtr pNv = NVPTR(pScrn);
1359         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1360         NVCrtcRegPtr regp;
1361         int i;
1362
1363         regp = &state->crtc_reg[nv_crtc->head];
1364
1365         if (pNv->Architecture >= NV_ARCH_10) {
1366                 if (pNv->twoHeads)
1367                         /* setting FSEL *must* come before CIO_CRE_LCD, as writing CIO_CRE_LCD sets some
1368                          * bits (16 & 17) in FSEL that should not be overwritten by writing FSEL */
1369                         NVCrtcWriteCRTC(crtc, NV_CRTC_FSEL, regp->head);
1370
1371                 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
1372                 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
1373                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
1374                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
1375                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1376                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1377                 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1378                 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1379                 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, 0);
1380
1381                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_21, regp->CRTC[NV_CIO_CRE_21]);
1382                 NVCrtcWriteCRTC(crtc, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
1383                 NVCrtcWriteCRTC(crtc, NV_CRTC_0830, regp->unk830);
1384                 NVCrtcWriteCRTC(crtc, NV_CRTC_0834, regp->unk834);
1385                 if (pNv->Architecture == NV_ARCH_40) {
1386                         NVCrtcWriteCRTC(crtc, NV_CRTC_0850, regp->unk850);
1387                         NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO_EXT, regp->gpio_ext);
1388                 }
1389
1390                 if (pNv->Architecture == NV_ARCH_40) {
1391                         uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
1392                         if (regp->config == NV_PCRTC_CONFIG_START_ADDRESS_HSYNC)
1393                                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 | 0x10000);
1394                         else
1395                                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
1396                 }
1397         }
1398
1399         NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, regp->config);
1400         NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO, regp->gpio);
1401
1402         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC0_INDEX, regp->CRTC[NV_CIO_CRE_RPC0_INDEX]);
1403         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC1_INDEX, regp->CRTC[NV_CIO_CRE_RPC1_INDEX]);
1404         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_LSR_INDEX, regp->CRTC[NV_CIO_CRE_LSR_INDEX]);
1405         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_PIXEL_INDEX, regp->CRTC[NV_CIO_CRE_PIXEL_INDEX]);
1406         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_LCD__INDEX, regp->CRTC[NV_CIO_CRE_LCD__INDEX]);
1407         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HEB__INDEX, regp->CRTC[NV_CIO_CRE_HEB__INDEX]);
1408         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_ENH_INDEX, regp->CRTC[NV_CIO_CRE_ENH_INDEX]);
1409         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_FF_INDEX, regp->CRTC[NV_CIO_CRE_FF_INDEX]);
1410         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_FFLWM__INDEX, regp->CRTC[NV_CIO_CRE_FFLWM__INDEX]);
1411         if (pNv->Architecture >= NV_ARCH_30)
1412                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_47, regp->CRTC[NV_CIO_CRE_47]);
1413
1414         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR0_INDEX, regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX]);
1415         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR1_INDEX, regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX]);
1416         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR2_INDEX, regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX]);
1417         if (pNv->Architecture == NV_ARCH_40)
1418                 nv_fix_nv40_hw_cursor(pNv, nv_crtc->head);
1419         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_ILACE__INDEX, regp->CRTC[NV_CIO_CRE_ILACE__INDEX]);
1420
1421         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_SCRATCH3__INDEX, regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX]);
1422         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_SCRATCH4__INDEX, regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX]);
1423         if (pNv->Architecture >= NV_ARCH_10) {
1424                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_EBR_INDEX, regp->CRTC[NV_CIO_CRE_EBR_INDEX]);
1425                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_CSB, regp->CRTC[NV_CIO_CRE_CSB]);
1426                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_4B, regp->CRTC[NV_CIO_CRE_4B]);
1427                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_52, regp->CRTC[NV_CIO_CRE_52]);
1428         }
1429         /* NV11 and NV20 stop at 0x52. */
1430         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
1431                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_53, regp->CRTC[NV_CIO_CRE_53]);
1432                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_54, regp->CRTC[NV_CIO_CRE_54]);
1433
1434                 for (i = 0; i < 0x10; i++)
1435                         NVWriteVgaCrtc5758(pNv, nv_crtc->head, i, regp->CR58[i]);
1436                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_59, regp->CRTC[NV_CIO_CRE_59]);
1437
1438                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_85, regp->CRTC[NV_CIO_CRE_85]);
1439                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_86, regp->CRTC[NV_CIO_CRE_86]);
1440         }
1441
1442         NVCrtcWriteCRTC(crtc, NV_CRTC_START, regp->fb_start);
1443
1444         /* Setting 1 on this value gives you interrupts for every vblank period. */
1445         NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_EN_0, 0);
1446         NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
1447 }
1448
1449 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1450 {
1451         ScrnInfoPtr pScrn = crtc->scrn;
1452         NVPtr pNv = NVPTR(pScrn);
1453         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1454         int i;
1455         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
1456
1457         regp->MiscOutReg = NVReadPRMVIO(pNv, nv_crtc->head, NV_PRMVIO_MISC__READ);
1458
1459         for (i = 0; i < 25; i++)
1460                 regp->CRTC[i] = NVReadVgaCrtc(pNv, nv_crtc->head, i);
1461
1462         NVSetEnablePalette(pNv, nv_crtc->head, true);
1463         for (i = 0; i < 21; i++)
1464                 regp->Attribute[i] = NVReadVgaAttr(pNv, nv_crtc->head, i);
1465         NVSetEnablePalette(pNv, nv_crtc->head, false);
1466
1467         for (i = 0; i < 9; i++)
1468                 regp->Graphics[i] = NVReadVgaGr(pNv, nv_crtc->head, i);
1469
1470         for (i = 0; i < 5; i++)
1471                 regp->Sequencer[i] = NVReadVgaSeq(pNv, nv_crtc->head, i);
1472 }
1473
1474 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1475 {
1476         ScrnInfoPtr pScrn = crtc->scrn;
1477         NVPtr pNv = NVPTR(pScrn);
1478         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1479         NVCrtcRegPtr regp;
1480         int i;
1481
1482         regp = &state->crtc_reg[nv_crtc->head];
1483
1484         regp->CRTC[NV_CIO_CRE_LCD__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_LCD__INDEX);
1485         regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC0_INDEX);
1486         regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RPC1_INDEX);
1487         regp->CRTC[NV_CIO_CRE_LSR_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_LSR_INDEX);
1488         regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_PIXEL_INDEX);
1489         regp->CRTC[NV_CIO_CRE_HEB__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HEB__INDEX);
1490         regp->CRTC[NV_CIO_CRE_ENH_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_ENH_INDEX);
1491
1492         regp->CRTC[NV_CIO_CRE_FF_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_FF_INDEX);
1493         regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_FFLWM__INDEX);
1494         regp->CRTC[NV_CIO_CRE_21] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_21);
1495         if (pNv->Architecture >= NV_ARCH_30)
1496                 regp->CRTC[NV_CIO_CRE_47] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_47);
1497         regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR0_INDEX);
1498         regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR1_INDEX);
1499         regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR2_INDEX);
1500         regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_ILACE__INDEX);
1501
1502         if (pNv->Architecture >= NV_ARCH_10) {
1503                 regp->unk830 = NVCrtcReadCRTC(crtc, NV_CRTC_0830);
1504                 regp->unk834 = NVCrtcReadCRTC(crtc, NV_CRTC_0834);
1505                 if (pNv->Architecture == NV_ARCH_40) {
1506                         regp->unk850 = NVCrtcReadCRTC(crtc, NV_CRTC_0850);
1507                         regp->gpio_ext = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO_EXT);
1508                 }
1509                 if (pNv->twoHeads) {
1510                         regp->head = NVCrtcReadCRTC(crtc, NV_CRTC_FSEL);
1511                         regp->crtcOwner = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_44);
1512                 }
1513                 regp->cursorConfig = NVCrtcReadCRTC(crtc, NV_CRTC_CURSOR_CONFIG);
1514         }
1515
1516         regp->gpio = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO);
1517         regp->config = NVCrtcReadCRTC(crtc, NV_CRTC_CONFIG);
1518
1519         regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_SCRATCH3__INDEX);
1520         regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_SCRATCH4__INDEX);
1521         if (pNv->Architecture >= NV_ARCH_10) {
1522                 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_EBR_INDEX);
1523                 regp->CRTC[NV_CIO_CRE_CSB] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_CSB);
1524                 regp->CRTC[NV_CIO_CRE_4B] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_4B);
1525                 regp->CRTC[NV_CIO_CRE_52] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_52);
1526         }
1527         /* NV11 and NV20 don't have this, they stop at 0x52. */
1528         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
1529                 for (i = 0; i < 0x10; i++)
1530                         regp->CR58[i] = NVReadVgaCrtc5758(pNv, nv_crtc->head, i);
1531
1532                 regp->CRTC[NV_CIO_CRE_59] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_59);
1533                 regp->CRTC[NV_CIO_CRE_53] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_53);
1534                 regp->CRTC[NV_CIO_CRE_54] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_54);
1535
1536                 regp->CRTC[NV_CIO_CRE_85] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_85);
1537                 regp->CRTC[NV_CIO_CRE_86] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_86);
1538         }
1539
1540         regp->fb_start = NVCrtcReadCRTC(crtc, NV_CRTC_START);
1541 }
1542
1543 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1544 {
1545         ScrnInfoPtr pScrn = crtc->scrn;
1546         NVPtr pNv = NVPTR(pScrn);
1547         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1548         NVCrtcRegPtr regp;
1549         int i;
1550
1551         regp = &state->crtc_reg[nv_crtc->head];
1552
1553         regp->general = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL);
1554
1555         if (pNv->twoHeads) {
1556                 if (pNv->NVArch >= 0x17)
1557                         regp->unk_630 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_630);
1558                 regp->fp_control        = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_CONTROL);
1559                 regp->debug_0   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_0);
1560                 regp->debug_1   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1);
1561                 regp->debug_2   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2);
1562
1563                 regp->unk_a20 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A20);
1564                 regp->unk_a24 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A24);
1565                 regp->unk_a34 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A34);
1566         }
1567
1568         if (pNv->NVArch == 0x11) {
1569                 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_DITHER_NV11);
1570         } else if (pNv->twoHeads) {
1571                 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DITHER);
1572                 for (i = 0; i < 3; i++) {
1573                         regp->dither_regs[i] = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_850 + i * 4);
1574                         regp->dither_regs[i + 3] = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_85C + i * 4);
1575                 }
1576         }
1577         if (pNv->Architecture >= NV_ARCH_10)
1578                 regp->nv10_cursync = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC);
1579
1580         /* The regs below are 0 for non-flatpanels, so you can load and save them */
1581
1582         for (i = 0; i < 7; i++) {
1583                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
1584                 regp->fp_horiz_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
1585         }
1586
1587         for (i = 0; i < 7; i++) {
1588                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
1589                 regp->fp_vert_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
1590         }
1591 }
1592
1593 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1594 {
1595         ScrnInfoPtr pScrn = crtc->scrn;
1596         NVPtr pNv = NVPTR(pScrn);
1597         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1598         NVCrtcRegPtr regp;
1599         int i;
1600
1601         regp = &state->crtc_reg[nv_crtc->head];
1602
1603         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL, regp->general);
1604
1605         if (pNv->twoHeads) {
1606                 if (pNv->NVArch >= 0x17)
1607                         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_630, regp->unk_630);
1608                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_CONTROL, regp->fp_control);
1609                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_0, regp->debug_0);
1610                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
1611                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
1612                 if (pNv->NVArch == 0x30) { /* For unknown purposes. */
1613                         uint32_t reg890 = NVCrtcReadRAMDAC(crtc, NV30_RAMDAC_890);
1614                         NVCrtcWriteRAMDAC(crtc, NV30_RAMDAC_89C, reg890);
1615                 }
1616
1617                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A20, regp->unk_a20);
1618                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A24, regp->unk_a24);
1619                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A34, regp->unk_a34);
1620         }
1621
1622         if (pNv->NVArch == 0x11)
1623                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_DITHER_NV11, regp->dither);
1624         else if (pNv->twoHeads) {
1625                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DITHER, regp->dither);
1626                 for (i = 0; i < 3; i++) {
1627                         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_850 + i * 4, regp->dither_regs[i]);
1628                         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_85C + i * 4, regp->dither_regs[i + 3]);
1629                 }
1630         }
1631         if (pNv->Architecture >= NV_ARCH_10)
1632                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
1633
1634         /* The regs below are 0 for non-flatpanels, so you can load and save them */
1635
1636         for (i = 0; i < 7; i++) {
1637                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
1638                 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_horiz_regs[i]);
1639         }
1640
1641         for (i = 0; i < 7; i++) {
1642                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
1643                 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_vert_regs[i]);
1644         }
1645 }
1646
1647 void NVCrtcSetBase(xf86CrtcPtr crtc, int x, int y)
1648 {
1649         ScrnInfoPtr pScrn = crtc->scrn;
1650         NVPtr pNv = NVPTR(pScrn);
1651         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1652         uint32_t start = (y * pScrn->displayWidth + x) * pScrn->bitsPerPixel / 8;
1653
1654         if (crtc->rotatedData != NULL) /* we do not exist on the real framebuffer */
1655 #if NOUVEAU_EXA_PIXMAPS
1656                 start = nv_crtc->shadow->offset;
1657 #else
1658                 start = pNv->FB->offset + nv_crtc->shadow->offset; /* We do exist relative to the framebuffer */
1659 #endif
1660         else
1661                 start += pNv->FB->offset;
1662
1663         /* 30 bits addresses in 32 bits according to haiku */
1664         start &= ~3;
1665         pNv->ModeReg.crtc_reg[nv_crtc->head].fb_start = start;
1666         NVCrtcWriteCRTC(crtc, NV_CRTC_START, start);
1667
1668         crtc->x = x;
1669         crtc->y = y;
1670 }
1671
1672 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1673 {
1674         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1675         NVPtr pNv = NVPTR(crtc->scrn);
1676         int head_offset = nv_crtc->head * NV_PRMDIO_SIZE, i;
1677
1678         VGA_WR08(pNv->REGS, NV_PRMDIO_PIXEL_MASK + head_offset, NV_PRMDIO_PIXEL_MASK_MASK);
1679         VGA_WR08(pNv->REGS, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0);
1680
1681         for (i = 0; i < 768; i++) {
1682                 state->crtc_reg[nv_crtc->head].DAC[i] = NV_RD08(pNv->REGS, NV_PRMDIO_PALETTE_DATA + head_offset);
1683                 DDXMMIOH("nv_crtc_save_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, NV_PRMDIO_PALETTE_DATA + head_offset, state->crtc_reg[nv_crtc->head].DAC[i]);
1684         }
1685
1686         NVSetEnablePalette(pNv, nv_crtc->head, false);
1687 }
1688 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1689 {
1690         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1691         NVPtr pNv = NVPTR(crtc->scrn);
1692         int head_offset = nv_crtc->head * NV_PRMDIO_SIZE, i;
1693
1694         VGA_WR08(pNv->REGS, NV_PRMDIO_PIXEL_MASK + head_offset, NV_PRMDIO_PIXEL_MASK_MASK);
1695         VGA_WR08(pNv->REGS, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0);
1696
1697         for (i = 0; i < 768; i++) {
1698                 DDXMMIOH("nv_crtc_load_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, NV_PRMDIO_PALETTE_DATA + head_offset, state->crtc_reg[nv_crtc->head].DAC[i]);
1699                 NV_WR08(pNv->REGS, NV_PRMDIO_PALETTE_DATA + head_offset, state->crtc_reg[nv_crtc->head].DAC[i]);
1700         }
1701
1702         NVSetEnablePalette(pNv, nv_crtc->head, false);
1703 }