1 /* $XConsortium: nvreg.h /main/2 1996/10/28 05:13:41 kaleb $ */
3 * Copyright 1996-1997 David J. McKay
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
19 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
20 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nvreg.h,v 1.6 2002/01/25 21:56:06 tsi Exp $ */
29 #define NV_PMC_OFFSET 0x00000000
30 #define NV_PMC_SIZE 0x00001000
32 #define NV_PBUS_OFFSET 0x00001000
33 #define NV_PBUS_SIZE 0x00001000
35 #define NV_PFIFO_OFFSET 0x00002000
36 #define NV_PFIFO_SIZE 0x00002000
38 #define NV_HDIAG_OFFSET 0x00005000
39 #define NV_HDIAG_SIZE 0x00001000
41 #define NV_PRAM_OFFSET 0x00006000
42 #define NV_PRAM_SIZE 0x00001000
44 #define NV_PVIDEO_OFFSET 0x00008000
45 #define NV_PVIDEO_SIZE 0x00001000
47 #define NV_PTIMER_OFFSET 0x00009000
48 #define NV_PTIMER_SIZE 0x00001000
50 #define NV_PPM_OFFSET 0x0000A000
51 #define NV_PPM_SIZE 0x00001000
53 #define NV_PRMVGA_OFFSET 0x000A0000
54 #define NV_PRMVGA_SIZE 0x00020000
56 #define NV_PRMVIO0_OFFSET 0x000C0000
57 #define NV_PRMVIO_SIZE 0x00002000
58 #define NV_PRMVIO1_OFFSET 0x000C2000
60 #define NV_PFB_OFFSET 0x00100000
61 #define NV_PFB_SIZE 0x00001000
63 #define NV_PEXTDEV_OFFSET 0x00101000
64 #define NV_PEXTDEV_SIZE 0x00001000
66 #define NV_PME_OFFSET 0x00200000
67 #define NV_PME_SIZE 0x00001000
69 #define NV_PROM_OFFSET 0x00300000
70 #define NV_PROM_SIZE 0x00010000
72 #define NV_PGRAPH_OFFSET 0x00400000
73 #define NV_PGRAPH_SIZE 0x00010000
75 #define NV_PCRTC0_OFFSET 0x00600000
76 #define NV_PCRTC0_SIZE 0x00002000 /* empirical */
78 #define NV_PRMCIO0_OFFSET 0x00601000
79 #define NV_PRMCIO_SIZE 0x00002000
80 #define NV_PRMCIO1_OFFSET 0x00603000
82 #define NV50_DISPLAY_OFFSET 0x00610000
83 #define NV50_DISPLAY_SIZE 0x0000FFFF
85 #define NV_PRAMDAC0_OFFSET 0x00680000
86 #define NV_PRAMDAC0_SIZE 0x00002000
88 #define NV_PRMDIO0_OFFSET 0x00681000
89 #define NV_PRMDIO_SIZE 0x00002000
90 #define NV_PRMDIO1_OFFSET 0x00683000
92 #define NV_PRAMIN_OFFSET 0x00700000
93 #define NV_PRAMIN_SIZE 0x00100000
95 #define NV_FIFO_OFFSET 0x00800000
96 #define NV_FIFO_SIZE 0x00800000
98 #define NV_PMC_BOOT_0 0x00000000
99 #define NV_PMC_ENABLE 0x00000200
101 #define NV_VIO_VSE2 0x000003c3
102 #define NV_VIO_SRX 0x000003c4
104 #define NV_CIO_CRX__COLOR 0x000003d4
105 #define NV_CIO_CR__COLOR 0x000003d5
107 #define NV_PBUS_DEBUG_1 0x00001084
108 #define NV_PBUS_DEBUG_4 0x00001098
109 #define NV_PBUS_DEBUG_DUALHEAD_CTL 0x000010f0
110 #define NV_PBUS_POWERCTRL_1 0x00001584
111 #define NV_PBUS_POWERCTRL_2 0x00001588
112 #define NV_PBUS_POWERCTRL_4 0x00001590
113 #define NV_PBUS_PCI_NV_19 0x0000184C
114 #define NV_PBUS_PCI_NV_20 0x00001850
115 # define NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED (0 << 0)
116 # define NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED (1 << 0)
118 #define NV_PFIFO_RAMHT 0x00002210
120 #define NV_PRMVIO_MISC__WRITE 0x000c03c2
121 #define NV_PRMVIO_SRX 0x000c03c4
122 #define NV_PRMVIO_SR 0x000c03c5
123 #define NV_VIO_SR_RESET_INDEX 0x00
124 #define NV_VIO_SR_CLOCK_INDEX 0x01
125 #define NV_VIO_SR_PLANE_MASK_INDEX 0x02
126 #define NV_VIO_SR_CHAR_MAP_INDEX 0x03
127 #define NV_VIO_SR_MEM_MODE_INDEX 0x04
128 #define NV_PRMVIO_MISC__READ 0x000c03cc
129 #define NV_PRMVIO_GRX 0x000c03ce
130 #define NV_PRMVIO_GX 0x000c03cf
131 #define NV_VIO_GX_SR_INDEX 0x00
132 #define NV_VIO_GX_SREN_INDEX 0x01
133 #define NV_VIO_GX_CCOMP_INDEX 0x02
134 #define NV_VIO_GX_ROP_INDEX 0x03
135 #define NV_VIO_GX_READ_MAP_INDEX 0x04
136 #define NV_VIO_GX_MODE_INDEX 0x05
137 #define NV_VIO_GX_MISC_INDEX 0x06
138 #define NV_VIO_GX_DONT_CARE_INDEX 0x07
139 #define NV_VIO_GX_BIT_MASK_INDEX 0x08
141 #define NV_PFB_BOOT_0 0x00100000
142 #define NV_PFB_CFG0 0x00100200
143 #define NV_PFB_CFG1 0x00100204
144 #define NV_PFB_020C 0x0010020C
145 #define NV_PFB_REFCTRL 0x00100210
146 # define NV_PFB_REFCTRL_VALID_1 (1 << 31)
147 #define NV_PFB_PAD 0x0010021C
148 # define NV_PFB_PAD_CKE_NORMAL (1 << 0)
149 #define NV_PFB_TILE_NV10 0x00100240
150 #define NV_PFB_TILE_SIZE_NV10 0x00100244
151 #define NV_PFB_REF 0x001002D0
152 # define NV_PFB_REF_CMD_REFRESH (1 << 0)
153 #define NV_PFB_PRE 0x001002D4
154 # define NV_PFB_PRE_CMD_PRECHARGE (1 << 0)
155 #define NV_PFB_CLOSE_PAGE2 0x0010033C
156 #define NV_PFB_TILE_NV40 0x00100600
157 #define NV_PFB_TILE_SIZE_NV40 0x00100604
159 #define NV_PEXTDEV_BOOT_0 0x00101000
160 # define NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT (1 << 15)
161 #define NV_PEXTDEV_BOOT_3 0x0010100c
163 #define NV_CRTC_INTR_0 0x00600100
164 # define NV_CRTC_INTR_VBLANK (1<<0)
165 #define NV_CRTC_INTR_EN_0 0x00600140
166 #define NV_CRTC_START 0x00600800
167 #define NV_CRTC_CONFIG 0x00600804
168 #define NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA 1
169 #define NV_PCRTC_CONFIG_START_ADDRESS_HSYNC 2
170 #define NV_CRTC_CURSOR_ADDRESS 0x0060080C
171 #define NV_CRTC_CURSOR_CONFIG 0x00600810
172 # define NV_CRTC_CURSOR_CONFIG_ENABLE (1 << 0)
173 # define NV_CRTC_CURSOR_CONFIG_DOUBLE_SCAN (1 << 4)
174 # define NV_CRTC_CURSOR_CONFIG_32BPP (1 << 12)
175 # define NV_CRTC_CURSOR_CONFIG_64PIXELS (1 << 16)
176 # define NV_CRTC_CURSOR_CONFIG_32LINES (1 << 25)
177 # define NV_CRTC_CURSOR_CONFIG_64LINES (1 << 26)
178 # define NV_CRTC_CURSOR_CONFIG_ALPHA_BLEND (1 << 28)
180 #define NV_CRTC_GPIO 0x00600818
181 #define NV_CRTC_GPIO_EXT 0x0060081c
182 #define NV_CRTC_0830 0x00600830
183 #define NV_CRTC_0834 0x00600834
184 #define NV_CRTC_0850 0x00600850
185 #define NV_CRTC_FSEL 0x00600860
186 # define NV_CRTC_FSEL_I2C (1<<4)
187 # define NV_CRTC_FSEL_TVOUT1 (1<<8)
188 # define NV_CRTC_FSEL_TVOUT2 (2<<8)
189 # define NV_CRTC_FSEL_OVERLAY (1<<12)
191 #define NV_PRMCIO_ARX 0x006013c0
192 #define NV_PRMCIO_AR__WRITE 0x006013c0
193 #define NV_PRMCIO_AR__READ 0x006013c1
194 #define NV_CIO_AR_MODE_INDEX 0x10
195 #define NV_CIO_AR_OSCAN_INDEX 0x11
196 #define NV_CIO_AR_PLANE_INDEX 0x12
197 #define NV_CIO_AR_HPP_INDEX 0x13
198 #define NV_CIO_AR_CSEL_INDEX 0x14
199 #define NV_PRMCIO_CRX__COLOR 0x006013d4
200 #define NV_PRMCIO_CR__COLOR 0x006013d5
201 /* Standard VGA CRTC registers */
202 #define NV_CIO_CR_HDT_INDEX 0x00 /* horizontal display total */
203 #define NV_CIO_CR_HDE_INDEX 0x01 /* horizontal display end */
204 #define NV_CIO_CR_HBS_INDEX 0x02 /* horizontal blanking start */
205 #define NV_CIO_CR_HBE_INDEX 0x03 /* horizontal blanking end */
206 #define NV_CIO_CR_HRS_INDEX 0x04 /* horizontal retrace start */
207 #define NV_CIO_CR_HRE_INDEX 0x05 /* horizontal retrace end */
208 #define NV_CIO_CR_VDT_INDEX 0x06 /* vertical display total */
209 #define NV_CIO_CR_OVL_INDEX 0x07 /* overflow bits */
210 #define NV_CIO_CR_RSAL_INDEX 0x08 /* normally "preset row scan" */
211 #define NV_CIO_CR_CELL_HT_INDEX 0x09 /* cell height?! normally "max scan line" */
212 #define NV_CIO_CR_CELL_HT_SCANDBL 0x80
213 #define NV_CIO_CR_CURS_ST_INDEX 0x0a /* cursor start */
214 #define NV_CIO_CR_CURS_END_INDEX 0x0b /* cursor end */
215 #define NV_CIO_CR_SA_HI_INDEX 0x0c /* screen start address high */
216 #define NV_CIO_CR_SA_LO_INDEX 0x0d /* screen start address low */
217 #define NV_CIO_CR_TCOFF_HI_INDEX 0x0e /* cursor offset high */
218 #define NV_CIO_CR_TCOFF_LO_INDEX 0x0f /* cursor offset low */
219 #define NV_CIO_CR_VRS_INDEX 0x10 /* vertical retrace start */
220 #define NV_CIO_CR_VRE_INDEX 0x11 /* vertical retrace end */
221 #define NV_CIO_CR_VDE_INDEX 0x12 /* vertical display end */
222 #define NV_CIO_CR_OFFSET_INDEX 0x13 /* sets screen pitch */
223 #define NV_CIO_CR_ULINE_INDEX 0x14 /* underline location */
224 #define NV_CIO_CR_VBS_INDEX 0x15 /* vertical blank start */
225 #define NV_CIO_CR_VBE_INDEX 0x16 /* vertical blank end */
226 #define NV_CIO_CR_MODE_INDEX 0x17 /* crtc mode control */
227 #define NV_CIO_CR_LCOMP_INDEX 0x18 /* line compare */
228 /* Extended VGA CRTC registers */
229 #define NV_CIO_CRE_RPC0_INDEX 0x19 /* repaint control 0 */
230 #define NV_CIO_CRE_RPC1_INDEX 0x1a /* repaint control 1 */
231 #define NV_CIO_CRE_FF_INDEX 0x1b /* fifo control */
232 #define NV_CIO_CRE_ENH_INDEX 0x1c /* enhanced? */
233 #define NV_CIO_SR_LOCK_INDEX 0x1f /* crtc lock */
234 #define NV_CIO_SR_UNLOCK_RW_VALUE 0x57
235 #define NV_CIO_SR_LOCK_VALUE 0x99
236 #define NV_CIO_CRE_FFLWM__INDEX 0x20 /* fifo low water mark */
237 #define NV_CIO_CRE_21 0x21 /* referred to by some .scp as `shadow lock' */
238 #define NV_CIO_CRE_LSR_INDEX 0x25 /* ? */
239 #define NV_CIO_CR_ARX_INDEX 0x26 /* attribute index -- ro copy of 0x60.3c0 */
240 #define NV_CIO_CRE_CHIP_ID_INDEX 0x27 /* chip revision */
241 #define NV_CIO_CRE_PIXEL_INDEX 0x28
242 #define NV_CIO_CRE_HEB__INDEX 0x2d /* horizontal extra bits? */
243 #define NV_CIO_CRE_HCUR_ADDR2_INDEX 0x2f /* cursor */
244 #define NV_CIO_CRE_HCUR_ADDR0_INDEX 0x30 /* pixmap */
245 #define NV_CIO_CRE_HCUR_ASI 0x80
246 #define NV_CIO_CRE_HCUR_ADDR1_INDEX 0x31 /* address */
247 #define NV_CIO_CRE_HCUR_ADDR1_CUR_DBL 0x02
248 #define NV_CIO_CRE_HCUR_ADDR1_ENABLE 0x01
249 #define NV_CIO_CRE_LCD__INDEX 0x33
250 #define NV_CIO_CRE_LCD_LCD_SELECT 0x01
251 #define NV_CIO_CRE_DDC0_STATUS__INDEX 0x36
252 #define NV_CIO_CRE_DDC0_WR__INDEX 0x37
253 #define NV_CIO_CRE_ILACE__INDEX 0x39 /* interlace */
254 #define NV_CIO_CRE_SCRATCH3__INDEX 0x3b
255 #define NV_CIO_CRE_SCRATCH4__INDEX 0x3c
256 #define NV_CIO_CRE_DDC_STATUS__INDEX 0x3e
257 #define NV_CIO_CRE_DDC_WR__INDEX 0x3f
258 #define NV_CIO_CRE_EBR_INDEX 0x41 /* extra bits ? (vertical) */
259 #define NV_CIO_CRE_44 0x44 /* head control */
260 #define NV_CIO_CRE_CSB 0x45
261 #define NV_CIO_CRE_RCR 0x46
262 #define NV_CIO_CRE_RCR_ENDIAN_BIG 0x80;
263 #define NV_CIO_CRE_47 0x47 /* extended fifo lwm, used on nv30+ */
264 #define NV_CIO_CRE_4B 0x4b /* given patterns in 0x[2-3][a-c] regs, probably scratch 6 */
265 #define NV_CIO_CRE_52 0x52
266 #define NV_CIO_CRE_53 0x53 /* `fp_htiming' according to Haiku */
267 #define NV_CIO_CRE_54 0x54 /* `fp_vtiming' according to Haiku */
268 #define NV_CIO_CRE_57 0x57 /* index reg for cr58 */
269 #define NV_CIO_CRE_58 0x58 /* data reg for cr57 */
270 #define NV_CIO_CRE_59 0x59
271 #define NV_CIO_CRE_85 0x85
272 #define NV_CIO_CRE_86 0x86
273 #define NV_PRMCIO_INP0__COLOR 0x006013da
275 #define NV_RAMDAC_CURSOR_POS 0x00680300
276 #define NV_RAMDAC_CURSOR_CTRL 0x00680320
277 #define NV_RAMDAC_CURSOR_DATA_LO 0x00680324
278 #define NV_RAMDAC_CURSOR_DATA_HI 0x00680328
279 #define NV_RAMDAC_NV10_CURSYNC 0x00680404
281 #define NV_RAMDAC_NVPLL 0x00680500
282 #define NV_RAMDAC_MPLL 0x00680504
283 #define NV_RAMDAC_VPLL 0x00680508
284 # define NV_RAMDAC_PLL_COEFF_MDIV 0x000000FF
285 # define NV_RAMDAC_PLL_COEFF_NDIV 0x0000FF00
286 # define NV_RAMDAC_PLL_COEFF_PDIV 0x00070000
287 # define NV30_RAMDAC_ENABLE_VCO2 (1 << 7)
289 #define NV_RAMDAC_PLL_SELECT 0x0068050c
290 /* Without this it will use vpll1 */
291 /* Maybe only for nv4x */
292 # define NV_RAMDAC_PLL_SELECT_USE_VPLL2_FALSE (0<<2)
293 # define NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE (1<<2)
294 # define NV_RAMDAC_PLL_SELECT_DLL_BYPASS (1<<4)
295 # define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_DEFAULT (0<<8)
296 # define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL (1<<8)
297 # define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL (2<<8)
298 # define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL (4<<8)
299 # define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL (7<<8)
300 # define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2 (8<<8)
301 # define NV_RAMDAC_PLL_SELECT_MPLL_BYPASS_FALSE (0<<12)
302 # define NV_RAMDAC_PLL_SELECT_MPLL_BYPASS_TRUE (1<<12)
303 # define NV_RAMDAC_PLL_SELECT_VS_PCLK_TV_NONE (0<<16)
304 # define NV_RAMDAC_PLL_SELECT_VS_PCLK_TV_VSCLK (1<<16)
305 # define NV_RAMDAC_PLL_SELECT_VS_PCLK_TV_PCLK (2<<16)
306 # define NV_RAMDAC_PLL_SELECT_VS_PCLK_TV_BOTH (3<<16)
307 # define NV_RAMDAC_PLL_SELECT_TVCLK_SOURCE_EXT (0<<20)
308 # define NV_RAMDAC_PLL_SELECT_TVCLK_SOURCE_VIP (1<<20)
309 # define NV_RAMDAC_PLL_SELECT_TVCLK_RATIO_DB1 (0<<24)
310 # define NV_RAMDAC_PLL_SELECT_TVCLK_RATIO_DB2 (1<<24)
311 # define NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB1 (0<<28)
312 # define NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 (1<<28)
313 # define NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB1 (0<<29)
314 # define NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2 (1<<29)
316 #define NV_RAMDAC_PLL_SETUP_CONTROL 0x00680510
317 #define NV_RAMDAC_PLL_TEST_COUNTER 0x00680514
318 #define NV_RAMDAC_PALETTE_TEST 0x00680518
319 #define NV_RAMDAC_VPLL2 0x00680520
320 #define NV_RAMDAC_SEL_CLK 0x00680524
321 #define NV_RAMDAC_DITHER_NV11 0x00680528
322 #define NV_RAMDAC_OUTPUT 0x0068052c
323 # define NV_RAMDAC_OUTPUT_DAC_ENABLE (1<<0)
324 # define NV_RAMDAC_OUTPUT_SELECT_CRTC1 (1<<8)
326 #define NV_RAMDAC_NVPLL_B 0x00680570
327 #define NV_RAMDAC_MPLL_B 0x00680574
328 #define NV_RAMDAC_VPLL_B 0x00680578
329 #define NV_RAMDAC_VPLL2_B 0x0068057c
330 /* Educated guess, should remain on for NV4x vpll's. */
331 # define NV31_RAMDAC_ENABLE_VCO2 (1 << 31)
333 #define NV_RAMDAC_580 0x00680580
334 /* This is not always activated, but only when VCLK_RATIO_DB1 is used */
335 # define NV_RAMDAC_580_VPLL1_ACTIVE (1<<8)
336 # define NV_RAMDAC_580_VPLL2_ACTIVE (1<<28)
338 #define NV_RAMDAC_594 0x00680594
339 #define NV_RAMDAC_GENERAL_CONTROL 0x00680600
340 #define NV_RAMDAC_TEST_CONTROL 0x00680608
341 #define NV_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED (1 << 12)
342 #define NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF (1 << 16)
343 #define NV_PRAMDAC_TEST_CONTROL_SENSEB_ALLHI (1 << 28)
344 #define NV_RAMDAC_TEST_DATA 0x00680610
345 #define NV_PRAMDAC_TESTPOINT_DATA_NOTBLANK (1 << 31)
346 #define NV_RAMDAC_630 0x00680630
347 /* This register is similar to TEST_CONTROL in the style of values */
348 #define NV_RAMDAC_670 0x00680670
350 #define NV_RAMDAC_TV_SETUP 0x00680700
351 #define NV_RAMDAC_TV_VBLANK_START 0x00680704
352 #define NV_RAMDAC_TV_VBLANK_END 0x00680708
353 #define NV_RAMDAC_TV_HBLANK_START 0x0068070c
354 #define NV_RAMDAC_TV_HBLANK_END 0x00680710
355 #define NV_RAMDAC_TV_BLANK_COLOR 0x00680714
356 #define NV_RAMDAC_TV_VTOTAL 0x00680720
357 #define NV_RAMDAC_TV_VSYNC_START 0x00680724
358 #define NV_RAMDAC_TV_VSYNC_END 0x00680728
359 #define NV_RAMDAC_TV_HTOTAL 0x0068072c
360 #define NV_RAMDAC_TV_HSYNC_START 0x00680730
361 #define NV_RAMDAC_TV_HSYNC_END 0x00680734
362 #define NV_RAMDAC_TV_SYNC_DELAY 0x00680738
364 #define REG_DISP_END 0
365 #define REG_DISP_TOTAL 1
366 #define REG_DISP_CRTC 2
367 #define REG_DISP_SYNC_START 3
368 #define REG_DISP_SYNC_END 4
369 #define REG_DISP_VALID_START 5
370 #define REG_DISP_VALID_END 6
372 #define NV_RAMDAC_FP_VDISP_END 0x00680800
373 #define NV_RAMDAC_FP_VTOTAL 0x00680804
374 #define NV_RAMDAC_FP_VCRTC 0x00680808
375 #define NV_RAMDAC_FP_VSYNC_START 0x0068080c
376 #define NV_RAMDAC_FP_VSYNC_END 0x00680810
377 #define NV_RAMDAC_FP_VVALID_START 0x00680814
378 #define NV_RAMDAC_FP_VVALID_END 0x00680818
379 #define NV_RAMDAC_FP_HDISP_END 0x00680820
380 #define NV_RAMDAC_FP_HTOTAL 0x00680824
381 #define NV_RAMDAC_FP_HCRTC 0x00680828
382 #define NV_RAMDAC_FP_HSYNC_START 0x0068082c
383 #define NV_RAMDAC_FP_HSYNC_END 0x00680830
384 #define NV_RAMDAC_FP_HVALID_START 0x00680834
385 #define NV_RAMDAC_FP_HVALID_END 0x00680838
387 #define NV_RAMDAC_FP_DITHER 0x0068083c
388 #define NV_RAMDAC_FP_CHECKSUM 0x00680840
389 #define NV_RAMDAC_FP_TEST_CONTROL 0x00680844
390 #define NV_RAMDAC_FP_CONTROL 0x00680848
391 # define NV_RAMDAC_FP_CONTROL_VSYNC_NEG (0 << 0)
392 # define NV_RAMDAC_FP_CONTROL_VSYNC_POS (1 << 0)
393 # define NV_RAMDAC_FP_CONTROL_VSYNC_DISABLE (2 << 0)
394 # define NV_RAMDAC_FP_CONTROL_HSYNC_NEG (0 << 4)
395 # define NV_RAMDAC_FP_CONTROL_HSYNC_POS (1 << 4)
396 # define NV_RAMDAC_FP_CONTROL_HSYNC_DISABLE (2 << 4)
397 # define NV_RAMDAC_FP_CONTROL_MODE_SCALE (0 << 8)
398 # define NV_RAMDAC_FP_CONTROL_MODE_CENTER (1 << 8)
399 # define NV_RAMDAC_FP_CONTROL_MODE_NATIVE (2 << 8)
400 # define NV_RAMDAC_FP_CONTROL_WIDTH_12 (1 << 24)
401 # define NV_RAMDAC_FP_CONTROL_DISPEN_POS (1 << 28)
402 # define NV_RAMDAC_FP_CONTROL_DISPEN_DISABLE (2 << 28)
403 #define NV_PRAMDAC_FP_TG_CONTROL_OFF (NV_RAMDAC_FP_CONTROL_DISPEN_DISABLE | \
404 NV_RAMDAC_FP_CONTROL_HSYNC_DISABLE | \
405 NV_RAMDAC_FP_CONTROL_VSYNC_DISABLE)
406 #define NV_RAMDAC_FP_850 0x00680850
407 #define NV_RAMDAC_FP_85C 0x0068085c
409 #define NV_RAMDAC_FP_DEBUG_0 0x00680880
410 # define NV_RAMDAC_FP_DEBUG_0_XSCALE_ENABLED (1 << 0)
411 # define NV_RAMDAC_FP_DEBUG_0_YSCALE_ENABLED (1 << 4)
412 /* This doesn't seem to be essential for tmds, but still often set */
413 # define NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED (1 << 7)
414 # define NV_RAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK (1 << 28)
415 # define NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL (2 << 28)
416 # define NV_RAMDAC_FP_DEBUG_0_PWRDOWN_BOTH (3 << 28)
417 #define NV_RAMDAC_FP_DEBUG_1 0x00680884
418 #define NV_RAMDAC_FP_DEBUG_2 0x00680888
419 #define NV_RAMDAC_FP_DEBUG_3 0x0068088C
421 /* Some unknown regs, purely for NV30 it seems. */
422 #define NV30_RAMDAC_890 0x00680890
423 #define NV30_RAMDAC_894 0x00680894
424 #define NV30_RAMDAC_89C 0x0068089C
426 /* see NV_PRAMDAC_INDIR_TMDS in rules.xml */
427 #define NV_RAMDAC_FP_TMDS_CONTROL 0x006808b0
428 # define NV_RAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE (1<<16)
429 #define NV_RAMDAC_FP_TMDS_DATA 0x006808b4
430 #define NV_RAMDAC_FP_TMDS_CONTROL_2 0x006808b8
431 # define NV_RAMDAC_FP_TMDS_CONTROL_2_WRITE_DISABLE (1<<16)
432 #define NV_RAMDAC_FP_TMDS_DATA_2 0x006808bc
434 /* Some kind of switch */
435 #define NV_RAMDAC_900 0x00680900
436 #define NV_RAMDAC_A20 0x00680A20
437 #define NV_RAMDAC_A24 0x00680A24
438 #define NV_RAMDAC_A34 0x00680A34
440 /* names fabricated from NV_USER_DAC info */
441 #define NV_PRMDIO_PIXEL_MASK 0x006813c6
442 #define NV_PRMDIO_PIXEL_MASK_MASK 0xff
443 #define NV_PRMDIO_READ_MODE_ADDRESS 0x006813c7
444 #define NV_PRMDIO_WRITE_MODE_ADDRESS 0x006813c8
445 #define NV_PRMDIO_PALETTE_DATA 0x006813c9
447 #define NV_PGRAPH_DEBUG_0 0x00400080
448 #define NV_PGRAPH_DEBUG_1 0x00400084
449 #define NV_PGRAPH_DEBUG_2_NV04 0x00400088
450 #define NV_PGRAPH_DEBUG_2 0x00400620
451 #define NV_PGRAPH_DEBUG_3 0x0040008c
452 #define NV_PGRAPH_DEBUG_4 0x00400090
453 #define NV_PGRAPH_INTR 0x00400100
454 #define NV_PGRAPH_INTR_EN 0x00400140
455 #define NV_PGRAPH_CTX_CONTROL 0x00400144
456 #define NV_PGRAPH_CTX_CONTROL_NV04 0x00400170
457 #define NV_PGRAPH_ABS_UCLIP_XMIN 0x0040053C
458 #define NV_PGRAPH_ABS_UCLIP_YMIN 0x00400540
459 #define NV_PGRAPH_ABS_UCLIP_XMAX 0x00400544
460 #define NV_PGRAPH_ABS_UCLIP_YMAX 0x00400548
461 #define NV_PGRAPH_BETA_AND 0x00400608
462 #define NV_PGRAPH_LIMIT_VIOL_PIX 0x00400610
463 #define NV_PGRAPH_BOFFSET0 0x00400640
464 #define NV_PGRAPH_BOFFSET1 0x00400644
465 #define NV_PGRAPH_BOFFSET2 0x00400648
466 #define NV_PGRAPH_BLIMIT0 0x00400684
467 #define NV_PGRAPH_BLIMIT1 0x00400688
468 #define NV_PGRAPH_BLIMIT2 0x0040068c
469 #define NV_PGRAPH_STATUS 0x00400700
470 #define NV_PGRAPH_SURFACE 0x00400710
471 #define NV_PGRAPH_STATE 0x00400714
472 #define NV_PGRAPH_FIFO 0x00400720
473 #define NV_PGRAPH_PATTERN_SHAPE 0x00400810
474 #define NV_PGRAPH_TILE 0x00400b00
476 #define NV_PVIDEO_INTR_EN 0x00008140
477 #define NV_PVIDEO_BUFFER 0x00008700
478 #define NV_PVIDEO_STOP 0x00008704
479 #define NV_PVIDEO_UVPLANE_BASE(buff) (0x00008800+(buff)*4)
480 #define NV_PVIDEO_UVPLANE_LIMIT(buff) (0x00008808+(buff)*4)
481 #define NV_PVIDEO_UVPLANE_OFFSET_BUFF(buff) (0x00008820+(buff)*4)
482 #define NV_PVIDEO_BASE(buff) (0x00008900+(buff)*4)
483 #define NV_PVIDEO_LIMIT(buff) (0x00008908+(buff)*4)
484 #define NV_PVIDEO_LUMINANCE(buff) (0x00008910+(buff)*4)
485 #define NV_PVIDEO_CHROMINANCE(buff) (0x00008918+(buff)*4)
486 #define NV_PVIDEO_OFFSET_BUFF(buff) (0x00008920+(buff)*4)
487 #define NV_PVIDEO_SIZE_IN(buff) (0x00008928+(buff)*4)
488 #define NV_PVIDEO_POINT_IN(buff) (0x00008930+(buff)*4)
489 #define NV_PVIDEO_DS_DX(buff) (0x00008938+(buff)*4)
490 #define NV_PVIDEO_DT_DY(buff) (0x00008940+(buff)*4)
491 #define NV_PVIDEO_POINT_OUT(buff) (0x00008948+(buff)*4)
492 #define NV_PVIDEO_SIZE_OUT(buff) (0x00008950+(buff)*4)
493 #define NV_PVIDEO_FORMAT(buff) (0x00008958+(buff)*4)
494 # define NV_PVIDEO_FORMAT_PLANAR (1 << 0)
495 # define NV_PVIDEO_FORMAT_COLOR_LE_CR8YB8CB8YA8 (1 << 16)
496 # define NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY (1 << 20)
497 # define NV_PVIDEO_FORMAT_MATRIX_ITURBT709 (1 << 24)
498 #define NV_PVIDEO_COLOR_KEY 0x00008B00
500 /* NV04 overlay defines from VIDIX & Haiku */
501 #define NV_PVIDEO_INTR_EN_0 0x00680140
502 #define NV_PVIDEO_STEP_SIZE 0x00680200
503 #define NV_PVIDEO_CONTROL_Y 0x00680204
504 #define NV_PVIDEO_CONTROL_X 0x00680208
505 #define NV_PVIDEO_BUFF0_START_ADDRESS 0x0068020c
506 #define NV_PVIDEO_BUFF0_PITCH_LENGTH 0x00680214
507 #define NV_PVIDEO_BUFF0_OFFSET 0x0068021c
508 #define NV_PVIDEO_BUFF1_START_ADDRESS 0x00680210
509 #define NV_PVIDEO_BUFF1_PITCH_LENGTH 0x00680218
510 #define NV_PVIDEO_BUFF1_OFFSET 0x00680220
511 #define NV_PVIDEO_OE_STATE 0x00680224
512 #define NV_PVIDEO_SU_STATE 0x00680228
513 #define NV_PVIDEO_RM_STATE 0x0068022c
514 #define NV_PVIDEO_WINDOW_START 0x00680230
515 #define NV_PVIDEO_WINDOW_SIZE 0x00680234
516 #define NV_PVIDEO_FIFO_THRES_SIZE 0x00680238
517 #define NV_PVIDEO_FIFO_BURST_LENGTH 0x0068023c
518 #define NV_PVIDEO_KEY 0x00680240
519 #define NV_PVIDEO_OVERLAY 0x00680244
520 #define NV_PVIDEO_RED_CSC_OFFSET 0x00680280
521 #define NV_PVIDEO_GREEN_CSC_OFFSET 0x00680284
522 #define NV_PVIDEO_BLUE_CSC_OFFSET 0x00680288
523 #define NV_PVIDEO_CSC_ADJUST 0x0068028c
525 /* These are the real registers, not the redirected ones */
526 #define NV40_VCLK1_A 0x4010
527 #define NV40_VCLK1_B 0x4014
528 #define NV40_VCLK2_A 0x4018
529 #define NV40_VCLK2_B 0x401c