git.oblomov.eu Git - nouveau/blob - src/nv_hw.c

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   2 |*                                                                           *|
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  37 |*                                                                           *|
  38  \***************************************************************************/
  39 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_hw.c,v 1.16 2005/09/14 02:28:03 mvojkovi Exp $ */
  40
  41 #ifdef HAVE_CONFIG_H
  42 #include "config.h"
  43 #endif
  44
  45 #include "nv_local.h"
  46 #include "compiler.h"
  47 #include "nv_include.h"
  48
  49
  50 void NVLockUnlock (
  51     NVPtr pNv,
  52     Bool  Lock
  53 )
  54 {
  55     CARD8 cr11;
  56
  57     VGA_WR08(pNv->PCIO, 0x3D4, 0x1F);
  58     VGA_WR08(pNv->PCIO, 0x3D5, Lock ? 0x99 : 0x57);
  59
  60     VGA_WR08(pNv->PCIO, 0x3D4, 0x11);
  61     cr11 = VGA_RD08(pNv->PCIO, 0x3D5);
  62     if(Lock) cr11 |= 0x80;
  63     else cr11 &= ~0x80;
  64     VGA_WR08(pNv->PCIO, 0x3D5, cr11);
  65 }
  66
  67 int NVShowHideCursor (
  68     NVPtr pNv,
  69     int   ShowHide
  70 )
  71 {
  72     int current = pNv->CurrentState->cursor1;
  73
  74     pNv->CurrentState->cursor1 = (pNv->CurrentState->cursor1 & 0xFE) |
  75                                  (ShowHide & 0x01);
  76     VGA_WR08(pNv->PCIO, 0x3D4, 0x31);
  77     VGA_WR08(pNv->PCIO, 0x3D5, pNv->CurrentState->cursor1);
  78
  79     if(pNv->Architecture == NV_ARCH_40) {  /* HW bug */
  80        volatile CARD32 curpos = pNv->PRAMDAC[0x0300/4];
  81        pNv->PRAMDAC[0x0300/4] = curpos;
  82     }
  83
  84     return (current & 0x01);
  85 }
  86
  87 /****************************************************************************\
  88 *                                                                            *
  89 * The video arbitration routines calculate some "magic" numbers.  Fixes      *
  90 * the snow seen when accessing the framebuffer without it.                   *
  91 * It just works (I hope).                                                    *
  92 *                                                                            *
  93 \****************************************************************************/
  94
  95 typedef struct {
  96   int graphics_lwm;
  97   int video_lwm;
  98   int graphics_burst_size;
  99   int video_burst_size;
 100   int valid;
 101 } nv4_fifo_info;
 102
 103 typedef struct {
 104   int pclk_khz;
 105   int mclk_khz;
 106   int nvclk_khz;
 107   char mem_page_miss;
 108   char mem_latency;
 109   int memory_width;
 110   char enable_video;
 111   char gr_during_vid;
 112   char pix_bpp;
 113   char mem_aligned;
 114   char enable_mp;
 115 } nv4_sim_state;
 116
 117 typedef struct {
 118   int graphics_lwm;
 119   int video_lwm;
 120   int graphics_burst_size;
 121   int video_burst_size;
 122   int valid;
 123 } nv10_fifo_info;
 124
 125 typedef struct {
 126   int pclk_khz;
 127   int mclk_khz;
 128   int nvclk_khz;
 129   char mem_page_miss;
 130   char mem_latency;
 131   int memory_type;
 132   int memory_width;
 133   char enable_video;
 134   char gr_during_vid;
 135   char pix_bpp;
 136   char mem_aligned;
 137   char enable_mp;
 138 } nv10_sim_state;
 139
 140
 141 static void nvGetClocks(NVPtr pNv, unsigned int *MClk, unsigned int *NVClk)
 142 {
 143     unsigned int pll, N, M, MB, NB, P;
 144
 145     if(pNv->Architecture >= NV_ARCH_40) {
 146        pll = pNv->PMC[0x4020/4];
 147        P = (pll >> 16) & 0x03;
 148        pll = pNv->PMC[0x4024/4];
 149        M = pll & 0xFF;
 150        N = (pll >> 8) & 0xFF;
 151        MB = (pll >> 16) & 0xFF;
 152        NB = (pll >> 24) & 0xFF;
 153        *MClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
 154
 155        pll = pNv->PMC[0x4000/4];
 156        P = (pll >> 16) & 0x03;
 157        pll = pNv->PMC[0x4004/4];
 158        M = pll & 0xFF;
 159        N = (pll >> 8) & 0xFF;
 160        MB = (pll >> 16) & 0xFF;
 161        NB = (pll >> 24) & 0xFF;
 162
 163        *NVClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
 164     } else
 165     if(pNv->twoStagePLL) {
 166        pll = pNv->PRAMDAC0[0x0504/4];
 167        M = pll & 0xFF;
 168        N = (pll >> 8) & 0xFF;
 169        P = (pll >> 16) & 0x0F;
 170        pll = pNv->PRAMDAC0[0x0574/4];
 171        if(pll & 0x80000000) {
 172            MB = pll & 0xFF;
 173            NB = (pll >> 8) & 0xFF;
 174        } else {
 175            MB = 1;
 176            NB = 1;
 177        }
 178        *MClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
 179
 180        pll = pNv->PRAMDAC0[0x0500/4];
 181        M = pll & 0xFF;
 182        N = (pll >> 8) & 0xFF;
 183        P = (pll >> 16) & 0x0F;
 184        pll = pNv->PRAMDAC0[0x0570/4];
 185        if(pll & 0x80000000) {
 186            MB = pll & 0xFF;
 187            NB = (pll >> 8) & 0xFF;
 188        } else {
 189            MB = 1;
 190            NB = 1;
 191        }
 192        *NVClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
 193     } else
 194     if(((pNv->Chipset & 0x0ff0) == 0x0300) ||
 195        ((pNv->Chipset & 0x0ff0) == 0x0330))
 196     {
 197        pll = pNv->PRAMDAC0[0x0504/4];
 198        M = pll & 0x0F;
 199        N = (pll >> 8) & 0xFF;
 200        P = (pll >> 16) & 0x07;
 201        if(pll & 0x00000080) {
 202            MB = (pll >> 4) & 0x07;
 203            NB = (pll >> 19) & 0x1f;
 204        } else {
 205            MB = 1;
 206            NB = 1;
 207        }
 208        *MClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
 209
 210        pll = pNv->PRAMDAC0[0x0500/4];
 211        M = pll & 0x0F;
 212        N = (pll >> 8) & 0xFF;
 213        P = (pll >> 16) & 0x07;
 214        if(pll & 0x00000080) {
 215            MB = (pll >> 4) & 0x07;
 216            NB = (pll >> 19) & 0x1f;
 217        } else {
 218            MB = 1;
 219            NB = 1;
 220        }
 221        *NVClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
 222     } else {
 223        pll = pNv->PRAMDAC0[0x0504/4];
 224        M = pll & 0xFF;
 225        N = (pll >> 8) & 0xFF;
 226        P = (pll >> 16) & 0x0F;
 227        *MClk = (N * pNv->CrystalFreqKHz / M) >> P;
 228
 229        pll = pNv->PRAMDAC0[0x0500/4];
 230        M = pll & 0xFF;
 231        N = (pll >> 8) & 0xFF;
 232        P = (pll >> 16) & 0x0F;
 233        *NVClk = (N * pNv->CrystalFreqKHz / M) >> P;
 234     }
 235
 236 #if 0
 237     ErrorF("NVClock = %i MHz, MEMClock = %i MHz\n", *NVClk/1000, *MClk/1000);
 238 #endif
 239 }
 240
 241
 242 static void nv4CalcArbitration (
 243     nv4_fifo_info *fifo,
 244     nv4_sim_state *arb
 245 )
 246 {
 247     int data, pagemiss, cas,width, video_enable, bpp;
 248     int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
 249     int found, mclk_extra, mclk_loop, cbs, m1, p1;
 250     int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
 251     int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate;
 252     int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt,clwm;
 253
 254     fifo->valid = 1;
 255     pclk_freq = arb->pclk_khz;
 256     mclk_freq = arb->mclk_khz;
 257     nvclk_freq = arb->nvclk_khz;
 258     pagemiss = arb->mem_page_miss;
 259     cas = arb->mem_latency;
 260     width = arb->memory_width >> 6;
 261     video_enable = arb->enable_video;
 262     bpp = arb->pix_bpp;
 263     mp_enable = arb->enable_mp;
 264     clwm = 0;
 265     vlwm = 0;
 266     cbs = 128;
 267     pclks = 2;
 268     nvclks = 2;
 269     nvclks += 2;
 270     nvclks += 1;
 271     mclks = 5;
 272     mclks += 3;
 273     mclks += 1;
 274     mclks += cas;
 275     mclks += 1;
 276     mclks += 1;
 277     mclks += 1;
 278     mclks += 1;
 279     mclk_extra = 3;
 280     nvclks += 2;
 281     nvclks += 1;
 282     nvclks += 1;
 283     nvclks += 1;
 284     if (mp_enable)
 285         mclks+=4;
 286     nvclks += 0;
 287     pclks += 0;
 288     found = 0;
 289     vbs = 0;
 290     while (found != 1)
 291     {
 292         fifo->valid = 1;
 293         found = 1;
 294         mclk_loop = mclks+mclk_extra;
 295         us_m = mclk_loop *1000*1000 / mclk_freq;
 296         us_n = nvclks*1000*1000 / nvclk_freq;
 297         us_p = nvclks*1000*1000 / pclk_freq;
 298         if (video_enable)
 299         {
 300             video_drain_rate = pclk_freq * 2;
 301             crtc_drain_rate = pclk_freq * bpp/8;
 302             vpagemiss = 2;
 303             vpagemiss += 1;
 304             crtpagemiss = 2;
 305             vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq;
 306             if (nvclk_freq * 2 > mclk_freq * width)
 307                 video_fill_us = cbs*1000*1000 / 16 / nvclk_freq ;
 308             else
 309                 video_fill_us = cbs*1000*1000 / (8 * width) / mclk_freq;
 310             us_video = vpm_us + us_m + us_n + us_p + video_fill_us;
 311             vlwm = us_video * video_drain_rate/(1000*1000);
 312             vlwm++;
 313             vbs = 128;
 314             if (vlwm > 128) vbs = 64;
 315             if (vlwm > (256-64)) vbs = 32;
 316             if (nvclk_freq * 2 > mclk_freq * width)
 317                 video_fill_us = vbs *1000*1000/ 16 / nvclk_freq ;
 318             else
 319                 video_fill_us = vbs*1000*1000 / (8 * width) / mclk_freq;
 320             cpm_us = crtpagemiss  * pagemiss *1000*1000/ mclk_freq;
 321             us_crt =
 322             us_video
 323             +video_fill_us
 324             +cpm_us
 325             +us_m + us_n +us_p
 326             ;
 327             clwm = us_crt * crtc_drain_rate/(1000*1000);
 328             clwm++;
 329         }
 330         else
 331         {
 332             crtc_drain_rate = pclk_freq * bpp/8;
 333             crtpagemiss = 2;
 334             crtpagemiss += 1;
 335             cpm_us = crtpagemiss  * pagemiss *1000*1000/ mclk_freq;
 336             us_crt =  cpm_us + us_m + us_n + us_p ;
 337             clwm = us_crt * crtc_drain_rate/(1000*1000);
 338             clwm++;
 339         }
 340         m1 = clwm + cbs - 512;
 341         p1 = m1 * pclk_freq / mclk_freq;
 342         p1 = p1 * bpp / 8;
 343         if ((p1 < m1) && (m1 > 0))
 344         {
 345             fifo->valid = 0;
 346             found = 0;
 347             if (mclk_extra ==0)   found = 1;
 348             mclk_extra--;
 349         }
 350         else if (video_enable)
 351         {
 352             if ((clwm > 511) || (vlwm > 255))
 353             {
 354                 fifo->valid = 0;
 355                 found = 0;
 356                 if (mclk_extra ==0)   found = 1;
 357                 mclk_extra--;
 358             }
 359         }
 360         else
 361         {
 362             if (clwm > 519)
 363             {
 364                 fifo->valid = 0;
 365                 found = 0;
 366                 if (mclk_extra ==0)   found = 1;
 367                 mclk_extra--;
 368             }
 369         }
 370         if (clwm < 384) clwm = 384;
 371         if (vlwm < 128) vlwm = 128;
 372         data = (int)(clwm);
 373         fifo->graphics_lwm = data;
 374         fifo->graphics_burst_size = 128;
 375         data = (int)((vlwm+15));
 376         fifo->video_lwm = data;
 377         fifo->video_burst_size = vbs;
 378     }
 379 }
 380
 381 static void nv4UpdateArbitrationSettings (
 382     unsigned      VClk,
 383     unsigned      pixelDepth,
 384     unsigned     *burst,
 385     unsigned     *lwm,
 386     NVPtr        pNv
 387 )
 388 {
 389     nv4_fifo_info fifo_data;
 390     nv4_sim_state sim_data;
 391     unsigned int MClk, NVClk, cfg1;
 392
 393     nvGetClocks(pNv, &MClk, &NVClk);
 394
 395     cfg1 = pNv->PFB[0x00000204/4];
 396     sim_data.pix_bpp        = (char)pixelDepth;
 397     sim_data.enable_video   = 0;
 398     sim_data.enable_mp      = 0;
 399     sim_data.memory_width   = (pNv->PEXTDEV[0x0000/4] & 0x10) ? 128 : 64;
 400     sim_data.mem_latency    = (char)cfg1 & 0x0F;
 401     sim_data.mem_aligned    = 1;
 402     sim_data.mem_page_miss  = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01));
 403     sim_data.gr_during_vid  = 0;
 404     sim_data.pclk_khz       = VClk;
 405     sim_data.mclk_khz       = MClk;
 406     sim_data.nvclk_khz      = NVClk;
 407     nv4CalcArbitration(&fifo_data, &sim_data);
 408     if (fifo_data.valid)
 409     {
 410         int  b = fifo_data.graphics_burst_size >> 4;
 411         *burst = 0;
 412         while (b >>= 1) (*burst)++;
 413         *lwm   = fifo_data.graphics_lwm >> 3;
 414     }
 415 }
 416
 417 static void nv10CalcArbitration (
 418     nv10_fifo_info *fifo,
 419     nv10_sim_state *arb
 420 )
 421 {
 422     int data, pagemiss, width, video_enable, bpp;
 423     int nvclks, mclks, pclks, vpagemiss, crtpagemiss;
 424     int nvclk_fill;
 425     int found, mclk_extra, mclk_loop, cbs, m1;
 426     int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
 427     int us_m, us_m_min, us_n, us_p, crtc_drain_rate;
 428     int vus_m;
 429     int vpm_us, us_video, cpm_us, us_crt,clwm;
 430     int clwm_rnd_down;
 431     int m2us, us_pipe_min, p1clk, p2;
 432     int min_mclk_extra;
 433     int us_min_mclk_extra;
 434
 435     fifo->valid = 1;
 436     pclk_freq = arb->pclk_khz; /* freq in KHz */
 437     mclk_freq = arb->mclk_khz;
 438     nvclk_freq = arb->nvclk_khz;
 439     pagemiss = arb->mem_page_miss;
 440     width = arb->memory_width/64;
 441     video_enable = arb->enable_video;
 442     bpp = arb->pix_bpp;
 443     mp_enable = arb->enable_mp;
 444     clwm = 0;
 445
 446     cbs = 512;
 447
 448     pclks = 4; /* lwm detect. */
 449
 450     nvclks = 3; /* lwm -> sync. */
 451     nvclks += 2; /* fbi bus cycles (1 req + 1 busy) */
 452
 453     mclks  = 1;   /* 2 edge sync.  may be very close to edge so just put one. */
 454
 455     mclks += 1;   /* arb_hp_req */
 456     mclks += 5;   /* ap_hp_req   tiling pipeline */
 457
 458     mclks += 2;    /* tc_req     latency fifo */
 459     mclks += 2;    /* fb_cas_n_  memory request to fbio block */
 460     mclks += 7;    /* sm_d_rdv   data returned from fbio block */
 461
 462     /* fb.rd.d.Put_gc   need to accumulate 256 bits for read */
 463     if (arb->memory_type == 0)
 464       if (arb->memory_width == 64) /* 64 bit bus */
 465         mclks += 4;
 466       else
 467         mclks += 2;
 468     else
 469       if (arb->memory_width == 64) /* 64 bit bus */
 470         mclks += 2;
 471       else
 472         mclks += 1;
 473
 474     if ((!video_enable) && (arb->memory_width == 128))
 475     {
 476       mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */
 477       min_mclk_extra = 17;
 478     }
 479     else
 480     {
 481       mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */
 482       /* mclk_extra = 4; */ /* Margin of error */
 483       min_mclk_extra = 18;
 484     }
 485
 486     nvclks += 1; /* 2 edge sync.  may be very close to edge so just put one. */
 487     nvclks += 1; /* fbi_d_rdv_n */
 488     nvclks += 1; /* Fbi_d_rdata */
 489     nvclks += 1; /* crtfifo load */
 490
 491     if(mp_enable)
 492       mclks+=4; /* Mp can get in with a burst of 8. */
 493     /* Extra clocks determined by heuristics */
 494
 495     nvclks += 0;
 496     pclks += 0;
 497     found = 0;
 498     while(found != 1) {
 499       fifo->valid = 1;
 500       found = 1;
 501       mclk_loop = mclks+mclk_extra;
 502       us_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */
 503       us_m_min = mclks * 1000*1000 / mclk_freq; /* Minimum Mclk latency in us */
 504       us_min_mclk_extra = min_mclk_extra *1000*1000 / mclk_freq;
 505       us_n = nvclks*1000*1000 / nvclk_freq;/* nvclk latency in us */
 506       us_p = pclks*1000*1000 / pclk_freq;/* nvclk latency in us */
 507       us_pipe_min = us_m_min + us_n + us_p;
 508
 509       vus_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */
 510
 511       if(video_enable) {
 512         crtc_drain_rate = pclk_freq * bpp/8; /* MB/s */
 513
 514         vpagemiss = 1; /* self generating page miss */
 515         vpagemiss += 1; /* One higher priority before */
 516
 517         crtpagemiss = 2; /* self generating page miss */
 518         if(mp_enable)
 519             crtpagemiss += 1; /* if MA0 conflict */
 520
 521         vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq;
 522
 523         us_video = vpm_us + vus_m; /* Video has separate read return path */
 524
 525         cpm_us = crtpagemiss  * pagemiss *1000*1000/ mclk_freq;
 526         us_crt =
 527           us_video  /* Wait for video */
 528           +cpm_us /* CRT Page miss */
 529           +us_m + us_n +us_p /* other latency */
 530           ;
 531
 532         clwm = us_crt * crtc_drain_rate/(1000*1000);
 533         clwm++; /* fixed point <= float_point - 1.  Fixes that */
 534       } else {
 535         crtc_drain_rate = pclk_freq * bpp/8; /* bpp * pclk/8 */
 536
 537         crtpagemiss = 1; /* self generating page miss */
 538         crtpagemiss += 1; /* MA0 page miss */
 539         if(mp_enable)
 540             crtpagemiss += 1; /* if MA0 conflict */
 541         cpm_us = crtpagemiss  * pagemiss *1000*1000/ mclk_freq;
 542         us_crt =  cpm_us + us_m + us_n + us_p ;
 543         clwm = us_crt * crtc_drain_rate/(1000*1000);
 544         clwm++; /* fixed point <= float_point - 1.  Fixes that */
 545
 546           /* Finally, a heuristic check when width == 64 bits */
 547           if(width == 1){
 548               nvclk_fill = nvclk_freq * 8;
 549               if(crtc_drain_rate * 100 >= nvclk_fill * 102)
 550                       clwm = 0xfff; /*Large number to fail */
 551
 552               else if(crtc_drain_rate * 100  >= nvclk_fill * 98) {
 553                   clwm = 1024;
 554                   cbs = 512;
 555               }
 556           }
 557       }
 558
 559
 560       /*
 561         Overfill check:
 562
 563         */
 564
 565       clwm_rnd_down = ((int)clwm/8)*8;
 566       if (clwm_rnd_down < clwm)
 567           clwm += 8;
 568
 569       m1 = clwm + cbs -  1024; /* Amount of overfill */
 570       m2us = us_pipe_min + us_min_mclk_extra;
 571
 572       /* pclk cycles to drain */
 573       p1clk = m2us * pclk_freq/(1000*1000);
 574       p2 = p1clk * bpp / 8; /* bytes drained. */
 575
 576       if((p2 < m1) && (m1 > 0)) {
 577           fifo->valid = 0;
 578           found = 0;
 579           if(min_mclk_extra == 0)   {
 580             if(cbs <= 32) {
 581               found = 1; /* Can't adjust anymore! */
 582             } else {
 583               cbs = cbs/2;  /* reduce the burst size */
 584             }
 585           } else {
 586             min_mclk_extra--;
 587           }
 588       } else {
 589         if (clwm > 1023){ /* Have some margin */
 590           fifo->valid = 0;
 591           found = 0;
 592           if(min_mclk_extra == 0)
 593               found = 1; /* Can't adjust anymore! */
 594           else
 595               min_mclk_extra--;
 596         }
 597       }
 598
 599       if(clwm < (1024-cbs+8)) clwm = 1024-cbs+8;
 600       data = (int)(clwm);
 601       /*  printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n", clwm, data ); */
 602       fifo->graphics_lwm = data;   fifo->graphics_burst_size = cbs;
 603
 604       fifo->video_lwm = 1024;  fifo->video_burst_size = 512;
 605     }
 606 }
 607
 608 static void nv10UpdateArbitrationSettings (
 609     unsigned      VClk,
 610     unsigned      pixelDepth,
 611     unsigned     *burst,
 612     unsigned     *lwm,
 613     NVPtr        pNv
 614 )
 615 {
 616     nv10_fifo_info fifo_data;
 617     nv10_sim_state sim_data;
 618     unsigned int MClk, NVClk, cfg1;
 619
 620     nvGetClocks(pNv, &MClk, &NVClk);
 621
 622     cfg1 = pNv->PFB[0x0204/4];
 623     sim_data.pix_bpp        = (char)pixelDepth;
 624     sim_data.enable_video   = 1;
 625     sim_data.enable_mp      = 0;
 626     sim_data.memory_type    = (pNv->PFB[0x0200/4] & 0x01) ? 1 : 0;
 627     sim_data.memory_width   = (pNv->PEXTDEV[0x0000/4] & 0x10) ? 128 : 64;
 628     sim_data.mem_latency    = (char)cfg1 & 0x0F;
 629     sim_data.mem_aligned    = 1;
 630     sim_data.mem_page_miss  = (char)(((cfg1>>4) &0x0F) + ((cfg1>>31) & 0x01));
 631     sim_data.gr_during_vid  = 0;
 632     sim_data.pclk_khz       = VClk;
 633     sim_data.mclk_khz       = MClk;
 634     sim_data.nvclk_khz      = NVClk;
 635     nv10CalcArbitration(&fifo_data, &sim_data);
 636     if (fifo_data.valid) {
 637         int  b = fifo_data.graphics_burst_size >> 4;
 638         *burst = 0;
 639         while (b >>= 1) (*burst)++;
 640         *lwm   = fifo_data.graphics_lwm >> 3;
 641     }
 642 }
 643
 644
 645 static void nv30UpdateArbitrationSettings (
 646     NVPtr        pNv,
 647     unsigned     *burst,
 648     unsigned     *lwm
 649 )
 650 {
 651     unsigned int MClk, NVClk;
 652     unsigned int fifo_size, burst_size, graphics_lwm;
 653
 654     fifo_size = 2048;
 655     burst_size = 512;
 656     graphics_lwm = fifo_size - burst_size;
 657
 658     nvGetClocks(pNv, &MClk, &NVClk);
 659
 660     *burst = 0;
 661     burst_size >>= 5;
 662     while(burst_size >>= 1) (*burst)++;
 663     *lwm = graphics_lwm >> 3;
 664 }
 665
 666 static void nForceUpdateArbitrationSettings (
 667     unsigned      VClk,
 668     unsigned      pixelDepth,
 669     unsigned     *burst,
 670     unsigned     *lwm,
 671     NVPtr        pNv
 672 )
 673 {
 674     nv10_fifo_info fifo_data;
 675     nv10_sim_state sim_data;
 676     unsigned int M, N, P, pll, MClk, NVClk, memctrl;
 677
 678     if((pNv->Chipset & 0x0FF0) == 0x01A0) {
 679        unsigned int uMClkPostDiv;
 680
 681        uMClkPostDiv = (pciReadLong(pciTag(0, 0, 3), 0x6C) >> 8) & 0xf;
 682        if(!uMClkPostDiv) uMClkPostDiv = 4;
 683        MClk = 400000 / uMClkPostDiv;
 684     } else {
 685        MClk = pciReadLong(pciTag(0, 0, 5), 0x4C) / 1000;
 686     }
 687
 688     pll = pNv->PRAMDAC0[0x0500/4];
 689     M = (pll >> 0)  & 0xFF; N = (pll >> 8)  & 0xFF; P = (pll >> 16) & 0x0F;
 690     NVClk  = (N * pNv->CrystalFreqKHz / M) >> P;
 691     sim_data.pix_bpp        = (char)pixelDepth;
 692     sim_data.enable_video   = 0;
 693     sim_data.enable_mp      = 0;
 694     sim_data.memory_type    = (pciReadLong(pciTag(0, 0, 1), 0x7C) >> 12) & 1;
 695     sim_data.memory_width   = 64;
 696
 697     memctrl = pciReadLong(pciTag(0, 0, 3), 0x00) >> 16;
 698
 699     if((memctrl == 0x1A9) || (memctrl == 0x1AB) || (memctrl == 0x1ED)) {
 700         int dimm[3];
 701
 702         dimm[0] = (pciReadLong(pciTag(0, 0, 2), 0x40) >> 8) & 0x4F;
 703         dimm[1] = (pciReadLong(pciTag(0, 0, 2), 0x44) >> 8) & 0x4F;
 704         dimm[2] = (pciReadLong(pciTag(0, 0, 2), 0x48) >> 8) & 0x4F;
 705
 706         if((dimm[0] + dimm[1]) != dimm[2]) {
 707              ErrorF("WARNING: "
 708               "your nForce DIMMs are not arranged in optimal banks!\n");
 709         }
 710     }
 711
 712     sim_data.mem_latency    = 3;
 713     sim_data.mem_aligned    = 1;
 714     sim_data.mem_page_miss  = 10;
 715     sim_data.gr_during_vid  = 0;
 716     sim_data.pclk_khz       = VClk;
 717     sim_data.mclk_khz       = MClk;
 718     sim_data.nvclk_khz      = NVClk;
 719     nv10CalcArbitration(&fifo_data, &sim_data);
 720     if (fifo_data.valid)
 721     {
 722         int  b = fifo_data.graphics_burst_size >> 4;
 723         *burst = 0;
 724         while (b >>= 1) (*burst)++;
 725         *lwm   = fifo_data.graphics_lwm >> 3;
 726     }
 727 }
 728
 729
 730 /****************************************************************************\
 731 *                                                                            *
 732 *                          RIVA Mode State Routines                          *
 733 *                                                                            *
 734 \****************************************************************************/
 735
 736 /*
 737  * Calculate the Video Clock parameters for the PLL.
 738  */
 739 static void CalcVClock (
 740     int           clockIn,
 741     int          *clockOut,
 742     U032         *pllOut,
 743     NVPtr        pNv
 744 )
 745 {
 746     unsigned lowM, highM;
 747     unsigned DeltaNew, DeltaOld;
 748     unsigned VClk, Freq;
 749     unsigned M, N, P;
 750
 751     DeltaOld = 0xFFFFFFFF;
 752
 753     VClk = (unsigned)clockIn;
 754
 755     if (pNv->CrystalFreqKHz == 13500) {
 756         lowM  = 7;
 757         highM = 13;
 758     } else {
 759         lowM  = 8;
 760         highM = 14;
 761     }
 762
 763     for (P = 0; P <= 4; P++) {
 764         Freq = VClk << P;
 765         if ((Freq >= 128000) && (Freq <= 350000)) {
 766             for (M = lowM; M <= highM; M++) {
 767                 N = ((VClk << P) * M) / pNv->CrystalFreqKHz;
 768                 if(N <= 255) {
 769                     Freq = ((pNv->CrystalFreqKHz * N) / M) >> P;
 770                     if (Freq > VClk)
 771                         DeltaNew = Freq - VClk;
 772                     else
 773                         DeltaNew = VClk - Freq;
 774                     if (DeltaNew < DeltaOld) {
 775                         *pllOut   = (P << 16) | (N << 8) | M;
 776                         *clockOut = Freq;
 777                         DeltaOld  = DeltaNew;
 778                     }
 779                 }
 780             }
 781         }
 782     }
 783 }
 784
 785 static void CalcVClock2Stage (
 786     int           clockIn,
 787     int          *clockOut,
 788     U032         *pllOut,
 789     U032         *pllBOut,
 790     NVPtr        pNv
 791 )
 792 {
 793     unsigned DeltaNew, DeltaOld;
 794     unsigned VClk, Freq;
 795     unsigned M, N, P;
 796
 797     DeltaOld = 0xFFFFFFFF;
 798
 799     *pllBOut = 0x80000401;  /* fixed at x4 for now */
 800
 801     VClk = (unsigned)clockIn;
 802
 803     for (P = 0; P <= 6; P++) {
 804         Freq = VClk << P;
 805         if ((Freq >= 400000) && (Freq <= 1000000)) {
 806             for (M = 1; M <= 13; M++) {
 807                 N = ((VClk << P) * M) / (pNv->CrystalFreqKHz << 2);
 808                 if((N >= 5) && (N <= 255)) {
 809                     Freq = (((pNv->CrystalFreqKHz << 2) * N) / M) >> P;
 810                     if (Freq > VClk)
 811                         DeltaNew = Freq - VClk;
 812                     else
 813                         DeltaNew = VClk - Freq;
 814                     if (DeltaNew < DeltaOld) {
 815                         *pllOut   = (P << 16) | (N << 8) | M;
 816                         *clockOut = Freq;
 817                         DeltaOld  = DeltaNew;
 818                     }
 819                 }
 820             }
 821         }
 822     }
 823 }
 824
 825 /*
 826  * Calculate extended mode parameters (SVGA) and save in a
 827  * mode state structure.
 828  */
 829 void NVCalcStateExt (
 830     NVPtr pNv,
 831     RIVA_HW_STATE *state,
 832     int            bpp,
 833     int            width,
 834     int            hDisplaySize,
 835     int            height,
 836     int            dotClock,
 837     int            flags
 838 )
 839 {
 840     int pixelDepth, VClk;
 841     /*
 842      * Save mode parameters.
 843      */
 844     state->bpp    = bpp;    /* this is not bitsPerPixel, it's 8,15,16,32 */
 845     state->width  = width;
 846     state->height = height;
 847     /*
 848      * Extended RIVA registers.
 849      */
 850     pixelDepth = (bpp + 1)/8;
 851     if(pNv->twoStagePLL)
 852         CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB, pNv);
 853     else
 854         CalcVClock(dotClock, &VClk, &state->pll, pNv);
 855
 856     switch (pNv->Architecture)
 857     {
 858         case NV_ARCH_04:
 859             nv4UpdateArbitrationSettings(VClk,
 860                                          pixelDepth * 8,
 861                                         &(state->arbitration0),
 862                                         &(state->arbitration1),
 863                                          pNv);
 864             state->cursor0  = 0x00;
 865             state->cursor1  = 0xbC;
 866             if (flags & V_DBLSCAN)
 867                 state->cursor1 |= 2;
 868             state->cursor2  = 0x00000000;
 869             state->pllsel   = 0x10000700;
 870             state->config   = 0x00001114;
 871             state->general  = bpp == 16 ? 0x00101100 : 0x00100100;
 872             state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
 873             break;
 874         case NV_ARCH_10:
 875         case NV_ARCH_20:
 876         case NV_ARCH_30:
 877         default:
 878             if(((pNv->Chipset & 0xffff) == 0x01A0) ||
 879                ((pNv->Chipset & 0xffff) == 0x01f0))
 880             {
 881                 nForceUpdateArbitrationSettings(VClk,
 882                                           pixelDepth * 8,
 883                                          &(state->arbitration0),
 884                                          &(state->arbitration1),
 885                                           pNv);
 886             } else if(pNv->Architecture < NV_ARCH_30) {
 887                 nv10UpdateArbitrationSettings(VClk,
 888                                           pixelDepth * 8,
 889                                          &(state->arbitration0),
 890                                          &(state->arbitration1),
 891                                           pNv);
 892             } else {
 893                 nv30UpdateArbitrationSettings(pNv,
 894                                          &(state->arbitration0),
 895                                          &(state->arbitration1));
 896             }
 897             state->cursor0  = 0x80 | (pNv->CursorStart >> 17);
 898             state->cursor1  = (pNv->CursorStart >> 11) << 2;
 899             state->cursor2  = pNv->CursorStart >> 24;
 900             if (flags & V_DBLSCAN)
 901                 state->cursor1 |= 2;
 902             state->pllsel   = 0x10000700;
 903             state->config   = pNv->PFB[0x00000200/4];
 904             state->general  = bpp == 16 ? 0x00101100 : 0x00100100;
 905             state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
 906             break;
 907     }
 908
 909     if(bpp != 8) /* DirectColor */
 910         state->general |= 0x00000030;
 911
 912     state->repaint0 = (((width / 8) * pixelDepth) & 0x700) >> 3;
 913     state->pixel    = (pixelDepth > 2) ? 3 : pixelDepth;
 914 }
 915
 916
 917 void NVLoadStateExt (
 918     NVPtr pNv,
 919     RIVA_HW_STATE *state
 920 )
 921 {
 922     int i;
 923
 924     pNv->PMC[0x0140/4] = 0x00000000;
 925     pNv->PMC[0x0200/4] = 0xFFFF00FF;
 926     pNv->PMC[0x0200/4] = 0xFFFFFFFF;
 927
 928     pNv->PTIMER[0x0200] = 0x00000008;
 929     pNv->PTIMER[0x0210] = 0x00000003;
 930     pNv->PTIMER[0x0140] = 0x00000000;
 931     pNv->PTIMER[0x0100] = 0xFFFFFFFF;
 932
 933     if(pNv->Architecture == NV_ARCH_04) {
 934         pNv->PFB[0x0200/4] = state->config;
 935     } else
 936     if((pNv->Architecture < NV_ARCH_40) ||
 937        ((pNv->Chipset & 0xfff0) == 0x0040))
 938     {
 939         for(i = 0; i < 8; i++) {
 940            pNv->PFB[(0x0240 + (i * 0x10))/4] = 0;
 941            pNv->PFB[(0x0244 + (i * 0x10))/4] = pNv->FbMapSize - 1;
 942         }
 943     } else {
 944         int regions = 12;
 945
 946         if(((pNv->Chipset & 0xfff0) == 0x0090) ||
 947            ((pNv->Chipset & 0xfff0) == 0x01D0) ||
 948            ((pNv->Chipset & 0xfff0) == 0x0290))
 949         {
 950            regions = 15;
 951         }
 952
 953        for(i = 0; i < regions; i++) {
 954           pNv->PFB[(0x0600 + (i * 0x10))/4] = 0;
 955           pNv->PFB[(0x0604 + (i * 0x10))/4] = pNv->FbMapSize - 1;
 956        }
 957     }
 958
 959     if(pNv->Architecture >= NV_ARCH_40) {
 960        pNv->PRAMIN[0x0000] = 0x80000010;
 961        pNv->PRAMIN[0x0001] = 0x00101202;
 962        pNv->PRAMIN[0x0002] = 0x80000011;
 963        pNv->PRAMIN[0x0003] = 0x00101204;
 964        pNv->PRAMIN[0x0004] = 0x80000012;
 965        pNv->PRAMIN[0x0005] = 0x00101206;
 966        pNv->PRAMIN[0x0006] = 0x80000013;
 967        pNv->PRAMIN[0x0007] = 0x00101208;
 968        pNv->PRAMIN[0x0008] = 0x80000014;
 969        pNv->PRAMIN[0x0009] = 0x0010120A;
 970        pNv->PRAMIN[0x000A] = 0x80000015;
 971        pNv->PRAMIN[0x000B] = 0x0010120C;
 972        pNv->PRAMIN[0x000C] = 0x80000016;
 973        pNv->PRAMIN[0x000D] = 0x0010120E;
 974        pNv->PRAMIN[0x000E] = 0x80000017;
 975        pNv->PRAMIN[0x000F] = 0x00101210;
 976        pNv->PRAMIN[0x0800] = 0x00003000;
 977        pNv->PRAMIN[0x0801] = pNv->FbMapSize - 1;
 978        pNv->PRAMIN[0x0802] = 0x00000002;
 979        pNv->PRAMIN[0x0808] = 0x02080062;
 980        pNv->PRAMIN[0x0809] = 0x00000000;
 981        pNv->PRAMIN[0x080A] = 0x00001200;
 982        pNv->PRAMIN[0x080B] = 0x00001200;
 983        pNv->PRAMIN[0x080C] = 0x00000000;
 984        pNv->PRAMIN[0x080D] = 0x00000000;
 985        pNv->PRAMIN[0x0810] = 0x02080043;
 986        pNv->PRAMIN[0x0811] = 0x00000000;
 987        pNv->PRAMIN[0x0812] = 0x00000000;
 988        pNv->PRAMIN[0x0813] = 0x00000000;
 989        pNv->PRAMIN[0x0814] = 0x00000000;
 990        pNv->PRAMIN[0x0815] = 0x00000000;
 991        pNv->PRAMIN[0x0818] = 0x02080044;
 992        pNv->PRAMIN[0x0819] = 0x02000000;
 993        pNv->PRAMIN[0x081A] = 0x00000000;
 994        pNv->PRAMIN[0x081B] = 0x00000000;
 995        pNv->PRAMIN[0x081C] = 0x00000000;
 996        pNv->PRAMIN[0x081D] = 0x00000000;
 997        pNv->PRAMIN[0x0820] = 0x02080019;
 998        pNv->PRAMIN[0x0821] = 0x00000000;
 999        pNv->PRAMIN[0x0822] = 0x00000000;
1000        pNv->PRAMIN[0x0823] = 0x00000000;
1001        pNv->PRAMIN[0x0824] = 0x00000000;
1002        pNv->PRAMIN[0x0825] = 0x00000000;
1003        pNv->PRAMIN[0x0828] = 0x020A005C;
1004        pNv->PRAMIN[0x0829] = 0x00000000;
1005        pNv->PRAMIN[0x082A] = 0x00000000;
1006        pNv->PRAMIN[0x082B] = 0x00000000;
1007        pNv->PRAMIN[0x082C] = 0x00000000;
1008        pNv->PRAMIN[0x082D] = 0x00000000;
1009        pNv->PRAMIN[0x0830] = 0x0208009F;
1010        pNv->PRAMIN[0x0831] = 0x00000000;
1011        pNv->PRAMIN[0x0832] = 0x00001200;
1012        pNv->PRAMIN[0x0833] = 0x00001200;
1013        pNv->PRAMIN[0x0834] = 0x00000000;
1014        pNv->PRAMIN[0x0835] = 0x00000000;
1015        pNv->PRAMIN[0x0838] = 0x0208004A;
1016        pNv->PRAMIN[0x0839] = 0x02000000;
1017        pNv->PRAMIN[0x083A] = 0x00000000;
1018        pNv->PRAMIN[0x083B] = 0x00000000;
1019        pNv->PRAMIN[0x083C] = 0x00000000;
1020        pNv->PRAMIN[0x083D] = 0x00000000;
1021        pNv->PRAMIN[0x0840] = 0x02080077;
1022        pNv->PRAMIN[0x0841] = 0x00000000;
1023        pNv->PRAMIN[0x0842] = 0x00001200;
1024        pNv->PRAMIN[0x0843] = 0x00001200;
1025        pNv->PRAMIN[0x0844] = 0x00000000;
1026        pNv->PRAMIN[0x0845] = 0x00000000;
1027        pNv->PRAMIN[0x084C] = 0x00003002;
1028        pNv->PRAMIN[0x084D] = 0x00007FFF;
1029        pNv->PRAMIN[0x084E] = pNv->FbUsableSize | 0x00000002;
1030
1031 #if X_BYTE_ORDER == X_BIG_ENDIAN
1032        pNv->PRAMIN[0x080A] |= 0x01000000;
1033        pNv->PRAMIN[0x0812] |= 0x01000000;
1034        pNv->PRAMIN[0x081A] |= 0x01000000;
1035        pNv->PRAMIN[0x0822] |= 0x01000000;
1036        pNv->PRAMIN[0x082A] |= 0x01000000;
1037        pNv->PRAMIN[0x0832] |= 0x01000000;
1038        pNv->PRAMIN[0x083A] |= 0x01000000;
1039        pNv->PRAMIN[0x0842] |= 0x01000000;
1040        pNv->PRAMIN[0x0819] = 0x01000000;
1041        pNv->PRAMIN[0x0839] = 0x01000000;
1042 #endif
1043     } else {
1044        pNv->PRAMIN[0x0000] = 0x80000010;
1045        pNv->PRAMIN[0x0001] = 0x80011201;
1046        pNv->PRAMIN[0x0002] = 0x80000011;
1047        pNv->PRAMIN[0x0003] = 0x80011202;
1048        pNv->PRAMIN[0x0004] = 0x80000012;
1049        pNv->PRAMIN[0x0005] = 0x80011203;
1050        pNv->PRAMIN[0x0006] = 0x80000013;
1051        pNv->PRAMIN[0x0007] = 0x80011204;
1052        pNv->PRAMIN[0x0008] = 0x80000014;
1053        pNv->PRAMIN[0x0009] = 0x80011205;
1054        pNv->PRAMIN[0x000A] = 0x80000015;
1055        pNv->PRAMIN[0x000B] = 0x80011206;
1056        pNv->PRAMIN[0x000C] = 0x80000016;
1057        pNv->PRAMIN[0x000D] = 0x80011207;
1058        pNv->PRAMIN[0x000E] = 0x80000017;
1059        pNv->PRAMIN[0x000F] = 0x80011208;
1060        pNv->PRAMIN[0x0800] = 0x00003000;
1061        pNv->PRAMIN[0x0801] = pNv->FbMapSize - 1;
1062        pNv->PRAMIN[0x0802] = 0x00000002;
1063        pNv->PRAMIN[0x0803] = 0x00000002;
1064        if(pNv->Architecture >= NV_ARCH_10)
1065           pNv->PRAMIN[0x0804] = 0x01008062;
1066        else
1067           pNv->PRAMIN[0x0804] = 0x01008042;
1068        pNv->PRAMIN[0x0805] = 0x00000000;
1069        pNv->PRAMIN[0x0806] = 0x12001200;
1070        pNv->PRAMIN[0x0807] = 0x00000000;
1071        pNv->PRAMIN[0x0808] = 0x01008043;
1072        pNv->PRAMIN[0x0809] = 0x00000000;
1073        pNv->PRAMIN[0x080A] = 0x00000000;
1074        pNv->PRAMIN[0x080B] = 0x00000000;
1075        pNv->PRAMIN[0x080C] = 0x01008044;
1076        pNv->PRAMIN[0x080D] = 0x00000002;
1077        pNv->PRAMIN[0x080E] = 0x00000000;
1078        pNv->PRAMIN[0x080F] = 0x00000000;
1079        pNv->PRAMIN[0x0810] = 0x01008019;
1080        pNv->PRAMIN[0x0811] = 0x00000000;
1081        pNv->PRAMIN[0x0812] = 0x00000000;
1082        pNv->PRAMIN[0x0813] = 0x00000000;
1083        pNv->PRAMIN[0x0814] = 0x0100A05C;
1084        pNv->PRAMIN[0x0815] = 0x00000000;
1085        pNv->PRAMIN[0x0816] = 0x00000000;
1086        pNv->PRAMIN[0x0817] = 0x00000000;
1087        if(pNv->WaitVSyncPossible)
1088           pNv->PRAMIN[0x0818] = 0x0100809F;
1089        else
1090           pNv->PRAMIN[0x0818] = 0x0100805F;
1091        pNv->PRAMIN[0x0819] = 0x00000000;
1092        pNv->PRAMIN[0x081A] = 0x12001200;
1093        pNv->PRAMIN[0x081B] = 0x00000000;
1094        pNv->PRAMIN[0x081C] = 0x0100804A;
1095        pNv->PRAMIN[0x081D] = 0x00000002;
1096        pNv->PRAMIN[0x081E] = 0x00000000;
1097        pNv->PRAMIN[0x081F] = 0x00000000;
1098        pNv->PRAMIN[0x0820] = 0x01018077;
1099        pNv->PRAMIN[0x0821] = 0x00000000;
1100        pNv->PRAMIN[0x0822] = 0x12001200;
1101        pNv->PRAMIN[0x0823] = 0x00000000;
1102        pNv->PRAMIN[0x0824] = 0x00003002;
1103        pNv->PRAMIN[0x0825] = 0x00007FFF;
1104        pNv->PRAMIN[0x0826] = pNv->FbUsableSize | 0x00000002;
1105        pNv->PRAMIN[0x0827] = 0x00000002;
1106
1107 #if X_BYTE_ORDER == X_BIG_ENDIAN
1108        pNv->PRAMIN[0x0804] |= 0x00080000;
1109        pNv->PRAMIN[0x0808] |= 0x00080000;
1110        pNv->PRAMIN[0x080C] |= 0x00080000;
1111        pNv->PRAMIN[0x0810] |= 0x00080000;
1112        pNv->PRAMIN[0x0814] |= 0x00080000;
1113        pNv->PRAMIN[0x0818] |= 0x00080000;
1114        pNv->PRAMIN[0x081C] |= 0x00080000;
1115        pNv->PRAMIN[0x0820] |= 0x00080000;
1116        pNv->PRAMIN[0x080D] = 0x00000001;
1117        pNv->PRAMIN[0x081D] = 0x00000001;
1118 #endif
1119     }
1120
1121     if(pNv->Architecture < NV_ARCH_10) {
1122        if((pNv->Chipset & 0x0fff) == 0x0020) {
1123            pNv->PRAMIN[0x0824] |= 0x00020000;
1124            pNv->PRAMIN[0x0826] += pNv->FbAddress;
1125        }
1126        pNv->PGRAPH[0x0080/4] = 0x000001FF;
1127        pNv->PGRAPH[0x0080/4] = 0x1230C000;
1128        pNv->PGRAPH[0x0084/4] = 0x72111101;
1129        pNv->PGRAPH[0x0088/4] = 0x11D5F071;
1130        pNv->PGRAPH[0x008C/4] = 0x0004FF31;
1131        pNv->PGRAPH[0x008C/4] = 0x4004FF31;
1132
1133        pNv->PGRAPH[0x0140/4] = 0x00000000;
1134        pNv->PGRAPH[0x0100/4] = 0xFFFFFFFF;
1135        pNv->PGRAPH[0x0170/4] = 0x10010100;
1136        pNv->PGRAPH[0x0710/4] = 0xFFFFFFFF;
1137        pNv->PGRAPH[0x0720/4] = 0x00000001;
1138
1139        pNv->PGRAPH[0x0810/4] = 0x00000000;
1140        pNv->PGRAPH[0x0608/4] = 0xFFFFFFFF;
1141     } else {
1142        pNv->PGRAPH[0x0080/4] = 0xFFFFFFFF;
1143        pNv->PGRAPH[0x0080/4] = 0x00000000;
1144
1145        pNv->PGRAPH[0x0140/4] = 0x00000000;
1146        pNv->PGRAPH[0x0100/4] = 0xFFFFFFFF;
1147        pNv->PGRAPH[0x0144/4] = 0x10010100;
1148        pNv->PGRAPH[0x0714/4] = 0xFFFFFFFF;
1149        pNv->PGRAPH[0x0720/4] = 0x00000001;
1150        pNv->PGRAPH[0x0710/4] &= 0x0007ff00;
1151        pNv->PGRAPH[0x0710/4] |= 0x00020100;
1152
1153        if(pNv->Architecture == NV_ARCH_10) {
1154            pNv->PGRAPH[0x0084/4] = 0x00118700;
1155            pNv->PGRAPH[0x0088/4] = 0x24E00810;
1156            pNv->PGRAPH[0x008C/4] = 0x55DE0030;
1157
1158            for(i = 0; i < 32; i++)
1159              pNv->PGRAPH[(0x0B00/4) + i] = pNv->PFB[(0x0240/4) + i];
1160
1161            pNv->PGRAPH[0x640/4] = 0;
1162            pNv->PGRAPH[0x644/4] = 0;
1163            pNv->PGRAPH[0x684/4] = pNv->FbMapSize - 1;
1164            pNv->PGRAPH[0x688/4] = pNv->FbMapSize - 1;
1165
1166            pNv->PGRAPH[0x0810/4] = 0x00000000;
1167            pNv->PGRAPH[0x0608/4] = 0xFFFFFFFF;
1168        } else {
1169            if(pNv->Architecture >= NV_ARCH_40) {
1170               pNv->PGRAPH[0x0084/4] = 0x401287c0;
1171               pNv->PGRAPH[0x008C/4] = 0x60de8051;
1172               pNv->PGRAPH[0x0090/4] = 0x00008000;
1173               pNv->PGRAPH[0x0610/4] = 0x00be3c5f;
1174
1175               if((pNv->Chipset & 0xfff0) == 0x0040) {
1176                  pNv->PGRAPH[0x09b0/4] = 0x83280fff;
1177                  pNv->PGRAPH[0x09b4/4] = 0x000000a0;
1178               } else {
1179                  pNv->PGRAPH[0x0820/4] = 0x83280eff;
1180                  pNv->PGRAPH[0x0824/4] = 0x000000a0;
1181               }
1182
1183               switch(pNv->Chipset & 0xfff0) {
1184               case 0x0040:
1185               case 0x0210:
1186                  pNv->PGRAPH[0x09b8/4] = 0x0078e366;
1187                  pNv->PGRAPH[0x09bc/4] = 0x0000014c;
1188                  pNv->PFB[0x033C/4] &= 0xffff7fff;
1189                  break;
1190               case 0x00C0:
1191               case 0x0120:
1192                  pNv->PGRAPH[0x0828/4] = 0x007596ff;
1193                  pNv->PGRAPH[0x082C/4] = 0x00000108;
1194                  break;
1195               case 0x0160:
1196               case 0x01D0:
1197                  pNv->PMC[0x1700/4] = pNv->PFB[0x020C/4];
1198                  pNv->PMC[0x1704/4] = 0;
1199                  pNv->PMC[0x1708/4] = 0;
1200                  pNv->PMC[0x170C/4] = pNv->PFB[0x020C/4];
1201                  pNv->PGRAPH[0x0860/4] = 0;
1202                  pNv->PGRAPH[0x0864/4] = 0;
1203                  pNv->PRAMDAC[0x0608/4] |= 0x00100000;
1204                  break;
1205               case 0x0140:
1206                  pNv->PGRAPH[0x0828/4] = 0x0072cb77;
1207                  pNv->PGRAPH[0x082C/4] = 0x00000108;
1208                  break;
1209               case 0x0220:
1210               case 0x0230:
1211                  pNv->PGRAPH[0x0860/4] = 0;
1212                  pNv->PGRAPH[0x0864/4] = 0;
1213                  pNv->PRAMDAC[0x0608/4] |= 0x00100000;
1214                  break;
1215               case 0x0090:
1216               case 0x0290:
1217                  pNv->PRAMDAC[0x0608/4] |= 0x00100000;
1218                  pNv->PGRAPH[0x0828/4] = 0x07830610;
1219                  pNv->PGRAPH[0x082C/4] = 0x0000016A;
1220                  break;
1221               default:
1222                  break;
1223               };
1224
1225               pNv->PGRAPH[0x0b38/4] = 0x2ffff800;
1226               pNv->PGRAPH[0x0b3c/4] = 0x00006000;
1227               pNv->PGRAPH[0x032C/4] = 0x01000000;
1228               pNv->PGRAPH[0x0220/4] = 0x00001200;
1229            } else
1230            if(pNv->Architecture == NV_ARCH_30) {
1231               pNv->PGRAPH[0x0084/4] = 0x40108700;
1232               pNv->PGRAPH[0x0890/4] = 0x00140000;
1233               pNv->PGRAPH[0x008C/4] = 0xf00e0431;
1234               pNv->PGRAPH[0x0090/4] = 0x00008000;
1235               pNv->PGRAPH[0x0610/4] = 0xf04b1f36;
1236               pNv->PGRAPH[0x0B80/4] = 0x1002d888;
1237               pNv->PGRAPH[0x0B88/4] = 0x62ff007f;
1238            } else {
1239               pNv->PGRAPH[0x0084/4] = 0x00118700;
1240               pNv->PGRAPH[0x008C/4] = 0xF20E0431;
1241               pNv->PGRAPH[0x0090/4] = 0x00000000;
1242               pNv->PGRAPH[0x009C/4] = 0x00000040;
1243
1244               if((pNv->Chipset & 0x0ff0) >= 0x0250) {
1245                  pNv->PGRAPH[0x0890/4] = 0x00080000;
1246                  pNv->PGRAPH[0x0610/4] = 0x304B1FB6;
1247                  pNv->PGRAPH[0x0B80/4] = 0x18B82880;
1248                  pNv->PGRAPH[0x0B84/4] = 0x44000000;
1249                  pNv->PGRAPH[0x0098/4] = 0x40000080;
1250                  pNv->PGRAPH[0x0B88/4] = 0x000000ff;
1251               } else {
1252                  pNv->PGRAPH[0x0880/4] = 0x00080000;
1253                  pNv->PGRAPH[0x0094/4] = 0x00000005;
1254                  pNv->PGRAPH[0x0B80/4] = 0x45CAA208;
1255                  pNv->PGRAPH[0x0B84/4] = 0x24000000;
1256                  pNv->PGRAPH[0x0098/4] = 0x00000040;
1257                  pNv->PGRAPH[0x0750/4] = 0x00E00038;
1258                  pNv->PGRAPH[0x0754/4] = 0x00000030;
1259                  pNv->PGRAPH[0x0750/4] = 0x00E10038;
1260                  pNv->PGRAPH[0x0754/4] = 0x00000030;
1261               }
1262            }
1263
1264            if((pNv->Architecture < NV_ARCH_40) ||
1265               ((pNv->Chipset & 0xfff0) == 0x0040))
1266            {
1267               for(i = 0; i < 32; i++)
1268                 pNv->PGRAPH[(0x0900/4) + i] = pNv->PFB[(0x0240/4) + i];
1269            } else {
1270               if(((pNv->Chipset & 0xfff0) == 0x0090) ||
1271                  ((pNv->Chipset & 0xfff0) == 0x01D0) ||
1272                  ((pNv->Chipset & 0xfff0) == 0x0290))
1273               {
1274                  for(i = 0; i < 60; i++)
1275                    pNv->PGRAPH[(0x0D00/4) + i] = pNv->PFB[(0x0600/4) + i];
1276               } else {
1277                  for(i = 0; i < 48; i++)
1278                    pNv->PGRAPH[(0x0900/4) + i] = pNv->PFB[(0x0600/4) + i];
1279               }
1280            }
1281
1282            if(pNv->Architecture >= NV_ARCH_40) {
1283               if((pNv->Chipset & 0xfff0) == 0x0040) {
1284                  pNv->PGRAPH[0x09A4/4] = pNv->PFB[0x0200/4];
1285                  pNv->PGRAPH[0x09A8/4] = pNv->PFB[0x0204/4];
1286                  pNv->PGRAPH[0x69A4/4] = pNv->PFB[0x0200/4];
1287                  pNv->PGRAPH[0x69A8/4] = pNv->PFB[0x0204/4];
1288
1289                  pNv->PGRAPH[0x0820/4] = 0;
1290                  pNv->PGRAPH[0x0824/4] = 0;
1291                  pNv->PGRAPH[0x0864/4] = pNv->FbMapSize - 1;
1292                  pNv->PGRAPH[0x0868/4] = pNv->FbMapSize - 1;
1293               } else {
1294                  if(((pNv->Chipset & 0xfff0) == 0x0090) ||
1295                     ((pNv->Chipset & 0xfff0) == 0x01D0) ||
1296                     ((pNv->Chipset & 0xfff0) == 0x0290))
1297                  {
1298                     pNv->PGRAPH[0x0DF0/4] = pNv->PFB[0x0200/4];
1299                     pNv->PGRAPH[0x0DF4/4] = pNv->PFB[0x0204/4];
1300                  } else {
1301                     pNv->PGRAPH[0x09F0/4] = pNv->PFB[0x0200/4];
1302                     pNv->PGRAPH[0x09F4/4] = pNv->PFB[0x0204/4];
1303                  }
1304                  pNv->PGRAPH[0x69F0/4] = pNv->PFB[0x0200/4];
1305                  pNv->PGRAPH[0x69F4/4] = pNv->PFB[0x0204/4];
1306
1307                  pNv->PGRAPH[0x0840/4] = 0;
1308                  pNv->PGRAPH[0x0844/4] = 0;
1309                  pNv->PGRAPH[0x08a0/4] = pNv->FbMapSize - 1;
1310                  pNv->PGRAPH[0x08a4/4] = pNv->FbMapSize - 1;
1311               }
1312            } else {
1313               pNv->PGRAPH[0x09A4/4] = pNv->PFB[0x0200/4];
1314               pNv->PGRAPH[0x09A8/4] = pNv->PFB[0x0204/4];
1315               pNv->PGRAPH[0x0750/4] = 0x00EA0000;
1316               pNv->PGRAPH[0x0754/4] = pNv->PFB[0x0200/4];
1317               pNv->PGRAPH[0x0750/4] = 0x00EA0004;
1318               pNv->PGRAPH[0x0754/4] = pNv->PFB[0x0204/4];
1319
1320               pNv->PGRAPH[0x0820/4] = 0;
1321               pNv->PGRAPH[0x0824/4] = 0;
1322               pNv->PGRAPH[0x0864/4] = pNv->FbMapSize - 1;
1323               pNv->PGRAPH[0x0868/4] = pNv->FbMapSize - 1;
1324            }
1325
1326            pNv->PGRAPH[0x0B20/4] = 0x00000000;
1327            pNv->PGRAPH[0x0B04/4] = 0xFFFFFFFF;
1328        }
1329     }
1330     pNv->PGRAPH[0x053C/4] = 0;
1331     pNv->PGRAPH[0x0540/4] = 0;
1332     pNv->PGRAPH[0x0544/4] = 0x00007FFF;
1333     pNv->PGRAPH[0x0548/4] = 0x00007FFF;
1334
1335     pNv->PFIFO[0x0140] = 0x00000000;
1336     pNv->PFIFO[0x0141] = 0x00000001;
1337     pNv->PFIFO[0x0480] = 0x00000000;
1338     pNv->PFIFO[0x0494] = 0x00000000;
1339     if(pNv->Architecture >= NV_ARCH_40)
1340        pNv->PFIFO[0x0481] = 0x00010000;
1341     else
1342        pNv->PFIFO[0x0481] = 0x00000100;
1343     pNv->PFIFO[0x0490] = 0x00000000;
1344     pNv->PFIFO[0x0491] = 0x00000000;
1345     if(pNv->Architecture >= NV_ARCH_40)
1346        pNv->PFIFO[0x048B] = 0x00001213;
1347     else
1348        pNv->PFIFO[0x048B] = 0x00001209;
1349     pNv->PFIFO[0x0400] = 0x00000000;
1350     pNv->PFIFO[0x0414] = 0x00000000;
1351     pNv->PFIFO[0x0084] = 0x03000100;
1352     pNv->PFIFO[0x0085] = 0x00000110;
1353     pNv->PFIFO[0x0086] = 0x00000112;
1354     pNv->PFIFO[0x0143] = 0x0000FFFF;
1355     pNv->PFIFO[0x0496] = 0x0000FFFF;
1356     pNv->PFIFO[0x0050] = 0x00000000;
1357     pNv->PFIFO[0x0040] = 0xFFFFFFFF;
1358     pNv->PFIFO[0x0415] = 0x00000001;
1359     pNv->PFIFO[0x048C] = 0x00000000;
1360     pNv->PFIFO[0x04A0] = 0x00000000;
1361 #if X_BYTE_ORDER == X_BIG_ENDIAN
1362     pNv->PFIFO[0x0489] = 0x800F0078;
1363 #else
1364     pNv->PFIFO[0x0489] = 0x000F0078;
1365 #endif
1366     pNv->PFIFO[0x0488] = 0x00000001;
1367     pNv->PFIFO[0x0480] = 0x00000001;
1368     pNv->PFIFO[0x0494] = 0x00000001;
1369     pNv->PFIFO[0x0495] = 0x00000001;
1370     pNv->PFIFO[0x0140] = 0x00000001;
1371
1372     if(pNv->Architecture >= NV_ARCH_10) {
1373         if(pNv->twoHeads) {
1374            pNv->PCRTC0[0x0860/4] = state->head;
1375            pNv->PCRTC0[0x2860/4] = state->head2;
1376         }
1377         pNv->PRAMDAC[0x0404/4] |= (1 << 25);
1378
1379         pNv->PMC[0x8704/4] = 1;
1380         pNv->PMC[0x8140/4] = 0;
1381         pNv->PMC[0x8920/4] = 0;
1382         pNv->PMC[0x8924/4] = 0;
1383         pNv->PMC[0x8908/4] = pNv->FbMapSize - 1;
1384         pNv->PMC[0x890C/4] = pNv->FbMapSize - 1;
1385         pNv->PMC[0x1588/4] = 0;
1386
1387         pNv->PCRTC[0x0810/4] = state->cursorConfig;
1388         pNv->PCRTC[0x0830/4] = state->displayV - 3;
1389         pNv->PCRTC[0x0834/4] = state->displayV - 1;
1390
1391         if(pNv->FlatPanel) {
1392            if((pNv->Chipset & 0x0ff0) == 0x0110) {
1393                pNv->PRAMDAC[0x0528/4] = state->dither;
1394            } else
1395            if(pNv->twoHeads) {
1396                pNv->PRAMDAC[0x083C/4] = state->dither;
1397            }
1398
1399            VGA_WR08(pNv->PCIO, 0x03D4, 0x53);
1400            VGA_WR08(pNv->PCIO, 0x03D5, state->timingH);
1401            VGA_WR08(pNv->PCIO, 0x03D4, 0x54);
1402            VGA_WR08(pNv->PCIO, 0x03D5, state->timingV);
1403            VGA_WR08(pNv->PCIO, 0x03D4, 0x21);
1404            VGA_WR08(pNv->PCIO, 0x03D5, 0xfa);
1405         }
1406
1407         VGA_WR08(pNv->PCIO, 0x03D4, 0x41);
1408         VGA_WR08(pNv->PCIO, 0x03D5, state->extra);
1409     }
1410
1411     VGA_WR08(pNv->PCIO, 0x03D4, 0x19);
1412     VGA_WR08(pNv->PCIO, 0x03D5, state->repaint0);
1413     VGA_WR08(pNv->PCIO, 0x03D4, 0x1A);
1414     VGA_WR08(pNv->PCIO, 0x03D5, state->repaint1);
1415     VGA_WR08(pNv->PCIO, 0x03D4, 0x25);
1416     VGA_WR08(pNv->PCIO, 0x03D5, state->screen);
1417     VGA_WR08(pNv->PCIO, 0x03D4, 0x28);
1418     VGA_WR08(pNv->PCIO, 0x03D5, state->pixel);
1419     VGA_WR08(pNv->PCIO, 0x03D4, 0x2D);
1420     VGA_WR08(pNv->PCIO, 0x03D5, state->horiz);
1421     VGA_WR08(pNv->PCIO, 0x03D4, 0x1C);
1422     VGA_WR08(pNv->PCIO, 0x03D5, state->fifo);
1423     VGA_WR08(pNv->PCIO, 0x03D4, 0x1B);
1424     VGA_WR08(pNv->PCIO, 0x03D5, state->arbitration0);
1425     VGA_WR08(pNv->PCIO, 0x03D4, 0x20);
1426     VGA_WR08(pNv->PCIO, 0x03D5, state->arbitration1);
1427     if(pNv->Architecture >= NV_ARCH_30) {
1428       VGA_WR08(pNv->PCIO, 0x03D4, 0x47);
1429       VGA_WR08(pNv->PCIO, 0x03D5, state->arbitration1 >> 8);
1430     }
1431     VGA_WR08(pNv->PCIO, 0x03D4, 0x30);
1432     VGA_WR08(pNv->PCIO, 0x03D5, state->cursor0);
1433     VGA_WR08(pNv->PCIO, 0x03D4, 0x31);
1434     VGA_WR08(pNv->PCIO, 0x03D5, state->cursor1);
1435     VGA_WR08(pNv->PCIO, 0x03D4, 0x2F);
1436     VGA_WR08(pNv->PCIO, 0x03D5, state->cursor2);
1437     VGA_WR08(pNv->PCIO, 0x03D4, 0x39);
1438     VGA_WR08(pNv->PCIO, 0x03D5, state->interlace);
1439
1440     if(!pNv->FlatPanel) {
1441        pNv->PRAMDAC0[0x050C/4] = state->pllsel;
1442        pNv->PRAMDAC0[0x0508/4] = state->vpll;
1443        if(pNv->twoHeads)
1444           pNv->PRAMDAC0[0x0520/4] = state->vpll2;
1445        if(pNv->twoStagePLL) {
1446           pNv->PRAMDAC0[0x0578/4] = state->vpllB;
1447           pNv->PRAMDAC0[0x057C/4] = state->vpll2B;
1448        }
1449     } else {
1450        pNv->PRAMDAC[0x0848/4] = state->scale;
1451        pNv->PRAMDAC[0x0828/4] = state->crtcSync;
1452     }
1453     pNv->PRAMDAC[0x0600/4] = state->general;
1454
1455     pNv->PCRTC[0x0140/4] = 0;
1456     pNv->PCRTC[0x0100/4] = 1;
1457
1458     pNv->CurrentState = state;
1459 }
1460
1461 void NVUnloadStateExt
1462 (
1463     NVPtr pNv,
1464     RIVA_HW_STATE *state
1465 )
1466 {
1467     VGA_WR08(pNv->PCIO, 0x03D4, 0x19);
1468     state->repaint0     = VGA_RD08(pNv->PCIO, 0x03D5);
1469     VGA_WR08(pNv->PCIO, 0x03D4, 0x1A);
1470     state->repaint1     = VGA_RD08(pNv->PCIO, 0x03D5);
1471     VGA_WR08(pNv->PCIO, 0x03D4, 0x25);
1472     state->screen       = VGA_RD08(pNv->PCIO, 0x03D5);
1473     VGA_WR08(pNv->PCIO, 0x03D4, 0x28);
1474     state->pixel        = VGA_RD08(pNv->PCIO, 0x03D5);
1475     VGA_WR08(pNv->PCIO, 0x03D4, 0x2D);
1476     state->horiz        = VGA_RD08(pNv->PCIO, 0x03D5);
1477     VGA_WR08(pNv->PCIO, 0x03D4, 0x1C);
1478     state->fifo         = VGA_RD08(pNv->PCIO, 0x03D5);
1479     VGA_WR08(pNv->PCIO, 0x03D4, 0x1B);
1480     state->arbitration0 = VGA_RD08(pNv->PCIO, 0x03D5);
1481     VGA_WR08(pNv->PCIO, 0x03D4, 0x20);
1482     state->arbitration1 = VGA_RD08(pNv->PCIO, 0x03D5);
1483     if(pNv->Architecture >= NV_ARCH_30) {
1484        VGA_WR08(pNv->PCIO, 0x03D4, 0x47);
1485        state->arbitration1 |= (VGA_RD08(pNv->PCIO, 0x03D5) & 1) << 8;
1486     }
1487     VGA_WR08(pNv->PCIO, 0x03D4, 0x30);
1488     state->cursor0      = VGA_RD08(pNv->PCIO, 0x03D5);
1489     VGA_WR08(pNv->PCIO, 0x03D4, 0x31);
1490     state->cursor1      = VGA_RD08(pNv->PCIO, 0x03D5);
1491     VGA_WR08(pNv->PCIO, 0x03D4, 0x2F);
1492     state->cursor2      = VGA_RD08(pNv->PCIO, 0x03D5);
1493     VGA_WR08(pNv->PCIO, 0x03D4, 0x39);
1494     state->interlace    = VGA_RD08(pNv->PCIO, 0x03D5);
1495     state->vpll         = pNv->PRAMDAC0[0x0508/4];
1496     if(pNv->twoHeads)
1497        state->vpll2     = pNv->PRAMDAC0[0x0520/4];
1498     if(pNv->twoStagePLL) {
1499         state->vpllB    = pNv->PRAMDAC0[0x0578/4];
1500         state->vpll2B   = pNv->PRAMDAC0[0x057C/4];
1501     }
1502     state->pllsel       = pNv->PRAMDAC0[0x050C/4];
1503     state->general      = pNv->PRAMDAC[0x0600/4];
1504     state->scale        = pNv->PRAMDAC[0x0848/4];
1505     state->config       = pNv->PFB[0x0200/4];
1506
1507     if(pNv->Architecture >= NV_ARCH_10) {
1508         if(pNv->twoHeads) {
1509            state->head     = pNv->PCRTC0[0x0860/4];
1510            state->head2    = pNv->PCRTC0[0x2860/4];
1511            VGA_WR08(pNv->PCIO, 0x03D4, 0x44);
1512            state->crtcOwner = VGA_RD08(pNv->PCIO, 0x03D5);
1513         }
1514         VGA_WR08(pNv->PCIO, 0x03D4, 0x41);
1515         state->extra = VGA_RD08(pNv->PCIO, 0x03D5);
1516         state->cursorConfig = pNv->PCRTC[0x0810/4];
1517
1518         if((pNv->Chipset & 0x0ff0) == 0x0110) {
1519            state->dither = pNv->PRAMDAC[0x0528/4];
1520         } else
1521         if(pNv->twoHeads) {
1522             state->dither = pNv->PRAMDAC[0x083C/4];
1523         }
1524
1525         if(pNv->FlatPanel) {
1526            VGA_WR08(pNv->PCIO, 0x03D4, 0x53);
1527            state->timingH = VGA_RD08(pNv->PCIO, 0x03D5);
1528            VGA_WR08(pNv->PCIO, 0x03D4, 0x54);
1529            state->timingV = VGA_RD08(pNv->PCIO, 0x03D5);
1530         }
1531     }
1532
1533     if(pNv->FlatPanel) {
1534        state->crtcSync = pNv->PRAMDAC[0x0828/4];
1535     }
1536 }
1537
1538 void NVSetStartAddress (
1539     NVPtr   pNv,
1540     CARD32 start
1541 )
1542 {
1543     pNv->PCRTC[0x800/4] = start;
1544 }
1545
1546