2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2008 Stuart Bennett
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 #include "nv_include.h"
29 /* FIXME: put these somewhere */
30 #define CRTC_INDEX_COLOR (VGA_IOBASE_COLOR + VGA_CRTC_INDEX_OFFSET)
31 #define NV_VGA_CRTCX_OWNER_HEADA 0x0
32 #define NV_VGA_CRTCX_OWNER_HEADB 0x3
33 #define NV_PBUS_PCI_NV_19 0x0000184C
34 #define NV_PBUS_PCI_NV_20 0x00001850
35 #define NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED 0x00000000
36 #define NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED 0x00000001
37 #define NV_PEXTDEV_BOOT_0 0x00101000
38 /* undef, as we want the +0x00100000 version */
40 #define NV_PFB_CFG0 0x00100200
41 #define NV_PFB_REFCTRL 0x00100210
42 #define NV_PFB_REFCTRL_VALID_1 0x80000000
43 #define NV_PRAMIN_ROM_OFFSET 0x00700000
51 static int crtchead = 0;
53 /* this will need remembering across a suspend */
54 static uint32_t saved_nv_pfb_cfg0;
61 static uint16_t le16_to_cpu(const uint16_t x)
63 #if X_BYTE_ORDER == X_BIG_ENDIAN
70 static uint32_t le32_to_cpu(const uint32_t x)
72 #if X_BYTE_ORDER == X_BIG_ENDIAN
79 static Bool nv_cksum(const uint8_t *data, unsigned int length)
81 /* there's a few checksums in the BIOS, so here's a generic checking function */
85 for (i = 0; i < length; i++)
94 static int NVValidVBIOS(ScrnInfoPtr pScrn, const uint8_t *data)
96 /* check for BIOS signature */
97 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
98 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
99 "... BIOS signature not found\n");
103 if (nv_cksum(data, data[2] * 512)) {
104 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
105 "... BIOS checksum invalid\n");
106 /* probably ought to set a do_not_execute flag for table parsing here,
107 * assuming most BIOSen are valid */
110 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "... appears to be valid\n");
115 static void NVShadowVBIOS_PROM(ScrnInfoPtr pScrn, uint8_t *data)
117 NVPtr pNv = NVPTR(pScrn);
120 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
121 "Attempting to locate BIOS image in PROM\n");
123 /* enable ROM access */
124 nvWriteMC(pNv, NV_PBUS_PCI_NV_20, NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED);
125 for (i = 0; i < NV_PROM_SIZE; i++) {
126 /* according to nvclock, we need that to work around a 6600GT/6800LE bug */
127 data[i] = pNv->PROM[i];
128 data[i] = pNv->PROM[i];
129 data[i] = pNv->PROM[i];
130 data[i] = pNv->PROM[i];
131 data[i] = pNv->PROM[i];
133 /* disable ROM access */
134 nvWriteMC(pNv, NV_PBUS_PCI_NV_20, NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
137 static void NVShadowVBIOS_PRAMIN(ScrnInfoPtr pScrn, uint32_t *data)
139 NVPtr pNv = NVPTR(pScrn);
140 const uint32_t *pramin = (uint32_t *)&pNv->REGS[NV_PRAMIN_ROM_OFFSET/4];
141 uint32_t old_bar0_pramin = 0;
143 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
144 "Attempting to locate BIOS image in PRAMIN\n");
146 if (pNv->Architecture >= NV_ARCH_50) {
149 vbios_vram = (pNv->REGS[0x619f04/4] & ~0xff) << 8;
151 vbios_vram = pNv->REGS[0x1700/4] << 16;
152 vbios_vram += 0xf0000;
155 old_bar0_pramin = pNv->REGS[0x1700/4];
156 pNv->REGS[0x1700/4] = vbios_vram >> 16;
159 memcpy(data, pramin, NV_PROM_SIZE);
161 if (pNv->Architecture >= NV_ARCH_50) {
162 pNv->REGS[0x1700/4] = old_bar0_pramin;
166 static void NVVBIOS_PCIROM(ScrnInfoPtr pScrn, uint8_t *data)
168 NVPtr pNv = NVPTR(pScrn);
170 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
171 "Attempting to use PCI ROM BIOS image\n");
173 #if XSERVER_LIBPCIACCESS
174 pci_device_read_rom(pNv->PciInfo, data);
176 xf86ReadPciBIOS(0, pNv->PciTag, 0, data, NV_PROM_SIZE);
180 static Bool NVShadowVBIOS(ScrnInfoPtr pScrn, uint8_t *data)
182 NVShadowVBIOS_PROM(pScrn, data);
183 if (NVValidVBIOS(pScrn, data) == 2)
186 NVShadowVBIOS_PRAMIN(pScrn, (uint32_t *)data);
187 if (NVValidVBIOS(pScrn, data))
191 NVVBIOS_PCIROM(pScrn, data);
192 if (NVValidVBIOS(pScrn, data))
204 int length_multiplier;
205 Bool (*handler)(ScrnInfoPtr pScrn, bios_t *, uint16_t, init_exec_t *);
214 static void parse_init_table(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset, init_exec_t *iexec);
216 #define MACRO_INDEX_SIZE 2
218 #define CONDITION_SIZE 12
219 #define IO_FLAG_CONDITION_SIZE 9
227 static int nv_valid_reg(NVPtr pNv, uint32_t reg)
229 /* C51 has misaligned regs on purpose. Marvellous */
230 if ((reg & 0x3 && pNv->VBIOS.chip_version != 0x51) ||
231 (reg & 0x2 && pNv->VBIOS.chip_version == 0x51)) {
232 ErrorF("========== misaligned reg 0x%08X ==========\n", reg);
236 #define WITHIN(x,y,z) ((x>=y)&&(x<y+z))
237 if (WITHIN(reg,NV_PRAMIN_OFFSET,NV_PRAMIN_SIZE))
239 if (WITHIN(reg,NV_PCRTC0_OFFSET,NV_PCRTC0_SIZE))
241 if (WITHIN(reg,NV_PRAMDAC0_OFFSET,NV_PRAMDAC0_SIZE))
243 if (WITHIN(reg,NV_PFB_OFFSET,NV_PFB_SIZE))
245 if (WITHIN(reg,NV_PFIFO_OFFSET,NV_PFIFO_SIZE))
247 if (WITHIN(reg,NV_PGRAPH_OFFSET,NV_PGRAPH_SIZE))
249 if (WITHIN(reg,NV_PEXTDEV_OFFSET,NV_PEXTDEV_SIZE))
251 if (WITHIN(reg,NV_PTIMER_OFFSET,NV_PTIMER_SIZE))
253 if (WITHIN(reg,NV_PVIDEO_OFFSET,NV_PVIDEO_SIZE))
255 if (WITHIN(reg,NV_PMC_OFFSET,NV_PMC_SIZE))
257 if (WITHIN(reg,NV_FIFO_OFFSET,NV_FIFO_SIZE))
259 if (WITHIN(reg,NV_PCIO0_OFFSET,NV_PCIO0_SIZE))
261 if (WITHIN(reg,NV_PDIO0_OFFSET,NV_PDIO0_SIZE))
263 if (WITHIN(reg,NV_PVIO_OFFSET,NV_PVIO_SIZE))
265 if (WITHIN(reg,NV_PROM_OFFSET,NV_PROM_SIZE))
267 if (WITHIN(reg,NV_PRAMIN_ROM_OFFSET,NV_PROM_SIZE))
270 if (WITHIN(reg,0x88000,0x1000))
274 ErrorF("========== unknown reg 0x%08X ==========\n", reg);
279 static uint32_t nv32_rd(ScrnInfoPtr pScrn, uint32_t reg)
281 NVPtr pNv = NVPTR(pScrn);
284 if (!nv_valid_reg(pNv, reg))
287 /* C51 sometimes uses regs with bit0 set in the address. For these
288 * cases there should exist a translation in a BIOS table to an IO
289 * port address which the BIOS uses for accessing the reg
291 * These only seem to appear for the power control regs to a flat panel
292 * and in C51 mmio traces the normal regs for 0x1308 and 0x1310 are
293 * used - hence the mask below. An S3 suspend-resume mmio trace from a
294 * C51 will be required to see if this is true for the power microcode
295 * in 0x14.., or whether the direct IO port access method is needed
300 data = pNv->REGS[reg/4];
303 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
304 " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
309 static int nv32_wr(ScrnInfoPtr pScrn, uint32_t reg, uint32_t data)
311 NVPtr pNv = NVPTR(pScrn);
313 if (!nv_valid_reg(pNv, reg))
316 /* see note in nv32_rd */
323 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
324 " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
326 if (pNv->VBIOS.execute) {
328 pNv->REGS[reg/4] = data;
334 static uint8_t nv_idx_port_rd(ScrnInfoPtr pScrn, uint16_t port, uint8_t index)
336 NVPtr pNv = NVPTR(pScrn);
337 volatile uint8_t *ptr = crtchead ? pNv->PCIO1 : pNv->PCIO0;
340 VGA_WR08(ptr, port, index);
341 data = VGA_RD08(ptr, port + 1);
344 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
345 " Indexed read: Port: 0x%04X, Index: 0x%02X, Head: 0x%02X, Data: 0x%02X\n",
346 port, index, crtchead, data);
351 static void nv_idx_port_wr(ScrnInfoPtr pScrn, uint16_t port, uint8_t index, uint8_t data)
353 NVPtr pNv = NVPTR(pScrn);
354 volatile uint8_t *ptr;
356 /* The current head is maintained in a file scope variable crtchead.
357 * We trap changes to CRTCX_OWNER and update the head variable
358 * and hence the register set written.
359 * As CRTCX_OWNER only exists on CRTC0, we update crtchead to head0
360 * in advance of the write, and to head1 after the write
362 if (port == CRTC_INDEX_COLOR && index == NV_VGA_CRTCX_OWNER && data != NV_VGA_CRTCX_OWNER_HEADB)
364 ptr = crtchead ? pNv->PCIO1 : pNv->PCIO0;
367 nv_idx_port_rd(pScrn, port, index);
369 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
370 " Indexed write: Port: 0x%04X, Index: 0x%02X, Head: 0x%02X, Data: 0x%02X\n",
371 port, index, crtchead, data);
373 if (pNv->VBIOS.execute) {
375 VGA_WR08(ptr, port, index);
376 VGA_WR08(ptr, port + 1, data);
379 if (port == CRTC_INDEX_COLOR && index == NV_VGA_CRTCX_OWNER && data == NV_VGA_CRTCX_OWNER_HEADB)
383 #define ACCESS_UNLOCK 0
384 #define ACCESS_LOCK 1
385 static void crtc_access(ScrnInfoPtr pScrn, Bool lock)
387 NVPtr pNv = NVPTR(pScrn);
388 int savedhead = crtchead;
391 /* necessary external dependancy (twoHeads) */
393 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_OWNER, NV_VGA_CRTCX_OWNER_HEADA);
394 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_LOCK, lock ? 0x99 : 0x57);
395 cr11 = nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_VSYNCE);
396 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_VSYNCE, lock ? cr11 | 0x80 : cr11 & ~0x80);
399 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_OWNER, NV_VGA_CRTCX_OWNER_HEADB);
400 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_LOCK, lock ? 0x99 : 0x57);
401 cr11 = nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_VSYNCE);
402 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_VSYNCE, lock ? cr11 | 0x80 : cr11 & ~0x80);
405 crtchead = savedhead;
408 static Bool io_flag_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, uint8_t cond)
410 /* The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
411 * for the CRTC index; 1 byte for the mask to apply to the value
412 * retrieved from the CRTC; 1 byte for the shift right to apply to the
413 * masked CRTC value; 2 bytes for the offset to the flag array, to
414 * which the shifted value is added; 1 byte for the mask applied to the
415 * value read from the flag array; and 1 byte for the value to compare
416 * against the masked byte from the flag table.
419 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
420 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[condptr])));
421 uint8_t crtcindex = bios->data[condptr + 2];
422 uint8_t mask = bios->data[condptr + 3];
423 uint8_t shift = bios->data[condptr + 4];
424 uint16_t flagarray = le16_to_cpu(*((uint16_t *)(&bios->data[condptr + 5])));
425 uint8_t flagarraymask = bios->data[condptr + 7];
426 uint8_t cmpval = bios->data[condptr + 8];
430 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
431 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, Cmpval: 0x%02X\n",
432 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
434 data = nv_idx_port_rd(pScrn, crtcport, crtcindex);
436 data = bios->data[flagarray + ((data & mask) >> shift)];
437 data &= flagarraymask;
440 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
441 "0x%04X: Checking if 0x%02X equals 0x%02X\n",
442 offset, data, cmpval);
450 uint32_t getMNP_single(ScrnInfoPtr pScrn, uint32_t clk, int *bestNM, int *bestlog2P)
452 /* Find M, N and P for a single stage PLL
454 * Note that some bioses (NV3x) have lookup tables of precomputed MNP
455 * values, but we're too lazy to use those atm
457 * "clk" parameter in kHz
458 * returns calculated clock
461 bios_t *bios = &NVPTR(pScrn)->VBIOS;
463 int maxlog2P, log2P, P;
465 uint32_t minvco = bios->fminvco;
466 uint32_t maxvco = bios->fmaxvco;
469 unsigned int bestdelta = UINT_MAX;
470 uint32_t bestclk = 0;
472 unsigned int crystal_strap_mask = 1 << 6;
473 /* open coded pNv->twoHeads test */
474 if (bios->chip_version > 0x10 && bios->chip_version != 0x15 &&
475 bios->chip_version != 0x1a && bios->chip_version != 0x20)
476 crystal_strap_mask |= 1 << 22;
477 switch (nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) & crystal_strap_mask) {
487 case (1 << 22 | 1 << 6):
493 /* this division verified for nv20, nv28 (Haiku), nv34 -- nv17 is guessed */
494 /* possibly correlated with introduction of 27MHz crystal */
495 if (bios->chip_version <= 0x16 || bios->chip_version == 0x20) {
511 if ((clk << maxlog2P) < minvco) {
512 minvco = clk << maxlog2P;
515 if (clk + clk/200 > maxvco) /* +0.5% */
516 maxvco = clk + clk/200;
518 /* NV34 goes maxlog2P->0, NV20 goes 0->maxlog2P */
519 for (log2P = 0; log2P <= maxlog2P; log2P++) {
527 /* nv_hw.c in nv driver uses 7 and 8 for minM */
528 for (M = 1; M <= maxM; M++) {
529 /* add crystal/2 to round better */
530 N = (clkP * M + crystal/2) / crystal;
531 if (N > 256) /* we lost */
534 /* more rounding additions */
535 calcclk = ((N * crystal + P/2) / P + M/2) / M;
536 delta = abs(calcclk - clk);
537 /* we do an exhaustive search rather than terminating
538 * on an optimality condition...
540 if (delta < bestdelta) {
543 *bestNM = N << 8 | M;
545 if (delta == 0) /* except this one */
556 Bool get_pll_limits(ScrnInfoPtr pScrn, uint32_t reg, struct pll_lims *pll_lim);
558 int getMNP_double(ScrnInfoPtr pScrn, uint32_t reg, int clk, int *bestNM1, int *bestNM2, int *bestlog2P)
560 /* Find M, N and P for a two stage PLL
562 * Note that some bioses (NV30+) have lookup tables of precomputed MNP
563 * values, but we're too lazy to use those atm
565 * "clk" parameter in kHz
566 * returns calculated clock
569 struct pll_lims pll_lim;
571 /* high regs (such as in the mac g5 table) are not -= 4 */
574 if (!get_pll_limits(pScrn, reg - 4, &pll_lim))
577 int minvco1 = pll_lim.vco1.minfreq, maxvco1 = pll_lim.vco1.maxfreq;
578 int minvco2 = pll_lim.vco2.minfreq, maxvco2 = pll_lim.vco2.maxfreq;
579 int minU1 = pll_lim.vco1.min_inputfreq, minU2 = pll_lim.vco2.min_inputfreq;
580 int maxU1 = pll_lim.vco1.max_inputfreq, maxU2 = pll_lim.vco2.max_inputfreq;
581 int minM1 = pll_lim.vco1.min_m, maxM1 = pll_lim.vco1.max_m;
582 int minN1 = pll_lim.vco1.min_n, maxN1 = pll_lim.vco1.max_n;
583 int minM2 = pll_lim.vco2.min_m, maxM2 = pll_lim.vco2.max_m;
584 int minN2 = pll_lim.vco2.min_n, maxN2 = pll_lim.vco2.max_n;
585 Bool fixedgain2 = (minM2 == maxM2 && minN2 == maxN2);
587 int M1, N1, M2, N2, log2P;
588 int clkP, calcclk1, calcclk2, calcclkout;
589 int delta, bestdelta = INT_MAX;
593 crystal = pll_lim.refclk;
595 switch (nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) & (1 << 22 | 1 << 6)) {
605 case (1 << 22 | 1 << 6):
610 int vco2 = (maxvco2 - maxvco2/200) / 2;
611 for (log2P = 0; log2P < 6 && clk <= (vco2 >> log2P); log2P++) /* log2P is maximum of 6 */
615 if (maxvco2 < clk + clk/200) /* +0.5% */
616 maxvco2 = clk + clk/200;
618 for (M1 = minM1; M1 <= maxM1; M1++) {
619 if (crystal/M1 < minU1)
621 if (crystal/M1 > maxU1)
624 for (N1 = minN1; N1 <= maxN1; N1++) {
625 calcclk1 = crystal * N1 / M1;
626 if (calcclk1 < minvco1)
628 if (calcclk1 > maxvco1)
631 for (M2 = minM2; M2 <= maxM2; M2++) {
632 if (calcclk1/M2 < minU2)
634 if (calcclk1/M2 > maxU2)
637 /* add calcclk1/2 to round better */
638 N2 = (clkP * M2 + calcclk1/2) / calcclk1;
645 if (N2/M2 < 4 || N2/M2 > 10)
648 calcclk2 = calcclk1 * N2 / M2;
649 if (calcclk2 < minvco2)
651 if (calcclk2 > maxvco2)
656 calcclkout = calcclk2 >> log2P;
657 delta = abs(calcclkout - clk);
658 /* we do an exhaustive search rather than terminating
659 * on an optimality condition...
661 if (delta < bestdelta) {
663 bestclk = calcclkout;
664 *bestNM1 = N1 << 8 | M1;
665 *bestNM2 = N2 << 8 | M2;
667 if (delta == 0) /* except this one */
677 static void setPLL_single(ScrnInfoPtr pScrn, uint32_t reg, int NM, int log2P)
679 bios_t *bios = &NVPTR(pScrn)->VBIOS;
680 uint32_t oldpll = nv32_rd(pScrn, reg);
681 uint32_t pll = (oldpll & 0xfff80000) | log2P << 16 | NM;
682 uint32_t saved1584 = 0;
686 return; /* already set */
688 /* FIXME needs verification on pre nv30 */
689 if (bios->chip_version >= 0x17 && bios->chip_version != 0x20) {
701 if (shift1584 >= 0) {
702 saved1584 = nv32_rd(pScrn, 0x00001584);
703 nv32_wr(pScrn, 0x00001584, (saved1584 & ~(0xf << shift1584)) | 1 << shift1584);
708 nv32_wr(pScrn, reg, (oldpll & 0xffff0000) | NM);
714 /* then write P as well */
715 nv32_wr(pScrn, reg, pll);
718 nv32_wr(pScrn, 0x00001584, saved1584);
721 static void setPLL_double_highregs(ScrnInfoPtr pScrn, uint32_t reg1, int NM1, int NM2, int log2P)
723 bios_t *bios = &NVPTR(pScrn)->VBIOS;
724 uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70);
725 uint32_t oldpll1 = nv32_rd(pScrn, reg1), oldpll2 = nv32_rd(pScrn, reg2);
726 uint32_t pll1 = (oldpll1 & 0xfff80000) | log2P << 16 | NM1;
727 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | NM2;
728 uint32_t saved1584 = 0, savedc040 = 0, maskc040 = ~0;
731 if (oldpll1 == pll1 && oldpll2 == pll2)
732 return; /* already set */
734 if (reg1 == 0x680500) {
736 maskc040 = ~(3 << 20);
738 if (reg1 == 0x680504) {
740 maskc040 = ~(3 << 22);
742 if (shift1584 >= 0) {
743 saved1584 = nv32_rd(pScrn, 0x1584);
744 nv32_wr(pScrn, 0x1584, (saved1584 & ~(0xf << shift1584)) | 1 << shift1584);
747 if (bios->chip_version >= 0x40) {
748 savedc040 = nv32_rd(pScrn, 0xc040);
749 nv32_wr(pScrn, 0xc040, savedc040 & maskc040);
751 if (reg1 == 0x680508)
752 nv32_wr(pScrn, 0x680580, nv32_rd(pScrn, 0x680580) & ~(1 << 28));
753 if (reg1 == 0x680520)
754 nv32_wr(pScrn, 0x680580, nv32_rd(pScrn, 0x680580) & ~(1 << 8));
757 nv32_wr(pScrn, reg2, pll2);
758 nv32_wr(pScrn, reg1, pll1);
760 if (shift1584 >= 0) {
761 nv32_wr(pScrn, 0x1584, saved1584);
762 if (bios->chip_version >= 0x40)
763 nv32_wr(pScrn, 0xc040, savedc040);
767 static void setPLL_double_lowregs(ScrnInfoPtr pScrn, uint32_t NMNMreg, int NM1, int NM2, int log2P)
769 /* When setting PLLs, there is a merry game of disabling and enabling
770 * various bits of hardware during the process. This function is a
771 * synthesis of six nv40 traces, nearly each card doing a subtly
772 * different thing. With luck all the necessary bits for each card are
773 * combined herein. Without luck it deviates from each card's formula
774 * so as to not work on any :)
777 uint32_t Preg = NMNMreg - 4;
778 uint32_t oldPval = nv32_rd(pScrn, Preg);
779 uint32_t NMNM = NM2 << 16 | NM1;
780 uint32_t Pval = (oldPval & ((Preg == 0x4020) ? ~(0x11 << 16) : ~(1 << 16))) | 0xc << 28 | log2P << 16;
781 uint32_t saved4600 = 0;
782 /* some cards have different maskc040s */
783 uint32_t maskc040 = ~(3 << 14), savedc040;
785 if (nv32_rd(pScrn, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval)
791 maskc040 = ~(3 << 26);
793 if (Preg == 0x4020) {
794 struct pll_lims pll_lim;
797 if (!get_pll_limits(pScrn, Preg, &pll_lim))
800 Pval2 = log2P + pll_lim.log2p_bias;
801 if (Pval2 > pll_lim.max_log2p_bias)
802 Pval2 = pll_lim.max_log2p_bias;
803 Pval |= 1 << 28 | Pval2 << 20;
805 saved4600 = nv32_rd(pScrn, 0x4600);
806 nv32_wr(pScrn, 0x4600, saved4600 | 1 << 31);
809 nv32_wr(pScrn, Preg, oldPval | 1 << 28);
810 nv32_wr(pScrn, Preg, Pval & ~(1 << 30));
811 if (Preg == 0x4020) {
812 Pval |= 1 << 23 | 1 << 12;
813 nv32_wr(pScrn, 0x4020, Pval & ~(3 << 30));
814 nv32_wr(pScrn, 0x4038, Pval & ~(3 << 30));
817 savedc040 = nv32_rd(pScrn, 0xc040);
818 nv32_wr(pScrn, 0xc040, savedc040 & maskc040);
820 nv32_wr(pScrn, NMNMreg, NMNM);
821 if (NMNMreg == 0x4024)
822 nv32_wr(pScrn, 0x403c, NMNM);
824 nv32_wr(pScrn, Preg, Pval);
825 if (Preg == 0x4020) {
827 nv32_wr(pScrn, 0x4020, Pval);
828 nv32_wr(pScrn, 0x4038, Pval);
829 nv32_wr(pScrn, 0x4600, saved4600);
832 nv32_wr(pScrn, 0xc040, savedc040);
834 if (Preg == 0x4020) {
835 nv32_wr(pScrn, 0x4020, Pval & ~(1 << 28));
836 nv32_wr(pScrn, 0x4038, Pval & ~(1 << 28));
840 static void setPLL(ScrnInfoPtr pScrn, bios_t *bios, uint32_t reg, uint32_t clk)
843 int NM1 = 0xbeef, NM2 = 0xdead, log2P;
845 if (bios->chip_version >= 0x40 || bios->chip_version == 0x31 || bios->chip_version == 0x36) {
846 getMNP_double(pScrn, reg, clk, &NM1, &NM2, &log2P);
848 setPLL_double_highregs(pScrn, reg, NM1, NM2, log2P);
850 setPLL_double_lowregs(pScrn, reg, NM1, NM2, log2P);
852 getMNP_single(pScrn, clk, &NM1, &log2P);
853 setPLL_single(pScrn, reg, NM1, log2P);
858 static Bool init_prog(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
860 /* INIT_PROG opcode: 0x31
862 * offset (8 bit): opcode
863 * offset + 1 (32 bit): reg
864 * offset + 5 (32 bit): and mask
865 * offset + 9 (8 bit): shift right
866 * offset + 10 (8 bit): number of configurations
867 * offset + 11 (32 bit): register
868 * offset + 15 (32 bit): configuration 1
871 * Starting at offset + 15 there are "number of configurations"
872 * 32 bit values. To find out which configuration value to use
873 * read "CRTC reg" on the CRTC controller with index "CRTC index"
874 * and bitwise AND this value with "and mask" and then bit shift the
875 * result "shift right" bits to the right.
876 * Assign "register" with appropriate configuration value.
879 CARD32 reg = *((CARD32 *) (&bios->data[offset + 1]));
880 CARD32 and = *((CARD32 *) (&bios->data[offset + 5]));
881 CARD8 shiftr = *((CARD8 *) (&bios->data[offset + 9]));
882 CARD8 nr = *((CARD8 *) (&bios->data[offset + 10]));
883 CARD32 reg2 = *((CARD32 *) (&bios->data[offset + 11]));
885 CARD32 configval, tmp;
887 if (iexec->execute) {
888 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: REG: 0x%04X\n", offset,
891 tmp = nv32_rd(pScrn, reg);
892 configuration = (tmp & and) >> shiftr;
894 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONFIGURATION TO USE: 0x%02X\n",
895 offset, configuration);
897 if (configuration <= nr) {
900 *((CARD32 *) (&bios->data[offset + 15 + configuration * 4]));
902 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: REG: 0x%08X, VALUE: 0x%08X\n", offset,
905 tmp = nv32_rd(pScrn, reg2);
906 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CURRENT VALUE IS: 0x%08X\n",
908 nv32_wr(pScrn, reg2, configval);
915 static Bool init_io_restrict_prog(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
917 /* INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
919 * offset (8 bit): opcode
920 * offset + 1 (16 bit): CRTC port
921 * offset + 3 (8 bit): CRTC index
922 * offset + 4 (8 bit): mask
923 * offset + 5 (8 bit): shift
924 * offset + 6 (8 bit): count
925 * offset + 7 (32 bit): register
926 * offset + 11 (32 bit): configuration 1
929 * Starting at offset + 11 there are "count" 32 bit values.
930 * To find out which value to use read index "CRTC index" on "CRTC port",
931 * AND this value with "mask" and then bit shift right "shift" bits.
932 * Read the appropriate value using this index and write to "register"
935 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
936 uint8_t crtcindex = bios->data[offset + 3];
937 uint8_t mask = bios->data[offset + 4];
938 uint8_t shift = bios->data[offset + 5];
939 uint8_t count = bios->data[offset + 6];
940 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7])));
948 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
949 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
950 offset, crtcport, crtcindex, mask, shift, count, reg);
952 config = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) >> shift;
953 if (config > count) {
954 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
955 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
956 offset, config, count);
960 configval = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 11 + config * 4])));
963 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
964 "0x%04X: Writing config %02X\n", offset, config);
966 nv32_wr(pScrn, reg, configval);
971 static Bool init_repeat(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
973 /* INIT_REPEAT opcode: 0x33 ('3')
975 * offset (8 bit): opcode
976 * offset + 1 (8 bit): count
978 * Execute script following this opcode up to INIT_REPEAT_END
982 uint8_t count = bios->data[offset + 1];
985 /* no iexec->execute check by design */
987 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
988 "0x%04X: REPEATING FOLLOWING SEGMENT %d TIMES\n",
991 iexec->repeat = TRUE;
993 /* count - 1, as the script block will execute once when we leave this
994 * opcode -- this is compatible with bios behaviour as:
995 * a) the block is always executed at least once, even if count == 0
996 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
999 for (i = 0; i < count - 1; i++)
1000 parse_init_table(pScrn, bios, offset + 2, iexec);
1002 iexec->repeat = FALSE;
1007 static Bool init_io_restrict_pll(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1009 /* INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
1011 * offset (8 bit): opcode
1012 * offset + 1 (16 bit): CRTC port
1013 * offset + 3 (8 bit): CRTC index
1014 * offset + 4 (8 bit): mask
1015 * offset + 5 (8 bit): shift
1016 * offset + 6 (8 bit): IO flag condition index
1017 * offset + 7 (8 bit): count
1018 * offset + 8 (32 bit): register
1019 * offset + 12 (16 bit): frequency 1
1022 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
1023 * Set PLL register "register" to coefficients for frequency n,
1024 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1025 * "mask" and shifted right by "shift". If "IO flag condition index" > 0,
1026 * and condition met, double frequency before setting it.
1029 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1030 uint8_t crtcindex = bios->data[offset + 3];
1031 uint8_t mask = bios->data[offset + 4];
1032 uint8_t shift = bios->data[offset + 5];
1033 int8_t io_flag_condition_idx = bios->data[offset + 6];
1034 uint8_t count = bios->data[offset + 7];
1035 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 8])));
1039 if (!iexec->execute)
1042 if (DEBUGLEVEL >= 6)
1043 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1044 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, IO Flag Condition: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1045 offset, crtcport, crtcindex, mask, shift, io_flag_condition_idx, count, reg);
1047 config = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) >> shift;
1048 if (config > count) {
1049 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1050 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1051 offset, config, count);
1055 freq = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 12 + config * 2])));
1057 if (io_flag_condition_idx > 0) {
1058 if (io_flag_condition(pScrn, bios, offset, io_flag_condition_idx)) {
1059 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1060 "0x%04X: CONDITION FULFILLED - FREQ DOUBLED\n", offset);
1063 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1064 "0x%04X: CONDITION IS NOT FULFILLED. FREQ UNCHANGED\n", offset);
1067 if (DEBUGLEVEL >= 6)
1068 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1069 "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
1070 offset, reg, config, freq);
1072 setPLL(pScrn, bios, reg, freq * 10);
1077 static Bool init_end_repeat(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1079 /* INIT_END_REPEAT opcode: 0x36 ('6')
1081 * offset (8 bit): opcode
1083 * Marks the end of the block for INIT_REPEAT to repeat
1086 /* no iexec->execute check by design */
1088 /* iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
1089 * we're not in repeat mode
1097 static Bool init_copy(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1099 /* INIT_COPY opcode: 0x37 ('7')
1101 * offset (8 bit): opcode
1102 * offset + 1 (32 bit): register
1103 * offset + 5 (8 bit): shift
1104 * offset + 6 (8 bit): srcmask
1105 * offset + 7 (16 bit): CRTC port
1106 * offset + 9 (8 bit): CRTC index
1107 * offset + 10 (8 bit): mask
1109 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
1110 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC port
1113 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1114 uint8_t shift = bios->data[offset + 5];
1115 uint8_t srcmask = bios->data[offset + 6];
1116 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 7])));
1117 uint8_t crtcindex = bios->data[offset + 9];
1118 uint8_t mask = bios->data[offset + 10];
1122 if (!iexec->execute)
1125 if (DEBUGLEVEL >= 6)
1126 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1127 "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1128 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1130 data = nv32_rd(pScrn, reg);
1135 data <<= (0x100 - shift);
1139 crtcdata = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) | (uint8_t)data;
1140 nv_idx_port_wr(pScrn, crtcport, crtcindex, crtcdata);
1145 static Bool init_not(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1147 /* INIT_NOT opcode: 0x38 ('8')
1149 * offset (8 bit): opcode
1151 * Invert the current execute / no-execute condition (i.e. "else")
1154 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1155 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
1157 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1158 "0x%04X: ------ EXECUTING FOLLOWING COMMANDS ------\n", offset);
1160 iexec->execute = !iexec->execute;
1164 static Bool init_io_flag_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1166 /* INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1168 * offset (8 bit): opcode
1169 * offset + 1 (8 bit): condition number
1171 * Check condition "condition number" in the IO flag condition table.
1172 * If condition not met skip subsequent opcodes until condition
1173 * is inverted (INIT_NOT), or we hit INIT_RESUME
1176 uint8_t cond = bios->data[offset + 1];
1178 if (!iexec->execute)
1181 if (io_flag_condition(pScrn, bios, offset, cond))
1182 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1183 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n", offset);
1185 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1186 "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
1187 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1188 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
1189 iexec->execute = FALSE;
1195 Bool init_idx_addr_latched(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1197 /* INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1199 * offset (8 bit): opcode
1200 * offset + 1 (32 bit): control register
1201 * offset + 5 (32 bit): data register
1202 * offset + 9 (32 bit): mask
1203 * offset + 13 (32 bit): data
1204 * offset + 17 (8 bit): count
1205 * offset + 18 (8 bit): address 1
1206 * offset + 19 (8 bit): data 1
1209 * For each of "count" address and data pairs, write "data n" to "data register",
1210 * read the current value of "control register", and write it back once ANDed
1211 * with "mask", ORed with "data", and ORed with "address n"
1214 uint32_t controlreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1215 uint32_t datareg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1216 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
1217 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 13])));
1218 uint8_t count = bios->data[offset + 17];
1222 if (!iexec->execute)
1225 if (DEBUGLEVEL >= 6)
1226 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1227 "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1228 offset, controlreg, datareg, mask, data, count);
1230 for (i = 0; i < count; i++) {
1231 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1232 uint8_t instdata = bios->data[offset + 19 + i * 2];
1234 if (DEBUGLEVEL >= 6)
1235 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1236 "0x%04X: Address: 0x%02X, Data: 0x%02X\n", offset, instaddress, instdata);
1238 nv32_wr(pScrn, datareg, instdata);
1239 value = (nv32_rd(pScrn, controlreg) & mask) | data | instaddress;
1240 nv32_wr(pScrn, controlreg, value);
1246 static Bool init_io_restrict_pll2(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1248 /* INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1250 * offset (8 bit): opcode
1251 * offset + 1 (16 bit): CRTC port
1252 * offset + 3 (8 bit): CRTC index
1253 * offset + 4 (8 bit): mask
1254 * offset + 5 (8 bit): shift
1255 * offset + 6 (8 bit): count
1256 * offset + 7 (32 bit): register
1257 * offset + 11 (32 bit): frequency 1
1260 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1261 * Set PLL register "register" to coefficients for frequency n,
1262 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1263 * "mask" and shifted right by "shift".
1266 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1267 uint8_t crtcindex = bios->data[offset + 3];
1268 uint8_t mask = bios->data[offset + 4];
1269 uint8_t shift = bios->data[offset + 5];
1270 uint8_t count = bios->data[offset + 6];
1271 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7])));
1275 if (!iexec->execute)
1278 if (DEBUGLEVEL >= 6)
1279 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1280 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1281 offset, crtcport, crtcindex, mask, shift, count, reg);
1286 config = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) >> shift;
1287 if (config > count) {
1288 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1289 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1290 offset, config, count);
1294 freq = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 11 + config * 4])));
1296 if (DEBUGLEVEL >= 6)
1297 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1298 "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1299 offset, reg, config, freq);
1301 setPLL(pScrn, bios, reg, freq);
1306 static Bool init_pll2(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1308 /* INIT_PLL2 opcode: 0x4B ('K')
1310 * offset (8 bit): opcode
1311 * offset + 1 (32 bit): register
1312 * offset + 5 (32 bit): freq
1314 * Set PLL register "register" to coefficients for frequency "freq"
1317 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1318 uint32_t freq = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1320 if (!iexec->execute)
1323 if (DEBUGLEVEL >= 6)
1324 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1325 "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1328 setPLL(pScrn, bios, reg, freq);
1333 static uint32_t get_tmds_index_reg(ScrnInfoPtr pScrn, uint8_t mlv)
1335 /* For mlv < 0x80, it is an index into a table of TMDS base addresses
1336 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by CR58 for CR57 = 0
1337 * to index a table of offsets to the basic 0x6808b0 address
1338 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by CR58 for CR57 = 0
1339 * to index a table of offsets to the basic 0x6808b0 address, and then flip the offset by 8
1342 NVPtr pNv = NVPTR(pScrn);
1343 int pramdac_offset[13] = {0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000};
1344 uint32_t pramdac_table[4] = {0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8};
1347 /* here we assume that the DCB table has already been parsed */
1350 /* This register needs to be written to set index for reading CR58 */
1351 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, 0x57, 0);
1352 dcb_entry = nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, 0x58);
1353 if (dcb_entry > pNv->dcb_table.entries) {
1354 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1355 "CR58 doesn't have a valid DCB entry currently (%02X)\n", dcb_entry);
1358 dacoffset = pramdac_offset[pNv->dcb_table.entry[dcb_entry].or];
1361 return (0x6808b0 + dacoffset);
1363 if (mlv > (sizeof(pramdac_table) / sizeof(uint32_t))) {
1364 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1365 "Magic Lookup Value too big (%02X)\n", mlv);
1368 return pramdac_table[mlv];
1372 static Bool init_tmds(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1374 /* INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1376 * offset (8 bit): opcode
1377 * offset + 1 (8 bit): magic lookup value
1378 * offset + 2 (8 bit): TMDS address
1379 * offset + 3 (8 bit): mask
1380 * offset + 4 (8 bit): data
1382 * Read the data reg for TMDS address "TMDS address", AND it with mask
1383 * and OR it with data, then write it back
1384 * "magic lookup value" determines which TMDS base address register is used --
1385 * see get_tmds_index_reg()
1388 uint8_t mlv = bios->data[offset + 1];
1389 uint32_t tmdsaddr = bios->data[offset + 2];
1390 uint8_t mask = bios->data[offset + 3];
1391 uint8_t data = bios->data[offset + 4];
1392 uint32_t reg, value;
1394 if (!iexec->execute)
1397 if (DEBUGLEVEL >= 6)
1398 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1399 "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1400 offset, mlv, tmdsaddr, mask, data);
1402 reg = get_tmds_index_reg(pScrn, mlv);
1404 nv32_wr(pScrn, reg, tmdsaddr | 0x10000);
1405 value = (nv32_rd(pScrn, reg + 4) & mask) | data;
1406 nv32_wr(pScrn, reg + 4, value);
1407 nv32_wr(pScrn, reg, tmdsaddr);
1412 Bool init_zm_tmds_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1414 /* INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1416 * offset (8 bit): opcode
1417 * offset + 1 (8 bit): magic lookup value
1418 * offset + 2 (8 bit): count
1419 * offset + 3 (8 bit): addr 1
1420 * offset + 4 (8 bit): data 1
1423 * For each of "count" TMDS address and data pairs write "data n" to "addr n"
1424 * "magic lookup value" determines which TMDS base address register is used --
1425 * see get_tmds_index_reg()
1428 uint8_t mlv = bios->data[offset + 1];
1429 uint8_t count = bios->data[offset + 2];
1433 if (!iexec->execute)
1436 if (DEBUGLEVEL >= 6)
1437 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1438 "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1439 offset, mlv, count);
1441 reg = get_tmds_index_reg(pScrn, mlv);
1443 for (i = 0; i < count; i++) {
1444 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1445 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1447 nv32_wr(pScrn, reg + 4, tmdsdata);
1448 nv32_wr(pScrn, reg, tmdsaddr);
1454 Bool init_cr_idx_adr_latch(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1456 /* INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1458 * offset (8 bit): opcode
1459 * offset + 1 (8 bit): CRTC index1
1460 * offset + 2 (8 bit): CRTC index2
1461 * offset + 3 (8 bit): baseaddr
1462 * offset + 4 (8 bit): count
1463 * offset + 5 (8 bit): data 1
1466 * For each of "count" address and data pairs, write "baseaddr + n" to
1467 * "CRTC index1" and "data n" to "CRTC index2"
1468 * Once complete, restore initial value read from "CRTC index1"
1470 uint8_t crtcindex1 = bios->data[offset + 1];
1471 uint8_t crtcindex2 = bios->data[offset + 2];
1472 uint8_t baseaddr = bios->data[offset + 3];
1473 uint8_t count = bios->data[offset + 4];
1474 uint8_t oldaddr, data;
1477 if (!iexec->execute)
1480 if (DEBUGLEVEL >= 6)
1481 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1482 "0x%04X: Index1: 0x%02X, Index2: 0x%02X, BaseAddr: 0x%02X, Count: 0x%02X\n",
1483 offset, crtcindex1, crtcindex2, baseaddr, count);
1485 oldaddr = nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, crtcindex1);
1487 for (i = 0; i < count; i++) {
1488 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex1, baseaddr + i);
1490 data = bios->data[offset + 5 + i];
1491 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex2, data);
1494 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex1, oldaddr);
1499 Bool init_cr(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1501 /* INIT_CR opcode: 0x52 ('R')
1503 * offset (8 bit): opcode
1504 * offset + 1 (8 bit): CRTC index
1505 * offset + 2 (8 bit): mask
1506 * offset + 3 (8 bit): data
1508 * Assign the value of at "CRTC index" ANDed with mask and ORed with data
1509 * back to "CRTC index"
1512 uint8_t crtcindex = bios->data[offset + 1];
1513 uint8_t mask = bios->data[offset + 2];
1514 uint8_t data = bios->data[offset + 3];
1517 if (!iexec->execute)
1520 if (DEBUGLEVEL >= 6)
1521 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1522 "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1523 offset, crtcindex, mask, data);
1525 value = (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, crtcindex) & mask) | data;
1526 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex, value);
1531 static Bool init_zm_cr(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1533 /* INIT_ZM_CR opcode: 0x53 ('S')
1535 * offset (8 bit): opcode
1536 * offset + 1 (8 bit): CRTC index
1537 * offset + 2 (8 bit): value
1539 * Assign "value" to CRTC register with index "CRTC index".
1542 uint8_t crtcindex = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1543 uint8_t data = bios->data[offset + 2];
1545 if (!iexec->execute)
1548 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex, data);
1553 static Bool init_zm_cr_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1555 /* INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1557 * offset (8 bit): opcode
1558 * offset + 1 (8 bit): count
1559 * offset + 2 (8 bit): CRTC index 1
1560 * offset + 3 (8 bit): value 1
1563 * For "count", assign "value n" to CRTC register with index "CRTC index n".
1566 uint8_t count = bios->data[offset + 1];
1569 if (!iexec->execute)
1572 for (i = 0; i < count; i++)
1573 init_zm_cr(pScrn, bios, offset + 2 + 2 * i - 1, iexec);
1578 static Bool init_condition_time(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1580 /* INIT_CONDITION_TIME opcode: 0x56 ('V')
1582 * offset (8 bit): opcode
1583 * offset + 1 (8 bit): condition number
1584 * offset + 2 (8 bit): retries / 50
1586 * Check condition "condition number" in the condition table.
1587 * The condition table entry has 4 bytes for the address of the
1588 * register to check, 4 bytes for a mask and 4 for a test value.
1589 * If condition not met sleep for 2ms, and repeat upto "retries" times.
1590 * If still not met after retries, clear execution flag for this table.
1593 uint8_t cond = bios->data[offset + 1];
1594 uint16_t retries = bios->data[offset + 2];
1595 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
1596 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[condptr])));
1597 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 4])));
1598 uint32_t cmpval = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 8])));
1601 if (!iexec->execute)
1606 if (DEBUGLEVEL >= 6)
1607 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1608 "0x%04X: Cond: 0x%02X, Retries: 0x%02X\n", offset, cond, retries);
1610 for (; retries > 0; retries--) {
1611 data = nv32_rd(pScrn, reg) & mask;
1613 if (DEBUGLEVEL >= 6)
1614 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1615 "0x%04X: Checking if 0x%08X equals 0x%08X\n",
1616 offset, data, cmpval);
1618 if (data != cmpval) {
1619 if (DEBUGLEVEL >= 6)
1620 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1621 "0x%04X: Condition not met, sleeping for 2ms\n", offset);
1624 if (DEBUGLEVEL >= 6)
1625 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1626 "0x%04X: Condition met, continuing\n", offset);
1631 if (data != cmpval) {
1632 if (DEBUGLEVEL >= 6)
1633 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1634 "0x%04X: Condition still not met, skiping following opcodes\n", offset);
1635 iexec->execute = FALSE;
1641 static Bool init_zm_reg_sequence(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1643 /* INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1645 * offset (8 bit): opcode
1646 * offset + 1 (32 bit): base register
1647 * offset + 5 (8 bit): count
1648 * offset + 6 (32 bit): value 1
1651 * Starting at offset + 6 there are "count" 32 bit values.
1652 * For "count" iterations set "base register" + 4 * current_iteration
1653 * to "value current_iteration"
1656 uint32_t basereg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1657 uint32_t count = bios->data[offset + 5];
1660 if (!iexec->execute)
1663 if (DEBUGLEVEL >= 6)
1664 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1665 "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1666 offset, basereg, count);
1668 for (i = 0; i < count; i++) {
1669 uint32_t reg = basereg + i * 4;
1670 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 6 + i * 4])));
1672 nv32_wr(pScrn, reg, data);
1679 static Bool init_indirect_reg(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
1681 /* INIT_INDIRECT_REG opcode: 0x5A
1683 * offset (8 bit): opcode
1684 * offset + 1 (32 bit): register
1685 * offset + 5 (16 bit): adress offset (in bios)
1687 * Lookup value at offset data in the bios and write it to reg
1689 CARD32 reg = *((CARD32 *) (&bios->data[offset + 1]));
1690 CARD16 data = le16_to_cpu(*((CARD16 *) (&bios->data[offset + 5])));
1691 CARD32 data2 = bios->data[data];
1693 if (iexec->execute) {
1694 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1695 "0x%04X: REG: 0x%04X, DATA AT: 0x%04X, VALUE IS: 0x%08X\n",
1696 offset, reg, data, data2);
1698 if (DEBUGLEVEL >= 6) {
1700 tmpval = nv32_rd(pScrn, reg);
1701 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CURRENT VALUE IS: 0x%08X\n", offset, tmpval);
1704 nv32_wr(pScrn, reg, data2);
1710 static Bool init_sub_direct(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1712 /* INIT_SUB_DIRECT opcode: 0x5B ('[')
1714 * offset (8 bit): opcode
1715 * offset + 1 (16 bit): subroutine offset (in bios)
1717 * Calls a subroutine that will execute commands until INIT_DONE
1721 uint16_t sub_offset = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1723 if (!iexec->execute)
1726 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: EXECUTING SUB-ROUTINE AT 0x%04X\n",
1727 offset, sub_offset);
1729 parse_init_table(pScrn, bios, sub_offset, iexec);
1731 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: END OF SUB-ROUTINE AT 0x%04X\n",
1732 offset, sub_offset);
1737 static Bool init_copy_nv_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1739 /* INIT_COPY_NV_REG opcode: 0x5F ('_')
1741 * offset (8 bit): opcode
1742 * offset + 1 (32 bit): src reg
1743 * offset + 5 (8 bit): shift
1744 * offset + 6 (32 bit): src mask
1745 * offset + 10 (32 bit): xor
1746 * offset + 14 (32 bit): dst reg
1747 * offset + 18 (32 bit): dst mask
1749 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
1750 * "src mask", then XOR with "xor". Write this OR'd with
1751 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
1754 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
1755 uint8_t shift = bios->data[offset + 5];
1756 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
1757 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
1758 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
1759 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
1760 uint32_t srcvalue, dstvalue;
1762 if (!iexec->execute)
1765 if (DEBUGLEVEL >= 6)
1766 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1767 "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
1768 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
1770 srcvalue = nv32_rd(pScrn, srcreg);
1775 srcvalue <<= (0x100 - shift);
1777 srcvalue = (srcvalue & srcmask) ^ xor;
1779 dstvalue = nv32_rd(pScrn, dstreg) & dstmask;
1781 nv32_wr(pScrn, dstreg, dstvalue | srcvalue);
1786 static Bool init_zm_index_io(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1788 /* INIT_ZM_INDEX_IO opcode: 0x62 ('b')
1790 * offset (8 bit): opcode
1791 * offset + 1 (16 bit): CRTC port
1792 * offset + 3 (8 bit): CRTC index
1793 * offset + 4 (8 bit): data
1795 * Write "data" to index "CRTC index" of "CRTC port"
1797 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
1798 uint8_t crtcindex = bios->data[offset + 3];
1799 uint8_t data = bios->data[offset + 4];
1801 if (!iexec->execute)
1804 nv_idx_port_wr(pScrn, crtcport, crtcindex, data);
1809 static Bool init_compute_mem(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1811 /* INIT_COMPUTE_MEM opcode: 0x63 ('c')
1813 * offset (8 bit): opcode
1815 * This opcode is meant to set NV_PFB_CFG0 (0x100200) appropriately so
1816 * that the hardware can correctly calculate how much VRAM it has
1817 * (and subsequently report that value in 0x10020C)
1819 * The implementation of this opcode in general consists of two parts:
1820 * 1) determination of the memory bus width
1821 * 2) determination of how many of the card's RAM pads have ICs attached
1823 * 1) is done by a cunning combination of writes to offsets 0x1c and
1824 * 0x3c in the framebuffer, and seeing whether the written values are
1825 * read back correctly. This then affects bits 4-7 of NV_PFB_CFG0
1827 * 2) is done by a cunning combination of writes to an offset slightly
1828 * less than the maximum memory reported by 0x10020C, then seeing if
1829 * the test pattern can be read back. This then affects bits 12-15 of
1832 * In this context a "cunning combination" may include multiple reads
1833 * and writes to varying locations, often alternating the test pattern
1834 * and 0, doubtless to make sure buffers are filled, residual charges
1835 * on tracks are removed etc.
1837 * Unfortunately, the "cunning combination"s mentioned above, and the
1838 * changes to the bits in NV_PFB_CFG0 differ with nearly every bios
1841 * Therefore, we cheat and assume the value of NV_PFB_CFG0 with which
1842 * we started was correct, and use that instead
1845 /* no iexec->execute check by design */
1847 /* on every card I've seen, this step gets done for us earlier in the init scripts
1848 uint8_t crdata = nv_idx_port_rd(pScrn, VGA_SEQ_INDEX, 0x01);
1849 nv_idx_port_wr(pScrn, VGA_SEQ_INDEX, 0x01, crdata | 0x20);
1852 /* this also has probably been done in the scripts, but an mmio trace of
1853 * s3 resume shows nvidia doing it anyway (unlike the VGA_SEQ_INDEX write)
1855 nv32_wr(pScrn, NV_PFB_REFCTRL, NV_PFB_REFCTRL_VALID_1);
1857 /* write back the saved configuration value */
1858 nv32_wr(pScrn, NV_PFB_CFG0, saved_nv_pfb_cfg0);
1863 static Bool init_reset(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1865 /* INIT_RESET opcode: 0x65 ('e')
1867 * offset (8 bit): opcode
1868 * offset + 1 (32 bit): register
1869 * offset + 5 (32 bit): value1
1870 * offset + 9 (32 bit): value2
1872 * Assign "value1" to "register", then assign "value2" to "register"
1875 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
1876 uint32_t value1 = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
1877 uint32_t value2 = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
1878 uint32_t pci_nv_19, pci_nv_20;
1880 /* no iexec->execute check by design */
1882 pci_nv_19 = nv32_rd(pScrn, NV_PBUS_PCI_NV_19);
1883 nv32_wr(pScrn, NV_PBUS_PCI_NV_19, 0);
1884 nv32_wr(pScrn, reg, value1);
1888 nv32_wr(pScrn, reg, value2);
1889 nv32_wr(pScrn, NV_PBUS_PCI_NV_19, pci_nv_19);
1891 pci_nv_20 = nv32_rd(pScrn, NV_PBUS_PCI_NV_20);
1892 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
1893 nv32_wr(pScrn, NV_PBUS_PCI_NV_20, pci_nv_20);
1899 static Bool init_index_io8(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
1901 /* INIT_INDEX_IO8 opcode: 0x69
1903 * offset (8 bit): opcode
1904 * offset + 1 (16 bit): CRTC reg
1905 * offset + 3 (8 bit): and mask
1906 * offset + 4 (8 bit): or with
1911 NVPtr pNv = NVPTR(pScrn);
1912 volatile CARD8 *ptr = crtchead ? pNv->PCIO1 : pNv->PCIO0;
1913 CARD16 reg = le16_to_cpu(*((CARD16 *)(&bios->data[offset + 1])));
1914 CARD8 and = *((CARD8 *)(&bios->data[offset + 3]));
1915 CARD8 or = *((CARD8 *)(&bios->data[offset + 4]));
1918 if (iexec->execute) {
1919 data = (VGA_RD08(ptr, reg) & and) | or;
1921 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1922 "0x%04X: CRTC REG: 0x%04X, VALUE: 0x%02X\n",
1924 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CURRENT VALUE IS: 0x%02X\n", offset,
1925 VGA_RD08(ptr, reg));
1927 #ifdef PERFORM_WRITE
1928 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "init_index_io8 crtcreg 0x%X value 0x%X\n",reg,data);
1930 VGA_WR08(ptr, reg, data);
1937 static Bool init_sub(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
1939 /* INIT_SUB opcode: 0x6B ('k')
1941 * offset (8 bit): opcode
1942 * offset + 1 (8 bit): script number
1944 * Execute script number "script number", as a subroutine
1947 uint8_t sub = bios->data[offset + 1];
1949 if (!iexec->execute)
1952 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1953 "0x%04X: EXECUTING SUB-SCRIPT %d\n", offset, sub);
1955 parse_init_table(pScrn, bios,
1956 le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + sub * 2]))),
1959 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1960 "0x%04X: END OF SUB-SCRIPT %d\n", offset, sub);
1966 static Bool init_ram_condition(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
1968 /* INIT_RAM_CONDITION opcode: 0x6D
1970 * offset (8 bit): opcode
1971 * offset + 1 (8 bit): and mask
1972 * offset + 2 (8 bit): cmpval
1974 * Test if (NV_PFB_BOOT & and mask) matches cmpval
1976 NVPtr pNv = NVPTR(pScrn);
1977 CARD8 and = *((CARD8 *) (&bios->data[offset + 1]));
1978 CARD8 cmpval = *((CARD8 *) (&bios->data[offset + 2]));
1981 if (iexec->execute) {
1982 data=(pNv->PFB[NV_PFB_BOOT/4])∧
1984 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1985 "0x%04X: CHECKING IF REGVAL: 0x%08X equals COND: 0x%08X\n",
1986 offset, data, cmpval);
1988 if (data == cmpval) {
1989 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1990 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n",
1993 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
1994 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1995 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
1996 iexec->execute = FALSE;
2003 static Bool init_nv_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2005 /* INIT_NV_REG opcode: 0x6E ('n')
2007 * offset (8 bit): opcode
2008 * offset + 1 (32 bit): register
2009 * offset + 5 (32 bit): mask
2010 * offset + 9 (32 bit): data
2012 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2015 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2016 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
2017 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 9])));
2019 if (!iexec->execute)
2022 if (DEBUGLEVEL >= 6)
2023 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2024 "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2025 offset, reg, mask, data);
2027 nv32_wr(pScrn, reg, (nv32_rd(pScrn, reg) & mask) | data);
2032 static Bool init_macro(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2034 /* INIT_MACRO opcode: 0x6F ('o')
2036 * offset (8 bit): opcode
2037 * offset + 1 (8 bit): macro number
2039 * Look up macro index "macro number" in the macro index table.
2040 * The macro index table entry has 1 byte for the index in the macro table,
2041 * and 1 byte for the number of times to repeat the macro.
2042 * The macro table entry has 4 bytes for the register address and
2043 * 4 bytes for the value to write to that register
2046 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2047 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2048 uint8_t macro_tbl_idx = bios->data[tmp];
2049 uint8_t count = bios->data[tmp + 1];
2053 if (!iexec->execute)
2056 if (DEBUGLEVEL >= 6)
2057 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2058 "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, Count: 0x%02X\n",
2059 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2061 for (i = 0; i < count; i++) {
2062 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2064 reg = le32_to_cpu(*((uint32_t *)(&bios->data[macroentryptr])));
2065 data = le32_to_cpu(*((uint32_t *)(&bios->data[macroentryptr + 4])));
2067 nv32_wr(pScrn, reg, data);
2073 static Bool init_done(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2075 /* INIT_DONE opcode: 0x71 ('q')
2077 * offset (8 bit): opcode
2079 * End the current script
2082 /* mild retval abuse to stop parsing this table */
2086 static Bool init_resume(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2088 /* INIT_RESUME opcode: 0x72 ('r')
2090 * offset (8 bit): opcode
2092 * End the current execute / no-execute condition
2098 iexec->execute = TRUE;;
2099 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2100 "0x%04X: ---- EXECUTING FOLLOWING COMMANDS ----\n", offset);
2106 static Bool init_ram_condition2(ScrnInfoPtr pScrn, bios_t *bios, CARD16 offset, init_exec_t *iexec)
2108 /* INIT_RAM_CONDITION2 opcode: 0x73
2110 * offset (8 bit): opcode
2111 * offset + 1 (8 bit): and mask
2112 * offset + 2 (8 bit): cmpval
2114 * Test if (NV_EXTDEV_BOOT & and mask) matches cmpval
2116 NVPtr pNv = NVPTR(pScrn);
2117 CARD32 and = *((CARD32 *) (&bios->data[offset + 1]));
2118 CARD32 cmpval = *((CARD32 *) (&bios->data[offset + 5]));
2121 if (iexec->execute) {
2122 data=(nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT))∧
2124 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2125 "0x%04X: CHECKING IF REGVAL: 0x%08X equals COND: 0x%08X\n",
2126 offset, data, cmpval);
2128 if (data == cmpval) {
2129 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2130 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n",
2133 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
2134 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2135 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
2136 iexec->execute = FALSE;
2143 static Bool init_time(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2145 /* INIT_TIME opcode: 0x74 ('t')
2147 * offset (8 bit): opcode
2148 * offset + 1 (16 bit): time
2150 * Sleep for "time" microseconds.
2153 uint16_t time = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
2155 if (!iexec->execute)
2158 if (DEBUGLEVEL >= 6)
2159 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2160 "0x%04X: Sleeping for 0x%04X microseconds\n", offset, time);
2167 static Bool init_condition(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2169 /* INIT_CONDITION opcode: 0x75 ('u')
2171 * offset (8 bit): opcode
2172 * offset + 1 (8 bit): condition number
2174 * Check condition "condition number" in the condition table.
2175 * The condition table entry has 4 bytes for the address of the
2176 * register to check, 4 bytes for a mask and 4 for a test value.
2177 * If condition not met skip subsequent opcodes until condition
2178 * is inverted (INIT_NOT), or we hit INIT_RESUME
2181 uint8_t cond = bios->data[offset + 1];
2182 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
2183 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[condptr])));
2184 uint32_t mask = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 4])));
2185 uint32_t cmpval = le32_to_cpu(*((uint32_t *)(&bios->data[condptr + 8])));
2188 if (!iexec->execute)
2191 if (DEBUGLEVEL >= 6)
2192 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2193 "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X, Cmpval: 0x%08X\n",
2194 offset, cond, reg, mask, cmpval);
2196 data = nv32_rd(pScrn, reg) & mask;
2198 if (DEBUGLEVEL >= 6)
2199 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2200 "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2201 offset, data, cmpval);
2203 if (data == cmpval) {
2204 if (DEBUGLEVEL >= 6)
2205 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2206 "0x%04X: CONDITION FULFILLED - CONTINUING TO EXECUTE\n", offset);
2208 if (DEBUGLEVEL >= 6)
2209 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2210 "0x%04X: CONDITION IS NOT FULFILLED\n", offset);
2211 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2212 "0x%04X: ------ SKIPPING FOLLOWING COMMANDS ------\n", offset);
2213 iexec->execute = FALSE;
2219 static Bool init_index_io(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2221 /* INIT_INDEX_IO opcode: 0x78 ('x')
2223 * offset (8 bit): opcode
2224 * offset + 1 (16 bit): CRTC port
2225 * offset + 3 (8 bit): CRTC index
2226 * offset + 4 (8 bit): mask
2227 * offset + 5 (8 bit): data
2229 * Read value at index "CRTC index" on "CRTC port", AND with "mask", OR with "data", write-back
2232 uint16_t crtcport = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 1])));
2233 uint8_t crtcindex = bios->data[offset + 3];
2234 uint8_t mask = bios->data[offset + 4];
2235 uint8_t data = bios->data[offset + 5];
2238 if (!iexec->execute)
2241 if (DEBUGLEVEL >= 6)
2242 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2243 "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
2244 offset, crtcport, crtcindex, mask, data);
2246 value = (nv_idx_port_rd(pScrn, crtcport, crtcindex) & mask) | data;
2247 nv_idx_port_wr(pScrn, crtcport, crtcindex, value);
2252 static Bool init_pll(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2254 /* INIT_PLL opcode: 0x79 ('y')
2256 * offset (8 bit): opcode
2257 * offset + 1 (32 bit): register
2258 * offset + 5 (16 bit): freq
2260 * Set PLL register "register" to coefficients for frequency (10kHz) "freq"
2263 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2264 uint16_t freq = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 5])));
2266 if (!iexec->execute)
2269 if (DEBUGLEVEL >= 6)
2270 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2271 "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n",
2274 setPLL(pScrn, bios, reg, freq * 10);
2279 static Bool init_zm_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2281 /* INIT_ZM_REG opcode: 0x7A ('z')
2283 * offset (8 bit): opcode
2284 * offset + 1 (32 bit): register
2285 * offset + 5 (32 bit): value
2287 * Assign "value" to "register"
2290 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2291 uint32_t value = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
2293 if (!iexec->execute)
2296 nv32_wr(pScrn, reg, value);
2301 /* hack to avoid moving the itbl_entry array before this function */
2302 int init_ram_restrict_zm_reg_group_blocklen = 0;
2304 static Bool init_ram_restrict_zm_reg_group(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2306 /* INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
2308 * offset (8 bit): opcode
2309 * offset + 1 (32 bit): reg
2310 * offset + 5 (8 bit): regincrement
2311 * offset + 6 (8 bit): count
2312 * offset + 7 (32 bit): value 1,1
2315 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2316 * ram_restrict_table_ptr. The value read from here is 'n', and
2317 * "value 1,n" gets written to "reg". This repeats "count" times and on
2318 * each iteration 'm', "reg" increases by "regincrement" and
2319 * "value m,n" is used. The extent of n is limited by a number read
2320 * from the 'M' BIT table, herein called "blocklen"
2323 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2324 uint8_t regincrement = bios->data[offset + 5];
2325 uint8_t count = bios->data[offset + 6];
2326 uint32_t strap_ramcfg, data;
2331 /* previously set by 'M' BIT table */
2332 blocklen = init_ram_restrict_zm_reg_group_blocklen;
2334 if (!iexec->execute)
2338 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2339 "0x%04X: Zero block length - has the M table been parsed?\n", offset);
2343 strap_ramcfg = (nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
2344 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
2346 if (DEBUGLEVEL >= 6)
2347 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2348 "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
2349 offset, reg, regincrement, count, strap_ramcfg, index);
2351 for (i = 0; i < count; i++) {
2352 data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 7 + index * 4 + blocklen * i])));
2354 nv32_wr(pScrn, reg, data);
2356 reg += regincrement;
2362 static Bool init_copy_zm_reg(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2364 /* INIT_COPY_ZM_REG opcode: 0x90 ('')
2366 * offset (8 bit): opcode
2367 * offset + 1 (32 bit): src reg
2368 * offset + 5 (32 bit): dst reg
2370 * Put contents of "src reg" into "dst reg"
2373 uint32_t srcreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2374 uint32_t dstreg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 5])));
2376 if (!iexec->execute)
2379 nv32_wr(pScrn, dstreg, nv32_rd(pScrn, srcreg));
2384 static Bool init_zm_reg_group_addr_latched(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2386 /* INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
2388 * offset (8 bit): opcode
2389 * offset + 1 (32 bit): src reg
2390 * offset + 5 (8 bit): count
2391 * offset + 6 (32 bit): data 1
2394 * For each of "count" values write "data n" to "src reg"
2397 uint32_t reg = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 1])));
2398 uint8_t count = bios->data[offset + 5];
2401 if (!iexec->execute)
2404 for (i = 0; i < count; i++) {
2405 uint32_t data = le32_to_cpu(*((uint32_t *)(&bios->data[offset + 6 + 4 * i])));
2406 nv32_wr(pScrn, reg, data);
2412 static Bool init_reserved(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_t *iexec)
2414 /* INIT_RESERVED opcode: 0x92 ('')
2416 * offset (8 bit): opcode
2418 * Seemingly does nothing
2424 static init_tbl_entry_t itbl_entry[] = {
2425 /* command name , id , length , offset , mult , command handler */
2426 // { "INIT_PROG" , 0x31, 15 , 10 , 4 , init_prog },
2427 { "INIT_IO_RESTRICT_PROG" , 0x32, 11 , 6 , 4 , init_io_restrict_prog },
2428 { "INIT_REPEAT" , 0x33, 2 , 0 , 0 , init_repeat },
2429 { "INIT_IO_RESTRICT_PLL" , 0x34, 12 , 7 , 2 , init_io_restrict_pll },
2430 { "INIT_END_REPEAT" , 0x36, 1 , 0 , 0 , init_end_repeat },
2431 { "INIT_COPY" , 0x37, 11 , 0 , 0 , init_copy },
2432 { "INIT_NOT" , 0x38, 1 , 0 , 0 , init_not },
2433 { "INIT_IO_FLAG_CONDITION" , 0x39, 2 , 0 , 0 , init_io_flag_condition },
2434 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, 18 , 17 , 2 , init_idx_addr_latched },
2435 { "INIT_IO_RESTRICT_PLL2" , 0x4A, 11 , 6 , 4 , init_io_restrict_pll2 },
2436 { "INIT_PLL2" , 0x4B, 9 , 0 , 0 , init_pll2 },
2437 /* { "INIT_I2C_BYTE" , 0x4C, x , x , x , init_i2c_byte }, */
2438 /* { "INIT_ZM_I2C_BYTE" , 0x4D, x , x , x , init_zm_i2c_byte }, */
2439 /* { "INIT_ZM_I2C" , 0x4E, x , x , x , init_zm_i2c }, */
2440 { "INIT_TMDS" , 0x4F, 5 , 0 , 0 , init_tmds },
2441 { "INIT_ZM_TMDS_GROUP" , 0x50, 3 , 2 , 2 , init_zm_tmds_group },
2442 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, 5 , 4 , 1 , init_cr_idx_adr_latch },
2443 { "INIT_CR" , 0x52, 4 , 0 , 0 , init_cr },
2444 { "INIT_ZM_CR" , 0x53, 3 , 0 , 0 , init_zm_cr },
2445 { "INIT_ZM_CR_GROUP" , 0x54, 2 , 1 , 2 , init_zm_cr_group },
2446 { "INIT_CONDITION_TIME" , 0x56, 3 , 0 , 0 , init_condition_time },
2447 { "INIT_ZM_REG_SEQUENCE" , 0x58, 6 , 5 , 4 , init_zm_reg_sequence },
2448 // { "INIT_INDIRECT_REG" , 0x5A, 7 , 0 , 0 , init_indirect_reg },
2449 { "INIT_SUB_DIRECT" , 0x5B, 3 , 0 , 0 , init_sub_direct },
2450 { "INIT_COPY_NV_REG" , 0x5F, 22 , 0 , 0 , init_copy_nv_reg },
2451 { "INIT_ZM_INDEX_IO" , 0x62, 5 , 0 , 0 , init_zm_index_io },
2452 { "INIT_COMPUTE_MEM" , 0x63, 1 , 0 , 0 , init_compute_mem },
2453 { "INIT_RESET" , 0x65, 13 , 0 , 0 , init_reset },
2454 /* { "INIT_NEXT" , 0x66, x , x , x , init_next }, */
2455 /* { "INIT_NEXT" , 0x67, x , x , x , init_next }, */
2456 /* { "INIT_NEXT" , 0x68, x , x , x , init_next }, */
2457 // { "INIT_INDEX_IO8" , 0x69, 5 , 0 , 0 , init_index_io8 },
2458 { "INIT_SUB" , 0x6B, 2 , 0 , 0 , init_sub },
2459 // { "INIT_RAM_CONDITION" , 0x6D, 3 , 0 , 0 , init_ram_condition },
2460 { "INIT_NV_REG" , 0x6E, 13 , 0 , 0 , init_nv_reg },
2461 { "INIT_MACRO" , 0x6F, 2 , 0 , 0 , init_macro },
2462 { "INIT_DONE" , 0x71, 1 , 0 , 0 , init_done },
2463 { "INIT_RESUME" , 0x72, 1 , 0 , 0 , init_resume },
2464 // { "INIT_RAM_CONDITION2" , 0x73, 9 , 0 , 0 , init_ram_condition2 },
2465 { "INIT_TIME" , 0x74, 3 , 0 , 0 , init_time },
2466 { "INIT_CONDITION" , 0x75, 2 , 0 , 0 , init_condition },
2467 /* { "INIT_IO_CONDITION" , 0x76, x , x , x , init_io_condition }, */
2468 { "INIT_INDEX_IO" , 0x78, 6 , 0 , 0 , init_index_io },
2469 { "INIT_PLL" , 0x79, 7 , 0 , 0 , init_pll },
2470 { "INIT_ZM_REG" , 0x7A, 9 , 0 , 0 , init_zm_reg },
2471 /* INIT_RAM_RESTRICT_ZM_REG_GROUP's mult is loaded by M table in BIT */
2472 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, 7 , 6 , 0 , init_ram_restrict_zm_reg_group },
2473 { "INIT_COPY_ZM_REG" , 0x90, 9 , 0 , 0 , init_copy_zm_reg },
2474 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, 6 , 5 , 4 , init_zm_reg_group_addr_latched },
2475 { "INIT_RESERVED" , 0x92, 1 , 0 , 0 , init_reserved },
2476 { 0 , 0 , 0 , 0 , 0 , 0 }
2479 static unsigned int get_init_table_entry_length(bios_t *bios, unsigned int offset, int i)
2481 /* Calculates the length of a given init table entry. */
2482 return itbl_entry[i].length + bios->data[offset + itbl_entry[i].length_offset]*itbl_entry[i].length_multiplier;
2485 static void parse_init_table(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset, init_exec_t *iexec)
2487 /* Parses all commands in a init table. */
2489 /* We start out executing all commands found in the
2490 * init table. Some op codes may change the status
2491 * of this variable to SKIP, which will cause
2492 * the following op codes to perform no operation until
2493 * the value is changed back to EXECUTE.
2499 /* Loop until INIT_DONE causes us to break out of the loop
2500 * (or until offset > bios length just in case... )
2501 * (and no more than 10000 iterations just in case... ) */
2502 while ((offset < bios->length) && (count++ < 10000)) {
2503 id = bios->data[offset];
2505 /* Find matching id in itbl_entry */
2506 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
2509 if (itbl_entry[i].name) {
2510 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: [ (0x%02X) - %s ]\n",
2511 offset, itbl_entry[i].id, itbl_entry[i].name);
2513 /* execute eventual command handler */
2514 if (itbl_entry[i].handler)
2515 if (!(*itbl_entry[i].handler)(pScrn, bios, offset, iexec))
2518 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2519 "0x%04X: Init table command not found: 0x%02X\n", offset, id);
2523 /* Add the offset of the current command including all data
2524 * of that command. The offset will then be pointing on the
2527 offset += get_init_table_entry_length(bios, offset, i);
2531 static void parse_init_tables(ScrnInfoPtr pScrn, bios_t *bios)
2533 /* Loops and calls parse_init_table() for each present table. */
2537 init_exec_t iexec = {TRUE, FALSE};
2539 while ((table = le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + i]))))) {
2541 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: Parsing init table %d\n",
2544 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2545 "0x%04X: ------ EXECUTING FOLLOWING COMMANDS ------\n", table);
2547 parse_init_table(pScrn, bios, table, &iexec);
2552 void link_head_and_output(ScrnInfoPtr pScrn, int head, int dcb_entry, Bool overrideval)
2554 /* The BIOS scripts don't do this for us, sadly
2555 * Luckily we do know the values ;-)
2557 * head < 0 indicates we wish to force a setting with the overrideval
2558 * (for VT restore etc.)
2561 NVPtr pNv = NVPTR(pScrn);
2562 int preferred_output = (ffs(pNv->dcb_table.entry[dcb_entry].or) & OUTPUT_1) >> 1;
2563 uint8_t tmds04 = 0x80;
2564 uint32_t tmds_ctrl, tmds_ctrl2;
2566 /* Bit 3 crosswires output and bus. */
2567 if (head >= 0 && head != preferred_output)
2569 if (head < 0 && overrideval)
2572 if (pNv->dcb_table.entry[dcb_entry].type == OUTPUT_LVDS)
2575 tmds_ctrl = NV_PRAMDAC0_OFFSET + (preferred_output ? NV_PRAMDAC0_SIZE : 0) + NV_RAMDAC_FP_TMDS_CONTROL;
2576 tmds_ctrl2 = NV_PRAMDAC0_OFFSET + (preferred_output ? NV_PRAMDAC0_SIZE : 0) + NV_RAMDAC_FP_TMDS_CONTROL_2;
2578 Bool oldexecute = pNv->VBIOS.execute;
2579 pNv->VBIOS.execute = TRUE;
2580 nv32_wr(pScrn, tmds_ctrl + 4, tmds04);
2581 nv32_wr(pScrn, tmds_ctrl, 0x04);
2582 if (pNv->dcb_table.entry[dcb_entry].type == OUTPUT_LVDS && pNv->VBIOS.fp.dual_link)
2583 nv32_wr(pScrn, tmds_ctrl2 + 4, tmds04 ^ 0x08);
2585 /* I have encountered no dvi (dual-link or not) that sets to anything else. */
2586 /* Does this change beyond the 165 MHz boundary? */
2587 nv32_wr(pScrn, tmds_ctrl2 + 4, 0x0);
2589 nv32_wr(pScrn, tmds_ctrl2, 0x04);
2590 pNv->VBIOS.execute = oldexecute;
2593 static void call_lvds_manufacturer_script(ScrnInfoPtr pScrn, int head, int dcb_entry, enum LVDS_script script)
2595 NVPtr pNv = NVPTR(pScrn);
2596 bios_t *bios = &pNv->VBIOS;
2597 init_exec_t iexec = {TRUE, FALSE};
2599 uint8_t sub = bios->data[bios->fp.xlated_entry + script];
2600 uint16_t scriptofs = le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + sub * 2])));
2601 Bool power_off_for_reset;
2602 uint16_t off_on_delay;
2604 if (!bios->fp.xlated_entry || !sub || !scriptofs)
2607 if (script == LVDS_INIT && bios->data[scriptofs] != 'q') {
2608 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "LVDS init script not stubbed\n");
2612 power_off_for_reset = bios->data[bios->fp.xlated_entry] & 1;
2613 off_on_delay = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.xlated_entry + 7]);
2615 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
2616 call_lvds_manufacturer_script(pScrn, head, dcb_entry, LVDS_RESET);
2617 if (script == LVDS_RESET && power_off_for_reset)
2618 call_lvds_manufacturer_script(pScrn, head, dcb_entry, LVDS_PANEL_OFF);
2620 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Calling LVDS script %d:\n", script);
2621 pNv->VBIOS.execute = TRUE;
2622 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_OWNER,
2623 head ? NV_VGA_CRTCX_OWNER_HEADB : NV_VGA_CRTCX_OWNER_HEADA);
2624 parse_init_table(pScrn, bios, scriptofs, &iexec);
2625 pNv->VBIOS.execute = FALSE;
2627 if (script == LVDS_PANEL_OFF)
2628 usleep(off_on_delay * 1000);
2629 if (script == LVDS_RESET)
2630 link_head_and_output(pScrn, head, dcb_entry, FALSE);
2633 static uint16_t clkcmptable(bios_t *bios, uint16_t clktable, int pxclk)
2635 int compare_record_len, i = 0;
2636 uint16_t compareclk, scriptptr = 0;
2638 if (bios->major_version < 5) /* pre BIT */
2639 compare_record_len = 3;
2641 compare_record_len = 4;
2644 compareclk = le16_to_cpu(*((uint16_t *)&bios->data[clktable + compare_record_len * i]));
2645 if (pxclk >= compareclk * 10) {
2646 if (bios->major_version < 5) {
2647 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
2648 scriptptr = le16_to_cpu(*((uint16_t *)(&bios->data[bios->init_script_tbls_ptr + tmdssub * 2])));
2650 scriptptr = le16_to_cpu(*((uint16_t *)&bios->data[clktable + 2 + compare_record_len * i]));
2654 } while (compareclk);
2659 static void rundigitaloutscript(ScrnInfoPtr pScrn, uint16_t scriptptr, int head, int dcb_entry)
2661 bios_t *bios = &NVPTR(pScrn)->VBIOS;
2662 init_exec_t iexec = {TRUE, FALSE};
2664 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: Parsing digital output script table\n", scriptptr);
2665 bios->execute = TRUE;
2666 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_VGA_CRTCX_OWNER,
2667 head ? NV_VGA_CRTCX_OWNER_HEADB : NV_VGA_CRTCX_OWNER_HEADA);
2668 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, 0x57, 0);
2669 nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, 0x58, dcb_entry);
2670 parse_init_table(pScrn, bios, scriptptr, &iexec);
2671 bios->execute = FALSE;
2673 link_head_and_output(pScrn, head, dcb_entry, FALSE);
2676 static void run_lvds_table(ScrnInfoPtr pScrn, int head, int dcb_entry, enum LVDS_script script, int pxclk)
2678 /* The BIT LVDS table's header has the information to setup the
2679 * necessary registers. Following the standard 4 byte header are:
2680 * A bitmask byte and a dual-link transition pxclk value for use in
2681 * selecting the init script when not using straps; 4 script pointers
2682 * for panel power, selected by output and on/off; and 8 table pointers
2683 * for panel init, the needed one determined by output, and bits in the
2684 * conf byte. These tables are similar to the TMDS tables, consisting
2685 * of a list of pxclks and script pointers.
2688 NVPtr pNv = NVPTR(pScrn);
2689 bios_t *bios = &pNv->VBIOS;
2690 unsigned int fpstrapping, outputset = (pNv->dcb_table.entry[dcb_entry].or == 4) ? 1 : 0;
2691 uint16_t scriptptr = 0, clktable;
2692 uint8_t clktableptr = 0;
2694 fpstrapping = (nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
2696 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
2697 run_lvds_table(pScrn, head, dcb_entry, LVDS_RESET, pxclk);
2698 /* no sign of the "panel off for reset" bit, but it's safer to assume we should */
2699 if (script == LVDS_RESET)
2700 run_lvds_table(pScrn, head, dcb_entry, LVDS_PANEL_OFF, pxclk);
2702 /* for now we assume version 3.0 table - g80 support will need some changes */
2707 case LVDS_BACKLIGHT_ON: // check applicability of the script for this
2709 scriptptr = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
2711 case LVDS_BACKLIGHT_OFF: // check applicability of the script for this
2712 case LVDS_PANEL_OFF:
2713 scriptptr = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
2716 if (pNv->dcb_table.entry[dcb_entry].lvdsconf.use_straps_for_mode ||
2717 (fpstrapping != 0x0f && bios->data[bios->fp.xlated_entry + 1] != 0x0f)) {
2718 if (bios->fp.dual_link)
2720 if (bios->fp.BITbit1)
2723 uint8_t fallback = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
2724 int fallbackcmpval = (pNv->dcb_table.entry[dcb_entry].or == 4) ? 4 : 1;
2726 if (pxclk >= bios->fp.duallink_transition_clk) {
2728 fallbackcmpval *= 2;
2730 if (fallbackcmpval & fallback)
2734 /* adding outputset * 8 may not be correct */
2735 clktable = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 15 + clktableptr * 2 + outputset * 8]);
2737 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Pixel clock comparison table not found\n");
2740 scriptptr = clkcmptable(bios, clktable, pxclk);
2744 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "LVDS output init script not found\n");
2747 rundigitaloutscript(pScrn, scriptptr, head, dcb_entry);
2750 void call_lvds_script(ScrnInfoPtr pScrn, int head, int dcb_entry, enum LVDS_script script, int pxclk)
2752 /* LVDS operations are multiplexed in an effort to present a single API
2753 * which works with two vastly differing underlying structures.
2754 * This acts as the demux
2757 bios_t *bios = &NVPTR(pScrn)->VBIOS;
2758 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
2763 if (lvds_ver < 0x30)
2764 call_lvds_manufacturer_script(pScrn, head, dcb_entry, script);
2766 run_lvds_table(pScrn, head, dcb_entry, script, pxclk);
2770 uint16_t fptablepointer;
2771 uint16_t fpxlatetableptr;
2772 uint16_t fpxlatemanufacturertableptr;
2776 static void parse_fp_mode_table(ScrnInfoPtr pScrn, bios_t *bios, struct fppointers *fpp)
2778 unsigned int fpstrapping;
2780 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
2782 DisplayModePtr mode;
2784 fpstrapping = (nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
2786 if (fpp->fptablepointer == 0x0 || fpp->fpxlatetableptr == 0x0) {
2787 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2788 "Pointers to flat panel table invalid\n");
2792 fptable = &bios->data[fpp->fptablepointer];
2794 fptable_ver = fptable[0];
2796 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2797 "Found flat panel mode table revision %d.%d\n",
2798 fptable_ver >> 4, fptable_ver & 0xf);
2800 switch (fptable_ver) {
2801 /* BMP version 0x5.0x11 BIOSen have version 1 like tables, but no version field,
2802 * and miss one of the spread spectrum/PWM bytes.
2803 * This could affect early GF2Go parts (not seen any appropriate ROMs though).
2804 * Here we assume that a version of 0x05 matches this case (combining with a
2805 * BMP version check would be better), as the common case for the panel type
2806 * field is 0x0005, and that is in fact what we are reading the first byte of. */
2807 case 0x05: /* some NV10, 11, 15, 16 */
2811 case 0x10: /* some NV15/16, and NV11+ */
2815 case 0x20: /* NV40+ */
2816 headerlen = fptable[1];
2817 recordlen = fptable[2];
2818 fpentries = fptable[3];
2819 /* fptable[4] is the minimum RAMDAC_FP_HCRTC->RAMDAC_FP_HSYNC_START gap.
2820 * Only seen 0x4b (=75) which is what is used in nv_crtc.c anyway,
2821 * so we're not using this table value for now
2826 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2827 "FP Table revision not currently supported\n");
2831 fpindex = bios->data[fpp->fpxlatetableptr + fpstrapping * fpp->xlatwidth];
2832 if (fpindex > fpentries) {
2833 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2834 "Bad flat panel table index\n");
2838 /* reserved values - means that ddc or hard coded edid should be used */
2839 if (fpindex == 0xf && fpstrapping == 0xf) {
2840 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Ignoring FP table\n");
2844 if (!(mode = xcalloc(1, sizeof(DisplayModeRec))))
2847 int modeofs = headerlen + recordlen * fpindex + ofs;
2848 mode->Clock = le16_to_cpu(*(uint16_t *)&fptable[modeofs]) * 10;
2849 mode->HDisplay = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 2]);
2850 mode->HSyncStart = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 10] + 1);
2851 mode->HSyncEnd = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 12] + 1);
2852 mode->HTotal = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 14] + 1);
2853 mode->VDisplay = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 16]);
2854 mode->VSyncStart = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 24] + 1);
2855 mode->VSyncEnd = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 26] + 1);
2856 mode->VTotal = le16_to_cpu(*(uint16_t *)&fptable[modeofs + 28] + 1);
2857 mode->Flags |= (fptable[modeofs + 30] & 0x10) ? V_PHSYNC : V_NHSYNC;
2858 mode->Flags |= (fptable[modeofs + 30] & 0x1) ? V_PVSYNC : V_NVSYNC;
2861 * bytes 1-2 are "panel type", including bits on whether Colour/mono, single/dual link, and type (TFT etc.)
2862 * bytes 3-6 are bits per colour in RGBX
2864 * 13-14 is HValid Start
2865 * 15-16 is HValid End
2866 * bytes 38-39 relate to spread spectrum settings
2867 * bytes 40-43 are something to do with PWM */
2869 mode->prev = mode->next = NULL;
2870 mode->status = MODE_OK;
2871 mode->type = M_T_DRIVER | M_T_PREFERRED;
2872 xf86SetModeDefaultName(mode);
2874 // if (XF86_CRTC_CONFIG_PTR(pScrn)->debug_modes) {
2875 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2876 "Found flat panel mode in BIOS tables:\n");
2877 xf86PrintModeline(pScrn->scrnIndex, mode);
2880 bios->fp.native_mode = mode;
2883 static void parse_lvds_manufacturer_table_init(ScrnInfoPtr pScrn, bios_t *bios, struct fppointers *fpp)
2885 /* The LVDS table changed considerably with BIT bioses. Previously
2886 * there was a header of version and record length, followed by several
2887 * records, indexed by a seperate xlat table, indexed in turn by the fp
2888 * strap in EXTDEV_BOOT. Each record had a config byte, followed by 6
2889 * script numbers for use by INIT_SUB which controlled panel init and
2890 * power, and finally a dword of ms to sleep between power off and on
2893 * The BIT LVDS table has the typical BIT table header: version byte,
2894 * header length byte, record length byte, and a byte for the maximum
2895 * number of records that can be held in the table. At byte 5 in the
2896 * header is the dual-link transition pxclk (in 10s kHz) - if straps
2897 * are not being used for the panel, this specifies the frequency at
2898 * which modes should be set up in the dual link style.
2900 * The table following the header serves as an integrated config and
2901 * xlat table: the records in the table are indexed by the FP strap
2902 * nibble in EXTDEV_BOOT, and each record has two bytes - the first as
2903 * a config byte, the second for indexing the fp mode table pointed to
2904 * by the BIT 'D' table
2907 unsigned int fpstrapping, lvdsmanufacturerindex = 0;
2908 uint8_t lvds_ver, headerlen, recordlen;
2910 fpstrapping = (nv32_rd(pScrn, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
2912 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
2913 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2914 "Pointer to LVDS manufacturer table invalid\n");
2918 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
2920 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2921 "Found LVDS manufacturer table revision %d.%d\n",
2922 lvds_ver >> 4, lvds_ver & 0xf);
2925 case 0x0a: /* pre NV40 */
2926 lvdsmanufacturerindex = bios->data[fpp->fpxlatemanufacturertableptr + fpstrapping];
2929 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
2932 case 0x30: /* NV4x */
2933 lvdsmanufacturerindex = fpstrapping;
2934 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
2935 if (headerlen < 0x1f) {
2936 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2937 "LVDS table header not understood\n");
2940 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
2942 case 0x40: /* It changed again with gf8 :o( */
2944 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2945 "LVDS table revision not currently supported\n");
2949 uint16_t lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + headerlen + recordlen * lvdsmanufacturerindex;
2952 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
2953 bios->fp.dual_link = bios->data[lvdsofs] & 4;
2954 bios->fp.if_is_18bit = !(bios->data[lvdsofs] & 16);
2957 /* no sign of the "reset for panel on" bit, but it's safer to assume we should */
2958 bios->fp.reset_after_pclk_change = TRUE;
2959 bios->fp.dual_link = bios->data[lvdsofs] & 1;
2960 bios->fp.BITbit1 = bios->data[lvdsofs] & 2;
2961 /* BMP likely has something like this, but I have no dump to point to where it is */
2962 bios->fp.duallink_transition_clk = le16_to_cpu(*(uint16_t *)&bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
2963 fpp->fpxlatetableptr = bios->fp.lvdsmanufacturerpointer + headerlen + 1;
2964 fpp->xlatwidth = recordlen;
2969 void run_tmds_table(ScrnInfoPtr pScrn, int dcb_entry, int head, int pxclk)
2971 /* the dcb_entry parameter is the index of the appropriate DCB entry
2972 * the pxclk parameter is in kHz
2974 * This runs the TMDS regs setting code found on BIT bios cards
2976 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
2977 * ffs(or) == 3, use the second.
2980 NVPtr pNv = NVPTR(pScrn);
2981 bios_t *bios = &pNv->VBIOS;
2982 uint16_t clktable = 0, scriptptr;
2984 if (pNv->dcb_table.entry[dcb_entry].location) /* off chip */
2987 switch (ffs(pNv->dcb_table.entry[dcb_entry].or)) {
2989 clktable = bios->tmds.output0_script_ptr;
2993 clktable = bios->tmds.output1_script_ptr;
2998 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Pixel clock comparison table not found\n");
3002 scriptptr = clkcmptable(bios, clktable, pxclk);
3005 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TMDS output init script not found\n");
3009 rundigitaloutscript(pScrn, scriptptr, head, dcb_entry);
3012 static void parse_bios_version(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset)
3014 /* offset + 0 (8 bits): Micro version
3015 * offset + 1 (8 bits): Minor version
3016 * offset + 2 (8 bits): Chip version
3017 * offset + 3 (8 bits): Major version
3020 bios->major_version = bios->data[offset + 3];
3021 bios->chip_version = bios->data[offset + 2];
3022 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Bios version %02x.%02x.%02x.%02x\n",
3023 bios->data[offset + 3], bios->data[offset + 2],
3024 bios->data[offset + 1], bios->data[offset]);
3027 //int getMNP_double_plltype(ScrnInfoPtr pScrn, enum pll_types plltype, int clk, int *NM1, int *NM2, int *log2P)
3028 int get_pll_limits_plltype(ScrnInfoPtr pScrn, enum pll_types plltype, struct pll_lims *pll_lim)
3031 * Here we just try to find a register matching plltype in the PLL
3032 * limits table. The table is better explained in get_pll_limits below.
3035 bios_t *bios = &NVPTR(pScrn)->VBIOS;
3037 if (!bios->pll_limit_tbl_ptr) {
3038 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Pointer to PLL limits table invalid\n");
3042 switch (bios->data[bios->pll_limit_tbl_ptr]) {
3044 return get_pll_limits(pScrn, 0, pll_lim);
3045 // return getMNP_double(pScrn, 0, clk, NM1, NM2, log2P);
3049 uint8_t headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
3050 uint8_t recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
3051 uint8_t entries = bios->data[bios->pll_limit_tbl_ptr + 3];
3052 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
3056 for (i = 1; i < entries; i++) {
3057 uint32_t cmpreg = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + recordlen * i])));
3059 if (plltype == VPLL1 && (cmpreg == 0x680508 || cmpreg == 0x4010)) {
3063 if (plltype == VPLL2 && (cmpreg == 0x680520 || cmpreg == 0x4018)) {
3069 return get_pll_limits(pScrn, reg, pll_lim);
3070 // return getMNP_double(pScrn, reg, clk, NM1, NM2, log2P);
3073 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3074 "PLL limits table revision not currently supported\n");
3079 Bool get_pll_limits(ScrnInfoPtr pScrn, uint32_t reg, struct pll_lims *pll_lim)
3083 * Version 0x10: NV31
3084 * One byte header (version), one record of 24 bytes
3085 * Version 0x11: NV36 - Not implemented
3086 * Seems to have same record style as 0x10, but 3 records rather than 1
3087 * Version 0x20: Found on Geforce 6 cards
3088 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
3089 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
3090 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record length
3093 bios_t *bios = &NVPTR(pScrn)->VBIOS;
3094 uint8_t pll_lim_ver, headerlen, recordlen, entries;
3095 int pllindex = 0, i;
3097 if (!bios->pll_limit_tbl_ptr) {
3098 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Pointer to PLL limits table invalid\n");
3102 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
3104 if (DEBUGLEVEL >= 6)
3105 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3106 "Found PLL limits table version 0x%X\n", pll_lim_ver);
3108 switch (pll_lim_ver) {
3117 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
3118 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
3119 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
3122 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3123 "PLL limits table revision not currently supported\n");
3127 /* initialize all members to zero */
3128 memset (pll_lim, 0, sizeof(struct pll_lims));
3130 if (pll_lim_ver == 0x10) {
3131 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex;
3133 pll_lim->vco1.minfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs])));
3134 pll_lim->vco1.maxfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 4])));
3135 pll_lim->vco2.minfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 8])));
3136 pll_lim->vco2.maxfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 12])));
3137 pll_lim->vco1.min_inputfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 16])));
3138 pll_lim->vco2.min_inputfreq = le32_to_cpu(*((uint32_t *)(&bios->data[plloffs + 20])));
3139 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
3141 /* these values taken from nv31. nv30, nv36 might do better with different ones */
3142 pll_lim->vco1.min_n = 0x1;
3143 pll_lim->vco1.max_n = 0xff;
3144 pll_lim->vco1.min_m = 0x1;
3145 pll_lim->vco1.max_m = 0xd;
3146 pll_lim->vco2.min_n = 0x4;
3147 pll_lim->vco2.max_n = 0x46;
3148 if (bios->chip_version == 0x30)
3149 /* only 5 bits available for N2 on nv30 */
3150 pll_lim->vco2.max_n = 0x1f;
3151 if (bios->chip_version == 0x31)
3152 /* on nv31, N2 is compared to maxN2 (0x46) and maxM2 (0x4),
3153 * so set maxN2 to 0x4 and save a comparison
3155 pll_lim->vco2.max_n = 0x4;
3156 pll_lim->vco2.min_m = 0x1;
3157 pll_lim->vco2.max_m = 0x4;
3158 } else { /* ver 0x20, 0x21 */
3159 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
3161 /* first entry is default match, if nothing better. warn if reg field nonzero */
3162 if (le32_to_cpu(*((uint32_t *)&bios->data[plloffs])))
3163 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
3164 "Default PLL limit entry has non-zero register field\n");
3166 for (i = 1; i < entries; i++)
3167 if (le32_to_cpu(*((uint32_t *)&bios->data[plloffs + recordlen * i])) == reg) {
3172 plloffs += recordlen * pllindex;
3174 if (DEBUGLEVEL >= 6)
3175 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Loading PLL limits for reg 0x%08x\n",
3176 pllindex ? reg : 0);
3178 /* frequencies are stored in tables in MHz, kHz are more useful, so we convert */
3180 /* What output frequencies can each VCO generate? */
3181 pll_lim->vco1.minfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 4]))) * 1000;
3182 pll_lim->vco1.maxfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 6]))) * 1000;
3183 pll_lim->vco2.minfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 8]))) * 1000;
3184 pll_lim->vco2.maxfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 10]))) * 1000;
3186 /* What input frequencies do they accept (past the m-divider)? */
3187 pll_lim->vco1.min_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 12]))) * 1000;
3188 pll_lim->vco2.min_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 14]))) * 1000;
3189 pll_lim->vco1.max_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 16]))) * 1000;
3190 pll_lim->vco2.max_inputfreq = le16_to_cpu(*((uint16_t *)(&bios->data[plloffs + 18]))) * 1000;
3192 /* What values are accepted as multiplier and divider? */
3193 pll_lim->vco1.min_n = bios->data[plloffs + 20];
3194 pll_lim->vco1.max_n = bios->data[plloffs + 21];
3195 pll_lim->vco1.min_m = bios->data[plloffs + 22];
3196 pll_lim->vco1.max_m = bios->data[plloffs + 23];
3197 pll_lim->vco2.min_n = bios->data[plloffs + 24];
3198 pll_lim->vco2.max_n = bios->data[plloffs + 25];
3199 pll_lim->vco2.min_m = bios->data[plloffs + 26];
3200 pll_lim->vco2.max_m = bios->data[plloffs + 27];
3202 pll_lim->unk1c = bios->data[plloffs + 28];
3203 pll_lim->max_log2p_bias = bios->data[plloffs + 29];
3204 pll_lim->log2p_bias = bios->data[plloffs + 30];
3206 if (recordlen > 0x22)
3207 pll_lim->refclk = le32_to_cpu(*((uint32_t *)&bios->data[plloffs + 31]));
3210 #if 1 /* for easy debugging */
3211 ErrorF("pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
3212 ErrorF("pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
3213 ErrorF("pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
3214 ErrorF("pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
3216 ErrorF("pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
3217 ErrorF("pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
3218 ErrorF("pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
3219 ErrorF("pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
3221 ErrorF("pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
3222 ErrorF("pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
3223 ErrorF("pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
3224 ErrorF("pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
3225 ErrorF("pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
3226 ErrorF("pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
3227 ErrorF("pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
3228 ErrorF("pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
3230 ErrorF("pll.unk1c: %d\n", pll_lim->unk1c);
3231 ErrorF("pll.max_log2p_bias: %d\n", pll_lim->max_log2p_bias);
3232 ErrorF("pll.log2p_bias: %d\n", pll_lim->log2p_bias);
3234 ErrorF("pll.refclk: %d\n", pll_lim->refclk);
3240 static int parse_bit_B_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3242 /* offset + 0 (32 bits): BIOS version dword
3244 * There's a bunch of bits in this table other than the bios version
3245 * that we don't use - their use currently unknown
3248 if (bitentry->length < 0x4) {
3249 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3250 "Do not understand B table entry\n");
3254 parse_bios_version(pScrn, bios, bitentry->offset);
3259 static int parse_bit_C_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3261 /* offset + 8 (16 bits): PLL limits table pointer
3263 * There's more in here, but that's unknown.
3266 if (bitentry->length < 10) {
3267 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Do not understand C table entry\n");
3271 bios->pll_limit_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 8])));
3276 static int parse_bit_display_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry, struct fppointers *fpp)
3278 /* Parses the flat panel table segment that the bit entry points to.
3279 * Starting at bitentry->offset:
3281 * offset + 0 (16 bits): FIXME table pointer
3282 * offset + 2 (16 bits): mode table pointer
3285 if (bitentry->length != 4) {
3286 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3287 "Do not understand BIT display table entry\n");
3291 fpp->fptablepointer = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 2])));
3296 static unsigned int parse_bit_init_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3298 /* Parses the init table segment that the bit entry points to.
3299 * Starting at bitentry->offset:
3301 * offset + 0 (16 bits): init script tables pointer
3302 * offset + 2 (16 bits): macro index table pointer
3303 * offset + 4 (16 bits): macro table pointer
3304 * offset + 6 (16 bits): condition table pointer
3305 * offset + 8 (16 bits): io condition table pointer
3306 * offset + 10 (16 bits): io flag condition table pointer
3307 * offset + 12 (16 bits): init function table pointer
3311 if (bitentry->length < 14) {
3312 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3313 "Unable to recognize BIT init table entry\n");
3317 bios->init_script_tbls_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
3318 bios->macro_index_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 2])));
3319 bios->macro_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 4])));
3320 bios->condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 6])));
3321 bios->io_condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 8])));
3322 bios->io_flag_condition_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 10])));
3323 bios->init_function_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 12])));
3328 static int parse_bit_i_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3330 /* offset + 13 (16 bits): pointer to table containing DAC load detection comparison values
3332 * There's other things in this table, purpose unknown
3337 if (bitentry->length < 15) {
3338 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3339 "BIT i table not long enough for DAC load detection comparison table\n");
3343 offset = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 13])));
3345 /* doesn't exist on g80 */
3349 /* The first value in the table, following the header, is the comparison value
3350 * Purpose of subsequent values unknown - TV load detection?
3353 uint8_t version = bios->data[offset];
3355 if (version != 0x00 && version != 0x10) {
3356 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
3357 "DAC load detection comparison table version %d.%d not known\n",
3358 version >> 4, version & 0xf);
3362 uint8_t headerlen = bios->data[offset + 1];
3364 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3365 "DAC load detection comparison table version %x found\n", version);
3367 bios->dactestval = le32_to_cpu(*((uint32_t *)(&bios->data[offset + headerlen])));
3372 static int parse_bit_lvds_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry, struct fppointers *fpp)
3374 /* Parses the LVDS table segment that the bit entry points to.
3375 * Starting at bitentry->offset:
3377 * offset + 0 (16 bits): LVDS strap xlate table pointer
3380 if (bitentry->length != 2) {
3381 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3382 "Do not understand BIT LVDS table entry\n");
3386 /* no idea if it's still called the LVDS manufacturer table, but the concept's close enough */
3387 bios->fp.lvdsmanufacturerpointer = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
3389 parse_lvds_manufacturer_table_init(pScrn, bios, fpp);
3394 static int parse_bit_M_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3396 /* offset + 2 (8 bits): number of options in an INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
3397 * offset + 3 (16 bits): pointer to strap xlate table for RAM restrict option selection
3399 * There's a bunch of bits in this table other than the RAM restrict
3400 * stuff that we don't use - their use currently unknown
3405 /* Older bios versions don't have a sufficiently long table for what we want */
3406 if (bitentry->length < 0x5)
3409 /* set up multiplier for INIT_RAM_RESTRICT_ZM_REG_GROUP */
3410 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != 0x8f); i++)
3412 itbl_entry[i].length_multiplier = bios->data[bitentry->offset + 2] * 4;
3413 init_ram_restrict_zm_reg_group_blocklen = itbl_entry[i].length_multiplier;
3415 bios->ram_restrict_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset + 3])));
3420 static int parse_bit_tmds_tbl_entry(ScrnInfoPtr pScrn, bios_t *bios, bit_entry_t *bitentry)
3422 /* Parses the pointer to the TMDS table
3424 * Starting at bitentry->offset:
3426 * offset + 0 (16 bits): TMDS table pointer
3428 * The TMDS table is typically found just before the DCB table, with a
3429 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
3432 * At offset +7 is a pointer to a script, which I don't know how to run yet
3433 * At offset +9 is a pointer to another script, likewise
3434 * Offset +11 has a pointer to a table where the first word is a pxclk
3435 * frequency and the second word a pointer to a script, which should be
3436 * run if the comparison pxclk frequency is less than the pxclk desired.
3437 * This repeats for decreasing comparison frequencies
3438 * Offset +13 has a pointer to a similar table
3439 * The selection of table (and possibly +7/+9 script) is dictated by
3440 * "or" from the DCB.
3443 uint16_t tmdstableptr, script1, script2;
3445 if (bitentry->length != 2) {
3446 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3447 "Do not understand BIT TMDS table entry\n");
3451 tmdstableptr = le16_to_cpu(*((uint16_t *)(&bios->data[bitentry->offset])));
3453 if (tmdstableptr == 0x0) {
3454 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Pointer to TMDS table invalid\n");
3458 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Found TMDS table revision %d.%d\n",
3459 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
3461 /* These two scripts are odd: they don't seem to get run even when they are not stubbed */
3462 script1 = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 7]));
3463 script2 = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 9]));
3464 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
3465 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TMDS table script pointers not stubbed\n");
3467 bios->tmds.output0_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 11]));
3468 bios->tmds.output1_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[tmdstableptr + 13]));
3473 static void parse_bit_structure(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset)
3475 bit_entry_t bitentry;
3477 struct fppointers fpp;
3478 NVPtr pNv = NVPTR(pScrn);
3480 memset(&fpp, 0, sizeof(struct fppointers));
3483 bitentry.id[0] = bios->data[offset];
3484 bitentry.id[1] = bios->data[offset + 1];
3485 bitentry.length = le16_to_cpu(*((uint16_t *)&bios->data[offset + 2]));
3486 bitentry.offset = le16_to_cpu(*((uint16_t *)&bios->data[offset + 4]));
3488 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3489 "0x%04X: Found BIT command with id 0x%02X (%c)\n",
3490 offset, bitentry.id[0], bitentry.id[0]);
3492 switch (bitentry.id[0]) {
3494 /* id[0] = 0 and id[1] = 0 ==> end of BIT struture */
3495 if (bitentry.id[1] == 0)
3499 parse_bit_B_tbl_entry(pScrn, bios, &bitentry);
3502 parse_bit_C_tbl_entry(pScrn, bios, &bitentry);
3505 parse_bit_display_tbl_entry(pScrn, bios, &bitentry, &fpp);
3508 parse_bit_init_tbl_entry(pScrn, bios, &bitentry);
3511 parse_bit_i_tbl_entry(pScrn, bios, &bitentry);
3514 parse_bit_lvds_tbl_entry(pScrn, bios, &bitentry, &fpp);
3516 case 'M': /* memory? */
3517 parse_bit_M_tbl_entry(pScrn, bios, &bitentry);
3520 parse_bit_tmds_tbl_entry(pScrn, bios, &bitentry);
3524 offset += sizeof(bit_entry_t);
3527 /* C and M tables have to be parsed before init can run */
3528 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3529 "Parsing previously deferred init table entry\n");
3530 parse_init_tables(pScrn, bios);
3532 /* If it's not a laptop, you probably don't care about LVDS */
3533 /* FIXME: detect mobile BIOS? */
3537 /* Need D and L tables parsed before doing this */
3538 parse_fp_mode_table(pScrn, bios, &fpp);
3541 static void parse_bmp_structure(ScrnInfoPtr pScrn, bios_t *bios, unsigned int offset)
3543 /* Parse the BMP structure for useful things
3545 * offset + 5: BMP major version
3546 * offset + 6: BMP minor version
3547 * offset + 10: BCD encoded BIOS version
3549 * offset + 18: init script table pointer (for bios versions < 5.10h)
3550 * offset + 20: extra init script table pointer (for bios versions < 5.10h)
3552 * offset + 24: FIXME
3553 * offset + 26: FIXME
3554 * offset + 28: FIXME
3556 * offset + 54: index of I2C CRTC pair to use for CRT output
3557 * offset + 55: index of I2C CRTC pair to use for TV output
3558 * offset + 56: index of I2C CRTC pair to use for flat panel output
3559 * offset + 58: write CRTC index for I2C pair 0
3560 * offset + 59: read CRTC index for I2C pair 0
3561 * offset + 60: write CRTC index for I2C pair 1
3562 * offset + 61: read CRTC index for I2C pair 1
3564 * offset + 67: maximum internal PLL frequency (single stage PLL)
3565 * offset + 71: minimum internal PLL frequency (single stage PLL)
3567 * offset + 75: script table pointers, as for parse_bit_init_tbl_entry
3569 * offset + 89: TMDS single link output A table pointer
3570 * offset + 91: TMDS single link output B table pointer
3571 * offset + 105: flat panel timings table pointer
3572 * offset + 107: flat panel strapping translation table pointer
3573 * offset + 117: LVDS manufacturer panel config table pointer
3574 * offset + 119: LVDS manufacturer strapping translation table pointer
3576 * offset + 142: PLL limits table pointer
3579 NVPtr pNv = NVPTR(pScrn);
3581 struct fppointers fpp;
3582 memset(&fpp, 0, sizeof(struct fppointers));
3584 uint8_t bmp_version_major = bios->data[offset + 5];
3585 uint8_t bmp_version_minor = bios->data[offset + 6];
3587 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BMP version %d.%d\n",
3588 bmp_version_major, bmp_version_minor);
3590 /* version 6 could theoretically exist, but I suspect BIT happened instead */
3591 if (bmp_version_major < 2 || bmp_version_major > 5) {
3592 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "You have an unsupported BMP version. Please send in your bios\n");
3596 if (bmp_version_major == 2)
3597 bmplength = 48; /* exact for 2.01 - not sure if minor version used in versions < 5 */
3598 else if (bmp_version_major == 3)
3599 bmplength = 54; /* guessed - mem init tables added in this version */
3600 else if (bmp_version_major == 4 || bmp_version_minor < 0x1) /* don't know if 5.0 exists... */
3601 bmplength = 62; /* guessed - BMP I2C indices added in version 4*/
3602 else if (bmp_version_minor < 0x6)
3603 bmplength = 67; /* exact for 5.01 */
3604 else if (bmp_version_minor < 0x10)
3605 bmplength = 75; /* exact for 5.06 */
3606 else if (bmp_version_minor == 0x10)
3607 bmplength = 89; /* exact for 5.10h */
3608 else if (bmp_version_minor < 0x14)
3609 bmplength = 118; /* exact for 5.11h */
3610 else if (bmp_version_minor < 0x24) /* not sure of version where pll limits came in;
3611 * certainly exist by 0x24 though */
3612 /* length not exact: this is long enough to get lvds members */
3615 /* length not exact: this is long enough to get pll limit member */
3619 if (nv_cksum(bios->data + offset, 8)) {
3620 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Bad BMP checksum\n");
3624 parse_bios_version(pScrn, bios, offset + 10);
3626 bios->init_script_tbls_ptr = le16_to_cpu(*(uint16_t *)&bios->data[offset + 18]);
3627 bios->extra_init_script_tbl_ptr = le16_to_cpu(*(uint16_t *)&bios->data[offset + 20]);
3630 // FIXME needed for pre v16? - haiku uses this in its COMPUTE_MEM on early biosen
3631 if (bmp_version_major > 2) {
3632 uint16_t meminittbl = le16_to_cpu(*(uint16_t *)&bios->data[offset + 24]);
3633 uint16_t sdrmemseqtbl = le16_to_cpu(*(uint16_t *)&bios->data[offset + 26]);
3634 uint16_t ddrmemseqtbl = le16_to_cpu(*(uint16_t *)&bios->data[offset + 28]);
3638 uint16_t legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
3640 legacy_i2c_offset = offset + 54;
3641 bios->legacy_i2c_indices.crt = bios->data[legacy_i2c_offset];
3642 bios->legacy_i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
3643 bios->legacy_i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
3644 pNv->dcb_table.i2c_write[0] = bios->data[legacy_i2c_offset + 4];
3645 pNv->dcb_table.i2c_read[0] = bios->data[legacy_i2c_offset + 5];
3646 pNv->dcb_table.i2c_write[1] = bios->data[legacy_i2c_offset + 6];
3647 pNv->dcb_table.i2c_read[1] = bios->data[legacy_i2c_offset + 7];
3649 if (bmplength > 74) {
3650 bios->fmaxvco = le32_to_cpu(*((uint32_t *)&bios->data[offset + 67]));
3651 bios->fminvco = le32_to_cpu(*((uint32_t *)&bios->data[offset + 71]));
3653 if (bmplength > 88) {
3654 bit_entry_t initbitentry;
3655 initbitentry.length = 14;
3656 initbitentry.offset = offset + 75;
3657 parse_bit_init_tbl_entry(pScrn, bios, &initbitentry);
3659 if (bmplength > 92) {
3660 bios->tmds.output0_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[offset + 89]));
3661 bios->tmds.output1_script_ptr = le16_to_cpu(*((uint16_t *)&bios->data[offset + 91]));
3663 if (bmplength > 108) {
3664 fpp.fptablepointer = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 105])));
3665 fpp.fpxlatetableptr = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 107])));
3668 if (bmplength > 120) {
3669 bios->fp.lvdsmanufacturerpointer = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 117])));
3670 fpp.fpxlatemanufacturertableptr = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 119])));
3672 if (bmplength > 143)
3673 bios->pll_limit_tbl_ptr = le16_to_cpu(*((uint16_t *)(&bios->data[offset + 142])));
3675 /* want pll_limit_tbl_ptr set (if available) before init is run */
3676 if (bmp_version_major < 5 || bmp_version_minor < 0x10) {
3677 init_exec_t iexec = {TRUE, FALSE};
3678 if (bios->init_script_tbls_ptr)
3679 parse_init_table(pScrn, bios, bios->init_script_tbls_ptr, &iexec);
3680 if (bios->extra_init_script_tbl_ptr)
3681 parse_init_table(pScrn, bios, bios->extra_init_script_tbl_ptr, &iexec);
3683 parse_init_tables(pScrn, bios);
3685 /* If it's not a laptop, you probably don't care about fptables */
3686 /* FIXME: detect mobile BIOS? */
3690 parse_fp_mode_table(pScrn, bios, &fpp);
3691 parse_lvds_manufacturer_table_init(pScrn, bios, &fpp);
3692 /* I've never seen a valid LVDS_INIT script, so we'll do a test for it here */
3693 call_lvds_script(pScrn, 0, 0, LVDS_INIT, 0);
3696 static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
3700 for (i = 0; i <= (n - len); i++) {
3701 for (j = 0; j < len; j++)
3702 if (data[i + j] != str[j])
3711 static Bool parse_dcb_entry(ScrnInfoPtr pScrn, uint8_t dcb_version, uint32_t conn, uint32_t conf, struct dcb_entry *entry)
3713 NVPtr pNv = NVPTR(pScrn);
3715 memset(entry, 0, sizeof (struct dcb_entry));
3717 /* safe defaults for a crt */
3719 entry->i2c_index = 0;
3722 entry->location = 0;
3724 entry->duallink_possible = FALSE;
3726 if (dcb_version >= 0x20) {
3727 entry->type = conn & 0xf;
3728 entry->i2c_index = (conn >> 4) & 0xf;
3729 entry->heads = (conn >> 8) & 0xf;
3730 entry->bus = (conn >> 16) & 0xf;
3731 entry->location = (conn >> 20) & 0xf;
3732 entry->or = (conn >> 24) & 0xf;
3733 /* Normal entries consist of a single bit, but dual link has the
3734 * adjacent more significant bit set too
3736 if ((1 << (ffs(entry->or) - 1)) * 3 == entry->or)
3737 entry->duallink_possible = TRUE;
3739 switch (entry->type) {
3741 if (conf & 0xfffffffa)
3742 ErrorF("Unknown LVDS configuration bits, please report\n");
3744 entry->lvdsconf.use_straps_for_mode = TRUE;
3746 entry->lvdsconf.use_power_scripts = TRUE;
3749 } else if (dcb_version >= 0x14 ) {
3750 if (conn != 0xf0003f00 && conn != 0xf2204301 && conn != 0xf2045f14 && conn != 0xf2205004 && conn != 0xf2208001 && conn != 0xf4204011) {
3751 ErrorF("Unknown DCB 1.4 / 1.5 entry, please report\n");
3752 /* cause output setting to fail, so message is seen */
3753 pNv->dcb_table.entries = 0;
3756 /* most of the below is a "best guess" atm */
3757 entry->type = conn & 0xf;
3758 if (entry->type == 4) { /* digital */
3760 entry->type = OUTPUT_LVDS;
3762 entry->type = OUTPUT_TMDS;
3764 /* what's in bits 5-13? could be some brooktree/chrontel/philips thing, in tv case */
3765 entry->i2c_index = (conn >> 14) & 0xf;
3766 /* raw heads field is in range 0-1, so move to 1-2 */
3767 entry->heads = ((conn >> 18) & 0x7) + 1;
3768 entry->location = (conn >> 21) & 0xf;
3769 entry->bus = (conn >> 25) & 0x7;
3770 /* set or to be same as heads -- hopefully safe enough */
3771 entry->or = entry->heads;
3773 switch (entry->type) {
3775 /* these are probably buried in conn's unknown bits */
3776 entry->lvdsconf.use_straps_for_mode = TRUE;
3777 entry->lvdsconf.use_power_scripts = TRUE;
3780 /* invent a DVI-A output, by copying the fields of the DVI-D output
3781 * reported to work by math_b on an NV20(!) */
3782 memcpy(&entry[1], &entry[0], sizeof(struct dcb_entry));
3783 entry[1].type = OUTPUT_ANALOG;
3784 pNv->dcb_table.entries++;
3786 } else if (dcb_version >= 0x12) {
3787 /* use the defaults for a crt
3788 * v1.2 tables often have other entries though - need a trace
3790 entry->type = conn & 0xf; // this is valid, but will probably confuse the randr stuff
3792 } else { /* pre DCB / v1.1 - use the safe defaults for a crt */
3793 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3794 "No information in BIOS output table; assuming a CRT output exists\n");
3795 entry->i2c_index = pNv->VBIOS.legacy_i2c_indices.crt;
3798 pNv->dcb_table.entries++;
3804 read_dcb_i2c_table(ScrnInfoPtr pScrn, bios_t *bios, uint8_t dcb_version, uint16_t i2ctabptr)
3806 NVPtr pNv = NVPTR(pScrn);
3808 uint8_t headerlen = 0;
3810 int recordoffset = 0, rdofs = 1, wrofs = 0;
3813 i2c_entries = MAX_NUM_DCB_ENTRIES;
3814 memset(pNv->dcb_table.i2c_read, 0, sizeof(pNv->dcb_table.i2c_read));
3815 memset(pNv->dcb_table.i2c_write, 0, sizeof(pNv->dcb_table.i2c_write));
3817 i2ctable = &bios->data[i2ctabptr];
3819 if (dcb_version >= 0x30) {
3820 if (i2ctable[0] != dcb_version) { /* necessary? */
3821 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3822 "DCB I2C table version mismatch (%02X vs %02X)\n",
3823 i2ctable[0], dcb_version);
3826 headerlen = i2ctable[1];
3827 i2c_entries = i2ctable[2];
3828 if (i2ctable[0] >= 0x40) {
3829 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3830 "G80 DCB I2C table detected, arrgh\n"); /* they're plain weird */
3834 /* it's your own fault if you call this function on a DCB 1.1 BIOS --
3835 * the below assumes DCB 1.2
3837 if (dcb_version < 0x14) {
3843 for (i = 0; i < i2c_entries; i++)
3844 if (i2ctable[headerlen + 4 * i + 3] != 0xff) {
3845 pNv->dcb_table.i2c_read[i] = i2ctable[headerlen + recordoffset + rdofs + 4 * i];
3846 pNv->dcb_table.i2c_write[i] = i2ctable[headerlen + recordoffset + wrofs + 4 * i];
3850 static unsigned int parse_dcb_table(ScrnInfoPtr pScrn, bios_t *bios)
3852 NVPtr pNv = NVPTR(pScrn);
3853 uint16_t dcbptr, i2ctabptr = 0;
3855 uint8_t dcb_version, headerlen = 0x4, entries = MAX_NUM_DCB_ENTRIES;
3856 Bool configblock = TRUE;
3857 int recordlength = 8, confofs = 4;
3860 pNv->dcb_table.entries = 0;
3862 /* get the offset from 0x36 */
3863 dcbptr = le16_to_cpu(*(uint16_t *)&bios->data[0x36]);
3865 if (dcbptr == 0x0) {
3866 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3867 "No Display Configuration Block pointer found\n");
3868 /* this situation likely means a really old card, pre DCB, so we'll add the safe CRT entry */
3869 parse_dcb_entry(pScrn, 0, 0, 0, &pNv->dcb_table.entry[0]);
3873 dcbtable = &bios->data[dcbptr];
3875 /* get DCB version */
3876 dcb_version = dcbtable[0];
3877 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3878 "Display Configuration Block version %d.%d found\n",
3879 dcb_version >> 4, dcb_version & 0xf);
3881 if (dcb_version >= 0x20) { /* NV17+ */
3884 if (dcb_version >= 0x30) { /* NV40+ */
3885 headerlen = dcbtable[1];
3886 entries = dcbtable[2];
3887 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[4]);
3888 sig = le32_to_cpu(*(uint32_t *)&dcbtable[6]);
3890 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3891 "DCB header length %02X, with %02X possible entries\n",
3892 headerlen, entries);
3894 /* dcb_block_count = *(dcbtable[1]); */
3895 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
3896 sig = le32_to_cpu(*(uint32_t *)&dcbtable[4]);
3900 if (sig != 0x4edcbdcb) {
3901 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3902 "Bad Display Configuration Block signature (%08X)\n", sig);
3905 } else if (dcb_version >= 0x14) { /* some NV15/16, and NV11+ */
3909 strncpy(sig, (char *)&dcbtable[-7], 7);
3910 /* dcb_block_count = *(dcbtable[1]); */
3911 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
3915 if (strcmp(sig, "DEV_REC")) {
3916 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3917 "Bad Display Configuration Block signature (%s)\n", sig);
3920 } else if (dcb_version >= 0x12) { /* some NV6/10, and NV15+ */
3921 /* dcb_block_count = *(dcbtable[1]); */
3922 i2ctabptr = le16_to_cpu(*(uint16_t *)&dcbtable[2]);
3923 configblock = FALSE;
3924 } else { /* NV5+, maybe NV4 */
3925 /* DCB 1.1 seems to be quite unhelpful - we'll just add the safe CRT entry */
3926 parse_dcb_entry(pScrn, dcb_version, 0, 0, &pNv->dcb_table.entry[0]);
3930 if (entries >= MAX_NUM_DCB_ENTRIES)
3931 entries = MAX_NUM_DCB_ENTRIES;
3933 for (i = 0; i < entries; i++) {
3934 uint32_t connection, config = 0;
3936 connection = le32_to_cpu(*(uint32_t *)&dcbtable[headerlen + recordlength * i]);
3938 config = le32_to_cpu(*(uint32_t *)&dcbtable[headerlen + confofs + recordlength * i]);
3940 /* Should we allow discontinuous DCBs? Certainly DCB I2C tables
3941 * can be discontinuous */
3942 if ((connection & 0x0000000f) == 0x0000000f) /* end of records */
3945 ErrorF("Raw DCB entry %d: %08x %08x\n", i, connection, config);
3946 if (!parse_dcb_entry(pScrn, dcb_version, connection, config, &pNv->dcb_table.entry[pNv->dcb_table.entries]))
3950 read_dcb_i2c_table(pScrn, bios, dcb_version, i2ctabptr);
3952 /* DCB v2.0, in particular, lists each output combination separately.
3953 * Here we merge compatible entries to have fewer outputs, with more options
3955 for (i = 0; i < pNv->dcb_table.entries; i++) {
3956 struct dcb_entry *ient = &pNv->dcb_table.entry[i];
3959 for (j = i + 1; j < pNv->dcb_table.entries; j++) {
3960 struct dcb_entry *jent = &pNv->dcb_table.entry[j];
3962 if (jent->type == 100) /* already merged entry */
3965 if (jent->i2c_index == ient->i2c_index && jent->type == ient->type && jent->location == ient->location) {
3966 /* only merge heads field when output field is the same --
3967 * we could merge output field for same heads, but dual link,
3968 * the resultant need to make several merging passes, and lack
3969 * of applicable real life cases has deterred this so far
3971 if (jent->or == ient->or) {
3972 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
3973 "Merging DCB entries %d and %d\n", i, j);
3974 ient->heads |= jent->heads;
3975 jent->type = 100; /* dummy value */
3981 /* Compact entries merged into others out of dcb_table */
3983 for (i = 0; i < pNv->dcb_table.entries; i++) {
3984 if ( pNv->dcb_table.entry[i].type == 100 )
3987 if (newentries != i)
3988 memcpy(&pNv->dcb_table.entry[newentries], &pNv->dcb_table.entry[i], sizeof(struct dcb_entry));
3992 pNv->dcb_table.entries = newentries;
3994 return pNv->dcb_table.entries;
3997 static void load_nv17_hw_sequencer_ucode(ScrnInfoPtr pScrn, bios_t *bios, uint16_t hwsq_offset, int entry)
3999 /* BMP based cards, from NV17, need a microcode loading to correctly
4000 * control the GPIO etc for LVDS panels
4002 * BIT based cards seem to do this directly in the init scripts
4004 * The microcode entries are found by the "HWSQ" signature.
4005 * The header following has the number of entries, and the entry size
4007 * An entry consists of a dword to write to the sequencer control reg
4008 * (0x00001304), followed by the ucode bytes, written sequentially,
4009 * starting at reg 0x00001400
4012 uint8_t bytes_to_write;
4015 if (bios->data[hwsq_offset] <= entry) {
4016 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
4017 "Too few entries in HW sequencer table for requested entry\n");
4021 bytes_to_write = bios->data[hwsq_offset + 1];
4023 if (bytes_to_write != 36) {
4024 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unknown HW sequencer entry size\n");
4028 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Loading NV17 power sequencing microcode\n");
4030 uint16_t hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
4032 /* set sequencer control */
4033 nv32_wr(pScrn, 0x00001304, le32_to_cpu(*(uint32_t *)&bios->data[hwsq_entry_offset]));
4034 bytes_to_write -= 4;
4037 for (i = 0; i < bytes_to_write; i += 4)
4038 nv32_wr(pScrn, 0x00001400 + i, le32_to_cpu(*(uint32_t *)&bios->data[hwsq_entry_offset + i + 4]));
4040 /* twiddle 0x1098 */
4041 nv32_wr(pScrn, 0x00001098, nv32_rd(pScrn, 0x00001098) | 0x18);
4044 static void read_bios_edid(ScrnInfoPtr pScrn)
4046 bios_t *bios = &NVPTR(pScrn)->VBIOS;
4047 const uint8_t edid_sig[] = { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
4048 uint16_t offset = 0, newoffset;
4049 int searchlen = NV_PROM_SIZE, i;
4052 if (!(newoffset = findstr(&bios->data[offset], searchlen, edid_sig, 8)))
4054 offset += newoffset;
4055 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
4058 searchlen -= offset;
4062 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Found EDID in BIOS\n");
4064 bios->fp.edid = xalloc(EDID1_LEN);
4065 for (i = 0; i < EDID1_LEN; i++)
4066 bios->fp.edid[i] = bios->data[offset + i];
4069 Bool NVInitVBIOS(ScrnInfoPtr pScrn)
4071 NVPtr pNv = NVPTR(pScrn);
4073 memset(&pNv->VBIOS, 0, sizeof(bios_t));
4074 pNv->VBIOS.data = xalloc(NV_PROM_SIZE);
4076 if (!NVShadowVBIOS(pScrn, pNv->VBIOS.data)) {
4077 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
4078 "No valid BIOS image found\n");
4079 xfree(pNv->VBIOS.data);
4083 pNv->VBIOS.length = pNv->VBIOS.data[2] * 512;
4084 if (pNv->VBIOS.length > NV_PROM_SIZE)
4085 pNv->VBIOS.length = NV_PROM_SIZE;
4090 Bool NVRunVBIOSInit(ScrnInfoPtr pScrn)
4092 NVPtr pNv = NVPTR(pScrn);
4093 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
4094 const uint8_t bit_signature[] = { 'B', 'I', 'T' };
4095 int offset, ret = 0;
4097 crtc_access(pScrn, ACCESS_UNLOCK);
4099 if ((offset = findstr(pNv->VBIOS.data, pNv->VBIOS.length, bit_signature, sizeof(bit_signature)))) {
4100 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BIT BIOS found\n");
4101 parse_bit_structure(pScrn, &pNv->VBIOS, offset + 4);
4102 } else if ((offset = findstr(pNv->VBIOS.data, pNv->VBIOS.length, bmp_signature, sizeof(bmp_signature)))) {
4103 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
4106 if ((hwsq_offset = findstr(pNv->VBIOS.data, pNv->VBIOS.length, hwsq_signature, sizeof(hwsq_signature))))
4107 /* always use entry 0? */
4108 load_nv17_hw_sequencer_ucode(pScrn, &pNv->VBIOS, hwsq_offset + sizeof(hwsq_signature), 0);
4110 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "BMP BIOS found\n");
4111 parse_bmp_structure(pScrn, &pNv->VBIOS, offset);
4113 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
4114 "No known BIOS signature found\n");
4118 crtc_access(pScrn, ACCESS_LOCK);
4126 unsigned int NVParseBios(ScrnInfoPtr pScrn)
4128 NVPtr pNv = NVPTR(pScrn);
4129 uint32_t saved_nv_pextdev_boot_0;
4131 if (!NVInitVBIOS(pScrn))
4134 /* these will need remembering across a suspend */
4135 saved_nv_pextdev_boot_0 = nv32_rd(pScrn, NV_PEXTDEV_BOOT_0);
4136 saved_nv_pfb_cfg0 = nv32_rd(pScrn, NV_PFB_CFG0);
4138 pNv->VBIOS.execute = FALSE;
4140 nv32_wr(pScrn, NV_PEXTDEV_BOOT_0, saved_nv_pextdev_boot_0);
4142 if (!NVRunVBIOSInit(pScrn))
4145 if (parse_dcb_table(pScrn, &pNv->VBIOS))
4146 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
4147 "Found %d entries in DCB\n", pNv->dcb_table.entries);
4149 if (pNv->Mobile && !pNv->VBIOS.fp.native_mode)
4150 read_bios_edid(pScrn);