2 * Copyright 2006 Dave Airlie
3 * Copyright 2007 Maarten Maathuis
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
26 * decleration is at the bottom of this file as it is rather ugly
40 #include "mipointer.h"
41 #include "windowstr.h"
43 #include <X11/extensions/render.h>
44 #include "X11/Xatom.h"
47 #include "nv_include.h"
49 const char *OutputType[] = {
58 const char *MonTypeName[7] = {
69 * TMDS registers are indirect 8 bit registers.
70 * Reading is straightforward, writing a bit odd.
71 * Reading: Write adress (+write protect bit, do not forget this), then read value.
72 * Writing: Write adress (+write protect bit), write value, write adress again and write it again (+write protect bit).
75 void NVWriteTMDS(NVPtr pNv, int ramdac, CARD32 tmds_reg, CARD32 val)
77 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_CONTROL,
78 (tmds_reg & 0xff) | NV_RAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
80 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_DATA, val & 0xff);
82 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_CONTROL, tmds_reg & 0xff);
83 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_CONTROL,
84 (tmds_reg & 0xff) | NV_RAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
87 CARD8 NVReadTMDS(NVPtr pNv, int ramdac, CARD32 tmds_reg)
89 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_CONTROL,
90 (tmds_reg & 0xff) | NV_RAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
92 return (nvReadRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_DATA) & 0xff);
95 /* Two register sets exist, this one is only used for dual link dvi/lvds */
97 void NVWriteTMDS2(NVPtr pNv, int ramdac, CARD32 tmds_reg, CARD32 val)
99 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_CONTROL_2,
100 (tmds_reg & 0xff) | NV_RAMDAC_FP_TMDS_CONTROL_2_WRITE_DISABLE);
102 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_DATA_2, val & 0xff);
104 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_CONTROL_2, tmds_reg & 0xff);
105 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_CONTROL_2,
106 (tmds_reg & 0xff) | NV_RAMDAC_FP_TMDS_CONTROL_2_WRITE_DISABLE);
109 CARD8 NVReadTMDS2(NVPtr pNv, int ramdac, CARD32 tmds_reg)
111 nvWriteRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_CONTROL_2,
112 (tmds_reg & 0xff) | NV_RAMDAC_FP_TMDS_CONTROL_2_WRITE_DISABLE);
114 return (nvReadRAMDAC(pNv, ramdac, NV_RAMDAC_FP_TMDS_DATA_2) & 0xff);
117 void NVOutputWriteTMDS(xf86OutputPtr output, CARD32 tmds_reg, CARD32 val)
119 NVOutputPrivatePtr nv_output = output->driver_private;
120 ScrnInfoPtr pScrn = output->scrn;
121 NVPtr pNv = NVPTR(pScrn);
123 /* We must write to the "bus" of the output */
124 NVWriteTMDS(pNv, nv_output->preferred_output, tmds_reg, val);
127 CARD8 NVOutputReadTMDS(xf86OutputPtr output, CARD32 tmds_reg)
129 NVOutputPrivatePtr nv_output = output->driver_private;
130 ScrnInfoPtr pScrn = output->scrn;
131 NVPtr pNv = NVPTR(pScrn);
133 /* We must read from the "bus" of the output */
134 return NVReadTMDS(pNv, nv_output->preferred_output, tmds_reg);
137 void NVOutputWriteTMDS2(xf86OutputPtr output, CARD32 tmds_reg, CARD32 val)
139 NVOutputPrivatePtr nv_output = output->driver_private;
140 ScrnInfoPtr pScrn = output->scrn;
141 NVPtr pNv = NVPTR(pScrn);
143 /* We must write to the "bus" of the output */
144 NVWriteTMDS2(pNv, nv_output->preferred_output, tmds_reg, val);
147 CARD8 NVOutputReadTMDS2(xf86OutputPtr output, CARD32 tmds_reg)
149 NVOutputPrivatePtr nv_output = output->driver_private;
150 ScrnInfoPtr pScrn = output->scrn;
151 NVPtr pNv = NVPTR(pScrn);
153 /* We must read from the "bus" of the output */
154 return NVReadTMDS2(pNv, nv_output->preferred_output, tmds_reg);
157 /* These functions now write into the output, instead of a specific ramdac */
159 void NVOutputWriteRAMDAC(xf86OutputPtr output, CARD32 ramdac_reg, CARD32 val)
161 NVOutputPrivatePtr nv_output = output->driver_private;
162 ScrnInfoPtr pScrn = output->scrn;
163 NVPtr pNv = NVPTR(pScrn);
165 nvWriteRAMDAC(pNv, nv_output->preferred_output, ramdac_reg, val);
168 CARD32 NVOutputReadRAMDAC(xf86OutputPtr output, CARD32 ramdac_reg)
170 NVOutputPrivatePtr nv_output = output->driver_private;
171 ScrnInfoPtr pScrn = output->scrn;
172 NVPtr pNv = NVPTR(pScrn);
174 return nvReadRAMDAC(pNv, nv_output->preferred_output, ramdac_reg);
177 static void dpms_update_output_ramdac(xf86OutputPtr output, int mode)
179 NVOutputPrivatePtr nv_output = output->driver_private;
180 ScrnInfoPtr pScrn = output->scrn;
181 NVPtr pNv = NVPTR(pScrn);
182 xf86CrtcPtr crtc = output->crtc;
183 if (!crtc) /* we need nv_crtc, so give up */
185 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
187 /* We may be going for modesetting, so we must reset our output binding */
188 if (mode == DPMSModeOff) {
189 NVWriteVGACR5758(pNv, nv_crtc->head, 0, 0x7f);
190 NVWriteVGACR5758(pNv, nv_crtc->head, 2, 0);
194 /* The previous call was not a modeset, but a normal dpms call */
195 NVWriteVGACR5758(pNv, nv_crtc->head, 0, pNv->dcb_table.entry[nv_output->dcb_entry].type);
196 NVWriteVGACR5758(pNv, nv_crtc->head, 2, pNv->dcb_table.entry[nv_output->dcb_entry].or);
200 nv_lvds_output_dpms(xf86OutputPtr output, int mode)
202 NVOutputPrivatePtr nv_output = output->driver_private;
203 NVPtr pNv = NVPTR(output->scrn);
204 xf86CrtcPtr crtc = output->crtc;
205 if (!crtc) /* we need nv_crtc, so give up */
207 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
209 ErrorF("nv_lvds_output_dpms is called with mode %d\n", mode);
211 dpms_update_output_ramdac(output, mode);
213 if (!pNv->dcb_table.entry[nv_output->dcb_entry].lvdsconf.use_power_scripts)
217 case DPMSModeStandby:
218 case DPMSModeSuspend:
219 call_lvds_script(output->scrn, nv_crtc->head, nv_output->dcb_entry, LVDS_BACKLIGHT_OFF, 0);
222 call_lvds_script(output->scrn, nv_crtc->head, nv_output->dcb_entry, LVDS_PANEL_OFF, 0);
225 call_lvds_script(output->scrn, nv_crtc->head, nv_output->dcb_entry, LVDS_PANEL_ON, 0);
232 nv_analog_output_dpms(xf86OutputPtr output, int mode)
234 xf86CrtcPtr crtc = output->crtc;
236 ErrorF("nv_analog_output_dpms is called with mode %d\n", mode);
238 dpms_update_output_ramdac(output, mode);
241 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
243 ErrorF("nv_analog_output_dpms is called for CRTC %d with mode %d\n", nv_crtc->head, mode);
248 nv_tmds_output_dpms(xf86OutputPtr output, int mode)
250 xf86CrtcPtr crtc = output->crtc;
251 NVPtr pNv = NVPTR(output->scrn);
253 ErrorF("nv_tmds_output_dpms is called with mode %d\n", mode);
255 dpms_update_output_ramdac(output, mode);
257 /* Are we assigned a ramdac already?, else we will be activated during mode set */
259 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
261 ErrorF("nv_tmds_output_dpms is called for CRTC %d with mode %d\n", nv_crtc->head, mode);
263 CARD32 fpcontrol = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL);
265 case DPMSModeStandby:
266 case DPMSModeSuspend:
268 /* cut the TMDS output */
269 fpcontrol |= 0x20000022;
272 /* disable cutting the TMDS output */
273 fpcontrol &= ~0x20000022;
276 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, fpcontrol);
280 void nv_output_save_state_ext(xf86OutputPtr output, RIVA_HW_STATE *state)
282 NVOutputPrivatePtr nv_output = output->driver_private;
286 regp = &state->dac_reg[nv_output->output_resource];
288 regp->output = NVOutputReadRAMDAC(output, NV_RAMDAC_OUTPUT);
290 /* NV11's don't seem to like this, so let's restrict it to digital outputs only. */
291 if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS) {
292 /* Store the registers in case we need them again for something (like data for VT restore) */
293 for (i = 0; i < 0xFF; i++) {
294 regp->TMDS[i] = NVOutputReadTMDS(output, i);
297 for (i = 0; i < 0xFF; i++) {
298 regp->TMDS2[i] = NVOutputReadTMDS2(output, i);
303 void nv_output_load_state_ext(xf86OutputPtr output, RIVA_HW_STATE *state, Bool override)
305 NVOutputPrivatePtr nv_output = output->driver_private;
308 regp = &state->dac_reg[nv_output->output_resource];
310 /* This exists purely for proper text mode restore */
311 if (override) NVOutputWriteRAMDAC(output, NV_RAMDAC_OUTPUT, regp->output);
314 /* NOTE: Don't rely on this data for anything other than restoring VT's */
317 nv_output_save (xf86OutputPtr output)
319 ScrnInfoPtr pScrn = output->scrn;
320 NVPtr pNv = NVPTR(pScrn);
321 RIVA_HW_STATE *state;
323 ErrorF("nv_output_save is called\n");
324 state = &pNv->SavedReg;
326 /* Due to strange mapping of outputs we could have swapped analog and digital */
327 /* So we force save all the registers */
328 nv_output_save_state_ext(output, state);
331 uint32_t nv_calc_tmds_clock_from_pll(xf86OutputPtr output)
333 ScrnInfoPtr pScrn = output->scrn;
334 NVPtr pNv = NVPTR(pScrn);
335 RIVA_HW_STATE *state;
337 NVOutputPrivatePtr nv_output = output->driver_private;
339 state = &pNv->SavedReg;
340 /* Registers are stored by their preferred ramdac */
341 regp = &state->dac_reg[nv_output->output_resource];
343 /* Only do it once for a dvi-d/dvi-a pair */
344 Bool swapped_clock = FALSE;
345 Bool vpllb_disabled = FALSE;
346 /* Bit3 swaps crtc (clocks are bound to crtc) and output */
347 if (regp->TMDS[0x4] & (1 << 3)) {
348 swapped_clock = TRUE;
351 uint8_t vpll_num = swapped_clock ^ nv_output->preferred_output;
356 /* For the moment the syntax is the same for NV40 and earlier */
357 if (pNv->Architecture == NV_ARCH_40) {
358 vplla = vpll_num ? state->vpll2_a : state->vpll1_a;
359 vpllb = vpll_num ? state->vpll2_b : state->vpll1_b;
361 vplla = vpll_num ? state->vpll2 : state->vpll;
362 if (pNv->twoStagePLL)
363 vpllb = vpll_num ? state->vpll2B : state->vpllB;
366 if (!pNv->twoStagePLL)
367 vpllb_disabled = TRUE;
369 /* This is the dummy value nvidia sets when vpll is disabled */
370 if ((vpllb & 0xFFFF) == 0x11F)
371 vpllb_disabled = TRUE;
373 uint8_t m1, m2, n1, n2, p;
376 n1 = (vplla >> 8) & 0xFF;
377 p = (vplla >> 16) & 0x7;
379 if (vpllb_disabled) {
384 n2 = (vpllb >> 8) & 0xFF;
387 uint32_t clock = ((pNv->CrystalFreqKHz * n1 * n2)/(m1 * m2)) >> p;
388 ErrorF("The original bios clock seems to have been %d kHz\n", clock);
392 void nv_set_tmds_registers(xf86OutputPtr output, uint32_t clock, Bool override, Bool crosswired)
394 ScrnInfoPtr pScrn = output->scrn;
395 NVOutputPrivatePtr nv_output = output->driver_private;
396 xf86CrtcPtr crtc = output->crtc;
397 /* We have no crtc, so what are we supposed to do now? */
398 /* This can only happen during VT restore */
399 if (crtc && !override) {
400 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
402 * Resetting all registers is a bad idea, it seems to work fine without it.
404 if (nv_output->type == OUTPUT_TMDS)
405 run_tmds_table(pScrn, nv_output->dcb_entry, nv_crtc->head, clock/10);
407 call_lvds_script(pScrn, nv_crtc->head, nv_output->dcb_entry, LVDS_RESET, clock / 10);
410 * We have no crtc, but we do know what output we are and if we were crosswired.
411 * We can determine our crtc from this.
413 if (nv_output->type == OUTPUT_TMDS)
414 run_tmds_table(pScrn, nv_output->dcb_entry, nv_output->preferred_output ^ crosswired, clock/10);
416 call_lvds_script(pScrn, nv_output->preferred_output ^ crosswired, nv_output->dcb_entry, LVDS_RESET, clock / 10);
417 call_lvds_script(pScrn, nv_output->preferred_output ^ crosswired, nv_output->dcb_entry, LVDS_PANEL_ON, 0);
423 nv_output_restore (xf86OutputPtr output)
425 ScrnInfoPtr pScrn = output->scrn;
426 NVPtr pNv = NVPTR(pScrn);
427 RIVA_HW_STATE *state;
428 NVOutputPrivatePtr nv_output = output->driver_private;
429 ErrorF("nv_output_restore is called\n");
431 state = &pNv->SavedReg;
432 /* Select the default output resource for consistent restore. */
433 if (ffs(pNv->dcb_table.entry[nv_output->dcb_entry].or) & OUTPUT_1) {
434 nv_output->output_resource = 1;
436 nv_output->output_resource = 0;
439 /* Due to strange mapping of outputs we could have swapped analog and digital */
440 /* So we force load all the registers */
441 nv_output_load_state_ext(output, state, TRUE);
445 nv_output_mode_valid(xf86OutputPtr output, DisplayModePtr pMode)
447 if (pMode->Flags & V_DBLSCAN)
448 return MODE_NO_DBLESCAN;
450 if (pMode->Clock > 400000 || pMode->Clock < 25000)
451 return MODE_CLOCK_RANGE;
458 nv_output_mode_fixup(xf86OutputPtr output, DisplayModePtr mode,
459 DisplayModePtr adjusted_mode)
461 NVOutputPrivatePtr nv_output = output->driver_private;
462 ErrorF("nv_output_mode_fixup is called\n");
464 /* For internal panels and gpu scaling on DVI we need the native mode */
465 if ((nv_output->type == OUTPUT_LVDS || (nv_output->type == OUTPUT_TMDS && nv_output->scaling_mode != SCALE_PANEL))) {
466 adjusted_mode->HDisplay = nv_output->native_mode->HDisplay;
467 adjusted_mode->HSkew = nv_output->native_mode->HSkew;
468 adjusted_mode->HSyncStart = nv_output->native_mode->HSyncStart;
469 adjusted_mode->HSyncEnd = nv_output->native_mode->HSyncEnd;
470 adjusted_mode->HTotal = nv_output->native_mode->HTotal;
471 adjusted_mode->VDisplay = nv_output->native_mode->VDisplay;
472 adjusted_mode->VScan = nv_output->native_mode->VScan;
473 adjusted_mode->VSyncStart = nv_output->native_mode->VSyncStart;
474 adjusted_mode->VSyncEnd = nv_output->native_mode->VSyncEnd;
475 adjusted_mode->VTotal = nv_output->native_mode->VTotal;
476 adjusted_mode->Clock = nv_output->native_mode->Clock;
478 xf86SetModeCrtc(adjusted_mode, INTERLACE_HALVE_V);
485 nv_output_mode_set_regs(xf86OutputPtr output, DisplayModePtr mode, DisplayModePtr adjusted_mode)
487 NVOutputPrivatePtr nv_output = output->driver_private;
488 ScrnInfoPtr pScrn = output->scrn;
489 //RIVA_HW_STATE *state;
490 //NVOutputRegPtr regp, savep;
492 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
495 /* It's getting quiet here, not removing function just yet, we may still need it */
497 //state = &pNv->ModeReg;
498 //regp = &state->dac_reg[nv_output->output_resource];
500 if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)
504 NVCrtcPrivatePtr nv_crtc = output->crtc->driver_private;
508 for (i = 0; i < config->num_output; i++) {
509 NVOutputPrivatePtr nv_output2 = config->output[i]->driver_private;
511 /* is it this output ?? */
512 if (config->output[i] == output)
515 /* it the output connected */
516 if (config->output[i]->crtc == NULL)
520 if ((nv_output2->type == OUTPUT_ANALOG) && (nv_output->type == OUTPUT_ANALOG)) {
525 ErrorF("%d: crtc %d output %d twocrt %d twomon %d\n", is_fp, nv_crtc->head, nv_output->output_resource, two_crt, two_mon);
529 /* Only return if output is active (=have a crtc). */
532 nv_have_duallink(ScrnInfoPtr pScrn)
534 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
535 NVPtr pNv = NVPTR(pScrn);
538 for (i = 0; i < xf86_config->num_output; i++) {
539 xf86OutputPtr output = xf86_config->output[i];
540 NVOutputPrivatePtr nv_output = output->driver_private;
541 if (pNv->dcb_table.entry[nv_output->dcb_entry].duallink_possible &&
542 (pNv->dcb_table.entry[nv_output->dcb_entry].type == OUTPUT_LVDS ||
543 pNv->dcb_table.entry[nv_output->dcb_entry].type == OUTPUT_TMDS) &&
554 nv_output_mode_set_routing(xf86OutputPtr output)
556 NVOutputPrivatePtr nv_output = output->driver_private;
557 xf86CrtcPtr crtc = output->crtc;
558 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
559 ScrnInfoPtr pScrn = output->scrn;
560 NVPtr pNv = NVPTR(pScrn);
562 uint32_t output_reg[2] = {0, 0};
564 /* This is for simplicity */
565 output_reg[0] = NV_RAMDAC_OUTPUT_DAC_ENABLE;
566 output_reg[1] = NV_RAMDAC_OUTPUT_DAC_ENABLE;
568 /* Some (most?) pre-NV30 cards have switchable crtc's. */
569 if (pNv->switchable_crtc) {
570 if (nv_crtc->head == 1) {
571 output_reg[nv_output->output_resource] |= NV_RAMDAC_OUTPUT_SELECT_CRTC1;
573 output_reg[(~nv_output->output_resource) & 1] |= NV_RAMDAC_OUTPUT_SELECT_CRTC1;
577 /* The registers can't be considered seperately on most cards */
578 nvWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT, output_reg[0]);
579 nvWriteRAMDAC(pNv, 1, NV_RAMDAC_OUTPUT, output_reg[1]);
581 /* This could use refinement for flatpanels, but it should work this way */
582 if (pNv->NVArch < 0x44) {
583 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_TEST_CONTROL, 0xf0000000);
584 if (pNv->Architecture == NV_ARCH_40)
585 nvWriteRAMDAC(pNv, 0, NV_RAMDAC_670, 0xf0000000);
587 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_TEST_CONTROL, 0x00100000);
588 nvWriteRAMDAC(pNv, 0, NV_RAMDAC_670, 0x00100000);
593 nv_output_mode_set(xf86OutputPtr output, DisplayModePtr mode,
594 DisplayModePtr adjusted_mode)
596 ScrnInfoPtr pScrn = output->scrn;
597 NVPtr pNv = NVPTR(pScrn);
598 NVOutputPrivatePtr nv_output = output->driver_private;
599 RIVA_HW_STATE *state;
601 ErrorF("nv_output_mode_set is called\n");
603 state = &pNv->ModeReg;
605 nv_output_mode_set_regs(output, mode, adjusted_mode);
606 nv_output_load_state_ext(output, state, FALSE);
607 if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)
608 nv_set_tmds_registers(output, adjusted_mode->Clock, FALSE, FALSE);
610 nv_output_mode_set_routing(output);
614 nv_get_edid(xf86OutputPtr output)
616 /* no use for shared DDC output */
617 NVOutputPrivatePtr nv_output = output->driver_private;
620 if (nv_output->pDDCBus == NULL)
623 ddc_mon = xf86OutputGetEDID(output, nv_output->pDDCBus);
627 if (ddc_mon->features.input_type && (nv_output->type == OUTPUT_ANALOG))
630 if ((!ddc_mon->features.input_type) && (nv_output->type == OUTPUT_TMDS ||
631 nv_output->type == OUTPUT_LVDS))
642 nv_ddc_detect(xf86OutputPtr output)
644 xf86MonPtr m = nv_get_edid(output);
654 nv_crt_load_detect(xf86OutputPtr output)
656 ScrnInfoPtr pScrn = output->scrn;
657 NVOutputPrivatePtr nv_output = output->driver_private;
658 NVPtr pNv = NVPTR(pScrn);
659 CARD32 reg_output, reg_test_ctrl, temp;
660 Bool present = FALSE;
662 /* For some reason we get false positives on output 1, maybe due tv-out? */
663 if (nv_output->preferred_output == 1) {
667 if (nv_output->pDDCBus != NULL) {
668 xf86MonPtr ddc_mon = xf86OutputGetEDID(output, nv_output->pDDCBus);
669 /* Is there a digital flatpanel on this channel? */
670 if (ddc_mon && ddc_mon->features.input_type) {
675 reg_output = nvReadRAMDAC(pNv, nv_output->preferred_output, NV_RAMDAC_OUTPUT);
676 reg_test_ctrl = nvReadRAMDAC(pNv, nv_output->preferred_output, NV_RAMDAC_TEST_CONTROL);
678 nvWriteRAMDAC(pNv, nv_output->preferred_output, NV_RAMDAC_TEST_CONTROL, (reg_test_ctrl & ~0x00010000));
680 nvWriteRAMDAC(pNv, nv_output->preferred_output, NV_RAMDAC_OUTPUT, (reg_output & 0x0000FEEE));
683 temp = nvReadRAMDAC(pNv, nv_output->preferred_output, NV_RAMDAC_OUTPUT);
684 nvWriteRAMDAC(pNv, nv_output->preferred_output, NV_RAMDAC_OUTPUT, temp | 1);
686 nvWriteRAMDAC(pNv, nv_output->preferred_output, NV_RAMDAC_TEST_DATA, 0x94050140);
687 temp = nvReadRAMDAC(pNv, nv_output->preferred_output, NV_RAMDAC_TEST_CONTROL);
688 nvWriteRAMDAC(pNv, nv_output->preferred_output, NV_RAMDAC_TEST_CONTROL, temp | 0x1000);
692 present = (nvReadRAMDAC(pNv, nv_output->preferred_output, NV_RAMDAC_TEST_CONTROL) & (1 << 28)) ? TRUE : FALSE;
694 temp = NVOutputReadRAMDAC(output, NV_RAMDAC_TEST_CONTROL);
695 nvWriteRAMDAC(pNv, nv_output->preferred_output, NV_RAMDAC_TEST_CONTROL, temp & 0x000EFFF);
697 nvWriteRAMDAC(pNv, nv_output->preferred_output, NV_RAMDAC_OUTPUT, reg_output);
698 nvWriteRAMDAC(pNv, nv_output->preferred_output, NV_RAMDAC_TEST_CONTROL, reg_test_ctrl);
701 ErrorF("A crt was detected on output %d with no ddc support\n", nv_output->preferred_output);
708 static xf86OutputStatus
709 nv_tmds_output_detect(xf86OutputPtr output)
711 ErrorF("nv_tmds_output_detect is called\n");
713 if (nv_ddc_detect(output))
714 return XF86OutputStatusConnected;
716 return XF86OutputStatusDisconnected;
720 static xf86OutputStatus
721 nv_analog_output_detect(xf86OutputPtr output)
723 ErrorF("nv_analog_output_detect is called\n");
725 if (nv_ddc_detect(output))
726 return XF86OutputStatusConnected;
728 //if (nv_crt_load_detect(output))
729 // return XF86OutputStatusConnected;
731 return XF86OutputStatusDisconnected;
734 static DisplayModePtr
735 nv_output_get_modes(xf86OutputPtr output)
737 NVOutputPrivatePtr nv_output = output->driver_private;
739 DisplayModePtr ddc_modes;
741 ErrorF("nv_output_get_modes is called\n");
743 ddc_mon = nv_get_edid(output);
745 xf86OutputSetEDID(output, ddc_mon);
750 ddc_modes = xf86OutputGetEDIDModes (output);
752 if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS) {
756 for (i = 0; i < 4; i++) {
757 /* We only look at detailed timings atm */
758 if (ddc_mon->det_mon[i].type != DT)
760 /* Selecting only based on width ok? */
761 if (ddc_mon->det_mon[i].section.d_timings.h_active > nv_output->fpWidth) {
762 nv_output->fpWidth = ddc_mon->det_mon[i].section.d_timings.h_active;
763 nv_output->fpHeight = ddc_mon->det_mon[i].section.d_timings.v_active;
767 if (nv_output->native_mode)
768 xfree(nv_output->native_mode);
769 nv_output->native_mode = NULL;
770 if (nv_output->type == OUTPUT_TMDS) {
771 DisplayModePtr cvtmode;
772 /* Add a native resolution mode that is preferred */
773 /* Reduced blanking should be fine on DVI monitor */
774 cvtmode = xf86CVTMode(nv_output->fpWidth, nv_output->fpHeight, 60.0, TRUE, FALSE);
775 cvtmode->type = M_T_DRIVER | M_T_PREFERRED;
777 /* can xf86CVTMode generate invalid modes? */
778 if (output->funcs->mode_valid(output, cvtmode) == MODE_OK) {
779 ddc_modes = xf86ModesAdd(ddc_modes, cvtmode);
780 nv_output->native_mode = xf86DuplicateMode(cvtmode);
782 xf86DeleteMode(&cvtmode, cvtmode);
786 if (!nv_output->native_mode)
787 for (mode = ddc_modes; mode != NULL; mode = mode->next)
788 if (mode->HDisplay == nv_output->fpWidth &&
789 mode->VDisplay == nv_output->fpHeight) {
790 nv_output->native_mode = xf86DuplicateMode(mode);
793 if (!nv_output->native_mode) {
794 ErrorF("Really bad stuff happening, CVT mode bad and no other native mode can be found.\n");
795 ErrorF("Bailing out\n");
799 /* We want the new mode to be the only preferred one */
800 for (mode = ddc_modes; mode != NULL; mode = mode->next)
801 if (mode->type & M_T_PREFERRED && !xf86ModesEqual(mode, nv_output->native_mode))
802 mode->type &= ~M_T_PREFERRED;
809 nv_output_destroy (xf86OutputPtr output)
811 ErrorF("nv_output_destroy is called\n");
812 NVOutputPrivatePtr nv_output = output->driver_private;
815 if (nv_output->native_mode)
816 xfree(nv_output->native_mode);
817 xfree(output->driver_private);
822 nv_output_prepare(xf86OutputPtr output)
824 ErrorF("nv_output_prepare is called\n");
825 NVOutputPrivatePtr nv_output = output->driver_private;
826 ScrnInfoPtr pScrn = output->scrn;
827 xf86CrtcPtr crtc = output->crtc;
828 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
829 NVPtr pNv = NVPTR(pScrn);
830 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
833 output->funcs->dpms(output, DPMSModeOff);
835 /* Set our output type and output routing possibilities to the right registers */
836 NVWriteVGACR5758(pNv, nv_crtc->head, 0, pNv->dcb_table.entry[nv_output->dcb_entry].type);
837 NVWriteVGACR5758(pNv, nv_crtc->head, 2, pNv->dcb_table.entry[nv_output->dcb_entry].or);
840 * Here we detect output resource conflicts.
841 * We do this based on connected monitors, since we need to catch this before something important happens.
844 uint8_t output_resource_mask = 0;
845 for (i = 0; i < xf86_config->num_output; i++) {
846 xf86OutputPtr output2 = xf86_config->output[i];
847 NVOutputPrivatePtr nv_output2 = output2->driver_private;
849 /* I don't know how well this will deal with triple connected output situations. */
850 if (output2 != output && output2->crtc) { /* output in use? */
851 output_resource_mask |= nv_output2->output_resource;
855 uint8_t or = pNv->dcb_table.entry[nv_output->dcb_entry].or;
856 /* Do we have a output resource conflict? */
857 if (output_resource_mask & nv_output->output_resource) {
858 if (or == ffs(or)) { /* we need this output resource */
859 for (i = 0; i < xf86_config->num_output; i++) { /* let's find the other */
860 xf86OutputPtr output2 = xf86_config->output[i];
861 NVOutputPrivatePtr nv_output2 = output2->driver_private;
863 if (output2 != output && output2->status == XF86OutputStatusConnected) {
864 if (nv_output->output_resource == nv_output2->output_resource) {
865 nv_output2->output_resource ^= 1;
866 break; /* We don't deal with triple outputs yet */
870 } else { /* we have alternatives */
871 nv_output->output_resource ^= 1;
877 nv_output_commit(xf86OutputPtr output)
879 ErrorF("nv_output_commit is called\n");
881 output->funcs->dpms(output, DPMSModeOn);
884 static const xf86OutputFuncsRec nv_analog_output_funcs = {
885 .dpms = nv_analog_output_dpms,
886 .save = nv_output_save,
887 .restore = nv_output_restore,
888 .mode_valid = nv_output_mode_valid,
889 .mode_fixup = nv_output_mode_fixup,
890 .mode_set = nv_output_mode_set,
891 .detect = nv_analog_output_detect,
892 .get_modes = nv_output_get_modes,
893 .destroy = nv_output_destroy,
894 .prepare = nv_output_prepare,
895 .commit = nv_output_commit,
898 #ifdef RANDR_12_INTERFACE
900 * Several scaling modes exist, let the user choose.
902 #define SCALING_MODE_NAME "SCALING_MODE"
903 static const struct {
905 enum scaling_modes mode;
907 { "panel", SCALE_PANEL },
908 { "fullscreen", SCALE_FULLSCREEN },
909 { "aspect", SCALE_ASPECT },
910 { "noscale", SCALE_NOSCALE },
911 { NULL, SCALE_INVALID}
913 static Atom scaling_mode_atom;
916 nv_scaling_mode_lookup(char *name, int size)
920 /* for when name is zero terminated */
924 for (i = 0; scaling_mode[i].name; i++)
925 /* We're getting non-terminated strings */
926 if (strlen(scaling_mode[i].name) >= size &&
927 !strncasecmp(name, scaling_mode[i].name, size))
930 return scaling_mode[i].mode;
934 nv_digital_output_create_resources(xf86OutputPtr output)
936 NVOutputPrivatePtr nv_output = output->driver_private;
937 ScrnInfoPtr pScrn = output->scrn;
941 * Setup scaling mode property.
943 scaling_mode_atom = MakeAtom(SCALING_MODE_NAME, sizeof(SCALING_MODE_NAME) - 1, TRUE);
945 error = RRConfigureOutputProperty(output->randr_output,
946 scaling_mode_atom, TRUE, FALSE, FALSE,
950 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
951 "RRConfigureOutputProperty error, %d\n", error);
954 char *existing_scale_name = NULL;
955 for (i = 0; scaling_mode[i].name; i++)
956 if (scaling_mode[i].mode == nv_output->scaling_mode)
957 existing_scale_name = scaling_mode[i].name;
959 error = RRChangeOutputProperty(output->randr_output, scaling_mode_atom,
960 XA_STRING, 8, PropModeReplace,
961 strlen(existing_scale_name),
962 existing_scale_name, FALSE, TRUE);
965 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
966 "Failed to set scaling mode, %d\n", error);
971 nv_digital_output_set_property(xf86OutputPtr output, Atom property,
972 RRPropertyValuePtr value)
974 NVOutputPrivatePtr nv_output = output->driver_private;
976 if (property == scaling_mode_atom) {
980 if (value->type != XA_STRING || value->format != 8)
983 name = (char *) value->data;
985 /* Match a string to a scaling mode */
986 ret = nv_scaling_mode_lookup(name, value->size);
987 if (ret == SCALE_INVALID)
990 /* LVDS must always use gpu scaling. */
991 if (ret == SCALE_PANEL && nv_output->type == OUTPUT_LVDS)
994 nv_output->scaling_mode = ret;
1001 #endif /* RANDR_12_INTERFACE */
1004 nv_tmds_output_mode_valid(xf86OutputPtr output, DisplayModePtr pMode)
1006 ScrnInfoPtr pScrn = output->scrn;
1007 NVPtr pNv = NVPTR(pScrn);
1008 NVOutputPrivatePtr nv_output = output->driver_private;
1010 /* We can't exceed the native mode.*/
1011 if (pMode->HDisplay > nv_output->fpWidth || pMode->VDisplay > nv_output->fpHeight)
1014 if (pNv->dcb_table.entry[nv_output->dcb_entry].duallink_possible) {
1015 if (pMode->Clock > 330000) /* 2x165 MHz */
1016 return MODE_CLOCK_RANGE;
1018 if (pMode->Clock > 165000) /* 165 MHz */
1019 return MODE_CLOCK_RANGE;
1022 return nv_output_mode_valid(output, pMode);
1025 static const xf86OutputFuncsRec nv_tmds_output_funcs = {
1026 .dpms = nv_tmds_output_dpms,
1027 .save = nv_output_save,
1028 .restore = nv_output_restore,
1029 .mode_valid = nv_tmds_output_mode_valid,
1030 .mode_fixup = nv_output_mode_fixup,
1031 .mode_set = nv_output_mode_set,
1032 .detect = nv_tmds_output_detect,
1033 .get_modes = nv_output_get_modes,
1034 .destroy = nv_output_destroy,
1035 .prepare = nv_output_prepare,
1036 .commit = nv_output_commit,
1037 #ifdef RANDR_12_INTERFACE
1038 .create_resources = nv_digital_output_create_resources,
1039 .set_property = nv_digital_output_set_property,
1040 #endif /* RANDR_12_INTERFACE */
1043 static int nv_lvds_output_mode_valid
1044 (xf86OutputPtr output, DisplayModePtr pMode)
1046 NVOutputPrivatePtr nv_output = output->driver_private;
1048 /* No modes > panel's native res */
1049 if (pMode->HDisplay > nv_output->fpWidth || pMode->VDisplay > nv_output->fpHeight)
1052 return nv_output_mode_valid(output, pMode);
1055 static xf86OutputStatus
1056 nv_lvds_output_detect(xf86OutputPtr output)
1058 ErrorF("nv_lvds_output_detect is called\n");
1059 ScrnInfoPtr pScrn = output->scrn;
1060 NVPtr pNv = NVPTR(pScrn);
1061 NVOutputPrivatePtr nv_output = output->driver_private;
1063 if (pNv->dcb_table.entry[nv_output->dcb_entry].lvdsconf.use_straps_for_mode &&
1064 pNv->VBIOS.fp.native_mode)
1065 return XF86OutputStatusConnected;
1066 if (nv_ddc_detect(output))
1067 return XF86OutputStatusConnected;
1069 return XF86OutputStatusDisconnected;
1072 static DisplayModePtr
1073 nv_lvds_output_get_modes(xf86OutputPtr output)
1075 ErrorF("nv_lvds_output_get_modes is called\n");
1076 ScrnInfoPtr pScrn = output->scrn;
1077 NVPtr pNv = NVPTR(pScrn);
1078 NVOutputPrivatePtr nv_output = output->driver_private;
1079 DisplayModePtr modes;
1081 if ((modes = nv_output_get_modes(output)))
1084 /* it is possible to set up a mode from what we can read from the
1085 * RAMDAC registers, but if we can't read the BIOS table correctly
1086 * we might as well give up */
1087 if (!pNv->dcb_table.entry[nv_output->dcb_entry].lvdsconf.use_straps_for_mode ||
1088 (pNv->VBIOS.fp.native_mode == NULL))
1091 nv_output->fpWidth = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_HDISP_END) + 1;
1092 nv_output->fpHeight = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_VDISP_END) + 1;
1093 nv_output->fpSyncs = NVOutputReadRAMDAC(output, NV_RAMDAC_FP_CONTROL) & 0x30000033;
1095 if (pNv->VBIOS.fp.native_mode->HDisplay != nv_output->fpWidth ||
1096 pNv->VBIOS.fp.native_mode->VDisplay != nv_output->fpHeight) {
1097 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1098 "Panel size mismatch; ignoring RAMDAC\n");
1099 nv_output->fpWidth = pNv->VBIOS.fp.native_mode->HDisplay;
1100 nv_output->fpHeight = pNv->VBIOS.fp.native_mode->VDisplay;
1103 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Panel size is %u x %u\n",
1104 nv_output->fpWidth, nv_output->fpHeight);
1106 nv_output->native_mode = xf86DuplicateMode(pNv->VBIOS.fp.native_mode);
1108 return xf86DuplicateMode(pNv->VBIOS.fp.native_mode);
1111 static const xf86OutputFuncsRec nv_lvds_output_funcs = {
1112 .dpms = nv_lvds_output_dpms,
1113 .save = nv_output_save,
1114 .restore = nv_output_restore,
1115 .mode_valid = nv_lvds_output_mode_valid,
1116 .mode_fixup = nv_output_mode_fixup,
1117 .mode_set = nv_output_mode_set,
1118 .detect = nv_lvds_output_detect,
1119 .get_modes = nv_lvds_output_get_modes,
1120 .destroy = nv_output_destroy,
1121 .prepare = nv_output_prepare,
1122 .commit = nv_output_commit,
1123 #ifdef RANDR_12_INTERFACE
1124 .create_resources = nv_digital_output_create_resources,
1125 .set_property = nv_digital_output_set_property,
1126 #endif /* RANDR_12_INTERFACE */
1129 static void nv_add_analog_output(ScrnInfoPtr pScrn, int dcb_entry, Bool dvi_pair)
1131 NVPtr pNv = NVPTR(pScrn);
1132 xf86OutputPtr output;
1133 NVOutputPrivatePtr nv_output;
1134 char outputname[20];
1135 Bool create_output = TRUE;
1136 int i2c_index = pNv->dcb_table.entry[dcb_entry].i2c_index;
1138 /* DVI have an analog connector and a digital one, differentiate between that and a normal vga */
1140 sprintf(outputname, "DVI-A-%d", pNv->dvi_a_count);
1143 sprintf(outputname, "VGA-%d", pNv->vga_count);
1147 nv_output = xnfcalloc (sizeof (NVOutputPrivateRec), 1);
1152 nv_output->dcb_entry = dcb_entry;
1154 if (pNv->dcb_table.i2c_read[i2c_index] && pNv->pI2CBus[i2c_index] == NULL)
1155 NV_I2CInit(pScrn, &pNv->pI2CBus[i2c_index], pNv->dcb_table.i2c_read[i2c_index], xstrdup(outputname));
1157 nv_output->type = OUTPUT_ANALOG;
1160 * bit0: OUTPUT_0 valid
1161 * bit1: OUTPUT_1 valid
1162 * So lowest order has highest priority.
1163 * Below is guesswork:
1164 * bit2: All outputs valid
1166 /* We choose the preferred output resource initially. */
1167 if (ffs(pNv->dcb_table.entry[dcb_entry].or) & OUTPUT_1) {
1168 nv_output->preferred_output = 1;
1169 nv_output->output_resource = 1;
1171 nv_output->preferred_output = 0;
1172 nv_output->output_resource = 0;
1175 nv_output->bus = pNv->dcb_table.entry[dcb_entry].bus;
1177 if (!create_output) {
1182 /* Delay creation of output until we actually know we want it */
1183 output = xf86OutputCreate (pScrn, &nv_analog_output_funcs, outputname);
1187 output->driver_private = nv_output;
1189 nv_output->pDDCBus = pNv->pI2CBus[i2c_index];
1191 if (pNv->switchable_crtc) {
1192 output->possible_crtcs = pNv->dcb_table.entry[dcb_entry].heads;
1194 output->possible_crtcs = (1 << nv_output->preferred_output);
1197 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Adding output %s\n", outputname);
1200 static void nv_add_digital_output(ScrnInfoPtr pScrn, int dcb_entry, int lvds)
1202 NVPtr pNv = NVPTR(pScrn);
1203 xf86OutputPtr output;
1204 NVOutputPrivatePtr nv_output;
1205 char outputname[20];
1206 Bool create_output = TRUE;
1207 int i2c_index = pNv->dcb_table.entry[dcb_entry].i2c_index;
1210 sprintf(outputname, "LVDS-%d", pNv->lvds_count);
1213 sprintf(outputname, "DVI-D-%d", pNv->dvi_d_count);
1217 nv_output = xnfcalloc (sizeof (NVOutputPrivateRec), 1);
1223 nv_output->dcb_entry = dcb_entry;
1225 if (pNv->dcb_table.i2c_read[i2c_index] && pNv->pI2CBus[i2c_index] == NULL)
1226 NV_I2CInit(pScrn, &pNv->pI2CBus[i2c_index], pNv->dcb_table.i2c_read[i2c_index], xstrdup(outputname));
1228 nv_output->pDDCBus = pNv->pI2CBus[i2c_index];
1231 * bit0: OUTPUT_0 valid
1232 * bit1: OUTPUT_1 valid
1233 * So lowest order has highest priority.
1234 * Below is guesswork:
1235 * bit2: All outputs valid
1237 /* We choose the preferred output resource initially. */
1238 if (ffs(pNv->dcb_table.entry[dcb_entry].or) & OUTPUT_1) {
1239 nv_output->preferred_output = 1;
1240 nv_output->output_resource = 1;
1242 nv_output->preferred_output = 0;
1243 nv_output->output_resource = 0;
1246 nv_output->bus = pNv->dcb_table.entry[dcb_entry].bus;
1249 nv_output->type = OUTPUT_LVDS;
1250 /* comment below two lines to test LVDS under RandR12.
1251 * If your screen "blooms" or "bleeds" (i.e. has a developing
1252 * white / psychedelic pattern) then KILL X IMMEDIATELY
1253 * (ctrl+alt+backspace) & if the effect continues reset power */
1254 ErrorF("Output refused because we don't accept LVDS at the moment.\n");
1255 create_output = FALSE;
1257 nv_output->type = OUTPUT_TMDS;
1260 if (!create_output) {
1265 /* Delay creation of output until we are certain is desirable */
1267 output = xf86OutputCreate (pScrn, &nv_lvds_output_funcs, outputname);
1269 output = xf86OutputCreate (pScrn, &nv_tmds_output_funcs, outputname);
1273 output->driver_private = nv_output;
1275 if (pNv->fpScaler) /* GPU Scaling */
1276 nv_output->scaling_mode = SCALE_ASPECT;
1277 else /* Panel scaling */
1278 nv_output->scaling_mode = SCALE_PANEL;
1280 #ifdef RANDR_12_INTERFACE
1281 if (xf86GetOptValString(pNv->Options, OPTION_SCALING_MODE)) {
1282 nv_output->scaling_mode = nv_scaling_mode_lookup(xf86GetOptValString(pNv->Options, OPTION_SCALING_MODE), -1);
1283 if (nv_output->scaling_mode == SCALE_INVALID)
1284 nv_output->scaling_mode = SCALE_ASPECT; /* default */
1286 #endif /* RANDR_12_INTERFACE */
1288 /* Due to serious problems we have to restrict the crtc's for certain types of outputs. */
1289 /* This is a result of problems with G70 cards that have a dvi with ffs(or) == 1 */
1290 /* Anyone know what the solution for this is? */
1291 if (nv_output->preferred_output == 0) {
1292 output->possible_crtcs = (1 << 0);
1294 if (pNv->switchable_crtc) {
1295 output->possible_crtcs = pNv->dcb_table.entry[dcb_entry].heads;
1297 output->possible_crtcs = (1 << nv_output->preferred_output);
1301 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Adding output %s\n", outputname);
1304 void NvDCBSetupOutputs(ScrnInfoPtr pScrn)
1306 NVPtr pNv = NVPTR(pScrn);
1307 int i, type, i2c_count[0xf];
1309 pNv->switchable_crtc = FALSE;
1310 /* I was wrong, again. */
1311 if (pNv->NVArch > 0x11 && pNv->twoHeads)
1312 pNv->switchable_crtc = TRUE;
1314 memset(i2c_count, 0, sizeof(i2c_count));
1315 for (i = 0 ; i < pNv->dcb_table.entries; i++)
1316 i2c_count[pNv->dcb_table.entry[i].i2c_index]++;
1318 /* we setup the outputs up from the BIOS table */
1319 for (i = 0 ; i < pNv->dcb_table.entries; i++) {
1320 type = pNv->dcb_table.entry[i].type;
1322 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DCB type %d not known\n", type);
1326 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "DCB entry %d: type: %d, i2c_index: %d, heads: %d, bus: %d, or: %d\n", i, type, pNv->dcb_table.entry[i].i2c_index, pNv->dcb_table.entry[i].heads, pNv->dcb_table.entry[i].bus, pNv->dcb_table.entry[i].or);
1330 nv_add_analog_output(pScrn, i, (i2c_count[pNv->dcb_table.entry[i].i2c_index] > 1));
1333 nv_add_digital_output(pScrn, i, 0);
1336 nv_add_digital_output(pScrn, i, 1);
1344 void NvSetupOutputs(ScrnInfoPtr pScrn)
1346 NVPtr pNv = NVPTR(pScrn);
1348 pNv->Television = FALSE;
1350 memset(pNv->pI2CBus, 0, sizeof(pNv->pI2CBus));
1351 NvDCBSetupOutputs(pScrn);
1354 /*************************************************************************** \
1356 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
1358 |* NOTICE TO USER: The source code is copyrighted under U.S. and *|
1359 |* international laws. Users and possessors of this source code are *|
1360 |* hereby granted a nonexclusive, royalty-free copyright license to *|
1361 |* use this code in individual and commercial software. *|
1363 |* Any use of this source code must include, in the user documenta- *|
1364 |* tion and internal comments to the code, notices to the end user *|
1367 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
1369 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
1370 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
1371 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
1372 |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
1373 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
1374 |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
1375 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
1376 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
1377 |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
1378 |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
1379 |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
1381 |* U.S. Government End Users. This source code is a "commercial *|
1382 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
1383 |* consisting of "commercial computer software" and "commercial *|
1384 |* computer software documentation," as such terms are used in *|
1385 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
1386 |* ment only as a commercial end item. Consistent with 48 C.F.R. *|
1387 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
1388 |* all U.S. Government End Users acquire the source code with only *|
1389 |* those rights set forth herein. *|
1391 \***************************************************************************/