git.oblomov.eu Git - nouveau/blob - src/nv50_display.c

   1 /*
   2  * Copyright (c) 2007 NVIDIA, Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sublicense, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included
  13  * in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  16  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  18  * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
  19  * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  20  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  21  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <float.h>
  25 #include <math.h>
  26 #include <strings.h>
  27 #include <unistd.h>
  28
  29 #include "nv_include.h"
  30 #include "nv50_type.h"
  31 #include "nv50_cursor.h"
  32 #include "nv50_display.h"
  33 #include "nv50_output.h"
  34
  35 static void NV50CrtcShowHideCursor(xf86CrtcPtr crtc, Bool show, Bool update);
  36
  37 /*
  38  * PLL calculation.  pclk is in kHz.
  39  */
  40 static void
  41 NV50CalcPLL(float pclk, int *pNA, int *pMA, int *pNB, int *pMB, int *pP)
  42 {
  43     const float refclk = 27000.0f;
  44     const float minVcoA = 100000;
  45     const float maxVcoA = 400000;
  46     const float minVcoB = 600000;
  47     float maxVcoB = 1400000;
  48     const float minUA = 2000;
  49     const float maxUA = 400000;
  50     const float minUB = 50000;
  51     const float maxUB = 200000;
  52     const int minNA = 1, maxNA = 255;
  53     const int minNB = 1, maxNB = 31;
  54     const int minMA = 1, maxMA = 255;
  55     const int minMB = 1, maxMB = 31;
  56     const int minP = 0, maxP = 6;
  57     int lowP, highP;
  58     float vcoB;
  59
  60     int na, ma, nb, mb, p;
  61     float bestError = FLT_MAX;
  62
  63     *pNA = *pMA = *pNB = *pMB = *pP = 0;
  64
  65     if(maxVcoB < pclk + pclk / 200)
  66         maxVcoB = pclk + pclk / 200;
  67     if(minVcoB / (1 << maxP) > pclk)
  68         pclk = minVcoB / (1 << maxP);
  69
  70     vcoB = maxVcoB - maxVcoB / 200;
  71     lowP = minP;
  72     vcoB /= 1 << (lowP + 1);
  73
  74     while(pclk <= vcoB && lowP < maxP)
  75     {
  76         vcoB /= 2;
  77         lowP++;
  78     }
  79
  80     vcoB = maxVcoB + maxVcoB / 200;
  81     highP = lowP;
  82     vcoB /= 1 << (highP + 1);
  83
  84     while(pclk <= vcoB && highP < maxP)
  85     {
  86         vcoB /= 2;
  87         highP++;
  88     }
  89
  90     for(p = lowP; p <= highP; p++)
  91     {
  92         for(ma = minMA; ma <= maxMA; ma++)
  93         {
  94             if(refclk / ma < minUA)
  95                 break;
  96             else if(refclk / ma > maxUA)
  97                 continue;
  98
  99             for(na = minNA; na <= maxNA; na++)
 100             {
 101                 if(refclk * na / ma < minVcoA || refclk * na / ma > maxVcoA)
 102                     continue;
 103
 104                 for(mb = minMB; mb <= maxMB; mb++)
 105                 {
 106                     if(refclk * na / ma / mb < minUB)
 107                         break;
 108                     else if(refclk * na / ma / mb > maxUB)
 109                         continue;
 110
 111                     nb = rint(pclk * (1 << p) * (ma / (float)na) * mb / refclk);
 112
 113                     if(nb > maxNB)
 114                         break;
 115                     else if(nb < minNB)
 116                         continue;
 117                     else
 118                     {
 119                         float freq = refclk * (na / (float)ma) * (nb / (float)mb) / (1 << p);
 120                         float error = fabsf(pclk - freq);
 121                         if(error < bestError) {
 122                             *pNA = na;
 123                             *pMA = ma;
 124                             *pNB = nb;
 125                             *pMB = mb;
 126                             *pP = p;
 127                             bestError = error;
 128                         }
 129                     }
 130                 }
 131             }
 132         }
 133     }
 134 }
 135
 136 void NV50CrtcSetPClk(xf86CrtcPtr crtc)
 137 {
 138         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 139         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(crtc->scrn);
 140         ScrnInfoPtr pScrn = crtc->scrn;
 141         NVPtr pNv = NVPTR(pScrn);
 142         int lo_n, lo_m, hi_n, hi_m, p, i;
 143         /* These clocks are probably rerouted from the 0x4000 range to the 0x610000 range */
 144         CARD32 lo = NVRead(pNv, nv_crtc->head ? NV50_CRTC_VPLL2_A : NV50_CRTC_VPLL1_A);
 145         CARD32 hi = NVRead(pNv, nv_crtc->head ? NV50_CRTC_VPLL2_B : NV50_CRTC_VPLL1_B);
 146
 147         NVWrite(pNv, 0x00614100 + nv_crtc->head * 0x800, 0x10000610);
 148         lo &= 0xff00ff00;
 149         hi &= 0x8000ff00;
 150
 151         NV50CalcPLL(nv_crtc->pclk, &lo_n, &lo_m, &hi_n, &hi_m, &p);
 152
 153         lo |= (lo_m << 16) | lo_n;
 154         hi |= (p << 28) | (hi_m << 16) | hi_n;
 155         NVWrite(pNv, nv_crtc->head ? NV50_CRTC_VPLL2_A : NV50_CRTC_VPLL1_A, lo);
 156         NVWrite(pNv, nv_crtc->head ? NV50_CRTC_VPLL2_B : NV50_CRTC_VPLL1_B, hi);
 157         NVWrite(pNv, 0x00614200 + nv_crtc->head * 0x800, 0);
 158
 159         for(i = 0; i < xf86_config->num_output; i++) {
 160                 xf86OutputPtr output = xf86_config->output[i];
 161
 162                 if(output->crtc != crtc)
 163                         continue;
 164                 NV50OutputSetPClk(output, nv_crtc->pclk);
 165         }
 166 }
 167
 168 Head
 169 NV50CrtcGetHead(xf86CrtcPtr crtc)
 170 {
 171         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 172         return nv_crtc->head;
 173 }
 174
 175 Bool
 176 NV50DispPreInit(ScrnInfoPtr pScrn)
 177 {
 178         NVPtr pNv = NVPTR(pScrn);
 179         /* These labels are guesswork based on symmetry (2 SOR's and 3 DAC's exist)*/
 180         NVWrite(pNv, 0x00610184, NVRead(pNv, 0x00614004));
 181         NVWrite(pNv, 0x00610190 + SOR0 * 0x10, NVRead(pNv, 0x00616100 + SOR0 * 0x800));
 182         NVWrite(pNv, 0x00610190 + SOR1 * 0x10, NVRead(pNv, 0x00616100 + SOR1 * 0x800));
 183         NVWrite(pNv, 0x00610194 + SOR0 * 0x10, NVRead(pNv, 0x00616104 + SOR0 * 0x800));
 184         NVWrite(pNv, 0x00610194 + SOR1 * 0x10, NVRead(pNv, 0x00616104 + SOR1 * 0x800));
 185         NVWrite(pNv, 0x00610198 + SOR0 * 0x10, NVRead(pNv, 0x00616108 + SOR0 * 0x800));
 186         NVWrite(pNv, 0x00610198 + SOR1 * 0x10, NVRead(pNv, 0x00616108 + SOR1 * 0x800));
 187         NVWrite(pNv, 0x0061019c + SOR0 * 0x10, NVRead(pNv, 0x0061610c + SOR0 * 0x800));
 188         NVWrite(pNv, 0x0061019c + SOR1 * 0x10, NVRead(pNv, 0x0061610c + SOR1 * 0x800));
 189         NVWrite(pNv, 0x006101d0 + DAC0 * 0x4, NVRead(pNv, 0x0061a000 + DAC0 * 0x800));
 190         NVWrite(pNv, 0x006101d0 + DAC1 * 0x4, NVRead(pNv, 0x0061a000 + DAC1 * 0x800));
 191         NVWrite(pNv, 0x006101d0 + DAC2 * 0x4, NVRead(pNv, 0x0061a000 + DAC2 * 0x800));
 192         NVWrite(pNv, 0x006101e0 + SOR0 * 0x4, NVRead(pNv, 0x0061c000 + SOR0 * 0x800));
 193         NVWrite(pNv, 0x006101e0 + SOR1 * 0x4, NVRead(pNv, 0x0061c000 + SOR1 * 0x800));
 194         NVWrite(pNv, 0x0061a004 + DAC0 * 0x800, 0x80550000);
 195         NVWrite(pNv, 0x0061a010 + DAC0 * 0x800, 0x00000001);
 196         NVWrite(pNv, 0x0061a004 + DAC1 * 0x800, 0x80550000);
 197         NVWrite(pNv, 0x0061a010 + DAC1 * 0x800, 0x00000001);
 198         NVWrite(pNv, 0x0061a004 + DAC2 * 0x800, 0x80550000);
 199         NVWrite(pNv, 0x0061a010 + DAC2 * 0x800, 0x00000001);
 200
 201         return TRUE;
 202 }
 203
 204 Bool
 205 NV50DispInit(ScrnInfoPtr pScrn)
 206 {
 207         NVPtr pNv = NVPTR(pScrn);
 208         if (NVRead(pNv, 0x00610024) & 0x100) {
 209                 NVWrite(pNv, 0x00610024, 0x100);
 210                 NVWrite(pNv, 0x006194e8, NVRead(pNv, 0x006194e8) & ~1);
 211                 while (NVRead(pNv, 0x006194e8) & 2);
 212         }
 213
 214         NVWrite(pNv, 0x00610200, 0x2b00);
 215         /* A bugfix (#12637) from the nv driver, to unlock the driver if it's left in a poor state */
 216         do {
 217                 CARD32 val = NVRead(pNv, 0x00610200);
 218                 if ((val & 0x9f0000) == 0x20000)
 219                         NVWrite(pNv, 0x00610200, val | 0x800000);
 220
 221                 if ((val & 0x3f0000) == 0x30000)
 222                         NVWrite(pNv, 0x00610200, val | 0x200000);
 223         } while ((NVRead(pNv, 0x00610200) & 0x1e0000) != 0);
 224         NVWrite(pNv, 0x00610300, 0x1);
 225         NVWrite(pNv, 0x00610200, 0x1000b03);
 226         while (!(NVRead(pNv, 0x00610200) & 0x40000000));
 227
 228         NV50DisplayCommand(pScrn, 0x84, 0);
 229         NV50DisplayCommand(pScrn, 0x88, 0);
 230         NV50DisplayCommand(pScrn, 0x874, 0);
 231         NV50DisplayCommand(pScrn, 0x800, 0);
 232         NV50DisplayCommand(pScrn, 0x810, 0);
 233         NV50DisplayCommand(pScrn, 0x82c, 0);
 234
 235         return TRUE;
 236 }
 237
 238 void
 239 NV50DispShutdown(ScrnInfoPtr pScrn)
 240 {
 241         NVPtr pNv = NVPTR(pScrn);
 242         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 243         int i;
 244
 245         for(i = 0; i < xf86_config->num_crtc; i++) {
 246                 xf86CrtcPtr crtc = xf86_config->crtc[i];
 247
 248                 NV50CrtcBlankScreen(crtc, TRUE);
 249         }
 250
 251         NV50DisplayCommand(pScrn, 0x80, 0);
 252
 253         for(i = 0; i < xf86_config->num_crtc; i++) {
 254                 xf86CrtcPtr crtc = xf86_config->crtc[i];
 255
 256                 if(crtc->enabled) {
 257                         const CARD32 mask = 4 << NV50CrtcGetHead(crtc);
 258
 259                         NVWrite(pNv, 0x00610024, mask);
 260                         while(!(NVRead(pNv, 0x00610024) & mask));
 261                 }
 262         }
 263
 264         NVWrite(pNv, 0x00610200, 0x0);
 265         NVWrite(pNv, 0x00610300, 0x0);
 266         while ((NVRead(pNv, 0x00610200) & 0x1e0000) != 0);
 267         while ((NVRead(pNv, 0x0061c030 + SOR0 * 0x800) & 0x10000000));
 268         while ((NVRead(pNv, 0x0061c030 + SOR1 * 0x800) & 0x10000000));
 269 }
 270
 271 void
 272 NV50CrtcDoModeFixup(DisplayModePtr dst, const DisplayModePtr src)
 273 {
 274         /* Magic mode timing fudge factor */
 275         const int fudge = ((src->Flags & V_INTERLACE) && (src->Flags & V_DBLSCAN)) ? 2 : 1;
 276         const int interlaceDiv = (src->Flags & V_INTERLACE) ? 2 : 1;
 277
 278         /* Stash the src timings in the Crtc fields in dst */
 279         dst->CrtcHBlankStart = src->CrtcVTotal << 16 | src->CrtcHTotal;
 280         dst->CrtcHSyncEnd = ((src->CrtcVSyncEnd - src->CrtcVSyncStart) / interlaceDiv - 1) << 16 |
 281                 (src->CrtcHSyncEnd - src->CrtcHSyncStart - 1);
 282         dst->CrtcHBlankEnd = ((src->CrtcVBlankEnd - src->CrtcVSyncStart) / interlaceDiv - fudge) << 16 |
 283                 (src->CrtcHBlankEnd - src->CrtcHSyncStart - 1);
 284         dst->CrtcHTotal = ((src->CrtcVTotal - src->CrtcVSyncStart + src->CrtcVBlankStart) / interlaceDiv - fudge) << 16 |
 285                 (src->CrtcHTotal - src->CrtcHSyncStart + src->CrtcHBlankStart - 1);
 286         dst->CrtcHSkew = ((src->CrtcVTotal + src->CrtcVBlankEnd - src->CrtcVSyncStart) / 2 - 2) << 16 |
 287                 ((2*src->CrtcVTotal - src->CrtcVSyncStart + src->CrtcVBlankStart) / 2 - 2);
 288 }
 289
 290 Bool
 291 NV50CrtcModeFixup(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
 292 {
 293         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 294
 295         if (nv_crtc->skipModeFixup)
 296                 return TRUE;
 297
 298         NV50CrtcDoModeFixup(adjusted_mode, mode);
 299         return TRUE;
 300 }
 301
 302 void
 303 NV50CrtcModeSet(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode, int x, int y)
 304 {
 305         ScrnInfoPtr pScrn = crtc->scrn;
 306         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 307         const int HDisplay = adjusted_mode->HDisplay;
 308         const int VDisplay = adjusted_mode->VDisplay;
 309
 310         nv_crtc->pclk = adjusted_mode->Clock;
 311
 312         /* NV50CrtcCommand includes head offset */
 313         NV50CrtcCommand(crtc, NV50_CRTC0_CLOCK, adjusted_mode->Clock | 0x800000);
 314         NV50CrtcCommand(crtc, NV50_CRTC0_INTERLACE, (adjusted_mode->Flags & V_INTERLACE) ? 2 : 0);
 315         NV50CrtcCommand(crtc, 0x810, 0);
 316         NV50CrtcCommand(crtc, 0x82c, 0);
 317         /* This confirms my suspicion that recent nvidia hardware does no vertical programming */
 318         /* NV40 still has it as a legacy mode, and i don't know how to do the "new" way, but it definately exists */
 319         NV50CrtcCommand(crtc, NV50_CRTC0_HBLANK_START, adjusted_mode->CrtcHBlankStart);
 320         NV50CrtcCommand(crtc, NV50_CRTC0_HSYNC_END, adjusted_mode->CrtcHSyncEnd);
 321         NV50CrtcCommand(crtc, NV50_CRTC0_HBLANK_END, adjusted_mode->CrtcHBlankEnd);
 322         NV50CrtcCommand(crtc, NV50_CRTC0_HTOTAL, adjusted_mode->CrtcHTotal);
 323         if(adjusted_mode->Flags & V_INTERLACE) {
 324                 NV50CrtcCommand(crtc, 0x824, adjusted_mode->CrtcHSkew);
 325         }
 326         NV50CrtcCommand(crtc, NV50_CRTC0_FB_SIZE, pScrn->virtualY << 16 | pScrn->virtualX);
 327         NV50CrtcCommand(crtc, NV50_CRTC0_PITCH, pScrn->displayWidth * (pScrn->bitsPerPixel / 8) | 0x100000);
 328         switch(pScrn->depth) {
 329                 case 8:
 330                         NV50CrtcCommand(crtc, NV50_CRTC0_DEPTH, NV50_CRTC0_DEPTH_8BPP);
 331                         break;
 332                 case 15:
 333                         NV50CrtcCommand(crtc, NV50_CRTC0_DEPTH, NV50_CRTC0_DEPTH_15BPP);
 334                         break;
 335                 case 16:
 336                         NV50CrtcCommand(crtc, NV50_CRTC0_DEPTH, NV50_CRTC0_DEPTH_16BPP);
 337                         break;
 338                 case 24:
 339                         NV50CrtcCommand(crtc, NV50_CRTC0_DEPTH, NV50_CRTC0_DEPTH_24BPP);
 340                         break;
 341         }
 342         NV50CrtcSetDither(crtc, nv_crtc->ditherEnabled, FALSE);
 343         NV50CrtcCommand(crtc, 0x8a8, 0x40000);
 344         NV50CrtcCommand(crtc, NV50_CRTC0_FB_POS, y << 16 | x);
 345         NV50CrtcCommand(crtc, NV50_CRTC0_SCRN_SIZE, VDisplay << 16 | HDisplay);
 346         NV50CrtcCommand(crtc, 0x8d4, 0);
 347
 348         NV50CrtcBlankScreen(crtc, FALSE);
 349 }
 350
 351 void
 352 NV50CrtcBlankScreen(xf86CrtcPtr crtc, Bool blank)
 353 {
 354         ScrnInfoPtr pScrn = crtc->scrn;
 355         NVPtr pNv = NVPTR(pScrn);
 356         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 357
 358         if(blank) {
 359                 NV50CrtcShowHideCursor(crtc, FALSE, FALSE);
 360
 361                 NV50CrtcCommand(crtc, NV50_CRTC0_CLUT_MODE, NV50_CRTC0_CLUT_MODE_BLANK);
 362                 NV50CrtcCommand(crtc, NV50_CRTC0_CLUT_OFFSET, 0);
 363                 if(pNv->NVArch != 0x50)
 364                         NV50CrtcCommand(crtc, 0x85c, 0);
 365                 NV50CrtcCommand(crtc, 0x874, 0);
 366                 if(pNv->NVArch != 0x50)
 367                         NV50CrtcCommand(crtc, 0x89c, 0);
 368         } else {
 369                 NV50CrtcCommand(crtc, NV50_CRTC0_FB_OFFSET, pNv->FB->offset >> 8);
 370                 NV50CrtcCommand(crtc, 0x864, 0);
 371                 NVWrite(pNv, 0x00610380, 0);
 372                 /* RAM is clamped to 256 MiB. */
 373                 NVWrite(pNv, NV50_CRTC0_RAM_AMOUNT, pNv->RamAmountKBytes * 1024 - 1);
 374                 NVWrite(pNv, 0x00610388, 0x150000);
 375                 NVWrite(pNv, 0x0061038C, 0);
 376                 NV50CrtcCommand(crtc, NV50_CRTC0_CURSOR_OFFSET, pNv->Cursor->offset >> 8);
 377                 if(pNv->NVArch != 0x50)
 378                         NV50CrtcCommand(crtc, 0x89c, 1);
 379                 if(nv_crtc->cursorVisible)
 380                         NV50CrtcShowHideCursor(crtc, TRUE, FALSE);
 381                 NV50CrtcCommand(crtc, NV50_CRTC0_CLUT_MODE,
 382                         pScrn->depth == 8 ? NV50_CRTC0_CLUT_MODE_OFF : NV50_CRTC0_CLUT_MODE_ON);
 383                 NV50CrtcCommand(crtc, NV50_CRTC0_CLUT_OFFSET, pNv->CLUT->offset >> 8);
 384                 if(pNv->NVArch != 0x50)
 385                         NV50CrtcCommand(crtc, 0x85c, 1);
 386                 NV50CrtcCommand(crtc, 0x874, 1);
 387      }
 388 }
 389
 390 /******************************** Cursor stuff ********************************/
 391 static void NV50CrtcShowHideCursor(xf86CrtcPtr crtc, Bool show, Bool update)
 392 {
 393         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 394
 395         NV50CrtcCommand(crtc, NV50_CRTC0_CURSOR0,
 396                 show ? NV50_CRTC0_CURSOR0_SHOW : NV50_CRTC0_CURSOR0_HIDE);
 397         if(update) {
 398                 nv_crtc->cursorVisible = show;
 399                 NV50CrtcCommand(crtc, 0x80, 0);
 400         }
 401 }
 402
 403 void NV50CrtcShowCursor(xf86CrtcPtr crtc)
 404 {
 405         NV50CrtcShowHideCursor(crtc, TRUE, TRUE);
 406 }
 407
 408 void NV50CrtcHideCursor(xf86CrtcPtr crtc)
 409 {
 410         NV50CrtcShowHideCursor(crtc, FALSE, TRUE);
 411 }
 412
 413 /******************************** CRTC stuff ********************************/
 414
 415 void
 416 NV50CrtcPrepare(xf86CrtcPtr crtc)
 417 {
 418         ScrnInfoPtr pScrn = crtc->scrn;
 419         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 420         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 421         int i;
 422
 423         for(i = 0; i < xf86_config->num_output; i++) {
 424                 xf86OutputPtr output = xf86_config->output[i];
 425
 426                 if(!output->crtc)
 427                         output->funcs->mode_set(output, NULL, NULL);
 428         }
 429
 430         nv_crtc->skipModeFixup = FALSE;
 431 }
 432
 433 void
 434 NV50CrtcSkipModeFixup(xf86CrtcPtr crtc)
 435 {
 436         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 437         nv_crtc->skipModeFixup = TRUE;
 438 }
 439
 440 void
 441 NV50CrtcSetDither(xf86CrtcPtr crtc, Bool dither, Bool update)
 442 {
 443         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 444
 445         nv_crtc->ditherEnabled = dither;
 446
 447         NV50CrtcCommand(crtc, 0x8a0, dither ? 0x11 : 0);
 448         if(update)
 449                 NV50CrtcCommand(crtc, 0x80, 0);
 450 }
 451
 452 static void ComputeAspectScale(DisplayModePtr mode, int *outX, int *outY)
 453 {
 454         float scaleX, scaleY, scale;
 455
 456         scaleX = mode->CrtcHDisplay / (float)mode->HDisplay;
 457         scaleY = mode->CrtcVDisplay / (float)mode->VDisplay;
 458
 459         if(scaleX > scaleY)
 460                 scale = scaleY;
 461         else
 462                 scale = scaleX;
 463
 464         *outX = mode->HDisplay * scale;
 465         *outY = mode->VDisplay * scale;
 466 }
 467
 468 void NV50CrtcSetScale(xf86CrtcPtr crtc, DisplayModePtr mode, enum NV50ScaleMode scale)
 469 {
 470         int outX = 0, outY = 0;
 471
 472         switch(scale) {
 473                 case NV50_SCALE_ASPECT:
 474                         ComputeAspectScale(mode, &outX, &outY);
 475                         break;
 476                 case NV50_SCALE_OFF:
 477                 case NV50_SCALE_FILL:
 478                         outX = mode->CrtcHDisplay;
 479                         outY = mode->CrtcVDisplay;
 480                         break;
 481                 case NV50_SCALE_CENTER:
 482                         outX = mode->HDisplay;
 483                         outY = mode->VDisplay;
 484                         break;
 485         }
 486
 487         if ((mode->Flags & V_DBLSCAN) || (mode->Flags & V_INTERLACE) ||
 488                 mode->HDisplay != outX || mode->VDisplay != outY) {
 489                 NV50CrtcCommand(crtc, 0x8a4, 9);
 490         } else {
 491                 NV50CrtcCommand(crtc, 0x8a4, 0);
 492         }
 493         NV50CrtcCommand(crtc, 0x8d8, outY << 16 | outX);
 494         NV50CrtcCommand(crtc, 0x8dc, outY << 16 | outX);
 495 }
 496
 497 void
 498 NV50CrtcCommit(xf86CrtcPtr crtc)
 499 {
 500         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(crtc->scrn);
 501         int i, crtc_mask = 0;
 502
 503         /* If any heads are unused, blank them */
 504         for(i = 0; i < xf86_config->num_output; i++) {
 505                 xf86OutputPtr output = xf86_config->output[i];
 506
 507                 if (output->crtc) {
 508                         /* XXXagp: This assumes that xf86_config->crtc[i] is HEADi */
 509                         crtc_mask |= 1 << NV50CrtcGetHead(output->crtc);
 510                 }
 511         }
 512
 513         for(i = 0; i < xf86_config->num_crtc; i++) {
 514                 if(!((1 << i) & crtc_mask)) {
 515                         NV50CrtcBlankScreen(xf86_config->crtc[i], TRUE);
 516                 }
 517         }
 518
 519         NV50CrtcCommand(crtc, 0x80, 0);
 520 }
 521