git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 2006 Dave Airlie
   3  * Copyright 2007 Maarten Maathuis
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
  26  * decleration is at the bottom of this file as it is rather ugly
  27  */
  28
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include <assert.h>
  34 #include "xf86.h"
  35 #include "os.h"
  36 #include "mibank.h"
  37 #include "globals.h"
  38 #include "xf86.h"
  39 #include "xf86Priv.h"
  40 #include "xf86DDC.h"
  41 #include "mipointer.h"
  42 #include "windowstr.h"
  43 #include <randrstr.h>
  44 #include <X11/extensions/render.h>
  45
  46 #include "xf86Crtc.h"
  47 #include "nv_include.h"
  48
  49 #include "vgaHW.h"
  50
  51 #define CRTC_INDEX 0x3d4
  52 #define CRTC_DATA 0x3d5
  53 #define CRTC_IN_STAT_1 0x3da
  54
  55 #define WHITE_VALUE 0x3F
  56 #define BLACK_VALUE 0x00
  57 #define OVERSCAN_VALUE 0x01
  58
  59 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  60 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override);
  61 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  62 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  63 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  64 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  65
  66 uint32_t NVReadCRTC(NVPtr pNv, uint8_t head, uint32_t reg)
  67 {
  68         volatile const void *ptr = head ? pNv->PCRTC1 : pNv->PCRTC0;
  69         DDXMMIOH("NVReadCRTC: head %d reg %08x val %08x\n", head, reg + NV_PCRTC0_OFFSET + (head ? NV_PCRTC0_SIZE : 0), (uint32_t)MMIO_IN32(ptr, reg));
  70         return MMIO_IN32(ptr, reg);
  71 }
  72
  73 void NVWriteCRTC(NVPtr pNv, uint8_t head, uint32_t reg, uint32_t val)
  74 {
  75         volatile const void *ptr = head ? pNv->PCRTC1 : pNv->PCRTC0;
  76         DDXMMIOH("NVWriteCRTC: head %d reg %08x val %08x\n", head, reg + NV_PCRTC0_OFFSET + (head ? NV_PCRTC0_SIZE : 0), val);
  77         MMIO_OUT32(ptr, reg, val);
  78 }
  79
  80 uint32_t NVCrtcReadCRTC(xf86CrtcPtr crtc, uint32_t reg)
  81 {
  82         ScrnInfoPtr pScrn = crtc->scrn;
  83         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  84         NVPtr pNv = NVPTR(pScrn);
  85
  86         return NVReadCRTC(pNv, nv_crtc->head, reg);
  87 }
  88
  89 void NVCrtcWriteCRTC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
  90 {
  91         ScrnInfoPtr pScrn = crtc->scrn;
  92         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  93         NVPtr pNv = NVPTR(pScrn);
  94
  95         NVWriteCRTC(pNv, nv_crtc->head, reg, val);
  96 }
  97
  98 uint32_t NVReadRAMDAC(NVPtr pNv, uint8_t head, uint32_t reg)
  99 {
 100         volatile const void *ptr = head ? pNv->PRAMDAC1 : pNv->PRAMDAC0;
 101         DDXMMIOH("NVReadRamdac: head %d reg %08x val %08x\n", head, reg + NV_PRAMDAC0_OFFSET + (head ? NV_PRAMDAC0_SIZE : 0), (uint32_t)MMIO_IN32(ptr, reg));
 102         return MMIO_IN32(ptr, reg);
 103 }
 104
 105 void NVWriteRAMDAC(NVPtr pNv, uint8_t head, uint32_t reg, uint32_t val)
 106 {
 107         volatile const void *ptr = head ? pNv->PRAMDAC1 : pNv->PRAMDAC0;
 108         DDXMMIOH("NVWriteRamdac: head %d reg %08x val %08x\n", head, reg + NV_PRAMDAC0_OFFSET + (head ? NV_PRAMDAC0_SIZE : 0), val);
 109         MMIO_OUT32(ptr, reg, val);
 110 }
 111
 112 uint32_t NVCrtcReadRAMDAC(xf86CrtcPtr crtc, uint32_t reg)
 113 {
 114         ScrnInfoPtr pScrn = crtc->scrn;
 115         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 116         NVPtr pNv = NVPTR(pScrn);
 117
 118         return NVReadRAMDAC(pNv, nv_crtc->head, reg);
 119 }
 120
 121 void NVCrtcWriteRAMDAC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
 122 {
 123         ScrnInfoPtr pScrn = crtc->scrn;
 124         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 125         NVPtr pNv = NVPTR(pScrn);
 126
 127         NVWriteRAMDAC(pNv, nv_crtc->head, reg, val);
 128 }
 129
 130 static uint8_t NVReadPVIO(xf86CrtcPtr crtc, uint32_t address)
 131 {
 132         ScrnInfoPtr pScrn = crtc->scrn;
 133         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 134         NVPtr pNv = NVPTR(pScrn);
 135
 136         /* Only NV4x have two pvio ranges */
 137         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
 138                 DDXMMIOH("NVReadPVIO: head %d reg %08x val %02x\n", 1, address + NV_PVIO_OFFSET + NV_PVIO_SIZE, NV_RD08(pNv->PVIO1, address));
 139                 return NV_RD08(pNv->PVIO1, address);
 140         } else {
 141                 DDXMMIOH("NVReadPVIO: head %d reg %08x val %02x\n", 0, address + NV_PVIO_OFFSET, NV_RD08(pNv->PVIO0, address));
 142                 return NV_RD08(pNv->PVIO0, address);
 143         }
 144 }
 145
 146 static void NVWritePVIO(xf86CrtcPtr crtc, uint32_t address, uint8_t value)
 147 {
 148         ScrnInfoPtr pScrn = crtc->scrn;
 149         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 150         NVPtr pNv = NVPTR(pScrn);
 151
 152         DDXMMIOH("NVWritePVIO: head %d reg %08x val %02x\n", nv_crtc->head, address + NV_PVIO_OFFSET + (nv_crtc->head ? NV_PVIO_SIZE : 0), value);
 153         /* Only NV4x have two pvio ranges */
 154         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
 155                 NV_WR08(pNv->PVIO1, address, value);
 156         } else {
 157                 NV_WR08(pNv->PVIO0, address, value);
 158         }
 159 }
 160
 161 static void NVWriteMiscOut(xf86CrtcPtr crtc, uint8_t value)
 162 {
 163         NVWritePVIO(crtc, VGA_MISC_OUT_W, value);
 164 }
 165
 166 static uint8_t NVReadMiscOut(xf86CrtcPtr crtc)
 167 {
 168         return NVReadPVIO(crtc, VGA_MISC_OUT_R);
 169 }
 170
 171 void NVWriteVGA(NVPtr pNv, int head, uint8_t index, uint8_t value)
 172 {
 173         volatile uint8_t *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 174
 175         DDXMMIOH("NVWriteVGA: head %d index 0x%02x data 0x%02x\n", head, index, value);
 176         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 177         NV_WR08(pCRTCReg, CRTC_DATA, value);
 178 }
 179
 180 uint8_t NVReadVGA(NVPtr pNv, int head, uint8_t index)
 181 {
 182         volatile uint8_t *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 183
 184         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 185         DDXMMIOH("NVReadVGA: head %d index 0x%02x data 0x%02x\n", head, index, NV_RD08(pCRTCReg, CRTC_DATA));
 186         return NV_RD08(pCRTCReg, CRTC_DATA);
 187 }
 188
 189 /* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
 190  * I suspect they in fact do nothing, but are merely a way to carry useful
 191  * per-head variables around
 192  *
 193  * Known uses:
 194  * CR57         CR58
 195  * 0x00         index to the appropriate dcb entry (or 7f for inactive)
 196  * 0x02         dcb entry's "or" value (or 00 for inactive)
 197  * 0x03         bit0 set for dual link (LVDS, possibly elsewhere too)
 198  * 0x08 or 0x09 pxclk in MHz
 199  * 0x0f         laptop panel info -     low nibble for PEXTDEV_BOOT strap
 200  *                                      high nibble for xlat strap value
 201  */
 202
 203 void NVWriteVGACR5758(NVPtr pNv, int head, uint8_t index, uint8_t value)
 204 {
 205         NVWriteVGA(pNv, head, 0x57, index);
 206         NVWriteVGA(pNv, head, 0x58, value);
 207 }
 208
 209 uint8_t NVReadVGACR5758(NVPtr pNv, int head, uint8_t index)
 210 {
 211         NVWriteVGA(pNv, head, 0x57, index);
 212         return NVReadVGA(pNv, head, 0x58);
 213 }
 214
 215 void NVWriteVgaCrtc(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 216 {
 217         ScrnInfoPtr pScrn = crtc->scrn;
 218         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 219         NVPtr pNv = NVPTR(pScrn);
 220
 221         NVWriteVGA(pNv, nv_crtc->head, index, value);
 222 }
 223
 224 uint8_t NVReadVgaCrtc(xf86CrtcPtr crtc, uint8_t index)
 225 {
 226         ScrnInfoPtr pScrn = crtc->scrn;
 227         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 228         NVPtr pNv = NVPTR(pScrn);
 229
 230         return NVReadVGA(pNv, nv_crtc->head, index);
 231 }
 232
 233 static void NVWriteVgaSeq(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 234 {
 235         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 236         NVWritePVIO(crtc, VGA_SEQ_DATA, value);
 237 }
 238
 239 static uint8_t NVReadVgaSeq(xf86CrtcPtr crtc, uint8_t index)
 240 {
 241         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 242         return NVReadPVIO(crtc, VGA_SEQ_DATA);
 243 }
 244
 245 static void NVWriteVgaGr(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 246 {
 247         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 248         NVWritePVIO(crtc, VGA_GRAPH_DATA, value);
 249 }
 250
 251 static uint8_t NVReadVgaGr(xf86CrtcPtr crtc, uint8_t index)
 252 {
 253         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 254         return NVReadPVIO(crtc, VGA_GRAPH_DATA);
 255 }
 256
 257
 258 static void NVWriteVgaAttr(xf86CrtcPtr crtc, uint8_t index, uint8_t value)
 259 {
 260         ScrnInfoPtr pScrn = crtc->scrn;
 261         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 262         NVPtr pNv = NVPTR(pScrn);
 263         volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 264
 265         DDXMMIOH("NVWriteVgaAttr: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, CRTC_IN_STAT_1, NV_RD08(pCRTCReg, CRTC_IN_STAT_1));
 266         NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 267         if (nv_crtc->paletteEnabled)
 268                 index &= ~0x20;
 269         else
 270                 index |= 0x20;
 271
 272         DDXMMIOH("NVWriteVgaAttr: head %d index 0x%02x data 0x%02x\n", nv_crtc->head, index, value);
 273         NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 274         NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
 275 }
 276
 277 static uint8_t NVReadVgaAttr(xf86CrtcPtr crtc, uint8_t index)
 278 {
 279         ScrnInfoPtr pScrn = crtc->scrn;
 280         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 281         NVPtr pNv = NVPTR(pScrn);
 282         volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 283
 284         DDXMMIOH("NVReadVgaAttr: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, CRTC_IN_STAT_1, NV_RD08(pCRTCReg, CRTC_IN_STAT_1));
 285         NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 286         if (nv_crtc->paletteEnabled)
 287                 index &= ~0x20;
 288         else
 289                 index |= 0x20;
 290
 291         NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 292         DDXMMIOH("NVReadVgaAttr: head %d index 0x%02x data 0x%02x\n", nv_crtc->head, index, NV_RD08(pCRTCReg, VGA_ATTR_DATA_R));
 293         return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
 294 }
 295
 296 static void NVCrtcSetOwner(xf86CrtcPtr crtc)
 297 {
 298         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 299         ScrnInfoPtr pScrn = crtc->scrn;
 300         NVPtr pNv = NVPTR(pScrn);
 301         /* Non standard beheaviour required by NV11 */
 302         if (pNv) {
 303                 uint8_t owner = NVReadVGA(pNv, 0, NV_VGA_CRTCX_OWNER);
 304                 ErrorF("pre-Owner: 0x%X\n", owner);
 305                 if (owner == 0x04) {
 306                         uint32_t pbus84 = nvReadMC(pNv, 0x1084);
 307                         ErrorF("pbus84: 0x%X\n", pbus84);
 308                         pbus84 &= ~(1<<28);
 309                         ErrorF("pbus84: 0x%X\n", pbus84);
 310                         nvWriteMC(pNv, 0x1084, pbus84);
 311                 }
 312                 /* The blob never writes owner to pcio1, so should we */
 313                 if (pNv->NVArch == 0x11) {
 314                         NVWriteVGA(pNv, 0, NV_VGA_CRTCX_OWNER, 0xff);
 315                 }
 316                 NVWriteVGA(pNv, 0, NV_VGA_CRTCX_OWNER, nv_crtc->head * 0x3);
 317                 owner = NVReadVGA(pNv, 0, NV_VGA_CRTCX_OWNER);
 318                 ErrorF("post-Owner: 0x%X\n", owner);
 319         } else {
 320                 ErrorF("pNv pointer is NULL\n");
 321         }
 322 }
 323
 324 static void
 325 NVEnablePalette(xf86CrtcPtr crtc)
 326 {
 327         ScrnInfoPtr pScrn = crtc->scrn;
 328         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 329         NVPtr pNv = NVPTR(pScrn);
 330         volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 331
 332         DDXMMIOH("NVEnablePalette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, CRTC_IN_STAT_1, NV_RD08(pCRTCReg, CRTC_IN_STAT_1));
 333         NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 334         DDXMMIOH("NVEnablePalette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_ATTR_INDEX, 0);
 335         NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
 336         nv_crtc->paletteEnabled = TRUE;
 337 }
 338
 339 static void
 340 NVDisablePalette(xf86CrtcPtr crtc)
 341 {
 342         ScrnInfoPtr pScrn = crtc->scrn;
 343         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 344         NVPtr pNv = NVPTR(pScrn);
 345         volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 346
 347         DDXMMIOH("NVDisablePalette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, CRTC_IN_STAT_1, NV_RD08(pCRTCReg, CRTC_IN_STAT_1));
 348         NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 349         DDXMMIOH("NVEnablePalette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_ATTR_INDEX, 0x20);
 350         NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
 351         nv_crtc->paletteEnabled = FALSE;
 352 }
 353
 354 static void NVWriteVgaReg(xf86CrtcPtr crtc, uint32_t reg, uint8_t value)
 355 {
 356         ScrnInfoPtr pScrn = crtc->scrn;
 357         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 358         NVPtr pNv = NVPTR(pScrn);
 359         volatile uint8_t *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 360
 361         DDXMMIOH("NVWriteVgaReg: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, reg, value);
 362         NV_WR08(pCRTCReg, reg, value);
 363 }
 364
 365 /* perform a sequencer reset */
 366 static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
 367 {
 368   if (start)
 369     NVWriteVgaSeq(crtc, 0x00, 0x1);
 370   else
 371     NVWriteVgaSeq(crtc, 0x00, 0x3);
 372
 373 }
 374 static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
 375 {
 376         uint8_t tmp;
 377
 378         if (on) {
 379                 tmp = NVReadVgaSeq(crtc, 0x1);
 380                 NVVgaSeqReset(crtc, TRUE);
 381                 NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
 382
 383                 NVEnablePalette(crtc);
 384         } else {
 385                 /*
 386                  * Reenable sequencer, then turn on screen.
 387                  */
 388                 tmp = NVReadVgaSeq(crtc, 0x1);
 389                 NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20); /* reenable display */
 390                 NVVgaSeqReset(crtc, FALSE);
 391
 392                 NVDisablePalette(crtc);
 393         }
 394 }
 395
 396 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool Lock)
 397 {
 398         NVPtr pNv = NVPTR(crtc->scrn);
 399         uint8_t cr11;
 400
 401         if (pNv->twoHeads)
 402                 NVCrtcSetOwner(crtc);
 403
 404         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57);
 405         cr11 = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE);
 406         if (Lock) cr11 |= 0x80;
 407         else cr11 &= ~0x80;
 408         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE, cr11);
 409 }
 410
 411 xf86OutputPtr
 412 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
 413 {
 414         ScrnInfoPtr pScrn = crtc->scrn;
 415         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 416         int i;
 417         for (i = 0; i < xf86_config->num_output; i++) {
 418                 xf86OutputPtr output = xf86_config->output[i];
 419
 420                 if (output->crtc == crtc) {
 421                         return output;
 422                 }
 423         }
 424
 425         return NULL;
 426 }
 427
 428 xf86CrtcPtr
 429 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
 430 {
 431         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 432         int i;
 433
 434         for (i = 0; i < xf86_config->num_crtc; i++) {
 435                 xf86CrtcPtr crtc = xf86_config->crtc[i];
 436                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 437                 if (nv_crtc->head == index)
 438                         return crtc;
 439         }
 440
 441         return NULL;
 442 }
 443
 444 /*
 445  * Calculate the Video Clock parameters for the PLL.
 446  */
 447 /* Code taken from NVClock, with permission of the author (being a GPL->MIT code transfer). */
 448
 449 static void
 450 CalculateVClkNV4x_SingleVCO(NVPtr pNv, struct pll_lims *pll_lim, uint32_t clockIn, uint32_t *n1_best, uint32_t *m1_best, uint32_t *p_best)
 451 {
 452         uint32_t clock, M, N, P;
 453         uint32_t delta, bestDelta, minM, maxM, minN, maxN, maxP;
 454         uint32_t minVCOInputFreq, minVCOFreq, maxVCOFreq;
 455         uint32_t VCOFreq;
 456         uint32_t refClk = pNv->CrystalFreqKHz;
 457         bestDelta = clockIn;
 458
 459         minVCOInputFreq = pll_lim->vco1.min_inputfreq;
 460         minVCOFreq = pll_lim->vco1.minfreq;
 461         maxVCOFreq = pll_lim->vco1.maxfreq;
 462         minM = pll_lim->vco1.min_m;
 463         maxM = pll_lim->vco1.max_m;
 464         minN = pll_lim->vco1.min_n;
 465         maxN = pll_lim->vco1.max_n;
 466
 467         maxP = 6;
 468
 469         /* The optimal frequency for the PLL to work at is somewhere in the center of its range.
 470         /  Choose a post divider in such a way to achieve this.
 471         /  The G8x nv driver does something similar but they they derive a minP and maxP. That
 472         /  doesn't seem required as you get so many matching clocks that you don't enter a second
 473         /  iteration for P. (The minP / maxP values in the nv driver only differ at most 1, so it is for
 474         /  some rare corner cases.
 475         */
 476         for (P=0, VCOFreq=maxVCOFreq/2; clockIn<=VCOFreq && P <= maxP; P++)
 477         {
 478                 VCOFreq /= 2;
 479         }
 480
 481         /* Calculate the m and n values. There are a lot of values which give the same speed;
 482         /  We choose the speed for which the difference with the request speed is as small as possible.
 483         */
 484         for (M=minM; M<=maxM; M++)
 485         {
 486                 /* The VCO has a minimum input frequency */
 487                 if ((refClk/M) < minVCOInputFreq)
 488                         break;
 489
 490                 for (N=minN; N<=maxN; N++)
 491                 {
 492                         /* Calculate the frequency generated by VCO1 */
 493                         clock = (int)(refClk * N / (float)M);
 494
 495                         /* Verify if the clock lies within the output limits of VCO1 */
 496                         if (clock < minVCOFreq)
 497                                 continue;
 498                         else if (clock > maxVCOFreq) /* It is no use to continue as the clock will only become higher */
 499                                 break;
 500
 501                         clock >>= P;
 502                         delta = abs((int)(clockIn - clock));
 503                         /* When the difference is 0 or less than .5% accept the speed */
 504                         if (((delta == 0) || ((float)delta/(float)clockIn <= 0.005)))
 505                         {
 506                                 *m1_best = M;
 507                                 *n1_best = N;
 508                                 *p_best = P;
 509                                 return;
 510                         }
 511
 512                         /* When the new difference is smaller than the old one, use this one */
 513                         if (delta < bestDelta)
 514                         {
 515                                 bestDelta = delta;
 516                                 *m1_best = M;
 517                                 *n1_best = N;
 518                                 *p_best = P;
 519                         }
 520                 }
 521         }
 522 }
 523
 524 static void
 525 CalculateVClkNV4x_DoubleVCO(NVPtr pNv, struct pll_lims *pll_lim, uint32_t clockIn, uint32_t *n1_best, uint32_t *n2_best, uint32_t *m1_best, uint32_t *m2_best, uint32_t *p_best)
 526 {
 527         uint32_t clock1, clock2, M, M2, N, N2, P;
 528         uint32_t delta, bestDelta, minM, minM2, maxM, maxM2, minN, minN2, maxN, maxN2, maxP;
 529         uint32_t minVCOInputFreq, minVCO2InputFreq, maxVCO2InputFreq, minVCOFreq, minVCO2Freq, maxVCOFreq, maxVCO2Freq;
 530         uint32_t VCO2Freq, maxClock;
 531         uint32_t refClk = pNv->CrystalFreqKHz;
 532         bestDelta = clockIn;
 533
 534         minVCOInputFreq = pll_lim->vco1.min_inputfreq;
 535         minVCOFreq = pll_lim->vco1.minfreq;
 536         maxVCOFreq = pll_lim->vco1.maxfreq;
 537         minM = pll_lim->vco1.min_m;
 538         maxM = pll_lim->vco1.max_m;
 539         minN = pll_lim->vco1.min_n;
 540         maxN = pll_lim->vco1.max_n;
 541
 542         minVCO2InputFreq = pll_lim->vco2.min_inputfreq;
 543         maxVCO2InputFreq = pll_lim->vco2.max_inputfreq;
 544         minVCO2Freq = pll_lim->vco2.minfreq;
 545         maxVCO2Freq = pll_lim->vco2.maxfreq;
 546         minM2 = pll_lim->vco2.min_m;
 547         maxM2 = pll_lim->vco2.max_m;
 548         minN2 = pll_lim->vco2.min_n;
 549         maxN2 = pll_lim->vco2.max_n;
 550
 551         maxP = 6;
 552
 553         maxClock = maxVCO2Freq;
 554         /* If the requested clock is behind the bios limits, try it anyway */
 555         if (clockIn > maxVCO2Freq)
 556                 maxClock = clockIn + clockIn/200; /* Add a .5% margin */
 557
 558         /* The optimal frequency for the PLL to work at is somewhere in the center of its range.
 559         /  Choose a post divider in such a way to achieve this.
 560         /  The G8x nv driver does something similar but they they derive a minP and maxP. That
 561         /  doesn't seem required as you get so many matching clocks that you don't enter a second
 562         /  iteration for P. (The minP / maxP values in the nv driver only differ at most 1, so it is for
 563         /  some rare corner cases.
 564         */
 565         for (P=0, VCO2Freq=maxClock/2; clockIn<=VCO2Freq && P <= maxP; P++)
 566         {
 567                 VCO2Freq /= 2;
 568         }
 569
 570         /* The PLLs on Geforce6/7 hardware can operate in a single stage made with only 1 VCO
 571         /  and a cascade mode of two VCOs. This second mode is in general used for relatively high
 572         /  frequencies. The loop below calculates the divider and multiplier ratios for the cascade
 573         /  mode. The code takes into account limits defined in the video bios.
 574         */
 575         for (M=minM; M<=maxM; M++)
 576         {
 577                 /* The VCO has a minimum input frequency */
 578                 if ((refClk/M) < minVCOInputFreq)
 579                         break;
 580
 581                 for (N=minN; N<=maxN; N++)
 582                 {
 583                         /* Calculate the frequency generated by VCO1 */
 584                         clock1 = (int)(refClk * N / (float)M);
 585                         /* Verify if the clock lies within the output limits of VCO1 */
 586                         if ( (clock1 < minVCOFreq) )
 587                                 continue;
 588                         else if (clock1 > maxVCOFreq) /* For future N, the clock will only increase so stop; xorg nv continues but that is useless */
 589                                 break;
 590
 591                         for (M2=minM2; M2<=maxM2; M2++)
 592                         {
 593                                 /* The clock fed to the second VCO needs to lie within a certain input range */
 594                                 if (clock1 / M2 < minVCO2InputFreq)
 595                                         break;
 596                                 else if (clock1 / M2 > maxVCO2InputFreq)
 597                                         continue;
 598
 599                                 N2 = (int)((float)((clockIn << P) * M * M2) / (float)(refClk * N)+.5);
 600                                 if( (N2 < minN2) || (N2 > maxN2) )
 601                                         continue;
 602
 603                                 /* The clock before being fed to the post-divider needs to lie within a certain range.
 604                                 /  Further there are some limits on N2/M2.
 605                                 */
 606                                 clock2 = (int)((float)(N*N2)/(M*M2) * refClk);
 607                                 if( (clock2 < minVCO2Freq) || (clock2 > maxClock))// || ((N2 / M2) < 4) || ((N2 / M2) > 10) )
 608                                         continue;
 609
 610                                 /* The post-divider delays the 'high' clock to create a low clock if requested.
 611                                 /  This post-divider exists because the VCOs can only generate frequencies within
 612                                 /  a limited frequency range. This range has been tuned to lie around half of its max
 613                                 /  input frequency. It tries to calculate all clocks (including lower ones) around this
 614                                 /  'center' frequency.
 615                                 */
 616                                 clock2 >>= P;
 617                                 delta = abs((int)(clockIn - clock2));
 618
 619                                 /* When the difference is 0 or less than .5% accept the speed */
 620                                 if (((delta == 0) || ((float)delta/(float)clockIn <= 0.005)))
 621                                 {
 622                                         *m1_best = M;
 623                                         *m2_best = M2;
 624                                         *n1_best = N;
 625                                         *n2_best = N2;
 626                                         *p_best = P;
 627                                         return;
 628                                 }
 629
 630                                 /* When the new difference is smaller than the old one, use this one */
 631                                 if (delta < bestDelta)
 632                                 {
 633                                         bestDelta = delta;
 634                                         *m1_best = M;
 635                                         *m2_best = M2;
 636                                         *n1_best = N;
 637                                         *n2_best = N2;
 638                                         *p_best = P;
 639                                 }
 640                         }
 641                 }
 642         }
 643 }
 644
 645 /* BIG NOTE: modifying vpll1 and vpll2 does not work, what bit is the switch to allow it? */
 646
 647 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
 648 /* They are only valid for NV4x, appearantly reordered for NV5x */
 649 /* gpu pll: 0x4000 + 0x4004
 650  * unknown pll: 0x4008 + 0x400c
 651  * vpll1: 0x4010 + 0x4014
 652  * vpll2: 0x4018 + 0x401c
 653  * unknown pll: 0x4020 + 0x4024
 654  * unknown pll: 0x4038 + 0x403c
 655  * Some of the unknown's are probably memory pll's.
 656  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
 657  * 1 and 2 refer to the registers of each pair. There is only one post divider.
 658  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
 659  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
 660  *     bit8: A switch that turns of the second divider and multiplier off.
 661  *     bit12: Also a switch, i haven't seen it yet.
 662  *     bit16-19: p-divider
 663  *     but 28-31: Something related to the mode that is used (see bit8).
 664  * 2) bit0-7: m-divider (a)
 665  *     bit8-15: n-multiplier (a)
 666  *     bit16-23: m-divider (b)
 667  *     bit24-31: n-multiplier (b)
 668  */
 669
 670 /* Modifying the gpu pll for example requires:
 671  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 672  * This is not needed for the vpll's which have their own bits.
 673  */
 674
 675 static void
 676 CalculateVClkNV4x(
 677         ScrnInfoPtr pScrn,
 678         uint32_t requested_clock,
 679         uint32_t *given_clock,
 680         uint32_t *pll_a,
 681         uint32_t *pll_b,
 682         uint32_t *reg580,
 683         Bool    *db1_ratio,
 684         Bool primary
 685 )
 686 {
 687         NVPtr pNv = NVPTR(pScrn);
 688         uint32_t pll_lim_reg;
 689         struct pll_lims pll_lim;
 690         /* We have 2 mulitpliers, 2 dividers and one post divider */
 691         /* Note that p is only 3 bits */
 692         int NM1 = 0xbeef, NM2 = 0xdead, log2P = 0;
 693         uint32_t special_bits = 0;
 694
 695         if (primary) {
 696                 if (!get_pll_limits_reg(pScrn, VPLL1, &pll_lim_reg))
 697                         return;
 698         } else
 699                 if (!get_pll_limits_reg(pScrn, VPLL2, &pll_lim_reg))
 700                         return;
 701
 702         get_pll_limits(pScrn, pll_lim_reg, &pll_lim);
 703
 704         if (requested_clock < pll_lim.vco1.maxfreq && pNv->NVArch > 0x40) { /* single VCO */
 705                 *db1_ratio = TRUE;
 706                 /* Turn the second set of divider and multiplier off */
 707                 /* Bogus data, the same nvidia uses */
 708                 NM2 = 0x11f;
 709                 *given_clock = getMNP_single(pScrn, pll_lim_reg, requested_clock, &NM1, &log2P);
 710         } else { /* dual VCO */
 711                 *db1_ratio = FALSE;
 712                 *given_clock = getMNP_double(pScrn, pll_lim_reg, requested_clock, &NM1, &NM2, &log2P);
 713         }
 714
 715         /* Are this all (relevant) G70 cards? */
 716         if (pNv->NVArch == 0x4B || pNv->NVArch == 0x46 || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
 717                 /* This is a big guess, but should be reasonable until we can narrow it down. */
 718                 if (*db1_ratio) {
 719                         special_bits = 0x1;
 720                 } else {
 721                         special_bits = 0x3;
 722                 }
 723         }
 724
 725         /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
 726         *pll_a = (special_bits << 30) | (log2P << 16) | NM1;
 727         /* This VCO2 bit is an educated guess, but it needs to stay on for NV4x. */
 728         *pll_b = NV31_RAMDAC_ENABLE_VCO2 | NM2;
 729
 730         if (*db1_ratio) {
 731                 if (primary) {
 732                         *reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 733                 } else {
 734                         *reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 735                 }
 736         } else {
 737                 if (primary) {
 738                         *reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
 739                 } else {
 740                         *reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
 741                 }
 742         }
 743
 744         if (*db1_ratio) {
 745                 ErrorF("vpll: n1 %d m1 %d p %d db1_ratio %d\n", NM1 >> 8, NM1 & 0xff, log2P, *db1_ratio);
 746         } else {
 747                 ErrorF("vpll: n1 %d n2 %d m1 %d m2 %d p %d db1_ratio %d\n", NM1 >> 8, NM2 >> 8, NM1 & 0xff, NM2 & 0xff, log2P, *db1_ratio);
 748         }
 749 }
 750
 751 static void nv40_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 752 {
 753         state->vpll1_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL);
 754         state->vpll1_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B);
 755         state->vpll2_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2);
 756         state->vpll2_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B);
 757         state->pllsel = NVReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT);
 758         state->sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
 759         state->reg580 = NVReadRAMDAC(pNv, 0, NV_RAMDAC_580);
 760         state->reg594 = NVReadRAMDAC(pNv, 0, NV_RAMDAC_594);
 761 }
 762
 763 static void nv40_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 764 {
 765         ScrnInfoPtr pScrn = crtc->scrn;
 766         NVPtr pNv = NVPTR(pScrn);
 767         uint32_t fp_debug_0[2];
 768         uint32_t index[2];
 769         fp_debug_0[0] = NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
 770         fp_debug_0[1] = NVReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
 771
 772         /* The TMDS_PLL switch is on the actual ramdac */
 773         if (state->crosswired) {
 774                 index[0] = 1;
 775                 index[1] = 0;
 776                 ErrorF("Crosswired pll state load\n");
 777         } else {
 778                 index[0] = 0;
 779                 index[1] = 1;
 780         }
 781
 782         if (state->vpll2_b && state->vpll_changed[1]) {
 783                 NVWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0,
 784                         fp_debug_0[index[1]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 785
 786                 /* Wait for the situation to stabilise */
 787                 usleep(5000);
 788
 789                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 790                 /* for vpll2 change bits 18 and 19 are disabled */
 791                 reg_c040 &= ~(0x3 << 18);
 792                 nvWriteMC(pNv, 0xc040, reg_c040);
 793
 794                 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 795                 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 796
 797                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2, state->vpll2_a);
 798                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 799
 800                 ErrorF("writing pllsel %08X\n", state->pllsel);
 801                 /* Don't turn vpll1 off. */
 802                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
 803
 804                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_580, state->reg580);
 805                 ErrorF("writing reg580 %08X\n", state->reg580);
 806
 807                 /* We need to wait a while */
 808                 usleep(5000);
 809                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 810
 811                 NVWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[1]]);
 812
 813                 /* Wait for the situation to stabilise */
 814                 usleep(5000);
 815         }
 816
 817         if (state->vpll1_b && state->vpll_changed[0]) {
 818                 NVWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0,
 819                         fp_debug_0[index[0]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 820
 821                 /* Wait for the situation to stabilise */
 822                 usleep(5000);
 823
 824                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 825                 /* for vpll2 change bits 16 and 17 are disabled */
 826                 reg_c040 &= ~(0x3 << 16);
 827                 nvWriteMC(pNv, 0xc040, reg_c040);
 828
 829                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 830                 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 831
 832                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL, state->vpll1_a);
 833                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B, state->vpll1_b);
 834
 835                 ErrorF("writing pllsel %08X\n", state->pllsel);
 836                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
 837
 838                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_580, state->reg580);
 839                 ErrorF("writing reg580 %08X\n", state->reg580);
 840
 841                 /* We need to wait a while */
 842                 usleep(5000);
 843                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 844
 845                 NVWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[0]]);
 846
 847                 /* Wait for the situation to stabilise */
 848                 usleep(5000);
 849         }
 850
 851         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 852         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, state->sel_clk);
 853
 854         ErrorF("writing reg594 %08X\n", state->reg594);
 855         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_594, state->reg594);
 856
 857         /* All clocks have been set at this point. */
 858         state->vpll_changed[0] = FALSE;
 859         state->vpll_changed[1] = FALSE;
 860 }
 861
 862 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 863 {
 864         state->vpll1_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL);
 865         if (pNv->twoHeads) {
 866                 state->vpll2_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2);
 867         }
 868         if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 869                 state->vpll1_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B);
 870                 state->vpll2_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B);
 871         }
 872         state->pllsel = NVReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT);
 873         state->sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
 874 }
 875
 876
 877 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 878 {
 879         /* This sequence is important, the NV28 is very sensitive in this area. */
 880         /* Keep pllsel last and sel_clk first. */
 881         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 882         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, state->sel_clk);
 883
 884         if (state->vpll2_a && state->vpll_changed[1]) {
 885                 if (pNv->twoHeads) {
 886                         ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 887                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2, state->vpll2_a);
 888                 }
 889                 if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 890                         ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 891                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 892                 }
 893         }
 894
 895         if (state->vpll1_a && state->vpll_changed[0]) {
 896                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 897                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL, state->vpll1_a);
 898                 if (pNv->twoStagePLL && pNv->NVArch != 0x30) {
 899                         ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 900                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B, state->vpll1_b);
 901                 }
 902         }
 903
 904         ErrorF("writing pllsel %08X\n", state->pllsel);
 905         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
 906
 907         /* All clocks have been set at this point. */
 908         state->vpll_changed[0] = FALSE;
 909         state->vpll_changed[1] = FALSE;
 910 }
 911
 912 #define IS_NV44P (pNv->NVArch >= 0x44 ? 1 : 0)
 913 #define SEL_CLK_OFFSET (nv_get_sel_clk_offset(pNv->NVArch, nv_output->bus))
 914
 915 #define WIPE_OTHER_CLOCKS(_sel_clk, _head, _bus) (nv_wipe_other_clocks(_sel_clk, pNv->NVArch, _head, _bus))
 916
 917 /*
 918  * Calculate extended mode parameters (SVGA) and save in a
 919  * mode state structure.
 920  * State is not specific to a single crtc, but shared.
 921  */
 922 void nv_crtc_calc_state_ext(
 923         xf86CrtcPtr             crtc,
 924         DisplayModePtr  mode,
 925         int                             bpp,
 926         int                             DisplayWidth, /* Does this change after setting the mode? */
 927         int                             CrtcHDisplay,
 928         int                             CrtcVDisplay,
 929         int                             dotClock,
 930         int                             flags
 931 )
 932 {
 933         ScrnInfoPtr pScrn = crtc->scrn;
 934         uint32_t pixelDepth, VClk = 0;
 935         uint32_t CursorStart;
 936         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 937         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 938         NVCrtcRegPtr regp;
 939         NVPtr pNv = NVPTR(pScrn);
 940         RIVA_HW_STATE *state;
 941         int num_crtc_enabled, i;
 942         uint32_t old_clock_a = 0, old_clock_b = 0;
 943
 944         state = &pNv->ModeReg;
 945
 946         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 947
 948         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 949         NVOutputPrivatePtr nv_output = NULL;
 950         Bool is_fp = FALSE;
 951         if (output) {
 952                 nv_output = output->driver_private;
 953                 if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)
 954                         is_fp = TRUE;
 955         }
 956
 957         /* Store old clock. */
 958         if (nv_crtc->head == 1) {
 959                 old_clock_a = state->vpll2_a;
 960                 old_clock_b = state->vpll2_b;
 961         } else {
 962                 old_clock_a = state->vpll1_a;
 963                 old_clock_b = state->vpll1_b;
 964         }
 965
 966         /*
 967          * Extended RIVA registers.
 968          */
 969         /* This is pitch related, not mode related. */
 970         pixelDepth = (bpp + 1)/8;
 971         if (pNv->Architecture == NV_ARCH_40) {
 972                 /* Does register 0x580 already have a value? */
 973                 if (!state->reg580) {
 974                         state->reg580 = pNv->misc_info.ramdac_0_reg_580;
 975                 }
 976                 if (nv_crtc->head == 1) {
 977                         CalculateVClkNV4x(pScrn, dotClock, &VClk, &state->vpll2_a, &state->vpll2_b, &state->reg580, &state->db1_ratio[1], FALSE);
 978                 } else {
 979                         CalculateVClkNV4x(pScrn, dotClock, &VClk, &state->vpll1_a, &state->vpll1_b, &state->reg580, &state->db1_ratio[0], TRUE);
 980                 }
 981         } else if (pNv->twoStagePLL) {
 982                 int NM1, NM2, log2P;
 983                 VClk = getMNP_double(pScrn, 0, dotClock, &NM1, &NM2, &log2P);
 984                 if (pNv->NVArch == 0x30) {
 985                         /* See nvregisters.xml for details. */
 986                         state->pll = log2P << 16 | NM1 | (NM2 & 7) << 4 | ((NM2 >> 8) & 7) << 19 | ((NM2 >> 11) & 3) << 24 | NV30_RAMDAC_ENABLE_VCO2;
 987                 } else {
 988                         state->pll = log2P << 16 | NM1;
 989                         state->pllB = NV31_RAMDAC_ENABLE_VCO2 | NM2;
 990                 }
 991         } else {
 992                 int NM, log2P;
 993                 VClk = getMNP_single(pScrn, 0, dotClock, &NM, &log2P);
 994                 state->pll = log2P << 16 | NM;
 995         }
 996
 997         if (pNv->Architecture < NV_ARCH_40) {
 998                 if (nv_crtc->head == 1) {
 999                         state->vpll2_a = state->pll;
1000                         state->vpll2_b = state->pllB;
1001                 } else {
1002                         state->vpll1_a = state->pll;
1003                         state->vpll1_b = state->pllB;
1004                 }
1005         }
1006
1007         /* always reset vpll, just to be sure. */
1008         state->vpll_changed[nv_crtc->head] = TRUE;
1009
1010         switch (pNv->Architecture) {
1011         case NV_ARCH_04:
1012                 nv4UpdateArbitrationSettings(VClk,
1013                                                 pixelDepth * 8,
1014                                                 &(state->arbitration0),
1015                                                 &(state->arbitration1),
1016                                                 pNv);
1017                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
1018                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
1019                 if (flags & V_DBLSCAN)
1020                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
1021                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
1022                 state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
1023                 state->config = 0x00001114;
1024                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
1025                 break;
1026         case NV_ARCH_10:
1027         case NV_ARCH_20:
1028         case NV_ARCH_30:
1029         default:
1030                 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
1031                         ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
1032                         state->arbitration0 = 128;
1033                         state->arbitration1 = 0x0480;
1034                 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
1035                         ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
1036                         nForceUpdateArbitrationSettings(VClk,
1037                                                 pixelDepth * 8,
1038                                                 &(state->arbitration0),
1039                                                 &(state->arbitration1),
1040                                                 pNv);
1041                 } else if (pNv->Architecture < NV_ARCH_30) {
1042                         nv10UpdateArbitrationSettings(VClk,
1043                                                 pixelDepth * 8,
1044                                                 &(state->arbitration0),
1045                                                 &(state->arbitration1),
1046                                                 pNv);
1047                 } else {
1048                         nv30UpdateArbitrationSettings(pNv,
1049                                                 &(state->arbitration0),
1050                                                 &(state->arbitration1));
1051                 }
1052
1053                 if (nv_crtc->head == 1) {
1054                         CursorStart = pNv->Cursor2->offset;
1055                 } else {
1056                         CursorStart = pNv->Cursor->offset;
1057                 }
1058
1059                 if (!NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1060                         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
1061                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
1062                         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
1063                 } else {
1064                         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x0;
1065                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0x0;
1066                         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x0;
1067                 }
1068
1069                 if (flags & V_DBLSCAN)
1070                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
1071
1072                 state->config   = nvReadFB(pNv, NV_PFB_CFG0);
1073                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
1074                 break;
1075         }
1076
1077         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1078                 /* This is a bit of a guess. */
1079                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] |= 0xB8;
1080         }
1081
1082         /* okay do we have 2 CRTCs running ? */
1083         num_crtc_enabled = 0;
1084         for (i = 0; i < xf86_config->num_crtc; i++) {
1085                 if (xf86_config->crtc[i]->enabled) {
1086                         num_crtc_enabled++;
1087                 }
1088         }
1089
1090         ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
1091
1092         /* The main stuff seems to be valid for NV3x also. */
1093         if (pNv->Architecture >= NV_ARCH_30) {
1094                 /* This register is only used on the primary ramdac */
1095                 /* This seems to be needed to select the proper clocks, otherwise bad things happen */
1096
1097                 if (!state->sel_clk)
1098                         state->sel_clk = pNv->misc_info.sel_clk & ~(0xf << 16);
1099
1100                 if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
1101                         /* Only wipe when are a relevant (digital) output. */
1102                         state->sel_clk &= ~(0xf << 16);
1103                         Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1104                         /* Even with two dvi, this should not conflict. */
1105                         if (crossed_clocks) {
1106                                 state->sel_clk |= (0x1 << 16);
1107                         } else {
1108                                 state->sel_clk |= (0x4 << 16);
1109                         }
1110                 }
1111
1112                 /* Some cards, specifically dual dvi/lvds cards set another bitrange.
1113                  * I suspect inverse beheaviour to the normal bitrange, but i am not a 100% certain about this.
1114                  * This is all based on default settings found in mmio-traces.
1115                  * The blob never changes these, as it doesn't run unusual output configurations.
1116                  * It seems to prefer situations that avoid changing these bits (for a good reason?).
1117                  * I still don't know the purpose of value 2, it's similar to 4, but what exactly does it do?
1118                  */
1119
1120                 /* Some extra info:
1121                  * nv30:
1122                  *      bit 0           NVClk spread spectrum on/off
1123                  *      bit 2           MemClk spread spectrum on/off
1124                  *      bit 4           PixClk1 spread spectrum on/off
1125                  *      bit 6           PixClk2 spread spectrum on/off
1126
1127                  *      nv40:
1128                  *      what causes setting of bits not obvious but:
1129                  *      bits 4&5                relate to headA
1130                 *       bits 6&7                relate to headB
1131                 */
1132                 /* Only let digital outputs mess with this, otherwise strange output routings may mess it up. */
1133                 if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
1134                         if (pNv->Architecture == NV_ARCH_40) {
1135                                 for (i = 0; i < 4; i++) {
1136                                         uint32_t var = (state->sel_clk & (0xf << 4*i)) >> 4*i;
1137                                         if (var == 0x1 || var == 0x4) {
1138                                                 state->sel_clk &= ~(0xf << 4*i);
1139                                                 Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1140                                                 if (crossed_clocks) {
1141                                                         state->sel_clk |= (0x4 << 4*i);
1142                                                 } else {
1143                                                         state->sel_clk |= (0x1 << 4*i);
1144                                                 }
1145                                                 break; /* This should only occur once. */
1146                                         }
1147                                 }
1148                         /* Based on NV31M. */
1149                         } else if (pNv->Architecture == NV_ARCH_30) {
1150                                 for (i = 0; i < 4; i++) {
1151                                         uint32_t var = (state->sel_clk & (0xf << 4*i)) >> 4*i;
1152                                         if (var == 0x4 || var == 0x5) {
1153                                                 state->sel_clk &= ~(0xf << 4*i);
1154                                                 Bool crossed_clocks = nv_output->preferred_output ^ nv_crtc->head;
1155                                                 if (crossed_clocks) {
1156                                                         state->sel_clk |= (0x4 << 4*i);
1157                                                 } else {
1158                                                         state->sel_clk |= (0x5 << 4*i);
1159                                                 }
1160                                                 break; /* This should only occur once. */
1161                                         }
1162                                 }
1163                         }
1164                 }
1165         } else {
1166                 /* Don't change SEL_CLK on NV0x/NV1x/NV2x cards */
1167                 state->sel_clk = pNv->misc_info.sel_clk;
1168                 state->crosswired = FALSE;
1169         }
1170
1171         /* Are we crosswired? */
1172         if (output && nv_crtc->head != nv_output->preferred_output) {
1173                 state->crosswired = TRUE;
1174         } else {
1175                 state->crosswired = FALSE;
1176         }
1177
1178         if (nv_crtc->head == 1) {
1179                 if (state->db1_ratio[1])
1180                         ErrorF("We are a lover of the DB1 VCLK ratio\n");
1181         } else if (nv_crtc->head == 0) {
1182                 if (state->db1_ratio[0])
1183                         ErrorF("We are a lover of the DB1 VCLK ratio\n");
1184         }
1185
1186         /* The NV40 seems to have more similarities to NV3x than other cards. */
1187         if (pNv->NVArch < 0x41) {
1188                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL;
1189                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL;
1190         }
1191
1192         if (nv_crtc->head == 1) {
1193                 if (!state->db1_ratio[1]) {
1194                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1195                 } else {
1196                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1197                 }
1198                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
1199         } else {
1200                 if (!state->db1_ratio[0]) {
1201                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1202                 } else {
1203                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1204                 }
1205                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
1206         }
1207
1208         /* The blob uses this always, so let's do the same */
1209         if (pNv->Architecture == NV_ARCH_40) {
1210                 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
1211         }
1212
1213         /* The primary output resource doesn't seem to care */
1214         if (output && pNv->Architecture == NV_ARCH_40 && nv_output->output_resource == 1) { /* This is the "output" */
1215                 /* non-zero values are for analog, don't know about tv-out and the likes */
1216                 if (output && nv_output->type != OUTPUT_ANALOG) {
1217                         state->reg594 = 0x0;
1218                 } else if (output) {
1219                         /* Are we a flexible output? */
1220                         if (ffs(pNv->dcb_table.entry[nv_output->dcb_entry].or) & OUTPUT_0) {
1221                                 state->reg594 = 0x1;
1222                                 pNv->restricted_mode = FALSE;
1223                         } else {
1224                                 state->reg594 = 0x0;
1225                                 pNv->restricted_mode = TRUE;
1226                         }
1227
1228                         /* More values exist, but they seem related to the 3rd dac (tv-out?) somehow */
1229                         /* bit 16-19 are bits that are set on some G70 cards */
1230                         /* Those bits are also set to the 3rd OUTPUT register */
1231                         if (nv_crtc->head == 1) {
1232                                 state->reg594 |= 0x100;
1233                         }
1234                 }
1235         }
1236
1237         regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
1238         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
1239         if (pNv->Architecture >= NV_ARCH_30) {
1240                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
1241         }
1242
1243         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1244                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = ((CrtcHDisplay/16) & 0x700) >> 3;
1245         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1246                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((CrtcHDisplay*bpp)/64) & 0x700) >> 3;
1247         } else { /* framebuffer can be larger than crtc scanout area. */
1248                 regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
1249         }
1250         regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
1251 }
1252
1253 static void
1254 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
1255 {
1256         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1257
1258         ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->head, mode);
1259
1260         if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */
1261                 return;
1262
1263         nv_crtc->last_dpms = mode;
1264
1265         ScrnInfoPtr pScrn = crtc->scrn;
1266         NVPtr pNv = NVPTR(pScrn);
1267         unsigned char seq1 = 0, crtc17 = 0;
1268         unsigned char crtc1A;
1269
1270         if (pNv->twoHeads)
1271                 NVCrtcSetOwner(crtc);
1272
1273         crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
1274         switch(mode) {
1275                 case DPMSModeStandby:
1276                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
1277                 seq1 = 0x20;
1278                 crtc17 = 0x80;
1279                 crtc1A |= 0x80;
1280                 break;
1281         case DPMSModeSuspend:
1282                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
1283                 seq1 = 0x20;
1284                 crtc17 = 0x80;
1285                 crtc1A |= 0x40;
1286                 break;
1287         case DPMSModeOff:
1288                 /* Screen: Off; HSync: Off, VSync: Off */
1289                 seq1 = 0x20;
1290                 crtc17 = 0x00;
1291                 crtc1A |= 0xC0;
1292                 break;
1293         case DPMSModeOn:
1294         default:
1295                 /* Screen: On; HSync: On, VSync: On */
1296                 seq1 = 0x00;
1297                 crtc17 = 0x80;
1298                 break;
1299         }
1300
1301         NVVgaSeqReset(crtc, TRUE);
1302         /* Each head has it's own sequencer, so we can turn it off when we want */
1303         seq1 |= (NVReadVgaSeq(crtc, 0x01) & ~0x20);
1304         NVWriteVgaSeq(crtc, 0x1, seq1);
1305         crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
1306         usleep(10000);
1307         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
1308         NVVgaSeqReset(crtc, FALSE);
1309
1310         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
1311
1312         /* I hope this is the right place */
1313         if (crtc->enabled && mode == DPMSModeOn) {
1314                 pNv->crtc_active[nv_crtc->head] = TRUE;
1315         } else {
1316                 pNv->crtc_active[nv_crtc->head] = FALSE;
1317         }
1318 }
1319
1320 static Bool
1321 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
1322                      DisplayModePtr adjusted_mode)
1323 {
1324         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1325         ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->head);
1326
1327         return TRUE;
1328 }
1329
1330 static void
1331 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1332 {
1333         ScrnInfoPtr pScrn = crtc->scrn;
1334         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1335         NVCrtcRegPtr regp;
1336         NVPtr pNv = NVPTR(pScrn);
1337         NVFBLayout *pLayout = &pNv->CurrentLayout;
1338         int depth = pScrn->depth;
1339
1340         /* This is pitch/memory size related. */
1341         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE))
1342                 depth = pNv->console_mode[nv_crtc->head].bpp;
1343
1344         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1345
1346         /* Calculate our timings */
1347         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
1348         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
1349         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
1350         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
1351         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
1352         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
1353         int vertDisplay         = mode->CrtcVDisplay                    - 1;
1354         int vertStart           = mode->CrtcVSyncStart          - 1;
1355         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
1356         int vertTotal           = mode->CrtcVTotal                      - 2;
1357         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
1358         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
1359
1360         Bool is_fp = FALSE;
1361
1362         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1363         NVOutputPrivatePtr nv_output = NULL;
1364         if (output) {
1365                 nv_output = output->driver_private;
1366
1367                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1368                         is_fp = TRUE;
1369         }
1370
1371         ErrorF("Mode clock: %d\n", mode->Clock);
1372         ErrorF("Adjusted mode clock: %d\n", adjusted_mode->Clock);
1373
1374         /* Reverted to what nv did, because that works for all resolutions on flatpanels */
1375         if (is_fp) {
1376                 vertStart = vertTotal - 3;
1377                 vertEnd = vertTotal - 2;
1378                 vertBlankStart = vertStart;
1379                 horizStart = horizTotal - 5;
1380                 horizEnd = horizTotal - 2;
1381                 horizBlankEnd = horizTotal + 4;
1382                 if (pNv->overlayAdaptor && pNv->Architecture >= NV_ARCH_10) {
1383                         /* This reportedly works around Xv some overlay bandwidth problems*/
1384                         horizTotal += 2;
1385                 }
1386         }
1387
1388         if (mode->Flags & V_INTERLACE)
1389                 vertTotal |= 1;
1390
1391         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
1392         ErrorF("horizStart: 0x%X \n", horizStart);
1393         ErrorF("horizEnd: 0x%X \n", horizEnd);
1394         ErrorF("horizTotal: 0x%X \n", horizTotal);
1395         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
1396         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
1397         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
1398         ErrorF("vertStart: 0x%X \n", vertStart);
1399         ErrorF("vertEnd: 0x%X \n", vertEnd);
1400         ErrorF("vertTotal: 0x%X \n", vertTotal);
1401         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
1402         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
1403
1404         /*
1405         * compute correct Hsync & Vsync polarity
1406         */
1407         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
1408                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
1409
1410                 regp->MiscOutReg = 0x23;
1411                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
1412                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
1413         } else {
1414                 int VDisplay = mode->VDisplay;
1415                 if (mode->Flags & V_DBLSCAN)
1416                         VDisplay *= 2;
1417                 if (mode->VScan > 1)
1418                         VDisplay *= mode->VScan;
1419                 if (VDisplay < 400) {
1420                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
1421                 } else if (VDisplay < 480) {
1422                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
1423                 } else if (VDisplay < 768) {
1424                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
1425                 } else {
1426                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
1427                 }
1428         }
1429
1430         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
1431
1432         /*
1433         * Time Sequencer
1434         */
1435         regp->Sequencer[0] = 0x00;
1436         /* 0x20 disables the sequencer */
1437         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1438                 if (mode->HDisplay == 720) {
1439                         regp->Sequencer[1] = 0x21; /* enable 9/8 mode */
1440                 } else {
1441                         regp->Sequencer[1] = 0x20;
1442                 }
1443         } else {
1444                 if (mode->Flags & V_CLKDIV2) {
1445                         regp->Sequencer[1] = 0x29;
1446                 } else {
1447                         regp->Sequencer[1] = 0x21;
1448                 }
1449         }
1450         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1451                 regp->Sequencer[2] = 0x03; /* select 2 out of 4 planes */
1452         } else {
1453                 regp->Sequencer[2] = 0x0F;
1454         }
1455         regp->Sequencer[3] = 0x00;                     /* Font select */
1456         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1457                 regp->Sequencer[4] = 0x02;
1458         } else {
1459                 regp->Sequencer[4] = 0x0E;                             /* Misc */
1460         }
1461
1462         /*
1463         * CRTC Controller
1464         */
1465         regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
1466         regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
1467         regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
1468         regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0)
1469                                 | SetBit(7);
1470         regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
1471         regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
1472                                 | SetBitField(horizEnd,4:0,4:0);
1473         regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
1474         regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
1475                                 | SetBitField(vertDisplay,8:8,1:1)
1476                                 | SetBitField(vertStart,8:8,2:2)
1477                                 | SetBitField(vertBlankStart,8:8,3:3)
1478                                 | SetBit(4)
1479                                 | SetBitField(vertTotal,9:9,5:5)
1480                                 | SetBitField(vertDisplay,9:9,6:6)
1481                                 | SetBitField(vertStart,9:9,7:7);
1482         regp->CRTC[NV_VGA_CRTCX_PRROWSCN]  = 0x00;
1483         regp->CRTC[NV_VGA_CRTCX_MAXSCLIN]  = SetBitField(vertBlankStart,9:9,5:5)
1484                                 | SetBit(6)
1485                                 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00)
1486                                 | (NVMatchModePrivate(mode, NV_MODE_VGA) ? 0xF : 0x00); /* 8x15 chars */
1487         if (NVMatchModePrivate(mode, NV_MODE_VGA)) { /* Were do these cursor offsets come from? */
1488                 regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0xD; /* start scanline */
1489                 regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0xE; /* end scanline */
1490         } else {
1491                 regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0x00;
1492                 regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0x00;
1493         }
1494         regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00;
1495         regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
1496         regp->CRTC[0xe] = 0x00;
1497         regp->CRTC[0xf] = 0x00;
1498         regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
1499         /* What is the meaning of bit5, it is empty in the vga spec. */
1500         regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) |
1501                                                                         (NVMatchModePrivate(mode, NV_MODE_VGA) ? 0 : SetBit(5));
1502         regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
1503         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1504                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = (mode->CrtcHDisplay/16);
1505         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1506                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((mode->CrtcHDisplay*depth)/64);
1507         } else { /* framebuffer can be larger than crtc scanout area. */
1508                 regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
1509         }
1510         if (depth == 4) { /* How can these values be calculated? */
1511                 regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x1F;
1512         } else {
1513                 regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x00;
1514         }
1515         regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
1516         regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
1517         /* 0x80 enables the sequencer, we don't want that */
1518         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1519                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xA3 & ~0x80;
1520         } else if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1521                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xE3 & ~0x80;
1522         } else {
1523                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80;
1524         }
1525         regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
1526
1527         /*
1528          * Some extended CRTC registers (they are not saved with the rest of the vga regs).
1529          */
1530
1531         regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
1532                                 | SetBitField(vertBlankStart,10:10,3:3)
1533                                 | SetBitField(vertStart,10:10,2:2)
1534                                 | SetBitField(vertDisplay,10:10,1:1)
1535                                 | SetBitField(vertTotal,10:10,0:0);
1536
1537         regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
1538                                 | SetBitField(horizDisplay,8:8,1:1)
1539                                 | SetBitField(horizBlankStart,8:8,2:2)
1540                                 | SetBitField(horizStart,8:8,3:3);
1541
1542         regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
1543                                 | SetBitField(vertDisplay,11:11,2:2)
1544                                 | SetBitField(vertStart,11:11,4:4)
1545                                 | SetBitField(vertBlankStart,11:11,6:6);
1546
1547         if(mode->Flags & V_INTERLACE) {
1548                 horizTotal = (horizTotal >> 1) & ~1;
1549                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
1550                 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
1551         } else {
1552                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff;  /* interlace off */
1553         }
1554
1555         /*
1556         * Theory resumes here....
1557         */
1558
1559         /*
1560         * Graphics Display Controller
1561         */
1562         regp->Graphics[0] = 0x00;
1563         regp->Graphics[1] = 0x00;
1564         regp->Graphics[2] = 0x00;
1565         regp->Graphics[3] = 0x00;
1566         regp->Graphics[4] = 0x00;
1567         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1568                 regp->Graphics[5] = 0x10;
1569                 regp->Graphics[6] = 0x0E; /* map 32k mem */
1570                 regp->Graphics[7] = 0x00;
1571         } else {
1572                 regp->Graphics[5] = 0x40; /* 256 color mode */
1573                 regp->Graphics[6] = 0x05; /* map 64k mem + graphic mode */
1574                 regp->Graphics[7] = 0x0F;
1575         }
1576         regp->Graphics[8] = 0xFF;
1577
1578         /* I ditched the mono stuff */
1579         regp->Attribute[0]  = 0x00; /* standard colormap translation */
1580         regp->Attribute[1]  = 0x01;
1581         regp->Attribute[2]  = 0x02;
1582         regp->Attribute[3]  = 0x03;
1583         regp->Attribute[4]  = 0x04;
1584         regp->Attribute[5]  = 0x05;
1585         regp->Attribute[6]  = 0x06;
1586         regp->Attribute[7]  = 0x07;
1587         regp->Attribute[8]  = 0x08;
1588         regp->Attribute[9]  = 0x09;
1589         regp->Attribute[10] = 0x0A;
1590         regp->Attribute[11] = 0x0B;
1591         regp->Attribute[12] = 0x0C;
1592         regp->Attribute[13] = 0x0D;
1593         regp->Attribute[14] = 0x0E;
1594         regp->Attribute[15] = 0x0F;
1595         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1596                 regp->Attribute[16] = 0x0C; /* Line Graphics Enable + Blink enable */
1597         } else {
1598                 regp->Attribute[16] = 0x01; /* Enable graphic mode */
1599         }
1600         /* Non-vga */
1601         regp->Attribute[17] = 0x00;
1602         regp->Attribute[18] = 0x0F; /* enable all color planes */
1603         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1604                 regp->Attribute[19] = 0x08; /* shift bits by 8 */
1605         } else {
1606                 regp->Attribute[19] = 0x00;
1607         }
1608         regp->Attribute[20] = 0x00;
1609 }
1610
1611 #define MAX_H_VALUE(i) ((0x1ff + i) << 3)
1612 #define MAX_V_VALUE(i) ((0xfff + i) << 0)
1613
1614 /**
1615  * Sets up registers for the given mode/adjusted_mode pair.
1616  *
1617  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1618  *
1619  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1620  * be easily turned on/off after this.
1621  */
1622 static void
1623 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1624 {
1625         ScrnInfoPtr pScrn = crtc->scrn;
1626         NVPtr pNv = NVPTR(pScrn);
1627         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1628         NVFBLayout *pLayout = &pNv->CurrentLayout;
1629         NVCrtcRegPtr regp, savep;
1630         uint32_t i, depth;
1631         Bool is_fp = FALSE;
1632         Bool is_lvds = FALSE;
1633
1634         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1635         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1636
1637         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1638         NVOutputPrivatePtr nv_output = NULL;
1639         if (output) {
1640                 nv_output = output->driver_private;
1641
1642                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1643                         is_fp = TRUE;
1644
1645                 if (nv_output->type == OUTPUT_LVDS)
1646                         is_lvds = TRUE;
1647         }
1648
1649         /* Registers not directly related to the (s)vga mode */
1650
1651         /* bit2 = 0 -> fine pitched crtc granularity */
1652         /* The rest disables double buffering on CRTC access */
1653         regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
1654
1655         if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
1656                 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1657                 if (nv_crtc->head == 0) {
1658                         regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1659                 }
1660
1661                 if (is_fp) {
1662                         regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0);
1663                         if (!NVMatchModePrivate(mode, NV_MODE_VGA)) {
1664                                 regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 1);
1665                         }
1666                 }
1667         } else {
1668                 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
1669                 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
1670         }
1671
1672         /* Sometimes 0x10 is used, what is this? */
1673         regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1674         /* Some kind of tmds switch for older cards */
1675         if (pNv->Architecture < NV_ARCH_40) {
1676                 regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
1677         }
1678
1679         /*
1680         * Initialize DAC palette.
1681         * Will only be written when depth != 8.
1682         */
1683         for (i = 0; i < 256; i++) {
1684                 regp->DAC[i*3] = i;
1685                 regp->DAC[(i*3)+1] = i;
1686                 regp->DAC[(i*3)+2] = i;
1687         }
1688
1689         /*
1690         * Calculate the extended registers.
1691         */
1692
1693         if (pLayout->depth < 24) {
1694                 depth = pLayout->depth;
1695         } else {
1696                 depth = 32;
1697         }
1698
1699         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1700                 /* bpp is pitch related. */
1701                 depth = pNv->console_mode[nv_crtc->head].bpp;
1702         }
1703
1704         /* What is the meaning of this register? */
1705         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1706         regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
1707
1708         regp->head = 0;
1709
1710         /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1711         /* But what are those special conditions? */
1712         if (pNv->Architecture <= NV_ARCH_30) {
1713                 if (is_fp) {
1714                         if(nv_crtc->head == 1) {
1715                                 regp->head |= NV_CRTC_FSEL_FPP1;
1716                         } else if (pNv->twoHeads) {
1717                                 regp->head |= NV_CRTC_FSEL_FPP2;
1718                         }
1719                 }
1720         } else {
1721                 /* Most G70 cards have FPP2 set on the secondary CRTC. */
1722                 if (nv_crtc->head == 1 && pNv->NVArch > 0x44) {
1723                         regp->head |= NV_CRTC_FSEL_FPP2;
1724                 }
1725         }
1726
1727         /* Except for rare conditions I2C is enabled on the primary crtc */
1728         if (nv_crtc->head == 0) {
1729                 regp->head |= NV_CRTC_FSEL_I2C;
1730         }
1731
1732         /* Set overlay to desired crtc. */
1733         if (pNv->overlayAdaptor) {
1734                 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(pNv);
1735                 if (pPriv->overlayCRTC == nv_crtc->head)
1736                         regp->head |= NV_CRTC_FSEL_OVERLAY;
1737         }
1738
1739         /* This is not what nv does, but it is what the blob does (for nv4x at least) */
1740         /* This fixes my cursor corruption issue */
1741         regp->cursorConfig = 0x0;
1742         if(mode->Flags & V_DBLSCAN)
1743                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_DOUBLE_SCAN;
1744         if (pNv->alphaCursor && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1745                 regp->cursorConfig |=   (NV_CRTC_CURSOR_CONFIG_32BPP |
1746                                                         NV_CRTC_CURSOR_CONFIG_64PIXELS |
1747                                                         NV_CRTC_CURSOR_CONFIG_64LINES |
1748                                                         NV_CRTC_CURSOR_CONFIG_ALPHA_BLEND);
1749         } else {
1750                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_32LINES;
1751         }
1752
1753         /* Unblock some timings */
1754         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1755         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1756
1757         /* What is the purpose of this register? */
1758         /* 0x14 may be disabled? */
1759         regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1760
1761         /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
1762         if (is_lvds) {
1763                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x11;
1764         } else if (is_fp) {
1765                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1766         } else {
1767                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1768         }
1769
1770         /* These values seem to vary */
1771         /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
1772         regp->CRTC[NV_VGA_CRTCX_3C] = savep->CRTC[NV_VGA_CRTCX_3C];
1773
1774         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1775                 regp->CRTC[NV_VGA_CRTCX_45] = 0x0;
1776         } else {
1777                 regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1778         }
1779
1780         /* What does this do?:
1781          * bit0: crtc0
1782          * bit6: lvds
1783          * bit7: lvds + tmds (only in X)
1784          */
1785         if (nv_crtc->head == 0)
1786                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x1;
1787         else
1788                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x0;
1789
1790         if (is_lvds)
1791                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x40;
1792
1793         if (is_fp && !NVMatchModePrivate(mode, NV_MODE_VGA))
1794                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x80;
1795
1796         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) { /* we need consistent restore. */
1797                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[nv_crtc->head];
1798         } else {
1799                 /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1.*/
1800                 if (nv_crtc->head == 1) {
1801                         regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[0];
1802                 } else {
1803                         regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_reg_52[0] + 4;
1804                 }
1805         }
1806
1807         if (pNv->twoHeads)
1808                 /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1809                 regp->unk81c = NVReadCRTC(pNv, 0, NV_CRTC_081C);
1810
1811         if (NVMatchModePrivate(mode, NV_MODE_VGA)) {
1812                 regp->unk830 = 0;
1813                 regp->unk834 = 0;
1814         } else {
1815                 regp->unk830 = mode->CrtcVDisplay - 3;
1816                 regp->unk834 = mode->CrtcVDisplay - 1;
1817         }
1818
1819         if (pNv->twoHeads)
1820                 /* This is what the blob does */
1821                 regp->unk850 = NVReadCRTC(pNv, 0, NV_CRTC_0850);
1822
1823         /* Never ever modify gpio, unless you know very well what you're doing */
1824         regp->gpio = NVReadCRTC(pNv, 0, NV_CRTC_GPIO);
1825
1826         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
1827                 regp->config = 0x0; /* VGA mode */
1828         } else {
1829                 regp->config = 0x2; /* HSYNC mode */
1830         }
1831
1832         /* Some misc regs */
1833         regp->CRTC[NV_VGA_CRTCX_43] = 0x1;
1834         if (pNv->Architecture == NV_ARCH_40) {
1835                 regp->CRTC[NV_VGA_CRTCX_85] = 0xFF;
1836                 regp->CRTC[NV_VGA_CRTCX_86] = 0x1;
1837         }
1838
1839         /*
1840          * Calculate the state that is common to all crtc's (stored in the state struct).
1841          */
1842         ErrorF("crtc %d %d %d\n", nv_crtc->head, mode->CrtcHDisplay, pScrn->displayWidth);
1843         nv_crtc_calc_state_ext(crtc,
1844                                 mode,
1845                                 depth,
1846                                 pScrn->displayWidth,
1847                                 mode->CrtcHDisplay,
1848                                 mode->CrtcVDisplay,
1849                                 adjusted_mode->Clock,
1850                                 mode->Flags);
1851
1852         /* Enable slaved mode */
1853         if (is_fp) {
1854                 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1855         }
1856 }
1857
1858 static void
1859 nv_crtc_mode_set_ramdac_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1860 {
1861         ScrnInfoPtr pScrn = crtc->scrn;
1862         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1863         NVCrtcRegPtr regp, savep;
1864         NVPtr pNv = NVPTR(pScrn);
1865         NVFBLayout *pLayout = &pNv->CurrentLayout;
1866         Bool is_fp = FALSE;
1867         Bool is_lvds = FALSE;
1868         float aspect_ratio, panel_ratio;
1869         uint32_t h_scale, v_scale;
1870
1871         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1872         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1873
1874         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1875         NVOutputPrivatePtr nv_output = NULL;
1876         if (output) {
1877                 nv_output = output->driver_private;
1878
1879                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1880                         is_fp = TRUE;
1881
1882                 if (nv_output->type == OUTPUT_LVDS)
1883                         is_lvds = TRUE;
1884         }
1885
1886         if (is_fp) {
1887                 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
1888                 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
1889                 /* This is what the blob does. */
1890                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HSyncStart - 75 - 1;
1891                 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
1892                 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
1893                 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
1894                 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
1895
1896                 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
1897                 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
1898                 /* This is what the blob does. */
1899                 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VTotal - 5 - 1;
1900                 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
1901                 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
1902                 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
1903                 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
1904
1905                 ErrorF("Horizontal:\n");
1906                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
1907                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
1908                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
1909                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
1910                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
1911                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
1912                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
1913
1914                 ErrorF("Vertical:\n");
1915                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
1916                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
1917                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
1918                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
1919                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
1920                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
1921                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
1922         }
1923
1924         /*
1925         * bit0: positive vsync
1926         * bit4: positive hsync
1927         * bit8: enable center mode
1928         * bit9: enable native mode
1929         * bit24: 12/24 bit interface (12bit=on, 24bit=off)
1930         * bit26: a bit sometimes seen on some g70 cards
1931         * bit28: fp display enable bit
1932         * bit31: set for dual link LVDS
1933         * nv10reg contains a few more things, but i don't quite get what it all means.
1934         */
1935
1936         if (pNv->Architecture >= NV_ARCH_30)
1937                 regp->fp_control[nv_crtc->head] = 0x00100000;
1938         else
1939                 regp->fp_control[nv_crtc->head] = 0x00000000;
1940
1941         /* Deal with vsync/hsync polarity */
1942         /* LVDS screens do set this, but modes with +ve syncs are very rare */
1943         if (is_fp) {
1944                 if (adjusted_mode->Flags & V_PVSYNC)
1945                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
1946                 if (adjusted_mode->Flags & V_PHSYNC)
1947                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
1948         } else {
1949                 /* The blob doesn't always do this, but often */
1950                 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_VSYNC_DISABLE;
1951                 regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_HSYNC_DISABLE;
1952         }
1953
1954         if (is_fp) {
1955                 if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) /* seems to be used almost always */
1956                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1957                 else if (nv_output->scaling_mode == SCALE_PANEL) /* panel needs to scale */
1958                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
1959                 /* This is also true for panel scaling, so we must put the panel scale check first */
1960                 else if (mode->Clock == adjusted_mode->Clock) /* native mode */
1961                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
1962                 else /* gpu needs to scale */
1963                         regp->fp_control[nv_crtc->head] |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1964         }
1965
1966         if (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
1967                 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
1968
1969         /* If the special bit exists, it exists on both ramdacs */
1970         regp->fp_control[nv_crtc->head] |= NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL) & (1 << 26);
1971
1972         if (is_fp)
1973                 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS;
1974         else
1975                 regp->fp_control[nv_crtc->head] |= NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE;
1976
1977         Bool lvds_use_straps = pNv->dcb_table.entry[nv_output->dcb_entry].lvdsconf.use_straps_for_mode;
1978         if (is_lvds && ((lvds_use_straps && pNv->VBIOS.fp.dual_link) || (!lvds_use_straps && adjusted_mode->Clock >= pNv->VBIOS.fp.duallink_transition_clk)))
1979                 regp->fp_control[nv_crtc->head] |= (8 << 28);
1980
1981         if (is_fp) {
1982                 ErrorF("Pre-panel scaling\n");
1983                 ErrorF("panel-size:%dx%d\n", nv_output->fpWidth, nv_output->fpHeight);
1984                 panel_ratio = (nv_output->fpWidth)/(float)(nv_output->fpHeight);
1985                 ErrorF("panel_ratio=%f\n", panel_ratio);
1986                 aspect_ratio = (mode->HDisplay)/(float)(mode->VDisplay);
1987                 ErrorF("aspect_ratio=%f\n", aspect_ratio);
1988                 /* Scale factors is the so called 20.12 format, taken from Haiku */
1989                 h_scale = ((1 << 12) * mode->HDisplay)/nv_output->fpWidth;
1990                 v_scale = ((1 << 12) * mode->VDisplay)/nv_output->fpHeight;
1991                 ErrorF("h_scale=%d\n", h_scale);
1992                 ErrorF("v_scale=%d\n", v_scale);
1993
1994                 /* This can override HTOTAL and VTOTAL */
1995                 regp->debug_2 = 0;
1996
1997                 /* We want automatic scaling */
1998                 regp->debug_1 = 0;
1999
2000                 regp->fp_hvalid_start = 0;
2001                 regp->fp_hvalid_end = (nv_output->fpWidth - 1);
2002
2003                 regp->fp_vvalid_start = 0;
2004                 regp->fp_vvalid_end = (nv_output->fpHeight - 1);
2005
2006                 /* 0 = panel scaling */
2007                 if (nv_output->scaling_mode == SCALE_PANEL) {
2008                         ErrorF("Flat panel is doing the scaling.\n");
2009                 } else {
2010                         ErrorF("GPU is doing the scaling.\n");
2011
2012                         if (nv_output->scaling_mode == SCALE_ASPECT) {
2013                                 /* GPU scaling happens automaticly at a ratio of 1.33 */
2014                                 /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
2015                                 if (h_scale != (1 << 12) && (panel_ratio > (aspect_ratio + 0.10))) {
2016                                         uint32_t diff;
2017
2018                                         ErrorF("Scaling resolution on a widescreen panel\n");
2019
2020                                         /* Scaling in both directions needs to the same */
2021                                         h_scale = v_scale;
2022
2023                                         /* Set a new horizontal scale factor and enable testmode (bit12) */
2024                                         regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
2025
2026                                         diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
2027                                         regp->fp_hvalid_start = diff/2;
2028                                         regp->fp_hvalid_end = nv_output->fpWidth - (diff/2) - 1;
2029                                 }
2030
2031                                 /* Same scaling, just for panels with aspect ratio's smaller than 1 */
2032                                 if (v_scale != (1 << 12) && (panel_ratio < (aspect_ratio - 0.10))) {
2033                                         uint32_t diff;
2034
2035                                         ErrorF("Scaling resolution on a portrait panel\n");
2036
2037                                         /* Scaling in both directions needs to the same */
2038                                         v_scale = h_scale;
2039
2040                                         /* Set a new vertical scale factor and enable testmode (bit28) */
2041                                         regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
2042
2043                                         diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
2044                                         regp->fp_vvalid_start = diff/2;
2045                                         regp->fp_vvalid_end = nv_output->fpHeight - (diff/2) - 1;
2046                                 }
2047                         }
2048                 }
2049
2050                 ErrorF("Post-panel scaling\n");
2051         }
2052
2053         if (!is_fp && NVMatchModePrivate(mode, NV_MODE_VGA)) {
2054                 regp->debug_1 = 0x08000800;
2055         }
2056
2057         if (pNv->Architecture >= NV_ARCH_10) {
2058                 /* Only bit that bios and blob set. */
2059                 regp->nv10_cursync = (1<<25);
2060         }
2061
2062         /* These are the common blob values, minus a few fp specific bit's */
2063         /* Let's keep the TMDS pll and fpclock running in all situations */
2064         regp->debug_0[nv_crtc->head] = 0x1101100;
2065
2066         if (is_fp && nv_output->scaling_mode != SCALE_NOSCALE) {
2067                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_XSCALE_ENABLED;
2068                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_YSCALE_ENABLED;
2069         } else if (is_fp) { /* no_scale mode, so we must center it */
2070                 uint32_t diff;
2071
2072                 diff = nv_output->fpWidth - mode->HDisplay;
2073                 regp->fp_hvalid_start = diff/2;
2074                 regp->fp_hvalid_end = (nv_output->fpWidth - diff/2 - 1);
2075
2076                 diff = nv_output->fpHeight - mode->VDisplay;
2077                 regp->fp_vvalid_start = diff/2;
2078                 regp->fp_vvalid_end = (nv_output->fpHeight - diff/2 - 1);
2079         }
2080
2081         /* Is this crtc bound or output bound? */
2082         /* Does the bios TMDS script try to change this sometimes? */
2083         if (is_fp) {
2084                 /* I am not completely certain, but seems to be set only for dfp's */
2085                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED;
2086         }
2087
2088         if (output)
2089                 ErrorF("output %d debug_0 %08X\n", nv_output->output_resource, regp->debug_0[nv_crtc->head]);
2090
2091         /* Flatpanel support needs at least a NV10 */
2092         if (pNv->twoHeads) {
2093                 /* The blob does this differently. */
2094                 /* TODO: Find out what precisely and why. */
2095                 /* Let's not destroy any bits that were already present. */
2096                 if (pNv->FPDither || (is_lvds && pNv->VBIOS.fp.if_is_18bit)) {
2097                         if (pNv->NVArch == 0x11) {
2098                                 regp->dither = savep->dither | 0x00010000;
2099                         } else {
2100                                 regp->dither = savep->dither | 0x00000001;
2101                         }
2102                 } else {
2103                         regp->dither = savep->dither;
2104                 }
2105         }
2106
2107         uint8_t depth;
2108         /* This is mode related, not pitch. */
2109         if (NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
2110                 depth = pNv->console_mode[nv_crtc->head].depth;
2111         } else {
2112                 depth = pLayout->depth;
2113         }
2114
2115         switch (depth) {
2116                 case 4:
2117                         regp->general = 0x00000100;
2118                         break;
2119                 case 24:
2120                 case 15:
2121                         regp->general = 0x00100100;
2122                         break;
2123                 case 32:
2124                 case 16:
2125                 case 8:
2126                 default:
2127                         regp->general = 0x00101100;
2128                         break;
2129         }
2130
2131         if (depth > 8 && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
2132                 regp->general |= 0x30; /* enable palette mode */
2133         }
2134
2135         if (pNv->alphaCursor && !NVMatchModePrivate(mode, NV_MODE_CONSOLE)) {
2136                 /* PIPE_LONG mode, something to do with the size of the cursor? */
2137                 regp->general |= (1<<29);
2138         }
2139
2140         /* Some values the blob sets */
2141         /* This may apply to the real ramdac that is being used (for crosswired situations) */
2142         /* Nevertheless, it's unlikely to cause many problems, since the values are equal for both */
2143         regp->unk_a20 = 0x0;
2144         regp->unk_a24 = 0xfffff;
2145         regp->unk_a34 = 0x1;
2146
2147         if (pNv->twoHeads) {
2148                 /* Do we also "own" the other register pair? */
2149                 /* If we own neither, they will just be ignored at load time. */
2150                 uint8_t other_head = (~nv_crtc->head) & 1;
2151                 if (pNv->fp_regs_owner[other_head] == nv_crtc->head) {
2152                         if (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS) {
2153                                 regp->fp_control[other_head] = regp->fp_control[nv_crtc->head];
2154                                 regp->debug_0[other_head] = regp->debug_0[nv_crtc->head];
2155                                 /* Set TMDS_PLL and FPCLK, only seen for a NV31M so far. */
2156                                 regp->debug_0[nv_crtc->head] |= NV_RAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK;
2157                                 regp->debug_0[other_head] |= NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL;
2158                         } else {
2159                                 ErrorF("This is BAD, we own more than one fp reg set, but are not a LVDS or TMDS output.\n");
2160                         }
2161                 }
2162         }
2163 }
2164
2165 /**
2166  * Sets up registers for the given mode/adjusted_mode pair.
2167  *
2168  * The clocks, CRTCs and outputs attached to this CRTC must be off.
2169  *
2170  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
2171  * be easily turned on/off after this.
2172  */
2173 static void
2174 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
2175                  DisplayModePtr adjusted_mode,
2176                  int x, int y)
2177 {
2178         ScrnInfoPtr pScrn = crtc->scrn;
2179         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2180         NVPtr pNv = NVPTR(pScrn);
2181         NVFBLayout *pLayout = &pNv->CurrentLayout;
2182
2183         ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->head);
2184
2185         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->head);
2186         xf86PrintModeline(pScrn->scrnIndex, mode);
2187         if (pNv->twoHeads)
2188                 NVCrtcSetOwner(crtc);
2189
2190         nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
2191         nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
2192         nv_crtc_mode_set_ramdac_regs(crtc, mode, adjusted_mode);
2193
2194         NVVgaProtect(crtc, TRUE);
2195         nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
2196         nv_crtc_load_state_ext(crtc, &pNv->ModeReg, FALSE);
2197         if (pLayout->depth > 8)
2198                 NVCrtcLoadPalette(crtc);
2199         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
2200         if (pNv->Architecture == NV_ARCH_40) {
2201                 nv40_crtc_load_state_pll(crtc, &pNv->ModeReg);
2202         } else {
2203                 nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
2204         }
2205
2206         NVVgaProtect(crtc, FALSE);
2207
2208         NVCrtcSetBase(crtc, x, y, NVMatchModePrivate(mode, NV_MODE_CONSOLE));
2209
2210 #if X_BYTE_ORDER == X_BIG_ENDIAN
2211         /* turn on LFB swapping */
2212         {
2213                 unsigned char tmp;
2214
2215                 tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
2216                 tmp |= (1 << 7);
2217                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
2218         }
2219 #endif
2220 }
2221
2222 /* This functions generates data that is not saved, but still is needed. */
2223 void nv_crtc_restore_generate(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2224 {
2225         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2226         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
2227         int i;
2228
2229         /* It's a good idea to also save a default palette on shutdown. */
2230         for (i = 0; i < 256; i++) {
2231                 regp->DAC[i*3] = i;
2232                 regp->DAC[(i*3)+1] = i;
2233                 regp->DAC[(i*3)+2] = i;
2234         }
2235 }
2236
2237 void nv_crtc_save(xf86CrtcPtr crtc)
2238 {
2239         ScrnInfoPtr pScrn = crtc->scrn;
2240         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2241         NVPtr pNv = NVPTR(pScrn);
2242
2243         ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->head);
2244
2245         /* We just came back from terminal, so unlock */
2246         NVCrtcLockUnlock(crtc, FALSE);
2247
2248         if (pNv->twoHeads)
2249                 NVCrtcSetOwner(crtc);
2250         nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
2251         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
2252         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
2253         if (pNv->Architecture == NV_ARCH_40) {
2254                 nv40_crtc_save_state_pll(pNv, &pNv->SavedReg);
2255         } else {
2256                 nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
2257         }
2258 }
2259
2260 void nv_crtc_restore(xf86CrtcPtr crtc)
2261 {
2262         ScrnInfoPtr pScrn = crtc->scrn;
2263         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2264         NVPtr pNv = NVPTR(pScrn);
2265         RIVA_HW_STATE *state;
2266         NVCrtcRegPtr savep;
2267
2268         state = &pNv->SavedReg;
2269         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
2270
2271         ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->head);
2272
2273         if (pNv->twoHeads)
2274                 NVCrtcSetOwner(crtc);
2275
2276         /* Just to be safe */
2277         NVCrtcLockUnlock(crtc, FALSE);
2278
2279         NVVgaProtect(crtc, TRUE);
2280         nv_crtc_restore_generate(crtc, &pNv->SavedReg);
2281         nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
2282         nv_crtc_load_state_ext(crtc, &pNv->SavedReg, TRUE);
2283         if (savep->general & 0x30) /* Palette mode */
2284                 NVCrtcLoadPalette(crtc);
2285         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
2286
2287         /* Force restoring vpll. */
2288         state->vpll_changed[nv_crtc->head] = TRUE;
2289
2290         if (pNv->Architecture == NV_ARCH_40) {
2291                 nv40_crtc_load_state_pll(crtc, &pNv->SavedReg);
2292         } else {
2293                 nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
2294         }
2295         if (pNv->twoHeads)
2296                 nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->vtOWNER);
2297         NVVgaProtect(crtc, FALSE);
2298
2299         nv_crtc->last_dpms = NV_DPMS_CLEARED;
2300 }
2301
2302 static void
2303 NVResetCrtcConfig(xf86CrtcPtr crtc, Bool set)
2304 {
2305         ScrnInfoPtr pScrn = crtc->scrn;
2306         NVPtr pNv = NVPTR(pScrn);
2307
2308         if (pNv->twoHeads) {
2309                 uint32_t val = 0;
2310
2311                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2312
2313                 if (set) {
2314                         NVCrtcRegPtr regp;
2315
2316                         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2317                         val = regp->head;
2318                 }
2319
2320                 NVCrtcWriteCRTC(crtc, NV_CRTC_FSEL, val);
2321         }
2322 }
2323
2324 void nv_crtc_prepare(xf86CrtcPtr crtc)
2325 {
2326         ScrnInfoPtr pScrn = crtc->scrn;
2327         NVPtr pNv = NVPTR(pScrn);
2328         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2329
2330         ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->head);
2331
2332         /* Just in case */
2333         NVCrtcLockUnlock(crtc, 0);
2334
2335         NVResetCrtcConfig(crtc, FALSE);
2336
2337         crtc->funcs->dpms(crtc, DPMSModeOff);
2338
2339         /* Sync the engine before adjust mode */
2340         if (pNv->EXADriverPtr) {
2341                 exaMarkSync(pScrn->pScreen);
2342                 exaWaitSync(pScrn->pScreen);
2343         }
2344
2345         NVCrtcBlankScreen(crtc, FALSE); /* Blank screen */
2346
2347         /* Some more preperation. */
2348         NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, 0x1); /* Go to non-vga mode/out of enhanced mode */
2349         if (pNv->Architecture == NV_ARCH_40) {
2350                 uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
2351                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
2352         }
2353 }
2354
2355 void nv_crtc_commit(xf86CrtcPtr crtc)
2356 {
2357         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2358         ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->head);
2359
2360         crtc->funcs->dpms (crtc, DPMSModeOn);
2361
2362         if (crtc->scrn->pScreen != NULL)
2363                 xf86_reload_cursors (crtc->scrn->pScreen);
2364
2365         NVResetCrtcConfig(crtc, TRUE);
2366 }
2367
2368 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
2369 {
2370         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2371         ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->head);
2372
2373         return FALSE;
2374 }
2375
2376 static void nv_crtc_unlock(xf86CrtcPtr crtc)
2377 {
2378         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2379         ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->head);
2380 }
2381
2382 static void
2383 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
2384                                         int size)
2385 {
2386         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2387         ScrnInfoPtr pScrn = crtc->scrn;
2388         NVPtr pNv = NVPTR(pScrn);
2389         int i, j;
2390
2391         NVCrtcRegPtr regp;
2392         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2393
2394         switch (pNv->CurrentLayout.depth) {
2395         case 15:
2396                 /* R5G5B5 */
2397                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
2398                 for (i = 0; i < 32; i++) {
2399                         for (j = 0; j < 8; j++) {
2400                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2401                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
2402                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2403                         }
2404                 }
2405                 break;
2406         case 16:
2407                 /* R5G6B5 */
2408                 /* First deal with the 5 bit colors */
2409                 for (i = 0; i < 32; i++) {
2410                         for (j = 0; j < 8; j++) {
2411                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2412                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2413                         }
2414                 }
2415                 /* Now deal with the 6 bit color */
2416                 for (i = 0; i < 64; i++) {
2417                         for (j = 0; j < 4; j++) {
2418                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
2419                         }
2420                 }
2421                 break;
2422         default:
2423                 /* R8G8B8 */
2424                 for (i = 0; i < 256; i++) {
2425                         regp->DAC[i * 3] = red[i] >> 8;
2426                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
2427                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
2428                 }
2429                 break;
2430         }
2431
2432         NVCrtcLoadPalette(crtc);
2433 }
2434
2435 /**
2436  * Allocates memory for a locked-in-framebuffer shadow of the given
2437  * width and height for this CRTC's rotated shadow framebuffer.
2438  */
2439
2440 static void *
2441 nv_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
2442 {
2443         ErrorF("nv_crtc_shadow_allocate is called\n");
2444         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2445         ScrnInfoPtr pScrn = crtc->scrn;
2446 #if !NOUVEAU_EXA_PIXMAPS
2447         ScreenPtr pScreen = pScrn->pScreen;
2448 #endif /* !NOUVEAU_EXA_PIXMAPS */
2449         NVPtr pNv = NVPTR(pScrn);
2450         void *offset;
2451
2452         unsigned long rotate_pitch;
2453         int size, align = 64;
2454
2455         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2456         size = rotate_pitch * height;
2457
2458         assert(nv_crtc->shadow == NULL);
2459 #if NOUVEAU_EXA_PIXMAPS
2460         if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN,
2461                         align, size, &nv_crtc->shadow)) {
2462                 ErrorF("Failed to allocate memory for shadow buffer!\n");
2463                 return NULL;
2464         }
2465
2466         if (nv_crtc->shadow && nouveau_bo_map(nv_crtc->shadow, NOUVEAU_BO_RDWR)) {
2467                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2468                                 "Failed to map shadow buffer.\n");
2469                 return NULL;
2470         }
2471
2472         offset = nv_crtc->shadow->map;
2473 #else
2474         nv_crtc->shadow = exaOffscreenAlloc(pScreen, size, align, TRUE, NULL, NULL);
2475         if (nv_crtc->shadow == NULL) {
2476                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2477                         "Couldn't allocate shadow memory for rotated CRTC\n");
2478                 return NULL;
2479         }
2480         offset = pNv->FB->map + nv_crtc->shadow->offset;
2481 #endif /* NOUVEAU_EXA_PIXMAPS */
2482
2483         return offset;
2484 }
2485
2486 /**
2487  * Creates a pixmap for this CRTC's rotated shadow framebuffer.
2488  */
2489 static PixmapPtr
2490 nv_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
2491 {
2492         ErrorF("nv_crtc_shadow_create is called\n");
2493         ScrnInfoPtr pScrn = crtc->scrn;
2494 #if NOUVEAU_EXA_PIXMAPS
2495         ScreenPtr pScreen = pScrn->pScreen;
2496         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2497 #endif /* NOUVEAU_EXA_PIXMAPS */
2498         unsigned long rotate_pitch;
2499         PixmapPtr rotate_pixmap;
2500 #if NOUVEAU_EXA_PIXMAPS
2501         struct nouveau_pixmap *nvpix;
2502 #endif /* NOUVEAU_EXA_PIXMAPS */
2503
2504         if (!data)
2505                 data = crtc->funcs->shadow_allocate (crtc, width, height);
2506
2507         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
2508
2509 #if NOUVEAU_EXA_PIXMAPS
2510         /* Create a dummy pixmap, to get a private that will be accepted by the system.*/
2511         rotate_pixmap = pScreen->CreatePixmap(pScreen,
2512                                                                 0, /* width */
2513                                                                 0, /* height */
2514         #ifdef CREATE_PIXMAP_USAGE_SCRATCH /* there seems to have been no api bump */
2515                                                                 pScrn->depth,
2516                                                                 0);
2517         #else
2518                                                                 pScrn->depth);
2519         #endif /* CREATE_PIXMAP_USAGE_SCRATCH */
2520 #else
2521         rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen,
2522                                                                 width, height,
2523                                                                 pScrn->depth,
2524                                                                 pScrn->bitsPerPixel,
2525                                                                 rotate_pitch,
2526                                                                 data);
2527 #endif /* NOUVEAU_EXA_PIXMAPS */
2528
2529         if (rotate_pixmap == NULL) {
2530                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2531                         "Couldn't allocate shadow pixmap for rotated CRTC\n");
2532         }
2533
2534 #if NOUVEAU_EXA_PIXMAPS
2535         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2536         if (!nvpix) {
2537                 ErrorF("No shadow private, stage 1\n");
2538         } else {
2539                 nvpix->bo = nv_crtc->shadow;
2540                 nvpix->mapped = TRUE;
2541         }
2542
2543         /* Modify the pixmap to actually be the one we need. */
2544         pScreen->ModifyPixmapHeader(rotate_pixmap,
2545                                         width,
2546                                         height,
2547                                         pScrn->depth,
2548                                         pScrn->bitsPerPixel,
2549                                         rotate_pitch,
2550                                         data);
2551
2552         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
2553         if (!nvpix || !nvpix->bo)
2554                 ErrorF("No shadow private, stage 2\n");
2555 #endif /* NOUVEAU_EXA_PIXMAPS */
2556
2557         return rotate_pixmap;
2558 }
2559
2560 static void
2561 nv_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
2562 {
2563         ErrorF("nv_crtc_shadow_destroy is called\n");
2564         ScrnInfoPtr pScrn = crtc->scrn;
2565         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2566         ScreenPtr pScreen = pScrn->pScreen;
2567
2568         if (rotate_pixmap) { /* This should also unmap the buffer object if relevant. */
2569                 pScreen->DestroyPixmap(rotate_pixmap);
2570         }
2571
2572 #if !NOUVEAU_EXA_PIXMAPS
2573         if (data && nv_crtc->shadow) {
2574                 exaOffscreenFree(pScreen, nv_crtc->shadow);
2575         }
2576 #endif /* !NOUVEAU_EXA_PIXMAPS */
2577
2578         nv_crtc->shadow = NULL;
2579 }
2580
2581 /* NV04-NV10 doesn't support alpha cursors */
2582 static const xf86CrtcFuncsRec nv_crtc_funcs = {
2583         .dpms = nv_crtc_dpms,
2584         .save = nv_crtc_save, /* XXX */
2585         .restore = nv_crtc_restore, /* XXX */
2586         .mode_fixup = nv_crtc_mode_fixup,
2587         .mode_set = nv_crtc_mode_set,
2588         .prepare = nv_crtc_prepare,
2589         .commit = nv_crtc_commit,
2590         .destroy = NULL, /* XXX */
2591         .lock = nv_crtc_lock,
2592         .unlock = nv_crtc_unlock,
2593         .set_cursor_colors = nv_crtc_set_cursor_colors,
2594         .set_cursor_position = nv_crtc_set_cursor_position,
2595         .show_cursor = nv_crtc_show_cursor,
2596         .hide_cursor = nv_crtc_hide_cursor,
2597         .load_cursor_image = nv_crtc_load_cursor_image,
2598         .gamma_set = nv_crtc_gamma_set,
2599         .shadow_create = nv_crtc_shadow_create,
2600         .shadow_allocate = nv_crtc_shadow_allocate,
2601         .shadow_destroy = nv_crtc_shadow_destroy,
2602 };
2603
2604 /* NV11 and up has support for alpha cursors. */
2605 /* Due to different maximum sizes we cannot allow it to use normal cursors */
2606 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
2607         .dpms = nv_crtc_dpms,
2608         .save = nv_crtc_save, /* XXX */
2609         .restore = nv_crtc_restore, /* XXX */
2610         .mode_fixup = nv_crtc_mode_fixup,
2611         .mode_set = nv_crtc_mode_set,
2612         .prepare = nv_crtc_prepare,
2613         .commit = nv_crtc_commit,
2614         .destroy = NULL, /* XXX */
2615         .lock = nv_crtc_lock,
2616         .unlock = nv_crtc_unlock,
2617         .set_cursor_colors = NULL, /* Alpha cursors do not need this */
2618         .set_cursor_position = nv_crtc_set_cursor_position,
2619         .show_cursor = nv_crtc_show_cursor,
2620         .hide_cursor = nv_crtc_hide_cursor,
2621         .load_cursor_argb = nv_crtc_load_cursor_argb,
2622         .gamma_set = nv_crtc_gamma_set,
2623         .shadow_create = nv_crtc_shadow_create,
2624         .shadow_allocate = nv_crtc_shadow_allocate,
2625         .shadow_destroy = nv_crtc_shadow_destroy,
2626 };
2627
2628
2629 void
2630 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
2631 {
2632         NVPtr pNv = NVPTR(pScrn);
2633         xf86CrtcPtr crtc;
2634         NVCrtcPrivatePtr nv_crtc;
2635
2636         if (pNv->NVArch >= 0x11) {
2637                 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
2638         } else {
2639                 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
2640         }
2641         if (crtc == NULL)
2642                 return;
2643
2644         nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
2645         nv_crtc->head = crtc_num;
2646         nv_crtc->last_dpms = NV_DPMS_CLEARED;
2647         pNv->fp_regs_owner[nv_crtc->head] = nv_crtc->head;
2648
2649         crtc->driver_private = nv_crtc;
2650
2651         NVCrtcLockUnlock(crtc, FALSE);
2652 }
2653
2654 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2655 {
2656         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2657         int i;
2658         NVCrtcRegPtr regp;
2659
2660         regp = &state->crtc_reg[nv_crtc->head];
2661
2662         NVWriteMiscOut(crtc, regp->MiscOutReg);
2663
2664         for (i = 1; i < 5; i++)
2665                 NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
2666
2667         /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
2668         NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
2669
2670         for (i = 0; i < 25; i++)
2671                 NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
2672
2673         for (i = 0; i < 9; i++)
2674                 NVWriteVgaGr(crtc, i, regp->Graphics[i]);
2675
2676         NVEnablePalette(crtc);
2677         for (i = 0; i < 21; i++)
2678                 NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
2679
2680         NVDisablePalette(crtc);
2681 }
2682
2683 static void nv_crtc_fix_nv40_hw_cursor(xf86CrtcPtr crtc)
2684 {
2685         /* TODO - implement this properly */
2686         ScrnInfoPtr pScrn = crtc->scrn;
2687         NVPtr pNv = NVPTR(pScrn);
2688
2689         if (pNv->Architecture == NV_ARCH_40) {  /* HW bug */
2690                 volatile uint32_t curpos = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_CURSOR_POS);
2691                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_CURSOR_POS, curpos);
2692         }
2693 }
2694 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override)
2695 {
2696         ScrnInfoPtr pScrn = crtc->scrn;
2697         NVPtr pNv = NVPTR(pScrn);
2698         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2699         NVCrtcRegPtr regp;
2700         int i;
2701
2702         regp = &state->crtc_reg[nv_crtc->head];
2703
2704         if (pNv->Architecture >= NV_ARCH_10) {
2705                 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
2706                 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
2707                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
2708                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
2709                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2710                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2711                 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2712                 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2713                 nvWriteMC(pNv, 0x1588, 0);
2714
2715                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
2716                 NVCrtcWriteCRTC(crtc, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
2717                 NVCrtcWriteCRTC(crtc, NV_CRTC_0830, regp->unk830);
2718                 NVCrtcWriteCRTC(crtc, NV_CRTC_0834, regp->unk834);
2719                 if (pNv->Architecture == NV_ARCH_40) {
2720                         NVCrtcWriteCRTC(crtc, NV_CRTC_0850, regp->unk850);
2721                         NVCrtcWriteCRTC(crtc, NV_CRTC_081C, regp->unk81c);
2722                 }
2723
2724                 if (pNv->Architecture == NV_ARCH_40) {
2725                         uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
2726                         if (regp->config == 0x2) { /* enhanced "horizontal only" non-vga mode */
2727                                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 | 0x10000);
2728                         } else {
2729                                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
2730                         }
2731                 }
2732         }
2733
2734         NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, regp->config);
2735         NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO, regp->gpio);
2736
2737         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
2738         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
2739         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
2740         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
2741         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
2742         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
2743         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
2744         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
2745         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
2746         if (pNv->Architecture >= NV_ARCH_30)
2747                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
2748
2749         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
2750         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
2751         nv_crtc_fix_nv40_hw_cursor(crtc);
2752         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
2753         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
2754
2755         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
2756         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
2757         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3C, regp->CRTC[NV_VGA_CRTCX_3C]);
2758         if (pNv->Architecture >= NV_ARCH_10) {
2759                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
2760                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_43, regp->CRTC[NV_VGA_CRTCX_43]);
2761                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
2762                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_4B, regp->CRTC[NV_VGA_CRTCX_4B]);
2763                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
2764         }
2765         /* NV11 and NV20 stop at 0x52. */
2766         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
2767                 if (override)
2768                         for (i = 0; i < 0x10; i++)
2769                                 NVWriteVGACR5758(pNv, nv_crtc->head, i, regp->CR58[i]);
2770
2771                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
2772                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
2773
2774                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
2775
2776                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_85, regp->CRTC[NV_VGA_CRTCX_85]);
2777                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_86, regp->CRTC[NV_VGA_CRTCX_86]);
2778         }
2779
2780         /* Setting 1 on this value gives you interrupts for every vblank period. */
2781         NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_EN_0, 0);
2782         NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
2783
2784         pNv->CurrentState = state;
2785 }
2786
2787 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2788 {
2789         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2790         int i;
2791         NVCrtcRegPtr regp;
2792
2793         regp = &state->crtc_reg[nv_crtc->head];
2794
2795         regp->MiscOutReg = NVReadMiscOut(crtc);
2796
2797         for (i = 0; i < 25; i++)
2798                 regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
2799
2800         NVEnablePalette(crtc);
2801         for (i = 0; i < 21; i++)
2802                 regp->Attribute[i] = NVReadVgaAttr(crtc, i);
2803         NVDisablePalette(crtc);
2804
2805         for (i = 0; i < 9; i++)
2806                 regp->Graphics[i] = NVReadVgaGr(crtc, i);
2807
2808         for (i = 1; i < 5; i++)
2809                 regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
2810 }
2811
2812 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2813 {
2814         ScrnInfoPtr pScrn = crtc->scrn;
2815         NVPtr pNv = NVPTR(pScrn);
2816         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2817         NVCrtcRegPtr regp;
2818         int i;
2819
2820         regp = &state->crtc_reg[nv_crtc->head];
2821
2822         regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
2823         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
2824         regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
2825         regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
2826         regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
2827         regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
2828         regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
2829
2830         regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
2831         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
2832         regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
2833         if (pNv->Architecture >= NV_ARCH_30)
2834                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
2835         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
2836         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
2837         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
2838         regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
2839
2840         if (pNv->Architecture >= NV_ARCH_10) {
2841                 regp->unk830 = NVCrtcReadCRTC(crtc, NV_CRTC_0830);
2842                 regp->unk834 = NVCrtcReadCRTC(crtc, NV_CRTC_0834);
2843                 if (pNv->Architecture == NV_ARCH_40) {
2844                         regp->unk850 = NVCrtcReadCRTC(crtc, NV_CRTC_0850);
2845                         regp->unk81c = NVCrtcReadCRTC(crtc, NV_CRTC_081C);
2846                 }
2847                 if (pNv->twoHeads) {
2848                         regp->head = NVCrtcReadCRTC(crtc, NV_CRTC_FSEL);
2849                         regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
2850                 }
2851                 regp->cursorConfig = NVCrtcReadCRTC(crtc, NV_CRTC_CURSOR_CONFIG);
2852         }
2853
2854         regp->gpio = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO);
2855         regp->config = NVCrtcReadCRTC(crtc, NV_CRTC_CONFIG);
2856
2857         regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
2858         regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
2859         regp->CRTC[NV_VGA_CRTCX_3C] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3C);
2860         if (pNv->Architecture >= NV_ARCH_10) {
2861                 regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
2862                 regp->CRTC[NV_VGA_CRTCX_43] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_43);
2863                 regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
2864                 regp->CRTC[NV_VGA_CRTCX_4B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_4B);
2865                 regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
2866         }
2867         /* NV11 and NV20 don't have this, they stop at 0x52. */
2868         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
2869                 for (i = 0; i < 0x10; i++)
2870                         regp->CR58[i] = NVReadVGACR5758(pNv, nv_crtc->head, i);
2871
2872                 regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
2873                 regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
2874                 regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
2875
2876                 regp->CRTC[NV_VGA_CRTCX_85] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_85);
2877                 regp->CRTC[NV_VGA_CRTCX_86] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_86);
2878         }
2879 }
2880
2881 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2882 {
2883         ScrnInfoPtr pScrn = crtc->scrn;
2884         NVPtr pNv = NVPTR(pScrn);
2885         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2886         NVCrtcRegPtr regp;
2887         int i;
2888
2889         regp = &state->crtc_reg[nv_crtc->head];
2890
2891         regp->general = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL);
2892
2893         regp->fp_control[0]     = NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL);
2894         regp->debug_0[0]        = NVReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
2895
2896         if (pNv->twoHeads) {
2897                 regp->fp_control[1]     = NVReadRAMDAC(pNv, 1, NV_RAMDAC_FP_CONTROL);
2898                 regp->debug_0[1]        = NVReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
2899
2900                 regp->debug_1   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1);
2901                 regp->debug_2   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2);
2902
2903                 regp->unk_a20 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A20);
2904                 regp->unk_a24 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A24);
2905                 regp->unk_a34 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A34);
2906         }
2907
2908         if (pNv->NVArch == 0x11) {
2909                 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_DITHER_NV11);
2910         } else if (pNv->twoHeads) {
2911                 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DITHER);
2912         }
2913         if (pNv->Architecture >= NV_ARCH_10)
2914                 regp->nv10_cursync = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC);
2915
2916         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2917
2918         for (i = 0; i < 7; i++) {
2919                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2920                 regp->fp_horiz_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
2921         }
2922
2923         for (i = 0; i < 7; i++) {
2924                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2925                 regp->fp_vert_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
2926         }
2927
2928         regp->fp_hvalid_start = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_HVALID_START);
2929         regp->fp_hvalid_end = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_HVALID_END);
2930         regp->fp_vvalid_start = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_VVALID_START);
2931         regp->fp_vvalid_end = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_VVALID_END);
2932 }
2933
2934 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2935 {
2936         ScrnInfoPtr pScrn = crtc->scrn;
2937         NVPtr pNv = NVPTR(pScrn);
2938         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2939         NVCrtcRegPtr regp;
2940         int i;
2941
2942         regp = &state->crtc_reg[nv_crtc->head];
2943
2944         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL, regp->general);
2945
2946         if (pNv->fp_regs_owner[0] == nv_crtc->head) {
2947                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_FP_CONTROL, regp->fp_control[0]);
2948                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0, regp->debug_0[0]);
2949         }
2950         if (pNv->twoHeads) {
2951                 if (pNv->fp_regs_owner[1] == nv_crtc->head) {
2952                         NVWriteRAMDAC(pNv, 1, NV_RAMDAC_FP_CONTROL, regp->fp_control[1]);
2953                         NVWriteRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0, regp->debug_0[1]);
2954                 }
2955                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
2956                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
2957                 if (pNv->NVArch == 0x30) { /* For unknown purposes. */
2958                         uint32_t reg890 = NVCrtcReadRAMDAC(crtc, NV30_RAMDAC_890);
2959                         NVCrtcWriteRAMDAC(crtc, NV30_RAMDAC_89C, reg890);
2960                 }
2961
2962                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A20, regp->unk_a20);
2963                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A24, regp->unk_a24);
2964                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A34, regp->unk_a34);
2965         }
2966
2967         if (pNv->NVArch == 0x11) {
2968                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_DITHER_NV11, regp->dither);
2969         } else if (pNv->twoHeads) {
2970                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DITHER, regp->dither);
2971         }
2972         if (pNv->Architecture >= NV_ARCH_10)
2973                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
2974
2975         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2976
2977         for (i = 0; i < 7; i++) {
2978                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2979                 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_horiz_regs[i]);
2980         }
2981
2982         for (i = 0; i < 7; i++) {
2983                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2984                 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_vert_regs[i]);
2985         }
2986
2987         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_HVALID_START, regp->fp_hvalid_start);
2988         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_HVALID_END, regp->fp_hvalid_end);
2989         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_VVALID_START, regp->fp_vvalid_start);
2990         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_VVALID_END, regp->fp_vvalid_end);
2991 }
2992
2993 void
2994 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y, Bool bios_restore)
2995 {
2996         ScrnInfoPtr pScrn = crtc->scrn;
2997         NVPtr pNv = NVPTR(pScrn);
2998         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2999         NVFBLayout *pLayout = &pNv->CurrentLayout;
3000         uint32_t start = 0;
3001
3002         ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
3003
3004         if (bios_restore) {
3005                 start = pNv->console_mode[nv_crtc->head].fb_start;
3006         } else {
3007                 start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
3008                 if (crtc->rotatedData != NULL) { /* we do not exist on the real framebuffer */
3009 #if NOUVEAU_EXA_PIXMAPS
3010                         start = nv_crtc->shadow->offset;
3011 #else
3012                         start = pNv->FB->offset + nv_crtc->shadow->offset; /* We do exist relative to the framebuffer */
3013 #endif
3014                 } else {
3015                         start += pNv->FB->offset;
3016                 }
3017         }
3018
3019         /* 30 bits addresses in 32 bits according to haiku */
3020         NVCrtcWriteCRTC(crtc, NV_CRTC_START, start & 0xfffffffc);
3021
3022         /* set NV4/NV10 byte adress: (bit0 - 1) */
3023         NVWriteVgaAttr(crtc, 0x13, (start & 0x3) << 1);
3024
3025         crtc->x = x;
3026         crtc->y = y;
3027 }
3028
3029 static void NVCrtcWriteDacMask(xf86CrtcPtr crtc, uint8_t value)
3030 {
3031         ScrnInfoPtr pScrn = crtc->scrn;
3032         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3033         NVPtr pNv = NVPTR(pScrn);
3034         volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3035
3036         DDXMMIOH("NVCrtcWriteDacMask: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_MASK, value);
3037         NV_WR08(pDACReg, VGA_DAC_MASK, value);
3038 }
3039
3040 static uint8_t NVCrtcReadDacMask(xf86CrtcPtr crtc)
3041 {
3042         ScrnInfoPtr pScrn = crtc->scrn;
3043         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3044         NVPtr pNv = NVPTR(pScrn);
3045         volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3046
3047         DDXMMIOH("NVCrtcReadDacMask: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_MASK, NV_RD08(pDACReg, VGA_DAC_MASK));
3048         return NV_RD08(pDACReg, VGA_DAC_MASK);
3049 }
3050
3051 static void NVCrtcWriteDacReadAddr(xf86CrtcPtr crtc, uint8_t value)
3052 {
3053         ScrnInfoPtr pScrn = crtc->scrn;
3054         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3055         NVPtr pNv = NVPTR(pScrn);
3056         volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3057
3058         DDXMMIOH("NVCrtcWriteDacReadAddr: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_READ_ADDR, value);
3059         NV_WR08(pDACReg, VGA_DAC_READ_ADDR, value);
3060 }
3061
3062 static void NVCrtcWriteDacWriteAddr(xf86CrtcPtr crtc, uint8_t value)
3063 {
3064         ScrnInfoPtr pScrn = crtc->scrn;
3065         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3066         NVPtr pNv = NVPTR(pScrn);
3067         volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3068
3069         DDXMMIOH("NVCrtcWriteDacWriteAddr: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_WRITE_ADDR, value);
3070         NV_WR08(pDACReg, VGA_DAC_WRITE_ADDR, value);
3071 }
3072
3073 static void NVCrtcWriteDacData(xf86CrtcPtr crtc, uint8_t value)
3074 {
3075         ScrnInfoPtr pScrn = crtc->scrn;
3076         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3077         NVPtr pNv = NVPTR(pScrn);
3078         volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3079
3080         DDXMMIOH("NVCrtcWriteDacData: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_DATA, value);
3081         NV_WR08(pDACReg, VGA_DAC_DATA, value);
3082 }
3083
3084 static uint8_t NVCrtcReadDacData(xf86CrtcPtr crtc, uint8_t value)
3085 {
3086         ScrnInfoPtr pScrn = crtc->scrn;
3087         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3088         NVPtr pNv = NVPTR(pScrn);
3089         volatile uint8_t *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
3090
3091         DDXMMIOH("NVCrtcReadDacData: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_DATA, NV_RD08(pDACReg, VGA_DAC_DATA));
3092         return NV_RD08(pDACReg, VGA_DAC_DATA);
3093 }
3094
3095 void NVCrtcLoadPalette(xf86CrtcPtr crtc)
3096 {
3097         int i;
3098         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3099         NVCrtcRegPtr regp;
3100         ScrnInfoPtr pScrn = crtc->scrn;
3101         NVPtr pNv = NVPTR(pScrn);
3102
3103         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
3104
3105         if (pNv->twoHeads)
3106                 NVCrtcSetOwner(crtc);
3107         NVCrtcWriteDacMask(crtc, 0xff);
3108         NVCrtcWriteDacWriteAddr(crtc, 0x00);
3109
3110         for (i = 0; i<768; i++) {
3111                 NVCrtcWriteDacData(crtc, regp->DAC[i]);
3112         }
3113         NVDisablePalette(crtc);
3114 }
3115
3116 /* on = unblank */
3117 void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
3118 {
3119         NVPtr pNv = NVPTR(crtc->scrn);
3120         unsigned char scrn;
3121
3122         if (pNv->twoHeads)
3123                 NVCrtcSetOwner(crtc);
3124
3125         scrn = NVReadVgaSeq(crtc, 0x01);
3126         if (on) {
3127                 scrn &= ~0x20;
3128         } else {
3129                 scrn |= 0x20;
3130         }
3131
3132         NVVgaSeqReset(crtc, TRUE);
3133         NVWriteVgaSeq(crtc, 0x01, scrn);
3134         NVVgaSeqReset(crtc, FALSE);
3135 }
3136
3137 /* Reset a mode after a drastic output resource change for example. */
3138 void NVCrtcModeFix(xf86CrtcPtr crtc)
3139 {
3140         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
3141         Bool need_unlock;
3142
3143         if (!crtc->enabled)
3144                 return;
3145
3146         if (!xf86ModesEqual(&crtc->mode, &crtc->desiredMode)) /* not currently in X */
3147                 return;
3148
3149         DisplayModePtr adjusted_mode = xf86DuplicateMode(&crtc->mode);
3150         uint8_t dpms_mode = nv_crtc->last_dpms;
3151
3152         /* Set the crtc mode again. */
3153         crtc->funcs->dpms(crtc, DPMSModeOff);
3154         need_unlock = crtc->funcs->lock(crtc);
3155         crtc->funcs->mode_fixup(crtc, &crtc->mode, adjusted_mode);
3156         crtc->funcs->prepare(crtc);
3157         crtc->funcs->mode_set(crtc, &crtc->mode, adjusted_mode, crtc->x, crtc->y);
3158         crtc->funcs->commit(crtc);
3159         if (need_unlock)
3160                 crtc->funcs->unlock(crtc);
3161         crtc->funcs->dpms(crtc, dpms_mode);
3162
3163         /* Free mode. */
3164         xfree(adjusted_mode);
3165 }
3166
3167 /*************************************************************************** \
3168 |*                                                                           *|
3169 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
3170 |*                                                                           *|
3171 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
3172 |*     international laws.  Users and possessors of this source code are     *|
3173 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
3174 |*     use this code in individual and commercial software.                  *|
3175 |*                                                                           *|
3176 |*     Any use of this source code must include,  in the user documenta-     *|
3177 |*     tion and  internal comments to the code,  notices to the end user     *|
3178 |*     as follows:                                                           *|
3179 |*                                                                           *|
3180 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
3181 |*                                                                           *|
3182 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
3183 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
3184 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
3185 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
3186 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
3187 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
3188 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
3189 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
3190 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
3191 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
3192 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
3193 |*                                                                           *|
3194 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
3195 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
3196 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
3197 |*     computer  software  documentation,"  as such  terms  are  used in     *|
3198 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
3199 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
3200 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
3201 |*     all U.S. Government End Users  acquire the source code  with only     *|
3202 |*     those rights set forth herein.                                        *|
3203 |*                                                                           *|
3204  \***************************************************************************/