1 /***************************************************************************\
3 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
5 |* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6 |* international laws. Users and possessors of this source code are *|
7 |* hereby granted a nonexclusive, royalty-free copyright license to *|
8 |* use this code in individual and commercial software. *|
10 |* Any use of this source code must include, in the user documenta- *|
11 |* tion and internal comments to the code, notices to the end user *|
14 |* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
16 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19 |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21 |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
24 |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25 |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26 |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
28 |* U.S. Government End Users. This source code is a "commercial *|
29 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30 |* consisting of "commercial computer software" and "commercial *|
31 |* computer software documentation," as such terms are used in *|
32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33 |* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35 |* all U.S. Government End Users acquire the source code with only *|
36 |* those rights set forth herein. *|
38 \***************************************************************************/
39 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_hw.c,v 1.21 2006/06/16 00:19:33 mvojkovi Exp $ */
41 #include "nv_include.h"
45 uint8_t nvReadVGA(NVPtr pNv, uint8_t index)
47 volatile const uint8_t *ptr = pNv->cur_head ? pNv->PCIO1 : pNv->PCIO0;
48 VGA_WR08(ptr, 0x03D4, index);
49 return VGA_RD08(ptr, 0x03D5);
52 void nvWriteVGA(NVPtr pNv, uint8_t index, uint8_t data)
54 volatile const uint8_t *ptr = pNv->cur_head ? pNv->PCIO1 : pNv->PCIO0;
55 VGA_WR08(ptr, 0x03D4, index);
56 VGA_WR08(ptr, 0x03D5, data);
59 CARD32 nvReadRAMDAC(NVPtr pNv, uint8_t head, uint32_t ramdac_reg)
61 volatile const void *ptr = head ? pNv->PRAMDAC1 : pNv->PRAMDAC0;
62 return MMIO_IN32(ptr, ramdac_reg);
65 void nvWriteRAMDAC(NVPtr pNv, uint8_t head, uint32_t ramdac_reg, CARD32 val)
67 volatile const void *ptr = head ? pNv->PRAMDAC1 : pNv->PRAMDAC0;
68 MMIO_OUT32(ptr, ramdac_reg, val);
71 CARD32 nvReadCRTC(NVPtr pNv, uint8_t head, uint32_t reg)
73 volatile const void *ptr = head ? pNv->PCRTC1 : pNv->PCRTC0;
74 return MMIO_IN32(ptr, reg);
77 void nvWriteCRTC(NVPtr pNv, uint8_t head, uint32_t reg, CARD32 val)
79 volatile const void *ptr = head ? pNv->PCRTC1 : pNv->PCRTC0;
80 MMIO_OUT32(ptr, reg, val);
90 nvWriteVGA(pNv, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57 );
92 cr11 = nvReadVGA(pNv, NV_VGA_CRTCX_VSYNCE);
93 if(Lock) cr11 |= 0x80;
95 nvWriteVGA(pNv, NV_VGA_CRTCX_VSYNCE, cr11);
98 int NVShowHideCursor (
103 int current = pNv->CurrentState->cursor1;
105 pNv->CurrentState->cursor1 = (pNv->CurrentState->cursor1 & 0xFE) |
108 nvWriteVGA(pNv, NV_VGA_CRTCX_CURCTL1, pNv->CurrentState->cursor1);
110 if(pNv->Architecture == NV_ARCH_40) { /* HW bug */
111 volatile CARD32 curpos = nvReadCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS);
112 nvWriteCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS, curpos);
115 return (current & 0x01);
118 /****************************************************************************\
120 * The video arbitration routines calculate some "magic" numbers. Fixes *
121 * the snow seen when accessing the framebuffer without it. *
122 * It just works (I hope). *
124 \****************************************************************************/
129 int graphics_burst_size;
130 int video_burst_size;
151 int graphics_burst_size;
152 int video_burst_size;
172 static void nvGetClocks(NVPtr pNv, unsigned int *MClk, unsigned int *NVClk)
174 unsigned int pll, N, M, MB, NB, P;
176 if(pNv->Architecture >= NV_ARCH_40) {
177 pll = nvReadMC(pNv, 0x4020);
178 P = (pll >> 16) & 0x07;
179 pll = nvReadMC(pNv, 0x4024);
181 N = (pll >> 8) & 0xFF;
182 if(((pNv->Chipset & 0xfff0) == CHIPSET_G71) ||
183 ((pNv->Chipset & 0xfff0) == CHIPSET_G73))
188 MB = (pll >> 16) & 0xFF;
189 NB = (pll >> 24) & 0xFF;
191 *MClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
193 pll = nvReadMC(pNv, 0x4000);
194 P = (pll >> 16) & 0x07;
195 pll = nvReadMC(pNv, 0x4004);
197 N = (pll >> 8) & 0xFF;
198 MB = (pll >> 16) & 0xFF;
199 NB = (pll >> 24) & 0xFF;
201 *NVClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
203 if(pNv->twoStagePLL) {
204 pll = nvReadRAMDAC0(pNv, NV_RAMDAC_MPLL);
206 N = (pll >> 8) & 0xFF;
207 P = (pll >> 16) & 0x0F;
208 pll = nvReadRAMDAC0(pNv, NV_RAMDAC_MPLL_B);
209 if(pll & 0x80000000) {
211 NB = (pll >> 8) & 0xFF;
216 *MClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
218 pll = nvReadRAMDAC0(pNv, NV_RAMDAC_NVPLL);
220 N = (pll >> 8) & 0xFF;
221 P = (pll >> 16) & 0x0F;
222 pll = nvReadRAMDAC0(pNv, NV_RAMDAC_NVPLL_B);
223 if(pll & 0x80000000) {
225 NB = (pll >> 8) & 0xFF;
230 *NVClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
232 if(((pNv->Chipset & 0x0ff0) == CHIPSET_NV30) ||
233 ((pNv->Chipset & 0x0ff0) == CHIPSET_NV35))
235 pll = nvReadRAMDAC0(pNv, NV_RAMDAC_MPLL);
237 N = (pll >> 8) & 0xFF;
238 P = (pll >> 16) & 0x07;
239 if(pll & 0x00000080) {
240 MB = (pll >> 4) & 0x07;
241 NB = (pll >> 19) & 0x1f;
246 *MClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
248 pll = nvReadRAMDAC0(pNv, NV_RAMDAC_NVPLL);
250 N = (pll >> 8) & 0xFF;
251 P = (pll >> 16) & 0x07;
252 if(pll & 0x00000080) {
253 MB = (pll >> 4) & 0x07;
254 NB = (pll >> 19) & 0x1f;
259 *NVClk = ((N * NB * pNv->CrystalFreqKHz) / (M * MB)) >> P;
261 pll = nvReadRAMDAC0(pNv, NV_RAMDAC_MPLL);
263 N = (pll >> 8) & 0xFF;
264 P = (pll >> 16) & 0x0F;
265 *MClk = (N * pNv->CrystalFreqKHz / M) >> P;
267 pll = nvReadRAMDAC0(pNv, NV_RAMDAC_NVPLL);
269 N = (pll >> 8) & 0xFF;
270 P = (pll >> 16) & 0x0F;
271 *NVClk = (N * pNv->CrystalFreqKHz / M) >> P;
275 ErrorF("NVClock = %i MHz, MEMClock = %i MHz\n", *NVClk/1000, *MClk/1000);
280 void nv4CalcArbitration (
285 int data, pagemiss, cas,width, video_enable, bpp;
286 int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
287 int found, mclk_extra, mclk_loop, cbs, m1, p1;
288 int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
289 int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate;
290 int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt,clwm;
293 pclk_freq = arb->pclk_khz;
294 mclk_freq = arb->mclk_khz;
295 nvclk_freq = arb->nvclk_khz;
296 pagemiss = arb->mem_page_miss;
297 cas = arb->mem_latency;
298 width = arb->memory_width >> 6;
299 video_enable = arb->enable_video;
301 mp_enable = arb->enable_mp;
332 mclk_loop = mclks+mclk_extra;
333 us_m = mclk_loop *1000*1000 / mclk_freq;
334 us_n = nvclks*1000*1000 / nvclk_freq;
335 us_p = nvclks*1000*1000 / pclk_freq;
338 video_drain_rate = pclk_freq * 2;
339 crtc_drain_rate = pclk_freq * bpp/8;
343 vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq;
344 if (nvclk_freq * 2 > mclk_freq * width)
345 video_fill_us = cbs*1000*1000 / 16 / nvclk_freq ;
347 video_fill_us = cbs*1000*1000 / (8 * width) / mclk_freq;
348 us_video = vpm_us + us_m + us_n + us_p + video_fill_us;
349 vlwm = us_video * video_drain_rate/(1000*1000);
352 if (vlwm > 128) vbs = 64;
353 if (vlwm > (256-64)) vbs = 32;
354 if (nvclk_freq * 2 > mclk_freq * width)
355 video_fill_us = vbs *1000*1000/ 16 / nvclk_freq ;
357 video_fill_us = vbs*1000*1000 / (8 * width) / mclk_freq;
358 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
365 clwm = us_crt * crtc_drain_rate/(1000*1000);
370 crtc_drain_rate = pclk_freq * bpp/8;
373 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
374 us_crt = cpm_us + us_m + us_n + us_p ;
375 clwm = us_crt * crtc_drain_rate/(1000*1000);
378 m1 = clwm + cbs - 512;
379 p1 = m1 * pclk_freq / mclk_freq;
381 if ((p1 < m1) && (m1 > 0))
385 if (mclk_extra ==0) found = 1;
388 else if (video_enable)
390 if ((clwm > 511) || (vlwm > 255))
394 if (mclk_extra ==0) found = 1;
404 if (mclk_extra ==0) found = 1;
408 if (clwm < 384) clwm = 384;
409 if (vlwm < 128) vlwm = 128;
411 fifo->graphics_lwm = data;
412 fifo->graphics_burst_size = 128;
413 data = (int)((vlwm+15));
414 fifo->video_lwm = data;
415 fifo->video_burst_size = vbs;
419 void nv4UpdateArbitrationSettings (
427 nv4_fifo_info fifo_data;
428 nv4_sim_state sim_data;
429 unsigned int MClk, NVClk, cfg1;
431 nvGetClocks(pNv, &MClk, &NVClk);
433 cfg1 = nvReadFB(pNv, NV_PFB_CFG1);
434 sim_data.pix_bpp = (char)pixelDepth;
435 sim_data.enable_video = 0;
436 sim_data.enable_mp = 0;
437 sim_data.memory_width = (nvReadEXTDEV(pNv, 0x0000) & 0x10) ? 128 : 64;
438 sim_data.mem_latency = (char)cfg1 & 0x0F;
439 sim_data.mem_aligned = 1;
440 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01));
441 sim_data.gr_during_vid = 0;
442 sim_data.pclk_khz = VClk;
443 sim_data.mclk_khz = MClk;
444 sim_data.nvclk_khz = NVClk;
445 nv4CalcArbitration(&fifo_data, &sim_data);
448 int b = fifo_data.graphics_burst_size >> 4;
450 while (b >>= 1) (*burst)++;
451 *lwm = fifo_data.graphics_lwm >> 3;
455 void nv10CalcArbitration (
456 nv10_fifo_info *fifo,
460 int data, pagemiss, width, video_enable, bpp;
461 int nvclks, mclks, pclks, vpagemiss, crtpagemiss;
463 int found, mclk_extra, mclk_loop, cbs, m1;
464 int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
465 int us_m, us_m_min, us_n, us_p, crtc_drain_rate;
467 int vpm_us, us_video, cpm_us, us_crt,clwm;
469 int m2us, us_pipe_min, p1clk, p2;
471 int us_min_mclk_extra;
474 pclk_freq = arb->pclk_khz; /* freq in KHz */
475 mclk_freq = arb->mclk_khz;
476 nvclk_freq = arb->nvclk_khz;
477 pagemiss = arb->mem_page_miss;
478 width = arb->memory_width/64;
479 video_enable = arb->enable_video;
481 mp_enable = arb->enable_mp;
486 pclks = 4; /* lwm detect. */
488 nvclks = 3; /* lwm -> sync. */
489 nvclks += 2; /* fbi bus cycles (1 req + 1 busy) */
491 mclks = 1; /* 2 edge sync. may be very close to edge so just put one. */
493 mclks += 1; /* arb_hp_req */
494 mclks += 5; /* ap_hp_req tiling pipeline */
496 mclks += 2; /* tc_req latency fifo */
497 mclks += 2; /* fb_cas_n_ memory request to fbio block */
498 mclks += 7; /* sm_d_rdv data returned from fbio block */
500 /* fb.rd.d.Put_gc need to accumulate 256 bits for read */
501 if (arb->memory_type == 0)
502 if (arb->memory_width == 64) /* 64 bit bus */
507 if (arb->memory_width == 64) /* 64 bit bus */
512 if ((!video_enable) && (arb->memory_width == 128))
514 mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */
519 mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */
520 /* mclk_extra = 4; */ /* Margin of error */
524 nvclks += 1; /* 2 edge sync. may be very close to edge so just put one. */
525 nvclks += 1; /* fbi_d_rdv_n */
526 nvclks += 1; /* Fbi_d_rdata */
527 nvclks += 1; /* crtfifo load */
530 mclks+=4; /* Mp can get in with a burst of 8. */
531 /* Extra clocks determined by heuristics */
539 mclk_loop = mclks+mclk_extra;
540 us_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */
541 us_m_min = mclks * 1000*1000 / mclk_freq; /* Minimum Mclk latency in us */
542 us_min_mclk_extra = min_mclk_extra *1000*1000 / mclk_freq;
543 us_n = nvclks*1000*1000 / nvclk_freq;/* nvclk latency in us */
544 us_p = pclks*1000*1000 / pclk_freq;/* nvclk latency in us */
545 us_pipe_min = us_m_min + us_n + us_p;
547 vus_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */
550 crtc_drain_rate = pclk_freq * bpp/8; /* MB/s */
552 vpagemiss = 1; /* self generating page miss */
553 vpagemiss += 1; /* One higher priority before */
555 crtpagemiss = 2; /* self generating page miss */
557 crtpagemiss += 1; /* if MA0 conflict */
559 vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq;
561 us_video = vpm_us + vus_m; /* Video has separate read return path */
563 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
565 us_video /* Wait for video */
566 +cpm_us /* CRT Page miss */
567 +us_m + us_n +us_p /* other latency */
570 clwm = us_crt * crtc_drain_rate/(1000*1000);
571 clwm++; /* fixed point <= float_point - 1. Fixes that */
573 crtc_drain_rate = pclk_freq * bpp/8; /* bpp * pclk/8 */
575 crtpagemiss = 1; /* self generating page miss */
576 crtpagemiss += 1; /* MA0 page miss */
578 crtpagemiss += 1; /* if MA0 conflict */
579 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq;
580 us_crt = cpm_us + us_m + us_n + us_p ;
581 clwm = us_crt * crtc_drain_rate/(1000*1000);
582 clwm++; /* fixed point <= float_point - 1. Fixes that */
584 /* Finally, a heuristic check when width == 64 bits */
586 nvclk_fill = nvclk_freq * 8;
587 if(crtc_drain_rate * 100 >= nvclk_fill * 102)
588 clwm = 0xfff; /*Large number to fail */
590 else if(crtc_drain_rate * 100 >= nvclk_fill * 98) {
603 clwm_rnd_down = ((int)clwm/8)*8;
604 if (clwm_rnd_down < clwm)
607 m1 = clwm + cbs - 1024; /* Amount of overfill */
608 m2us = us_pipe_min + us_min_mclk_extra;
610 /* pclk cycles to drain */
611 p1clk = m2us * pclk_freq/(1000*1000);
612 p2 = p1clk * bpp / 8; /* bytes drained. */
614 if((p2 < m1) && (m1 > 0)) {
617 if(min_mclk_extra == 0) {
619 found = 1; /* Can't adjust anymore! */
621 cbs = cbs/2; /* reduce the burst size */
627 if (clwm > 1023){ /* Have some margin */
630 if(min_mclk_extra == 0)
631 found = 1; /* Can't adjust anymore! */
637 if(clwm < (1024-cbs+8)) clwm = 1024-cbs+8;
639 /* printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n", clwm, data ); */
640 fifo->graphics_lwm = data; fifo->graphics_burst_size = cbs;
642 fifo->video_lwm = 1024; fifo->video_burst_size = 512;
646 void nv10UpdateArbitrationSettings (
654 nv10_fifo_info fifo_data;
655 nv10_sim_state sim_data;
656 unsigned int MClk, NVClk, cfg1;
658 nvGetClocks(pNv, &MClk, &NVClk);
660 cfg1 = nvReadFB(pNv, NV_PFB_CFG1);
661 sim_data.pix_bpp = (char)pixelDepth;
662 sim_data.enable_video = 1;
663 sim_data.enable_mp = 0;
664 sim_data.memory_type = (nvReadFB(pNv, NV_PFB_CFG0) & 0x01) ? 1 : 0;
665 sim_data.memory_width = (nvReadEXTDEV(pNv, 0x0000) & 0x10) ? 128 : 64;
666 sim_data.mem_latency = (char)cfg1 & 0x0F;
667 sim_data.mem_aligned = 1;
668 sim_data.mem_page_miss = (char)(((cfg1>>4) &0x0F) + ((cfg1>>31) & 0x01));
669 sim_data.gr_during_vid = 0;
670 sim_data.pclk_khz = VClk;
671 sim_data.mclk_khz = MClk;
672 sim_data.nvclk_khz = NVClk;
673 nv10CalcArbitration(&fifo_data, &sim_data);
674 if (fifo_data.valid) {
675 int b = fifo_data.graphics_burst_size >> 4;
677 while (b >>= 1) (*burst)++;
678 *lwm = fifo_data.graphics_lwm >> 3;
683 void nv30UpdateArbitrationSettings (NVPtr pNv,
687 unsigned int MClk, NVClk;
688 unsigned int fifo_size, burst_size, graphics_lwm;
692 graphics_lwm = fifo_size - burst_size;
694 nvGetClocks(pNv, &MClk, &NVClk);
698 while(burst_size >>= 1) (*burst)++;
699 *lwm = graphics_lwm >> 3;
702 #ifdef XSERVER_LIBPCIACCESS
704 struct pci_device GetDeviceByPCITAG(uint32_t bus, uint32_t dev, uint32_t func)
706 const struct pci_slot_match match[] = { {0, bus, dev, func, 0} };
707 struct pci_device_iterator *iterator = pci_slot_match_iterator_create(&match);
708 /* assume one device to exist */
709 struct pci_device *device = pci_device_next(iterator);
714 #endif /* XSERVER_LIBPCIACCESS */
716 void nForceUpdateArbitrationSettings (unsigned VClk,
723 nv10_fifo_info fifo_data;
724 nv10_sim_state sim_data;
725 unsigned int M, N, P, pll, MClk, NVClk, memctrl;
727 #ifdef XSERVER_LIBPCIACCESS
728 struct pci_device tmp;
729 #endif /* XSERVER_LIBPCIACCESS */
731 if((pNv->Chipset & 0x0FF0) == CHIPSET_NFORCE) {
732 unsigned int uMClkPostDiv;
734 #ifdef XSERVER_LIBPCIACCESS
735 tmp = GetDeviceByPCITAG(0, 0, 3);
736 PCI_DEV_READ_LONG(&tmp, 0x6C, &uMClkPostDiv);
737 uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
739 uMClkPostDiv = (pciReadLong(pciTag(0, 0, 3), 0x6C) >> 8) & 0xf;
740 #endif /* XSERVER_LIBPCIACCESS */
741 if(!uMClkPostDiv) uMClkPostDiv = 4;
742 MClk = 400000 / uMClkPostDiv;
744 #ifdef XSERVER_LIBPCIACCESS
745 tmp = GetDeviceByPCITAG(0, 0, 5);
746 PCI_DEV_READ_LONG(&tmp, 0x4C, &MClk);
749 MClk = pciReadLong(pciTag(0, 0, 5), 0x4C) / 1000;
750 #endif /* XSERVER_LIBPCIACCESS */
753 pll = nvReadRAMDAC0(pNv, NV_RAMDAC_NVPLL);
754 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
755 NVClk = (N * pNv->CrystalFreqKHz / M) >> P;
756 sim_data.pix_bpp = (char)pixelDepth;
757 sim_data.enable_video = 0;
758 sim_data.enable_mp = 0;
759 #ifdef XSERVER_LIBPCIACCESS
760 tmp = GetDeviceByPCITAG(0, 0, 1);
761 PCI_DEV_READ_LONG(&tmp, 0x7C, &(sim_data.memory_type));
762 sim_data.memory_type = (sim_data.memory_type >> 12) & 1;
764 sim_data.memory_type = (pciReadLong(pciTag(0, 0, 1), 0x7C) >> 12) & 1;
765 #endif /* XSERVER_LIBPCIACCESS */
766 sim_data.memory_width = 64;
768 #ifdef XSERVER_LIBPCIACCESS
769 /* This offset is 0, is this even usefull? */
770 tmp = GetDeviceByPCITAG(0, 0, 3);
771 PCI_DEV_READ_LONG(&tmp, 0x00, &memctrl);
774 memctrl = pciReadLong(pciTag(0, 0, 3), 0x00) >> 16;
775 #endif /* XSERVER_LIBPCIACCESS */
777 if((memctrl == 0x1A9) || (memctrl == 0x1AB) || (memctrl == 0x1ED)) {
779 #ifdef XSERVER_LIBPCIACCESS
780 tmp = GetDeviceByPCITAG(0, 0, 2);
781 PCI_DEV_READ_LONG(&tmp, 0x40, &dimm[0]);
782 PCI_DEV_READ_LONG(&tmp, 0x44, &dimm[1]);
783 PCI_DEV_READ_LONG(&tmp, 0x48, &dimm[2]);
785 for (i = 0; i < 3; i++) {
786 dimm[i] = (dimm[i] >> 8) & 0x4F;
789 dimm[0] = (pciReadLong(pciTag(0, 0, 2), 0x40) >> 8) & 0x4F;
790 dimm[1] = (pciReadLong(pciTag(0, 0, 2), 0x44) >> 8) & 0x4F;
791 dimm[2] = (pciReadLong(pciTag(0, 0, 2), 0x48) >> 8) & 0x4F;
794 if((dimm[0] + dimm[1]) != dimm[2]) {
796 "your nForce DIMMs are not arranged in optimal banks!\n");
800 sim_data.mem_latency = 3;
801 sim_data.mem_aligned = 1;
802 sim_data.mem_page_miss = 10;
803 sim_data.gr_during_vid = 0;
804 sim_data.pclk_khz = VClk;
805 sim_data.mclk_khz = MClk;
806 sim_data.nvclk_khz = NVClk;
807 nv10CalcArbitration(&fifo_data, &sim_data);
810 int b = fifo_data.graphics_burst_size >> 4;
812 while (b >>= 1) (*burst)++;
813 *lwm = fifo_data.graphics_lwm >> 3;
818 /****************************************************************************\
820 * RIVA Mode State Routines *
822 \****************************************************************************/
825 * Calculate the Video Clock parameters for the PLL.
827 static void CalcVClock (
834 unsigned lowM, highM;
835 unsigned DeltaNew, DeltaOld;
839 DeltaOld = 0xFFFFFFFF;
841 VClk = (unsigned)clockIn;
843 if (pNv->CrystalFreqKHz == 13500) {
851 for (P = 0; P <= 4; P++) {
853 if ((Freq >= 128000) && (Freq <= 350000)) {
854 for (M = lowM; M <= highM; M++) {
855 N = ((VClk << P) * M) / pNv->CrystalFreqKHz;
857 Freq = ((pNv->CrystalFreqKHz * N) / M) >> P;
859 DeltaNew = Freq - VClk;
861 DeltaNew = VClk - Freq;
862 if (DeltaNew < DeltaOld) {
863 *pllOut = (P << 16) | (N << 8) | M;
873 static void CalcVClock2Stage (
881 unsigned DeltaNew, DeltaOld;
885 DeltaOld = 0xFFFFFFFF;
887 *pllBOut = 0x80000401; /* fixed at x4 for now */
889 VClk = (unsigned)clockIn;
891 for (P = 0; P <= 6; P++) {
893 if ((Freq >= 400000) && (Freq <= 1000000)) {
894 for (M = 1; M <= 13; M++) {
895 N = ((VClk << P) * M) / (pNv->CrystalFreqKHz << 2);
896 if((N >= 5) && (N <= 255)) {
897 Freq = (((pNv->CrystalFreqKHz << 2) * N) / M) >> P;
899 DeltaNew = Freq - VClk;
901 DeltaNew = VClk - Freq;
902 if (DeltaNew < DeltaOld) {
903 *pllOut = (P << 16) | (N << 8) | M;
914 * Calculate extended mode parameters (SVGA) and save in a
915 * mode state structure.
917 void NVCalcStateExt (
919 RIVA_HW_STATE *state,
928 int pixelDepth, VClk;
932 * Save mode parameters.
934 state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */
935 state->width = width;
936 state->height = height;
938 * Extended RIVA registers.
940 pixelDepth = (bpp + 1)/8;
942 CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB, pNv);
944 CalcVClock(dotClock, &VClk, &state->pll, pNv);
946 switch (pNv->Architecture)
949 nv4UpdateArbitrationSettings(VClk,
951 &(state->arbitration0),
952 &(state->arbitration1),
954 state->cursor0 = 0x00;
955 state->cursor1 = 0xbC;
956 if (flags & V_DBLSCAN)
958 state->cursor2 = 0x00000000;
959 state->pllsel = 0x10000700;
960 state->config = 0x00001114;
961 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
962 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
968 if(((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
969 ((pNv->Chipset & 0xfff0) == CHIPSET_C512))
971 state->arbitration0 = 128;
972 state->arbitration1 = 0x0480;
974 if(((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
975 ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2))
977 nForceUpdateArbitrationSettings(VClk,
979 &(state->arbitration0),
980 &(state->arbitration1),
982 } else if(pNv->Architecture < NV_ARCH_30) {
983 nv10UpdateArbitrationSettings(VClk,
985 &(state->arbitration0),
986 &(state->arbitration1),
989 nv30UpdateArbitrationSettings(pNv,
990 &(state->arbitration0),
991 &(state->arbitration1));
993 CursorStart = pNv->Cursor->offset;
994 state->cursor0 = 0x80 | (CursorStart >> 17);
995 state->cursor1 = (CursorStart >> 11) << 2;
996 state->cursor2 = CursorStart >> 24;
997 if (flags & V_DBLSCAN)
999 state->pllsel = 0x10000700;
1000 state->config = nvReadFB(pNv, NV_PFB_CFG0);
1001 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
1002 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
1006 if(bpp != 8) /* DirectColor */
1007 state->general |= 0x00000030;
1009 state->repaint0 = (((width / 8) * pixelDepth) & 0x700) >> 3;
1010 state->pixel = (pixelDepth > 2) ? 3 : pixelDepth;
1014 void NVLoadStateExt (
1016 RIVA_HW_STATE *state
1019 NVPtr pNv = NVPTR(pScrn);
1022 if(pNv->Architecture >= NV_ARCH_40) {
1023 switch(pNv->Chipset & 0xfff0) {
1032 temp = nvReadCurRAMDAC(pNv, NV_RAMDAC_TEST_CONTROL);
1033 nvWriteCurRAMDAC(pNv, NV_RAMDAC_TEST_CONTROL, temp | 0x00100000);
1040 if(pNv->Architecture >= NV_ARCH_10) {
1042 nvWriteCRTC(pNv, 0, NV_CRTC_FSEL, state->head);
1043 nvWriteCRTC(pNv, 1, NV_CRTC_FSEL, state->head2);
1045 temp = nvReadCurRAMDAC(pNv, NV_RAMDAC_NV10_CURSYNC);
1046 nvWriteCurRAMDAC(pNv, NV_RAMDAC_NV10_CURSYNC, temp | (1 << 25));
1048 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
1049 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
1050 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
1051 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
1052 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1053 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1054 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1055 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1056 nvWriteMC(pNv, 0x1588, 0);
1058 nvWriteCurCRTC(pNv, NV_CRTC_CURSOR_CONFIG, state->cursorConfig);
1059 nvWriteCurCRTC(pNv, NV_CRTC_0830, state->displayV - 3);
1060 nvWriteCurCRTC(pNv, NV_CRTC_0834, state->displayV - 1);
1062 if(pNv->FlatPanel) {
1063 if((pNv->Chipset & 0x0ff0) == CHIPSET_NV11) {
1064 nvWriteCurRAMDAC(pNv, NV_RAMDAC_DITHER_NV11, state->dither);
1067 nvWriteCurRAMDAC(pNv, NV_RAMDAC_FP_DITHER, state->dither);
1070 nvWriteVGA(pNv, NV_VGA_CRTCX_FP_HTIMING, state->timingH);
1071 nvWriteVGA(pNv, NV_VGA_CRTCX_FP_VTIMING, state->timingV);
1072 nvWriteVGA(pNv, NV_VGA_CRTCX_BUFFER, 0xfa);
1075 nvWriteVGA(pNv, NV_VGA_CRTCX_EXTRA, state->extra);
1078 nvWriteVGA(pNv, NV_VGA_CRTCX_REPAINT0, state->repaint0);
1079 nvWriteVGA(pNv, NV_VGA_CRTCX_REPAINT1, state->repaint1);
1080 nvWriteVGA(pNv, NV_VGA_CRTCX_LSR, state->screen);
1081 nvWriteVGA(pNv, NV_VGA_CRTCX_PIXEL, state->pixel);
1082 nvWriteVGA(pNv, NV_VGA_CRTCX_HEB, state->horiz);
1083 nvWriteVGA(pNv, NV_VGA_CRTCX_FIFO1, state->fifo);
1084 nvWriteVGA(pNv, NV_VGA_CRTCX_FIFO0, state->arbitration0);
1085 nvWriteVGA(pNv, NV_VGA_CRTCX_FIFO_LWM, state->arbitration1);
1086 if(pNv->Architecture >= NV_ARCH_30) {
1087 nvWriteVGA(pNv, NV_VGA_CRTCX_FIFO_LWM_NV30, state->arbitration1 >> 8);
1090 nvWriteVGA(pNv, NV_VGA_CRTCX_CURCTL0, state->cursor0);
1091 nvWriteVGA(pNv, NV_VGA_CRTCX_CURCTL1, state->cursor1);
1092 if(pNv->Architecture == NV_ARCH_40) { /* HW bug */
1093 volatile CARD32 curpos = nvReadCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS);
1094 nvWriteCurRAMDAC(pNv, NV_RAMDAC_CURSOR_POS, curpos);
1096 nvWriteVGA(pNv, NV_VGA_CRTCX_CURCTL2, state->cursor2);
1097 nvWriteVGA(pNv, NV_VGA_CRTCX_INTERLACE, state->interlace);
1099 if(!pNv->FlatPanel) {
1100 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
1101 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll);
1103 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2);
1104 if(pNv->twoStagePLL) {
1105 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpllB);
1106 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2B);
1109 nvWriteCurRAMDAC(pNv, NV_RAMDAC_FP_CONTROL, state->scale);
1110 nvWriteCurRAMDAC(pNv, NV_RAMDAC_FP_HCRTC, state->crtcSync);
1112 nvWriteCurRAMDAC(pNv, NV_RAMDAC_GENERAL_CONTROL, state->general);
1114 nvWriteCurCRTC(pNv, NV_CRTC_INTR_EN_0, 0);
1115 nvWriteCurCRTC(pNv, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
1117 pNv->CurrentState = state;
1120 void NVUnloadStateExt
1123 RIVA_HW_STATE *state
1126 state->repaint0 = nvReadVGA(pNv, NV_VGA_CRTCX_REPAINT0);
1127 state->repaint1 = nvReadVGA(pNv, NV_VGA_CRTCX_REPAINT1);
1128 state->screen = nvReadVGA(pNv, NV_VGA_CRTCX_LSR);
1129 state->pixel = nvReadVGA(pNv, NV_VGA_CRTCX_PIXEL);
1130 state->horiz = nvReadVGA(pNv, NV_VGA_CRTCX_HEB);
1131 state->fifo = nvReadVGA(pNv, NV_VGA_CRTCX_FIFO1);
1132 state->arbitration0 = nvReadVGA(pNv, NV_VGA_CRTCX_FIFO0);
1133 state->arbitration1 = nvReadVGA(pNv, NV_VGA_CRTCX_FIFO_LWM);
1134 if(pNv->Architecture >= NV_ARCH_30) {
1135 state->arbitration1 |= (nvReadVGA(pNv, NV_VGA_CRTCX_FIFO_LWM_NV30) & 1) << 8;
1137 state->cursor0 = nvReadVGA(pNv, NV_VGA_CRTCX_CURCTL0);
1138 state->cursor1 = nvReadVGA(pNv, NV_VGA_CRTCX_CURCTL1);
1139 state->cursor2 = nvReadVGA(pNv, NV_VGA_CRTCX_CURCTL2);
1140 state->interlace = nvReadVGA(pNv, NV_VGA_CRTCX_INTERLACE);
1142 state->vpll = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
1144 state->vpll2 = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
1145 if(pNv->twoStagePLL) {
1146 state->vpllB = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
1147 state->vpll2B = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
1149 state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
1150 state->general = nvReadCurRAMDAC(pNv, NV_RAMDAC_GENERAL_CONTROL);
1151 state->scale = nvReadCurRAMDAC(pNv, NV_RAMDAC_FP_CONTROL);
1152 state->config = nvReadFB(pNv, NV_PFB_CFG0);
1154 if(pNv->Architecture >= NV_ARCH_10) {
1156 state->head = nvReadCRTC(pNv, 0, NV_CRTC_FSEL);
1157 state->head2 = nvReadCRTC(pNv, 1, NV_CRTC_FSEL);
1158 state->crtcOwner = nvReadVGA(pNv, NV_VGA_CRTCX_OWNER);
1160 state->extra = nvReadVGA(pNv, NV_VGA_CRTCX_EXTRA);
1162 state->cursorConfig = nvReadCurCRTC(pNv, NV_CRTC_CURSOR_CONFIG);
1164 if((pNv->Chipset & 0x0ff0) == CHIPSET_NV11) {
1165 state->dither = nvReadCurRAMDAC(pNv, NV_RAMDAC_DITHER_NV11);
1168 state->dither = nvReadCurRAMDAC(pNv, NV_RAMDAC_FP_DITHER);
1171 if(pNv->FlatPanel) {
1172 state->timingH = nvReadVGA(pNv, NV_VGA_CRTCX_FP_HTIMING);
1173 state->timingV = nvReadVGA(pNv, NV_VGA_CRTCX_FP_VTIMING);
1177 if(pNv->FlatPanel) {
1178 state->crtcSync = nvReadCurRAMDAC(pNv, NV_RAMDAC_FP_HCRTC);
1182 void NVSetStartAddress (
1187 nvWriteCurCRTC(pNv, NV_CRTC_START, start);