git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 2006 Dave Airlie
   3  * Copyright 2007 Maarten Maathuis
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * this code uses ideas taken from the NVIDIA nv driver - the nvidia license
  26  * decleration is at the bottom of this file as it is rather ugly
  27  */
  28
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include <assert.h>
  34 #include "xf86.h"
  35 #include "os.h"
  36 #include "mibank.h"
  37 #include "globals.h"
  38 #include "xf86.h"
  39 #include "xf86Priv.h"
  40 #include "xf86DDC.h"
  41 #include "mipointer.h"
  42 #include "windowstr.h"
  43 #include <randrstr.h>
  44 #include <X11/extensions/render.h>
  45
  46 #include "xf86Crtc.h"
  47 #include "nv_include.h"
  48
  49 #include "vgaHW.h"
  50
  51 #define CRTC_INDEX 0x3d4
  52 #define CRTC_DATA 0x3d5
  53 #define CRTC_IN_STAT_1 0x3da
  54
  55 #define WHITE_VALUE 0x3F
  56 #define BLACK_VALUE 0x00
  57 #define OVERSCAN_VALUE 0x01
  58
  59 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  60 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override);
  61 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  62 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  63 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  64 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  65
  66 static CARD8 NVReadPVIO(xf86CrtcPtr crtc, CARD32 address)
  67 {
  68         ScrnInfoPtr pScrn = crtc->scrn;
  69         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  70         NVPtr pNv = NVPTR(pScrn);
  71
  72         /* Only NV4x have two pvio ranges */
  73         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  74                 return NV_RD08(pNv->PVIO1, address);
  75         } else {
  76                 return NV_RD08(pNv->PVIO0, address);
  77         }
  78 }
  79
  80 static void NVWritePVIO(xf86CrtcPtr crtc, CARD32 address, CARD8 value)
  81 {
  82         ScrnInfoPtr pScrn = crtc->scrn;
  83         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
  84         NVPtr pNv = NVPTR(pScrn);
  85
  86         /* Only NV4x have two pvio ranges */
  87         if (nv_crtc->head == 1 && pNv->Architecture == NV_ARCH_40) {
  88                 NV_WR08(pNv->PVIO1, address, value);
  89         } else {
  90                 NV_WR08(pNv->PVIO0, address, value);
  91         }
  92 }
  93
  94 static void NVWriteMiscOut(xf86CrtcPtr crtc, CARD8 value)
  95 {
  96         NVWritePVIO(crtc, VGA_MISC_OUT_W, value);
  97 }
  98
  99 static CARD8 NVReadMiscOut(xf86CrtcPtr crtc)
 100 {
 101         return NVReadPVIO(crtc, VGA_MISC_OUT_R);
 102 }
 103
 104 void NVWriteVGA(NVPtr pNv, int head, CARD8 index, CARD8 value)
 105 {
 106         volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 107
 108         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 109         NV_WR08(pCRTCReg, CRTC_DATA, value);
 110 }
 111
 112 CARD8 NVReadVGA(NVPtr pNv, int head, CARD8 index)
 113 {
 114         volatile CARD8 *pCRTCReg = head ? pNv->PCIO1 : pNv->PCIO0;
 115
 116         NV_WR08(pCRTCReg, CRTC_INDEX, index);
 117         return NV_RD08(pCRTCReg, CRTC_DATA);
 118 }
 119
 120 /* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
 121  * I suspect they in fact do nothing, but are merely a way to carry useful
 122  * per-head variables around
 123  *
 124  * Known uses:
 125  * CR57         CR58
 126  * 0x00         index to the appropriate dcb entry (or 7f for inactive)
 127  * 0x02         dcb entry's "or" value (or 00 for inactive)
 128  * 0x03         bit0 set for dual link (LVDS, possibly elsewhere too)
 129  * 0x0f         laptop panel info -     high nibble for PEXTDEV_BOOT strap
 130  *                                      low nibble for xlat strap value
 131  */
 132
 133 void NVWriteVGACR5758(NVPtr pNv, int head, uint8_t index, uint8_t value)
 134 {
 135         NVWriteVGA(pNv, head, 0x57, index);
 136         NVWriteVGA(pNv, head, 0x58, value);
 137 }
 138
 139 uint8_t NVReadVGACR5758(NVPtr pNv, int head, uint8_t index)
 140 {
 141         NVWriteVGA(pNv, head, 0x57, index);
 142         return NVReadVGA(pNv, head, 0x58);
 143 }
 144
 145 void NVWriteVgaCrtc(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 146 {
 147         ScrnInfoPtr pScrn = crtc->scrn;
 148         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 149         NVPtr pNv = NVPTR(pScrn);
 150
 151         NVWriteVGA(pNv, nv_crtc->head, index, value);
 152 }
 153
 154 CARD8 NVReadVgaCrtc(xf86CrtcPtr crtc, CARD8 index)
 155 {
 156         ScrnInfoPtr pScrn = crtc->scrn;
 157         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 158         NVPtr pNv = NVPTR(pScrn);
 159
 160         return NVReadVGA(pNv, nv_crtc->head, index);
 161 }
 162
 163 static void NVWriteVgaSeq(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 164 {
 165         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 166         NVWritePVIO(crtc, VGA_SEQ_DATA, value);
 167 }
 168
 169 static CARD8 NVReadVgaSeq(xf86CrtcPtr crtc, CARD8 index)
 170 {
 171         NVWritePVIO(crtc, VGA_SEQ_INDEX, index);
 172         return NVReadPVIO(crtc, VGA_SEQ_DATA);
 173 }
 174
 175 static void NVWriteVgaGr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 176 {
 177         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 178         NVWritePVIO(crtc, VGA_GRAPH_DATA, value);
 179 }
 180
 181 static CARD8 NVReadVgaGr(xf86CrtcPtr crtc, CARD8 index)
 182 {
 183         NVWritePVIO(crtc, VGA_GRAPH_INDEX, index);
 184         return NVReadPVIO(crtc, VGA_GRAPH_DATA);
 185 }
 186
 187
 188 static void NVWriteVgaAttr(xf86CrtcPtr crtc, CARD8 index, CARD8 value)
 189 {
 190   ScrnInfoPtr pScrn = crtc->scrn;
 191   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 192   NVPtr pNv = NVPTR(pScrn);
 193   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 194
 195   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 196   if (nv_crtc->paletteEnabled)
 197     index &= ~0x20;
 198   else
 199     index |= 0x20;
 200   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 201   NV_WR08(pCRTCReg, VGA_ATTR_DATA_W, value);
 202 }
 203
 204 static CARD8 NVReadVgaAttr(xf86CrtcPtr crtc, CARD8 index)
 205 {
 206   ScrnInfoPtr pScrn = crtc->scrn;
 207   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 208   NVPtr pNv = NVPTR(pScrn);
 209   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 210
 211   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 212   if (nv_crtc->paletteEnabled)
 213     index &= ~0x20;
 214   else
 215     index |= 0x20;
 216   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, index);
 217   return NV_RD08(pCRTCReg, VGA_ATTR_DATA_R);
 218 }
 219
 220 void NVCrtcSetOwner(xf86CrtcPtr crtc)
 221 {
 222         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 223         ScrnInfoPtr pScrn = crtc->scrn;
 224         NVPtr pNv = NVPTR(pScrn);
 225         /* Non standard beheaviour required by NV11 */
 226         if (pNv) {
 227                 uint8_t owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 228                 ErrorF("pre-Owner: 0x%X\n", owner);
 229                 if (owner == 0x04) {
 230                         uint32_t pbus84 = nvReadMC(pNv, 0x1084);
 231                         ErrorF("pbus84: 0x%X\n", pbus84);
 232                         pbus84 &= ~(1<<28);
 233                         ErrorF("pbus84: 0x%X\n", pbus84);
 234                         nvWriteMC(pNv, 0x1084, pbus84);
 235                 }
 236                 /* The blob never writes owner to pcio1, so should we */
 237                 if (pNv->NVArch == 0x11) {
 238                         NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, 0xff);
 239                 }
 240                 NVWriteVGA0(pNv, NV_VGA_CRTCX_OWNER, nv_crtc->crtc * 0x3);
 241                 owner = NVReadVGA0(pNv, NV_VGA_CRTCX_OWNER);
 242                 ErrorF("post-Owner: 0x%X\n", owner);
 243         } else {
 244                 ErrorF("pNv pointer is NULL\n");
 245         }
 246 }
 247
 248 static void
 249 NVEnablePalette(xf86CrtcPtr crtc)
 250 {
 251   ScrnInfoPtr pScrn = crtc->scrn;
 252   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 253   NVPtr pNv = NVPTR(pScrn);
 254   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 255
 256   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 257   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0);
 258   nv_crtc->paletteEnabled = TRUE;
 259 }
 260
 261 static void
 262 NVDisablePalette(xf86CrtcPtr crtc)
 263 {
 264   ScrnInfoPtr pScrn = crtc->scrn;
 265   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 266   NVPtr pNv = NVPTR(pScrn);
 267   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 268
 269   NV_RD08(pCRTCReg, CRTC_IN_STAT_1);
 270   NV_WR08(pCRTCReg, VGA_ATTR_INDEX, 0x20);
 271   nv_crtc->paletteEnabled = FALSE;
 272 }
 273
 274 static void NVWriteVgaReg(xf86CrtcPtr crtc, CARD32 reg, CARD8 value)
 275 {
 276  ScrnInfoPtr pScrn = crtc->scrn;
 277   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 278   NVPtr pNv = NVPTR(pScrn);
 279   volatile CARD8 *pCRTCReg = nv_crtc->head ? pNv->PCIO1 : pNv->PCIO0;
 280
 281   NV_WR08(pCRTCReg, reg, value);
 282 }
 283
 284 /* perform a sequencer reset */
 285 static void NVVgaSeqReset(xf86CrtcPtr crtc, Bool start)
 286 {
 287   if (start)
 288     NVWriteVgaSeq(crtc, 0x00, 0x1);
 289   else
 290     NVWriteVgaSeq(crtc, 0x00, 0x3);
 291
 292 }
 293 static void NVVgaProtect(xf86CrtcPtr crtc, Bool on)
 294 {
 295         CARD8 tmp;
 296
 297         if (on) {
 298                 tmp = NVReadVgaSeq(crtc, 0x1);
 299                 NVVgaSeqReset(crtc, TRUE);
 300                 NVWriteVgaSeq(crtc, 0x01, tmp | 0x20);
 301
 302                 NVEnablePalette(crtc);
 303         } else {
 304                 /*
 305                  * Reenable sequencer, then turn on screen.
 306                  */
 307                 tmp = NVReadVgaSeq(crtc, 0x1);
 308                 NVWriteVgaSeq(crtc, 0x01, tmp & ~0x20); /* reenable display */
 309                 NVVgaSeqReset(crtc, FALSE);
 310
 311                 NVDisablePalette(crtc);
 312         }
 313 }
 314
 315 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool Lock)
 316 {
 317         CARD8 cr11;
 318
 319         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LOCK, Lock ? 0x99 : 0x57);
 320         cr11 = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE);
 321         if (Lock) cr11 |= 0x80;
 322         else cr11 &= ~0x80;
 323         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_VSYNCE, cr11);
 324 }
 325
 326 xf86OutputPtr
 327 NVGetOutputFromCRTC(xf86CrtcPtr crtc)
 328 {
 329         ScrnInfoPtr pScrn = crtc->scrn;
 330         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 331         int i;
 332         for (i = 0; i < xf86_config->num_output; i++) {
 333                 xf86OutputPtr output = xf86_config->output[i];
 334
 335                 if (output->crtc == crtc) {
 336                         return output;
 337                 }
 338         }
 339
 340         return NULL;
 341 }
 342
 343 xf86CrtcPtr
 344 nv_find_crtc_by_index(ScrnInfoPtr pScrn, int index)
 345 {
 346         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 347         int i;
 348
 349         for (i = 0; i < xf86_config->num_crtc; i++) {
 350                 xf86CrtcPtr crtc = xf86_config->crtc[i];
 351                 NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 352                 if (nv_crtc->crtc == index)
 353                         return crtc;
 354         }
 355
 356         return NULL;
 357 }
 358
 359 /*
 360  * Calculate the Video Clock parameters for the PLL.
 361  */
 362 static void CalcVClock (
 363         uint32_t                clockIn,
 364         uint32_t                *clockOut,
 365         CARD32          *pllOut,
 366         NVPtr           pNv
 367 )
 368 {
 369         unsigned lowM, highM, highP;
 370         unsigned DeltaNew, DeltaOld;
 371         unsigned VClk, Freq;
 372         unsigned M, N, P;
 373
 374         /* M: PLL reference frequency postscaler divider */
 375         /* P: PLL VCO output postscaler divider */
 376         /* N: PLL VCO postscaler setting */
 377
 378         DeltaOld = 0xFFFFFFFF;
 379
 380         VClk = (unsigned)clockIn;
 381
 382         /* Taken from Haiku, after someone with an NV28 had an issue */
 383         switch(pNv->NVArch) {
 384                 case 0x28:
 385                         lowM = 1;
 386                         highP = 32;
 387                         if (VClk > 340000) {
 388                                 highM = 2;
 389                         } else if (VClk > 200000) {
 390                                 highM = 4;
 391                         } else if (VClk > 150000) {
 392                                 highM = 6;
 393                         } else {
 394                                 highM = 14;
 395                         }
 396                         break;
 397                 default:
 398                         lowM = 1;
 399                         highP = 16;
 400                         if (VClk > 340000) {
 401                                 highM = 2;
 402                         } else if (VClk > 250000) {
 403                                 highM = 6;
 404                         } else {
 405                                 highM = 14;
 406                         }
 407                         break;
 408         }
 409
 410         for (P = 1; P <= highP; P++) {
 411                 Freq = VClk << P;
 412                 if ((Freq >= 128000) && (Freq <= 350000)) {
 413                         for (M = lowM; M <= highM; M++) {
 414                                 N = ((VClk << P) * M) / pNv->CrystalFreqKHz;
 415                                 if (N <= 255) {
 416                                         Freq = ((pNv->CrystalFreqKHz * N) / M) >> P;
 417                                         if (Freq > VClk) {
 418                                                 DeltaNew = Freq - VClk;
 419                                         } else {
 420                                                 DeltaNew = VClk - Freq;
 421                                         }
 422                                         if (DeltaNew < DeltaOld) {
 423                                                 *pllOut   = (P << 16) | (N << 8) | M;
 424                                                 *clockOut = Freq;
 425                                                 DeltaOld  = DeltaNew;
 426                                         }
 427                                 }
 428                         }
 429                 }
 430         }
 431 }
 432
 433 static void CalcVClock2Stage (
 434         uint32_t                clockIn,
 435         uint32_t                *clockOut,
 436         CARD32          *pllOut,
 437         CARD32          *pllBOut,
 438         NVPtr           pNv
 439 )
 440 {
 441         unsigned DeltaNew, DeltaOld;
 442         unsigned VClk, Freq;
 443         unsigned M, N, P;
 444         unsigned lowM, highM, highP;
 445
 446         DeltaOld = 0xFFFFFFFF;
 447
 448         *pllBOut = 0x80000401;  /* fixed at x4 for now */
 449
 450         VClk = (unsigned)clockIn;
 451
 452         /* Taken from Haiku, after someone with an NV28 had an issue */
 453         switch(pNv->NVArch) {
 454                 case 0x28:
 455                         lowM = 1;
 456                         highP = 32;
 457                         if (VClk > 340000) {
 458                                 highM = 2;
 459                         } else if (VClk > 200000) {
 460                                 highM = 4;
 461                         } else if (VClk > 150000) {
 462                                 highM = 6;
 463                         } else {
 464                                 highM = 14;
 465                         }
 466                         break;
 467                 default:
 468                         lowM = 1;
 469                         highP = 15;
 470                         if (VClk > 340000) {
 471                                 highM = 2;
 472                         } else if (VClk > 250000) {
 473                                 highM = 6;
 474                         } else {
 475                                 highM = 14;
 476                         }
 477                         break;
 478         }
 479
 480         for (P = 0; P <= highP; P++) {
 481                 Freq = VClk << P;
 482                 if ((Freq >= 400000) && (Freq <= 1000000)) {
 483                         for (M = lowM; M <= highM; M++) {
 484                                 N = ((VClk << P) * M) / (pNv->CrystalFreqKHz << 2);
 485                                 if ((N >= 5) && (N <= 255)) {
 486                                         Freq = (((pNv->CrystalFreqKHz << 2) * N) / M) >> P;
 487                                         if (Freq > VClk) {
 488                                                 DeltaNew = Freq - VClk;
 489                                         } else {
 490                                                 DeltaNew = VClk - Freq;
 491                                         }
 492                                         if (DeltaNew < DeltaOld) {
 493                                                 *pllOut   = (P << 16) | (N << 8) | M;
 494                                                 *clockOut = Freq;
 495                                                 DeltaOld  = DeltaNew;
 496                                         }
 497                                 }
 498                         }
 499                 }
 500         }
 501 }
 502
 503 /* BIG NOTE: modifying vpll1 and vpll2 does not work, what bit is the switch to allow it? */
 504
 505 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
 506 /* They are only valid for NV4x, appearantly reordered for NV5x */
 507 /* gpu pll: 0x4000 + 0x4004
 508  * unknown pll: 0x4008 + 0x400c
 509  * vpll1: 0x4010 + 0x4014
 510  * vpll2: 0x4018 + 0x401c
 511  * unknown pll: 0x4020 + 0x4024
 512  * unknown pll: 0x4038 + 0x403c
 513  * Some of the unknown's are probably memory pll's.
 514  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
 515  * 1 and 2 refer to the registers of each pair. There is only one post divider.
 516  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
 517  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
 518  *     bit8: A switch that turns of the second divider and multiplier off.
 519  *     bit12: Also a switch, i haven't seen it yet.
 520  *     bit16-19: p-divider
 521  *     but 28-31: Something related to the mode that is used (see bit8).
 522  * 2) bit0-7: m-divider (a)
 523  *     bit8-15: n-multiplier (a)
 524  *     bit16-23: m-divider (b)
 525  *     bit24-31: n-multiplier (b)
 526  */
 527
 528 /* Modifying the gpu pll for example requires:
 529  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 530  * This is not needed for the vpll's which have their own bits.
 531  */
 532
 533 static void
 534 CalculateVClkNV4x(
 535         NVPtr pNv,
 536         uint32_t requested_clock,
 537         uint32_t *given_clock,
 538         uint32_t *pll_a,
 539         uint32_t *pll_b,
 540         uint32_t *reg580,
 541         Bool    *db1_ratio,
 542         Bool primary,
 543         uint8_t special_bits
 544 )
 545 {
 546         uint32_t DeltaOld, DeltaNew;
 547         uint32_t freq, temp;
 548         /* We have 2 mulitpliers, 2 dividers and one post divider */
 549         /* Note that p is only 4 bits */
 550         uint32_t m1, m2, n1, n2, p;
 551         uint32_t m1_best = 0, m2_best = 0, n1_best = 0, n2_best = 0, p_best = 0;
 552
 553         DeltaOld = 0xFFFFFFFF;
 554
 555         /* This is no solid limit, but a reasonable boundary. */
 556         /* NV40 is a strange card, let's stay on the safe side .*/
 557         if (requested_clock < 120000 && pNv->NVArch > 0x40) {
 558                 *db1_ratio = TRUE;
 559                 /* Turn the second set of divider and multiplier off */
 560                 /* Neutral settings */
 561                 n2 = 1;
 562                 m2 = 1;
 563         } else {
 564                 *db1_ratio = FALSE;
 565                 /* Fixed at x4 for the moment */
 566                 n2 = 4;
 567                 m2 = 1;
 568         }
 569
 570         n2_best = n2;
 571         m2_best = m2;
 572
 573         /* Single pll */
 574         if (*db1_ratio) {
 575                 temp = 0.4975 * 250000;
 576                 p = 0;
 577
 578                 while (requested_clock <= temp) {
 579                         temp /= 2;
 580                         p++;
 581                 }
 582
 583                 /* The minimum clock after m1 is 3 Mhz, and the clock is 27 Mhz, so m_max = 9 */
 584                 /* The maximum clock is 25 Mhz */
 585                 for (m1 = 2; m1 <= 9; m1++) {
 586                         n1 = ((requested_clock << p) * m1)/(pNv->CrystalFreqKHz);
 587                         if (n1 > 0 && n1 <= 255) {
 588                                 freq = ((pNv->CrystalFreqKHz * n1)/m1) >> p;
 589                                 if (freq > requested_clock) {
 590                                         DeltaNew = freq - requested_clock;
 591                                 } else {
 592                                         DeltaNew = requested_clock - freq;
 593                                 }
 594                                 if (DeltaNew < DeltaOld) {
 595                                         m1_best = m1;
 596                                         n1_best = n1;
 597                                         p_best = p;
 598                                         DeltaOld = DeltaNew;
 599                                 }
 600                         }
 601                 }
 602         /* Dual pll */
 603         } else {
 604                 for (p = 0; p <= 6; p++) {
 605                         /* Assuming a fixed 2nd stage */
 606                         freq = requested_clock << p;
 607                         /* The maximum output frequency of stage 2 is allowed to be between 400 Mhz and 1 GHz */
 608                         if (freq > 400000 && freq < 1000000) {
 609                                 /* The minimum clock after m1 is 3 Mhz, and the clock is 27 Mhz, so m_max = 9 */
 610                                 /* The maximum clock is 25 Mhz */
 611                                 for (m1 = 2; m1 <= 9; m1++) {
 612                                         n1 = ((requested_clock << p) * m1 * m2)/(pNv->CrystalFreqKHz * n2);
 613                                         if (n1 >= 5 && n1 <= 255) {
 614                                                 freq = ((pNv->CrystalFreqKHz * n1 * n2)/(m1 * m2)) >> p;
 615                                                 if (freq > requested_clock) {
 616                                                         DeltaNew = freq - requested_clock;
 617                                                 } else {
 618                                                         DeltaNew = requested_clock - freq;
 619                                                 }
 620                                                 if (DeltaNew < DeltaOld) {
 621                                                         m1_best = m1;
 622                                                         n1_best = n1;
 623                                                         p_best = p;
 624                                                         DeltaOld = DeltaNew;
 625                                                 }
 626                                         }
 627                                 }
 628                         }
 629                 }
 630         }
 631
 632         if (*db1_ratio) {
 633                 /* Bogus data, the same nvidia uses */
 634                 n2_best = 1;
 635                 m2_best = 31;
 636         }
 637
 638         /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
 639         /* Let's keep the special bits, if the bios already set them */
 640         *pll_a = (special_bits << 30) | (p_best << 16) | (n1_best << 8) | (m1_best << 0);
 641         *pll_b = (1 << 31) | (n2_best << 8) | (m2_best << 0);
 642
 643         if (*db1_ratio) {
 644                 if (primary) {
 645                         *reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 646                 } else {
 647                         *reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 648                 }
 649         } else {
 650                 if (primary) {
 651                         *reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
 652                 } else {
 653                         *reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
 654                 }
 655         }
 656
 657         if (*db1_ratio) {
 658                 ErrorF("vpll: n1 %d m1 %d p %d db1_ratio %d\n", n1_best, m1_best, p_best, *db1_ratio);
 659         } else {
 660                 ErrorF("vpll: n1 %d n2 %d m1 %d m2 %d p %d db1_ratio %d\n", n1_best, n2_best, m1_best, m2_best, p_best, *db1_ratio);
 661         }
 662 }
 663
 664 static void nv40_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 665 {
 666         state->vpll1_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 667         state->vpll1_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 668         state->vpll2_a = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 669         state->vpll2_b = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 670         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 671         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 672         state->reg580 = nvReadRAMDAC0(pNv, NV_RAMDAC_580);
 673         state->reg594 = nvReadRAMDAC0(pNv, NV_RAMDAC_594);
 674 }
 675
 676 static void nv40_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 677 {
 678         CARD32 fp_debug_0[2];
 679         uint32_t index[2];
 680         fp_debug_0[0] = nvReadRAMDAC(pNv, 0, NV_RAMDAC_FP_DEBUG_0);
 681         fp_debug_0[1] = nvReadRAMDAC(pNv, 1, NV_RAMDAC_FP_DEBUG_0);
 682
 683         /* The TMDS_PLL switch is on the actual ramdac */
 684         if (state->crosswired) {
 685                 index[0] = 1;
 686                 index[1] = 0;
 687                 ErrorF("Crosswired pll state load\n");
 688         } else {
 689                 index[0] = 0;
 690                 index[1] = 1;
 691         }
 692
 693         if (state->vpll2_b) {
 694                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0,
 695                         fp_debug_0[index[1]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 696
 697                 /* Wait for the situation to stabilise */
 698                 usleep(5000);
 699
 700                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 701                 /* for vpll2 change bits 18 and 19 are disabled */
 702                 reg_c040 &= ~(0x3 << 18);
 703                 nvWriteMC(pNv, 0xc040, reg_c040);
 704
 705                 ErrorF("writing vpll2_a %08X\n", state->vpll2_a);
 706                 ErrorF("writing vpll2_b %08X\n", state->vpll2_b);
 707
 708                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2_a);
 709                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2_b);
 710
 711                 ErrorF("writing pllsel %08X\n", state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 712                 /* Let's keep the primary vpll off */
 713                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 714
 715                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 716                 ErrorF("writing reg580 %08X\n", state->reg580);
 717
 718                 /* We need to wait a while */
 719                 usleep(5000);
 720                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 721
 722                 nvWriteRAMDAC(pNv, index[1], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[1]]);
 723
 724                 /* Wait for the situation to stabilise */
 725                 usleep(5000);
 726         }
 727
 728         if (state->vpll1_b) {
 729                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0,
 730                         fp_debug_0[index[0]] | NV_RAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL);
 731
 732                 /* Wait for the situation to stabilise */
 733                 usleep(5000);
 734
 735                 uint32_t reg_c040 = pNv->misc_info.reg_c040;
 736                 /* for vpll2 change bits 16 and 17 are disabled */
 737                 reg_c040 &= ~(0x3 << 16);
 738                 nvWriteMC(pNv, 0xc040, reg_c040);
 739
 740                 ErrorF("writing vpll1_a %08X\n", state->vpll1_a);
 741                 ErrorF("writing vpll1_b %08X\n", state->vpll1_b);
 742
 743                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll1_a);
 744                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpll1_b);
 745
 746                 ErrorF("writing pllsel %08X\n", state->pllsel);
 747                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 748
 749                 nvWriteRAMDAC0(pNv, NV_RAMDAC_580, state->reg580);
 750                 ErrorF("writing reg580 %08X\n", state->reg580);
 751
 752                 /* We need to wait a while */
 753                 usleep(5000);
 754                 nvWriteMC(pNv, 0xc040, pNv->misc_info.reg_c040);
 755
 756                 nvWriteRAMDAC(pNv, index[0], NV_RAMDAC_FP_DEBUG_0, fp_debug_0[index[0]]);
 757
 758                 /* Wait for the situation to stabilise */
 759                 usleep(5000);
 760         }
 761
 762         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 763         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 764
 765         ErrorF("writing reg594 %08X\n", state->reg594);
 766         nvWriteRAMDAC0(pNv, NV_RAMDAC_594, state->reg594);
 767 }
 768
 769 static void nv_crtc_save_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 770 {
 771         state->vpll = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL);
 772         if(pNv->twoHeads) {
 773                 state->vpll2 = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2);
 774         }
 775         if(pNv->twoStagePLL) {
 776                 state->vpllB = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL_B);
 777                 state->vpll2B = nvReadRAMDAC0(pNv, NV_RAMDAC_VPLL2_B);
 778         }
 779         state->pllsel = nvReadRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT);
 780         state->sel_clk = nvReadRAMDAC0(pNv, NV_RAMDAC_SEL_CLK);
 781 }
 782
 783
 784 static void nv_crtc_load_state_pll(NVPtr pNv, RIVA_HW_STATE *state)
 785 {
 786         if (state->vpll2) {
 787                 if(pNv->twoHeads) {
 788                         ErrorF("writing vpll2 %08X\n", state->vpll2);
 789                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2, state->vpll2);
 790                 }
 791                 if(pNv->twoStagePLL) {
 792                         ErrorF("writing vpll2B %08X\n", state->vpll2B);
 793                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL2_B, state->vpll2B);
 794                 }
 795
 796                 ErrorF("writing pllsel %08X\n", state->pllsel);
 797                 /* Let's keep the primary vpll off */
 798                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel & ~NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL);
 799         }
 800
 801         if (state->vpll) {
 802                 ErrorF("writing vpll %08X\n", state->vpll);
 803                 nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL, state->vpll);
 804                 if(pNv->twoStagePLL) {
 805                         ErrorF("writing vpllB %08X\n", state->vpllB);
 806                         nvWriteRAMDAC0(pNv, NV_RAMDAC_VPLL_B, state->vpllB);
 807                 }
 808
 809                 ErrorF("writing pllsel %08X\n", state->pllsel);
 810                 nvWriteRAMDAC0(pNv, NV_RAMDAC_PLL_SELECT, state->pllsel);
 811         }
 812
 813         ErrorF("writing sel_clk %08X\n", state->sel_clk);
 814         nvWriteRAMDAC0(pNv, NV_RAMDAC_SEL_CLK, state->sel_clk);
 815 }
 816
 817 /* It is unknown if the bus has a similar meaning on pre-NV40 hardware. */
 818
 819 static uint8_t
 820 nv_get_sel_clk_offset(uint8_t NVArch, uint8_t bus)
 821 {
 822         switch(bus) {
 823                 case 0:
 824                         if (NVArch >= 0x44) {
 825                                 return 8;
 826                         } else {
 827                                 return 12;
 828                         }
 829                 case 1:
 830                         return 16;
 831                 case 2: /* bus 2 or 3 are either dvi on mobile or tv-out */
 832                 case 3: /* don't use this for tv-out */
 833                         return 4;
 834                 default:
 835                         ErrorF("Unknown bus, bad things may happen\n");
 836                         return 16;
 837         }
 838 }
 839
 840 static void
 841 nv_wipe_other_clocks(uint32_t *sel_clk, uint8_t NVArch, uint8_t head, uint8_t bus)
 842 {
 843         int i;
 844         /* head0 = 1, head1 = 4 */
 845         uint8_t our_clock = 1 + head*3;
 846
 847         if (!sel_clk)
 848                 return;
 849
 850         for (i = 0; i < 5; i++) {
 851                 int offset = i*4;
 852                 if (nv_get_sel_clk_offset(NVArch, bus) == offset) /* Let's keep our own clock */
 853                         continue;
 854
 855                 if (((*sel_clk << offset) & 0xf) == (our_clock << offset)) /* Let's wipe other entries */
 856                         *sel_clk &= ~(0xf << offset);
 857         }
 858 }
 859
 860 #define IS_NV44P (pNv->NVArch >= 0x44 ? 1 : 0)
 861 #define SEL_CLK_OFFSET (nv_get_sel_clk_offset(pNv->NVArch, nv_output->bus))
 862
 863 #define WIPE_OTHER_CLOCKS(_sel_clk, _head, _bus) (nv_wipe_other_clocks(_sel_clk, pNv->NVArch, _head, _bus))
 864
 865 /*
 866  * Calculate extended mode parameters (SVGA) and save in a
 867  * mode state structure.
 868  * State is not specific to a single crtc, but shared.
 869  */
 870 void nv_crtc_calc_state_ext(
 871         xf86CrtcPtr     crtc,
 872         int                     bpp,
 873         int                     DisplayWidth, /* Does this change after setting the mode? */
 874         int                     CrtcHDisplay,
 875         int                     CrtcVDisplay,
 876         int                     dotClock,
 877         int                     flags
 878 )
 879 {
 880         ScrnInfoPtr pScrn = crtc->scrn;
 881         uint32_t pixelDepth, VClk = 0;
 882         CARD32 CursorStart;
 883         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
 884         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 885         NVCrtcRegPtr regp;
 886         NVPtr pNv = NVPTR(pScrn);
 887         RIVA_HW_STATE *state, *sv_state;
 888         int num_crtc_enabled, i;
 889
 890         state = &pNv->ModeReg;
 891         sv_state = &pNv->SavedReg;
 892
 893         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 894
 895         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
 896         NVOutputPrivatePtr nv_output = NULL;
 897         if (output) {
 898                 nv_output = output->driver_private;
 899         }
 900
 901         /*
 902          * Extended RIVA registers.
 903          */
 904         pixelDepth = (bpp + 1)/8;
 905         if (pNv->Architecture == NV_ARCH_40) {
 906                 /* Does register 0x580 already have a value? */
 907                 if (!state->reg580) {
 908                         state->reg580 = pNv->misc_info.ramdac_0_reg_580;
 909                 }
 910                 if (nv_crtc->head == 1) {
 911                         CalculateVClkNV4x(pNv, dotClock, &VClk, &state->vpll2_a, &state->vpll2_b, &state->reg580, &state->db1_ratio[1], FALSE, (sv_state->vpll2_a >> 30));
 912                 } else {
 913                         CalculateVClkNV4x(pNv, dotClock, &VClk, &state->vpll1_a, &state->vpll1_b, &state->reg580, &state->db1_ratio[0], TRUE, (sv_state->vpll1_a >> 30));
 914                 }
 915         } else if (pNv->twoStagePLL) {
 916                 CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB, pNv);
 917         } else {
 918                 CalcVClock(dotClock, &VClk, &state->pll, pNv);
 919         }
 920
 921         switch (pNv->Architecture) {
 922         case NV_ARCH_04:
 923                 nv4UpdateArbitrationSettings(VClk,
 924                                                 pixelDepth * 8,
 925                                                 &(state->arbitration0),
 926                                                 &(state->arbitration1),
 927                                                 pNv);
 928                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x00;
 929                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = 0xbC;
 930                 if (flags & V_DBLSCAN)
 931                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 932                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = 0x00000000;
 933                 state->pllsel   |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2 | NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
 934                 state->config   = 0x00001114;
 935                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 936                 break;
 937         case NV_ARCH_10:
 938         case NV_ARCH_20:
 939         case NV_ARCH_30:
 940         default:
 941                 if (((pNv->Chipset & 0xfff0) == CHIPSET_C51) ||
 942                         ((pNv->Chipset & 0xfff0) == CHIPSET_C512)) {
 943                         state->arbitration0 = 128;
 944                         state->arbitration1 = 0x0480;
 945                 } else if (((pNv->Chipset & 0xffff) == CHIPSET_NFORCE) ||
 946                         ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE2)) {
 947                         nForceUpdateArbitrationSettings(VClk,
 948                                                 pixelDepth * 8,
 949                                                 &(state->arbitration0),
 950                                                 &(state->arbitration1),
 951                                                 pNv);
 952                 } else if (pNv->Architecture < NV_ARCH_30) {
 953                         nv10UpdateArbitrationSettings(VClk,
 954                                                 pixelDepth * 8,
 955                                                 &(state->arbitration0),
 956                                                 &(state->arbitration1),
 957                                                 pNv);
 958                 } else {
 959                         nv30UpdateArbitrationSettings(pNv,
 960                                                 &(state->arbitration0),
 961                                                 &(state->arbitration1));
 962                 }
 963
 964                 CursorStart = pNv->Cursor->offset;
 965
 966                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] = 0x80 | (CursorStart >> 17);
 967                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (CursorStart >> 11) << 2;
 968                 regp->CRTC[NV_VGA_CRTCX_CURCTL2] = CursorStart >> 24;
 969
 970                 if (flags & V_DBLSCAN)
 971                         regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 972
 973                 state->config   = nvReadFB(pNv, NV_PFB_CFG0);
 974                 regp->CRTC[NV_VGA_CRTCX_REPAINT1] = CrtcHDisplay < 1280 ? 0x04 : 0x00;
 975                 break;
 976         }
 977
 978         /* okay do we have 2 CRTCs running ? */
 979         num_crtc_enabled = 0;
 980         for (i = 0; i < xf86_config->num_crtc; i++) {
 981                 if (xf86_config->crtc[i]->enabled) {
 982                         num_crtc_enabled++;
 983                 }
 984         }
 985
 986         ErrorF("There are %d CRTC's enabled\n", num_crtc_enabled);
 987
 988         if (pNv->Architecture < NV_ARCH_40) {
 989                 /* We need this before the next code */
 990                 if (nv_crtc->head == 1) {
 991                         state->vpll2 = state->pll;
 992                         state->vpll2B = state->pllB;
 993                 } else {
 994                         state->vpll = state->pll;
 995                         state->vpllB = state->pllB;
 996                 }
 997         }
 998
 999         /* This stuff also applies to NV3x to some extend, but the rules are different. */
1000         if (pNv->Architecture == NV_ARCH_40) {
1001                 /* This register is only used on the primary ramdac */
1002                 /* This seems to be needed to select the proper clocks, otherwise bad things happen */
1003
1004                 if (!state->sel_clk)
1005                         state->sel_clk = pNv->misc_info.sel_clk & ~(0xfffff << 0);
1006
1007                 /* There are a few possibilities:
1008                  * Early NV4x cards: 0x41000 for example
1009                  * Later NV4x cards: 0x40100 for example
1010                  * See nv_get_sel_clk_offset() for the meaning of the buses.
1011                  * This is only valid for the first two outputs.
1012                  * 0: No dvi present on bus
1013                  * 1: crtc != preferred_output
1014                  * 2: Unknown, similar to 4?
1015                  * 4: crtc == preferred_output
1016                  */
1017
1018                 /* This won't work when tv-out's come into play */
1019                 state->sel_clk &= ~(0xf << SEL_CLK_OFFSET);
1020                 if (output && (nv_output->type == OUTPUT_TMDS || nv_output->type == OUTPUT_LVDS)) {
1021                         if (nv_output->bus < 2) { /* these are the normal outputs */
1022                                 if (nv_crtc->head == nv_output->preferred_output) {
1023                                         state->sel_clk |= (0x4 << SEL_CLK_OFFSET);
1024                                 } else {
1025                                         state->sel_clk |= (0x1 << SEL_CLK_OFFSET);
1026                                 }
1027                         } else { /* dvi on mobile cards */
1028                                 if (nv_crtc->head == 0) {
1029                                         state->sel_clk |= (0x4 << SEL_CLK_OFFSET);
1030                                 } else {
1031                                         state->sel_clk |= (0x1 << SEL_CLK_OFFSET);
1032                                 }
1033                         }
1034                 }
1035
1036                 /* The hardware gets upset if for example 0x00100 is set instead of 0x40100 */
1037                 /* Does this need further refinement? */
1038                 /* Let's hope this is enough */
1039                 if ((state->sel_clk & (0xffff << 0)) && !(state->sel_clk & (0xf << 16))) {
1040                         state->sel_clk |= (0x4 << 16);
1041                 }
1042
1043                 /* Are we crosswired? */
1044                 if (output && nv_crtc->head != nv_output->preferred_output) {
1045                         state->crosswired = TRUE;
1046                 } else {
1047                         state->crosswired = FALSE;
1048                 }
1049
1050                 if (nv_crtc->head == 1) {
1051                         if (state->db1_ratio[1])
1052                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1053                 } else if (nv_crtc->head == 0) {
1054                         if (state->db1_ratio[0])
1055                                 ErrorF("We are a lover of the DB1 VCLK ratio\n");
1056                 }
1057         } else {
1058                 /* This seems true for nv34 */
1059                 state->sel_clk = 0x0;
1060                 state->crosswired = FALSE;
1061         }
1062
1063         if (nv_crtc->head == 1) {
1064                 if (!state->db1_ratio[1]) {
1065                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1066                 } else {
1067                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
1068                 }
1069                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
1070         } else {
1071                 /* The NV40 seems to have more similarities to NV3x than other cards. */
1072                 if (pNv->NVArch < 0x41)
1073                         state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_ALL;
1074                 else
1075                         state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
1076                 if (!state->db1_ratio[0]) {
1077                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1078                 } else {
1079                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
1080                 }
1081         }
1082
1083         /* The blob uses this always, so let's do the same */
1084         if (pNv->Architecture == NV_ARCH_40) {
1085                 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
1086         }
1087
1088         /* The primary output doesn't seem to care */
1089         if (nv_output->preferred_output == 1) { /* This is the "output" */
1090                 /* non-zero values are for analog, don't know about tv-out and the likes */
1091                 if (output && nv_output->type != OUTPUT_ANALOG) {
1092                         state->reg594 = 0x0;
1093                 } else {
1094                         /* More values exist, but they seem related to the 3rd dac (tv-out?) somehow */
1095                         /* bit 16-19 are bits that are set on some G70 cards */
1096                         /* Those bits are also set to the 3rd OUTPUT register */
1097                         if (nv_crtc->head == 1) {
1098                                 state->reg594 = 0x101;
1099                         } else {
1100                                 state->reg594 = 0x1;
1101                         }
1102                 }
1103         }
1104
1105         regp->CRTC[NV_VGA_CRTCX_FIFO0] = state->arbitration0;
1106         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = state->arbitration1 & 0xff;
1107         if (pNv->Architecture >= NV_ARCH_30) {
1108                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = state->arbitration1 >> 8;
1109         }
1110
1111         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = (((DisplayWidth/8) * pixelDepth) & 0x700) >> 3;
1112         regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pixelDepth > 2) ? 3 : pixelDepth;
1113 }
1114
1115 static void
1116 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
1117 {
1118         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1119         ScrnInfoPtr pScrn = crtc->scrn;
1120         NVPtr pNv = NVPTR(pScrn);
1121         unsigned char seq1 = 0, crtc17 = 0;
1122         unsigned char crtc1A;
1123
1124         ErrorF("nv_crtc_dpms is called for CRTC %d with mode %d\n", nv_crtc->crtc, mode);
1125
1126         NVCrtcSetOwner(crtc);
1127
1128         crtc1A = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
1129         switch(mode) {
1130                 case DPMSModeStandby:
1131                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
1132                 seq1 = 0x20;
1133                 crtc17 = 0x80;
1134                 crtc1A |= 0x80;
1135                 break;
1136         case DPMSModeSuspend:
1137                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
1138                 seq1 = 0x20;
1139                 crtc17 = 0x80;
1140                 crtc1A |= 0x40;
1141                 break;
1142         case DPMSModeOff:
1143                 /* Screen: Off; HSync: Off, VSync: Off */
1144                 seq1 = 0x20;
1145                 crtc17 = 0x00;
1146                 crtc1A |= 0xC0;
1147                 break;
1148         case DPMSModeOn:
1149         default:
1150                 /* Screen: On; HSync: On, VSync: On */
1151                 seq1 = 0x00;
1152                 crtc17 = 0x80;
1153                 break;
1154         }
1155
1156         NVVgaSeqReset(crtc, TRUE);
1157         /* Each head has it's own sequencer, so we can turn it off when we want */
1158         seq1 |= (NVReadVgaSeq(crtc, 0x01) & ~0x20);
1159         NVWriteVgaSeq(crtc, 0x1, seq1);
1160         crtc17 |= (NVReadVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL) & ~0x80);
1161         usleep(10000);
1162         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_MODECTL, crtc17);
1163         NVVgaSeqReset(crtc, FALSE);
1164
1165         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, crtc1A);
1166
1167         /* I hope this is the right place */
1168         if (crtc->enabled && mode == DPMSModeOn) {
1169                 pNv->crtc_active[nv_crtc->head] = TRUE;
1170         } else {
1171                 pNv->crtc_active[nv_crtc->head] = FALSE;
1172         }
1173 }
1174
1175 static Bool
1176 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
1177                      DisplayModePtr adjusted_mode)
1178 {
1179         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1180         ErrorF("nv_crtc_mode_fixup is called for CRTC %d\n", nv_crtc->crtc);
1181
1182         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1183         NVOutputPrivatePtr nv_output = NULL;
1184         if (output) {
1185                 nv_output = output->driver_private;
1186         }
1187
1188         /* For internal panels and gpu scaling on DVI we need the native mode */
1189         if (output && ((nv_output->type == OUTPUT_LVDS) || (nv_output->scaling_mode > 0 && (nv_output->type == OUTPUT_TMDS)))) {
1190                 adjusted_mode->HDisplay = nv_output->native_mode->HDisplay;
1191                 adjusted_mode->HSkew = nv_output->native_mode->HSkew;
1192                 adjusted_mode->HSyncStart = nv_output->native_mode->HSyncStart;
1193                 adjusted_mode->HSyncEnd = nv_output->native_mode->HSyncEnd;
1194                 adjusted_mode->HTotal = nv_output->native_mode->HTotal;
1195                 adjusted_mode->VDisplay = nv_output->native_mode->VDisplay;
1196                 adjusted_mode->VScan = nv_output->native_mode->VScan;
1197                 adjusted_mode->VSyncStart = nv_output->native_mode->VSyncStart;
1198                 adjusted_mode->VSyncEnd = nv_output->native_mode->VSyncEnd;
1199                 adjusted_mode->VTotal = nv_output->native_mode->VTotal;
1200                 adjusted_mode->Clock = nv_output->native_mode->Clock;
1201
1202                 xf86SetModeCrtc(adjusted_mode, INTERLACE_HALVE_V);
1203         }
1204
1205         return TRUE;
1206 }
1207
1208 static void
1209 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1210 {
1211         ScrnInfoPtr pScrn = crtc->scrn;
1212         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1213         NVCrtcRegPtr regp;
1214         NVPtr pNv = NVPTR(pScrn);
1215         NVFBLayout *pLayout = &pNv->CurrentLayout;
1216         int depth = pScrn->depth;
1217
1218         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1219
1220         /* Calculate our timings */
1221         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
1222         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
1223         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
1224         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
1225         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
1226         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
1227         int vertDisplay         = mode->CrtcVDisplay                    - 1;
1228         int vertStart           = mode->CrtcVSyncStart          - 1;
1229         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
1230         int vertTotal           = mode->CrtcVTotal                      - 2;
1231         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
1232         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
1233
1234         Bool is_fp = FALSE;
1235
1236         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1237         NVOutputPrivatePtr nv_output = NULL;
1238         if (output) {
1239                 nv_output = output->driver_private;
1240
1241                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1242                         is_fp = TRUE;
1243         }
1244
1245         ErrorF("Mode clock: %d\n", mode->Clock);
1246         ErrorF("Adjusted mode clock: %d\n", adjusted_mode->Clock);
1247
1248         /* Reverted to what nv did, because that works for all resolutions on flatpanels */
1249         if (is_fp) {
1250                 vertStart = vertTotal - 3;
1251                 vertEnd = vertTotal - 2;
1252                 vertBlankStart = vertStart;
1253                 horizStart = horizTotal - 5;
1254                 horizEnd = horizTotal - 2;
1255                 horizBlankEnd = horizTotal + 4;
1256                 if (pNv->overlayAdaptor) {
1257                         /* This reportedly works around Xv some overlay bandwidth problems*/
1258                         horizTotal += 2;
1259                 }
1260         }
1261
1262         if(mode->Flags & V_INTERLACE)
1263                 vertTotal |= 1;
1264
1265         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
1266         ErrorF("horizStart: 0x%X \n", horizStart);
1267         ErrorF("horizEnd: 0x%X \n", horizEnd);
1268         ErrorF("horizTotal: 0x%X \n", horizTotal);
1269         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
1270         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
1271         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
1272         ErrorF("vertStart: 0x%X \n", vertStart);
1273         ErrorF("vertEnd: 0x%X \n", vertEnd);
1274         ErrorF("vertTotal: 0x%X \n", vertTotal);
1275         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
1276         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
1277
1278         /*
1279         * compute correct Hsync & Vsync polarity
1280         */
1281         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
1282                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
1283
1284                 regp->MiscOutReg = 0x23;
1285                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
1286                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
1287         } else {
1288                 int VDisplay = mode->VDisplay;
1289                 if (mode->Flags & V_DBLSCAN)
1290                         VDisplay *= 2;
1291                 if (mode->VScan > 1)
1292                         VDisplay *= mode->VScan;
1293                 if (VDisplay < 400) {
1294                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
1295                 } else if (VDisplay < 480) {
1296                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
1297                 } else if (VDisplay < 768) {
1298                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
1299                 } else {
1300                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
1301                 }
1302         }
1303
1304         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
1305
1306         /*
1307         * Time Sequencer
1308         */
1309         if (depth == 4) {
1310                 regp->Sequencer[0] = 0x02;
1311         } else {
1312                 regp->Sequencer[0] = 0x00;
1313         }
1314         /* 0x20 disables the sequencer */
1315         if (mode->Flags & V_CLKDIV2) {
1316                 regp->Sequencer[1] = 0x29;
1317         } else {
1318                 regp->Sequencer[1] = 0x21;
1319         }
1320         if (depth == 1) {
1321                 regp->Sequencer[2] = 1 << BIT_PLANE;
1322         } else {
1323                 regp->Sequencer[2] = 0x0F;
1324                 regp->Sequencer[3] = 0x00;                     /* Font select */
1325         }
1326         if (depth < 8) {
1327                 regp->Sequencer[4] = 0x06;                             /* Misc */
1328         } else {
1329                 regp->Sequencer[4] = 0x0E;                             /* Misc */
1330         }
1331
1332         /*
1333         * CRTC Controller
1334         */
1335         regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
1336         regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
1337         regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
1338         regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0)
1339                                 | SetBit(7);
1340         regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
1341         regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
1342                                 | SetBitField(horizEnd,4:0,4:0);
1343         regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
1344         regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
1345                                 | SetBitField(vertDisplay,8:8,1:1)
1346                                 | SetBitField(vertStart,8:8,2:2)
1347                                 | SetBitField(vertBlankStart,8:8,3:3)
1348                                 | SetBit(4)
1349                                 | SetBitField(vertTotal,9:9,5:5)
1350                                 | SetBitField(vertDisplay,9:9,6:6)
1351                                 | SetBitField(vertStart,9:9,7:7);
1352         regp->CRTC[NV_VGA_CRTCX_PRROWSCN]  = 0x00;
1353         regp->CRTC[NV_VGA_CRTCX_MAXSCLIN]  = SetBitField(vertBlankStart,9:9,5:5)
1354                                 | SetBit(6)
1355                                 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00);
1356         regp->CRTC[NV_VGA_CRTCX_VGACURCTRL] = 0x00;
1357         regp->CRTC[0xb] = 0x00;
1358         regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00;
1359         regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
1360         regp->CRTC[0xe] = 0x00;
1361         regp->CRTC[0xf] = 0x00;
1362         regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
1363         regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
1364         regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
1365         regp->CRTC[0x14] = 0x00;
1366         regp->CRTC[NV_VGA_CRTCX_PITCHL] = ((pScrn->displayWidth/8)*(pLayout->bitsPerPixel/8));
1367         regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
1368         regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
1369         /* 0x80 enables the sequencer, we don't want that */
1370         if (depth < 8) {
1371                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xE3 & ~0x80;
1372         } else {
1373                 regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80;
1374         }
1375         regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
1376
1377         /*
1378          * Some extended CRTC registers (they are not saved with the rest of the vga regs).
1379          */
1380
1381         regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
1382                                 | SetBitField(vertBlankStart,10:10,3:3)
1383                                 | SetBitField(vertStart,10:10,2:2)
1384                                 | SetBitField(vertDisplay,10:10,1:1)
1385                                 | SetBitField(vertTotal,10:10,0:0);
1386
1387         regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
1388                                 | SetBitField(horizDisplay,8:8,1:1)
1389                                 | SetBitField(horizBlankStart,8:8,2:2)
1390                                 | SetBitField(horizStart,8:8,3:3);
1391
1392         regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
1393                                 | SetBitField(vertDisplay,11:11,2:2)
1394                                 | SetBitField(vertStart,11:11,4:4)
1395                                 | SetBitField(vertBlankStart,11:11,6:6);
1396
1397         if(mode->Flags & V_INTERLACE) {
1398                 horizTotal = (horizTotal >> 1) & ~1;
1399                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
1400                 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
1401         } else {
1402                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff;  /* interlace off */
1403         }
1404
1405         /*
1406         * Theory resumes here....
1407         */
1408
1409         /*
1410         * Graphics Display Controller
1411         */
1412         regp->Graphics[0] = 0x00;
1413         regp->Graphics[1] = 0x00;
1414         regp->Graphics[2] = 0x00;
1415         regp->Graphics[3] = 0x00;
1416         if (depth == 1) {
1417                 regp->Graphics[4] = BIT_PLANE;
1418                 regp->Graphics[5] = 0x00;
1419         } else {
1420                 regp->Graphics[4] = 0x00;
1421                 if (depth == 4) {
1422                         regp->Graphics[5] = 0x02;
1423                 } else {
1424                         regp->Graphics[5] = 0x40;
1425                 }
1426         }
1427         regp->Graphics[6] = 0x05;   /* only map 64k VGA memory !!!! */
1428         regp->Graphics[7] = 0x0F;
1429         regp->Graphics[8] = 0xFF;
1430
1431         /* I ditched the mono stuff */
1432         regp->Attribute[0]  = 0x00; /* standard colormap translation */
1433         regp->Attribute[1]  = 0x01;
1434         regp->Attribute[2]  = 0x02;
1435         regp->Attribute[3]  = 0x03;
1436         regp->Attribute[4]  = 0x04;
1437         regp->Attribute[5]  = 0x05;
1438         regp->Attribute[6]  = 0x06;
1439         regp->Attribute[7]  = 0x07;
1440         regp->Attribute[8]  = 0x08;
1441         regp->Attribute[9]  = 0x09;
1442         regp->Attribute[10] = 0x0A;
1443         regp->Attribute[11] = 0x0B;
1444         regp->Attribute[12] = 0x0C;
1445         regp->Attribute[13] = 0x0D;
1446         regp->Attribute[14] = 0x0E;
1447         regp->Attribute[15] = 0x0F;
1448         /* These two below are non-vga */
1449         regp->Attribute[16] = 0x01;
1450         regp->Attribute[17] = 0x00;
1451         regp->Attribute[18] = 0x0F;
1452         regp->Attribute[19] = 0x00;
1453         regp->Attribute[20] = 0x00;
1454 }
1455
1456 #define MAX_H_VALUE(i) ((0x1ff + i) << 3)
1457 #define MAX_V_VALUE(i) ((0xfff + i) << 0)
1458
1459 /**
1460  * Sets up registers for the given mode/adjusted_mode pair.
1461  *
1462  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1463  *
1464  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1465  * be easily turned on/off after this.
1466  */
1467 static void
1468 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1469 {
1470         ScrnInfoPtr pScrn = crtc->scrn;
1471         NVPtr pNv = NVPTR(pScrn);
1472         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1473         NVFBLayout *pLayout = &pNv->CurrentLayout;
1474         NVCrtcRegPtr regp, savep;
1475         unsigned int i;
1476         Bool is_fp = FALSE;
1477
1478         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1479         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1480
1481         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1482         NVOutputPrivatePtr nv_output = NULL;
1483         if (output) {
1484                 nv_output = output->driver_private;
1485
1486                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1487                         is_fp = TRUE;
1488         }
1489
1490         /* Registers not directly related to the (s)vga mode */
1491
1492         /* bit2 = 0 -> fine pitched crtc granularity */
1493         /* The rest disables double buffering on CRTC access */
1494         regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
1495
1496         if (savep->CRTC[NV_VGA_CRTCX_LCD] <= 0xb) {
1497                 /* Common values are 0x0, 0x3, 0x8, 0xb, see logic below */
1498                 if (nv_crtc->head == 0) {
1499                         regp->CRTC[NV_VGA_CRTCX_LCD] = (1 << 3);
1500                 }
1501
1502                 if (is_fp) {
1503                         regp->CRTC[NV_VGA_CRTCX_LCD] |= (1 << 0) | (1 << 1);
1504                 }
1505         } else {
1506                 /* Let's keep any abnormal value there may be, like 0x54 or 0x79 */
1507                 regp->CRTC[NV_VGA_CRTCX_LCD] = savep->CRTC[NV_VGA_CRTCX_LCD];
1508         }
1509
1510         /* Sometimes 0x10 is used, what is this? */
1511         regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
1512         /* Some kind of tmds switch for older cards */
1513         if (pNv->Architecture < NV_ARCH_40) {
1514                 regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
1515         }
1516
1517         /*
1518         * Initialize DAC palette.
1519         */
1520         if(pLayout->bitsPerPixel != 8 ) {
1521                 for (i = 0; i < 256; i++) {
1522                         regp->DAC[i*3]     = i;
1523                         regp->DAC[(i*3)+1] = i;
1524                         regp->DAC[(i*3)+2] = i;
1525                 }
1526         }
1527
1528         /*
1529         * Calculate the extended registers.
1530         */
1531
1532         if(pLayout->depth < 24) {
1533                 i = pLayout->depth;
1534         } else {
1535                 i = 32;
1536         }
1537
1538         if(pNv->Architecture >= NV_ARCH_10) {
1539                 pNv->CURSOR = (CARD32 *)pNv->Cursor->map;
1540         }
1541
1542         /* What is the meaning of this register? */
1543         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
1544         regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
1545
1546         /* NV40's don't set FPP units, unless in special conditions (then they set both) */
1547         /* But what are those special conditions? */
1548         if (pNv->Architecture <= NV_ARCH_30) {
1549                 if (is_fp) {
1550                         if(nv_crtc->head == 1) {
1551                                 regp->head |= NV_CRTC_FSEL_FPP1;
1552                         } else if (pNv->twoHeads) {
1553                                 regp->head |= NV_CRTC_FSEL_FPP2;
1554                         }
1555                 }
1556         } else {
1557                 /* Some G70 cards have either FPP1 or FPP2 set, copy this if it's already present */
1558                 if (nv_crtc->head == 1 && pNv->NVArch > 0x44) {
1559                         regp->head |= savep->head & (NV_CRTC_FSEL_FPP1 | NV_CRTC_FSEL_FPP2);
1560                 }
1561         }
1562
1563         /* Except for rare conditions I2C is enabled on the primary crtc */
1564         if (nv_crtc->head == 0) {
1565                 if (pNv->overlayAdaptor) {
1566                         regp->head |= NV_CRTC_FSEL_OVERLAY;
1567                 }
1568                 regp->head |= NV_CRTC_FSEL_I2C;
1569         }
1570
1571         /* This is not what nv does, but it is what the blob does (for nv4x at least) */
1572         /* This fixes my cursor corruption issue */
1573         regp->cursorConfig = 0x0;
1574         if(mode->Flags & V_DBLSCAN)
1575                 regp->cursorConfig |= (1 << 4);
1576         if (pNv->alphaCursor) {
1577                 /* bit28 means we go into alpha blend mode and not rely on the current ROP */
1578                 regp->cursorConfig |= 0x14011000;
1579         } else {
1580                 regp->cursorConfig |= 0x02000000;
1581         }
1582
1583         /* Unblock some timings */
1584         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
1585         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
1586
1587         /* What is the purpose of this register? */
1588         /* 0x14 may be disabled? */
1589         regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
1590
1591         /* 0x00 is disabled, 0x22 crt and 0x88 dfp */
1592         /* 0x11 is LVDS? */
1593         if (is_fp) {
1594                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
1595         } else {
1596                 /* 0x20 is also seen sometimes, why? */
1597                 if (nv_crtc->head == 1) {
1598                         regp->CRTC[NV_VGA_CRTCX_3B] = 0x24;
1599                 } else {
1600                         regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
1601                 }
1602         }
1603
1604         /* These values seem to vary */
1605         if (nv_crtc->head == 1) {
1606                 regp->CRTC[NV_VGA_CRTCX_3C] = 0x0;
1607         } else {
1608                 regp->CRTC[NV_VGA_CRTCX_3C] = 0x70;
1609         }
1610
1611         /* 0x80 seems to be used very often, if not always */
1612         regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
1613
1614         if (nv_crtc->head == 1) {
1615                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x0;
1616         } else {
1617                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x1;
1618         }
1619
1620         if (is_fp)
1621                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x80;
1622
1623         /* Are these(0x55 and 0x56) also timing related registers, since disabling them does nothing? */
1624         regp->CRTC[NV_VGA_CRTCX_55] = 0x0;
1625
1626         /* Common values like 0x14 and 0x04 are converted to 0x10 and 0x00 */
1627         regp->CRTC[NV_VGA_CRTCX_56] = 0x0;
1628
1629         /* The blob seems to take the current value from crtc 0, add 4 to that and reuse the old value for crtc 1*/
1630         if (nv_crtc->head == 1) {
1631                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52;
1632         } else {
1633                 regp->CRTC[NV_VGA_CRTCX_52] = pNv->misc_info.crtc_0_reg_52 + 4;
1634         }
1635
1636         /* The exact purpose of this register is unknown, but we copy value from crtc0 */
1637         regp->unk81c = nvReadCRTC0(pNv, NV_CRTC_081C);
1638
1639         regp->unk830 = mode->CrtcVDisplay - 3;
1640         regp->unk834 = mode->CrtcVDisplay - 1;
1641
1642         /* This is what the blob does */
1643         regp->unk850 = nvReadCRTC(pNv, 0, NV_CRTC_0850);
1644
1645         /* Never ever modify gpio, unless you know very well what you're doing */
1646         regp->gpio = nvReadCRTC(pNv, 0, NV_CRTC_GPIO);
1647
1648         /* Switch to non-vga mode (the so called HSYNC mode) */
1649         regp->config = 0x2;
1650
1651         /*
1652          * Calculate the state that is common to all crtc's (stored in the state struct).
1653          */
1654         ErrorF("crtc %d %d %d\n", nv_crtc->crtc, mode->CrtcHDisplay, pScrn->displayWidth);
1655         nv_crtc_calc_state_ext(crtc,
1656                                 i,
1657                                 pScrn->displayWidth,
1658                                 mode->CrtcHDisplay,
1659                                 mode->CrtcVDisplay,
1660                                 adjusted_mode->Clock,
1661                                 mode->Flags);
1662
1663         /* Enable slaved mode */
1664         if (is_fp) {
1665                 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
1666         }
1667 }
1668
1669 static void
1670 nv_crtc_mode_set_ramdac_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
1671 {
1672         ScrnInfoPtr pScrn = crtc->scrn;
1673         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1674         NVCrtcRegPtr regp;
1675         NVPtr pNv = NVPTR(pScrn);
1676         NVFBLayout *pLayout = &pNv->CurrentLayout;
1677         Bool is_fp = FALSE;
1678         Bool is_lvds = FALSE;
1679         float aspect_ratio, panel_ratio;
1680         uint32_t h_scale, v_scale;
1681
1682         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1683
1684         xf86OutputPtr output = NVGetOutputFromCRTC(crtc);
1685         NVOutputPrivatePtr nv_output = NULL;
1686         if (output) {
1687                 nv_output = output->driver_private;
1688
1689                 if ((nv_output->type == OUTPUT_LVDS) || (nv_output->type == OUTPUT_TMDS))
1690                         is_fp = TRUE;
1691
1692                 if (nv_output->type == OUTPUT_LVDS)
1693                         is_lvds = TRUE;
1694         }
1695
1696         if (is_fp) {
1697                 regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
1698                 regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
1699                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HDisplay;
1700                 regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
1701                 regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
1702                 regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
1703                 regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
1704
1705                 regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
1706                 regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
1707                 regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VDisplay;
1708                 regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
1709                 regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
1710                 regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
1711                 regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
1712
1713                 ErrorF("Horizontal:\n");
1714                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_END]);
1715                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_horiz_regs[REG_DISP_TOTAL]);
1716                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_horiz_regs[REG_DISP_CRTC]);
1717                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_START]);
1718                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_SYNC_END]);
1719                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_START]);
1720                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_horiz_regs[REG_DISP_VALID_END]);
1721
1722                 ErrorF("Vertical:\n");
1723                 ErrorF("REG_DISP_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_END]);
1724                 ErrorF("REG_DISP_TOTAL: 0x%X\n", regp->fp_vert_regs[REG_DISP_TOTAL]);
1725                 ErrorF("REG_DISP_CRTC: 0x%X\n", regp->fp_vert_regs[REG_DISP_CRTC]);
1726                 ErrorF("REG_DISP_SYNC_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_START]);
1727                 ErrorF("REG_DISP_SYNC_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_SYNC_END]);
1728                 ErrorF("REG_DISP_VALID_START: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_START]);
1729                 ErrorF("REG_DISP_VALID_END: 0x%X\n", regp->fp_vert_regs[REG_DISP_VALID_END]);
1730         }
1731
1732         /*
1733         * bit0: positive vsync
1734         * bit4: positive hsync
1735         * bit8: enable center mode
1736         * bit9: enable native mode
1737         * bit26: a bit sometimes seen on some g70 cards
1738         * bit31: set for dual link LVDS
1739         * nv10reg contains a few more things, but i don't quite get what it all means.
1740         */
1741
1742         if (pNv->Architecture >= NV_ARCH_30) {
1743                 regp->fp_control = 0x01100000;
1744         } else {
1745                 regp->fp_control = 0x00000000;
1746         }
1747
1748         if (is_fp) {
1749                 regp->fp_control |= (1 << 28);
1750         } else {
1751                 regp->fp_control |= (2 << 28);
1752                 if (pNv->Architecture < NV_ARCH_30)
1753                         regp->fp_control |= (1 << 24);
1754         }
1755
1756         if (is_lvds && pNv->VBIOS.fp.dual_link) {
1757                 regp->fp_control |= (8 << 28);
1758         } else {
1759                 /* If the special bit exists, it exists on both ramdac's */
1760                 regp->fp_control |= nvReadRAMDAC0(pNv, NV_RAMDAC_FP_CONTROL) & (1 << 26);
1761         }
1762
1763         if (is_fp) {
1764                 if (nv_output->scaling_mode == 0) { /* panel needs to scale */
1765                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
1766                 /* This is also true for panel scaling, so we must put the panel scale check first */
1767                 } else if (mode->Clock == adjusted_mode->Clock) { /* native mode */
1768                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
1769                 } else { /* gpu needs to scale */
1770                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
1771                 }
1772         }
1773
1774         /* Deal with vsync/hsync polarity */
1775         if (is_fp) {
1776                 if (adjusted_mode->Flags & V_PVSYNC) {
1777                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
1778                 }
1779
1780                 if (adjusted_mode->Flags & V_PHSYNC) {
1781                         regp->fp_control |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
1782                 }
1783         } else {
1784                 /* The blob doesn't always do this, but often */
1785                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_VSYNC_DISABLE;
1786                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_HSYNC_DISABLE;
1787         }
1788
1789         if (is_fp) {
1790                 ErrorF("Pre-panel scaling\n");
1791                 ErrorF("panel-size:%dx%d\n", nv_output->fpWidth, nv_output->fpHeight);
1792                 panel_ratio = (nv_output->fpWidth)/(float)(nv_output->fpHeight);
1793                 ErrorF("panel_ratio=%f\n", panel_ratio);
1794                 aspect_ratio = (mode->HDisplay)/(float)(mode->VDisplay);
1795                 ErrorF("aspect_ratio=%f\n", aspect_ratio);
1796                 /* Scale factors is the so called 20.12 format, taken from Haiku */
1797                 h_scale = ((1 << 12) * mode->HDisplay)/nv_output->fpWidth;
1798                 v_scale = ((1 << 12) * mode->VDisplay)/nv_output->fpHeight;
1799                 ErrorF("h_scale=%d\n", h_scale);
1800                 ErrorF("v_scale=%d\n", v_scale);
1801
1802                 /* This can override HTOTAL and VTOTAL */
1803                 regp->debug_2 = 0;
1804
1805                 /* We want automatic scaling */
1806                 regp->debug_1 = 0;
1807
1808                 regp->fp_hvalid_start = 0;
1809                 regp->fp_hvalid_end = (nv_output->fpWidth - 1);
1810
1811                 regp->fp_vvalid_start = 0;
1812                 regp->fp_vvalid_end = (nv_output->fpHeight - 1);
1813
1814                 /* 0 = panel scaling */
1815                 if (nv_output->scaling_mode == 0) {
1816                         ErrorF("Flat panel is doing the scaling.\n");
1817                 } else {
1818                         ErrorF("GPU is doing the scaling.\n");
1819
1820                         /* 1 = fullscale gpu */
1821                         /* 2 = aspect ratio scaling */
1822                         /* 3 = no scaling */
1823                         if (nv_output->scaling_mode == 2) {
1824                                 /* GPU scaling happens automaticly at a ratio of 1.33 */
1825                                 /* A 1280x1024 panel has a ratio of 1.25, we don't want to scale that at 4:3 resolutions */
1826                                 if (h_scale != (1 << 12) && (panel_ratio > (aspect_ratio + 0.10))) {
1827                                         uint32_t diff;
1828
1829                                         ErrorF("Scaling resolution on a widescreen panel\n");
1830
1831                                         /* Scaling in both directions needs to the same */
1832                                         h_scale = v_scale;
1833
1834                                         /* Set a new horizontal scale factor and enable testmode (bit12) */
1835                                         regp->debug_1 = ((h_scale >> 1) & 0xfff) | (1 << 12);
1836
1837                                         diff = nv_output->fpWidth - (((1 << 12) * mode->HDisplay)/h_scale);
1838                                         regp->fp_hvalid_start = diff/2;
1839                                         regp->fp_hvalid_end = nv_output->fpWidth - (diff/2) - 1;
1840                                 }
1841
1842                                 /* Same scaling, just for panels with aspect ratio's smaller than 1 */
1843                                 if (v_scale != (1 << 12) && (panel_ratio < (aspect_ratio - 0.10))) {
1844                                         uint32_t diff;
1845
1846                                         ErrorF("Scaling resolution on a portrait panel\n");
1847
1848                                         /* Scaling in both directions needs to the same */
1849                                         v_scale = h_scale;
1850
1851                                         /* Set a new vertical scale factor and enable testmode (bit28) */
1852                                         regp->debug_1 = (((v_scale >> 1) & 0xfff) << 16) | (1 << (12 + 16));
1853
1854                                         diff = nv_output->fpHeight - (((1 << 12) * mode->VDisplay)/v_scale);
1855                                         regp->fp_vvalid_start = diff/2;
1856                                         regp->fp_vvalid_end = nv_output->fpHeight - (diff/2) - 1;
1857                                 }
1858                         }
1859                 }
1860
1861                 ErrorF("Post-panel scaling\n");
1862         }
1863
1864         if (pNv->Architecture >= NV_ARCH_10) {
1865                 /* Bios and blob don't seem to do anything (else) */
1866                 regp->nv10_cursync = (1<<25);
1867         }
1868
1869         /* These are the common blob values, minus a few fp specific bit's */
1870         /* Let's keep the TMDS pll and fpclock running in all situations */
1871         regp->debug_0 = 0x1101100;
1872
1873         if (is_fp && nv_output->scaling_mode != 3) { /* !no_scale mode */
1874                 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_XSCALE_ENABLED;
1875                 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_YSCALE_ENABLED;
1876         } else if (is_fp) { /* no_scale mode, so we must center it */
1877                 uint32_t diff;
1878
1879                 diff = nv_output->fpWidth - mode->HDisplay;
1880                 regp->fp_hvalid_start = diff/2;
1881                 regp->fp_hvalid_end = (nv_output->fpWidth - diff/2 - 1);
1882
1883                 diff = nv_output->fpHeight - mode->VDisplay;
1884                 regp->fp_vvalid_start = diff/2;
1885                 regp->fp_vvalid_end = (nv_output->fpHeight - diff/2 - 1);
1886         }
1887
1888         /* Is this crtc bound or output bound? */
1889         /* Does the bios TMDS script try to change this sometimes? */
1890         if (is_fp) {
1891                 /* I am not completely certain, but seems to be set only for dfp's */
1892                 regp->debug_0 |= NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED;
1893         }
1894
1895         if (output)
1896                 ErrorF("output %d debug_0 %08X\n", nv_output->preferred_output, regp->debug_0);
1897
1898         /* Flatpanel support needs at least a NV10 */
1899         if(pNv->twoHeads) {
1900                 /* The blob does this differently. */
1901                 /* TODO: Find out what precisely and why. */
1902                 if(pNv->FPDither) {
1903                         if (pNv->NVArch == 0x11) {
1904                                 regp->dither = 0x00010000;
1905                         } else {
1906                                 regp->dither = 0x00000001;
1907                         }
1908                 }
1909         }
1910
1911         /* Kindly borrowed from haiku driver */
1912         /* bit4 and bit5 activate indirect mode trough color palette */
1913         switch (pLayout->depth) {
1914                 case 32:
1915                 case 16:
1916                         regp->general = 0x00101130;
1917                         break;
1918                 case 24:
1919                 case 15:
1920                         regp->general = 0x00100130;
1921                         break;
1922                 case 8:
1923                 default:
1924                         regp->general = 0x00101100;
1925                         break;
1926         }
1927
1928         if (pNv->alphaCursor) {
1929                 /* PIPE_LONG mode, something to do with the size of the cursor? */
1930                 regp->general |= (1<<29);
1931         }
1932
1933         /* Some values the blob sets */
1934         /* This may apply to the real ramdac that is being used (for crosswired situations) */
1935         /* Nevertheless, it's unlikely to cause many problems, since the values are equal for both */
1936         regp->unk_a20 = 0x0;
1937         regp->unk_a24 = 0xfffff;
1938         regp->unk_a34 = 0x1;
1939 }
1940
1941 /**
1942  * Sets up registers for the given mode/adjusted_mode pair.
1943  *
1944  * The clocks, CRTCs and outputs attached to this CRTC must be off.
1945  *
1946  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
1947  * be easily turned on/off after this.
1948  */
1949 static void
1950 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
1951                  DisplayModePtr adjusted_mode,
1952                  int x, int y)
1953 {
1954         ScrnInfoPtr pScrn = crtc->scrn;
1955         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
1956         NVPtr pNv = NVPTR(pScrn);
1957
1958         ErrorF("nv_crtc_mode_set is called for CRTC %d\n", nv_crtc->crtc);
1959
1960         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->crtc);
1961         xf86PrintModeline(pScrn->scrnIndex, mode);
1962         NVCrtcSetOwner(crtc);
1963
1964         nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
1965         nv_crtc_mode_set_regs(crtc, mode, adjusted_mode);
1966         nv_crtc_mode_set_ramdac_regs(crtc, mode, adjusted_mode);
1967
1968         /* Just in case */
1969         NVCrtcLockUnlock(crtc, FALSE);
1970
1971         NVVgaProtect(crtc, TRUE);
1972         nv_crtc_load_state_ext(crtc, &pNv->ModeReg, FALSE);
1973         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
1974         if (pNv->Architecture == NV_ARCH_40) {
1975                 nv40_crtc_load_state_pll(pNv, &pNv->ModeReg);
1976         } else {
1977                 nv_crtc_load_state_pll(pNv, &pNv->ModeReg);
1978         }
1979         nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
1980
1981         NVVgaProtect(crtc, FALSE);
1982
1983         NVCrtcSetBase(crtc, x, y);
1984
1985 #if X_BYTE_ORDER == X_BIG_ENDIAN
1986         /* turn on LFB swapping */
1987         {
1988                 unsigned char tmp;
1989
1990                 tmp = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING);
1991                 tmp |= (1 << 7);
1992                 NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_SWAPPING, tmp);
1993         }
1994 #endif
1995 }
1996
1997 void nv_crtc_save(xf86CrtcPtr crtc)
1998 {
1999         ScrnInfoPtr pScrn = crtc->scrn;
2000         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2001         NVPtr pNv = NVPTR(pScrn);
2002
2003         ErrorF("nv_crtc_save is called for CRTC %d\n", nv_crtc->crtc);
2004
2005         /* We just came back from terminal, so unlock */
2006         NVCrtcLockUnlock(crtc, FALSE);
2007
2008         NVCrtcSetOwner(crtc);
2009         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
2010         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
2011         if (pNv->Architecture == NV_ARCH_40) {
2012                 nv40_crtc_save_state_pll(pNv, &pNv->SavedReg);
2013         } else {
2014                 nv_crtc_save_state_pll(pNv, &pNv->SavedReg);
2015         }
2016         nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
2017 }
2018
2019 void nv_crtc_restore(xf86CrtcPtr crtc)
2020 {
2021         ScrnInfoPtr pScrn = crtc->scrn;
2022         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2023         NVPtr pNv = NVPTR(pScrn);
2024         RIVA_HW_STATE *state;
2025
2026         state = &pNv->SavedReg;
2027
2028         ErrorF("nv_crtc_restore is called for CRTC %d\n", nv_crtc->crtc);
2029
2030         NVCrtcSetOwner(crtc);
2031
2032         /* Just to be safe */
2033         NVCrtcLockUnlock(crtc, FALSE);
2034
2035         NVVgaProtect(crtc, TRUE);
2036         nv_crtc_load_state_ext(crtc, &pNv->SavedReg, TRUE);
2037         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
2038         if (pNv->Architecture == NV_ARCH_40) {
2039                 nv40_crtc_load_state_pll(pNv, &pNv->SavedReg);
2040         } else {
2041                 nv_crtc_load_state_pll(pNv, &pNv->SavedReg);
2042         }
2043         nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
2044         nvWriteVGA(pNv, NV_VGA_CRTCX_OWNER, pNv->vtOWNER);
2045         NVVgaProtect(crtc, FALSE);
2046
2047         /* We must lock the door if we leave ;-) */
2048         NVCrtcLockUnlock(crtc, TRUE);
2049 }
2050
2051 void nv_crtc_prepare(xf86CrtcPtr crtc)
2052 {
2053         ScrnInfoPtr pScrn = crtc->scrn;
2054         NVPtr pNv = NVPTR(pScrn);
2055         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2056
2057         ErrorF("nv_crtc_prepare is called for CRTC %d\n", nv_crtc->crtc);
2058
2059         crtc->funcs->dpms(crtc, DPMSModeOff);
2060
2061         /* Sync the engine before adjust mode */
2062         if (pNv->EXADriverPtr) {
2063                 exaMarkSync(pScrn->pScreen);
2064                 exaWaitSync(pScrn->pScreen);
2065         }
2066 }
2067
2068 void nv_crtc_commit(xf86CrtcPtr crtc)
2069 {
2070         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2071         ErrorF("nv_crtc_commit for CRTC %d\n", nv_crtc->crtc);
2072
2073         crtc->funcs->dpms (crtc, DPMSModeOn);
2074
2075         if (crtc->scrn->pScreen != NULL)
2076                 xf86_reload_cursors (crtc->scrn->pScreen);
2077 }
2078
2079 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
2080 {
2081         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2082         ErrorF("nv_crtc_lock is called for CRTC %d\n", nv_crtc->crtc);
2083
2084         return FALSE;
2085 }
2086
2087 static void nv_crtc_unlock(xf86CrtcPtr crtc)
2088 {
2089         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2090         ErrorF("nv_crtc_unlock is called for CRTC %d\n", nv_crtc->crtc);
2091 }
2092
2093 static void
2094 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
2095                                         int size)
2096 {
2097         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2098         ScrnInfoPtr pScrn = crtc->scrn;
2099         NVPtr pNv = NVPTR(pScrn);
2100         int i, j;
2101
2102         NVCrtcRegPtr regp;
2103         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2104
2105         switch (pNv->CurrentLayout.depth) {
2106         case 15:
2107                 /* R5G5B5 */
2108                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
2109                 for (i = 0; i < 32; i++) {
2110                         for (j = 0; j < 8; j++) {
2111                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2112                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
2113                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2114                         }
2115                 }
2116                 break;
2117         case 16:
2118                 /* R5G6B5 */
2119                 /* First deal with the 5 bit colors */
2120                 for (i = 0; i < 32; i++) {
2121                         for (j = 0; j < 8; j++) {
2122                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
2123                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
2124                         }
2125                 }
2126                 /* Now deal with the 6 bit color */
2127                 for (i = 0; i < 64; i++) {
2128                         for (j = 0; j < 4; j++) {
2129                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
2130                         }
2131                 }
2132                 break;
2133         default:
2134                 /* R8G8B8 */
2135                 for (i = 0; i < 256; i++) {
2136                         regp->DAC[i * 3] = red[i] >> 8;
2137                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
2138                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
2139                 }
2140                 break;
2141         }
2142
2143         NVCrtcLoadPalette(crtc);
2144 }
2145
2146 /* NV04-NV10 doesn't support alpha cursors */
2147 static const xf86CrtcFuncsRec nv_crtc_funcs = {
2148         .dpms = nv_crtc_dpms,
2149         .save = nv_crtc_save, /* XXX */
2150         .restore = nv_crtc_restore, /* XXX */
2151         .mode_fixup = nv_crtc_mode_fixup,
2152         .mode_set = nv_crtc_mode_set,
2153         .prepare = nv_crtc_prepare,
2154         .commit = nv_crtc_commit,
2155         .destroy = NULL, /* XXX */
2156         .lock = nv_crtc_lock,
2157         .unlock = nv_crtc_unlock,
2158         .set_cursor_colors = nv_crtc_set_cursor_colors,
2159         .set_cursor_position = nv_crtc_set_cursor_position,
2160         .show_cursor = nv_crtc_show_cursor,
2161         .hide_cursor = nv_crtc_hide_cursor,
2162         .load_cursor_image = nv_crtc_load_cursor_image,
2163         .gamma_set = nv_crtc_gamma_set,
2164 };
2165
2166 /* NV11 and up has support for alpha cursors. */
2167 /* Due to different maximum sizes we cannot allow it to use normal cursors */
2168 static const xf86CrtcFuncsRec nv11_crtc_funcs = {
2169         .dpms = nv_crtc_dpms,
2170         .save = nv_crtc_save, /* XXX */
2171         .restore = nv_crtc_restore, /* XXX */
2172         .mode_fixup = nv_crtc_mode_fixup,
2173         .mode_set = nv_crtc_mode_set,
2174         .prepare = nv_crtc_prepare,
2175         .commit = nv_crtc_commit,
2176         .destroy = NULL, /* XXX */
2177         .lock = nv_crtc_lock,
2178         .unlock = nv_crtc_unlock,
2179         .set_cursor_colors = NULL, /* Alpha cursors do not need this */
2180         .set_cursor_position = nv_crtc_set_cursor_position,
2181         .show_cursor = nv_crtc_show_cursor,
2182         .hide_cursor = nv_crtc_hide_cursor,
2183         .load_cursor_argb = nv_crtc_load_cursor_argb,
2184         .gamma_set = nv_crtc_gamma_set,
2185 };
2186
2187
2188 void
2189 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
2190 {
2191         NVPtr pNv = NVPTR(pScrn);
2192         xf86CrtcPtr crtc;
2193         NVCrtcPrivatePtr nv_crtc;
2194
2195         if (pNv->NVArch >= 0x11) {
2196                 crtc = xf86CrtcCreate (pScrn, &nv11_crtc_funcs);
2197         } else {
2198                 crtc = xf86CrtcCreate (pScrn, &nv_crtc_funcs);
2199         }
2200         if (crtc == NULL)
2201                 return;
2202
2203         nv_crtc = xnfcalloc (sizeof (NVCrtcPrivateRec), 1);
2204         nv_crtc->crtc = crtc_num;
2205         nv_crtc->head = crtc_num;
2206
2207         crtc->driver_private = nv_crtc;
2208
2209         NVCrtcLockUnlock(crtc, FALSE);
2210 }
2211
2212 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2213 {
2214     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2215     int i;
2216     NVCrtcRegPtr regp;
2217
2218     regp = &state->crtc_reg[nv_crtc->head];
2219
2220     NVWriteMiscOut(crtc, regp->MiscOutReg);
2221
2222     for (i = 1; i < 5; i++)
2223       NVWriteVgaSeq(crtc, i, regp->Sequencer[i]);
2224
2225     /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
2226     NVWriteVgaCrtc(crtc, 17, regp->CRTC[17] & ~0x80);
2227
2228     for (i = 0; i < 25; i++)
2229       NVWriteVgaCrtc(crtc, i, regp->CRTC[i]);
2230
2231     for (i = 0; i < 9; i++)
2232       NVWriteVgaGr(crtc, i, regp->Graphics[i]);
2233
2234     NVEnablePalette(crtc);
2235     for (i = 0; i < 21; i++)
2236       NVWriteVgaAttr(crtc, i, regp->Attribute[i]);
2237     NVDisablePalette(crtc);
2238
2239 }
2240
2241 static void nv_crtc_fix_nv40_hw_cursor(xf86CrtcPtr crtc)
2242 {
2243         /* TODO - implement this properly */
2244         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2245         ScrnInfoPtr pScrn = crtc->scrn;
2246         NVPtr pNv = NVPTR(pScrn);
2247
2248         if (pNv->Architecture == NV_ARCH_40) {  /* HW bug */
2249                 volatile CARD32 curpos = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS);
2250                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_CURSOR_POS, curpos);
2251         }
2252 }
2253 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override)
2254 {
2255     ScrnInfoPtr pScrn = crtc->scrn;
2256     NVPtr pNv = NVPTR(pScrn);
2257     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2258     NVCrtcRegPtr regp;
2259     int i;
2260
2261     regp = &state->crtc_reg[nv_crtc->head];
2262
2263     if(pNv->Architecture >= NV_ARCH_10) {
2264         if(pNv->twoHeads) {
2265            nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL, regp->head);
2266         }
2267         nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
2268         nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
2269         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
2270         nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
2271         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
2272         nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
2273         nvWriteMC(pNv, 0x1588, 0);
2274
2275         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
2276         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
2277         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO, regp->gpio);
2278         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0830, regp->unk830);
2279         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0834, regp->unk834);
2280         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_0850, regp->unk850);
2281         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_081C, regp->unk81c);
2282
2283         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG, regp->config);
2284
2285         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
2286         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
2287
2288         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
2289         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
2290         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_3C, regp->CRTC[NV_VGA_CRTCX_3C]);
2291         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
2292         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_4B, regp->CRTC[NV_VGA_CRTCX_4B]);
2293         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
2294         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_56, regp->CRTC[NV_VGA_CRTCX_56]);
2295         if (override) {
2296                 for (i = 0; i < 0x10; i++)
2297                         NVWriteVGACR5758(pNv, nv_crtc->head, i, regp->CR58[i]);
2298         }
2299         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
2300         NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
2301     }
2302
2303     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
2304     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
2305     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
2306     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
2307     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
2308     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
2309     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
2310     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
2311     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
2312     if(pNv->Architecture >= NV_ARCH_30) {
2313       NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
2314     }
2315
2316     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
2317     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
2318     nv_crtc_fix_nv40_hw_cursor(crtc);
2319     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
2320     NVWriteVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
2321
2322     nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_EN_0, 0);
2323     nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
2324
2325     pNv->CurrentState = state;
2326 }
2327
2328 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2329 {
2330     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2331     int i;
2332     NVCrtcRegPtr regp;
2333
2334     regp = &state->crtc_reg[nv_crtc->head];
2335
2336     regp->MiscOutReg = NVReadMiscOut(crtc);
2337
2338     for (i = 0; i < 25; i++)
2339         regp->CRTC[i] = NVReadVgaCrtc(crtc, i);
2340
2341     NVEnablePalette(crtc);
2342     for (i = 0; i < 21; i++)
2343         regp->Attribute[i] = NVReadVgaAttr(crtc, i);
2344     NVDisablePalette(crtc);
2345
2346     for (i = 0; i < 9; i++)
2347         regp->Graphics[i] = NVReadVgaGr(crtc, i);
2348
2349     for (i = 1; i < 5; i++)
2350         regp->Sequencer[i] = NVReadVgaSeq(crtc, i);
2351
2352 }
2353
2354 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2355 {
2356     ScrnInfoPtr pScrn = crtc->scrn;
2357     NVPtr pNv = NVPTR(pScrn);
2358     NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2359     NVCrtcRegPtr regp;
2360     int i;
2361
2362     regp = &state->crtc_reg[nv_crtc->head];
2363
2364     regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LCD);
2365     regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT0);
2366     regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_REPAINT1);
2367     regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_LSR);
2368     regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_PIXEL);
2369     regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_HEB);
2370     regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO1);
2371
2372     regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO0);
2373     regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM);
2374     if(pNv->Architecture >= NV_ARCH_30) {
2375          regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FIFO_LWM_NV30);
2376     }
2377     regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL0);
2378     regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL1);
2379     regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_CURCTL2);
2380     regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_INTERLACE);
2381
2382     regp->gpio = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_GPIO);
2383     regp->unk830 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0830);
2384     regp->unk834 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0834);
2385     regp->unk850 = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_0850);
2386     regp->unk81c = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_081C);
2387
2388         regp->config = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CONFIG);
2389
2390     if(pNv->Architecture >= NV_ARCH_10) {
2391         if(pNv->twoHeads) {
2392            regp->head     = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_FSEL);
2393            regp->crtcOwner = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_OWNER);
2394         }
2395         regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_EXTRA);
2396
2397         regp->cursorConfig = nvReadCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_CONFIG);
2398
2399         regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_26);
2400         regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3B);
2401         regp->CRTC[NV_VGA_CRTCX_3C] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_3C);
2402         regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_45);
2403         regp->CRTC[NV_VGA_CRTCX_4B] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_4B);
2404         regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_52);
2405         regp->CRTC[NV_VGA_CRTCX_56] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_56);
2406         for (i = 0; i < 0x10; i++)
2407                 regp->CR58[i] = NVReadVGACR5758(pNv, nv_crtc->head, i);
2408         regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_59);
2409         regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_BUFFER);
2410         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_HTIMING);
2411         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(crtc, NV_VGA_CRTCX_FP_VTIMING);
2412     }
2413 }
2414
2415 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2416 {
2417         ScrnInfoPtr pScrn = crtc->scrn;
2418         NVPtr pNv = NVPTR(pScrn);
2419         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2420         NVCrtcRegPtr regp;
2421         int i;
2422
2423         regp = &state->crtc_reg[nv_crtc->head];
2424
2425         regp->general = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL);
2426
2427         regp->fp_control        = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL);
2428         regp->debug_0   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0);
2429         regp->debug_1   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1);
2430         regp->debug_2   = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2);
2431
2432         regp->unk_a20 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20);
2433         regp->unk_a24 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24);
2434         regp->unk_a34 = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34);
2435
2436         if (pNv->NVArch == 0x11) {
2437                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11);
2438         } else if (pNv->twoHeads) {
2439                 regp->dither = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER);
2440         }
2441         regp->nv10_cursync = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC);
2442
2443         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2444
2445         for (i = 0; i < 7; i++) {
2446                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2447                 regp->fp_horiz_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2448         }
2449
2450         for (i = 0; i < 7; i++) {
2451                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2452                 regp->fp_vert_regs[i] = nvReadRAMDAC(pNv, nv_crtc->head, ramdac_reg);
2453         }
2454
2455         regp->fp_hvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START);
2456         regp->fp_hvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END);
2457         regp->fp_vvalid_start = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START);
2458         regp->fp_vvalid_end = nvReadRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END);
2459 }
2460
2461 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
2462 {
2463         ScrnInfoPtr pScrn = crtc->scrn;
2464         NVPtr pNv = NVPTR(pScrn);
2465         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2466         NVCrtcRegPtr regp;
2467         int i;
2468
2469         regp = &state->crtc_reg[nv_crtc->head];
2470
2471         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_GENERAL_CONTROL, regp->general);
2472
2473         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control);
2474         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_0, regp->debug_0);
2475         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
2476         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
2477
2478         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A20, regp->unk_a20);
2479         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A24, regp->unk_a24);
2480         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_A34, regp->unk_a34);
2481
2482         if (pNv->NVArch == 0x11) {
2483                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_DITHER_NV11, regp->dither);
2484         } else if (pNv->twoHeads) {
2485                 nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_DITHER, regp->dither);
2486         }
2487         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
2488
2489         /* The regs below are 0 for non-flatpanels, so you can load and save them */
2490
2491         for (i = 0; i < 7; i++) {
2492                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
2493                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_horiz_regs[i]);
2494         }
2495
2496         for (i = 0; i < 7; i++) {
2497                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
2498                 nvWriteRAMDAC(pNv, nv_crtc->head, ramdac_reg, regp->fp_vert_regs[i]);
2499         }
2500
2501         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_START, regp->fp_hvalid_start);
2502         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_HVALID_END, regp->fp_hvalid_end);
2503         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_START, regp->fp_vvalid_start);
2504         nvWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_VVALID_END, regp->fp_vvalid_end);
2505 }
2506
2507 void
2508 NVCrtcSetBase (xf86CrtcPtr crtc, int x, int y)
2509 {
2510         ScrnInfoPtr pScrn = crtc->scrn;
2511         NVPtr pNv = NVPTR(pScrn);
2512         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2513         NVFBLayout *pLayout = &pNv->CurrentLayout;
2514         CARD32 start = 0;
2515
2516         ErrorF("NVCrtcSetBase: x: %d y: %d\n", x, y);
2517
2518         start += ((y * pScrn->displayWidth + x) * (pLayout->bitsPerPixel/8));
2519         start += pNv->FB->offset;
2520
2521         /* 30 bits addresses in 32 bits according to haiku */
2522         nvWriteCRTC(pNv, nv_crtc->head, NV_CRTC_START, start & 0xfffffffc);
2523
2524         /* set NV4/NV10 byte adress: (bit0 - 1) */
2525         NVWriteVgaAttr(crtc, 0x13, (start & 0x3) << 1);
2526
2527         crtc->x = x;
2528         crtc->y = y;
2529 }
2530
2531 static void NVCrtcWriteDacMask(xf86CrtcPtr crtc, CARD8 value)
2532 {
2533   ScrnInfoPtr pScrn = crtc->scrn;
2534   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2535   NVPtr pNv = NVPTR(pScrn);
2536   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2537
2538   NV_WR08(pDACReg, VGA_DAC_MASK, value);
2539 }
2540
2541 static CARD8 NVCrtcReadDacMask(xf86CrtcPtr crtc)
2542 {
2543   ScrnInfoPtr pScrn = crtc->scrn;
2544   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2545   NVPtr pNv = NVPTR(pScrn);
2546   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2547
2548   return NV_RD08(pDACReg, VGA_DAC_MASK);
2549 }
2550
2551 static void NVCrtcWriteDacReadAddr(xf86CrtcPtr crtc, CARD8 value)
2552 {
2553   ScrnInfoPtr pScrn = crtc->scrn;
2554   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2555   NVPtr pNv = NVPTR(pScrn);
2556   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2557
2558   NV_WR08(pDACReg, VGA_DAC_READ_ADDR, value);
2559 }
2560
2561 static void NVCrtcWriteDacWriteAddr(xf86CrtcPtr crtc, CARD8 value)
2562 {
2563   ScrnInfoPtr pScrn = crtc->scrn;
2564   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2565   NVPtr pNv = NVPTR(pScrn);
2566   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2567
2568   NV_WR08(pDACReg, VGA_DAC_WRITE_ADDR, value);
2569 }
2570
2571 static void NVCrtcWriteDacData(xf86CrtcPtr crtc, CARD8 value)
2572 {
2573   ScrnInfoPtr pScrn = crtc->scrn;
2574   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2575   NVPtr pNv = NVPTR(pScrn);
2576   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2577
2578   NV_WR08(pDACReg, VGA_DAC_DATA, value);
2579 }
2580
2581 static CARD8 NVCrtcReadDacData(xf86CrtcPtr crtc, CARD8 value)
2582 {
2583   ScrnInfoPtr pScrn = crtc->scrn;
2584   NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2585   NVPtr pNv = NVPTR(pScrn);
2586   volatile CARD8 *pDACReg = nv_crtc->head ? pNv->PDIO1 : pNv->PDIO0;
2587
2588   return NV_RD08(pDACReg, VGA_DAC_DATA);
2589 }
2590
2591 void NVCrtcLoadPalette(xf86CrtcPtr crtc)
2592 {
2593         int i;
2594         NVCrtcPrivatePtr nv_crtc = crtc->driver_private;
2595         NVCrtcRegPtr regp;
2596         ScrnInfoPtr pScrn = crtc->scrn;
2597         NVPtr pNv = NVPTR(pScrn);
2598
2599         regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
2600
2601         NVCrtcSetOwner(crtc);
2602         NVCrtcWriteDacMask(crtc, 0xff);
2603         NVCrtcWriteDacWriteAddr(crtc, 0x00);
2604
2605         for (i = 0; i<768; i++) {
2606                 NVCrtcWriteDacData(crtc, regp->DAC[i]);
2607         }
2608         NVDisablePalette(crtc);
2609 }
2610
2611 void NVCrtcBlankScreen(xf86CrtcPtr crtc, Bool on)
2612 {
2613         unsigned char scrn;
2614
2615         NVCrtcSetOwner(crtc);
2616
2617         scrn = NVReadVgaSeq(crtc, 0x01);
2618         if (on) {
2619                 scrn &= ~0x20;
2620         } else {
2621                 scrn |= 0x20;
2622         }
2623
2624         NVVgaSeqReset(crtc, TRUE);
2625         NVWriteVgaSeq(crtc, 0x01, scrn);
2626         NVVgaSeqReset(crtc, FALSE);
2627 }
2628
2629 /*************************************************************************** \
2630 |*                                                                           *|
2631 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
2632 |*                                                                           *|
2633 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
2634 |*     international laws.  Users and possessors of this source code are     *|
2635 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
2636 |*     use this code in individual and commercial software.                  *|
2637 |*                                                                           *|
2638 |*     Any use of this source code must include,  in the user documenta-     *|
2639 |*     tion and  internal comments to the code,  notices to the end user     *|
2640 |*     as follows:                                                           *|
2641 |*                                                                           *|
2642 |*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
2643 |*                                                                           *|
2644 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
2645 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
2646 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
2647 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
2648 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
2649 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
2650 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
2651 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
2652 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
2653 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
2654 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
2655 |*                                                                           *|
2656 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
2657 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
2658 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
2659 |*     computer  software  documentation,"  as such  terms  are  used in     *|
2660 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
2661 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
2662 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
2663 |*     all U.S. Government End Users  acquire the source code  with only     *|
2664 |*     those rights set forth herein.                                        *|
2665 |*                                                                           *|
2666  \***************************************************************************/