git.oblomov.eu Git - nouveau/blob - src/nv_crtc.c

   1 /*
   2  * Copyright 1993-2003 NVIDIA, Corporation
   3  * Copyright 2006 Dave Airlie
   4  * Copyright 2007 Maarten Maathuis
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include "nv_include.h"
  27
  28 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  29 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override);
  30 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  31 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  32 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  33 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  34 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  35 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state);
  36
  37 static uint32_t NVCrtcReadCRTC(xf86CrtcPtr crtc, uint32_t reg)
  38 {
  39         ScrnInfoPtr pScrn = crtc->scrn;
  40         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
  41         NVPtr pNv = NVPTR(pScrn);
  42
  43         return NVReadCRTC(pNv, nv_crtc->head, reg);
  44 }
  45
  46 static void NVCrtcWriteCRTC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
  47 {
  48         ScrnInfoPtr pScrn = crtc->scrn;
  49         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
  50         NVPtr pNv = NVPTR(pScrn);
  51
  52         NVWriteCRTC(pNv, nv_crtc->head, reg, val);
  53 }
  54
  55 static uint32_t NVCrtcReadRAMDAC(xf86CrtcPtr crtc, uint32_t reg)
  56 {
  57         ScrnInfoPtr pScrn = crtc->scrn;
  58         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
  59         NVPtr pNv = NVPTR(pScrn);
  60
  61         return NVReadRAMDAC(pNv, nv_crtc->head, reg);
  62 }
  63
  64 static void NVCrtcWriteRAMDAC(xf86CrtcPtr crtc, uint32_t reg, uint32_t val)
  65 {
  66         ScrnInfoPtr pScrn = crtc->scrn;
  67         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
  68         NVPtr pNv = NVPTR(pScrn);
  69
  70         NVWriteRAMDAC(pNv, nv_crtc->head, reg, val);
  71 }
  72
  73 void NVCrtcLockUnlock(xf86CrtcPtr crtc, Bool lock)
  74 {
  75         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
  76         ScrnInfoPtr pScrn = crtc->scrn;
  77         NVPtr pNv = NVPTR(pScrn);
  78
  79         if (pNv->twoHeads)
  80                 NVSetOwner(pScrn, nv_crtc->head);
  81         NVLockVgaCrtc(pNv, nv_crtc->head, lock);
  82 }
  83
  84 /* Even though they are not yet used, i'm adding some notes about some of the 0x4000 regs */
  85 /* They are only valid for NV4x, appearantly reordered for NV5x */
  86 /* gpu pll: 0x4000 + 0x4004
  87  * unknown pll: 0x4008 + 0x400c
  88  * vpll1: 0x4010 + 0x4014
  89  * vpll2: 0x4018 + 0x401c
  90  * unknown pll: 0x4020 + 0x4024
  91  * unknown pll: 0x4038 + 0x403c
  92  * Some of the unknown's are probably memory pll's.
  93  * The vpll's use two set's of multipliers and dividers. I refer to them as a and b.
  94  * 1 and 2 refer to the registers of each pair. There is only one post divider.
  95  * Logic: clock = reference_clock * ((n(a) * n(b))/(m(a) * m(b))) >> p
  96  * 1) bit 0-7: familiar values, but redirected from were? (similar to PLL_SETUP_CONTROL)
  97  *     bit8: A switch that turns of the second divider and multiplier off.
  98  *     bit12: Also a switch, i haven't seen it yet.
  99  *     bit16-19: p-divider
 100  *     but 28-31: Something related to the mode that is used (see bit8).
 101  * 2) bit0-7: m-divider (a)
 102  *     bit8-15: n-multiplier (a)
 103  *     bit16-23: m-divider (b)
 104  *     bit24-31: n-multiplier (b)
 105  */
 106
 107 /* Modifying the gpu pll for example requires:
 108  * - Disable value 0x333 (inverse AND mask) on the 0xc040 register.
 109  * This is not needed for the vpll's which have their own bits.
 110  */
 111
 112 static void nv_crtc_save_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 113 {
 114         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 115         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
 116         NVPtr pNv = NVPTR(crtc->scrn);
 117
 118         if (nv_crtc->head) {
 119                 regp->vpll_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2);
 120                 if (pNv->twoStagePLL)
 121                         regp->vpll_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B);
 122         } else {
 123                 regp->vpll_a = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL);
 124                 if (pNv->twoStagePLL)
 125                         regp->vpll_b = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B);
 126         }
 127         if (pNv->twoHeads)
 128                 state->sel_clk = NVReadRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK);
 129         state->pllsel = NVReadRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT);
 130         if (pNv->Architecture == NV_ARCH_40)
 131                 state->reg580 = NVReadRAMDAC(pNv, 0, NV_RAMDAC_580);
 132 }
 133
 134 static void nv_crtc_load_state_pll(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 135 {
 136         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 137         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
 138         ScrnInfoPtr pScrn = crtc->scrn;
 139         NVPtr pNv = NVPTR(pScrn);
 140         uint32_t savedc040 = 0;
 141
 142         /* This sequence is important, the NV28 is very sensitive in this area. */
 143         /* Keep pllsel last and sel_clk first. */
 144         if (pNv->twoHeads) {
 145                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_SEL_CLK %08X\n", state->sel_clk);
 146                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, state->sel_clk);
 147         }
 148
 149         if (pNv->Architecture == NV_ARCH_40) {
 150                 savedc040 = nvReadMC(pNv, 0xc040);
 151
 152                 /* for vpll1 change bits 16 and 17 are disabled */
 153                 /* for vpll2 change bits 18 and 19 are disabled */
 154                 nvWriteMC(pNv, 0xc040, savedc040 & ~(3 << (16 + nv_crtc->head * 2)));
 155         }
 156
 157         if (nv_crtc->head) {
 158                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_VPLL2 %08X\n", regp->vpll_a);
 159                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2, regp->vpll_a);
 160                 if (pNv->twoStagePLL) {
 161                         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_VPLL2_B %08X\n", regp->vpll_b);
 162                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL2_B, regp->vpll_b);
 163                 }
 164         } else {
 165                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_VPLL %08X\n", regp->vpll_a);
 166                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL, regp->vpll_a);
 167                 if (pNv->twoStagePLL) {
 168                         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_VPLL_B %08X\n", regp->vpll_b);
 169                         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B, regp->vpll_b);
 170                 }
 171         }
 172
 173         if (pNv->Architecture == NV_ARCH_40) {
 174                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_580 %08X\n", state->reg580);
 175                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_580, state->reg580);
 176
 177                 /* We need to wait a while */
 178                 usleep(5000);
 179                 nvWriteMC(pNv, 0xc040, savedc040);
 180         }
 181
 182         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_PLL_SELECT %08X\n", state->pllsel);
 183         NVWriteRAMDAC(pNv, 0, NV_RAMDAC_PLL_SELECT, state->pllsel);
 184 }
 185
 186 /* Calculate extended mode parameters (SVGA) and save in a mode state structure */
 187 static void nv_crtc_calc_state_ext(xf86CrtcPtr crtc, DisplayModePtr mode, int dot_clock)
 188 {
 189         ScrnInfoPtr pScrn = crtc->scrn;
 190         NVPtr pNv = NVPTR(pScrn);
 191         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 192         RIVA_HW_STATE *state = &pNv->ModeReg;
 193         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
 194         struct pll_lims pll_lim;
 195         int NM1 = 0xbeef, NM2 = 0, log2P = 0, VClk = 0;
 196         uint32_t g70_pll_special_bits = 0;
 197         Bool nv4x_single_stage_pll_mode = FALSE;
 198         uint8_t arbitration0;
 199         uint16_t arbitration1;
 200         uint32_t cursor_start;
 201
 202         if (!get_pll_limits(pScrn, nv_crtc->head ? VPLL2 : VPLL1, &pll_lim))
 203                 return;
 204
 205         if (pNv->twoStagePLL || pNv->NVArch == 0x30 || pNv->NVArch == 0x35) {
 206                 if (dot_clock < pll_lim.vco1.maxfreq && pNv->NVArch > 0x40) { /* use a single VCO */
 207                         nv4x_single_stage_pll_mode = TRUE;
 208                         /* Turn the second set of divider and multiplier off */
 209                         /* Bogus data, the same nvidia uses */
 210                         NM2 = 0x11f;
 211                         VClk = getMNP_single(pScrn, &pll_lim, dot_clock, &NM1, &log2P);
 212                 } else
 213                         VClk = getMNP_double(pScrn, &pll_lim, dot_clock, &NM1, &NM2, &log2P);
 214         } else
 215                 VClk = getMNP_single(pScrn, &pll_lim, dot_clock, &NM1, &log2P);
 216
 217         /* Are these all the (relevant) G70 cards? */
 218         if (pNv->NVArch == 0x4B || pNv->NVArch == 0x46 || pNv->NVArch == 0x47 || pNv->NVArch == 0x49) {
 219                 /* This is a big guess, but should be reasonable until we can narrow it down. */
 220                 /* What exactly are the purpose of the upper 2 bits of pll_a and pll_b? */
 221                 if (nv4x_single_stage_pll_mode)
 222                         g70_pll_special_bits = 0x1;
 223                 else
 224                         g70_pll_special_bits = 0x3;
 225         }
 226
 227         if (pNv->NVArch == 0x30 || pNv->NVArch == 0x35)
 228                 /* See nvregisters.xml for details. */
 229                 regp->vpll_a = (NM2 & (0x18 << 8)) << 13 | (NM2 & (0x7 << 8)) << 11 | log2P << 16 | NV30_RAMDAC_ENABLE_VCO2 | (NM2 & 7) << 4 | NM1;
 230         else
 231                 regp->vpll_a = g70_pll_special_bits << 30 | log2P << 16 | NM1;
 232         regp->vpll_b = NV31_RAMDAC_ENABLE_VCO2 | NM2;
 233
 234         if (nv4x_single_stage_pll_mode) {
 235                 if (nv_crtc->head == 0)
 236                         state->reg580 |= NV_RAMDAC_580_VPLL1_ACTIVE;
 237                 else
 238                         state->reg580 |= NV_RAMDAC_580_VPLL2_ACTIVE;
 239         } else {
 240                 if (nv_crtc->head == 0)
 241                         state->reg580 &= ~NV_RAMDAC_580_VPLL1_ACTIVE;
 242                 else
 243                         state->reg580 &= ~NV_RAMDAC_580_VPLL2_ACTIVE;
 244         }
 245
 246         /* The NV40 seems to have more similarities to NV3x than other NV4x */
 247         if (pNv->NVArch < 0x41)
 248                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_NVPLL |
 249                                  NV_RAMDAC_PLL_SELECT_PLL_SOURCE_MPLL;
 250         /* The blob uses this always, so let's do the same */
 251         if (pNv->Architecture == NV_ARCH_40)
 252                 state->pllsel |= NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE;
 253
 254         if (nv_crtc->head == 1) {
 255                 if (!nv4x_single_stage_pll_mode)
 256                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 257                 else
 258                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2;
 259                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2;
 260         } else {
 261                 if (!nv4x_single_stage_pll_mode)
 262                         state->pllsel |= NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 263                 else
 264                         state->pllsel &= ~NV_RAMDAC_PLL_SELECT_VCLK_RATIO_DB2;
 265                 state->pllsel |= NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL;
 266         }
 267
 268         if ((!pNv->twoStagePLL && pNv->NVArch != 0x30 && pNv->NVArch != 0x35) || nv4x_single_stage_pll_mode)
 269                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vpll: n %d m %d log2p %d\n", NM1 >> 8, NM1 & 0xff, log2P);
 270         else
 271                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", NM1 >> 8, NM2 >> 8, NM1 & 0xff, NM2 & 0xff, log2P);
 272
 273         if (pNv->Architecture < NV_ARCH_30)
 274                 nv4_10UpdateArbitrationSettings(pScrn, VClk, pScrn->bitsPerPixel, &arbitration0, &arbitration1);
 275         else if ((pNv->Chipset & 0xfff0) == CHIPSET_C51 ||
 276                  (pNv->Chipset & 0xfff0) == CHIPSET_C512) {
 277                 arbitration0 = 128;
 278                 arbitration1 = 0x0480;
 279         } else
 280                 nv30UpdateArbitrationSettings(&arbitration0, &arbitration1);
 281
 282         regp->CRTC[NV_VGA_CRTCX_FIFO0] = arbitration0;
 283         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = arbitration1 & 0xff;
 284         if (pNv->Architecture >= NV_ARCH_30)
 285                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = arbitration1 >> 8;
 286
 287         if (pNv->Architecture == NV_ARCH_04)
 288                 cursor_start = 0x5E00 << 2;
 289         else
 290                 cursor_start = nv_crtc->head ? pNv->Cursor2->offset : pNv->Cursor->offset;
 291
 292         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = cursor_start >> 17;
 293         if (pNv->Architecture != NV_ARCH_04)
 294                 regp->CRTC[NV_VGA_CRTCX_CURCTL0] |= 0x80;
 295         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = (cursor_start >> 11) << 2;
 296         if (mode->Flags & V_DBLSCAN)
 297                 regp->CRTC[NV_VGA_CRTCX_CURCTL1] |= 2;
 298         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = cursor_start >> 24;
 299 }
 300
 301 static void
 302 nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
 303 {
 304         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 305         ScrnInfoPtr pScrn = crtc->scrn;
 306         NVPtr pNv = NVPTR(pScrn);
 307         unsigned char seq1 = 0, crtc17 = 0;
 308         unsigned char crtc1A;
 309
 310         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_dpms is called for CRTC %d with mode %d.\n", nv_crtc->head, mode);
 311
 312         if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */
 313                 return;
 314
 315         nv_crtc->last_dpms = mode;
 316
 317         if (pNv->twoHeads)
 318                 NVSetOwner(pScrn, nv_crtc->head);
 319
 320         crtc1A = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT1) & ~0xC0;
 321         switch(mode) {
 322                 case DPMSModeStandby:
 323                 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
 324                 seq1 = 0x20;
 325                 crtc17 = 0x80;
 326                 crtc1A |= 0x80;
 327                 break;
 328         case DPMSModeSuspend:
 329                 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
 330                 seq1 = 0x20;
 331                 crtc17 = 0x80;
 332                 crtc1A |= 0x40;
 333                 break;
 334         case DPMSModeOff:
 335                 /* Screen: Off; HSync: Off, VSync: Off */
 336                 seq1 = 0x20;
 337                 crtc17 = 0x00;
 338                 crtc1A |= 0xC0;
 339                 break;
 340         case DPMSModeOn:
 341         default:
 342                 /* Screen: On; HSync: On, VSync: On */
 343                 seq1 = 0x00;
 344                 crtc17 = 0x80;
 345                 break;
 346         }
 347
 348         NVVgaSeqReset(pNv, nv_crtc->head, true);
 349         /* Each head has it's own sequencer, so we can turn it off when we want */
 350         seq1 |= (NVReadVgaSeq(pNv, nv_crtc->head, 0x01) & ~0x20);
 351         NVWriteVgaSeq(pNv, nv_crtc->head, 0x1, seq1);
 352         crtc17 |= (NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_MODECTL) & ~0x80);
 353         usleep(10000);
 354         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_MODECTL, crtc17);
 355         NVVgaSeqReset(pNv, nv_crtc->head, false);
 356
 357         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT1, crtc1A);
 358 }
 359
 360 static Bool
 361 nv_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
 362                      DisplayModePtr adjusted_mode)
 363 {
 364         return TRUE;
 365 }
 366
 367 static void
 368 nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
 369 {
 370         ScrnInfoPtr pScrn = crtc->scrn;
 371         NVPtr pNv = NVPTR(pScrn);
 372         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 373         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 374
 375         /* Calculate our timings */
 376         int horizDisplay        = (mode->CrtcHDisplay >> 3)     - 1;
 377         int horizStart          = (mode->CrtcHSyncStart >> 3)   - 1;
 378         int horizEnd            = (mode->CrtcHSyncEnd >> 3)     - 1;
 379         int horizTotal          = (mode->CrtcHTotal >> 3)               - 5;
 380         int horizBlankStart     = (mode->CrtcHDisplay >> 3)             - 1;
 381         int horizBlankEnd       = (mode->CrtcHTotal >> 3)               - 1;
 382         int vertDisplay         = mode->CrtcVDisplay                    - 1;
 383         int vertStart           = mode->CrtcVSyncStart          - 1;
 384         int vertEnd             = mode->CrtcVSyncEnd                    - 1;
 385         int vertTotal           = mode->CrtcVTotal                      - 2;
 386         int vertBlankStart      = mode->CrtcVDisplay                    - 1;
 387         int vertBlankEnd        = mode->CrtcVTotal                      - 1;
 388
 389         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 390         bool fp_output = false;
 391         int i;
 392
 393         for (i = 0; i < xf86_config->num_output; i++) {
 394                 xf86OutputPtr output = xf86_config->output[i];
 395                 struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 396
 397                 if (output->crtc == crtc && (nv_encoder->dcb->type == OUTPUT_LVDS ||
 398                                              nv_encoder->dcb->type == OUTPUT_TMDS))
 399                         fp_output = true;
 400         }
 401
 402         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Mode clock: %d\n", mode->Clock);
 403         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Adjusted mode clock: %d\n", adjusted_mode->Clock);
 404
 405         if (fp_output) {
 406                 vertStart = vertTotal - 3;
 407                 vertEnd = vertTotal - 2;
 408                 vertBlankStart = vertStart;
 409                 horizStart = horizTotal - 5;
 410                 horizEnd = horizTotal - 2;
 411                 horizBlankEnd = horizTotal + 4;
 412                 if (pNv->overlayAdaptor && pNv->Architecture >= NV_ARCH_10)
 413                         /* This reportedly works around some video overlay bandwidth problems */
 414                         horizTotal += 2;
 415         }
 416
 417         if (mode->Flags & V_INTERLACE)
 418                 vertTotal |= 1;
 419
 420 #if 0
 421         ErrorF("horizDisplay: 0x%X \n", horizDisplay);
 422         ErrorF("horizStart: 0x%X \n", horizStart);
 423         ErrorF("horizEnd: 0x%X \n", horizEnd);
 424         ErrorF("horizTotal: 0x%X \n", horizTotal);
 425         ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
 426         ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
 427         ErrorF("vertDisplay: 0x%X \n", vertDisplay);
 428         ErrorF("vertStart: 0x%X \n", vertStart);
 429         ErrorF("vertEnd: 0x%X \n", vertEnd);
 430         ErrorF("vertTotal: 0x%X \n", vertTotal);
 431         ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
 432         ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
 433 #endif
 434
 435         /*
 436         * compute correct Hsync & Vsync polarity
 437         */
 438         if ((mode->Flags & (V_PHSYNC | V_NHSYNC))
 439                 && (mode->Flags & (V_PVSYNC | V_NVSYNC))) {
 440
 441                 regp->MiscOutReg = 0x23;
 442                 if (mode->Flags & V_NHSYNC) regp->MiscOutReg |= 0x40;
 443                 if (mode->Flags & V_NVSYNC) regp->MiscOutReg |= 0x80;
 444         } else {
 445                 int VDisplay = mode->VDisplay;
 446                 if (mode->Flags & V_DBLSCAN)
 447                         VDisplay *= 2;
 448                 if (mode->VScan > 1)
 449                         VDisplay *= mode->VScan;
 450                 if (VDisplay < 400)
 451                         regp->MiscOutReg = 0xA3;                /* +hsync -vsync */
 452                 else if (VDisplay < 480)
 453                         regp->MiscOutReg = 0x63;                /* -hsync +vsync */
 454                 else if (VDisplay < 768)
 455                         regp->MiscOutReg = 0xE3;                /* -hsync -vsync */
 456                 else
 457                         regp->MiscOutReg = 0x23;                /* +hsync +vsync */
 458         }
 459
 460         regp->MiscOutReg |= (mode->ClockIndex & 0x03) << 2;
 461
 462         /*
 463         * Time Sequencer
 464         */
 465         regp->Sequencer[0] = 0x00;
 466         /* 0x20 disables the sequencer */
 467         if (mode->Flags & V_CLKDIV2)
 468                 regp->Sequencer[1] = 0x29;
 469         else
 470                 regp->Sequencer[1] = 0x21;
 471         regp->Sequencer[2] = 0x0F;
 472         regp->Sequencer[3] = 0x00;                     /* Font select */
 473         regp->Sequencer[4] = 0x0E;                             /* Misc */
 474
 475         /*
 476         * CRTC Controller
 477         */
 478         regp->CRTC[NV_VGA_CRTCX_HTOTAL]  = Set8Bits(horizTotal);
 479         regp->CRTC[NV_VGA_CRTCX_HDISPE]  = Set8Bits(horizDisplay);
 480         regp->CRTC[NV_VGA_CRTCX_HBLANKS]  = Set8Bits(horizBlankStart);
 481         regp->CRTC[NV_VGA_CRTCX_HBLANKE]  = SetBitField(horizBlankEnd,4:0,4:0)
 482                                 | SetBit(7);
 483         regp->CRTC[NV_VGA_CRTCX_HSYNCS]  = Set8Bits(horizStart);
 484         regp->CRTC[NV_VGA_CRTCX_HSYNCE]  = SetBitField(horizBlankEnd,5:5,7:7)
 485                                 | SetBitField(horizEnd,4:0,4:0);
 486         regp->CRTC[NV_VGA_CRTCX_VTOTAL]  = SetBitField(vertTotal,7:0,7:0);
 487         regp->CRTC[NV_VGA_CRTCX_OVERFLOW]  = SetBitField(vertTotal,8:8,0:0)
 488                                 | SetBitField(vertDisplay,8:8,1:1)
 489                                 | SetBitField(vertStart,8:8,2:2)
 490                                 | SetBitField(vertBlankStart,8:8,3:3)
 491                                 | SetBit(4)
 492                                 | SetBitField(vertTotal,9:9,5:5)
 493                                 | SetBitField(vertDisplay,9:9,6:6)
 494                                 | SetBitField(vertStart,9:9,7:7);
 495         regp->CRTC[NV_VGA_CRTCX_PRROWSCN]  = 0x00;
 496         regp->CRTC[NV_VGA_CRTCX_MAXSCLIN]  = SetBitField(vertBlankStart,9:9,5:5)
 497                                 | SetBit(6)
 498                                 | ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00);
 499         regp->CRTC[NV_VGA_CRTCX_VGACURSTART] = 0x00;
 500         regp->CRTC[NV_VGA_CRTCX_VGACUREND] = 0x00;
 501         regp->CRTC[NV_VGA_CRTCX_FBSTADDH] = 0x00;
 502         regp->CRTC[NV_VGA_CRTCX_FBSTADDL] = 0x00;
 503         regp->CRTC[0xe] = 0x00;
 504         regp->CRTC[0xf] = 0x00;
 505         regp->CRTC[NV_VGA_CRTCX_VSYNCS] = Set8Bits(vertStart);
 506         /* What is the meaning of bit5, it is empty in the vga spec. */
 507         regp->CRTC[NV_VGA_CRTCX_VSYNCE] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
 508         regp->CRTC[NV_VGA_CRTCX_VDISPE] = Set8Bits(vertDisplay);
 509         /* framebuffer can be larger than crtc scanout area. */
 510         regp->CRTC[NV_VGA_CRTCX_PITCHL] = pScrn->displayWidth / 8 * pScrn->bitsPerPixel / 8;
 511         regp->CRTC[NV_VGA_CRTCX_UNDERLINE] = 0x00;
 512         regp->CRTC[NV_VGA_CRTCX_VBLANKS] = Set8Bits(vertBlankStart);
 513         regp->CRTC[NV_VGA_CRTCX_VBLANKE] = Set8Bits(vertBlankEnd);
 514         /* 0x80 enables the sequencer, we don't want that */
 515         regp->CRTC[NV_VGA_CRTCX_MODECTL] = 0xC3 & ~0x80;
 516         regp->CRTC[NV_VGA_CRTCX_LINECOMP] = 0xff;
 517
 518         /*
 519          * Some extended CRTC registers (they are not saved with the rest of the vga regs).
 520          */
 521
 522         /* framebuffer can be larger than crtc scanout area. */
 523         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = ((pScrn->displayWidth / 8 * pScrn->bitsPerPixel / 8) & 0x700) >> 3;
 524         regp->CRTC[NV_VGA_CRTCX_REPAINT1] = mode->CrtcHDisplay < 1280 ? 0x04 : 0x00;
 525         regp->CRTC[NV_VGA_CRTCX_LSR] = SetBitField(horizBlankEnd,6:6,4:4)
 526                                 | SetBitField(vertBlankStart,10:10,3:3)
 527                                 | SetBitField(vertStart,10:10,2:2)
 528                                 | SetBitField(vertDisplay,10:10,1:1)
 529                                 | SetBitField(vertTotal,10:10,0:0);
 530
 531         regp->CRTC[NV_VGA_CRTCX_HEB] = SetBitField(horizTotal,8:8,0:0)
 532                                 | SetBitField(horizDisplay,8:8,1:1)
 533                                 | SetBitField(horizBlankStart,8:8,2:2)
 534                                 | SetBitField(horizStart,8:8,3:3);
 535
 536         regp->CRTC[NV_VGA_CRTCX_EXTRA] = SetBitField(vertTotal,11:11,0:0)
 537                                 | SetBitField(vertDisplay,11:11,2:2)
 538                                 | SetBitField(vertStart,11:11,4:4)
 539                                 | SetBitField(vertBlankStart,11:11,6:6);
 540
 541         if(mode->Flags & V_INTERLACE) {
 542                 horizTotal = (horizTotal >> 1) & ~1;
 543                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = Set8Bits(horizTotal);
 544                 regp->CRTC[NV_VGA_CRTCX_HEB] |= SetBitField(horizTotal,8:8,4:4);
 545         } else
 546                 regp->CRTC[NV_VGA_CRTCX_INTERLACE] = 0xff;  /* interlace off */
 547
 548         /*
 549         * Graphics Display Controller
 550         */
 551         regp->Graphics[0] = 0x00;
 552         regp->Graphics[1] = 0x00;
 553         regp->Graphics[2] = 0x00;
 554         regp->Graphics[3] = 0x00;
 555         regp->Graphics[4] = 0x00;
 556         regp->Graphics[5] = 0x40; /* 256 color mode */
 557         regp->Graphics[6] = 0x05; /* map 64k mem + graphic mode */
 558         regp->Graphics[7] = 0x0F;
 559         regp->Graphics[8] = 0xFF;
 560
 561         regp->Attribute[0]  = 0x00; /* standard colormap translation */
 562         regp->Attribute[1]  = 0x01;
 563         regp->Attribute[2]  = 0x02;
 564         regp->Attribute[3]  = 0x03;
 565         regp->Attribute[4]  = 0x04;
 566         regp->Attribute[5]  = 0x05;
 567         regp->Attribute[6]  = 0x06;
 568         regp->Attribute[7]  = 0x07;
 569         regp->Attribute[8]  = 0x08;
 570         regp->Attribute[9]  = 0x09;
 571         regp->Attribute[10] = 0x0A;
 572         regp->Attribute[11] = 0x0B;
 573         regp->Attribute[12] = 0x0C;
 574         regp->Attribute[13] = 0x0D;
 575         regp->Attribute[14] = 0x0E;
 576         regp->Attribute[15] = 0x0F;
 577         regp->Attribute[16] = 0x01; /* Enable graphic mode */
 578         /* Non-vga */
 579         regp->Attribute[17] = 0x00;
 580         regp->Attribute[18] = 0x0F; /* enable all color planes */
 581         regp->Attribute[19] = 0x00;
 582         regp->Attribute[20] = 0x00;
 583 }
 584
 585 /**
 586  * Sets up registers for the given mode/adjusted_mode pair.
 587  *
 588  * The clocks, CRTCs and outputs attached to this CRTC must be off.
 589  *
 590  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
 591  * be easily turned on/off after this.
 592  */
 593 static void
 594 nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode)
 595 {
 596         ScrnInfoPtr pScrn = crtc->scrn;
 597         NVPtr pNv = NVPTR(pScrn);
 598         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 599         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 600         NVCrtcRegPtr savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
 601         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 602         bool lvds_output = false, tmds_output = false;
 603         int i;
 604
 605         for (i = 0; i < xf86_config->num_output; i++) {
 606                 xf86OutputPtr output = xf86_config->output[i];
 607                 struct nouveau_encoder *nv_encoder = to_nouveau_encoder(output);
 608
 609                 if (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_LVDS)
 610                         lvds_output = true;
 611                 if (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_TMDS)
 612                         tmds_output = true;
 613         }
 614
 615         /* Registers not directly related to the (s)vga mode */
 616
 617         /* bit2 = 0 -> fine pitched crtc granularity */
 618         /* The rest disables double buffering on CRTC access */
 619         regp->CRTC[NV_VGA_CRTCX_BUFFER] = 0xfa;
 620
 621         /* the blob sometimes sets |= 0x10 (which is the same as setting |=
 622          * 1 << 30 on 0x60.830), for no apparent reason */
 623         regp->CRTC[NV_VGA_CRTCX_59] = 0x0;
 624         if (tmds_output && pNv->Architecture < NV_ARCH_40)
 625                 regp->CRTC[NV_VGA_CRTCX_59] |= 0x1;
 626
 627         /* What is the meaning of this register? */
 628         /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
 629         regp->CRTC[NV_VGA_CRTCX_FIFO1] = savep->CRTC[NV_VGA_CRTCX_FIFO1] & ~(1<<5);
 630
 631         regp->head = 0;
 632         /* Except for rare conditions I2C is enabled on the primary crtc */
 633         if (nv_crtc->head == 0)
 634                 regp->head |= NV_CRTC_FSEL_I2C;
 635         /* Set overlay to desired crtc. */
 636         if (pNv->overlayAdaptor) {
 637                 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(pNv);
 638                 if (pPriv->overlayCRTC == nv_crtc->head)
 639                         regp->head |= NV_CRTC_FSEL_OVERLAY;
 640         }
 641
 642         /* This is not what nv does, but it is what the blob does (for nv4x at least) */
 643         /* This fixes my cursor corruption issue */
 644         regp->cursorConfig = 0x0;
 645         if(mode->Flags & V_DBLSCAN)
 646                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_DOUBLE_SCAN;
 647         if (pNv->alphaCursor) {
 648                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_32BPP |
 649                                       NV_CRTC_CURSOR_CONFIG_64PIXELS |
 650                                       NV_CRTC_CURSOR_CONFIG_64LINES |
 651                                       NV_CRTC_CURSOR_CONFIG_ALPHA_BLEND;
 652         } else
 653                 regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_32LINES;
 654
 655         /* Unblock some timings */
 656         regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = 0;
 657         regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = 0;
 658
 659         /* What is the purpose of this register? */
 660         /* 0x14 may be disabled? */
 661         regp->CRTC[NV_VGA_CRTCX_26] = 0x20;
 662
 663         /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
 664         if (lvds_output)
 665                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x11;
 666         else if (tmds_output)
 667                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x88;
 668         else
 669                 regp->CRTC[NV_VGA_CRTCX_3B] = 0x22;
 670
 671         /* These values seem to vary */
 672         /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
 673         regp->CRTC[NV_VGA_CRTCX_SCRATCH4] = savep->CRTC[NV_VGA_CRTCX_SCRATCH4];
 674
 675         regp->CRTC[NV_VGA_CRTCX_45] = 0x80;
 676
 677         /* What does this do?:
 678          * bit0: crtc0
 679          * bit6: lvds
 680          * bit7: (only in X)
 681          */
 682         if (nv_crtc->head == 0)
 683                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x81;
 684         else
 685                 regp->CRTC[NV_VGA_CRTCX_4B] = 0x80;
 686
 687         if (lvds_output)
 688                 regp->CRTC[NV_VGA_CRTCX_4B] |= 0x40;
 689
 690         /* The blob seems to take the current value from crtc 0, add 4 to that
 691          * and reuse the old value for crtc 1 */
 692         regp->CRTC[NV_VGA_CRTCX_52] = pNv->SavedReg.crtc_reg[0].CRTC[NV_VGA_CRTCX_52];
 693         if (!nv_crtc->head)
 694                 regp->CRTC[NV_VGA_CRTCX_52] += 4;
 695
 696         regp->unk830 = mode->CrtcVDisplay - 3;
 697         regp->unk834 = mode->CrtcVDisplay - 1;
 698
 699         if (pNv->twoHeads)
 700                 /* This is what the blob does */
 701                 regp->unk850 = NVReadCRTC(pNv, 0, NV_CRTC_0850);
 702
 703         /* Never ever modify gpio, unless you know very well what you're doing */
 704         regp->gpio = NVReadCRTC(pNv, 0, NV_CRTC_GPIO);
 705
 706         if (pNv->twoHeads)
 707                 regp->gpio_ext = NVReadCRTC(pNv, 0, NV_CRTC_GPIO_EXT);
 708
 709         regp->config = 0x2; /* HSYNC mode */
 710
 711         /* Some misc regs */
 712         if (pNv->Architecture == NV_ARCH_40) {
 713                 regp->CRTC[NV_VGA_CRTCX_85] = 0xFF;
 714                 regp->CRTC[NV_VGA_CRTCX_86] = 0x1;
 715         }
 716
 717         regp->CRTC[NV_VGA_CRTCX_PIXEL] = (pScrn->depth + 1) / 8;
 718         /* Enable slaved mode */
 719         if (lvds_output || tmds_output)
 720                 regp->CRTC[NV_VGA_CRTCX_PIXEL] |= (1 << 7);
 721
 722         /* Generic PRAMDAC regs */
 723
 724         if (pNv->Architecture >= NV_ARCH_10)
 725                 /* Only bit that bios and blob set. */
 726                 regp->nv10_cursync = (1 << 25);
 727
 728         switch (pScrn->depth) {
 729                 case 24:
 730                 case 15:
 731                         regp->general = 0x00100130;
 732                         break;
 733                 case 16:
 734                 default:
 735                         regp->general = 0x00101130;
 736                         break;
 737         }
 738         if (pNv->alphaCursor)
 739                 /* PIPE_LONG mode, something to do with the size of the cursor? */
 740                 regp->general |= 1 << 29;
 741
 742         regp->unk_630 = 0; /* turn off green mode (tv test pattern?) */
 743
 744         /* Some values the blob sets */
 745         regp->unk_a20 = 0x0;
 746         regp->unk_a24 = 0xfffff;
 747         regp->unk_a34 = 0x1;
 748 }
 749
 750 /* this could be set in nv_output, but would require some rework of load/save */
 751 static void
 752 nv_crtc_mode_set_fp_regs(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode)
 753 {
 754         ScrnInfoPtr pScrn = crtc->scrn;
 755         NVPtr pNv = NVPTR(pScrn);
 756         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 757         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 758         NVCrtcRegPtr savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
 759         struct nouveau_encoder *nv_encoder = NULL;
 760         xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
 761         bool is_fp = false;
 762         bool is_lvds = false;
 763         uint32_t mode_ratio, panel_ratio;
 764         int i;
 765
 766         for (i = 0; i < xf86_config->num_output; i++) {
 767                 xf86OutputPtr output = xf86_config->output[i];
 768                 /* assuming one fp output per crtc seems ok */
 769                 nv_encoder = to_nouveau_encoder(output);
 770
 771                 if (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_LVDS)
 772                         is_lvds = true;
 773                 if (is_lvds || (output->crtc == crtc && nv_encoder->dcb->type == OUTPUT_TMDS)) {
 774                         is_fp = true;
 775                         break;
 776                 }
 777         }
 778         if (!is_fp)
 779                 return;
 780
 781         regp->fp_horiz_regs[REG_DISP_END] = adjusted_mode->HDisplay - 1;
 782         regp->fp_horiz_regs[REG_DISP_TOTAL] = adjusted_mode->HTotal - 1;
 783         if ((adjusted_mode->HSyncStart - adjusted_mode->HDisplay) >= pNv->VBIOS.digital_min_front_porch)
 784                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HDisplay;
 785         else
 786                 regp->fp_horiz_regs[REG_DISP_CRTC] = adjusted_mode->HSyncStart - pNv->VBIOS.digital_min_front_porch - 1;
 787         regp->fp_horiz_regs[REG_DISP_SYNC_START] = adjusted_mode->HSyncStart - 1;
 788         regp->fp_horiz_regs[REG_DISP_SYNC_END] = adjusted_mode->HSyncEnd - 1;
 789         regp->fp_horiz_regs[REG_DISP_VALID_START] = adjusted_mode->HSkew;
 790         regp->fp_horiz_regs[REG_DISP_VALID_END] = adjusted_mode->HDisplay - 1;
 791
 792         regp->fp_vert_regs[REG_DISP_END] = adjusted_mode->VDisplay - 1;
 793         regp->fp_vert_regs[REG_DISP_TOTAL] = adjusted_mode->VTotal - 1;
 794         regp->fp_vert_regs[REG_DISP_CRTC] = adjusted_mode->VTotal - 5 - 1;
 795         regp->fp_vert_regs[REG_DISP_SYNC_START] = adjusted_mode->VSyncStart - 1;
 796         regp->fp_vert_regs[REG_DISP_SYNC_END] = adjusted_mode->VSyncEnd - 1;
 797         regp->fp_vert_regs[REG_DISP_VALID_START] = 0;
 798         regp->fp_vert_regs[REG_DISP_VALID_END] = adjusted_mode->VDisplay - 1;
 799
 800         /*
 801         * bit0: positive vsync
 802         * bit4: positive hsync
 803         * bit8: enable center mode
 804         * bit9: enable native mode
 805         * bit24: 12/24 bit interface (12bit=on, 24bit=off)
 806         * bit26: a bit sometimes seen on some g70 cards
 807         * bit28: fp display enable bit
 808         * bit31: set for dual link LVDS
 809         */
 810
 811         regp->fp_control = (savep->fp_control & 0x04100000) |
 812                            NV_RAMDAC_FP_CONTROL_DISPEN_POS;
 813
 814         /* Deal with vsync/hsync polarity */
 815         /* LVDS screens do set this, but modes with +ve syncs are very rare */
 816         if (adjusted_mode->Flags & V_PVSYNC)
 817                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_VSYNC_POS;
 818         if (adjusted_mode->Flags & V_PHSYNC)
 819                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_HSYNC_POS;
 820
 821         if (nv_encoder->scaling_mode == SCALE_PANEL ||
 822             nv_encoder->scaling_mode == SCALE_NOSCALE) /* panel needs to scale */
 823                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_CENTER;
 824         /* This is also true for panel scaling, so we must put the panel scale check first */
 825         else if (mode->HDisplay == adjusted_mode->HDisplay &&
 826                  mode->VDisplay == adjusted_mode->VDisplay) /* native mode */
 827                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_NATIVE;
 828         else /* gpu needs to scale */
 829                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_MODE_SCALE;
 830
 831         if (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
 832                 regp->fp_control |= NV_RAMDAC_FP_CONTROL_WIDTH_12;
 833
 834         if (is_lvds && pNv->VBIOS.fp.dual_link)
 835                 regp->fp_control |= (8 << 28);
 836
 837         /* Use the generic value, and enable x-scaling, y-scaling, and the TMDS enable bit */
 838         regp->debug_0 = 0x01101191;
 839         /* We want automatic scaling */
 840         regp->debug_1 = 0;
 841         /* This can override HTOTAL and VTOTAL */
 842         regp->debug_2 = 0;
 843
 844         /* Use 20.12 fixed point format to avoid floats */
 845         mode_ratio = (1 << 12) * mode->HDisplay / mode->VDisplay;
 846         panel_ratio = (1 << 12) * adjusted_mode->HDisplay / adjusted_mode->VDisplay;
 847         /* if ratios are equal, SCALE_ASPECT will automatically (and correctly)
 848          * get treated the same as SCALE_FULLSCREEN */
 849         if (nv_encoder->scaling_mode == SCALE_ASPECT && mode_ratio != panel_ratio) {
 850                 uint32_t diff, scale;
 851
 852                 if (mode_ratio < panel_ratio) {
 853                         /* vertical needs to expand to glass size (automatic)
 854                          * horizontal needs to be scaled at vertical scale factor
 855                          * to maintain aspect */
 856
 857                         scale = (1 << 12) * mode->VDisplay / adjusted_mode->VDisplay;
 858                         regp->debug_1 = 1 << 12 | ((scale >> 1) & 0xfff);
 859
 860                         /* restrict area of screen used, horizontally */
 861                         diff = adjusted_mode->HDisplay -
 862                                adjusted_mode->VDisplay * mode_ratio / (1 << 12);
 863                         regp->fp_horiz_regs[REG_DISP_VALID_START] += diff / 2;
 864                         regp->fp_horiz_regs[REG_DISP_VALID_END] -= diff / 2;
 865                 }
 866
 867                 if (mode_ratio > panel_ratio) {
 868                         /* horizontal needs to expand to glass size (automatic)
 869                          * vertical needs to be scaled at horizontal scale factor
 870                          * to maintain aspect */
 871
 872                         scale = (1 << 12) * mode->HDisplay / adjusted_mode->HDisplay;
 873                         regp->debug_1 = 1 << 28 | ((scale >> 1) & 0xfff) << 16;
 874
 875                         /* restrict area of screen used, vertically */
 876                         diff = adjusted_mode->VDisplay -
 877                                (1 << 12) * adjusted_mode->HDisplay / mode_ratio;
 878                         regp->fp_vert_regs[REG_DISP_VALID_START] += diff / 2;
 879                         regp->fp_vert_regs[REG_DISP_VALID_END] -= diff / 2;
 880                 }
 881         }
 882
 883         /* Flatpanel support needs at least a NV10 */
 884         if (pNv->twoHeads) {
 885                 /* Output property. */
 886                 if (nv_encoder && nv_encoder->dithering) {
 887                         if (pNv->NVArch == 0x11)
 888                                 regp->dither = savep->dither | 0x00010000;
 889                         else {
 890                                 int i;
 891                                 regp->dither = savep->dither | 0x00000001;
 892                                 for (i = 0; i < 3; i++) {
 893                                         regp->dither_regs[i] = 0xe4e4e4e4;
 894                                         regp->dither_regs[i + 3] = 0x44444444;
 895                                 }
 896                         }
 897                 } else {
 898                         if (pNv->NVArch != 0x11) {
 899                                 /* reset them */
 900                                 int i;
 901                                 for (i = 0; i < 3; i++) {
 902                                         regp->dither_regs[i] = savep->dither_regs[i];
 903                                         regp->dither_regs[i + 3] = savep->dither_regs[i + 3];
 904                                 }
 905                         }
 906                         regp->dither = savep->dither;
 907                 }
 908         } else
 909                 regp->dither = savep->dither;
 910 }
 911
 912 /**
 913  * Sets up registers for the given mode/adjusted_mode pair.
 914  *
 915  * The clocks, CRTCs and outputs attached to this CRTC must be off.
 916  *
 917  * This shouldn't enable any clocks, CRTCs, or outputs, but they should
 918  * be easily turned on/off after this.
 919  */
 920 static void
 921 nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
 922                  DisplayModePtr adjusted_mode,
 923                  int x, int y)
 924 {
 925         ScrnInfoPtr pScrn = crtc->scrn;
 926         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 927         NVPtr pNv = NVPTR(pScrn);
 928
 929         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_mode_set is called for CRTC %d.\n", nv_crtc->head);
 930
 931         xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Mode on CRTC %d\n", nv_crtc->head);
 932         xf86PrintModeline(pScrn->scrnIndex, mode);
 933         if (pNv->twoHeads)
 934                 NVSetOwner(pScrn, nv_crtc->head);
 935
 936         nv_crtc_mode_set_vga(crtc, mode, adjusted_mode);
 937
 938         /* calculated in output_prepare, nv40 needs it written before calculating PLLs */
 939         if (pNv->Architecture == NV_ARCH_40) {
 940                 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Writing NV_RAMDAC_SEL_CLK %08X\n", pNv->ModeReg.sel_clk);
 941                 NVWriteRAMDAC(pNv, 0, NV_RAMDAC_SEL_CLK, pNv->ModeReg.sel_clk);
 942         }
 943         nv_crtc_mode_set_regs(crtc, mode);
 944         nv_crtc_mode_set_fp_regs(crtc, mode, adjusted_mode);
 945         nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->Clock);
 946
 947         NVVgaProtect(pNv, nv_crtc->head, true);
 948         nv_crtc_load_state_ramdac(crtc, &pNv->ModeReg);
 949         nv_crtc_load_state_ext(crtc, &pNv->ModeReg, FALSE);
 950         nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
 951         nv_crtc_load_state_vga(crtc, &pNv->ModeReg);
 952         nv_crtc_load_state_pll(crtc, &pNv->ModeReg);
 953
 954         NVVgaProtect(pNv, nv_crtc->head, false);
 955
 956         NVCrtcSetBase(crtc, x, y);
 957
 958 #if X_BYTE_ORDER == X_BIG_ENDIAN
 959         /* turn on LFB swapping */
 960         {
 961                 unsigned char tmp;
 962
 963                 tmp = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_SWAPPING);
 964                 tmp |= (1 << 7);
 965                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_SWAPPING, tmp);
 966         }
 967 #endif
 968 }
 969
 970 static void nv_crtc_save(xf86CrtcPtr crtc)
 971 {
 972         ScrnInfoPtr pScrn = crtc->scrn;
 973         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 974         NVPtr pNv = NVPTR(pScrn);
 975
 976         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_save is called for CRTC %d.\n", nv_crtc->head);
 977
 978         /* We just came back from terminal, so unlock */
 979         NVCrtcLockUnlock(crtc, FALSE);
 980
 981         nv_crtc_save_state_ramdac(crtc, &pNv->SavedReg);
 982         nv_crtc_save_state_vga(crtc, &pNv->SavedReg);
 983         nv_crtc_save_state_palette(crtc, &pNv->SavedReg);
 984         nv_crtc_save_state_ext(crtc, &pNv->SavedReg);
 985         nv_crtc_save_state_pll(crtc, &pNv->SavedReg);
 986
 987         /* init some state to saved value */
 988         pNv->ModeReg.reg580 = pNv->SavedReg.reg580;
 989         pNv->ModeReg.sel_clk = pNv->SavedReg.sel_clk & ~(0x5 << 16);
 990         pNv->ModeReg.crtc_reg[nv_crtc->head].CRTC[NV_VGA_CRTCX_LCD] = pNv->SavedReg.crtc_reg[nv_crtc->head].CRTC[NV_VGA_CRTCX_LCD];
 991 }
 992
 993 static void nv_crtc_restore(xf86CrtcPtr crtc)
 994 {
 995         ScrnInfoPtr pScrn = crtc->scrn;
 996         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 997         NVPtr pNv = NVPTR(pScrn);
 998         RIVA_HW_STATE *state;
 999         NVCrtcRegPtr savep;
1000
1001         state = &pNv->SavedReg;
1002         savep = &pNv->SavedReg.crtc_reg[nv_crtc->head];
1003
1004         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_restore is called for CRTC %d.\n", nv_crtc->head);
1005
1006         /* Just to be safe */
1007         NVCrtcLockUnlock(crtc, FALSE);
1008
1009         NVVgaProtect(pNv, nv_crtc->head, true);
1010         nv_crtc_load_state_ramdac(crtc, &pNv->SavedReg);
1011         nv_crtc_load_state_ext(crtc, &pNv->SavedReg, TRUE);
1012         nv_crtc_load_state_palette(crtc, &pNv->SavedReg);
1013         nv_crtc_load_state_vga(crtc, &pNv->SavedReg);
1014         nv_crtc_load_state_pll(crtc, &pNv->SavedReg);
1015         NVVgaProtect(pNv, nv_crtc->head, false);
1016
1017         nv_crtc->last_dpms = NV_DPMS_CLEARED;
1018 }
1019
1020 static void nv_crtc_prepare(xf86CrtcPtr crtc)
1021 {
1022         ScrnInfoPtr pScrn = crtc->scrn;
1023         NVPtr pNv = NVPTR(pScrn);
1024         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1025
1026         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_prepare is called for CRTC %d.\n", nv_crtc->head);
1027
1028         /* Just in case */
1029         NVCrtcLockUnlock(crtc, 0);
1030
1031         crtc->funcs->dpms(crtc, DPMSModeOff);
1032
1033         /* Sync the engine before adjust mode */
1034         if (pNv->EXADriverPtr) {
1035                 exaMarkSync(pScrn->pScreen);
1036                 exaWaitSync(pScrn->pScreen);
1037         }
1038
1039         NVBlankScreen(pScrn, nv_crtc->head, true);
1040
1041         /* Some more preperation. */
1042         NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, 0x1); /* Go to non-vga mode/out of enhanced mode */
1043         if (pNv->Architecture == NV_ARCH_40) {
1044                 uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
1045                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
1046         }
1047 }
1048
1049 static void nv_crtc_commit(xf86CrtcPtr crtc)
1050 {
1051         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1052         ScrnInfoPtr pScrn = crtc->scrn;
1053         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_commit for CRTC %d.\n", nv_crtc->head);
1054
1055         crtc->funcs->dpms (crtc, DPMSModeOn);
1056
1057         if (crtc->scrn->pScreen != NULL) {
1058                 NVPtr pNv = NVPTR(crtc->scrn);
1059
1060                 xf86_reload_cursors (crtc->scrn->pScreen);
1061                 if (!pNv->alphaCursor) {
1062                         /* this works round the fact that xf86_reload_cursors
1063                          * will quite happily show the hw cursor when it knows
1064                          * the hardware can't do alpha, and the current cursor
1065                          * has an alpha channel
1066                          */
1067                         xf86ForceHWCursor(crtc->scrn->pScreen, 1);
1068                         xf86ForceHWCursor(crtc->scrn->pScreen, 0);
1069                 }
1070         }
1071 }
1072
1073 static void nv_crtc_destroy(xf86CrtcPtr crtc)
1074 {
1075         xfree(to_nouveau_crtc(crtc));
1076 }
1077
1078 static Bool nv_crtc_lock(xf86CrtcPtr crtc)
1079 {
1080         return FALSE;
1081 }
1082
1083 static void nv_crtc_unlock(xf86CrtcPtr crtc)
1084 {
1085 }
1086
1087 static void
1088 nv_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, CARD16 *blue,
1089                                         int size)
1090 {
1091         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1092         ScrnInfoPtr pScrn = crtc->scrn;
1093         NVPtr pNv = NVPTR(pScrn);
1094         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
1095         int i, j;
1096
1097         switch (pScrn->depth) {
1098         case 15:
1099                 /* R5G5B5 */
1100                 /* We've got 5 bit (32 values) colors and 256 registers for each color */
1101                 for (i = 0; i < 32; i++)
1102                         for (j = 0; j < 8; j++) {
1103                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1104                                 regp->DAC[(i*8 + j) * 3 + 1] = green[i] >> 8;
1105                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1106                         }
1107                 break;
1108         case 16:
1109                 /* R5G6B5 */
1110                 /* First deal with the 5 bit colors */
1111                 for (i = 0; i < 32; i++)
1112                         for (j = 0; j < 8; j++) {
1113                                 regp->DAC[(i*8 + j) * 3 + 0] = red[i] >> 8;
1114                                 regp->DAC[(i*8 + j) * 3 + 2] = blue[i] >> 8;
1115                         }
1116                 /* Now deal with the 6 bit color */
1117                 for (i = 0; i < 64; i++)
1118                         for (j = 0; j < 4; j++)
1119                                 regp->DAC[(i*4 + j) * 3 + 1] = green[i] >> 8;
1120                 break;
1121         default:
1122                 /* R8G8B8 */
1123                 for (i = 0; i < 256; i++) {
1124                         regp->DAC[i * 3] = red[i] >> 8;
1125                         regp->DAC[(i * 3) + 1] = green[i] >> 8;
1126                         regp->DAC[(i * 3) + 2] = blue[i] >> 8;
1127                 }
1128                 break;
1129         }
1130
1131         nv_crtc_load_state_palette(crtc, &pNv->ModeReg);
1132 }
1133
1134 /**
1135  * Allocates memory for a locked-in-framebuffer shadow of the given
1136  * width and height for this CRTC's rotated shadow framebuffer.
1137  */
1138
1139 static void *
1140 nv_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
1141 {
1142         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1143         ScrnInfoPtr pScrn = crtc->scrn;
1144 #if !NOUVEAU_EXA_PIXMAPS
1145         ScreenPtr pScreen = pScrn->pScreen;
1146 #endif /* !NOUVEAU_EXA_PIXMAPS */
1147         NVPtr pNv = NVPTR(pScrn);
1148         void *offset;
1149
1150         unsigned long rotate_pitch;
1151         int size, align = 64;
1152
1153         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_shadow_allocate is called.\n");
1154
1155         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
1156         size = rotate_pitch * height;
1157
1158         assert(nv_crtc->shadow == NULL);
1159 #if NOUVEAU_EXA_PIXMAPS
1160         if (nouveau_bo_new(pNv->dev, NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN,
1161                         align, size, &nv_crtc->shadow)) {
1162                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to allocate memory for shadow buffer!\n");
1163                 return NULL;
1164         }
1165
1166         if (nv_crtc->shadow && nouveau_bo_map(nv_crtc->shadow, NOUVEAU_BO_RDWR)) {
1167                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1168                                 "Failed to map shadow buffer.\n");
1169                 return NULL;
1170         }
1171
1172         offset = nv_crtc->shadow->map;
1173 #else
1174         nv_crtc->shadow = exaOffscreenAlloc(pScreen, size, align, TRUE, NULL, NULL);
1175         if (nv_crtc->shadow == NULL) {
1176                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1177                         "Couldn't allocate shadow memory for rotated CRTC.\n");
1178                 return NULL;
1179         }
1180         offset = pNv->FB->map + nv_crtc->shadow->offset;
1181 #endif /* NOUVEAU_EXA_PIXMAPS */
1182
1183         return offset;
1184 }
1185
1186 /**
1187  * Creates a pixmap for this CRTC's rotated shadow framebuffer.
1188  */
1189 static PixmapPtr
1190 nv_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
1191 {
1192         ScrnInfoPtr pScrn = crtc->scrn;
1193 #if NOUVEAU_EXA_PIXMAPS
1194         ScreenPtr pScreen = pScrn->pScreen;
1195         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1196 #endif /* NOUVEAU_EXA_PIXMAPS */
1197         unsigned long rotate_pitch;
1198         PixmapPtr rotate_pixmap;
1199 #if NOUVEAU_EXA_PIXMAPS
1200         struct nouveau_pixmap *nvpix;
1201 #endif /* NOUVEAU_EXA_PIXMAPS */
1202
1203         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_shadow_create is called.\n");
1204
1205         if (!data)
1206                 data = crtc->funcs->shadow_allocate (crtc, width, height);
1207
1208         rotate_pitch = pScrn->displayWidth * (pScrn->bitsPerPixel/8);
1209
1210 #if NOUVEAU_EXA_PIXMAPS
1211         /* Create a dummy pixmap, to get a private that will be accepted by the system.*/
1212         rotate_pixmap = pScreen->CreatePixmap(pScreen,
1213                                                                 0, /* width */
1214                                                                 0, /* height */
1215         #ifdef CREATE_PIXMAP_USAGE_SCRATCH /* there seems to have been no api bump */
1216                                                                 pScrn->depth,
1217                                                                 0);
1218         #else
1219                                                                 pScrn->depth);
1220         #endif /* CREATE_PIXMAP_USAGE_SCRATCH */
1221 #else
1222         rotate_pixmap = GetScratchPixmapHeader(pScrn->pScreen,
1223                                                                 width, height,
1224                                                                 pScrn->depth,
1225                                                                 pScrn->bitsPerPixel,
1226                                                                 rotate_pitch,
1227                                                                 data);
1228 #endif /* NOUVEAU_EXA_PIXMAPS */
1229
1230         if (rotate_pixmap == NULL) {
1231                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1232                         "Couldn't allocate shadow pixmap for rotated CRTC\n");
1233         }
1234
1235 #if NOUVEAU_EXA_PIXMAPS
1236         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
1237         if (!nvpix) {
1238                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No initial shadow private available for rotation.\n");
1239         } else {
1240                 nvpix->bo = nv_crtc->shadow;
1241                 nvpix->mapped = TRUE;
1242         }
1243
1244         /* Modify the pixmap to actually be the one we need. */
1245         pScreen->ModifyPixmapHeader(rotate_pixmap,
1246                                         width,
1247                                         height,
1248                                         pScrn->depth,
1249                                         pScrn->bitsPerPixel,
1250                                         rotate_pitch,
1251                                         data);
1252
1253         nvpix = exaGetPixmapDriverPrivate(rotate_pixmap);
1254         if (!nvpix || !nvpix->bo)
1255                 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No final shadow private available for rotation.\n");
1256 #endif /* NOUVEAU_EXA_PIXMAPS */
1257
1258         return rotate_pixmap;
1259 }
1260
1261 static void
1262 nv_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr rotate_pixmap, void *data)
1263 {
1264         ScrnInfoPtr pScrn = crtc->scrn;
1265         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1266         ScreenPtr pScreen = pScrn->pScreen;
1267
1268         xf86DrvMsg(pScrn->scrnIndex, X_INFO, "nv_crtc_shadow_destroy is called.\n");
1269
1270         if (rotate_pixmap) { /* This should also unmap the buffer object if relevant. */
1271                 pScreen->DestroyPixmap(rotate_pixmap);
1272         }
1273
1274 #if !NOUVEAU_EXA_PIXMAPS
1275         if (data && nv_crtc->shadow) {
1276                 exaOffscreenFree(pScreen, nv_crtc->shadow);
1277         }
1278 #endif /* !NOUVEAU_EXA_PIXMAPS */
1279
1280         nv_crtc->shadow = NULL;
1281 }
1282
1283 static const xf86CrtcFuncsRec nv_crtc_funcs = {
1284         .dpms = nv_crtc_dpms,
1285         .save = nv_crtc_save,
1286         .restore = nv_crtc_restore,
1287         .mode_fixup = nv_crtc_mode_fixup,
1288         .mode_set = nv_crtc_mode_set,
1289         .prepare = nv_crtc_prepare,
1290         .commit = nv_crtc_commit,
1291         .destroy = nv_crtc_destroy,
1292         .lock = nv_crtc_lock,
1293         .unlock = nv_crtc_unlock,
1294         .set_cursor_colors = NULL, /* Alpha cursors do not need this */
1295         .set_cursor_position = nv_crtc_set_cursor_position,
1296         .show_cursor = nv_crtc_show_cursor,
1297         .hide_cursor = nv_crtc_hide_cursor,
1298         .load_cursor_argb = nv_crtc_load_cursor_argb,
1299         .gamma_set = nv_crtc_gamma_set,
1300         .shadow_create = nv_crtc_shadow_create,
1301         .shadow_allocate = nv_crtc_shadow_allocate,
1302         .shadow_destroy = nv_crtc_shadow_destroy,
1303 };
1304
1305 void
1306 nv_crtc_init(ScrnInfoPtr pScrn, int crtc_num)
1307 {
1308         NVPtr pNv = NVPTR(pScrn);
1309         static xf86CrtcFuncsRec crtcfuncs;
1310         xf86CrtcPtr crtc;
1311         struct nouveau_crtc *nv_crtc;
1312         NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[crtc_num];
1313         int i;
1314
1315         crtcfuncs = nv_crtc_funcs;
1316
1317         /* NV04-NV10 doesn't support alpha cursors */
1318         if (pNv->NVArch < 0x11) {
1319                 crtcfuncs.set_cursor_colors = nv_crtc_set_cursor_colors;
1320                 crtcfuncs.load_cursor_image = nv_crtc_load_cursor_image;
1321                 crtcfuncs.load_cursor_argb = NULL;
1322         }
1323         if (pNv->NoAccel) {
1324                 crtcfuncs.shadow_create = NULL;
1325                 crtcfuncs.shadow_allocate = NULL;
1326                 crtcfuncs.shadow_destroy = NULL;
1327         }
1328
1329         if (!(crtc = xf86CrtcCreate(pScrn, &crtcfuncs)))
1330                 return;
1331
1332         if (!(nv_crtc = xcalloc(1, sizeof (struct nouveau_crtc)))) {
1333                 xf86CrtcDestroy(crtc);
1334                 return;
1335         }
1336
1337         nv_crtc->head = crtc_num;
1338         nv_crtc->last_dpms = NV_DPMS_CLEARED;
1339
1340         crtc->driver_private = nv_crtc;
1341
1342         /* Initialise the default LUT table. */
1343         for (i = 0; i < 256; i++) {
1344                 regp->DAC[i*3] = i;
1345                 regp->DAC[(i*3)+1] = i;
1346                 regp->DAC[(i*3)+2] = i;
1347         }
1348
1349         NVCrtcLockUnlock(crtc, FALSE);
1350 }
1351
1352 static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1353 {
1354         ScrnInfoPtr pScrn = crtc->scrn;
1355         NVPtr pNv = NVPTR(pScrn);
1356         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1357         int i;
1358         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
1359
1360         NVWritePVIO(pNv, nv_crtc->head, VGA_MISC_OUT_W, regp->MiscOutReg);
1361
1362         for (i = 0; i < 5; i++)
1363                 NVWriteVgaSeq(pNv, nv_crtc->head, i, regp->Sequencer[i]);
1364
1365         /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
1366         NVWriteVgaCrtc(pNv, nv_crtc->head, 17, regp->CRTC[17] & ~0x80);
1367
1368         for (i = 0; i < 25; i++)
1369                 NVWriteVgaCrtc(pNv, nv_crtc->head, i, regp->CRTC[i]);
1370
1371         for (i = 0; i < 9; i++)
1372                 NVWriteVgaGr(pNv, nv_crtc->head, i, regp->Graphics[i]);
1373
1374         NVSetEnablePalette(pNv, nv_crtc->head, true);
1375         for (i = 0; i < 21; i++)
1376                 NVWriteVgaAttr(pNv, nv_crtc->head, i, regp->Attribute[i]);
1377
1378         NVSetEnablePalette(pNv, nv_crtc->head, false);
1379 }
1380
1381 static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state, Bool override)
1382 {
1383         ScrnInfoPtr pScrn = crtc->scrn;
1384         NVPtr pNv = NVPTR(pScrn);
1385         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1386         NVCrtcRegPtr regp;
1387         int i;
1388
1389         regp = &state->crtc_reg[nv_crtc->head];
1390
1391         if (pNv->Architecture >= NV_ARCH_10) {
1392                 if (pNv->twoHeads)
1393                         /* setting FSEL *must* come before CRTCX_LCD, as writing CRTCX_LCD sets some
1394                          * bits (16 & 17) in FSEL that should not be overwritten by writing FSEL */
1395                         NVCrtcWriteCRTC(crtc, NV_CRTC_FSEL, regp->head);
1396
1397                 nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
1398                 nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
1399                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
1400                 nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
1401                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1402                 nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1403                 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(0), pNv->VRAMPhysicalSize - 1);
1404                 nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(1), pNv->VRAMPhysicalSize - 1);
1405                 nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, 0);
1406
1407                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_BUFFER, regp->CRTC[NV_VGA_CRTCX_BUFFER]);
1408                 NVCrtcWriteCRTC(crtc, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
1409                 NVCrtcWriteCRTC(crtc, NV_CRTC_0830, regp->unk830);
1410                 NVCrtcWriteCRTC(crtc, NV_CRTC_0834, regp->unk834);
1411                 if (pNv->Architecture == NV_ARCH_40) {
1412                         NVCrtcWriteCRTC(crtc, NV_CRTC_0850, regp->unk850);
1413                         NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO_EXT, regp->gpio_ext);
1414                 }
1415
1416                 if (pNv->Architecture == NV_ARCH_40) {
1417                         uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
1418                         if (regp->config == 0x2) /* enhanced "horizontal only" non-vga mode */
1419                                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 | 0x10000);
1420                         else
1421                                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
1422                 }
1423         }
1424
1425         NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, regp->config);
1426         NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO, regp->gpio);
1427
1428         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT0, regp->CRTC[NV_VGA_CRTCX_REPAINT0]);
1429         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT1, regp->CRTC[NV_VGA_CRTCX_REPAINT1]);
1430         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LSR, regp->CRTC[NV_VGA_CRTCX_LSR]);
1431         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_PIXEL, regp->CRTC[NV_VGA_CRTCX_PIXEL]);
1432         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LCD, regp->CRTC[NV_VGA_CRTCX_LCD]);
1433         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_HEB, regp->CRTC[NV_VGA_CRTCX_HEB]);
1434         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO1, regp->CRTC[NV_VGA_CRTCX_FIFO1]);
1435         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO0, regp->CRTC[NV_VGA_CRTCX_FIFO0]);
1436         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO_LWM, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM]);
1437         if (pNv->Architecture >= NV_ARCH_30)
1438                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO_LWM_NV30, regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30]);
1439
1440         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL0, regp->CRTC[NV_VGA_CRTCX_CURCTL0]);
1441         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL1, regp->CRTC[NV_VGA_CRTCX_CURCTL1]);
1442         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL2, regp->CRTC[NV_VGA_CRTCX_CURCTL2]);
1443         if (pNv->Architecture == NV_ARCH_40)
1444                 nv_fix_nv40_hw_cursor(pNv, nv_crtc->head);
1445         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_INTERLACE, regp->CRTC[NV_VGA_CRTCX_INTERLACE]);
1446
1447         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_26, regp->CRTC[NV_VGA_CRTCX_26]);
1448         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_3B, regp->CRTC[NV_VGA_CRTCX_3B]);
1449         NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_SCRATCH4, regp->CRTC[NV_VGA_CRTCX_SCRATCH4]);
1450         if (pNv->Architecture >= NV_ARCH_10) {
1451                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_EXTRA, regp->CRTC[NV_VGA_CRTCX_EXTRA]);
1452                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_45, regp->CRTC[NV_VGA_CRTCX_45]);
1453                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_4B, regp->CRTC[NV_VGA_CRTCX_4B]);
1454                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_52, regp->CRTC[NV_VGA_CRTCX_52]);
1455         }
1456         /* NV11 and NV20 stop at 0x52. */
1457         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
1458                 if (override)
1459                         for (i = 0; i < 0x10; i++)
1460                                 NVWriteVgaCrtc5758(pNv, nv_crtc->head, i, regp->CR58[i]);
1461
1462                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FP_HTIMING, regp->CRTC[NV_VGA_CRTCX_FP_HTIMING]);
1463                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FP_VTIMING, regp->CRTC[NV_VGA_CRTCX_FP_VTIMING]);
1464
1465                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_59, regp->CRTC[NV_VGA_CRTCX_59]);
1466
1467                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_85, regp->CRTC[NV_VGA_CRTCX_85]);
1468                 NVWriteVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_86, regp->CRTC[NV_VGA_CRTCX_86]);
1469         }
1470
1471         if (override)
1472                 NVCrtcWriteCRTC(crtc, NV_CRTC_START, regp->fb_start);
1473
1474         /* Setting 1 on this value gives you interrupts for every vblank period. */
1475         NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_EN_0, 0);
1476         NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
1477 }
1478
1479 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1480 {
1481         ScrnInfoPtr pScrn = crtc->scrn;
1482         NVPtr pNv = NVPTR(pScrn);
1483         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1484         int i;
1485         NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
1486
1487         regp->MiscOutReg = NVReadPVIO(pNv, nv_crtc->head, VGA_MISC_OUT_R);
1488
1489         for (i = 0; i < 25; i++)
1490                 regp->CRTC[i] = NVReadVgaCrtc(pNv, nv_crtc->head, i);
1491
1492         NVSetEnablePalette(pNv, nv_crtc->head, true);
1493         for (i = 0; i < 21; i++)
1494                 regp->Attribute[i] = NVReadVgaAttr(pNv, nv_crtc->head, i);
1495         NVSetEnablePalette(pNv, nv_crtc->head, false);
1496
1497         for (i = 0; i < 9; i++)
1498                 regp->Graphics[i] = NVReadVgaGr(pNv, nv_crtc->head, i);
1499
1500         for (i = 0; i < 5; i++)
1501                 regp->Sequencer[i] = NVReadVgaSeq(pNv, nv_crtc->head, i);
1502 }
1503
1504 static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1505 {
1506         ScrnInfoPtr pScrn = crtc->scrn;
1507         NVPtr pNv = NVPTR(pScrn);
1508         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1509         NVCrtcRegPtr regp;
1510         int i;
1511
1512         regp = &state->crtc_reg[nv_crtc->head];
1513
1514         regp->CRTC[NV_VGA_CRTCX_LCD] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LCD);
1515         regp->CRTC[NV_VGA_CRTCX_REPAINT0] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT0);
1516         regp->CRTC[NV_VGA_CRTCX_REPAINT1] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_REPAINT1);
1517         regp->CRTC[NV_VGA_CRTCX_LSR] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_LSR);
1518         regp->CRTC[NV_VGA_CRTCX_PIXEL] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_PIXEL);
1519         regp->CRTC[NV_VGA_CRTCX_HEB] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_HEB);
1520         regp->CRTC[NV_VGA_CRTCX_FIFO1] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO1);
1521
1522         regp->CRTC[NV_VGA_CRTCX_FIFO0] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO0);
1523         regp->CRTC[NV_VGA_CRTCX_FIFO_LWM] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO_LWM);
1524         regp->CRTC[NV_VGA_CRTCX_BUFFER] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_BUFFER);
1525         if (pNv->Architecture >= NV_ARCH_30)
1526                 regp->CRTC[NV_VGA_CRTCX_FIFO_LWM_NV30] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FIFO_LWM_NV30);
1527         regp->CRTC[NV_VGA_CRTCX_CURCTL0] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL0);
1528         regp->CRTC[NV_VGA_CRTCX_CURCTL1] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL1);
1529         regp->CRTC[NV_VGA_CRTCX_CURCTL2] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_CURCTL2);
1530         regp->CRTC[NV_VGA_CRTCX_INTERLACE] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_INTERLACE);
1531
1532         if (pNv->Architecture >= NV_ARCH_10) {
1533                 regp->unk830 = NVCrtcReadCRTC(crtc, NV_CRTC_0830);
1534                 regp->unk834 = NVCrtcReadCRTC(crtc, NV_CRTC_0834);
1535                 if (pNv->Architecture == NV_ARCH_40) {
1536                         regp->unk850 = NVCrtcReadCRTC(crtc, NV_CRTC_0850);
1537                         regp->gpio_ext = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO_EXT);
1538                 }
1539                 if (pNv->twoHeads) {
1540                         regp->head = NVCrtcReadCRTC(crtc, NV_CRTC_FSEL);
1541                         regp->crtcOwner = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_OWNER);
1542                 }
1543                 regp->cursorConfig = NVCrtcReadCRTC(crtc, NV_CRTC_CURSOR_CONFIG);
1544         }
1545
1546         regp->gpio = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO);
1547         regp->config = NVCrtcReadCRTC(crtc, NV_CRTC_CONFIG);
1548
1549         regp->CRTC[NV_VGA_CRTCX_26] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_26);
1550         regp->CRTC[NV_VGA_CRTCX_3B] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_3B);
1551         regp->CRTC[NV_VGA_CRTCX_SCRATCH4] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_SCRATCH4);
1552         if (pNv->Architecture >= NV_ARCH_10) {
1553                 regp->CRTC[NV_VGA_CRTCX_EXTRA] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_EXTRA);
1554                 regp->CRTC[NV_VGA_CRTCX_45] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_45);
1555                 regp->CRTC[NV_VGA_CRTCX_4B] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_4B);
1556                 regp->CRTC[NV_VGA_CRTCX_52] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_52);
1557         }
1558         /* NV11 and NV20 don't have this, they stop at 0x52. */
1559         if (pNv->NVArch >= 0x17 && pNv->twoHeads) {
1560                 for (i = 0; i < 0x10; i++)
1561                         regp->CR58[i] = NVReadVgaCrtc5758(pNv, nv_crtc->head, i);
1562
1563                 regp->CRTC[NV_VGA_CRTCX_59] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_59);
1564                 regp->CRTC[NV_VGA_CRTCX_FP_HTIMING] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FP_HTIMING);
1565                 regp->CRTC[NV_VGA_CRTCX_FP_VTIMING] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_FP_VTIMING);
1566
1567                 regp->CRTC[NV_VGA_CRTCX_85] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_85);
1568                 regp->CRTC[NV_VGA_CRTCX_86] = NVReadVgaCrtc(pNv, nv_crtc->head, NV_VGA_CRTCX_86);
1569         }
1570
1571         regp->fb_start = NVCrtcReadCRTC(crtc, NV_CRTC_START);
1572 }
1573
1574 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1575 {
1576         ScrnInfoPtr pScrn = crtc->scrn;
1577         NVPtr pNv = NVPTR(pScrn);
1578         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1579         NVCrtcRegPtr regp;
1580         int i;
1581
1582         regp = &state->crtc_reg[nv_crtc->head];
1583
1584         regp->general = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL);
1585
1586         if (pNv->twoHeads) {
1587                 if (pNv->NVArch >= 0x17)
1588                         regp->unk_630 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_630);
1589                 regp->fp_control        = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_CONTROL);
1590                 regp->debug_0   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_0);
1591                 regp->debug_1   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1);
1592                 regp->debug_2   = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2);
1593
1594                 regp->unk_a20 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A20);
1595                 regp->unk_a24 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A24);
1596                 regp->unk_a34 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_A34);
1597         }
1598
1599         if (pNv->NVArch == 0x11) {
1600                 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_DITHER_NV11);
1601         } else if (pNv->twoHeads) {
1602                 regp->dither = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_DITHER);
1603                 for (i = 0; i < 3; i++) {
1604                         regp->dither_regs[i] = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_850 + i * 4);
1605                         regp->dither_regs[i + 3] = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_FP_85C + i * 4);
1606                 }
1607         }
1608         if (pNv->Architecture >= NV_ARCH_10)
1609                 regp->nv10_cursync = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC);
1610
1611         /* The regs below are 0 for non-flatpanels, so you can load and save them */
1612
1613         for (i = 0; i < 7; i++) {
1614                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
1615                 regp->fp_horiz_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
1616         }
1617
1618         for (i = 0; i < 7; i++) {
1619                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
1620                 regp->fp_vert_regs[i] = NVCrtcReadRAMDAC(crtc, ramdac_reg);
1621         }
1622 }
1623
1624 static void nv_crtc_load_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1625 {
1626         ScrnInfoPtr pScrn = crtc->scrn;
1627         NVPtr pNv = NVPTR(pScrn);
1628         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1629         NVCrtcRegPtr regp;
1630         int i;
1631
1632         regp = &state->crtc_reg[nv_crtc->head];
1633
1634         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_GENERAL_CONTROL, regp->general);
1635
1636         if (pNv->twoHeads) {
1637                 if (pNv->NVArch >= 0x17)
1638                         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_630, regp->unk_630);
1639                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_CONTROL, regp->fp_control);
1640                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_0, regp->debug_0);
1641                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_1, regp->debug_1);
1642                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DEBUG_2, regp->debug_2);
1643                 if (pNv->NVArch == 0x30) { /* For unknown purposes. */
1644                         uint32_t reg890 = NVCrtcReadRAMDAC(crtc, NV30_RAMDAC_890);
1645                         NVCrtcWriteRAMDAC(crtc, NV30_RAMDAC_89C, reg890);
1646                 }
1647
1648                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A20, regp->unk_a20);
1649                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A24, regp->unk_a24);
1650                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_A34, regp->unk_a34);
1651         }
1652
1653         if (pNv->NVArch == 0x11)
1654                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_DITHER_NV11, regp->dither);
1655         else if (pNv->twoHeads) {
1656                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_DITHER, regp->dither);
1657                 for (i = 0; i < 3; i++) {
1658                         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_850 + i * 4, regp->dither_regs[i]);
1659                         NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_FP_85C + i * 4, regp->dither_regs[i + 3]);
1660                 }
1661         }
1662         if (pNv->Architecture >= NV_ARCH_10)
1663                 NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
1664
1665         /* The regs below are 0 for non-flatpanels, so you can load and save them */
1666
1667         for (i = 0; i < 7; i++) {
1668                 uint32_t ramdac_reg = NV_RAMDAC_FP_HDISP_END + (i * 4);
1669                 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_horiz_regs[i]);
1670         }
1671
1672         for (i = 0; i < 7; i++) {
1673                 uint32_t ramdac_reg = NV_RAMDAC_FP_VDISP_END + (i * 4);
1674                 NVCrtcWriteRAMDAC(crtc, ramdac_reg, regp->fp_vert_regs[i]);
1675         }
1676 }
1677
1678 void NVCrtcSetBase(xf86CrtcPtr crtc, int x, int y)
1679 {
1680         ScrnInfoPtr pScrn = crtc->scrn;
1681         NVPtr pNv = NVPTR(pScrn);
1682         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1683         uint32_t start = (y * pScrn->displayWidth + x) * pScrn->bitsPerPixel / 8;
1684
1685         if (crtc->rotatedData != NULL) /* we do not exist on the real framebuffer */
1686 #if NOUVEAU_EXA_PIXMAPS
1687                 start = nv_crtc->shadow->offset;
1688 #else
1689                 start = pNv->FB->offset + nv_crtc->shadow->offset; /* We do exist relative to the framebuffer */
1690 #endif
1691         else
1692                 start += pNv->FB->offset;
1693
1694         /* 30 bits addresses in 32 bits according to haiku */
1695         NVCrtcWriteCRTC(crtc, NV_CRTC_START, start & 0xfffffffc);
1696
1697         crtc->x = x;
1698         crtc->y = y;
1699 }
1700
1701 static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1702 {
1703         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1704         NVPtr pNv = NVPTR(crtc->scrn);
1705         uint32_t mmiobase = nv_crtc->head ? NV_PDIO1_OFFSET : NV_PDIO0_OFFSET;
1706         int i;
1707
1708         VGA_WR08(pNv->REGS, VGA_DAC_MASK + mmiobase, 0xff);
1709         VGA_WR08(pNv->REGS, VGA_DAC_READ_ADDR + mmiobase, 0x0);
1710
1711         for (i = 0; i < 768; i++) {
1712                 state->crtc_reg[nv_crtc->head].DAC[i] = NV_RD08(pNv->REGS, VGA_DAC_DATA + mmiobase);
1713                 DDXMMIOH("nv_crtc_save_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_DATA + mmiobase, state->crtc_reg[nv_crtc->head].DAC[i]);
1714         }
1715
1716         NVSetEnablePalette(pNv, nv_crtc->head, false);
1717 }
1718 static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
1719 {
1720         struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
1721         NVPtr pNv = NVPTR(crtc->scrn);
1722         uint32_t mmiobase = nv_crtc->head ? NV_PDIO1_OFFSET : NV_PDIO0_OFFSET;
1723         int i;
1724
1725         VGA_WR08(pNv->REGS, VGA_DAC_MASK + mmiobase, 0xff);
1726         VGA_WR08(pNv->REGS, VGA_DAC_WRITE_ADDR + mmiobase, 0x0);
1727
1728         for (i = 0; i < 768; i++) {
1729                 DDXMMIOH("nv_crtc_load_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_DATA + mmiobase, state->crtc_reg[nv_crtc->head].DAC[i]);
1730                 NV_WR08(pNv->REGS, VGA_DAC_DATA + mmiobase, state->crtc_reg[nv_crtc->head].DAC[i]);
1731         }
1732
1733         NVSetEnablePalette(pNv, nv_crtc->head, false);
1734 }